diff --git a/src/arm/am5729-beagleboneai-efi.dts b/src/arm/am5729-beagleboneai-efi.dts
new file mode 100644
index 0000000000000000000000000000000000000000..b8e3f7c2a9898f6f67a7eb63d599d802c6f56fb2
--- /dev/null
+++ b/src/arm/am5729-beagleboneai-efi.dts
@@ -0,0 +1,1151 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2014-2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "dra74x.dtsi"
+#include "dra74x-mmc-iodelay.dtsi"
+#include "dra74-ipu-dsp-common.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/dra.h>
+
+/ {
+ model = "BeagleBoard.org BeagleBone AI";
+ compatible = "beagleboard.org,am5729-beagleboneai", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
+
+ aliases {
+ rtc0 = &tps659038_rtc;
+ rtc1 = &rtc;
+ display0 = &hdmi_conn;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+ base_dtb = "am5729-beagleboneai.dts";
+ base_dtb_timestamp = __TIMESTAMP__;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cmem_block_mem_1_ocmc3: cmem_block_mem@40500000 {
+ reg = <0x0 0x40500000 0x0 0x100000>;
+ no-map;
+ status = "okay";
+ };
+
+ ipu2_memory_region: ipu2-memory@95800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x95800000 0x0 0x3800000>;
+ reusable;
+ status = "okay";
+ };
+
+ dsp1_memory_region: dsp1-memory@99000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x99000000 0x0 0x4000000>;
+ reusable;
+ status = "okay";
+ };
+
+ ipu1_memory_region: ipu1-memory@9d000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x9d000000 0x0 0x2000000>;
+ reusable;
+ status = "okay";
+ };
+
+ dsp2_memory_region: dsp2-memory@9f000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x9f000000 0x0 0x800000>;
+ reusable;
+ status = "okay";
+ };
+
+ cmem_block_mem_0: cmem_block_mem@a0000000 {
+ reg = <0x0 0xa0000000 0x0 0x18000000>;
+ no-map;
+ status = "okay";
+ };
+ };
+
+ cmem {
+ compatible = "ti,cmem";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pool-size-cells = <2>;
+ status = "okay";
+
+ cmem_block_0: cmem_block@0 {
+ reg = <0>;
+ memory-region = <&cmem_block_mem_0>;
+ cmem-buf-pools = <1 0x0 0x18000000>;
+ };
+
+ cmem_block_1: cmem_block@1 {
+ reg = <1>;
+ memory-region = <&cmem_block_mem_1_ocmc3>;
+ };
+ };
+
+ vdd_adc: gpioregulator-vdd_adc {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd_adc";
+ vin-supply = <&vdd_5v>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0
+ 3300000 1>;
+ };
+
+ vdd_5v: fixedregulator-vdd_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vtt_fixed: fixedregulator-vtt {
+ /* TPS51200 */
+ compatible = "regulator-fixed";
+ regulator-name = "vtt_fixed";
+ vin-supply = <&vdd_ddr>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_default>;
+
+ led0 {
+ label = "beaglebone:green:usr0";
+ gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led1 {
+ label = "beaglebone:green:usr1";
+ gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ led2 {
+ label = "beaglebone:green:usr2";
+ gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "cpu";
+ default-state = "off";
+ };
+
+ led3 {
+ label = "beaglebone:green:usr3";
+ gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc1";
+ default-state = "off";
+ };
+
+ led4 {
+ label = "beaglebone:green:usr4";
+ gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "netdev";
+ default-state = "off";
+ };
+ };
+
+ hdmi_conn: connector@0 {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_encoder_out>;
+ };
+ };
+ };
+
+ hdmi_enc: encoder@0 {
+ compatible = "ti,tpd12s016", "ti,tpd12s015";
+ gpios = <0>,
+ <0>,
+ <&gpio7 12 GPIO_ACTIVE_HIGH>;
+
+ ports {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ hdmi_encoder_in: endpoint@0 {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <0x1>;
+
+ hdmi_encoder_out: endpoint@0 {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+
+ emmc_pwrseq: emmc_pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_pwrseq_pins_default>;
+ };
+
+ brcmf_pwrseq: brcmf_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&brcmf_pwrseq_pins_default>;
+ reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>, /* BT-REG-ON */
+ <&gpio3 18 GPIO_ACTIVE_LOW>; /* WL-REG-ON */
+ };
+
+ unused_pins: unused_pins {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&unused_pins_default>;
+ };
+
+ cape_pins: cape_pins {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cape_pins_default>;
+ };
+
+ extcon_usb1: extcon_usb1 {
+ compatible = "linux,extcon-usb-gpio";
+ ti,enable-id-detection;
+ id-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&extcon_usb1_pins_default>;
+ };
+};
+
+&ocp {
+ pruss1_shmem: pruss_shmem@4b200000 {
+ status = "okay";
+ compatible = "ti,pruss-shmem";
+ reg = <0x4b200000 0x020000>;
+ };
+
+ pruss2_shmem: pruss_shmem@4b280000 {
+ status = "okay";
+ compatible = "ti,pruss-shmem";
+ reg = <0x4b280000 0x020000>;
+ };
+};
+
+&dra7_pmx_core {
+ extcon_usb1_pins_default: extcon_usb1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3518, PIN_INPUT | MUX_MODE14) /* AG2: vin1a_d9.gpio3_13 - USR0 */
+ >;
+ };
+
+ led_pins_default: led_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3528, PIN_OUTPUT | MUX_MODE14) /* AF6: vin1a_d13.gpio3_17 - USR0 */
+ DRA7XX_CORE_IOPAD(0x36c0, PIN_OUTPUT | MUX_MODE14) /* J11: mcasp1_axr3.gpio5_5 - USR1 */
+ DRA7XX_CORE_IOPAD(0x3520, PIN_OUTPUT | MUX_MODE14) /* AG5: vin1a_d12.gpio3_15 - USR2 */
+ DRA7XX_CORE_IOPAD(0x351c, PIN_OUTPUT | MUX_MODE14) /* AG3: vin1a_d10.gpio3_14 - USR3 */
+ DRA7XX_CORE_IOPAD(0x3500, PIN_OUTPUT | MUX_MODE14) /* AH6: vin1a_d3.gpio3_7 - USR4 */
+ >;
+ };
+
+ microsd_extra_pins_default: microsd_extra_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT_PULLUP | MUX_MODE14) /* W7: mmc1_sdcd.gpio6_27 - MMC1_SDCD */
+ >;
+ };
+
+ ethphy_extra_pins_default: ethphy_extra_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT_PULLUP | MUX_MODE14) /* N1: gpmc_advn_ale.gpio2_23 - RGMII_RST */
+ DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT | MUX_MODE14) /* Y1: uart3_txd.gpio5_19 - MII0_INT */
+ >;
+ };
+
+ emmc_pwrseq_pins_default: emmc_pwrseq_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x36c8, PIN_OUTPUT_PULLUP | MUX_MODE14) /* F13: mcasp1_axr5.gpio5_7 - eMMC_RSTn */
+ >;
+ };
+
+ brcmf_pwrseq_pins_default: brcmf_pwrseq_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x352c, PIN_OUTPUT_PULLUP | MUX_MODE14) /* AF3: vin1a_d14.gpio3_18 - WL_REG_ON */
+ DRA7XX_CORE_IOPAD(0x353c, PIN_OUTPUT_PULLUP | MUX_MODE14) /* AE5: vin1a_d18.gpio3_22 - BT_REG_ON */
+ >;
+ };
+
+ wifibt_extra_pins_default: wifibt_extra_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3540, PIN_INPUT | MUX_MODE14) /* AE1: vin1a_d19.gpio3_23 - WL_HOST_WAKE */
+ DRA7XX_CORE_IOPAD(0x3450, PIN_INPUT | MUX_MODE8) /* P6: vin1a_d20.uart6_rxd - UART6_RXD */
+ DRA7XX_CORE_IOPAD(0x3454, PIN_INPUT | MUX_MODE8) /* R9: vin1a_d21.uart6_txd - UART6_TXD */
+ DRA7XX_CORE_IOPAD(0x3458, PIN_INPUT | MUX_MODE8) /* R5: vin1a_d22.uart6_ctsn - UART6_CTSN */
+ DRA7XX_CORE_IOPAD(0x345c, PIN_INPUT | MUX_MODE8) /* P5: vin1a_d23.uart6_rtsn - UART6_RTSN */
+ DRA7XX_CORE_IOPAD(0x3534, PIN_INPUT_PULLDOWN | MUX_MODE14) /* AF1: vin1a_d16.gpio3_20 - BT_HOST_WAKE */
+ DRA7XX_CORE_IOPAD(0x3538, PIN_OUTPUT_PULLDOWN | MUX_MODE14) /* AE3: vin1a_d6.gpio3_21 - BT_WAKE */
+ >;
+ };
+
+ adc_pins_default: adc_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3550, PIN_OUTPUT | MUX_MODE14) /* AD3: vin1a_d23.gpio3_27 - VDD_ADC_SEL */
+ DRA7XX_CORE_IOPAD(0x34DC, PIN_INPUT_PULLUP | MUX_MODE14) /* AG8: vin1a_clk0.gpio2_30 - INT_ADC */
+ >;
+ };
+
+ pmic_pins_default: pmic_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3690, PIN_INPUT_PULLUP | MUX_MODE14) /* F21: gpio6_16.gpio6_16 - PMIC_INT */
+ >;
+ };
+
+ hdmi_pins_default: hdmi_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* C25: i2c2_sda.hdmi1_ddc_scl - HDMI_DDC_SCL */
+ DRA7XX_CORE_IOPAD(0x380C, PIN_INPUT | MUX_MODE1) /* F17: i2c2_scl.hdmi1_ddc_sda - HDMI_DDC_SDA */
+ DRA7XX_CORE_IOPAD(0x37BC, PIN_INPUT | MUX_MODE6) /* B20: spi1_cs3.hdmi1_cec - HDMI_DDC_CEC */
+#if 0
+ DRA7XX_CORE_IOPAD(0x37B8, PIN_INPUT | MUX_MODE6) /* B21: spi1_cs2.hdmi1_hpd - HDMI_DDC_HPD */
+#else
+ DRA7XX_CORE_IOPAD(0x37B8, PIN_INPUT | MUX_MODE14) /* B21: spi1_cs2.gpio7_12 - HDMI_DDC_HPD */
+#endif
+ >;
+ };
+
+ unused_pins_default: unused_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3400, MUX_MODE15) /* M6: sysboot0 */
+ DRA7XX_CORE_IOPAD(0x3404, MUX_MODE15) /* M2: sysboot1 */
+ DRA7XX_CORE_IOPAD(0x3408, MUX_MODE15) /* L5: sysboot2 */
+ DRA7XX_CORE_IOPAD(0x340C, MUX_MODE15) /* M1: sysboot3 */
+ DRA7XX_CORE_IOPAD(0x3410, MUX_MODE15) /* L6: sysboot4 */
+ DRA7XX_CORE_IOPAD(0x3414, MUX_MODE15) /* L4: sysboot5 */
+ DRA7XX_CORE_IOPAD(0x3418, MUX_MODE15) /* L3: sysboot6 */
+ DRA7XX_CORE_IOPAD(0x341C, MUX_MODE15) /* L2: sysboot7 */
+ DRA7XX_CORE_IOPAD(0x3420, MUX_MODE15) /* L1: sysboot8 */
+ DRA7XX_CORE_IOPAD(0x3424, MUX_MODE15) /* K2: sysboot9 */
+ DRA7XX_CORE_IOPAD(0x3428, MUX_MODE15) /* J1: sysboot10 */
+ DRA7XX_CORE_IOPAD(0x342C, MUX_MODE15) /* J2: sysboot11 */
+ DRA7XX_CORE_IOPAD(0x3430, MUX_MODE15) /* H1: sysboot12 */
+ DRA7XX_CORE_IOPAD(0x3434, MUX_MODE15) /* J3: sysboot13 */
+ DRA7XX_CORE_IOPAD(0x3438, MUX_MODE15) /* H2: sysboot14 */
+ DRA7XX_CORE_IOPAD(0x343C, MUX_MODE15) /* H3: sysboot15 */
+
+ DRA7XX_CORE_IOPAD(0x3448, MUX_MODE15) /* T6: N/C */
+ DRA7XX_CORE_IOPAD(0x344C, MUX_MODE15) /* T7: N/C */
+
+ DRA7XX_CORE_IOPAD(0x3460, MUX_MODE15) /* N7: N/C */
+ DRA7XX_CORE_IOPAD(0x3464, MUX_MODE15) /* R4: N/C */
+ DRA7XX_CORE_IOPAD(0x3468, MUX_MODE15) /* N9: N/C */
+ DRA7XX_CORE_IOPAD(0x346C, MUX_MODE15) /* P9: N/C */
+ DRA7XX_CORE_IOPAD(0x3470, MUX_MODE15) /* P4: N/C */
+ DRA7XX_CORE_IOPAD(0x3474, MUX_MODE15) /* R3: N/C */
+ DRA7XX_CORE_IOPAD(0x3478, MUX_MODE15) /* T2: N/C */
+ DRA7XX_CORE_IOPAD(0x347C, MUX_MODE15) /* U2: N/C */
+ DRA7XX_CORE_IOPAD(0x3480, MUX_MODE15) /* U1: N/C */
+ DRA7XX_CORE_IOPAD(0x3484, MUX_MODE15) /* P3: N/C */
+ DRA7XX_CORE_IOPAD(0x3488, MUX_MODE15) /* R2: N/C */
+
+ DRA7XX_CORE_IOPAD(0x34B4, MUX_MODE15) /* T1: N/C */
+ DRA7XX_CORE_IOPAD(0x34B8, MUX_MODE15) /* P2: N/C */
+ DRA7XX_CORE_IOPAD(0x34BC, MUX_MODE15) /* P1: N/C */
+ DRA7XX_CORE_IOPAD(0x34C0, MUX_MODE15) /* P7: N/C */
+ DRA7XX_CORE_IOPAD(0x34C4, MUX_MODE15) /* N1: N/C */
+ DRA7XX_CORE_IOPAD(0x34C8, MUX_MODE15) /* M5: N/C */
+ DRA7XX_CORE_IOPAD(0x34CC, MUX_MODE15) /* M3: N/C */
+ DRA7XX_CORE_IOPAD(0x34D0, MUX_MODE15) /* N6: N/C */
+ DRA7XX_CORE_IOPAD(0x34D4, MUX_MODE15) /* M4: N/C */
+ DRA7XX_CORE_IOPAD(0x34D8, MUX_MODE15) /* N2: N/C */
+
+ DRA7XX_CORE_IOPAD(0x34E0, MUX_MODE15) /* AH7: N/C */
+
+ DRA7XX_CORE_IOPAD(0x34EC, MUX_MODE15) /* AE9: N/C */
+
+ DRA7XX_CORE_IOPAD(0x34F4, MUX_MODE15) /* AE8: N/C */
+ DRA7XX_CORE_IOPAD(0x34F8, MUX_MODE15) /* AD8: N/C */
+ DRA7XX_CORE_IOPAD(0x34FC, MUX_MODE15) /* AG7: N/C */
+
+ DRA7XX_CORE_IOPAD(0x3504, MUX_MODE15) /* AH3: N/C */
+ DRA7XX_CORE_IOPAD(0x3508, MUX_MODE15) /* AH5: N/C */
+
+ DRA7XX_CORE_IOPAD(0x3524, MUX_MODE15) /* AF2: N/C */
+
+ DRA7XX_CORE_IOPAD(0x3530, MUX_MODE15) /* AF4: N/C */
+
+ DRA7XX_CORE_IOPAD(0x354C, MUX_MODE15) /* AD2: N/C */
+
+ DRA7XX_CORE_IOPAD(0x3554, MUX_MODE15) /* E1: N/C */
+ DRA7XX_CORE_IOPAD(0x3558, MUX_MODE15) /* G2: N/C */
+ DRA7XX_CORE_IOPAD(0x355C, MUX_MODE15) /* H7: N/C */
+ DRA7XX_CORE_IOPAD(0x3560, MUX_MODE15) /* G1: N/C */
+
+ DRA7XX_CORE_IOPAD(0x356C, MUX_MODE15) /* F3: N/C */
+
+ DRA7XX_CORE_IOPAD(0x3574, MUX_MODE15) /* E2: N/C */
+
+ DRA7XX_CORE_IOPAD(0x3584, MUX_MODE15) /* E4: N/C */
+
+ DRA7XX_CORE_IOPAD(0x3594, MUX_MODE15) /* F6: N/C */
+
+ DRA7XX_CORE_IOPAD(0x35A4, MUX_MODE15) /* C4: N/C */
+ DRA7XX_CORE_IOPAD(0x35A8, MUX_MODE15) /* B2: N/C */
+
+ DRA7XX_CORE_IOPAD(0x35C0, MUX_MODE15) /* B5: N/C */
+ DRA7XX_CORE_IOPAD(0x35C4, MUX_MODE15) /* A4: N/C */
+
+ DRA7XX_CORE_IOPAD(0x35D0, MUX_MODE15) /* B11: N/C */
+
+ DRA7XX_CORE_IOPAD(0x3644, MUX_MODE15) /* U3: N/C */
+
+ DRA7XX_CORE_IOPAD(0x3680, MUX_MODE15) /* AB10: N/C */
+
+ DRA7XX_CORE_IOPAD(0x36BC, MUX_MODE15) /* G13: N/C */
+
+ DRA7XX_CORE_IOPAD(0x36C4, MUX_MODE15) /* E12: N/C */
+
+ DRA7XX_CORE_IOPAD(0x36CC, MUX_MODE15) /* C12: N/C */
+ DRA7XX_CORE_IOPAD(0x36D0, MUX_MODE15) /* D12: N/C */
+
+ DRA7XX_CORE_IOPAD(0x36FC, MUX_MODE15) /* E15: N/C */
+ DRA7XX_CORE_IOPAD(0x3700, MUX_MODE15) /* A20: N/C */
+
+ DRA7XX_CORE_IOPAD(0x370C, MUX_MODE15) /* C15: N/C */
+ DRA7XX_CORE_IOPAD(0x3710, MUX_MODE15) /* A16: N/C */
+ DRA7XX_CORE_IOPAD(0x3714, MUX_MODE15) /* D15: N/C */
+ DRA7XX_CORE_IOPAD(0x3718, MUX_MODE15) /* B16: N/C */
+ DRA7XX_CORE_IOPAD(0x371C, MUX_MODE15) /* B17: N/C */
+ DRA7XX_CORE_IOPAD(0x3720, MUX_MODE15) /* A17: N/C */
+ DRA7XX_CORE_IOPAD(0x3724, MUX_MODE15) /* B18: N/C */
+ DRA7XX_CORE_IOPAD(0x3728, MUX_MODE15) /* F15: N/C */
+
+ DRA7XX_CORE_IOPAD(0x3744, MUX_MODE15) /* AA3: N/C */
+ DRA7XX_CORE_IOPAD(0x3748, MUX_MODE15) /* AB9: N/C */
+ DRA7XX_CORE_IOPAD(0x374C, MUX_MODE15) /* AB3: N/C */
+ DRA7XX_CORE_IOPAD(0x3750, MUX_MODE15) /* AA4: N/C */
+
+ DRA7XX_CORE_IOPAD(0x3770, MUX_MODE15) /* Y9: N/C */
+ DRA7XX_CORE_IOPAD(0x3774, MUX_MODE15) /* AC5: N/C */
+ DRA7XX_CORE_IOPAD(0x3778, MUX_MODE15) /* AB4: N/C */
+
+ DRA7XX_CORE_IOPAD(0x37A4, MUX_MODE15) /* A25: N/C */
+ DRA7XX_CORE_IOPAD(0x37A8, MUX_MODE15) /* F16: N/C */
+ DRA7XX_CORE_IOPAD(0x37AC, MUX_MODE15) /* B25: N/C */
+ DRA7XX_CORE_IOPAD(0x37B0, MUX_MODE15) /* A24: N/C */
+
+ DRA7XX_CORE_IOPAD(0x37D0, MUX_MODE15) /* G20: N/C */
+ DRA7XX_CORE_IOPAD(0x37D4, MUX_MODE15) /* G19: N/C */
+
+ DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15) /* AD17: N/C */
+ DRA7XX_CORE_IOPAD(0x381C, MUX_MODE15) /* AC17: N/C */
+ DRA7XX_CORE_IOPAD(0x3820, MUX_MODE15) /* AB16: N/C */
+ DRA7XX_CORE_IOPAD(0x3824, MUX_MODE15) /* AC16: N/C */
+ >;
+ };
+
+ cape_pins_default: cape_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x379C, MUX_MODE14) /* AB8: P8.3: mmc3_dat6.off */
+ DRA7XX_CORE_IOPAD(0x37A0, MUX_MODE14) /* AB5: P8.4: mmc3_dat7.off */
+ DRA7XX_CORE_IOPAD(0x378C, MUX_MODE14) /* AC9: P8.5: mmc3_dat2.off */
+ DRA7XX_CORE_IOPAD(0x3790, MUX_MODE14) /* AC3: P8.6: mmc3_dat3.off */
+ DRA7XX_CORE_IOPAD(0x36EC, MUX_MODE14) /* G14: P8.7: mcasp1_axr14.off */
+ DRA7XX_CORE_IOPAD(0x36F0, MUX_MODE14) /* F14: P8.8: mcasp1_axr15.off */
+ DRA7XX_CORE_IOPAD(0x3698, MUX_MODE14) /* E17: P8.9: xref_clk1.off */
+ DRA7XX_CORE_IOPAD(0x36E8, MUX_MODE14) /* A13: P8.10: mcasp1_axr13.off */
+ DRA7XX_CORE_IOPAD(0x3510, MUX_MODE14) /* AH4: P8.11: vin1a_d7.off */
+ DRA7XX_CORE_IOPAD(0x350C, MUX_MODE14) /* AG6: P8.12: vin1a_d6.off */
+ DRA7XX_CORE_IOPAD(0x3590, PIN_INPUT | MUX_MODE12) /* D3: P8.13: vin2a_d10.off */
+ DRA7XX_CORE_IOPAD(0x3598, MUX_MODE14) /* D5: P8.14: vin2a_d12.off */
+ DRA7XX_CORE_IOPAD(0x3570, MUX_MODE14) /* D1: P8.15a: vin2a_d2.off */
+ DRA7XX_CORE_IOPAD(0x35B4, MUX_MODE13) /* A3: P8.15b: vin2a_d19.off */
+ DRA7XX_CORE_IOPAD(0x35BC, MUX_MODE13) /* B4: P8.16: vin2a_d21.off */
+ DRA7XX_CORE_IOPAD(0x3624, MUX_MODE14) /* A7: P8.17: vout1_d18.off */
+ DRA7XX_CORE_IOPAD(0x3588, PIN_INPUT | MUX_MODE12) /* F5: P8.18: vin2a_d8.off */
+ DRA7XX_CORE_IOPAD(0x358C, PIN_INPUT | MUX_MODE12) /* E6: P8.19: vin2a_d9.off */
+ DRA7XX_CORE_IOPAD(0x3780, MUX_MODE14) /* AC4: P8.20: mmc3_cmd.off */
+ DRA7XX_CORE_IOPAD(0x377C, MUX_MODE14) /* AD4: P8.21: mmc3_clk.off */
+ DRA7XX_CORE_IOPAD(0x3798, MUX_MODE14) /* AD6: P8.22: mmc3_dat5.off */
+ DRA7XX_CORE_IOPAD(0x3794, MUX_MODE14) /* AC8: P8.23: mmc3_dat4.off */
+ DRA7XX_CORE_IOPAD(0x3788, MUX_MODE14) /* AC6: P8.24: mmc3_dat1.off */
+ DRA7XX_CORE_IOPAD(0x3784, MUX_MODE14) /* AC7: P8.25: mmc3_dat0.off */
+ DRA7XX_CORE_IOPAD(0x35B8, MUX_MODE13) /* B3: P8.26: vin2a_d20.off */
+ DRA7XX_CORE_IOPAD(0x35D8, MUX_MODE14) /* E11: P8.27a: vout1_vsync.off */
+ DRA7XX_CORE_IOPAD(0x3628, MUX_MODE14) /* A8: P8.27b: vout1_d19.off */
+ DRA7XX_CORE_IOPAD(0x35C8, MUX_MODE14) /* D11: P8.28a: vout1_clk.off */
+ DRA7XX_CORE_IOPAD(0x362C, MUX_MODE14) /* C9: P8.28b: vout1_d20.off */
+ DRA7XX_CORE_IOPAD(0x35D4, MUX_MODE14) /* C11: P8.29a: vout1_hsync.off */
+ DRA7XX_CORE_IOPAD(0x3630, MUX_MODE14) /* A9: P8.29b: vout1_d21.off */
+ DRA7XX_CORE_IOPAD(0x35CC, MUX_MODE14) /* B10: P8.30a: vout1_de.off */
+ DRA7XX_CORE_IOPAD(0x3634, MUX_MODE14) /* B9: P8.30b: vout1_d22.off */
+ DRA7XX_CORE_IOPAD(0x3614, MUX_MODE14) /* C8: P8.31a: vout1_d14.off */
+ DRA7XX_CORE_IOPAD(0x373C, MUX_MODE14) /* G16: P8.31b: mcasp4_axr0.off */
+ DRA7XX_CORE_IOPAD(0x3618, MUX_MODE14) /* C7: P8.32a: vout1_d15.off */
+ DRA7XX_CORE_IOPAD(0x3740, MUX_MODE14) /* D17: P8.32b: mcasp4_axr1.off */
+ DRA7XX_CORE_IOPAD(0x3610, MUX_MODE14) /* C6: P8.33a: vout1_d13.off */
+ DRA7XX_CORE_IOPAD(0x34E8, MUX_MODE14) /* AF9: P8.33b: vin1a_fld0.off */
+ DRA7XX_CORE_IOPAD(0x3608, MUX_MODE14) /* D8: P8.34a: vout1_d11.off */
+ DRA7XX_CORE_IOPAD(0x3564, MUX_MODE14) /* G6: P8.34b: vin2a_vsync0.off */
+ DRA7XX_CORE_IOPAD(0x360C, MUX_MODE14) /* A5: P8.35a: vout1_d12.off */
+ DRA7XX_CORE_IOPAD(0x34E4, MUX_MODE14) /* AD9: P8.35b: vin1a_de0.off */
+ DRA7XX_CORE_IOPAD(0x3604, MUX_MODE14) /* D7: P8.36a: vout1_d10.off */
+ DRA7XX_CORE_IOPAD(0x3568, MUX_MODE14) /* F2: P8.36b: vin2a_d0.off */
+ DRA7XX_CORE_IOPAD(0x35FC, MUX_MODE14) /* E8: P8.37a: vout1_d8.off */
+ DRA7XX_CORE_IOPAD(0x3738, MUX_MODE14) /* A21: P8.37b: mcasp4_fsx.off */
+ DRA7XX_CORE_IOPAD(0x3600, MUX_MODE14) /* D9: P8.38a: vout1_d9.off */
+ DRA7XX_CORE_IOPAD(0x3734, MUX_MODE14) /* C18: P8.38b: mcasp4_aclkx.off */
+ DRA7XX_CORE_IOPAD(0x35F4, MUX_MODE14) /* F8: P8.39: vout1_d6.off */
+ DRA7XX_CORE_IOPAD(0x35F8, MUX_MODE14) /* E7: P8.40: vout1_d7.off */
+ DRA7XX_CORE_IOPAD(0x35EC, MUX_MODE14) /* E9: P8.41: vout1_d4.off */
+ DRA7XX_CORE_IOPAD(0x35F0, MUX_MODE14) /* F9: P8.42: vout1_d5.off */
+ DRA7XX_CORE_IOPAD(0x35E4, MUX_MODE14) /* F10: P8.43: vout1_d2.off */
+ DRA7XX_CORE_IOPAD(0x35E8, MUX_MODE14) /* G11: P8.44: vout1_d3.off */
+ DRA7XX_CORE_IOPAD(0x35DC, MUX_MODE14) /* F11: P8.45a: vout1_d0.off */
+ DRA7XX_CORE_IOPAD(0x361C, MUX_MODE14) /* B7: P8.45b: vout1_d16.off */
+ DRA7XX_CORE_IOPAD(0x35E0, MUX_MODE14) /* G10: P8.46a: vout1_d1.off */
+ DRA7XX_CORE_IOPAD(0x3638, MUX_MODE14) /* A10: P8.46b: vout1_d23.off */
+ DRA7XX_CORE_IOPAD(0x372C, MUX_MODE14) /* B19: P9.11a: mcasp3_axr0.off */
+ DRA7XX_CORE_IOPAD(0x3620, MUX_MODE14) /* B8: P9.11b: vout1_d17.off */
+ DRA7XX_CORE_IOPAD(0x36AC, MUX_MODE14) /* B14: P9.12: mcasp1_aclkr.off */
+ DRA7XX_CORE_IOPAD(0x3730, MUX_MODE14) /* C17: P9.13: mcasp3_axr1.off */
+ DRA7XX_CORE_IOPAD(0x35AC, MUX_MODE10) /* D6: P9.14: vin2a_d17.off */
+ DRA7XX_CORE_IOPAD(0x3514, MUX_MODE14) /* AG4: P9.15: vin1a_d8.off */
+ DRA7XX_CORE_IOPAD(0x35B0, MUX_MODE13) /* C5: P9.16: vin2a_d18.off */
+ DRA7XX_CORE_IOPAD(0x37CC, MUX_MODE14) /* B24: P9.17a: spi2_cs0.off */
+ DRA7XX_CORE_IOPAD(0x36B8, MUX_MODE14) /* F12: P9.17b: mcasp1_axr1.off */
+ DRA7XX_CORE_IOPAD(0x37C8, MUX_MODE14) /* G17: P9.18a: spi2_d0.off */
+ DRA7XX_CORE_IOPAD(0x36B4, MUX_MODE14) /* G12: P9.18b: mcasp1_axr0.off */
+ DRA7XX_CORE_IOPAD(0x3440, PIN_INPUT_PULLUP | MUX_MODE7) /* R6: P9.19a: gpmc_a0.i2c4_scl */
+ DRA7XX_CORE_IOPAD(0x357C, PIN_INPUT_PULLUP | MUX_MODE12 ) /* F4: P9.19b: vin2a_d5.pr1_pru1_gpi2 */
+ DRA7XX_CORE_IOPAD(0x3444, PIN_INPUT_PULLUP | MUX_MODE7) /* T9: P9.20a: gpmc_a1.i2c4_sda */
+ DRA7XX_CORE_IOPAD(0x3578, PIN_INPUT_PULLUP | MUX_MODE12) /* D2: P9.20b: vin2a_d4.pr1_pru1_gpi1 */
+ DRA7XX_CORE_IOPAD(0x34F0, MUX_MODE14) /* AF8: P9.21a: vin1a_vsync0.off */
+ DRA7XX_CORE_IOPAD(0x37C4, MUX_MODE14) /* B22: P9.21b: spi2_d1.off */
+ DRA7XX_CORE_IOPAD(0x369C, MUX_MODE14) /* B26: P9.22a: xref_clk2.off */
+ DRA7XX_CORE_IOPAD(0x37C0, MUX_MODE14) /* A26: P9.22b: spi2_sclk.off */
+ DRA7XX_CORE_IOPAD(0x37B4, MUX_MODE14) /* A22: P9.23: spi1_cs1.off */
+ DRA7XX_CORE_IOPAD(0x368C, MUX_MODE14) /* F20: P9.24: gpio6_15.off */
+ DRA7XX_CORE_IOPAD(0x3694, MUX_MODE14) /* D18: P9.25: xref_clk0.off */
+ DRA7XX_CORE_IOPAD(0x3688, MUX_MODE14) /* E21: P9.26a: gpio6_14.off */
+ DRA7XX_CORE_IOPAD(0x3544, MUX_MODE14) /* AE2: P9.26b: vin1a_d20.off */
+ DRA7XX_CORE_IOPAD(0x35A0, MUX_MODE14) /* C3: P9.27a: vin2a_d14.off */
+ DRA7XX_CORE_IOPAD(0x36B0, MUX_MODE14) /* J14: P9.27b: mcasp1_fsr.off */
+ DRA7XX_CORE_IOPAD(0x36E0, MUX_MODE14) /* A12: P9.28: mcasp1_axr11.off */
+ DRA7XX_CORE_IOPAD(0x36D8, MUX_MODE14) /* A11: P9.29a: mcasp1_axr9.off */
+ DRA7XX_CORE_IOPAD(0x36A8, MUX_MODE14) /* D14: P9.29b: mcasp1_fsx.off */
+ DRA7XX_CORE_IOPAD(0x36DC, MUX_MODE14) /* B13: P9.30: mcasp1_axr10.off */
+ DRA7XX_CORE_IOPAD(0x36D4, MUX_MODE14) /* B12: P9.31a: mcasp1_axr8.off */
+ DRA7XX_CORE_IOPAD(0x36A4, MUX_MODE14) /* C14: P9.31b: mcasp1_aclkx.off */
+ DRA7XX_CORE_IOPAD(0x36A0, MUX_MODE14) /* C23: P9.41a: xref_clk3.off */
+ DRA7XX_CORE_IOPAD(0x3580, MUX_MODE14) /* C1: P9.41b: vin2a_d6.off */
+ DRA7XX_CORE_IOPAD(0x36E4, MUX_MODE14) /* E14: P9.42a: mcasp1_axr12.off */
+ DRA7XX_CORE_IOPAD(0x359C, MUX_MODE14) /* C2: P9.42b: vin2a_d13.off */
+ >;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps659038: tps659038@58 {
+ compatible = "ti,tps659038";
+ reg = <0x58>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins_default>;
+
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,system-power-controller;
+ ti,palmas-override-powerhold;
+
+ tps659038_pmic {
+ compatible = "ti,tps659038-pmic";
+
+ smps12-in-supply = <&vdd_5v>;
+ smps3-in-supply = <&vdd_5v>;
+ smps45-in-supply = <&vdd_5v>;
+ smps6-in-supply = <&vdd_5v>;
+ smps7-in-supply = <&vdd_5v>;
+ mps3-in-supply = <&vdd_5v>;
+ smps8-in-supply = <&vdd_5v>;
+ smps9-in-supply = <&vdd_5v>;
+ ldo1-in-supply = <&vdd_5v>;
+ ldo2-in-supply = <&vdd_5v>;
+ ldo3-in-supply = <&vdd_5v>;
+ ldo4-in-supply = <&vdd_5v>;
+ ldo9-in-supply = <&vdd_5v>;
+ ldoln-in-supply = <&vdd_5v>;
+ ldousb-in-supply = <&vdd_5v>;
+ ldortc-in-supply = <&vdd_5v>;
+
+ regulators {
+ vdd_mpu: smps12 {
+ /* VDD_MPU */
+ regulator-name = "smps12";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_ddr: smps3 {
+ /* VDD_DDR EMIF1 EMIF2 */
+ regulator-name = "smps3";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_dspeve: smps45 {
+ /* VDD_DSPEVE on AM572 */
+ regulator-name = "smps45";
+ regulator-min-microvolt = < 850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_gpu: smps6 {
+ /* VDD_GPU */
+ regulator-name = "smps6";
+ regulator-min-microvolt = < 850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_core: smps7 {
+ /* VDD_CORE */
+ regulator-name = "smps7";
+ regulator-min-microvolt = < 850000>; /*** 1.15V */
+ regulator-max-microvolt = <1150000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_iva: smps8 {
+ /* VDD_IVAHD */ /*** 1.06V */
+ regulator-name = "smps8";
+ };
+
+ vdd_3v3: smps9 {
+ /* VDD_3V3 */
+ regulator-name = "smps9";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_sd: ldo1 {
+ /* VDDSHV8 - VSDMMC */
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd_1v8: ldo2 {
+ /* VDDSH18V */
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_1v8_phy_ldo3: ldo3 {
+ /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_1v8_phy_ldo4: ldo4 {
+ /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* LDO5-8 unused */
+
+ vdd_rtc: ldo9 {
+ /* VDD_RTC */
+ regulator-name = "ldo9";
+ regulator-min-microvolt = < 840000>;
+ regulator-max-microvolt = <1160000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_1v8_pll: ldoln {
+ /* VDDA_1V8_PLL */
+ regulator-name = "ldoln";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldousb_reg: ldousb {
+ /* VDDA_3V_USB: VDDA_USBHS33 */
+ regulator-name = "ldousb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldortc_reg: ldortc {
+ /* VDDA_RTC */
+ regulator-name = "ldortc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ regen1: regen1 {
+ /* VDD_3V3_ON */
+ regulator-name = "regen1";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ regen2: regen2 {
+ /* Needed for PMIC internal resource */
+ regulator-name = "regen2";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ tps659038_rtc: tps659038_rtc {
+ compatible = "ti,palmas-rtc";
+ interrupt-parent = <&tps659038>;
+ interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
+ };
+
+ tps659038_pwr_button: tps659038_pwr_button {
+ compatible = "ti,palmas-pwrbutton";
+ interrupt-parent = <&tps659038>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
+ ti,palmas-long-press-seconds = <12>;
+ };
+
+ tps659038_gpio: tps659038_gpio {
+ compatible = "ti,palmas-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ /* STMPE811 touch screen controller */
+ stmpe811@41 {
+ compatible = "st,stmpe811";
+ reg = <0x41>;
+ interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio2>;
+ interrupt-controller;
+ id = <0>;
+ blocks = <0x5>;
+ irq-trigger = <0x1>;
+ st,mod-12b = <1>; /* 12-bit ADC */
+ st,ref-sel = <0>; /* internal ADC reference */
+ st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */
+ st,sample-time = <4>; /* ADC converstion time: 80 clocks */
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&adc_pins_default>;
+
+ stmpe_adc {
+ compatible = "st,stmpe-adc";
+ st,norequest-mask = <0x00>; /* mask any channels to be used by touchscreen */
+ adc0: iio-device@0 {
+ #io-channel-cells = <1>;
+ iio-channels = <&adc0 4>, <&adc0 1>, <&adc0 2>, <&adc0 3>, <&adc0 4>, <&adc0 5>, <&adc0 6>;
+ iio-channel-names = "AIN0_P9_39", "AIN1_P9_40", "AIN2_P9_37", "AIN3_P9_38",
+ "AIN4_P9_33", "AIN5_P9_36", "AIN6_P9_35";
+ };
+ };
+
+ stmpe_touchscreen {
+ status = "disabled";
+ compatible = "st,stmpe-ts";
+ };
+
+ stmpe_gpio {
+ compatible = "st,stmpe-gpio";
+ };
+
+ stmpe_pwm {
+ compatible = "st,stmpe-pwm";
+ #pwm-cells = <2>;
+ };
+ };
+};
+
+&cpu0 {
+ vdd-supply = <&vdd_mpu>;
+ voltage-tolerance = <1>;
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&davinci_mdio {
+ reset-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2>;
+
+ phy0: ethernet-phy@1 {
+ reg = <4>;
+ compatible = "ethernet-phy-id004d.d072",
+ "ethernet-phy-ieee802.3-c22";
+ eee-broken-100tx;
+ eee-broken-1000t;
+ //interrupt-parent = <&gpio5>;
+ //interrupts = <19 IRQ_TYPE_EDGE_RISING>;
+ };
+};
+
+&mac {
+ slaves = <1>;
+ status = "okay";
+ //dual_emac;
+};
+
+&cpsw_emac0 {
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii";
+ //dual_emac_res_vlan = <1>;
+};
+
+&mmc1 {
+ status = "okay";
+ vmmc-supply = <&vdd_3v3>;
+ vqmmc-supply = <&vdd_sd>;
+ bus-width = <4>;
+ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
+
+ ti,needs-special-reset;
+ ti,dual-volt;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-ddr50;
+ sd-uhs-sdr104;
+ mmc-hs200-1_8v;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
+ dma-names = "tx", "rx";
+
+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+ pinctrl-0 = <&mmc1_pins_default µsd_extra_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs µsd_extra_pins_default>;
+ pinctrl-2 = <&mmc1_pins_sdr12 µsd_extra_pins_default>;
+ pinctrl-3 = <&mmc1_pins_sdr25 µsd_extra_pins_default>;
+ pinctrl-4 = <&mmc1_pins_sdr50 µsd_extra_pins_default>;
+ pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf µsd_extra_pins_default>;
+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf µsd_extra_pins_default>;
+};
+
+&mmc2 {
+ status = "okay";
+ vmmc-supply = <&vdd_1v8>;
+ vqmmc-supply = <&vdd_1v8>;
+ bus-width = <8>;
+ ti,non-removable;
+ non-removable;
+ mmc-pwrseq = <&emmc_pwrseq>;
+
+ ti,needs-special-reset;
+ dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
+ dma-names = "tx", "rx";
+
+ pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr_rev20>;
+ pinctrl-3 = <&mmc2_pins_hs200>;
+};
+
+&mmc4 {
+ /* DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3 V signaling). */
+ /* HS: High speed up to 50 MHz (3.3 V signaling). */
+ /* SDR12: SDR up to 25 MHz (1.8 V signaling). */
+ /* SDR25: SDR up to 50 MHz (1.8 V signaling). */
+ /* SDR50: SDR up to 100 MHz (1.8 V signaling). */
+ /* SDR104: SDR up to 208 MHz (1.8 V signaling) */
+ /* DDR50: DDR up to 50 MHz (1.8 V signaling). */
+ status = "okay";
+
+ pinctrl-names = "default", "hs";
+ pinctrl-0 = <&mmc4_pins_default &wifibt_extra_pins_default>;
+ pinctrl-1 = <&mmc4_pins_hs &wifibt_extra_pins_default>;
+
+ ti,needs-special-reset;
+ vmmc-supply = <&vdd_3v3>;
+ cap-power-off-card;
+ keep-power-in-suspend;
+ bus-width = <4>;
+ ti,non-removable;
+ non-removable;
+ no-1-8-v;
+ max-frequency = <24000000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mmc-pwrseq = <&brcmf_pwrseq>;
+
+ brcmf: wifi@1 {
+ status = "okay";
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+
+ /*
+ * Not Mainline: brcm,sd_head_align/brcm,sd_sgentry_align
+ * From: Cypress Linux WiFi Driver Release (FMAC) [2019-05-08]
+ * https://community.cypress.com/docs/DOC-17441
+ */
+ brcm,sd_head_align = <4>;
+ brcm,sd_sgentry_align = <512>;
+
+ interrupt-parent = <&gpio3>;
+ interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "host-wake";
+ };
+};
+
+&usb2_phy1 {
+ phy-supply = <&ldousb_reg>;
+};
+
+&usb2_phy2 {
+ phy-supply = <&ldousb_reg>;
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "otg";
+};
+
+&omap_dwc3_1 {
+ extcon = <&extcon_usb1>;
+};
+
+&usb2 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&bb2d {
+ status = "okay";
+};
+
+&dss {
+ status = "okay";
+ vdda_video-supply = <&vdd_1v8_pll>;
+};
+
+&hdmi {
+ status = "okay";
+ vdda-supply = <&vdd_1v8_phy_ldo4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pins_default>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&hdmi_encoder_in>;
+ //lanes = <1 0 3 2 5 4 7 6>;
+ };
+ };
+};
+
+&bandgap {
+ status = "okay";
+};
+
+&mailbox1 {
+ status = "okay";
+};
+
+&mailbox2 {
+ status = "okay";
+};
+
+&mailbox3 {
+ status = "okay";
+};
+
+&mailbox4 {
+ status = "okay";
+};
+
+&mailbox7 {
+ status = "okay";
+};
+
+&mailbox8 {
+ status = "okay";
+};
+
+&mailbox9 {
+ status = "okay";
+};
+
+&mailbox10 {
+ status = "okay";
+};
+
+&mailbox11 {
+ status = "okay";
+};
+
+&mailbox12 {
+ status = "okay";
+};
+
+&mailbox13 {
+ status = "okay";
+};
+
+&ipu1 {
+ status = "okay";
+ memory-region = <&ipu1_memory_region>;
+};
+
+&ipu2 {
+ status = "okay";
+ memory-region = <&ipu2_memory_region>;
+};
+
+&dsp1 {
+ status = "okay";
+ memory-region = <&dsp1_memory_region>;
+};
+
+&dsp2 {
+ status = "okay";
+ memory-region = <&dsp2_memory_region>;
+};
+
+&pruss_soc_bus1 {
+ status = "okay";
+};
+
+&pruss1 {
+ status = "okay";
+};
+
+&pruss_soc_bus2 {
+ status = "okay";
+};
+
+&pruss2 {
+ status = "okay";
+};
+
+&cpu_alert0 {
+ temperature = <55000>; /* milliCelsius */
+};
+
+&cpu_crit {
+ temperature = <85000>; /* milliCelsius */
+};
+
+&gpu_crit {
+ temperature = <85000>; /* milliCelsius */
+};
+
+&core_crit {
+ temperature = <85000>; /* milliCelsius */
+};
+
+&dspeve_crit {
+ temperature = <85000>; /* milliCelsius */
+};
+
+&iva_crit {
+ temperature = <85000>; /* milliCelsius */
+};
+
+&sata {
+ status = "disabled";
+};
+
+&sata_phy {
+ status = "disabled";
+};
+
+/* bluetooth */
+&uart6 {
+ status = "okay";
+};
+
+/* cape header stuff */
+&i2c4 {
+ status = "okay";
+ clock-frequency = <400000>;
+};
+
+/* thermal hacks */
+&cpu0_opp_table {
+ opp_slow-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <860000 850000 1100000>,
+ <860000 850000 1100000>;
+ opp-supported-hw = <0xFF 0x01>;
+ opp-suspend;
+ };
+};