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kernel-program-behaviour-models

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    Peter Chen authored and Greg Kroah-Hartman committed
    According to xHCI spec Figure 30: Interrupt Throttle Flow Diagram
    
    	If PCI Message Signaled Interrupts (MSI or MSI-X) are enabled,
           	then the assertion of the Interrupt Pending (IP) flag in Figure 30
           	generates a PCI Dword write. The IP flag is automatically cleared
           	by the completion of the PCI write.
    
    the MSI enabled HCs don't need to clear interrupt pending bit, but
    hcd->irq = 0 doesn't equal to MSI enabled HCD. At some Dual-role
    controller software designs, it sets hcd->irq as 0 to avoid HCD
    requesting interrupt, and they want to decide when to call usb_hcd_irq
    by software.
    
    Signed-off-by: default avatarPeter Chen <peter.chen@nxp.com>
    Signed-off-by: default avatarMathias Nyman <mathias.nyman@linux.intel.com>
    Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
    6a29beef
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