diff --git a/src/libpfm-3.y/Makefile b/src/libpfm-3.y/Makefile
index a0d5f02c531cad68f6d8d90fa0ca0aa5692a6aa4..032b045f3b468d96ef39d05d1d5ea63c484b7c97 100644
--- a/src/libpfm-3.y/Makefile
+++ b/src/libpfm-3.y/Makefile
@@ -27,16 +27,31 @@ TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi)
include config.mk
-DIRS=lib examples include docs libpfms
+DIRS=lib include docs
+
+EXAMPLES_DIRS = examples_v2.x
+
+ifneq ($(CONFIG_PFMLIB_OLD_PFMV2),y)
+EXAMPLES_DIRS += examples_v3.x
+endif
ifeq ($(ARCH),ia64)
-DIRS +=old_interface_ia64_examples
+DIRS +=examples_ia64_v2.0
+endif
+
+ifeq ($(SYS),Linux)
+DIRS +=libpfms
endif
+DIRS += $(EXAMPLES_DIRS)
+
all:
@echo Compiling for \'$(ARCH)\' target
@set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done
+lib:
+ $(MAKE) -C lib
+
clean:
@set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done
@@ -52,4 +67,10 @@ tarcvs: clean
a=`basename $$PWD`; cd ..; tar --exclude=CVS -zcf $$a.tar.gz $$a; echo generated ../$$a.tar.gz;
install:
@set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done
+
+install_examples:
+ @set -e ; for d in $(EXAMPLES_DIRS) ; do $(MAKE) -C $$d $@ ; done
+
+.PHONY: tar tarcvs lib
+
# DO NOT DELETE
diff --git a/src/libpfm-3.y/README b/src/libpfm-3.y/README
index 9d11fef0e4a23d041fb3aaceb36319928ba44207..630cd40bba20b7f2b38721538dc83349b5c0cc72 100644
--- a/src/libpfm-3.y/README
+++ b/src/libpfm-3.y/README
@@ -1,5 +1,5 @@
------------------------------------------------------
- libpfm-3.2:
+ libpfm-3.10:
a helper library to program the Performance Monitoring Unit (PMU)
------------------------------------------------------
Copyright (c) 2001-2007 Hewlett-Packard Development Company, L.P.
@@ -12,55 +12,92 @@ of several modern processors.
This version of libpfm supports:
- - For Intel IA-64 : Itanium (Merced), Itanium 2 (McKinley, Madison, Deerfield), Itanium 2 9000/9100 (Montecito,Montvale) and Generic
- - For AMD/Intel IA-32 (64 bit mode,X86-64): AMD Opteron (K8, fam 10h), Xeon, Intel Core 2 Duo, Intel Core 2
- - For AMD/Intel IA-32 (32 bit mode) : Pentium II, Pentium Pro, Pentium III, Pentium M/P6, Core Duo/Core Solo, Intel Pentium 4, AMD Opteron (K8,fam 10h)), Intel Core 2
- - For MIPS: 5K, 20K, 25KF, 34K, 5KC, 74K, R10000, R12000, RM7000, RM9000, SB1, VR5432, VR5500
- - For Cray: BlackWidow
- - IBM Cell processor
- - For IBM POWER: PPC970, PPC970MP, POWER4+, POWER5, POWER5+, POWER6
- - For Sun Sparc: Ultra12, Ultra3, Ultra3i, Ultra3Plus, Ultra4Plus, Niagara1, Niagara2
-
-The core library is generic and does not depend on the perfmon interface. It is possible to use
-it on other operating systems (some adjustments may still be needed).
+ - For Intel IA-64:
+ Itanium (Merced), Itanium 2 (McKinley, Madison, Deerfield),
+ Itanium 2 9000/9100 (Montecito, Montvale) and Generic
+ - For AMD X86:
+ AMD64 (K8, family 10h)
+ - For Intel X86:
+ Intel P6 (Pentium II, Pentium Pro, Pentium III, Pentium M)
+ Intel Yonah (Core Duo/Core Solo),
+ Intel Netburst (Pentium 4, Xeon)
+ Intel Core (Merom, Penryn, Dunnington) Core 2 and Quad
+ Intel Atom
+ Intel Nehalem (Nehalem, Westmere)
+ Intel architectural perfmon v1, v2, v3
+ - For MIPS:
+ 5K, 20K, 25KF, 34K, 5KC, 74K, R10000, R12000, RM7000, RM9000,
+ SB1, VR5432, VR5500, SiCortex ICA9A/ICE9B
+ - For Cray:
+ XT3, XT4, XT5, XT5h, X2
+ - For IBM:
+ IBM Cell processor
+ POWER: PPC970, PPC970MP, POWER4+, POWER5, POWER5+, POWER6, POWER7
+ - For Sun:
+ Sparc: Ultra12, Ultra3, Ultra3i, Ultra3Plus, Ultra4Plus,
+ Sparc: Niagara1, Niagara2
+
+The core library is generic and does not depend on the perfmon interface. It is
+possible to use it on other operating systems.
WHAT'S THERE
-------------
- - the library source code including support for all processors listed above
+ - the library source code including support for all processors listed
+ above
- - a set of examples showing how the library can be used with the perfmon2
- version 2.6 or higher kernel interface.
+ - a set of examples showing how the library can be used with the
+ perfmon2 and perfmon3 kernel interface.
- - a set of older examples for IA-64 only using the legacy perfmon2 interface (v2.0).
+ - a set of older examples for IA-64 only using the legacy perfmon2
+ interface (v2.0).
- - a set of library header files and the perfmon2 v2.6 kernel interface headers
+ - a set of library header files and the perfmon2 and perfmon3 kernel
+ interface headers
- - libpfms: a simple library to help setup SMP system-wide monitoring sessions. It comes
- with a simple example. This library is not part of libpfm.
+ - libpfms: a simple library to help setup SMP system-wide monitoring
+ sessions. It comes with a simple example. This library is not part
+ of libpfm.
- man pages for all the library entry points
+ - Python bindings for libpfm and the perfmon interface (experimental).
+
INSTALLATION
------------
- edit config.mk to :
- update some of the configuration variables
- make your compiler options
- - select which PMU you want to support. Multiple PMU for the same processor architecture
- can be supported by a single library
- type make
- type make install
+ - To compile and install the Python bindings, you need to go to the
+ python sub-directory and type make. Python is not systematically
+ built
+
+ - to compile the library for another ABI (e.g. 32-bit x86 on a
+ 64-bit x86) system, you can pass the ABI flag to the compiler as
+ follows (assuming you have the multilib version of gcc):
+ $ make OPTION="-m32 -O2"
+
REQUIREMENTS:
-------------
- - to run the programs in the examples subdir, you MUST be using a linux kernel version of
- 2.6.22 or later with the corresponding perfmon new code base patch installed.
- The patch can be downloaded from:
- http://perfmon2.sf.net/
+ - to run the programs in the examples subdir, you MUST be using a linux
+ kernel with perfmon3. Perfmon3 is available as a branch of the
+ perfmon kernel GIT tree on kernel.org.
+
+ - to run the programs in the examples_v2x subdir, you MUST be using a
+ linux kernel with perfmon2. Perfmon2 is available as the main branch
+ of the perfmon kernel GIT tree on kernel.org.
+
+ - On IA-64, the examples in old_interface_ia64_examples work with
+ any 2.6.x kernels.
- - On IA-64, the examples in old_interface_ia64_examples work with any 2.6.x kernels.
+ - to compile the Python bindings, you need to have SWIG and the python
+ development packages installed
DOCUMENTATION
-------------
- man pages for all entry points
- - More information can be found on library web site: http://perfmon2.sf.net
+ - More information can be found on library web site:
+ http://perfmon2.sf.net
diff --git a/src/libpfm-3.y/docs/Makefile b/src/libpfm-3.y/docs/Makefile
index 8a7d3e9f0b9274615307c10acd975ee74a455f5c..525c466184100aa524840548ec395a20fde9f58b 100644
--- a/src/libpfm-3.y/docs/Makefile
+++ b/src/libpfm-3.y/docs/Makefile
@@ -25,18 +25,16 @@ TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi)/..
include $(TOPDIR)/config.mk
include $(TOPDIR)/rules.mk
-.PHONY: all clean distclean depend
-
ifeq ($(CONFIG_PFMLIB_ARCH_IA64),y)
ARCH_MAN=libpfm_itanium.3 libpfm_itanium2.3 libpfm_montecito.3
endif
ifeq ($(CONFIG_PFMLIB_ARCH_I386),y)
-ARCH_MAN=libpfm_p6.3 libpfm_core.3 libpfm_amd64.3
+ARCH_MAN=libpfm_p6.3 libpfm_core.3 libpfm_amd64.3 libpfm_atom.3 libpfm_nehalem.3
endif
ifeq ($(CONFIG_PFMLIB_ARCH_X86_64),y)
-ARCH_MAN=libpfm_amd64.3 libpfm_core.3
+ARCH_MAN=libpfm_amd64.3 libpfm_core.3 libpfm_atom.3 libpfm_nehalem.3
endif
ifeq ($(CONFIG_PFMLIB_ARCH_MIPS64),y)
diff --git a/src/libpfm-3.y/docs/man3/libpfm.3 b/src/libpfm-3.y/docs/man3/libpfm.3
index fe6a741eeab580610903900019f1a7c17d3c9c03..4e0dad7c239f7bca8834ffbc45fed4f4bb3f9672 100644
--- a/src/libpfm-3.y/docs/man3/libpfm.3
+++ b/src/libpfm-3.y/docs/man3/libpfm.3
@@ -1,51 +1,105 @@
-.TH LIBPFM 3 "November, 2003" "" "Linux Programmer's Manual"
+.TH LIBPFM 3 "March, 2008" "" "Linux Programmer's Manual"
.SH NAME
-libpfm \- a helper library to program the hardware performance counters of IA-64 CPUs
+libpfm \- a helper library to program Hardware Performance Units (PMUs)
.SH SYNOPSIS
.nf
.B #include <perfmon/pfmlib.h>
.SH DESCRIPTION
-The libpfm library is a helper library which can be used by applications to program
-the IA-64 Performance Monitoring Unit (PMU). While it is being developed on Linux
-in conjunction with the Linux/ia64 subsystem. It is generic enough to be used on
-other IA-64 operating systems. It is important to realize that the library does
-not make the actual kernel calls to program the PMU, it simply helps you figure
-out which PMU registers to use to measure certain events. On Linux/ia64, for
-instance, it does not make any \fBperfmonctl\fR call.
+The libpfm library is a helper library which is used by applications to
+help program the Performance Monitoring Unit (PMU), i.e., the hardware
+performance counters of modern processors. It provides a generic and portable
+programming interface to help setup the PMU configuration registers given a
+list of events to measure.
-There are two categories of PMU registers. The performance monitoring data registers (PMD)
-are used to collects counts or serve as hardware buffers. The performance monitoring control
-registers (PMCS) are used to indicate what events need to be monitored. Programming the PMU
-consists in setting up the PMC registers to monitor certain events. The PMDS are commonly set
-to zero unless sampling is used.
+A diversity of PMU hardware is supported, a list can be found below
+under \fBSUPPORTED HARDWARE\fR. The library is primarily designed to be used in
+conjunction with the Perfmon2 Linux kernel interface. However, at its core,
+it is totally independent of that interface and could as well be used on other
+operating systems. It is important to realize that the library does not make the
+actual kernel calls to program the PMU, it simply helps applications figure out
+which PMU registers to use to measure certain events or access certain advanced
+PMU features.
-The number of PMC and PMD registers varies from one implementation of the IA-64
-architecture to another. The association of PMC to PMD can also change. Moreover
-the number and encoding of events can also widely change. Finally, the structure
-of a PMC register can also change. All these factors make it quite difficult to
-write monitoring tools.
+The library logically divides PMU registers into two categories. The
+performance monitoring data registers (PMD) are used to collect results, e.g.,
+counts. The performance monitoring configuration registers (PMCS) are used
+to indicate what events to measure or what feature to enable. Programming the
+PMU consists in setting up the PMC registers and collecting the results in the
+PMD registers. The central piece of the library is the \fBpfm_dispatch_events\fR
+function.
-This library is designed to simplify the programming of the PMC registers by hiding
-the complexity behind simple interfaces. The library does this without limiting
-accessibility to model specific features by using a layered design.
+The number of PMC and PMD registers varies between architectures and
+CPU models. The association of PMC to PMD can also change. Moreover
+the number and encodings of events can also widely change. Finally, the
+structure of a PMC register can also change. All these factors make it
+quite difficult to write monitoring tools.
+
+This library is designed to simplify the programming of the PMC registers by
+hiding the complexity behind a simple interface. The library does this without
+limiting accessibility to model specific features by using a layered design.
The library is structured in two layers. The common layer provides an interface
-that is shared across all PMU models.This layer is good enough to setup simple monitoring
-sessions which count occurrences of events. Then, there is a model-specific layer which
-gives access to the model-specific features. For instance, on Itanium, you can use the library
-to setup the registers for the the Branch Trace Buffer. Model-specific interfaces have the
-abbreviated PMU model name in their names. For instance,
+that is shared across all PMU models. This layer is good enough to setup simple
+monitoring sessions which count occurrences of events. Then, there is a
+model-specific layer which gives access to the model-specific features.
+For instance, on Itanium, applications can use the library to setup the
+registers for the Branch Trace Buffer. Model-specific interfaces have the
+abbreviated PMU model name in their names. For instance,
\fBpfm_ita2_get_event_umask()\fR is an Itanium2 (ita2) specific function.
-When the library is initialized, it automatically probes the host CPU and enables the right
-set of interfaces.
-
-The common interface is defined in the \fBpfmlib.h\fR header file. Model-specific interfaces
-are defined in model-specific header files. For instance, \fBpfmlib_itanium2.h\fR provides
-the Itanium2 interface.
+When the library is initialized, it automatically probes the host CPU and
+enables the right set of interfaces.
-.SH AUTHOR
+The common interface is defined in the \fBpfmlib.h\fR header file.
+Model-specific interfaces are defined in model-specific header files.
+For instance, \fBpfmlib_amd64.h\fR provides the AMD64 interface.
+.SH ENVIRONMENT VARIABLES
+It is possible to enable certain debug output of the library using environment
+variables. The following variables are defined:
+.TP
+.B LIBPFM_VERBOSE
+Enable verbose output. Value must be 0 or 1. When not set, verbosity level
+can be controlled with this function.
+.TP
+.B LIBPFM_DEBUG
+Enable debug output. Value must be 0 or 1. When not set, debug level
+can be controlled with this function.
+.TP
+.B LIBPFM_DEBUG_STDOUT
+Redirect verbose and debug output to the standard output file descriptor (stdout).
+By default, the output is directed to the standard error file descriptor (stderr).
+.sp
+Alternatively, it is possible to control verbosity and debug output using
+the \fBpfm_set_options\fR function.
+.LP
+.SH SUPPORTED HARDWARE
+.nf
+libpfm_amd64(3) AMD64 processors K8 and Barcelona (families 0Fh and 10h)
+libpfm_core(3) Intel Core processor family
+libpfm_atom(3) Intel Atom processor family
+libpfm_itanium(3) Intel Itanium
+libpfm_itanium2(3) Intel Itanium 2
+libpfm_montecito(3) Intel dual-core Itanium 2 9000 (Montecito)
+libpfm_p6(3) P6 processor family including the Pentium M processor
+libpfm_powerpc(3) IBM PowerPC and POWER processor families
+ (PPC970(FX,GX), PPC970MP POWER4, POWER4+, POWER5,
+ POWER5+, and POWER6)
+.fi
+.SH AUTHORS
+.nf
Stephane Eranian <eranian@hpl.hp.com>
-.SH SEE ALSO
-pfmlib_itanium(3), pfmlib_itanium2(3) and the set of examples shipped with the library
+Robert Richter <robert.richter@amd.com>
+.if
.PP
+.SH SEE ALSO
+libpfm(3), libpfm_amd64(3), libpfm_core(3), libpfm_itanium2(3),
+libpfm_itanium(3), libpfm_montecito(3), libpfm_p6(3),
+libpfm_powerpc(3).
+.nf
+pfm_dispatch_events(3), pfm_find_event(3), pfm_set_options(3),
+pfm_get_cycle_event(3), pfm_get_event_name(3), pfm_get_impl_pmcs(3),
+pfm_get_pmu_name(3), pfm_get_version(3), pfm_initialize(3),
+pfm_regmask_set(3), pfm_set_options(3), pfm_strerror(3).
+.fi
+.sp
+Examples shipped with the library
diff --git a/src/libpfm-3.y/docs/man3/libpfm_amd64.3 b/src/libpfm-3.y/docs/man3/libpfm_amd64.3
index dbaac818e4df158e3ac8170646d923f44b411da9..99e6412d1dfd24c23bfb787323f92621e1616e27 100644
--- a/src/libpfm-3.y/docs/man3/libpfm_amd64.3
+++ b/src/libpfm-3.y/docs/man3/libpfm_amd64.3
@@ -1,61 +1,158 @@
-.TH LIBPFM 3 "October, 2007" "" "Linux Programmer's Manual"
+.TH LIBPFM 3 "April, 2008" "" "Linux Programmer's Manual"
.SH NAME
-libpfm_x86_64 - support for AMD64 processors
+libpfm_amd64 - support for AMD64 processors
.SH SYNOPSIS
.nf
.B #include <perfmon/pfmlib.h>
.B #include <perfmon/pfmlib_amd64.h>
.sp
.SH DESCRIPTION
-The libpfm library provides full support for the AMD64 processor family 15 and 16 when
-running in either 32 or 64 bit mode. The interface is defined in \fBpfmlib_amd64.h\fR. It consists
-of a set of functions and structures which describe and allow access to the
-AMD64 specific PMU features. Note that it does not support Intel EM64T processors.
+The libpfm library provides full support for the AMD64 processor
+families 0Fh and 10H (K8, Barcelona, Phenom) when running in either
+32-bit or 64-bit mode. The interface is defined in
+\fBpfmlib_amd64.h\fR. It consists of a set of functions and structures
+which describe and allow access to the AMD64 specific PMU
+features. Note that it only supports AMD processors.
.sp
-When AMD64 processor-specific features are needed to support a measurement their descriptions must be passed
-as model-specific input arguments to the \fBpfm_dispatch_events\fR call. The AMD64 processor-specific
-input arguments are described in the \fBpfmlib_amd64_input_param_t\fR structure and the output
-parameters in \fBpfmlib_amd64_output_param_t\fR. They are defined as follows:
+When AMD64 processor-specific features are needed to support a
+measurement, their descriptions must be passed as model-specific input
+arguments to the \fBpfm_dispatch_events()\fR function. The AMD64
+processor-specific input arguments are described in the
+\fBpfmlib_amd64_input_param_t\fR structure and the output parameters
+in \fBpfmlib_amd64_output_param_t\fR. They are defined as follows:
.sp
.nf
typedef struct {
- unsigned int cnt_mask;
- unsigned int flags;
+ uint32_t cnt_mask;
+ uint32_t flags;
} pfmlib_amd64_counter_t;
typedef struct {
- pfmlib_amd64_counter_t pfp_amd64_counters[PMU_AMD64_NUM_COUNTERS];
- uint64_t reserved[4];
+ unsigned int maxcnt;
+ unsigned int options;
+} ibs_param_t;
+
+typedef struct {
+ pfmlib_amd64_counter_t pfp_amd64_counters[PMU_AMD64_MAX_COUNTERS];
+ uint32_t flags;
+ uint32_t reserved1;
+ ibs_param_t ibsfetch;
+ ibs_param_t ibsop;
+ uint64_t reserved2;
} pfmlib_amd64_input_param_t;
typedef struct {
- uint64_t reserved[8];
+ uint32_t ibsfetch_base;
+ uint32_t ibsop_base;
+ uint64_t reserved[7];
} pfmlib_amd64_output_param_t;
.fi
-.sp
-.sp
-The X86-64 processor provides a few additional per-event features for
-counters: thresholding, inversion, edge detection. They can be set using the
-\fBpfp_amd64_counters\fR data structure for each event. The \fBflags\fR
-field can be initialized as follows:
+.LP
+The \fBflags\fR field of \fBpfmlib_amd64_input_param_t\fR describes
+which features of the PMU to use. Following use flags exist:
+.TP
+.B PFMLIB_AMD64_USE_IBSFETCH
+Profile IBS fetch performance (see below under \fBINSTRUCTION BASED
+SAMPLING\fR)
+.TP
+.B PFMLIB_AMD64_USE_IBSOP
+Profile IBS execution performance (see below under \fBINSTRUCTION BASED
+SAMPLING\fR)
+.LP
+Multiple features can be selected. Note that there are no use flags
+needed for \fBADDITIONAL PER-EVENT FEATURES\fR.
+.LP
+Various typedefs for MSR encoding and decoding are available. See
+\fBpfmlib_amd64.h\fR for details.
+.SS ADDITIONAL PER-EVENT FEATURES
+AMD64 processors provide a few additional per-event features for
+counters: thresholding, inversion, edge detection,
+virtualization. They can be set using the \fBpfp_amd64_counters\fR
+data structure for each event. The \fBflags\fR field of
+\fBpfmlib_amd64_counter_t\fR can be initialized as follows:
.TP
.B PFMLIB_AMD64_SEL_INV
Inverse the results of the \fBcnt_mask\fR comparison when set
.TP
.B PFMLIB_AMD64_SEL_EDGE
Enables edge detection of events.
+.TP
+.B PFMLIB_AMD64_SEL_GUEST
+On AMD64 Family 10h processors only. Event is only measured when
+processor is in guest mode.
+.TP
+.B PFMLIB_AMD64_SEL_HOST
+On AMD64 Family 10h processors only. Event is only measured when
+processor is in host mode.
.LP
-
-The \fBcnt_mask\fR field contains is used to set the event threshold.
-The value of the counter is incremented each time the number of occurrences
-per cycle of the event is greater or equal to the value of the field. When
-zero all occurrences are counted.
-.sp
+The \fBcnt_mask\fR field is used to set the event threshold. The
+value of the counter is incremented each time the number of
+occurrences per cycle of the event is greater or equal to the value of
+the field. When zero all occurrences are counted.
+.SS INSTRUCTION BASED SAMPLING (IBS)
+The libpfm_amd64 provides access to the model specific feature
+Instruction Based Sampling (IBS). IBS has been introduced with family
+10h.
+.LP
+The IBS setup is using the structures \fBpfmlib_amd64_input_param_t\fR
+and \fBpfmlib_amd64_output_param_t\fR with its members \fBflags\fR,
+\fBibsfetch\fR, \fBibsop\fR, \fBibsfetch_base\fR,
+\fBibsop_base\fR. The input arguments \fBibsop\fR and \fBibsfetch\fR
+can be set in inp_mod (type \fBpfmlib_amd64_input_param_t\fR). The
+corresponding \fBflags\fR must be set to enable a feature.
+.LP
+Both, IBS execution profiling and IBS fetch profiling, require a
+maximum count value of the periodic counter (\fBmaxcnt\fR) as
+parameter. This is a 20 bit value, bits 3:0 are always set to
+zero. Additionally, there is an option (\fBoptions\fR) to enable
+randomization (\fBIBS_OPTIONS_RANDEN\fR) for IBS fetch profiling.
+.LP
+The IBS registers IbsFetchCtl (0xC0011030) and IbsOpCtl (0xC0011033)
+are available as PMC and PMD in Perfmon. The function
+\fBpfm_dispatch_events()\fR initializes these registers according to
+the input parameters in \fBpfmlib_amd64_input_param_t\fR.
+.LP
+Also, \fBpfm_dispatch_events()\fR passes back the index in pfp_pmds[]
+of the IbsOpCtl and IbsFetchCtl register. For this there are the
+entries \fBibsfetch_base\fR and \fBibsop_base\fR in
+\fBpfmlib_amd64_output_param_t\fR. The index may vary depending on
+other PMU settings, especially counter settings. If using the PMU with
+only one IBS feature and no counters, the index of the base register
+is 0.
+.LP
+Example code:
.LP
+.nf
+ /* initialize IBS */
+ inp_mod.ibsop.maxcnt = 0xFFFF0;
+ inp_mod.flags |= PFMLIB_AMD64_USE_IBSOP;
+ ret = pfm_dispatch_events(NULL, &inp_mod, &outp, &outp_mod);
+ if (ret != PFMLIB_SUCCESS) { ... }
+
+ /* setup PMU */
+ /* PMC_IBSOPCTL */
+ pc[0].reg_num = outp.pfp_pmcs[0].reg_num;
+ pc[0].reg_value = outp.pfp_pmcs[0].reg_value;
+ /* PMD_IBSOPCTL */
+ pd[0].reg_num = outp.pfp_pmds[0].reg_num;
+ pd[0].reg_value = 0;
+
+ /* setup sampling */
+ pd[0].reg_flags = PFM_REGFL_OVFL_NOTIFY;
+ /* add range check here */
+ pd[0].reg_smpl_pmds[0] =
+ ((1UL << PMD_IBSOP_NUM) - 1) << outp.pfp_pmds[0].reg_num;
+
+ /* write pc and pd to PMU */
+ ...
+.fi
.SH ERRORS
-Refer to the description of \fBpfm_dispatch_events()\fR for errors.
+Refer to the description of the \fBpfm_dispatch_events()\fR function for errors.
.SH SEE ALSO
pfm_dispatch_events(3) and set of examples shipped with the library
-.SH AUTHOR
-Stephane Eranian <eranian@hpl.hp.com>
+.SH AUTHORS
+.nf
+Stephane Eranian <eranian@gmail.com>
+Robert Richter <robert.richter@amd.com>
+.if
.PP
diff --git a/src/libpfm-3.y/docs/man3/libpfm_core.3 b/src/libpfm-3.y/docs/man3/libpfm_core.3
index 2b31f2d2b4ab882c9425613223340a996a5a7984..b738434973de1462ae3641db6f3cca45918f18c4 100644
--- a/src/libpfm-3.y/docs/man3/libpfm_core.3
+++ b/src/libpfm-3.y/docs/man3/libpfm_core.3
@@ -8,14 +8,14 @@ libpfm_core - support for Intel Core processor family
.sp
.SH DESCRIPTION
The libpfm library provides full support for the Intel Core processor family, including
-the Core 2 Duo series. The interface is defined in \fBpfmlib_core.h\fR. It consists
+the Core 2 Duo and Quad series. The interface is defined in \fBpfmlib_core.h\fR. It consists
of a set of functions and structures which describe and allow access to the
Intel Core processors specific PMU features.
.sp
When Intel Core processor specific features are needed to support a measurement, their descriptions
-must be passed as model-specific input arguments to the \fBpfm_dispatch_events\fR call. The Intel Core
- processors specific input arguments are described in the \fBpfmlib_core_input_param_t\fR structure and
-the output parameters in \fBpfmlib_core_output_param_t\fR. They are defined as follows:
+must be passed as model-specific input arguments to the \fBpfm_dispatch_events()\fR function. The Intel Core
+processors specific input arguments are described in the \fBpfmlib_core_input_param_t\fR structure. No
+output parameters are currently defined. The input parameters are defined as follows:
.sp
.nf
typedef struct {
@@ -32,17 +32,13 @@ typedef struct {
pfmlib_core_pebs_t pfp_core_pebs;
uint64_t reserved[4];
} pfmlib_core_input_param_t;
-
-typedef struct {
- uint64_t reserved[8];
-} pfmlib_core_output_param_t;
.fi
.sp
.sp
The Intel Core processor provides a few additional per-event features for
counters: thresholding, inversion, edge detection. They can be set using the
\fBpfp_core_counters\fR data structure for each event. The \fBflags\fR
-field can be initialized as follows:
+field can be initialized with any combinations of the following values:
.TP
.B PFMLIB_CORE_SEL_INV
Inverse the results of the \fBcnt_mask\fR comparison when set
@@ -50,24 +46,25 @@ Inverse the results of the \fBcnt_mask\fR comparison when set
.B PFMLIB_CORE_SEL_EDGE
Enables edge detection of events.
.LP
-The \fBcnt_mask\fR field contains is used to set the event threshold.
+The \fBcnt_mask\fR field is used to set the event threshold.
The value of the counter is incremented each time the number of occurrences
-per cycle of the event is greater or equal to the value of the field. When
-zero all occurrences are counted.
+per cycle of the event is greater or equal to the value of the field.
+Thus the event is modified to actually measure the number of qualifying cycles.
+When zero all occurrences are counted (this is the default).
.sp
.SH Support for Precise-Event Based Sampling (PEBS)
The library can be used to setup the PMC registers when using PEBS. In this case,
the \fBpfp_core_pebs\fR structure must be used and the \fBpebs_used\fR field must
be set to 1. When using PEBS, it is not possible to use more than one event.
-.SH Support for Intel Core 2 Duo processors
-The Intel Core 2 Duo processors are based on the Intel Core micro-architecture.
+.SH Support for Intel Core 2 Duo and Quad processors
+The Intel Core 2 Duo and Quad processors are based on the Intel Core micro-architecture.
They implement the Intel architectural PMU and some extensions such as PEBS.
They support all the architectural events and a lot more Core 2 specific events.
The library auto-detects the processor and provides access to Core 2 events whenever
possible.
.LP
.SH ERRORS
-Refer to the description of \fBpfm_dispatch_events()\fR for errors.
+Refer to the description of the \fBpfm_dispatch_events()\fR function for errors.
.SH SEE ALSO
pfm_dispatch_events(3) and set of examples shipped with the library
.SH AUTHOR
diff --git a/src/libpfm-3.y/docs/man3/libpfm_itanium.3 b/src/libpfm-3.y/docs/man3/libpfm_itanium.3
index a7a6cf2058a6626e42e476aa6660dc50dcfa5944..298fba20b751afacbb98d792ad01e1bc22cd9dff 100644
--- a/src/libpfm-3.y/docs/man3/libpfm_itanium.3
+++ b/src/libpfm-3.y/docs/man3/libpfm_itanium.3
@@ -28,7 +28,7 @@ Itanium specific PMU features.
.sp
The Itanium specific functions presented here are mostly used to retrieve
the characteristics of an event. Given a opaque event descriptor, obtained
-by \fBpfm_find_event\fR or its derivatives, they return a boolean value
+by the \fBpfm_find_event()\fR or its derivative functions, they return a boolean value
indicating whether this event support this features or is of a particular
kind.
.sp
@@ -83,7 +83,7 @@ designated by \fBi\fR.
.sp
When the Itanium specific features are needed to support a measurement their descriptions must be passed
-as model-specific input arguments to the \fBpfm_dispatch_events\fR call. The Itanium specific
+as model-specific input arguments to the \fBpfm_dispatch_events()\fR function. The Itanium specific
input arguments are described in the \fBpfmlib_ita_input_param_t\fR structure and the output
parameters in \fBpfmlib_ita_output_param_t\fR. They are defined as follows:
.sp
@@ -207,7 +207,7 @@ for this event. Qualifiers includes opcode matching, code and data range restric
event is marked as not supporting a particular qualifier, it usually means that it is ignored, i.e.,
the extra level of filtering is ignored. For instance, the CPU_CYCLES events does not support code
range restrictions and by default the library will refuse to program it if range restriction is also
-requested. Using the flag will override the check and the call to \fBpfm_dispatch_events\fR will succeed.
+requested. Using the flag will override the check and the call to the \fBpfm_dispatch_events()\fR function will succeed.
In this case, CPU_CYCLES will be measured for the entire program and not just for the code range requested.
For certain measurements this is perfectly acceptable as the range restriction will only be applied relevant
to events which support it. Make sure you understand which events do not support certain qualifiers before
@@ -324,7 +324,7 @@ the BTB is not programmed.
.SH DATA AND CODE RANGE RESTRICTIONS
The \fBpfp_ita_drange\fR and \fBpfp_ita_irange\fR fields control the range restrictions for the data and
code respectively. The idea is that the application passes a set of ranges, each designated by a start
-and end address. Upon return from \fBpfm_dispatch_events()\fR, the application gets back the set of
+and end address. Upon return from the \fBpfm_dispatch_events()\fR function, the application gets back the set of
registers and their values that needs to be programmed via a kernel interface.
Range restriction is implemented using the debug registers. There is a limited number of debug registers
@@ -387,7 +387,7 @@ bytes by which the actual range exceeds the requested range.
.sp
.LP
.SH ERRORS
-Refer to the description of \fBpfm_dispatch_events()\fR for errors when using the Itanium
+Refer to the description of the \fBpfm_dispatch_events()\fR function for errors when using the Itanium
specific input and output arguments.
.SH SEE ALSO
pfm_dispatch_events(3) and set of examples shipped with the library
diff --git a/src/libpfm-3.y/docs/man3/libpfm_itanium2.3 b/src/libpfm-3.y/docs/man3/libpfm_itanium2.3
index eb6fc6cf4e2eada499729d0cfcaddf97b7cb8cc1..edb05ba8ed4cb7c1ef380aca5921223a1d0860ea 100644
--- a/src/libpfm-3.y/docs/man3/libpfm_itanium2.3
+++ b/src/libpfm-3.y/docs/man3/libpfm_itanium2.3
@@ -33,7 +33,7 @@ Itanium 2 specific PMU features.
.sp
The Itanium 2 specific functions presented here are mostly used to retrieve
the characteristics of an event. Given a opaque event descriptor, obtained
-by \fBpfm_find_event\fR or its derivatives, they return a boolean value
+by the \fBpfm_find_event()\fR or its derivative functions, they return a boolean value
indicating whether this event support this feature or is of a particular
kind.
.sp
@@ -104,10 +104,10 @@ impose some restrictions on events. For a given group, events from different set
cannot be measured at the same time. If the event does not belong to a group
then the value of \fBset\fR is \fBPFMLIB_MONT_EVT_NO_SET\fR.
.sp
-The \fBpfm_ita2_irange_is_fine\fR function returns 1 if the configuration description passed
+The \fBpfm_ita2_irange_is_fine()\fR function returns 1 if the configuration description passed
in \fBoutp\fR, the generic output parameters and \fBmod_out\fR, the Itanium2 specific output parameters,
use code range restriction in fine mode. Otherwise the function returns 0. This function can only be
-called after a call \fBpfm_dispatch_events()\fR which returned successfully and had the data
+called after a call to the \fBpfm_dispatch_events()\fR function returns successfully and had the data
structures pointed to by \fBoutp\fR and \fBmod_out\fR as output parameters.
.sp
The \fBpfm_ita2_get_event_ear_mode()\fR function returns in \fBmode\fR the EAR mode of the
@@ -125,7 +125,7 @@ The event is an ALAT EAR. It can only be a data EAR event.
.sp
.LP
When the Itanium 2 specific features are needed to support a measurement their descriptions must be passed
-as model-specific input arguments to the \fBpfm_dispatch_events\fR call. The Itanium 2 specific
+as model-specific input arguments to the \fBpfm_dispatch_events()\fR function. The Itanium 2 specific
input arguments are described in the \fBpfmlib_ita2_input_param_t\fR structure and the output
parameters in \fBpfmlib_ita2_output_param_t\fR. They are defined as follows:
.sp
@@ -250,7 +250,7 @@ for this event. Qualifiers includes opcode matching, code and data range restric
event is marked as not supporting a particular qualifier, it usually means that it is ignored, i.e.,
the extra level of filtering is ignored. For instance, the CPU_CYCLES event does not support code
range restrictions and by default the library will refuse to program it if range restriction is also
-requested. Using the flag will override the check and the call to \fBpfm_dispatch_events\fR will succeed.
+requested. Using the flag will override the check and the call to the \fBpfm_dispatch_events()\fR function will succeed.
In this case, CPU_CYCLES will be measured for the entire program and not just for the code range requested.
For certain measurements this is perfectly acceptable as the range restriction will only be applied relevant
to events which support it. Make sure you understand which events do not support certain qualifiers before
@@ -333,7 +333,7 @@ is 2, then branches with correctly predicted path are captured. Finally if this
their path prediction.
.TP
.B btb_brt
-If this field is 0, then no branch is captured. If this field is 1, then only IP-relative branches are captured. If this field
+If this field is 0, then all branches are captured. If this field is 1, then only IP-relative branches are captured. If this field
is 2, then only return branches are captured. Finally if this field is 3 then only non-return indirect branches are captured.
.TP
.B btb_plm
@@ -365,7 +365,7 @@ the BTB is not programmed.
.SH DATA AND CODE RANGE RESTRICTIONS
The \fBpfp_ita2_drange\fR and \fBpfp_ita2_irange\fR fields control the range restrictions for the data and
code respectively. The idea is that the application passes a set of ranges, each designated by a start
-and end address. Upon return from \fBpfm_dispatch_events()\fR, the application gets back the set of
+and end address. Upon return from the \fBpfm_dispatch_events()\fR function, the application gets back the set of
registers and their values that needs to be programmed via a kernel interface.
Range restriction is implemented using the debug registers. There is a limited number of debug registers and they go in pair. With
@@ -447,7 +447,7 @@ bytes by which the actual range exceeds the requested range.
.sp
.LP
.SH ERRORS
-Refer to the description of \fBpfm_dispatch_events()\fR for errors when using the Itanium 2
+Refer to the description of the \fBpfm_dispatch_events()\fR function for errors when using the Itanium 2
specific input and output arguments.
.SH SEE ALSO
pfm_dispatch_events(3) and set of examples shipped with the library
diff --git a/src/libpfm-3.y/docs/man3/libpfm_montecito.3 b/src/libpfm-3.y/docs/man3/libpfm_montecito.3
index fbc53f22594f18d5e57d7ef938b0172b65223340..d376ed7a5a80c557a9138fb08ba852d6d03693a3 100644
--- a/src/libpfm-3.y/docs/man3/libpfm_montecito.3
+++ b/src/libpfm-3.y/docs/man3/libpfm_montecito.3
@@ -34,7 +34,7 @@ model specific PMU features.
.sp
The Itanium 2 900 (Montecito) processor specific functions presented here are mostly used to retrieve
the characteristics of an event. Given a opaque event descriptor, obtained
-by \fBpfm_find_event\fR or its derivatives, they return a boolean value
+by the \fBpfm_find_event()\fR or its derivative functions, they return a boolean value
indicating whether this event support this feature or is of a particular
kind.
.sp
@@ -124,11 +124,11 @@ The event does not belong to a processor thread
Hybrid event. It is floating if measured with .me. If is causal otherwise.
.LP
.sp
-The \fBpfm_mont_irange_is_fine\fR function returns 1 if the configuration description passed
+The \fBpfm_mont_irange_is_fine()\fR function returns 1 if the configuration description passed
in \fBoutp\fR, the generic output parameters and \fBmod_out\fR, the Itanium 2
9000 (Montecito) specific output parameters,
use code range restriction in fine mode. Otherwise the function returns 0. This function can only be
-called after a call \fBpfm_dispatch_events()\fR which returned successfully and had the data
+called after a call to the \fBpfm_dispatch_events()\fR function returns successfully and had the data
structures pointed to by \fBoutp\fR and \fBmod_out\fR as output parameters.
.sp
The \fBpfm_mont_get_event_ear_mode()\fR function returns in \fBmode\fR the EAR mode of the
@@ -146,7 +146,7 @@ The event is an ALAT EAR. It can only be a data EAR event.
.sp
.LP
When the Itanium 2 9000 (Montecito) specific features are needed to support a measurement their
-descriptions must be passed as model-specific input arguments to the \fBpfm_dispatch_events\fR call.
+descriptions must be passed as model-specific input arguments to the \fBpfm_dispatch_events()\fR function.
The Itanium 2 9000 (Montecito) specific input arguments are described in the \fBpfmlib_mont_input_param_t\fR
structure and the output parameters in \fBpfmlib_mont_output_param_t\fR. They are defined as follows:
.sp
@@ -260,7 +260,7 @@ for this event. Qualifiers includes opcode matching, code and data range restric
event is marked as not supporting a particular qualifier, it usually means that it is ignored, i.e.,
the extra level of filtering is ignored. For instance, the FE_BUBBLE_ALL event does not support code
range restrictions and by default the library will refuse to program it if range restriction is also
-requested. Using the flag will override the check and the call to \fBpfm_dispatch_events\fR will succeed.
+requested. Using the flag will override the check and the call to the \fBpfm_dispatch_events()\fR function will succeed.
In this case, FE_BUBBLE_ALL will be measured for the entire program and not just for the code range requested.
For certain measurements this is perfectly acceptable as the range restriction will only be applied relevant
to events which support it. Make sure you understand which events do not support certain qualifiers before
@@ -389,7 +389,7 @@ the ETB is not programmed.
.SH DATA AND CODE RANGE RESTRICTIONS
The \fBpfp_mont_drange\fR and \fBpfp_mont_irange\fR fields control the range restrictions for the data and
code respectively. The idea is that the application passes a set of ranges, each designated by a start
-and end address. Upon return from \fBpfm_dispatch_events()\fR, the application gets back the set of
+and end address. Upon return from the \fBpfm_dispatch_events()\fR function, the application gets back the set of
registers and their values that needs to be programmed via a kernel interface.
Range restriction is implemented using the debug registers. There is a limited number of debug registers and they go in pair. With
@@ -487,7 +487,7 @@ The number of cycles by which to delay the freeze of the ETB after a PMU interru
.LP
.sp
.SH ERRORS
-Refer to the description of \fBpfm_dispatch_events()\fR for errors when using
+Refer to the description of the \fBpfm_dispatch_events()\fR function for errors when using
the Itanium 2 9000 (Montecito) specific input and output arguments.
.SH SEE ALSO
pfm_dispatch_events(3) and set of examples shipped with the library
diff --git a/src/libpfm-3.y/docs/man3/libpfm_p6.3 b/src/libpfm-3.y/docs/man3/libpfm_p6.3
index 11dd73c9a0928c95d5c13ba990f03afe20ed4806..3a562b37f96885311676269994f3012475d1fa46 100644
--- a/src/libpfm-3.y/docs/man3/libpfm_p6.3
+++ b/src/libpfm-3.y/docs/man3/libpfm_p6.3
@@ -13,7 +13,7 @@ of a set of functions and structures which describe and allow access to the
P6 processors specific PMU features.
.sp
When P6 processor specific features are needed to support a measurement, their descriptions must be passed
-as model-specific input arguments to the \fBpfm_dispatch_events\fR call. The P6 processors specific
+as model-specific input arguments to the \fBpfm_dispatch_events()\fR function. The P6 processors specific
input arguments are described in the \fBpfmlib_i386_p6_input_param_t\fR structure and the output
parameters in \fBpfmlib_i386_p6_output_param_t\fR. They are defined as follows:
.sp
@@ -57,7 +57,7 @@ processor and can distinguish generic P6 processor from a Pentium. Thus no
special call is needed.
.sp
.SH ERRORS
-Refer to the description of \fBpfm_dispatch_events()\fR for errors.
+Refer to the description of the \fBpfm_dispatch_events()\fR function for errors.
.SH SEE ALSO
pfm_dispatch_events(3) and set of examples shipped with the library
.SH AUTHOR
diff --git a/src/libpfm-3.y/docs/man3/libpfm_powerpc.3 b/src/libpfm-3.y/docs/man3/libpfm_powerpc.3
index 31f5d6a50ab7c4902128055dafb4ac08ec4799ad..a5abb0cb62d702ed58b6191f586451960b17af21 100644
--- a/src/libpfm-3.y/docs/man3/libpfm_powerpc.3
+++ b/src/libpfm-3.y/docs/man3/libpfm_powerpc.3
@@ -13,7 +13,7 @@ processors: PPC970(FX,GX), PPC970MP POWER4, POWER4+, POWER5, POWER5+, and POWER6
.sp
.SH MODEL-SPECIFIC PARAMETERS
At present, the model_in and model_out model-specific input and output
-parameters are not used by pfm_dispatch_events call. For future
+parameters are not used by \fBpfm_dispatch_events()\fR function. For future
compatibility, NULLs must be passed for these arguments.
.sp
.SH COMBINING EVENTS IN A SET
@@ -22,7 +22,7 @@ together arbitrarily in the same event set, even if there are a sufficient
number of counters available. This implementation for IBM PowerPC/POWER
bases the event compatibility on a set of previously-defined compatible
event groups. If the events placed in an event set are all members of one
-of the predefined event groups, a call to pfm_dispatch_events will be
+of the predefined event groups, a call to the \fBpfm_dispatch_events()\fR function will be
successful. With the current interface, there is no way to discover
apriori which events are compatible, so application software that wishes to
combine events must do so by trial and error, possibly using multiplexed
@@ -30,7 +30,7 @@ event sets to count events that cannot otherwise be combined in the same
set.
.sp
.SH ERRORS
-Refer to the description of \fBpfm_dispatch_events()\fR for errors.
+Refer to the description of the \fBpfm_dispatch_events()\fR function for errors.
.SH SEE ALSO
pfm_dispatch_events(3) and set of examples shipped with the library
.SH AUTHOR
diff --git a/src/libpfm-3.y/docs/man3/pfm_dispatch_events.3 b/src/libpfm-3.y/docs/man3/pfm_dispatch_events.3
index 1632ffb79e0f35210b0a96aeca12eecd49988408..07175096c5e459bdba7f7289d3b2fc7211385da1 100644
--- a/src/libpfm-3.y/docs/man3/pfm_dispatch_events.3
+++ b/src/libpfm-3.y/docs/man3/pfm_dispatch_events.3
@@ -58,7 +58,7 @@ Each event is described in the \fBpfp_events\fR table by an opaque descriptor st
the \fBevent\fR field. This descriptor is obtained with the \fBpfm_find_full_event()\fR
or derivative functions. For some events, it may be necessary to specify at least one
unit mask in the \fBunit_masks\fR table. A unit mask is yet another opaque descriptor
-obtained via \fBpfm_find_event_mask()\fR or \fBpfm_find_full_event\fR. Typically, if
+obtained via the \fBpfm_find_event_mask()\fR or \fBpfm_find_full_event()\fR functions. Typically, if
an event supports multiple unit masks, they can be combined in which case more than one
entry in \fBunit_masks\fR must be specified. The actual number of unit mask descriptors
passed must be indicated in \fBnum_masks\fR. When no unit mask is used, this
@@ -141,14 +141,14 @@ address or index for the PMC register.
Refer to the PMU specific manual for a description of the model-specific
output parameters to be returned in \fBmod_out\fR.
.sp
-The current implementation of the \fBpfm_dispatch_events\fR completely overwrites
+The current implementation of the \fBpfm_dispatch_events()\fR function completely overwrites
the \fBpfmlib_output_param\fR structure. In other words, results do not accumulate
into the \fBpfp_pmcs\fR table across multiple calls. Unused fields are
guaranteed to be zeroed upon successful return.
.sp
Depending on the PMU model, there may not always be a one to one mapping between
a PMC register and a data register. Register dependencies may be more intricate.
-However the \fBpfm_dispatch_events\fR guarantees certain ordering between the
+However the \fBpfm_dispatch_events()\fR function guarantees certain ordering between the
\fBpfp_pmcs\fR and \fBpfp_pmds\fR tables. In particular, it guarantees that
the \fBpfp_pmds\fR table always starts with the counters corresponding, in
the same order, to the events as provided in the \fBpfp_event\fR table on input.
diff --git a/src/libpfm-3.y/docs/man3/pfm_find_event.3 b/src/libpfm-3.y/docs/man3/pfm_find_event.3
index 814031ed4f3613202e771b072ec824c239a2337a..2842c1c75a02a7d431eb49f91548f03b5656919d 100644
--- a/src/libpfm-3.y/docs/man3/pfm_find_event.3
+++ b/src/libpfm-3.y/docs/man3/pfm_find_event.3
@@ -11,7 +11,8 @@ masks
.BI "int pfm_find_full_event(const char *"str ", pfmlib_event_t *"e ");"
.BI "int pfm_find_event_bycode(int "code ", unsigned int *"desc ");"
.BI "int pfm_find_event_bycode_next(unsigned int "desc1 ", int "code ", unsigned int *"desc ");"
-.BI "int pfm_find_event_mask(unsigned int *"idx ", const char *"str ", unsigned int *"mask_idx ");"
+.BI "int pfm_find_event_mask(unsigned int "idx ", const char *"str ", unsigned int *"mask_idx ");"
+
.sp
.SH DESCRIPTION
The PMU counters can be programmed to count the number of occurrences
@@ -30,13 +31,13 @@ The set of functions described here can be used to get an event descriptor
given either the name of the event or its code. Several events may
share the same code. An event name is a string structured as: event_name[:unit_mask1[:unit_mask2]].
.sp
-The \fBpfm_find_event\fR function is a general purpose search routine.
+The \fBpfm_find_event()\fR function is a general purpose search routine.
Given an event name in \fBstr\fR, it returns the descriptor for the
corresponding event. If unit masks are provided, they are not taken
into account. This function is being \fBdeprecated\fR in favor of
-\fBpfm_find_full_event\fR.
+the \fBpfm_find_full_event()\fR function.
.sp
-The \fBpfm_find_full_event\fR function is the general purpose search routine.
+The \fBpfm_find_full_event()\fR function is the general purpose search routine.
Given an event name in \fBstr\fR, it returns in \fBev\fR, the full event descriptor that
includes the event descriptor in \fBev->event\fR and the unit mask descriptors
in \fBev->unit_masks\fR. The number of unit masks descriptors returned is
@@ -46,21 +47,21 @@ For instance, if event A supports unit masks M1 (0x1) and M2 (0x40), and
both unit masks are to be measured, then the following values for
\fBstr\fR are valid: "A:M1:M2", "A:M1:0x40", "A:M2:0x1", "A:0x1:0x40", "A:0x41".
.sp
-The \fBpfm_find_event_bycode\fR function searches for an event given
+The \fBpfm_find_event_bycode()\fR function searches for an event given
its \fBcode\fR represented as an integer. It returns in \fBdesc\fR,
the event code. Unit masks are ignored.
.sp
Because there can be several events with the same code, the library
-provides the \fBpfm_find_event_bycode_next\fR to search for other
+provides the \fBpfm_find_event_bycode_next()\fR function to search for other
events with the same code. Given an event \fBdesc1\fR and a \fBcode\fR,
this function will look for the next event with the same code. If
such an event exists, its descriptor will be stored into \fBdesc\fR.
-It is not necessary to have called \fBpfm_find_event_bycode\fR prior
+It is not necessary to have called the \fBpfm_find_event_bycode()\fR function prior
to calling this function. This function is fully threadsafe as it does
not maintain any state between calls.
.sp
-The \fBpfm_find_event_mask\fR function is used to find the unit mask descriptor
+The \fBpfm_find_event_mask()\fR function is used to find the unit mask descriptor
based on its name or numerical value passed in \fBstr\fR for the event specified
in \fBidx\fR. The numeric value must be an exact match of an existing unit mask value,
i.e., all bits must match. Some events do not have unit masks, in which case this function
diff --git a/src/libpfm-3.y/docs/man3/pfm_get_cycle_event.3 b/src/libpfm-3.y/docs/man3/pfm_get_cycle_event.3
index 3112e48db7f33bf430d7830f69f2a1144cb7aa26..e2623fece1ba07cef661615cd495139882e767fe 100644
--- a/src/libpfm-3.y/docs/man3/pfm_get_cycle_event.3
+++ b/src/libpfm-3.y/docs/man3/pfm_get_cycle_event.3
@@ -22,14 +22,14 @@ exact definition of those events. The library provides this information
on a best effort basis. User must refer to PMU model specific documentation
to validate the event definition.
.sp
-The \fBpfm_get_cycle_event\fR function returns in \fBev\fR the event
+The \fBpfm_get_cycle_event()\fR function returns in \fBev\fR the event
and optional unit mask descriptors for the event that counts elapsed
cycles. Depending on the PMU model, there may be unit mask(s) necessary
to count cycles. Application must check the value returned in
\fBev->num_masks\fR.
.sp
-The \fBpfm_get_inst_retired_event\fR function returns in \fBev\fR the event
+The \fBpfm_get_inst_retired_event()\fR function returns in \fBev\fR the event
and optional unit mask descriptors for the event that counts the number
of returned instruction. Depending on the PMU model, there may be unit
mask(s) necessary to count retired instructions. Application must check
diff --git a/src/libpfm-3.y/docs/man3/pfm_get_event_name.3 b/src/libpfm-3.y/docs/man3/pfm_get_event_name.3
index fb116a73791e6d8f87818e3f5f8bf123eae57965..becbfb25e86d2417f9b6e65119f2d4f7050150b8 100644
--- a/src/libpfm-3.y/docs/man3/pfm_get_event_name.3
+++ b/src/libpfm-3.y/docs/man3/pfm_get_event_name.3
@@ -7,9 +7,9 @@ pfm_get_event_description, pfm_get_event_mask_description \- get event informati
.nf
.B #include <perfmon/pfmlib.h>
.sp
-.BI "int pfm_get_event_name(unsigned int " e ", char *"name ", size_t" maxlen ");"
-.BI "int pfm_get_full_event_name(pfmlib_event_t *" ev ", char *"name ", size_t" maxlen ");"
-.BI "int pfm_get_event_mask_name(unsigned int " e ", unsigned int "mask ", char *"name ", size_t" maxlen ");"
+.BI "int pfm_get_event_name(unsigned int " e ", char *"name ", size_t " maxlen ");"
+.BI "int pfm_get_full_event_name(pfmlib_event_t *" ev ", char *"name ", size_t " maxlen ");"
+.BI "int pfm_get_event_mask_name(unsigned int " e ", unsigned int "mask ", char *"name ", size_t " maxlen ");"
.BI "int pfm_get_event_code(unsigned int " e ", int *"code ");"
.BI "int pfm_get_event_mask_code(unsigned int " e ", unsigned int "mask ", int *"code ");"
.BI "int pfm_get_event_code_counter(unsigned int " e ", unsigned int " cnt ", int *"code ");"
@@ -20,87 +20,94 @@ pfm_get_event_description, pfm_get_event_mask_description \- get event informati
.BI "int pfm_get_event_mask_description(unsigned int " ev ", unsigned int "mask ", char **" str ");"
.sp
.SH DESCRIPTION
-The \fBpfm_get_event_name\fR function returns in \fBname\fR the event
+The \fBpfm_get_event_name()\fR function returns in \fBname\fR the event
name given its opaque descriptor in \fBe\fR. The \fBmaxlen\fR argument
-indicates the maximum length of the buffer provided for \fBname\fR.
-Up to \fBmaxlen-1\fR characters will be returned, not including the
-termination character. Event names are returned in all upper case.
+indicates the maximum length of the buffer provided for \fBname\fR. Up
+to \fBmaxlen\fR-1 characters are stored in the buffer.
+The buffer size must be large enough to store the event name, otherwise
+an error is returned. This behavior is required to avoid returning partial
+names with no way for the caller to verify this is not the full name, except
+by failing other calls. The buffer can be appropriately sized using the
+\fBpfm_get_max_event_name_len()\fR function. The returned name is a
+null terminated string with all upper-case characters and no spaces.
.sp
-The \fBpfm_get_full_event_name\fR function returns in \fBname\fR the event
+The \fBpfm_get_full_event_name()\fR function returns in \fBname\fR the event
name given the full event description in \fBev\fR. The description contains
the event code in \fBev->event\fR and optional unit masks descriptors in
\fBev->unit_masks\fR. The \fBmaxlen\fR argument indicates the maximum length
-of the buffer provided for \fBname\fR. If more than \fBmaxlen-1\fR characters
-are needed to represent the event, an error is returned.
+of the buffer provided for \fBname\fR. If more than \fBmaxlen\fR-1 characters
+are needed to represent the event, an error is returned. Applications may use
+the \fBpfm_get_max_event_name_len()\fR function to size the buffer correctly.
In case unit masks are provided, the final event name string is structured as:
event_name:unit_masks1[:unit_masks2]. Event names and unit masks names are
returned in all upper case.
.sp
-The \fBpfm_get_event_code\fR function returns the event code in \fBcode\fR
+The \fBpfm_get_event_code()\fR function returns the event code in \fBcode\fR
given its opaque descriptor \fBe\fR.
.sp
On some PMU models, the code associated with an event is different based
-on the counter it is programmed into. The \fBpfm_get_event_code_counter\fR
+on the counter it is programmed into. The \fBpfm_get_event_code_counter()\fR
function is used to retrieve the event code in \fBcode\fR when the event \fBe\fR
is programmed into counter \fBcnt\fR. The counter index \fBcnt\fR must correspond
to of a counting PMD register.
.sp
-Given an opaque event descriptor \fBe\fR, the \fBpfm_get_event_counters\fR
+Given an opaque event descriptor \fBe\fR, the \fBpfm_get_event_counters()\fR
function returns in \fBcounters\fR a bitmask of type \fBpfmlib_regmask_t\fR where
each bit set represents a PMU config register which can be used to program this
event. The bitmask must be accessed using accessor macros defined by the library.
+.so
+The \fBpfm_get_num_events()\fR function returns in \fBcount\fR the
+total number of events available for the PMU model. On some PMU
+models, however, not all events in the table may be useable due
+to processor stepping changes. However, The library guarantees that
+no more that \fBcount\fR events are available.
.sp
It is possible to list all existing events for the detected host PMU
using accessor functions as the full table of events is not accessible
to the applications. The index of the first event is always zero,
-then using \fBpfm_get_num_events\fR you get the total number of events.
-Event descriptors are contiguous therefore a simple loop will allow
+then using the \fBpfm_get_num_events()\fR function you get the total number of events.
+On some PMU models, e.g., AMD64, not all events are necessarily supported by the host
+PMU, therefore the count returned by this calls may not be the actual number of available
+events. Event descriptors are contiguous therefore a simple loop will allow
complete scanning. The typical scan loop is constructed as
follows:
.sp
.nf
unsigned int i, count;
char name[256];
+int ret;
pfm_get_num_events(&count);
for(i=0;i < count; i++)
{
- pfm_get_event_name(i, name, 256);
+ ret = pfm_get_event_name(i, name, 256);
+ if (ret != PFMLIB_SUCCESS)
+ continue;
printf("%s\\n", name);
}
.fi
-.so
-The \fBpfm_get_num_events\fR function returns in \fBcount\fR the
-total number of events supported by the host PMU.
-.sp
-The former \fBpfm_get_first_event\fR has been deprecated. You can simply
-initialize your variable to 0 to point to the first event.
-.sp
-The former \fBpfm_get_next_event\fR has been deprecated. You need
-to retrieve the total number of events for the host PMU
-and then increment your loop variable until you reach that count.
.sp
-The \fBpfm_get_max_event_name_len\fR function returns in \fBlen\fR
+The \fBpfm_get_max_event_name_len()\fR function returns in \fBlen\fR
the maximum length in bytes for the name of the events or its unit masks, if any,
available on one PMU implementation. The value excludes the string termination
character ('\\0').
.sp
-The \fBpfm_get_event_description\fR function returns in \fBstr\fR the
+The \fBpfm_get_event_description()\fR function returns in \fBstr\fR the
description string associated with the event specified in \fBev\fR.
The description is returned into a buffer that is allocated to hold the entire
description text. It is the responsibility of the caller to free the buffer when
it becomes useless by calling the \fBfree(3)\fR function.
.sp
-The \fBpfm_get_event_mask_code\fR function must be used to retrieve the actual
+The \fBpfm_get_event_mask_code()\fR function must be used to retrieve the actual
unit mask value given a event descriptor in \fBe\fR and a unit mask descriptor
in \fBmask\fR. The value is returned in \fBcode\fR.
.sp
-The \fBpfm_get_event_mask_name\fR function must be used to retrieve the name
+The \fBpfm_get_event_mask_name()\fR function must be used to retrieve the name
associated with a unit mask specified in \fBmask\fR for event \fBe\fR. The
name is returned in the buffer specified in \fBname\fR. The maximum size
of the buffer must be specified in \fBmaxlen\fR.
.sp
-The \fBpfm_get_event_mask_description\fR function returns in \fBstr\fR the
+The \fBpfm_get_event_mask_description()\fR function returns in \fBstr\fR the
description string associated with the unit mask specified in \fBmask\fR for
the event specified in \fBev\fR. The description is returned into a buffer that
is allocated to hold the entire description text. It is the responsibility of
@@ -120,7 +127,7 @@ the string buffer provided is too small
.B PFMLIB_ERR_INVAL
the event or unit mask descriptor, or the \fBcnt\fR argument is invalid, or a pointer argument is NULL.
.SH SEE ALSO
-pfm_get_impl_counters(3), free(3)
+pfm_get_impl_counters(3), pfm_get_max_event_name_len(3), free(3)
.SH AUTHOR
-Stephane Eranian <eranian@hpl.hp.com>
+Stephane Eranian <eranian@gmail.com>
.PP
diff --git a/src/libpfm-3.y/docs/man3/pfm_get_impl_pmcs.3 b/src/libpfm-3.y/docs/man3/pfm_get_impl_pmcs.3
index dc383d96c8477e9059858f49b031379edafb7be5..f1bb21b0cacac2a9a49459c94aa8e4a7a2a1bec9 100644
--- a/src/libpfm-3.y/docs/man3/pfm_get_impl_pmcs.3
+++ b/src/libpfm-3.y/docs/man3/pfm_get_impl_pmcs.3
@@ -18,40 +18,40 @@ bitmask of implemented PMU registers or number of PMU registers
.BI "int pfm_get_hw_counter_width(unsigned int *"width ");"
.sp
.SH DESCRIPTION
-The \fBpfm_get_impl_*\fR functions can be used to figure out which
+The \fBpfm_get_impl_*()\fR functions can be used to figure out which
PMU registers are implemented on the host CPU. All implemented registers
may not necessarily be available to applications. Programs need to query
the operating system kernel monitoring interface to figure out the list
of available registers.
.sp
-The \fBpfm_get_impl_*\fR functions all return a bitmask of registers corresponding to
+The \fBpfm_get_impl_*()\fR functions all return a bitmask of registers corresponding to
the query. The bitmask pointer passed as argument is reset to zero by each function.
The returned bitmask must be accessed using the set of functions provided by the
library to ensure portability. See related man pages below.
.sp
-The \fBpfm_get_num_*\fR functions return the number of implemented PMC or PMD
+The \fBpfm_get_num_*()\fR functions return the number of implemented PMC or PMD
registers. Those numbers may be different from the actual number of registers
available to applications.
.sp
-The \fBpfm_get_impl_pmcs\fR returns in \fBimpl_pmcs\fR the bitmask of implemented PMCS.
+The \fBpfm_get_impl_pmcs()\fR function returns in \fBimpl_pmcs\fR the bitmask of implemented PMCS.
-The \fBpfm_get_impl_pmds\fR returns in \fBimpl_pmds\fR the bitmask of implemented PMDS.
+The \fBpfm_get_impl_pmds()\fR function returns in \fBimpl_pmds\fR the bitmask of implemented PMDS.
-The \fBpfm_get_impl_counters\fR returns in \fBimpl_counters\fR a bitmask of the PMD
+The \fBpfm_get_impl_counters()\fR function returns in \fBimpl_counters\fR a bitmask of the PMD
registers used as counters. Depending on the PMU mode, not all PMD registers are
necessarily used as counters.
.sp
-The \fBpfm_get_num_counters\fR function returns in \fBnum\fR the number of PMD
+The \fBpfm_get_num_counters()\fR function returns in \fBnum\fR the number of PMD
used as counters. A counter is a PMD which is used to accumulate the
number of occurrences of an event.
-The \fBpfm_get_num_pmcs\fR function returns in \fBnum\fR the number of
+The \fBpfm_get_num_pmcs()\fR function returns in \fBnum\fR the number of
implemented PMCs by the host PMU.
-The \fBpfm_get_num_pmds\fR function returns in \fBnum\fR the number of
+The \fBpfm_get_num_pmds()\fR function returns in \fBnum\fR the number of
implemented PMDs by the host PMU.
-The \fBpfm_get_hw_counter_width\fR function returns the width in bits of the
+The \fBpfm_get_hw_counter_width()\fR function returns the width in bits of the
counters in \fBwidth\fR. PMU implementations can have different number of
bits implemented. For instance, Itanium has 32-bit counters, while Itanium
2 has 47-bits.
diff --git a/src/libpfm-3.y/docs/man3/pfm_get_pmu_name.3 b/src/libpfm-3.y/docs/man3/pfm_get_pmu_name.3
index f04b8ed76724f8e4eeb0556cae63c6d2815e8e0d..5b123c6aa44a0eadc923f906a055dba0989beca5 100644
--- a/src/libpfm-3.y/docs/man3/pfm_get_pmu_name.3
+++ b/src/libpfm-3.y/docs/man3/pfm_get_pmu_name.3
@@ -22,113 +22,129 @@ a string and the former is a unique identifier. The currently
supported types are:
.TP
.B PFMLIB_GENERIC_PMU
-the default architected PMU model, i.e., the basic model.
+Intel Itanium default architected PMU model, i.e., the basic model.
.TP
.B PFMLIB_ITANIUM_PMU
-the Itanium processor PMU model. The model is found in the first
+Intel Itanium processor PMU model. The model is found in the first
implementation of the IA-64 architecture, code name Merced.
.TP
.B PFMLIB_ITANIUM2_PMU
-the Itanium 2 processor PMU model. This is the model provided
+Intel Itanium 2 processor PMU model. This is the model provided
by McKinley, Madison, and Deerfield processors.
.TP
+.B PFMLIB_MONTECITO_PMU
+Intel Dual-core Itanium 2 processor PMU model. This is the model provided
+by Montecito, Montvale processors.
+.TP
.B PFMLIB_AMD64_PMU
- the AMD64 processors (family 15 and 16)
+AMD AMD64 processors (family 15 and 16)
.TP
.B PFMLIB_GEN_IA32_PMU
- Intel architectural PMU v1 or v2
+ Intel X86 architectural PMU v1, v2, v3
.TP
.B PFMLIB_I386_P6_PMU
- Intel P6 processors. That includes Pentium Pro, Pentium II, Pentium III, but excludes Pentium M
+Intel P6 processors. That includes Pentium Pro, Pentium II, Pentium III, but excludes Pentium M
+.TP
+.B PFMLIB_I386_PM_PMU
+Intel Pentium M processors.
+.TP
+.B PFMLIB_INTEL_PII_PMU
+Intel Pentium II processors.
.TP
.B PFMLIB_PENTIUM4_PMU
- Intel processors based on Netburst micro-architecture. That includes Pentium 4.
+Intel processors based on Netburst micro-architecture. That includes Pentium 4.
.TP
.B PFMLIB_COREDUO_PMU
- Intel processors based on Yonah micro-architecture. That includes Intel Core Duo/Core Solo processors
+Intel processors based on Yonah micro-architecture. That includes Intel Core Duo/Core Solo processors
.TP
.B PFMLIB_I386_PM_PMU
- Intel Pentium M processors
+Intel Pentium M processors
.TP
.B PFMLIB_INTEL_CORE_PMU
- Intel processors based on the Core micro-architecture. That includes Intel Core 2 Duo/Quad processors
+Intel processors based on the Core micro-architecture. That includes Intel Core 2 Duo/Quad processors
+.TP
+.B PFMLIB_INTEL_ATOM_PMU
+Intel processors based on the Atom micro-architecture.
+.TP
+.B PFMLIB_INTEL_NHM_PMU
+Intel processors based on the Nehalem micro-architectures. That includes Intel Core i7 processors.
.TP
.B PFMLIB_MIPS_20KC_PMU
- MIPS 20KC processors
+MIPS 20KC processors
.TP
.B PFMLIB_MIPS_24K_PMU
- MIPS 24K processors
+MIPS 24K processors
.TP
.B PFMLIB_MIPS_25KF_PMU
- MIPS 25KF processors
+MIPS 25KF processors
.TP
.B PFMLIB_MIPS_34K_PMU
- MIPS 34K processors
+MIPS 34K processors
.TP
.B PFMLIB_MIPS_5KC_PMU
- MIPS 5KC processors
+MIPS 5KC processors
.TP
.B PFMLIB_MIPS_74K_PMU
- MIPS 74K processors
+MIPS 74K processors
.TP
.B PFMLIB_MIPS_R10000_PMU
- MIPS R10000 processors
+MIPS R10000 processors
.TP
.B PFMLIB_MIPS_R12000_PMU
- MIPS R12000 processors
+MIPS R12000 processors
.TP
.B PFMLIB_MIPS_RM7000_PMU
- MIPS RM7000 processors
+MIPS RM7000 processors
.TP
.B PFMLIB_MIPS_RM9000_PMU
- MIPS RM9000 processors
+MIPS RM9000 processors
.TP
.B PFMLIB_MIPS_SB1_PMU
- MIPS SB1/SB1A processors
+MIPS SB1/SB1A processors
.TP
.B PFMLIB_MIPS_VR5432_PMU
- MIPS VR5432 processors
+MIPS VR5432 processors
.TP
.B PFMLIB_MIPS_VR5500_PMU
- MIPS VR5500 processors
+MIPS VR5500 processors
.TP
.B PFMLIB_MIPS_ICE9A_PMU
- SiCortex ICE9A
+SiCortex ICE9A
.TP
.B PFMLIB_MIPS_ICE9B_PMU
- SiCortex ICE9B
+SiCortex ICE9B
.TP
.B PFMLIB_POWERPC_PMU
- IBM POWERPC processors
+IBM POWERPC processors
.TP
.B PFMLIB_CRAYX2_PMU
- Cray X2 processors
+Cray X2 processors
.TP
.B PFMLIB_CELL_PMU
- IBM Cell processors
+IBM Cell processors
.TP
.B PFMLIB_PPC970_PMU
- IBM PowerPC 970(FX,GX) processors
+IBM PowerPC 970(FX,GX) processors
.TP
.B PFMLIB_PPC970MP_PMU
- IBM PowerPC 970MP processors
+IBM PowerPC 970MP processors
.TP
.B PFMLIB_POWER3_PMU
- IBM POWER3 processors
+IBM POWER3 processors
.TP
.B PFMLIB_POWER4_PMU
- IBM POWER4 processors
+IBM POWER4 processors
.TP
.B PFMLIB_POWER5_PMU
- IBM POWER5 processors
+IBM POWER5 processors
.TP
.B PFMLIB_POWER5p_PMU
-IBM POWER5+ processors
+BM POWER5+ processors
.TP
.B PFMLIB_POWER6_PMU
- IBM POWER6 processors
+IBM POWER6 processors
.LP
-The \fBpfm_get_pmu_name\fR function returns the name of the detected
+The \fBpfm_get_pmu_name()\fR function returns the name of the detected
host PMU. The library must have been initialized properly before making this
call. The name is returned in the \fBname\fR argument. The \fBmaxlen\fR argument
indicates the maximum length of the buffer provided for \fBname\fR.
@@ -136,27 +152,27 @@ Up to \fBmaxlen-1\fR characters will be returned, not including the
termination character.
.sp
-The \fBpfm_get_pmu_type\fR function returns the type of the detected host
+The \fBpfm_get_pmu_type()\fR function returns the type of the detected host
PMU. The library must have been initialized properly before making this
call. The type returned in \fBtype\fR can be any one of the three listed above.
.sp
-The \fBpfm_get_pmu_name_bytype\fR function returns the name of a PMU model in
+The \fBpfm_get_pmu_name_bytype()\fR function returns the name of a PMU model in
\fBname\fR given a type in the \fBtype\fR argument. The \fBmaxlen\fR argument
indicates the maximum length of the buffer provided for \fBname\fR.
Up to \fBmaxlen-1\fR characters will be returned, not including the
termination character.
.sp
-The \fBpfm_pmu_is_supported\fR function returns \fBPFMLIB_SUCCESS\fR if the given
+The \fBpfm_pmu_is_supported()\fR function returns \fBPFMLIB_SUCCESS\fR if the given
PMU type is supported by the library independently of what the host PMU model is.
.sp
-The \fBpfm_force_pmu\fR function is used to forced the library to use a particular
+The \fBpfm_force_pmu()\fR function is used to forced the library to use a particular
PMU model compared to what it has detected. The library checks that the selected
type can be supported by the host PMU. This is mostly useful to force the
library to the use generic PMU model \fBPFMLIB_GENERIC_PMU\fR. This function can
be called at any time and upon return the library is considered initialized.
.sp
-The \fBpfm_list_supported_pmu\fR function is used to print the list PMU types
+The \fBpfm_list_supported_pmu()\fR function is used to print the list PMU types
that the library supports. The results is printed using the function provided
in the \fBpf\fR argument, which must be a printf-style function.
.SH RETURN
diff --git a/src/libpfm-3.y/docs/man3/pfm_initialize.3 b/src/libpfm-3.y/docs/man3/pfm_initialize.3
index 775210b1fedd07acf46eafe5730219d98d3ae22a..e52b20059654e23a35beae780f74eb24bc06d078 100644
--- a/src/libpfm-3.y/docs/man3/pfm_initialize.3
+++ b/src/libpfm-3.y/docs/man3/pfm_initialize.3
@@ -10,7 +10,7 @@ pfm_initialize \- initialize performance monitoring library
.SH DESCRIPTION
This is the first function that a program using the library
\fBmust\fR call otherwise the library will not function at all.
-This function probes the host PMU and intialize the internal
+This function probes the host PMU and initialize the internal
state of the library. In the case of a multi-threaded application,
this function needs to be called only once, most likely by the initial
thread.
diff --git a/src/libpfm-3.y/docs/man3/pfm_regmask_set.3 b/src/libpfm-3.y/docs/man3/pfm_regmask_set.3
index d12cacadfd4519a62f207bcc5213701c4e907729..add5a60d9dc0c6565c27d02501ec9602e5ad844d 100644
--- a/src/libpfm-3.y/docs/man3/pfm_regmask_set.3
+++ b/src/libpfm-3.y/docs/man3/pfm_regmask_set.3
@@ -18,34 +18,34 @@ pfm_regmask_eq, pfm_regmask_and, pfm_regmask_or, pfm_regmask_copy
.sp
.SH DESCRIPTION
This set of function is used to operate of the \fBpfmlib_regmask_t\fR bitmasks
-that are returned by certain functions or passed to \fBpfm_dispatch_events\fR.
+that are returned by certain functions or passed to the \fBpfm_dispatch_events()\fR function.
To ensure portability, it is important that applications use \fBonly\fR the
-functions specified here to access te bitmasks. It is strongly discouraged
+functions specified here to access the bitmasks. It is strongly discouraged
to access the internal fields of the \fBpfm_regmask_t\fR structure.
-The \fBpfm_regmask_set\fR function is used to set bit \fBb\fR in the bitmask
+The \fBpfm_regmask_set()\fR function is used to set bit \fBb\fR in the bitmask
\fBmask\fR.
-The \fBpfm_regmask_clr\fR function is used to clear bit \fBb\fR in the bitmask
+The \fBpfm_regmask_clr()\fR function is used to clear bit \fBb\fR in the bitmask
\fBmask\fR.
-The \fBpfm_regmask_isset\fR function returns a non-zero value if \fBb\fR is set
+The \fBpfm_regmask_isset()\fR function returns a non-zero value if \fBb\fR is set
in the bitmask \fBmask\fR.
-The \fBpfm_regmask_weight\fR function returns in \fBw\fR the number of bits set
+The \fBpfm_regmask_weight()\fR function returns in \fBw\fR the number of bits set
in the bitmask \fBmask\fR.
-The \fBpfm_regmask_eq\fR function returns a non-zero value if the bitmasks
+The \fBpfm_regmask_eq()\fR function returns a non-zero value if the bitmasks
\fBmask1\fR and \fBmask2\fR are identical.
-The \fBpfm_regmask_and\fR function returns in bitmask \fBdest\fR the result of
+The \fBpfm_regmask_and()\fR function returns in bitmask \fBdest\fR the result of
the logical AND operation between bitmask \fBm1\fR and bitmask \fBm2\fR.
-The \fBpfm_regmask_or\fR function returns in bitmask \fBdest\fR the result of
+The \fBpfm_regmask_or()\fR function returns in bitmask \fBdest\fR the result of
the logical OR operation between bitmask \fBm1\fR and bitmask \fBm2\fR.
-The \fBpfm_regmask_copy\fR function copies bitmask \fBsrc\fR into bitmask
+The \fBpfm_regmask_copy()\fR function copies bitmask \fBsrc\fR into bitmask
\fRdest\fR.
.SH RETURN
diff --git a/src/libpfm-3.y/docs/man3/pfm_set_options.3 b/src/libpfm-3.y/docs/man3/pfm_set_options.3
index 2afd09f39275b9c290f28731886c8be90e31e459..845e9bb41d6bd12a9534f63a60aa8b24e1d40387 100644
--- a/src/libpfm-3.y/docs/man3/pfm_set_options.3
+++ b/src/libpfm-3.y/docs/man3/pfm_set_options.3
@@ -9,13 +9,12 @@ pfm_set_options \- set performance monitoring library debug options
.sp
.SH DESCRIPTION
This function can be called at any time to adjust the level
-of debug of the library. You can adjust the verbosity
-or the debug level. In both cases, extra output will be
-generated on the standard output when the library gets
+of debug of the library. In both cases, extra output will be
+generated on standard error when the library gets
called. This can be useful to figure out how the PMC
-registers are initialized.
+registers are initialized for instance.
.sp
-The opt argument is a pointer to a
+The opt argument to this function is a pointer to a
.B pfmlib_options_t
structure which is defined as follows:
.sp
@@ -26,12 +25,31 @@ typedef struct {
} pfmlib_options_t;
.fi
.sp
+.sp
Setting \fBpfm_debug\fR to 1 will enable debug messages whereas setting
\fBpfm_verbose\fR will enable verbose messages.
+
+.SH ENVIRONMENT VARIABLES
+Setting library options with this function has lower priority than
+with environment variables. As such, the call to this function may
+not have any actual effects. A user can set the following environment
+variables to control verbosity and debug output:
+.TP
+.B LIBPFM_VERBOSE
+Enable verbose output. Value must be 0 or 1. When not set, verbosity level
+can be controlled with this function.
+.TP
+.B LIBPFM_DEBUG
+Enable debug output. Value must be 0 or 1. When not set, debug level
+can be controlled with this function.
+.LP
.SH RETURN
-The function returns whether or not it was successful.A return
+The function returns whether or not it was successful. A return
value of \fBPFMLIB_SUCCESS\fR indicates success, otherwise the
value is the error code.
+.sp
+When environment variables exist, they take precedence and this
+function returns \fBPFMLIB_SUCCESS\fR.
.SH ERRORS
.TP
.B PFMLIB_ERR_INVAL
diff --git a/src/libpfm-3.y/docs/man3/pfm_strerror.3 b/src/libpfm-3.y/docs/man3/pfm_strerror.3
index 1c11ff960669f0d04348a94296e968efa8dffdb2..dcd2234dbee704821e6d454fd528b2e6ba76967d 100644
--- a/src/libpfm-3.y/docs/man3/pfm_strerror.3
+++ b/src/libpfm-3.y/docs/man3/pfm_strerror.3
@@ -8,9 +8,13 @@ pfm_strerror \- return string describing error code
.BI "char *pfm_strerror(int "code);
.sp
.SH DESCRIPTION
-This function returns a string which describes the error
+This function returns a string which describes the libpfm error
value in \fBcode\fR. The string returned by the call must
be considered as read only.
+
+The function must \fBonly\fR be used on libpfm calls. It is not
+designed to handle OS system call errors.
+
.SH RETURN
The function returns a pointer to the string describing
the error code. If code is invalid then the default
diff --git a/src/libpfm-3.y/examples_ia64_v2.0/Makefile b/src/libpfm-3.y/examples_ia64_v2.0/Makefile
index b58a10385dc1789b66c48ad18590a4dd6f1e553f..d10a49e50a2b11015ac5b0dc88e10a37039acd0d 100644
--- a/src/libpfm-3.y/examples_ia64_v2.0/Makefile
+++ b/src/libpfm-3.y/examples_ia64_v2.0/Makefile
@@ -42,27 +42,17 @@ TARGETS=self task task_attach task_attach_timeout syst \
whichpmu showreset multiplex\
task_smpl notify_self_fork
-ifeq ($(CONFIG_PFMLIB_ITANIUM),y)
SRCS +=ita_rr.c ita_irr.c ita_opcode.c ita_btb.c ita_dear.c
TARGETS +=ita_rr ita_irr ita_opcode ita_btb ita_dear
-endif
-ifeq ($(CONFIG_PFMLIB_ITANIUM2),y)
SRCS +=ita2_opcode.c ita2_rr.c ita2_irr.c ita2_dear.c
TARGETS +=ita2_dear ita2_btb ita2_opcode ita2_rr ita2_irr
-endif
-ifeq ($(CONFIG_PFMLIB_MONTECITO),y)
SRCS +=mont_opcode.c mont_rr.c mont_irr.c mont_dear.c mont_etb.c
TARGETS +=mont_dear mont_opcode mont_rr mont_irr mont_etb
-endif
PFMLIB=$(PFMLIBDIR)/libpfm.a
-ifeq ($(ARCH),x86_64)
-TARGETS=
-endif
-
all: $(TARGETS)
notify_self2.o: notify_self2.c
@@ -81,4 +71,3 @@ depend:
#
# examples are installed as part of the RPM install, typically in /usr/share/doc/libpfm-X.Y/
#
-.PHONY: install
diff --git a/src/libpfm-3.y/examples_v2.x/Makefile b/src/libpfm-3.y/examples_v2.x/Makefile
index 8f8277c02d11fb374ce696c785898dd6715614bb..3bfb9e01fc3b36971adb928f2ff8354fa131ea53 100644
--- a/src/libpfm-3.y/examples_v2.x/Makefile
+++ b/src/libpfm-3.y/examples_v2.x/Makefile
@@ -59,7 +59,8 @@ TARGET_LINUX +=self task task_attach task_attach_timeout syst \
multiplex multiplex2 set_notify whichpmu \
showreginfo task_smpl task_smpl_user \
pfmsetup self_smpl_multi self_pipe \
- notify_self_fork
+ notify_self_fork self_smpl \
+ task_attach_timeout_np syst_np syst_multi_np
XTRA += rtop
endif
@@ -82,11 +83,12 @@ clean:
distclean: clean
install_examples: $(TARGET_LINUX) $(TARGET_GEN)
+
+install_examples:
@echo installing: $(TARGET_LINUX) $(TARGET_GEN)
- -mkdir -p $(DESTDIR)$(EXAMPLESDIR)
- $(INSTALL) -m 755 $(TARGET_LINUX) $(TARGET_GEN) $(DESTDIR)$(EXAMPLESDIR)
+ -mkdir -p $(DESTDIR)$(EXAMPLESDIR)/v2
+ $(INSTALL) -m 755 $(TARGET_LINUX) $(TARGET_GEN) $(DESTDIR)$(EXAMPLESDIR)/v2
@set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done
#
# examples are installed as part of the RPM install, typically in /usr/share/doc/libpfm-X.Y/
#
-.PHONY: install depend install_examples
diff --git a/src/libpfm-3.y/examples_v2.x/ia64/Makefile b/src/libpfm-3.y/examples_v2.x/ia64/Makefile
index 38e665ff96ed6bbe4a6b37e93eb9763614f6bfb8..860b5c96aae259dc4907099a83cedb891f9cb69f 100644
--- a/src/libpfm-3.y/examples_v2.x/ia64/Makefile
+++ b/src/libpfm-3.y/examples_v2.x/ia64/Makefile
@@ -54,6 +54,8 @@ depend:
$(MKDEP) $(CFLAGS) $(SRCS)
install_examples: $(TARGETS)
+
+install_examples:
@echo installing: $(TARGETS)
-mkdir -p $(DESTDIR)$(EXAMPLESDIR)/ia64
$(INSTALL) -m 755 $(TARGETS) $(DESTDIR)$(EXAMPLESDIR)/ia64
@@ -61,4 +63,3 @@ install_examples: $(TARGETS)
#
# examples are installed as part of the RPM install, typically in /usr/share/doc/libpfm-X.Y/
#
-.PHONY: install install_examples
diff --git a/src/libpfm-3.y/examples_v2.x/ia64/mont_dear.c b/src/libpfm-3.y/examples_v2.x/ia64/mont_dear.c
index d4f1ed376050a88777361f37d0065c49dbab36af..5bc039ff6216e2753e1fb92340bf4397913ce1fa 100644
--- a/src/libpfm-3.y/examples_v2.x/ia64/mont_dear.c
+++ b/src/libpfm-3.y/examples_v2.x/ia64/mont_dear.c
@@ -80,6 +80,7 @@ do_test(unsigned long size)
for(i=0; i<size; i++) {
array[i]=1;
}
+ free(array);
return sum;
}
diff --git a/src/libpfm-3.y/examples_v2.x/notify_self.c b/src/libpfm-3.y/examples_v2.x/notify_self.c
index 86615394a6748cb6da4a5f8da49868f9aca207c6..bf8d68a842df789300c8c518563c22e872d8a3e6 100644
--- a/src/libpfm-3.y/examples_v2.x/notify_self.c
+++ b/src/libpfm-3.y/examples_v2.x/notify_self.c
@@ -74,15 +74,12 @@ warning(char *fmt, ...)
}
static void
-sigio_handler(int n, struct siginfo *info, struct sigcontext *sc)
+sigio_handler(int n)
{
pfarg_msg_t msg;
int fd = ctx_fd;
int r;
- if (fd != ctx_fd)
- fatal_error("handler does not get valid file descriptor\n");
-
if (event1_name && pfm_read_pmds(fd, pd+1, 1) == -1)
fatal_error("pfm_read_pmds: %s", strerror(errno));
@@ -177,7 +174,7 @@ main(int argc, char **argv)
* Install the signal handler (SIGIO)
*/
memset(&act, 0, sizeof(act));
- act.sa_handler = (sig_t)sigio_handler;
+ act.sa_handler = sigio_handler;
sigaction (SIGIO, &act, 0);
memset(pc, 0, sizeof(pc));
diff --git a/src/libpfm-3.y/examples_v2.x/notify_self2.c b/src/libpfm-3.y/examples_v2.x/notify_self2.c
index d38971157c7a42e8a5ce78998dd31aa830db6001..375ef5e8f2feaa0e8ab683c59f56b423d2bf0fb9 100644
--- a/src/libpfm-3.y/examples_v2.x/notify_self2.c
+++ b/src/libpfm-3.y/examples_v2.x/notify_self2.c
@@ -89,6 +89,13 @@ sigio_handler(int n, struct siginfo *info, void *data)
fatal_error("info is NULL\n");
fd = info->si_fd;
+
+ if (info->si_code < 0)
+ fatal_error("signal not generated by kernel\n");
+
+ if (info->si_code != POLL_IN)
+ fatal_error("unexpected si_code=0x%x\n", info->si_code);
+
if (fd != ctx_fd)
fatal_error("handler does not get valid file descriptor\n");
@@ -183,8 +190,8 @@ main(int argc, char **argv)
* to get siginfo passed to handler.
*/
memset(&act, 0, sizeof(act));
- act.sa_handler = (sig_t)sigio_handler;
- act.sa_flags = SA_SIGINFO;
+ act.sa_sigaction = sigio_handler;
+ act.sa_flags = SA_SIGINFO;
sigaction (SIGIO, &act, 0);
memset(pc, 0, sizeof(pc));
diff --git a/src/libpfm-3.y/examples_v2.x/notify_self3.c b/src/libpfm-3.y/examples_v2.x/notify_self3.c
index 774a39fd8b4906dbdf96ce7af955b01564163d4a..8300b6258cdfa77f46c3edab02c701334242235a 100644
--- a/src/libpfm-3.y/examples_v2.x/notify_self3.c
+++ b/src/libpfm-3.y/examples_v2.x/notify_self3.c
@@ -64,7 +64,7 @@ fatal_error(char *fmt, ...)
}
static void
-sigio_handler(int n, struct siginfo *info, struct sigcontext *sc)
+sigio_handler(int n)
{
if (pfm_read_pmds(ctx_fd, pd+1, 1) == -1) {
fatal_error("pfm_read_pmds: %s", strerror(errno));
@@ -139,7 +139,7 @@ main(int argc, char **argv)
* Install the signal handler (SIGIO)
*/
memset(&act, 0, sizeof(act));
- act.sa_handler = (sig_t)sigio_handler;
+ act.sa_handler = sigio_handler;
sigaction (SIGIO, &act, 0);
memset(pc, 0, sizeof(pc));
diff --git a/src/libpfm-3.y/examples_v2.x/showevtinfo.c b/src/libpfm-3.y/examples_v2.x/showevtinfo.c
index 489f1b7d74fe95b8e1847b84179b8050ddf0b4cc..1cb01a5f06479913026834190894eae8d813e620 100644
--- a/src/libpfm-3.y/examples_v2.x/showevtinfo.c
+++ b/src/libpfm-3.y/examples_v2.x/showevtinfo.c
@@ -40,6 +40,18 @@ static void fatal_error(char *fmt,...) __attribute__((noreturn));
static size_t max_len;
+static struct {
+ int sort;
+ uint64_t mask;
+} options;
+
+typedef struct {
+ uint64_t code;
+ int idx;
+} code_info_t;
+
+static char *name;
+
static void
fatal_error(char *fmt, ...)
{
@@ -52,6 +64,19 @@ fatal_error(char *fmt, ...)
exit(1);
}
+int compare_codes(const void *a, const void *b)
+{
+ const code_info_t *aa = a;
+ const code_info_t *bb = b;
+ uint64_t m = options.mask;
+
+ if ((aa->code & m) < (bb->code &m))
+ return -1;
+ if ((aa->code & m) == (bb->code & m))
+ return 0;
+ return 1;
+}
+
static void
show_event_info(char *name, unsigned int idx)
{
@@ -59,6 +84,7 @@ show_event_info(char *name, unsigned int idx)
char *desc;
unsigned int n1, n2, i, c;
int code, prev_code = 0, first = 1;
+ int ret;
pfm_get_event_counters(idx, &cnt);
pfm_get_num_counters(&n2);
@@ -99,33 +125,136 @@ show_event_info(char *name, unsigned int idx)
puts("]");
pfm_get_num_event_masks(idx, &n1);
for (i = 0; i < n1; i++) {
+ ret = pfm_get_event_mask_name(idx, i, name, max_len+1);
+ if (ret != PFMLIB_SUCCESS)
+ continue;
pfm_get_event_mask_description(idx, i, &desc);
pfm_get_event_mask_code(idx, i, &c);
- pfm_get_event_mask_name(idx, i, name, max_len+1);
printf("Umask-%02u : 0x%02x : [%s] : %s\n", i, c, name, desc);
free(desc);
}
}
+static int
+show_info(regex_t *preg)
+{
+ unsigned int i, count = 0, match = 0;
+ int ret;
+
+ pfm_get_num_events(&count);
+
+ for(i=0; i < count; i++) {
+ ret = pfm_get_event_name(i, name, max_len+1);
+ /* skip unsupported events */
+ if (ret != PFMLIB_SUCCESS)
+ continue;
+
+ if (regexec(preg, name, 0, NULL, 0) == 0) {
+ show_event_info(name, i);
+ match++;
+ }
+ }
+ return match;
+}
+
+static int
+show_info_sorted(regex_t *preg)
+{
+ unsigned int i, n, count = 0, match = 0;
+ int code, ret;
+ code_info_t *codes = NULL;
+
+ pfm_get_num_events(&count);
+
+ codes = malloc(count * sizeof(*codes));
+ if (!codes)
+ fatal_error("cannot allocate memory\n");
+
+ for(i=0, n = 0; i < count; i++, n++) {
+ ret = pfm_get_event_code(i, &code);
+ /* skip unsupported events */
+ if (ret != PFMLIB_SUCCESS)
+ continue;
+
+ codes[n].idx = i;
+ codes[n].code = code;
+ }
+
+ qsort(codes, n, sizeof(*codes), compare_codes);
+
+ for(i=0; i < n; i++) {
+ ret = pfm_get_event_name(codes[i].idx, name, max_len+1);
+ /* skip unsupported events */
+ if (ret != PFMLIB_SUCCESS)
+ continue;
+
+ if (regexec(preg, name, 0, NULL, 0) == 0) {
+ show_event_info(name, codes[i].idx);
+ match++;
+ }
+ }
+ free(codes);
+ return match;
+}
+
+static void
+usage(void)
+{
+ printf("showevtinfo [-h] [-s] [-m mask]\n"
+ "-L\t\tlist one event per line\n"
+ "-h\t\tget help\n"
+ "-s\t\tsort event by PMU and by code based on -m mask\n"
+ "-m mask\t\thexadecimal event code mask, bits to match when sorting\n");
+}
+
+
+
#define MAX_PMU_NAME_LEN 32
int
main(int argc, char **argv)
{
- unsigned int i, count, match;
- char *name;
+ static char *argv_all[2] = { ".*", NULL };
+ char *endptr = NULL;
+ char **args;
+ int c, match;
regex_t preg;
char model[MAX_PMU_NAME_LEN];
+ while ((c=getopt(argc, argv,"hsm:")) != -1) {
+ switch(c) {
+ case 's':
+ options.sort = 1;
+ break;
+ case 'm':
+ options.mask = strtoull(optarg, &endptr, 16);
+ if (*endptr)
+ fatal_error("mask must be in hexadecimal\n");
+ break;
+ case 'h':
+ usage();
+ exit(0);
+ default:
+ fatal_error("unknown error");
+ }
+ }
+
if (pfm_initialize() != PFMLIB_SUCCESS)
fatal_error("PMU model not supported by library\n");
+ if (options.mask == 0)
+ options.mask = ~0;
+
+ if (optind == argc) {
+ args = argv_all;
+ } else {
+ args = argv + optind;
+ }
+
pfm_get_max_event_name_len(&max_len);
name = malloc(max_len+1);
if (name == NULL)
fatal_error("cannot allocate name buffer\n");
- pfm_get_num_events(&count);
-
if (argc == 1)
*argv = ".*"; /* match everything */
else
@@ -133,24 +262,24 @@ main(int argc, char **argv)
pfm_get_pmu_name(model, MAX_PMU_NAME_LEN);
printf("PMU model: %s\n", model);
- while(*argv) {
- if (regcomp(&preg, *argv, REG_ICASE|REG_NOSUB))
- fatal_error("error in regular expression for event \"%s\"\n", *argv);
-
- match = 0;
-
- for(i=0; i < count; i++) {
- pfm_get_event_name(i, name, max_len+1);
- if (regexec(&preg, name, 0, NULL, 0) == 0) {
- show_event_info(name, i);
- match++;
- }
- }
+
+ while(*args) {
+ if (regcomp(&preg, *args, REG_ICASE|REG_NOSUB))
+ fatal_error("error in regular expression for event \"%s\"", *argv);
+
+ if (options.sort)
+ match = show_info_sorted(&preg);
+ else
+ match = show_info(&preg);
+
if (match == 0)
- fatal_error("event %s not found\n", *argv);
+ fatal_error("event %s not found", *args);
- argv++;
+ args++;
}
+
+ regfree(&preg);
free(name);
+
return 0;
}
diff --git a/src/libpfm-3.y/examples_v2.x/task.c b/src/libpfm-3.y/examples_v2.x/task.c
index 9c975055ffac3b478ca3c229d9a1358b29cc9ce1..ae1151a926c0bf6855c7b77dd415134239e8888c 100644
--- a/src/libpfm-3.y/examples_v2.x/task.c
+++ b/src/libpfm-3.y/examples_v2.x/task.c
@@ -184,7 +184,10 @@ parent(char **arg)
/*
* and launch the child code
*/
- if (pid == 0) exit(child(arg));
+ if (pid == 0) {
+ close(ctx_fd);
+ exit(child(arg));
+ }
/*
* wait for the child to exec
diff --git a/src/libpfm-3.y/examples_v2.x/x86/Makefile b/src/libpfm-3.y/examples_v2.x/x86/Makefile
index 5200622e76ccf6f0f5577ef9911802b8f0e86347..2c312888afa3b5da129f6b8cc46429576be9cdb1 100644
--- a/src/libpfm-3.y/examples_v2.x/x86/Makefile
+++ b/src/libpfm-3.y/examples_v2.x/x86/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/rules.mk
LIBS += -lm
ifeq ($(SYS),Linux)
-TARGETS=smpl_p4_pebs smpl_core_pebs smpl_amd64_ibs
+TARGETS=smpl_p4_pebs smpl_core_pebs smpl_amd64_ibs smpl_nhm_lbr smpl_pebs
endif
all: $(TARGETS)
@@ -42,11 +42,12 @@ clean:
distclean: clean
install_examples: $(TARGETS)
+
+install_examples:
@echo installing: $(TARGETS)
- -mkdir -p $(DESTDIR)$(EXAMPLESDIR)/x86
- $(INSTALL) -m 755 $(TARGETS) $(DESTDIR)$(EXAMPLESDIR)/x86
+ -mkdir -p $(DESTDIR)$(EXAMPLESDIR)/v2/x86
+ $(INSTALL) -m 755 $(TARGETS) $(DESTDIR)$(EXAMPLESDIR)/v2/x86
#
# examples are installed as part of the RPM install, typically in /usr/share/doc/libpfm-X.Y/
#
-.PHONY: install depend install_examples
diff --git a/src/libpfm-3.y/examples_v2.x/x86/smpl_core_pebs.c b/src/libpfm-3.y/examples_v2.x/x86/smpl_core_pebs.c
index 083091b59b88dbf45306e7316223438d1bbf9899..5ebb9eefbec6e47a50f189b85765c487aa352019 100644
--- a/src/libpfm-3.y/examples_v2.x/x86/smpl_core_pebs.c
+++ b/src/libpfm-3.y/examples_v2.x/x86/smpl_core_pebs.c
@@ -47,7 +47,7 @@
#include "../detect_pmcs.h"
-#define SMPL_EVENT "INSTRUCTIONS_RETIRED" /* not all event support PEBS */
+#define SMPL_EVENT "INST_RETIRED:ANY_P" /* not all events support PEBS */
#define NUM_PMCS 16
#define NUM_PMDS 16
@@ -216,11 +216,6 @@ main(int argc, char **argv)
*/
buf_arg.cnt_reset = -SMPL_PERIOD;
- /*
- * we want to block the monitored thread when the buffer becomes full
- */
- ctx.ctx_flags = PFM_FL_NOTIFY_BLOCK;
-
/*
* trigger notification (interrupt) when reached 90% of buffer
*/
@@ -286,6 +281,8 @@ main(int argc, char **argv)
* PMC0 is the only counter useable with PEBS. We must disable
* 64-bit emulation to avoid getting interrupts for each
* sampling period, PEBS takes care of this part.
+ *
+ * This is obsolete with 2.6.30
*/
if (pc[i].reg_num == 0)
pc[i].reg_flags = PFM_REGFL_NO_EMUL64;
@@ -415,6 +412,8 @@ terminate_session:
*/
process_smpl_buf(hdr);
+ printf("collected samples %"PRIu64"n", collected_samples);
+
/*
* close context
*/
diff --git a/src/libpfm-3.y/examples_v2.x/x86/smpl_nhm_lbr.c b/src/libpfm-3.y/examples_v2.x/x86/smpl_nhm_lbr.c
index e97a569eb69e0450d85d9d37df380e987add9adb..301b3b66343381214ca8c4e350a06622efbace58 100644
--- a/src/libpfm-3.y/examples_v2.x/x86/smpl_nhm_lbr.c
+++ b/src/libpfm-3.y/examples_v2.x/x86/smpl_nhm_lbr.c
@@ -222,8 +222,8 @@ mainloop(char **arg)
inp.pfp_event_count = 1;
- mod_inp.pfm_nhm_lbr.lbr_used = 1;
- mod_inp.pfm_nhm_lbr.lbr_plm = 0; /* inherit from pfp_dfl_plm */
+ mod_inp.pfp_nhm_lbr.lbr_used = 1;
+ mod_inp.pfp_nhm_lbr.lbr_plm = 0; /* inherit from pfp_dfl_plm */
/*
* setup LBR filter
@@ -237,7 +237,7 @@ mainloop(char **arg)
*
* lbr_filter = PFM_NHM_LBR_NEAR_REL_CALL
*/
- mod_inp.pfm_nhm_lbr.lbr_filter = 0;
+ mod_inp.pfp_nhm_lbr.lbr_filter = 0;
/*
* the size of the buffer is indicated in bytes (not entries).
diff --git a/src/libpfm-3.y/include/Makefile b/src/libpfm-3.y/include/Makefile
index 8f0c4db7fbb89c2b3c9b21a8640d490c36560f9d..6d5b449101841fa36b8179616d822425e8228dee 100644
--- a/src/libpfm-3.y/include/Makefile
+++ b/src/libpfm-3.y/include/Makefile
@@ -25,9 +25,10 @@ TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi)/..
include $(TOPDIR)/config.mk
include $(TOPDIR)/rules.mk
-HEADERS=perfmon/perfmon.h \
- perfmon/perfmon_dfl_smpl.h \
+# perfmon/perfmon.h is installed below
+HEADERS=perfmon/perfmon_dfl_smpl.h \
perfmon/pfmlib.h \
+ perfmon/perfmon_v2.h \
perfmon/pfmlib_comp.h \
perfmon/pfmlib_os.h
@@ -45,14 +46,21 @@ endif
ifeq ($(CONFIG_PFMLIB_ARCH_X86_64),y)
HEADERS += perfmon/pfmlib_os_x86_64.h \
+ perfmon/pfmlib_os_i386.h \
perfmon/pfmlib_comp_x86_64.h \
+ perfmon/pfmlib_comp_i386.h \
perfmon/perfmon_x86_64.h \
perfmon/perfmon_i386.h \
+ perfmon/pfmlib_i386_p6.h \
perfmon/perfmon_pebs_p4_smpl.h \
perfmon/perfmon_pebs_core_smpl.h \
+ perfmon/perfmon_pebs_smpl.h \
perfmon/pfmlib_amd64.h \
perfmon/pfmlib_pentium4.h \
perfmon/pfmlib_core.h \
+ perfmon/pfmlib_coreduo.h \
+ perfmon/pfmlib_intel_atom.h \
+ perfmon/pfmlib_intel_nhm.h \
perfmon/pfmlib_gen_ia32.h
endif
@@ -61,18 +69,23 @@ ifeq ($(CONFIG_PFMLIB_ARCH_I386),y)
HEADERS += perfmon/pfmlib_os_i386.h \
perfmon/pfmlib_comp_i386.h \
perfmon/perfmon_i386.h \
- perfmon/perfmon_pebs_p4_smpl.h \
- perfmon/perfmon_pebs_core_smpl.h \
+ perfmon/perfmon_pebs_p4_smpl.h \
+ perfmon/perfmon_pebs_core_smpl.h \
+ perfmon/perfmon_pebs_smpl.h \
perfmon/pfmlib_amd64.h \
perfmon/pfmlib_pentium4.h \
perfmon/pfmlib_core.h \
+ perfmon/pfmlib_coreduo.h \
+ perfmon/pfmlib_intel_atom.h \
+ perfmon/pfmlib_intel_nhm.h \
perfmon/pfmlib_i386_p6.h \
perfmon/pfmlib_gen_ia32.h
endif
ifeq ($(CONFIG_PFMLIB_ARCH_POWERPC),y)
-HEADERS += perfmon/pfmlib_os_powerpc.h \
+HEADERS += perfmon/pfmlib_cell.h \
+ perfmon/pfmlib_os_powerpc.h \
perfmon/pfmlib_comp_powerpc.h \
perfmon/perfmon_powerpc.h \
perfmon/pfmlib_powerpc.h
@@ -89,7 +102,8 @@ ifeq ($(CONFIG_PFMLIB_ARCH_MIPS64),y)
HEADERS += perfmon/pfmlib_os_mips64.h \
perfmon/pfmlib_comp_mips64.h \
perfmon/perfmon_mips64.h \
- perfmon/pfmlib_gen_mips64.h
+ perfmon/pfmlib_gen_mips64.h \
+ perfmon/pfmlib_sicortex.h
endif
ifeq ($(CONFIG_PFMLIB_ARCH_CRAYX2),y)
@@ -99,15 +113,25 @@ HEADERS += perfmon/pfmlib_os_crayx2.h \
perfmon/pfmlib_crayx2.h
endif
-ifeq ($(CONFIG_PFMLIB_CELL),y)
-HEADERS += perfmon/pfmlib_cell.h \
- perfmon/pfmlib_comp_powerpc.h \
- perfmon/pfmlib_os_powerpc.h \
- perfmon/perfmon_powerpc.h
+.PHONY: perfmon.h dir
+
+perfmon.h: dir
+
+perfmon.h:
+ifeq ($(CONFIG_PFMLIB_OLD_PFMV2),y)
+ echo "#ifndef PFMLIB_OLD_PFMV2" > $(DESTDIR)$(INCDIR)/perfmon/perfmon.h
+ echo "#define PFMLIB_OLD_PFMV2" >> $(DESTDIR)$(INCDIR)/perfmon/perfmon.h
+ echo "#endif" >> $(DESTDIR)$(INCDIR)/perfmon/perfmon.h
+ cat perfmon/perfmon.h >> $(DESTDIR)$(INCDIR)/perfmon/perfmon.h
+ chmod 644 $(DESTDIR)$(INCDIR)/perfmon/perfmon.h
+else
+ $(INSTALL) -m 644 perfmon/perfmon.h $(DESTDIR)$(INCDIR)/perfmon
endif
-.PHONY: all clean distclean depend
+dir:
+ mkdir -p $(DESTDIR)$(INCDIR)/perfmon
+
+install: dir perfmon.h $(HEADERS)
install:
- -mkdir -p $(DESTDIR)$(INCDIR)/perfmon
$(INSTALL) -m 644 $(HEADERS) $(DESTDIR)$(INCDIR)/perfmon
diff --git a/src/libpfm-3.y/include/perfmon/perfmon.h b/src/libpfm-3.y/include/perfmon/perfmon.h
index 643be644a5096f98f0497eea1c1d2eb27c364385..db17dff12ad68e1002737863f8e748671c0006f8 100644
--- a/src/libpfm-3.y/include/perfmon/perfmon.h
+++ b/src/libpfm-3.y/include/perfmon/perfmon.h
@@ -1,6 +1,8 @@
/*
* This file contains the user level interface description for
- * the perfmon-2.x interface on Linux.
+ * the perfmon3.x interface on Linux.
+ *
+ * It also includes perfmon2.x interface definitions.
*
* Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P.
* Contributed by Stephane Eranian <eranian@hpl.hp.com>
@@ -10,11 +12,11 @@
#include <sys/types.h>
#include <stdint.h>
-#include <syscall.h>
#ifdef __cplusplus
extern "C" {
#endif
+
#ifdef __ia64__
#include <perfmon/perfmon_ia64.h>
#endif
@@ -27,11 +29,7 @@ extern "C" {
#include <perfmon/perfmon_i386.h>
#endif
-#ifdef __powerpc__
-#include <perfmon/perfmon_powerpc.h>
-#endif
-
-#ifdef __cell__
+#if defined(__powerpc__) || defined(__cell__)
#include <perfmon/perfmon_powerpc.h>
#endif
@@ -50,6 +48,7 @@ extern "C" {
#define PFM_MAX_PMCS PFM_ARCH_MAX_PMCS
#define PFM_MAX_PMDS PFM_ARCH_MAX_PMDS
+#ifndef SWIG
/*
* number of element for each type of bitvector
*/
@@ -57,288 +56,165 @@ extern "C" {
#define PFM_BVSIZE(x) (((x)+PFM_BPL-1) / PFM_BPL)
#define PFM_PMD_BV PFM_BVSIZE(PFM_MAX_PMDS)
#define PFM_PMC_BV PFM_BVSIZE(PFM_MAX_PMCS)
+#endif
/*
- * PMC/PMD flags to use with pfm_write_pmds() or pfm_write_pmcs()
- *
- * reg_flags layout:
- * bit 00-15 : generic flags
- * bit 16-23 : arch-specific flags
- * bit 24-31 : error codes
- */
-#define PFM_REGFL_OVFL_NOTIFY 0x1 /* PMD: send notification on overflow */
-#define PFM_REGFL_RANDOM 0x2 /* PMD: randomize sampling interval */
-#define PFM_REGFL_NO_EMUL64 0x4 /* PMC: no 64-bit emulation for counter */
-
-/*
- * generic event set flags
+ * special data type for syscall error value used to help
+ * with Python support and in particular for SWIG. By using
+ * a specific type we can detect syscalls and trap errors
+ * in one SWIG statement as opposed to having to keep track of
+ * each syscall individually. Programs can use 'int' safely for
+ * the return value.
*/
-#define PFM_SETFL_OVFL_SWITCH 0x01 /* enable switch on overflow (subject to individual switch_cnt */
-#define PFM_SETFL_TIME_SWITCH 0x02 /* switch set on timeout */
+typedef int os_err_t; /* error if -1 */
/*
- * argument to pfm_create_context()
+ * passed to pfm_create
+ * contains list of available register upon return
*/
-#ifndef PFMLIB_VERSION_22
typedef struct {
- uint32_t ctx_flags; /* noblock/block/syswide */
- uint32_t ctx_reserved1; /* for future use */
- uint64_t ctx_reserved3[7]; /* for future use */
-} pfarg_ctx_t;
-#endif
+ uint64_t sif_avail_pmcs[PFM_PMC_BV]; /* out: available PMCs */
+ uint64_t sif_avail_pmds[PFM_PMD_BV]; /* out: available PMDs */
+ uint64_t sif_reserved[4];
+} pfarg_sinfo_t;
+
+//os_err_t pfm_create(int flags, pfarg_sinfo_t *sif,
+// char *smpl_name, void *smpl_arg, size_t arg_size);
+extern os_err_t pfm_create(int flags, pfarg_sinfo_t *sif, ...);
+
/*
- * context flags (ctx_flags)
- *
+ * pfm_create flags:
+ * bits[00-15]: generic flags
+ * bits[16-31]: arch-specific flags (see perfmon_const.h)
*/
-#define PFM_FL_NOTIFY_BLOCK 0x01 /* block task on user notifications */
-#define PFM_FL_SYSTEM_WIDE 0x02 /* create a system wide context */
-#define PFM_FL_OVFL_NO_MSG 0x80 /* no overflow msgs */
+#define PFM_FL_NOTIFY_BLOCK 0x01 /* block task on user notifications */
+#define PFM_FL_SYSTEM_WIDE 0x02 /* create a system wide context */
+#define PFM_FL_SMPL_FMT 0x04 /* session uses sampling format */
+#define PFM_FL_OVFL_NO_MSG 0x80 /* no overflow msgs */
/*
- * argument for pfm_write_pmcs()
+ * PMC and PMD generic (simplified) register description
*/
typedef struct {
- uint16_t reg_num; /* which register */
- uint16_t reg_set; /* event set for this register */
- uint32_t reg_flags; /* REGFL flags */
- uint64_t reg_value; /* pmc value */
- uint64_t reg_reserved2[4]; /* for future use */
-} pfarg_pmc_t;
+ uint16_t reg_num; /* which register */
+ uint16_t reg_set; /* which event set */
+ uint32_t reg_flags; /* REGFL flags */
+ uint64_t reg_value; /* 64-bit value */
+} pfarg_pmr_t;
/*
- * argument pfm_write_pmds() and pfm_read_pmds()
+ * pfarg_pmr_t flags:
+ * bit[00-15] : generic flags
+ * bit[16-31] : arch-specific flags
+ *
+ * PFM_REGFL_NO_EMUL64: must be set on the PMC controlling the PMD
+ */
+#define PFM_REGFL_OVFL_NOTIFY 0x1 /* PMD: send notification on event */
+#define PFM_REGFL_RANDOM 0x2 /* PMD: randomize value after event */
+#define PFM_REGFL_NO_EMUL64 0x4 /* PMC: no 64-bit emulation */
+
+/*
+ * PMD extended description
+ * to be used with pfm_writeand pfm_read
+ * must be used with type = PFM_RW_PMD_ATTR
*/
typedef struct {
- uint16_t reg_num; /* which register */
- uint16_t reg_set; /* event set for this register */
- uint32_t reg_flags; /* REGFL flags */
- uint64_t reg_value; /* initial pmc/pmd value */
- uint64_t reg_long_reset; /* reset after buffer overflow notification */
- uint64_t reg_short_reset; /* reset after counter overflow */
- uint64_t reg_last_reset_val; /* return: PMD last reset value */
- uint64_t reg_ovfl_switch_cnt; /* how many overflow before switch for next set */
- uint64_t reg_reset_pmds[PFM_PMD_BV]; /* which other PMDS to reset on overflow */
- uint64_t reg_smpl_pmds[PFM_PMD_BV]; /* which other PMDS to record when the associated PMD overflows */
- uint64_t reg_smpl_eventid; /* opaque sampling event identifier */
- uint64_t reg_random_mask; /* bitmask used to limit random value */
- uint32_t reg_random_seed; /* seed for randomization (DEPRECATED) */
- uint32_t reg_reserved2[7]; /* for future use */
-} pfarg_pmd_t;
+ uint16_t reg_num; /* which register */
+ uint16_t reg_set; /* which event set */
+ uint32_t reg_flags; /* REGFL flags */
+ uint64_t reg_value; /* 64-bit value */
+ uint64_t reg_long_reset; /* write: value to reload after notification */
+ uint64_t reg_short_reset; /* write: reset after counter overflow */
+ uint64_t reg_random_mask; /* write: bitmask used to limit random value */
+ uint64_t reg_smpl_pmds[PFM_PMD_BV]; /* write: record in sample */
+ uint64_t reg_reset_pmds[PFM_PMD_BV]; /* write: reset on overflow */
+ uint64_t reg_ovfl_swcnt; /* write: # overflows before switch */
+ uint64_t reg_smpl_eventid; /* write: opaque event identifier */
+ uint64_t reg_last_value; /* read: PMD last reset value */
+ uint64_t reg_reserved[8]; /* for future use */
+} pfarg_pmd_attr_t;
+
/*
- * optional argument to pfm_start(), pass NULL if no arg needed
+ * pfm_write, pfm_read type:
*/
-typedef struct {
- uint16_t start_set; /* event set to start with */
- uint16_t start_reserved1; /* for future use */
- uint32_t start_reserved2; /* for future use */
- uint64_t reserved3[3]; /* for future use */
-} pfarg_start_t;
+#define PFM_RW_PMD 1 /* simplified PMD (pfarg_pmr_t) */
+#define PFM_RW_PMC 2 /* PMC registers (pfarg_pmr_t) */
+#define PFM_RW_PMD_ATTR 3 /* extended PMD (pfarg_pmd_attr) */
/*
- * argument to pfm_load_context()
+ * pfm_attach special target for detach
*/
-typedef struct {
- uint32_t load_pid; /* thread or CPU to attach to */
- uint16_t load_set; /* set to load first */
- uint16_t load_reserved1; /* for future use */
- uint64_t load_reserved2[3]; /* for future use */
-} pfarg_load_t;
+#define PFM_NO_TARGET -1 /* no target, detach */
+
/*
- * argument to pfm_create_evtsets()/pfm_delete_evtsets()
+ * pfm_set_state state:
*/
-#ifndef PFMLIB_VERSION_22
+#define PFM_ST_START 0x1 /* start monitoring */
+#define PFM_ST_STOP 0x2 /* stop monitoring */
+#define PFM_ST_RESTART 0x3 /* resume after notify */
+
+#ifndef PFMLIB_OLD_PFMV2
typedef struct {
uint16_t set_id; /* which set */
uint16_t set_reserved1; /* for future use */
uint32_t set_flags; /* SETFL flags */
uint64_t set_timeout; /* requested/effective switch timeout in nsecs */
uint64_t reserved[6]; /* for future use */
-} pfarg_setdesc_t;
-#endif
+} pfarg_set_desc_t;
-/*
- * argument to pfm_getinfo_evtsets()
- */
-#ifndef PFMLIB_VERSION_22
typedef struct {
uint16_t set_id; /* which set */
uint16_t set_reserved1; /* for future use */
- uint32_t set_flags; /* output: SETFL flags */
- uint64_t set_ovfl_pmds[PFM_PMD_BV]; /* output: last ovfl PMDs which triggered a switch from set */
- uint64_t set_runs; /* output: number of times the set was active */
- uint64_t set_timeout; /* output:effective/leftover switch timeout in nsecs */
- uint64_t set_act_duration; /* output: time set was active in nsecs */
- uint64_t set_avail_pmcs[PFM_PMC_BV];
- uint64_t set_avail_pmds[PFM_PMD_BV];
- uint64_t set_reserved3[6]; /* for future use */
-} pfarg_setinfo_t;
-
-typedef struct {
- uint32_t msg_type; /* PFM_MSG_OVFL */
- uint32_t msg_ovfl_pid; /* process id */
- uint16_t msg_active_set; /* active set at the time of overflow */
- uint16_t msg_ovfl_cpu; /* cpu on which the overflow occurred */
- uint32_t msg_ovfl_tid; /* thread id */
- uint64_t msg_ovfl_ip; /* instruction pointer where overflow interrupt happened */
- uint64_t msg_ovfl_pmds[PFM_PMD_BV];/* which PMDs overflowed */
-} pfarg_ovfl_msg_t;
-
+ uint32_t set_reserved2; /* for future use */
+ uint64_t set_ovfl_pmds[PFM_PMD_BV]; /* out: last ovfl PMDs */
+ uint64_t set_runs; /* out: #times set was active */
+ uint64_t set_timeout; /* out: leftover switch timeout (nsecs) */
+ uint64_t set_duration; /* out: time set was active (nsecs) */
+ uint64_t set_reserved3[4]; /* for future use */
+} pfarg_set_info_t;
#endif
-#define PFM_MSG_OVFL 1 /* an overflow happened */
-#define PFM_MSG_END 2 /* task to which context was attached ended */
-
/*
- * perfmon version number
+ * pfm_set_desc_t flags:
*/
-#define PFM_VERSION_MAJ 2U
-
-#ifndef PFMLIB_VERSION_22
-#define PFM_VERSION_MIN 7U
-#endif
-
-#define PFM_VERSION (((PFM_VERSION_MAJ&0xffff)<<16)|(PFM_VERSION_MIN & 0xffff))
-#define PFM_VERSION_MAJOR(x) (((x)>>16) & 0xffff)
-#define PFM_VERSION_MINOR(x) ((x) & 0xffff)
-
-/*
- * for backward compatibility with old code (to go away)
- */
-#ifdef PFMLIB_VERSION_22
-typedef struct {
- uint16_t set_id; /* which set */
- uint16_t set_id_next; /* next set to go to (must use PFM_SETFL_EXPL_NEXT) */
- uint32_t set_flags; /* SETFL flags */
- uint64_t set_timeout; /* requested/effective switch timeout in nsecs */
- uint64_t set_mmap_offset; /* cookie to pass as mmap offset to access 64-bit virtual PMD */
- uint64_t reserved[5]; /* for future use */
- } pfarg_setdesc_t;
-
-typedef struct {
- unsigned char ctx_smpl_buf_id[16]; /* which buffer format to use */
- uint32_t ctx_flags; /* noblock/block/syswide */
- int32_t ctx_fd; /* ret arg: fd for context */
- uint64_t ctx_smpl_buf_size; /* ret arg: actual buffer sz */
- uint64_t ctx_reserved3[12]; /* for future use */
-} pfarg_ctx_t;
-
-typedef struct {
- uint16_t set_id; /* which set */
- uint16_t set_id_next; /* output: next set to go to (must use PFM_SETFL_EXPL_NEXT) */
- uint32_t set_flags; /* output: SETFL flags */
- uint64_t set_ovfl_pmds[PFM_PMD_BV]; /* output: last ovfl PMDs which triggered a switch from set */
- uint64_t set_runs; /* output: number of times the set was active */
- uint64_t set_timeout; /* output:effective/leftover switch timeout in nsecs */
- uint64_t set_act_duration; /* number of cycles set was active (syswide only) */
- uint64_t set_mmap_offset; /* cookie to pass as mmap offset to access 64-bit virtual PMD */
- uint64_t set_avail_pmcs[PFM_PMC_BV];
- uint64_t set_avail_pmds[PFM_PMD_BV];
- uint64_t reserved[4]; /* for future use */
-} pfarg_setinfo_t;
-
-#ifdef __crayx2
-#define PFM_MAX_HW_PMDS 512
-#else
-#define PFM_MAX_HW_PMDS 256
-#endif
-#define PFM_HW_PMD_BV PFM_BVSIZE(PFM_MAX_HW_PMDS)
+#define PFM_SETFL_OVFL_SWITCH 0x01 /* enable switch on overflow (subject to individual switch_cnt */
+#define PFM_SETFL_TIME_SWITCH 0x02 /* switch set on timeout */
+#ifndef PFMLIB_OLD_PFMV2
typedef struct {
uint32_t msg_type; /* PFM_MSG_OVFL */
uint32_t msg_ovfl_pid; /* process id */
- uint64_t msg_ovfl_pmds[PFM_HW_PMD_BV];/* which PMDs overflowed */
uint16_t msg_active_set; /* active set at the time of overflow */
uint16_t msg_ovfl_cpu; /* cpu on which the overflow occurred */
uint32_t msg_ovfl_tid; /* thread id */
uint64_t msg_ovfl_ip; /* instruction pointer where overflow interrupt happened */
+ uint64_t msg_ovfl_pmds[PFM_PMD_BV];/* which PMDs overflowed */
} pfarg_ovfl_msg_t;
-#define PFM_VERSION_MIN 2U /* minior version number */
+extern os_err_t pfm_write(int fd, int flags, int type, void *reg, size_t n);
+extern os_err_t pfm_read(int fd, int flags, int type, void *reg, size_t n);
+extern os_err_t pfm_set_state(int fd, int flags, int state);
+extern os_err_t pfm_create_sets(int fd, int flags, pfarg_set_desc_t *s, size_t sz);
+extern os_err_t pfm_getinfo_sets(int fd, int flags, pfarg_set_info_t *s, size_t sz);
+extern os_err_t pfm_attach(int fd, int flags, int target);
+
#endif
+#include "perfmon_v2.h"
+
typedef union {
uint32_t type;
- pfarg_ovfl_msg_t pfm_ovfl_msg;
+ pfarg_ovfl_msg_t pfm_ovfl_msg;
} pfarg_msg_t;
-extern int pfm_create_context(pfarg_ctx_t *ctx, char *smpl_name, void *smpl_arg, size_t smpl_size);
-extern int pfm_write_pmcs(int fd, pfarg_pmc_t *pmcs, int count);
-extern int pfm_write_pmds(int fd, pfarg_pmd_t *pmds, int count);
-extern int pfm_read_pmds(int fd, pfarg_pmd_t *pmds, int count);
-extern int pfm_load_context(int fd, pfarg_load_t *load);
-extern int pfm_start(int fd, pfarg_start_t *start);
-extern int pfm_stop(int fd);
-extern int pfm_restart(int fd);
-extern int pfm_create_evtsets(int fd, pfarg_setdesc_t *setd, int count);
-extern int pfm_getinfo_evtsets(int fd, pfarg_setinfo_t *info, int count);
-extern int pfm_delete_evtsets(int fd, pfarg_setdesc_t *setd, int count);
-extern int pfm_unload_context(int fd);
-
-/*
- * until the syscall stubs are implemented by glibc
- * we define them here
- */
-#ifndef __NR_pfm_create_context
-#ifdef __x86_64__
-#ifdef CONFIG_PFMLIB_ARCH_CRAYXT
-#define __NR_pfm_create_context 273
-#else
-#define __NR_pfm_create_context 286
-#endif
-#endif /* __x86_64__ */
-
-#ifdef __i386__
-#define __NR_pfm_create_context 325
-#endif
-
-#ifdef __ia64__
-#define __NR_pfm_create_context 1310
-#endif
-
-#if defined(__mips__)
-#if (_MIPS_SIM == _ABIN32) || (_MIPS_SIM == _MIPS_SIM_NABI32)
-#define __NR_Linux 6000
-#define __NR_pfm_create_context __NR_Linux+280
-#elif (_MIPS_SIM == _ABI32) || (_MIPS_SIM == _MIPS_SIM_ABI32)
-#define __NR_Linux 4000
-#define __NR_pfm_create_context __NR_Linux+321
-#elif (_MIPS_SIM == _ABI64) || (_MIPS_SIM == _MIPS_SIM_ABI64)
-#define __NR_Linux 5000
-#define __NR_pfm_create_context __NR_Linux+284
-#endif
-#endif
-
-#ifdef __powerpc__
-#define __NR_pfm_create_context 310
-#endif
-
-#ifdef __sparc__
-#define __NR_pfm_create_context 315
-#endif
-
-#ifdef __cell__
-#define __NR_pfm_create_context 309
-#endif
-
-#ifdef __crayx2
-#define __NR_pfm_create_context 294
-#endif
+#define PFM_MSG_OVFL 1 /* an overflow happened */
+#define PFM_MSG_END 2 /* thread to which context was attached ended */
-#define __NR_pfm_write_pmcs (__NR_pfm_create_context+1)
-#define __NR_pfm_write_pmds (__NR_pfm_create_context+2)
-#define __NR_pfm_read_pmds (__NR_pfm_create_context+3)
-#define __NR_pfm_load_context (__NR_pfm_create_context+4)
-#define __NR_pfm_start (__NR_pfm_create_context+5)
-#define __NR_pfm_stop (__NR_pfm_create_context+6)
-#define __NR_pfm_restart (__NR_pfm_create_context+7)
-#define __NR_pfm_create_evtsets (__NR_pfm_create_context+8)
-#define __NR_pfm_getinfo_evtsets (__NR_pfm_create_context+9)
-#define __NR_pfm_delete_evtsets (__NR_pfm_create_context+10)
-#define __NR_pfm_unload_context (__NR_pfm_create_context+11)
-#endif /* __NR_pfm_create_context */
+#define PFM_VERSION_MAJOR(x) (((x)>>16) & 0xffff)
+#define PFM_VERSION_MINOR(x) ((x) & 0xffff)
#ifdef __cplusplus
};
diff --git a/src/libpfm-3.y/include/perfmon/perfmon_dfl_smpl.h b/src/libpfm-3.y/include/perfmon/perfmon_dfl_smpl.h
index bcc340c56d465de85ecfd2484da933da5aadee7c..e24fd095a6edcbb08aab114c3f61de83f91f9e5c 100644
--- a/src/libpfm-3.y/include/perfmon/perfmon_dfl_smpl.h
+++ b/src/libpfm-3.y/include/perfmon/perfmon_dfl_smpl.h
@@ -20,7 +20,7 @@ extern "C" {
#define PFM_DFL_SMPL_NAME "default"
-#ifdef PFMLIB_VERSION_22
+#ifdef PFMLIB_OLD_PFMV2
/*
* UUID for compatibility with perfmon v2.2 (used by Cray)
*/
diff --git a/src/libpfm-3.y/include/perfmon/perfmon_pebs_core_smpl.h b/src/libpfm-3.y/include/perfmon/perfmon_pebs_core_smpl.h
index 677bfd9a2715272de22315ccf40675f51888b124..f68f62568e707a3137646a9e9bd0e7ec49940dc6 100644
--- a/src/libpfm-3.y/include/perfmon/perfmon_pebs_core_smpl.h
+++ b/src/libpfm-3.y/include/perfmon/perfmon_pebs_core_smpl.h
@@ -4,7 +4,7 @@
*
* This file implements the sampling format to support Intel
* Precise Event Based Sampling (PEBS) feature of Intel
- * Core-based processors.
+ * Core and Atom processors.
*
* What is PEBS?
* ------------
@@ -65,8 +65,8 @@ extern "C" {
*/
typedef struct {
uint64_t cnt_reset; /* counter reset value */
- size_t buf_size; /* size of the buffer in bytes */
- size_t intr_thres; /* index of interrupt threshold entry */
+ uint64_t buf_size; /* size of the buffer in bytes */
+ uint64_t intr_thres; /* index of interrupt threshold entry */
uint64_t reserved[6]; /* for future use */
} pfm_pebs_core_smpl_arg_t;
diff --git a/src/libpfm-3.y/include/perfmon/pfmlib_cell.h b/src/libpfm-3.y/include/perfmon/pfmlib_cell.h
index f11d33d9ae3a00d410d51f4815d8e87fd1ee9d1b..f35aca2f190fecc04c6611bf7a365f958b4ac7e1 100644
--- a/src/libpfm-3.y/include/perfmon/pfmlib_cell.h
+++ b/src/libpfm-3.y/include/perfmon/pfmlib_cell.h
@@ -55,4 +55,6 @@ typedef struct {
uint64_t reserved[8]; /* for future use */
} pfmlib_cell_output_param_t;
+int pfm_cell_spe_event(unsigned int event_index);
+
#endif /* __PFMLIB_CELL_H__ */
diff --git a/src/libpfm-3.y/include/perfmon/pfmlib_crayx2.h b/src/libpfm-3.y/include/perfmon/pfmlib_crayx2.h
index abc657b33a20857ca1ac355d6dc1fa34ce3261d0..60284b9af6ca1cab65939e60b29558692c8467a0 100644
--- a/src/libpfm-3.y/include/perfmon/pfmlib_crayx2.h
+++ b/src/libpfm-3.y/include/perfmon/pfmlib_crayx2.h
@@ -24,10 +24,23 @@
#ifndef __PFMLIB_CRAYX2_H__
#define __PFMLIB_CRAYX2_H__ 1
+/*
+ * Allows <asm/perfmon.h> to be included on its own.
+ */
+#define PFM_MAX_HW_PMCS 12
+#define PFM_MAX_HW_PMDS 512
#include <asm/perfmon.h>
#include <sys/types.h>
+/* Priviledge level mask for Cray-X2:
+ *
+ * PFM_PLM0 = Kernel
+ * PFM_PLM1 = Kernel
+ * PFM_PLM2 = Exception
+ * PFM_PLM3 = User
+ */
+
/* The performance control (PMC) registers appear as follows:
* PMC0 control for CPU chip
* PMC1 events on CPU chip
diff --git a/src/libpfm-3.y/include/perfmon/pfmlib_gen_ia32.h b/src/libpfm-3.y/include/perfmon/pfmlib_gen_ia32.h
index 2dd819c3aa2171b0040320e74be2f48d7aa90ef1..7ae2bfcc30a5e09c99357383526094b1695497e7 100644
--- a/src/libpfm-3.y/include/perfmon/pfmlib_gen_ia32.h
+++ b/src/libpfm-3.y/include/perfmon/pfmlib_gen_ia32.h
@@ -1,5 +1,5 @@
/*
- * Intel architectural PMU v1
+ * Intel architectural PMU v1, v2, v3
*
* Copyright (c) 2006-2007 Hewlett-Packard Development Company, L.P.
* Contributed by Stephane Eranian <eranian@hpl.hp.com>
@@ -61,7 +61,7 @@ typedef union {
unsigned long sel_edge:1; /* edge detec */
unsigned long sel_pc:1; /* pin control */
unsigned long sel_int:1; /* enable APIC intr */
- unsigned long sel_res1:1; /* reserved */
+ unsigned long sel_any:1; /* any thread (v3) */
unsigned long sel_en:1; /* enable */
unsigned long sel_inv:1; /* invert counter mask */
unsigned long sel_cnt_mask:8; /* counter mask */
@@ -76,6 +76,7 @@ typedef struct {
#define PFM_GEN_IA32_SEL_INV 0x1 /* inverse */
#define PFM_GEN_IA32_SEL_EDGE 0x2 /* edge detect */
+#define PFM_GEN_IA32_SEL_ANYTHR 0x4 /* measure on any thread (v3 and up) */
/*
* model-specific parameters for the library
diff --git a/src/libpfm-3.y/include/perfmon/pfmlib_gen_mips64.h b/src/libpfm-3.y/include/perfmon/pfmlib_gen_mips64.h
index eaa7e5f9aaeea92bc663e5fe996f87500fdf3092..7afc754158a452db80ef6dfbefa7c98fc82521bd 100644
--- a/src/libpfm-3.y/include/perfmon/pfmlib_gen_mips64.h
+++ b/src/libpfm-3.y/include/perfmon/pfmlib_gen_mips64.h
@@ -61,8 +61,8 @@ typedef union {
unsigned long sel_sup:1; /* supervisor level */
unsigned long sel_usr:1; /* user level */
unsigned long sel_int:1; /* enable intr */
- unsigned long sel_event_mask:4; /* event mask */
- unsigned long sel_res1:23; /* reserved */
+ unsigned long sel_event_mask:5; /* event mask */
+ unsigned long sel_res1:22; /* reserved */
unsigned long sel_res2:32; /* reserved */
} perfsel;
} pfm_gen_mips64_sel_reg_t;
@@ -73,8 +73,8 @@ typedef union {
uint64_t val; /* complete register value */
struct {
unsigned long sel_res2:32; /* reserved */
- unsigned long sel_res1:23; /* reserved */
- unsigned long sel_event_mask:4; /* event mask */
+ unsigned long sel_res1:22; /* reserved */
+ unsigned long sel_event_mask:5; /* event mask */
unsigned long sel_int:1; /* enable intr */
unsigned long sel_usr:1; /* user level */
unsigned long sel_sup:1; /* supervisor level */
diff --git a/src/libpfm-3.y/include/perfmon/pfmlib_intel_nhm.h b/src/libpfm-3.y/include/perfmon/pfmlib_intel_nhm.h
index 83ceb13ac4540143cd11cc098390a4e0cf21a842..ad3b41688d58ca1124060ebacca1079e36b172bd 100644
--- a/src/libpfm-3.y/include/perfmon/pfmlib_intel_nhm.h
+++ b/src/libpfm-3.y/include/perfmon/pfmlib_intel_nhm.h
@@ -139,7 +139,7 @@ typedef struct {
typedef struct {
pfmlib_nhm_counter_t pfp_nhm_counters[PMU_NHM_NUM_COUNTERS];
pfmlib_nhm_pebs_t pfp_nhm_pebs; /* PEBS settings */
- pfmlib_nhm_lbr_t pfm_nhm_lbr; /* LBR settings */
+ pfmlib_nhm_lbr_t pfp_nhm_lbr; /* LBR settings */
uint64_t reserved[4]; /* for future use */
} pfmlib_nhm_input_param_t;
diff --git a/src/libpfm-3.y/include/perfmon/pfmlib_os.h b/src/libpfm-3.y/include/perfmon/pfmlib_os.h
index a32a4bb8849746a500fd6fec352485c2dba82ecc..efb115e5121abdf7493f9fceb3590e54eb9b6204 100644
--- a/src/libpfm-3.y/include/perfmon/pfmlib_os.h
+++ b/src/libpfm-3.y/include/perfmon/pfmlib_os.h
@@ -22,6 +22,7 @@
#ifndef __PFMLIB_OS_H__
#define __PFMLIB_OS_H__
+#ifdef __linux__
#ifdef __ia64__
#include <perfmon/pfmlib_os_ia64.h>
#endif
@@ -53,5 +54,5 @@
#ifdef __crayx2
#include <perfmon/pfmlib_os_crayx2.h>
#endif
-
+#endif /* __linux__ */
#endif /* __PFMLIB_OS_H__ */
diff --git a/src/libpfm-3.y/lib/Makefile b/src/libpfm-3.y/lib/Makefile
index c51745e2f2c872f9a2fc697a893c1f5c56d93a3c..b20a50d9d3c46045f7ae561a7302d99d1251589f 100644
--- a/src/libpfm-3.y/lib/Makefile
+++ b/src/libpfm-3.y/lib/Makefile
@@ -24,63 +24,78 @@ TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi)/..
include $(TOPDIR)/config.mk
include $(TOPDIR)/rules.mk
-#
-# Library version
-#
-VERSION=3
-REVISION=2
-AGE=0
-
#
# Common files
#
-SRCS=pfmlib_common.c pfmlib_os.c pfmlib_priv.c
+SRCS=pfmlib_common.c pfmlib_priv.c
+
+ifeq ($(SYS),Linux)
+SRCS += pfmlib_os_linux.c pfmlib_os_linux_v2.c
+
+ifneq ($(CONFIG_PFMLIB_OLD_PFMV2),y)
+SRCS += pfmlib_os_linux_v3.c
+endif
+
+endif
+
+ifeq ($(SYS),Darwin)
+SRCS += pfmlib_os_macos.c
+endif
CFLAGS+=-D_REENTRANT
#
# list all library support modules
#
-INCDEP=$(INC_COMMON)
-
ifeq ($(CONFIG_PFMLIB_ARCH_IA64),y)
-INCDEP := $(INCDEP) $(INC_IA64)
+INCARCH = $(INC_IA64)
SRCS += pfmlib_gen_ia64.c pfmlib_itanium.c pfmlib_itanium2.c pfmlib_montecito.c
CFLAGS += -DCONFIG_PFMLIB_ARCH_IA64
endif
ifeq ($(CONFIG_PFMLIB_ARCH_I386),y)
-INCDEP := $(INCDEP) $(INC_IA32)
-SRCS += pfmlib_i386_p6.c pfmlib_pentium4.c pfmlib_amd64.c pfmlib_core.c pfmlib_gen_ia32.c
+INCARCH = $(INC_IA32)
+SRCS += pfmlib_i386_p6.c pfmlib_pentium4.c pfmlib_amd64.c pfmlib_core.c pfmlib_gen_ia32.c \
+ pfmlib_intel_atom.c pfmlib_intel_nhm.c pfmlib_coreduo.c
CFLAGS += -DCONFIG_PFMLIB_ARCH_I386
endif
ifeq ($(CONFIG_PFMLIB_ARCH_X86_64),y)
-INCDEP := $(INCDEP) $(INC_X86_64)
-SRCS += pfmlib_pentium4.c pfmlib_amd64.c pfmlib_core.c pfmlib_gen_ia32.c
+INCARCH = $(INC_X86_64)
+SRCS += pfmlib_pentium4.c pfmlib_amd64.c pfmlib_core.c pfmlib_gen_ia32.c pfmlib_intel_atom.c \
+ pfmlib_intel_nhm.c
CFLAGS += -DCONFIG_PFMLIB_ARCH_X86_64
endif
ifeq ($(CONFIG_PFMLIB_ARCH_MIPS64),y)
-INCDEP := $(INCDEP) $(INC_MIPS64)
+INCARCH = $(INC_MIPS64)
SRCS += pfmlib_gen_mips64.c
CFLAGS += -DCONFIG_PFMLIB_ARCH_MIPS64
+
+ifeq ($(CONFIG_PFMLIB_ARCH_SICORTEX),y)
+ INCARCH = $(INC_SICORTEX)
+ CFLAGS += -DCONFIG_PFMLIB_ARCH_SICORTEX
+ifneq ($(SCINCDIR),)
+ CFLAGS += -I$(SCINCDIR)
+endif
+ SRCS += pfmlib_sicortex.c
+endif
endif
ifeq ($(CONFIG_PFMLIB_ARCH_POWERPC),y)
-INCDEP := $(INCDEP) $(INC_POWERPC)
+INCARCH = $(INC_POWERPC)
SRCS += pfmlib_gen_powerpc.c
CFLAGS += -DCONFIG_PFMLIB_ARCH_POWERPC
endif
ifeq ($(CONFIG_PFMLIB_ARCH_SPARC),y)
-INCDEP := $(INCDEP) $(INC_SPARC)
+INCARCH = $(INC_SPARC)
SRCS += pfmlib_sparc.c
CFLAGS += -DCONFIG_PFMLIB_ARCH_SPARC
endif
ifeq ($(CONFIG_PFMLIB_ARCH_CRAYX2),y)
-INCDEP := $(INCDEP) $(INC_CRAYX2)
+INCARCH = $(INC_CRAYX2)
SRCS += pfmlib_crayx2.c
CFLAGS += -DCONFIG_PFMLIB_ARCH_CRAYX2
endif
@@ -90,58 +105,30 @@ CFLAGS += -DCONFIG_PFMLIB_ARCH_CRAYXT
endif
ifeq ($(CONFIG_PFMLIB_CELL),y)
-INCDEP := $(INCDEP) $(INC_CELL)
+INCARCH = $(INC_CELL)
SRCS += pfmlib_cell.c
CFLAGS += -DCONFIG_PFMLIB_CELL
endif
-CFLAGS+=-I.
-ALIBPFM=libpfm.a
-
-ifneq ($(CONFIG_PFMLIB_ARCH_CRAYX2),y)
-ifneq ($(CC),qk-gcc)
+ifeq ($(SYS),Linux)
+SLDFLAGS=-shared -Wl,-soname -Wl,$(VLIBPFM)
SLIBPFM=libpfm.so.$(VERSION).$(REVISION).$(AGE)
VLIBPFM=libpfm.so.$(VERSION)
+SOLIBEXT=so
endif
-endif
-
-TARGETS=$(ALIBPFM) $(SLIBPFM)
-
-OBJS=$(SRCS:.c=.o)
-SOBJS=$(OBJS:.o=.lo)
-
-all: $(TARGETS)
-
-$(OBJS) $(SOBJS): $(TOPDIR)/config.mk $(TOPDIR)/rules.mk Makefile $(INCDEP)
-
-libpfm.a: $(OBJS)
- $(RM) $@
- $(AR) cru $@ $(OBJS)
-
-$(SLIBPFM): $(SOBJS)
- $(CC) -shared -Wl,-soname -Wl,$(VLIBPFM) -o $@ $(SOBJS)
- $(LN) $@ $(VLIBPFM)
- $(LN) $@ libpfm.so
-
-clean:
- $(RM) -f *.o *.lo *.a *.so* *~
-distclean: clean
+CFLAGS+=-I.
+ALIBPFM=libpfm.a
-depend:
- $(MKDEP) $(CFLAGS) $(SRCS)
+TARGETS=$(ALIBPFM)
-install: $(TARGETS)
- -mkdir -p $(DESTDIR)$(LIBDIR)
- $(INSTALL) -m 644 $(ALIBPFM) $(DESTDIR)$(LIBDIR)
-ifneq ($(CONFIG_PFMLIB_ARCH_CRAYX2),y)
-ifneq ($(CC),qk-gcc)
- $(INSTALL) $(SLIBPFM) $(DESTDIR)$(LIBDIR)
- cd $(DESTDIR)$(LIBDIR); $(LN) $(SLIBPFM) $(VLIBPFM)
- cd $(DESTDIR)$(LIBDIR); $(LN) $(SLIBPFM) libpfm.so
-endif
+ifeq ($(CONFIG_PFMLIB_SHARED),y)
+TARGETS += $(SLIBPFM)
endif
+OBJS=$(SRCS:.c=.o)
+SOBJS=$(OBJS:.o=.lo)
+
INC_COMMON= $(PFMINCDIR)/perfmon/pfmlib.h \
$(PFMINCDIR)/perfmon/pfmlib_comp.h \
$(PFMINCDIR)/perfmon/pfmlib_os.h \
@@ -160,36 +147,47 @@ INC_IA64= $(PFMINCDIR)/perfmon/pfmlib_itanium.h \
$(PFMINCDIR)/perfmon/pfmlib_os_ia64.h \
itanium_events.h itanium2_events.h montecito_events.h
-INC_X86_64= $(PFMINCDIR)/perfmon/perfmon_pebs_smpl.h \
- $(PFMINCDIR)/perfmon/pfmlib_amd64.h \
- $(PFMINCDIR)/perfmon/pfmlib_core.h \
- $(PFMINCDIR)/perfmon/pfmlib_gen_ia32.h \
- $(PFMINCDIR)/perfmon/pfmlib_pentium4.h \
- $(PFMINCDIR)/perfmon/pfmlib_comp_x86_64.h \
- $(PFMINCDIR)/perfmon/pfmlib_os_x86_64.h \
- amd64_events.h pentium4_events.h gen_ia32_events.h core_events.h
-
-INC_IA32=$(PFMINCDIR)/perfmon/perfmon_pebs_smpl.h \
+INC_IA32=$(PFMINCDIR)/perfmon/perfmon_pebs_core_smpl.h \
+ $(PFMINCDIR)/perfmon/perfmon_pebs_p4_smpl.h \
$(PFMINCDIR)/perfmon/pfmlib_pentium4.h \
$(PFMINCDIR)/perfmon/pfmlib_amd64.h \
$(PFMINCDIR)/perfmon/pfmlib_core.h \
+ $(PFMINCDIR)/perfmon/pfmlib_intel_atom.h \
+ $(PFMINCDIR)/perfmon/pfmlib_intel_nhm.h \
$(PFMINCDIR)/perfmon/pfmlib_i386_p6.h \
$(PFMINCDIR)/perfmon/pfmlib_gen_ia32.h \
$(PFMINCDIR)/perfmon/pfmlib_comp_i386.h \
$(PFMINCDIR)/perfmon/pfmlib_os_i386.h \
amd64_events.h i386_p6_events.h \
- pentium4_events.h gen_ia32_events.h coreduo_events.h core_events.h
+ pentium4_events.h gen_ia32_events.h coreduo_events.h core_events.h \
+ intel_atom_events.h intel_corei7_events.h intel_corei7_unc_events.h
+
+INC_X86_64= $(PFMINCDIR)/perfmon/perfmon_pebs_core_smpl.h \
+ $(PFMINCDIR)/perfmon/perfmon_pebs_p4_smpl.h \
+ $(PFMINCDIR)/perfmon/pfmlib_amd64.h \
+ $(PFMINCDIR)/perfmon/pfmlib_core.h \
+ $(PFMINCDIR)/perfmon/pfmlib_intel_atom.h \
+ $(PFMINCDIR)/perfmon/pfmlib_intel_nhm.h \
+ $(PFMINCDIR)/perfmon/pfmlib_gen_ia32.h \
+ $(PFMINCDIR)/perfmon/pfmlib_pentium4.h \
+ $(PFMINCDIR)/perfmon/pfmlib_comp_x86_64.h \
+ $(PFMINCDIR)/perfmon/pfmlib_os_x86_64.h \
+ amd64_events.h pentium4_events.h gen_ia32_events.h core_events.h \
+ intel_atom_events.h intel_corei7_events.h intel_corei7_unc_events.h
INC_MIPS64= $(PFMINCDIR)/perfmon/pfmlib_gen_mips64.h \
$(PFMINCDIR)/perfmon/pfmlib_comp_mips64.h \
$(PFMINCDIR)/perfmon/pfmlib_os_mips64.h \
gen_mips64_events.h
-INC_POWERPC= $(PFMINCDIR)/perfmon/pfmlib_gen_powerpc.h \
+INC_SICORTEX= $(INC_MIPS64) $(PFMINCDIR)/perfmon/pfmlib_sicortex.h
+
+INC_POWERPC= $(PFMINCDIR)/perfmon/pfmlib_powerpc.h \
$(PFMINCDIR)/perfmon/pfmlib_comp_powerpc.h \
$(PFMINCDIR)/perfmon/pfmlib_os_powerpc.h \
- ppc970_events.h ppc970mp_events.h power4_events.h power4+_events.h \
- power5_events.h power5+_events.h power6_events.h powerpc_reg.h
+ ppc970_events.h ppc970mp_events.h power4_events.h \
+ power5_events.h power5+_events.h power6_events.h \
+ power7_events.h powerpc_reg.h
INC_SPARC= $(PFMINCDIR)/perfmon/pfmlib_sparc.h \
$(PFMINCDIR)/perfmon/pfmlib_comp_sparc.h \
@@ -197,8 +195,43 @@ INC_SPARC= $(PFMINCDIR)/perfmon/pfmlib_sparc.h \
ultra12_events.h ultra3_events.h ultra3plus_events.h ultra3i_events.h \
ultra4plus_events.h niagara1_events.h niagara2_events.h
-INC_CRAYX2= $(PFMINCIDR)/perfmon/pfmlib_crayx2.h \
+INC_CRAYX2= $(PFMINCDIR)/perfmon/pfmlib_crayx2.h \
crayx2_events.h pfmlib_crayx2_priv.h
INC_CELL= $(PFMINCDIR)/perfmon/pfmlib_cell.h \
- cell_event.h
+ cell_events.h
+
+INCDEP=$(INC_COMMON) $(INCARCH)
+
+all: $(TARGETS)
+
+$(OBJS) $(SOBJS): $(TOPDIR)/config.mk $(TOPDIR)/rules.mk Makefile $(INCDEP)
+
+libpfm.a: $(OBJS)
+ $(RM) $@
+ $(AR) cru $@ $(OBJS)
+
+$(SLIBPFM): $(SOBJS)
+ $(CC) $(CFLAGS) $(SLDFLAGS) -o $@ $(SOBJS)
+ $(LN) $@ $(VLIBPFM)
+ $(LN) $@ libpfm.$(SOLIBEXT)
+
+clean:
+ $(RM) -f *.o *.lo *.a *.so* *~ *.$(SOLIBEXT)
+
+distclean: clean
+
+depend:
+ $(MKDEP) $(CFLAGS) $(SRCS)
+
+install: $(TARGETS)
+
+install:
+ @echo building: $(TARGETS)
+ -mkdir -p $(DESTDIR)$(LIBDIR)
+ $(INSTALL) -m 644 $(ALIBPFM) $(DESTDIR)$(LIBDIR)
+ifeq ($(CONFIG_PFMLIB_SHARED),y)
+ $(INSTALL) $(SLIBPFM) $(DESTDIR)$(LIBDIR)
+ cd $(DESTDIR)$(LIBDIR); $(LN) $(SLIBPFM) $(VLIBPFM)
+ cd $(DESTDIR)$(LIBDIR); $(LN) $(SLIBPFM) libpfm.$(SOLIBEXT)
+endif
diff --git a/src/libpfm-3.y/lib/amd64_events_k8.h b/src/libpfm-3.y/lib/amd64_events_k8.h
index e4cc79fb747116e328dab987d49f3724e15e6e7c..c969537e78b3ac281a331dc9f83b6a60fd63e53f 100644
--- a/src/libpfm-3.y/lib/amd64_events_k8.h
+++ b/src/libpfm-3.y/lib/amd64_events_k8.h
@@ -38,6 +38,12 @@
* 0Fh Processors, Publication # 32559, Revision: 3.08, Issue Date:
* July 2007
*
+ * Feb 26 2009 -- Robert Richter, robert.richter@amd.com
+ *
+ * Updates and fixes of some revision flags and descriptions according
+ * to these documents:
+ * BIOS and Kernel Developer's Guide, #26094, Revision: 3.30
+ * BIOS and Kernel Developer's Guide, #32559, Revision: 3.12
*/
static pme_amd64_entry_t amd64_k8_pe[]={
@@ -219,7 +225,7 @@ static pme_amd64_entry_t amd64_k8_pe[]={
.pme_udesc = "Modified-state line from L2",
.pme_ucode = 0x10,
},
- { .pme_uname = "L2_ALL",
+ { .pme_uname = "ALL",
.pme_udesc = "Shared, Exclusive, Owned, Modified State Refills",
.pme_ucode = 0x1F,
},
@@ -489,19 +495,26 @@ static pme_amd64_entry_t amd64_k8_pe[]={
.pme_code = 0x7F,
.pme_desc = "L2 Fill/Writeback",
.pme_flags = PFMLIB_AMD64_UMASK_COMBO,
- .pme_numasks = 3,
+ .pme_numasks = 4,
.pme_umasks = {
{ .pme_uname = "L2_FILLS",
.pme_udesc = "L2 fills (victims from L1 caches, TLB page table walks and data prefetches)",
.pme_ucode = 0x01,
},
- { .pme_uname = "L2_WRITEBACKS_TO_SYSTEM",
+ { .pme_uname = "ALL",
+ .pme_udesc = "All sub-events selected",
+ .pme_ucode = 0x01,
+ .pme_uflags = PFMLIB_AMD64_TILL_K8_REV_E,
+ },
+ { .pme_uname = "L2_WRITEBACKS",
.pme_udesc = "L2 Writebacks to system.",
.pme_ucode = 0x02,
+ .pme_uflags = PFMLIB_AMD64_K8_REV_F,
},
{ .pme_uname = "ALL",
.pme_udesc = "All sub-events selected",
.pme_ucode = 0x03,
+ .pme_uflags = PFMLIB_AMD64_K8_REV_F,
},
},
},
@@ -603,7 +616,7 @@ static pme_amd64_entry_t amd64_k8_pe[]={
},
/* 52 */{.pme_name = "RETIRED_MMX_AND_FP_INSTRUCTIONS",
.pme_code = 0xCB,
- .pme_desc = "Retired MMX Instructions",
+ .pme_desc = "Retired MMX/FP Instructions",
.pme_flags = PFMLIB_AMD64_UMASK_COMBO,
.pme_numasks = 5,
.pme_umasks = {
@@ -864,32 +877,42 @@ static pme_amd64_entry_t amd64_k8_pe[]={
/* 78 */{.pme_name = "THERMAL_STATUS_AND_ECC_ERRORS",
.pme_code = 0xE8,
.pme_desc = "Thermal Status and ECC Errors",
- .pme_flags = PFMLIB_AMD64_UMASK_COMBO,
- .pme_numasks = 6,
+ .pme_flags = PFMLIB_AMD64_UMASK_COMBO | PFMLIB_AMD64_K8_REV_E,
+ .pme_numasks = 7,
.pme_umasks = {
- { .pme_uname = "NUMBER_OF_CLOCKS_CPU_IS_ACTIVE_WHEN_HTC_IS_ACTIVE",
+ { .pme_uname = "CLKS_CPU_ACTIVE",
.pme_udesc = "Number of clocks CPU is active when HTC is active",
.pme_ucode = 0x01,
+ .pme_uflags = PFMLIB_AMD64_K8_REV_F,
},
- { .pme_uname = "NUMBER_OF_CLOCKS_CPU_CLOCK_IS_INACTIVE_WHEN_HTC_IS_ACTIVE",
+ { .pme_uname = "CLKS_CPU_INACTIVE",
.pme_udesc = "Number of clocks CPU clock is inactive when HTC is active",
.pme_ucode = 0x02,
+ .pme_uflags = PFMLIB_AMD64_K8_REV_F,
},
- { .pme_uname = "NUMBER_OF_CLOCKS_WHEN_DIE_TEMPERATURE_IS_HIGHER_THAN_THE_SOFTWARE_HIGH_TEMPERATURE",
- .pme_udesc = "Number of clocks when die temperature is higher than the software high temperature",
+ { .pme_uname = "CLKS_DIE_TEMP_TOO_HIGH",
+ .pme_udesc = "Number of clocks when die temperature is higher than the software high temperature threshold",
.pme_ucode = 0x04,
+ .pme_uflags = PFMLIB_AMD64_K8_REV_F,
},
- { .pme_uname = "NUMBER_OF_CLOCKS_WHEN_HIGH_TEMPERATURE_THRESHOLD_WAS_EXCEEDED",
+ { .pme_uname = "CLKS_TEMP_THRESHOLD_EXCEEDED",
.pme_udesc = "Number of clocks when high temperature threshold was exceeded",
.pme_ucode = 0x08,
+ .pme_uflags = PFMLIB_AMD64_K8_REV_F,
},
- { .pme_uname = "NUMBER_OF_CORRECTABLE_AND_UNCORRECTABLE_DRAM_ECC_ERRORS",
+ { .pme_uname = "DRAM_ECC_ERRORS",
.pme_udesc = "Number of correctable and Uncorrectable DRAM ECC errors",
.pme_ucode = 0x80,
},
+ { .pme_uname = "ALL",
+ .pme_udesc = "All sub-events selected",
+ .pme_ucode = 0x80,
+ .pme_uflags = PFMLIB_AMD64_TILL_K8_REV_E,
+ },
{ .pme_uname = "ALL",
.pme_udesc = "All sub-events selected",
.pme_ucode = 0x8F,
+ .pme_uflags = PFMLIB_AMD64_K8_REV_F,
},
},
},
@@ -897,7 +920,7 @@ static pme_amd64_entry_t amd64_k8_pe[]={
.pme_code = 0xE9,
.pme_desc = "CPU/IO Requests to Memory/IO",
.pme_flags = PFMLIB_AMD64_UMASK_COMBO | PFMLIB_AMD64_K8_REV_E,
- .pme_numasks = 19,
+ .pme_numasks = 9,
.pme_umasks = {
{ .pme_uname = "I_O_TO_I_O",
.pme_udesc = "I/O to I/O",
@@ -931,46 +954,6 @@ static pme_amd64_entry_t amd64_k8_pe[]={
.pme_udesc = "From local node",
.pme_ucode = 0x80,
},
- { .pme_uname = "LOCAL_CPU_TO_LOCAL_MEMORY",
- .pme_udesc = "Local CPU to local memory",
- .pme_ucode = 0xA8,
- },
- { .pme_uname = "LOCAL_CPU_TO_LOCAL_IO",
- .pme_udesc = "Local CPU to local input/output",
- .pme_ucode = 0xA4,
- },
- { .pme_uname = "LOCAL_IO_TO_LOCAL_MEMORY",
- .pme_udesc = "Local input/output to local memory",
- .pme_ucode = 0xA2,
- },
- { .pme_uname = "LOCAL_IO_TO_LOCAL_IO",
- .pme_udesc = "Local input/output to local input/output",
- .pme_ucode = 0xA1,
- },
- { .pme_uname = "LOCAL_CPU_TO_REMOTE_MEMORY",
- .pme_udesc = "Local CPU to remote memory",
- .pme_ucode = 0x98,
- },
- { .pme_uname = "LOCAL_CPU_TO_REMOTE_IO",
- .pme_udesc = "Local CPU to remote input/output",
- .pme_ucode = 0x94,
- },
- { .pme_uname = "LOCAL_IO_TO_REMOTE_MEMORY",
- .pme_udesc = "Local input/output to remote memory",
- .pme_ucode = 0x92,
- },
- { .pme_uname = "LOCAL_IO_TO_REMOTE_IO",
- .pme_udesc = "Local input/output to remote input/output",
- .pme_ucode = 0x91,
- },
- { .pme_uname = "REMOTE_CPU_TO_LOCAL_IO",
- .pme_udesc = "Remote CPU to local input/output",
- .pme_ucode = 0x64,
- },
- { .pme_uname = "REMOTE_IO_TO_LOCAL_IO",
- .pme_udesc = "Remote input/output to local input/output",
- .pme_ucode = 0x61,
- },
{ .pme_uname = "ALL",
.pme_udesc = "All sub-events selected",
.pme_ucode = 0xFF,
@@ -1024,11 +1007,11 @@ static pme_amd64_entry_t amd64_k8_pe[]={
.pme_ucode = 0x02,
},
{ .pme_uname = "POSTED_WRITE_BYTE",
- .pme_udesc = "Posted SzWr Byte (1-32 bytes) Sub-cache-line DMA writes, size varies; also",
+ .pme_udesc = "Posted SzWr Byte (1-32 bytes) Sub-cache-line DMA writes, size varies; also flushes of partially-filled Write Combining buffer",
.pme_ucode = 0x04,
},
{ .pme_uname = "POSTED_WRITE_DWORD",
- .pme_udesc = "Posted SzWr Dword (1-16 dwords) Block-oriented DMA writes, often cache-line",
+ .pme_udesc = "Posted SzWr Dword (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushes",
.pme_ucode = 0x08,
},
{ .pme_uname = "READ_BYTE_4_BYTES",
@@ -1036,7 +1019,7 @@ static pme_amd64_entry_t amd64_k8_pe[]={
.pme_ucode = 0x10,
},
{ .pme_uname = "READ_DWORD_1_16_DWORDS",
- .pme_udesc = "SzRd Dword (1-16 dwords) Block-oriented DMA reads, typically cache-",
+ .pme_udesc = "SzRd Dword (1-16 dwords) Block-oriented DMA reads, typically cache-line size",
.pme_ucode = 0x20,
},
{ .pme_uname = "READ_MODIFY_WRITE",
@@ -1053,7 +1036,7 @@ static pme_amd64_entry_t amd64_k8_pe[]={
.pme_code = 0xEC,
.pme_desc = "Probe Responses and Upstream Requests",
.pme_flags = PFMLIB_AMD64_UMASK_COMBO,
- .pme_numasks = 8,
+ .pme_numasks = 9,
.pme_umasks = {
{ .pme_uname = "MISS",
.pme_udesc = "Probe miss",
@@ -1079,6 +1062,11 @@ static pme_amd64_entry_t amd64_k8_pe[]={
.pme_udesc = "Upstream non-display refresh reads",
.pme_ucode = 0x20,
},
+ { .pme_uname = "ALL",
+ .pme_udesc = "All sub-events selected",
+ .pme_ucode = 0x3F,
+ .pme_uflags = PFMLIB_AMD64_TILL_K8_REV_C,
+ },
{ .pme_uname = "UPSTREAM_WRITES",
.pme_udesc = "Upstream writes",
.pme_ucode = 0x40,
@@ -1087,6 +1075,7 @@ static pme_amd64_entry_t amd64_k8_pe[]={
{ .pme_uname = "ALL",
.pme_udesc = "All sub-events selected",
.pme_ucode = 0x7F,
+ .pme_uflags = PFMLIB_AMD64_K8_REV_D,
},
},
},
diff --git a/src/libpfm-3.y/lib/cell_events.h b/src/libpfm-3.y/lib/cell_events.h
index 808db834991afaae3f5956a48bf8d7e30ade1f5f..62d0008e5aa9742a559994d787f385e6bd3fea81 100644
--- a/src/libpfm-3.y/lib/cell_events.h
+++ b/src/libpfm-3.y/lib/cell_events.h
@@ -22,89 +22,3058 @@
*/
static pme_cell_entry_t cell_pe[] = {
- {.pme_name = "Branch_Commit",
- .pme_desc = " Branch instruction committed. ",
- .pme_code = 0x834,
+ {.pme_name = "CYCLES",
+ .pme_desc = "CPU cycles",
+ .pme_code = 0x0, /* 0 */
+ .pme_enable_word = WORD_NONE,
+ .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "BRANCH_COMMIT_TH0",
+ .pme_desc = "Branch instruction committed.",
+ .pme_code = 0x834, /* 2100 */
+ .pme_enable_word = WORD_0_AND_1,
+ .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "BRANCH_FLUSH_TH0",
+ .pme_desc = "Branch instruction that caused a misprediction flush is committed. Branch misprediction includes",
+ .pme_code = 0x835, /* 2101 */
+ .pme_enable_word = WORD_0_AND_1,
+ .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "INST_BUFF_EMPTY_TH0",
+ .pme_desc = "Instruction buffer empty.",
+ .pme_code = 0x836, /* 2102 */
+ .pme_enable_word = WORD_0_AND_1,
+ .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "INST_ERAT_MISS_TH0",
+ .pme_desc = "Instruction effective-address-to-real-address translation (I-ERAT) miss.",
+ .pme_code = 0x837, /* 2103 */
+ .pme_enable_word = WORD_0_AND_1,
+ .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "L1_ICACHE_MISS_CYCLES_TH0",
+ .pme_desc = "L1 Instruction cache miss cycles. Counts the cycles from the miss event until the returned instruction is dispatched or cancelled due to branch misprediction, completion restart, or exceptions.",
+ .pme_code = 0x838, /* 2104 */
+ .pme_enable_word = WORD_0_AND_1,
+ .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "DISPATCH_BLOCKED_TH0",
+ .pme_desc = "Valid instruction available for dispatch, but dispatch is blocked.",
+ .pme_code = 0x83a, /* 2106 */
+ .pme_enable_word = WORD_0_AND_1,
+ .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "INST_FLUSH_TH0",
+ .pme_desc = "Instruction in pipeline stage EX7 causes a flush.",
+ .pme_code = 0x83d, /* 2109 */
+ .pme_enable_word = WORD_0_AND_1,
+ .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "PPC_INST_COMMIT_TH0",
+ .pme_desc = "Two PowerPC instructions committed. For microcode sequences, only the last microcode operation is counted. Committed instructions are counted two at a time. If only one instruction has committed for a given cycle, this event will not be raised until another instruction has been committed in a future cycle.",
+ .pme_code = 0x83f, /* 2111 */
+ .pme_enable_word = WORD_0_AND_1,
+ .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "BRANCH_COMMIT_TH1",
+ .pme_desc = "Branch instruction committed.",
+ .pme_code = 0x847, /* 2119 */
.pme_enable_word = WORD_0_AND_1,
.pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
.pme_type = COUNT_TYPE_OCCURRENCE,
},
- {.pme_name = "Branch_Flush",
- .pme_desc = " Branch instruction that caused a misprediction flush is committed. Branch misprediction includes: (1) misprediction of taken or not-taken on conditional branch, (2) misprediction of branch target address on bclr[1] and bcctr[1]. ",
- .pme_code = 0x835,
+ {.pme_name = "BRANCH_FLUSH_TH1",
+ .pme_desc = "Branch instruction that caused a misprediction flush is committed. Branch misprediction includes",
+ .pme_code = 0x848, /* 2120 */
.pme_enable_word = WORD_0_AND_1,
.pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
.pme_type = COUNT_TYPE_OCCURRENCE,
},
- {.pme_name = "Ibuf_Empty",
- .pme_desc = " Instruction buffer empty. ",
- .pme_code = 0x836,
+ {.pme_name = "INST_BUFF_EMPTY_TH1",
+ .pme_desc = "Instruction buffer empty.",
+ .pme_code = 0x849, /* 2121 */
.pme_enable_word = WORD_0_AND_1,
.pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
.pme_type = COUNT_TYPE_CUMULATIVE_LEN,
},
- {.pme_name = "IERAT_Miss",
- .pme_desc = " Instruction effective-address-to-real-address translation (I-ERAT) miss. ",
- .pme_code = 0x837,
+ {.pme_name = "INST_ERAT_MISS_TH1",
+ .pme_desc = "Instruction effective-address-to-real-address translation (I-ERAT) miss.",
+ .pme_code = 0x84a, /* 2122 */
.pme_enable_word = WORD_0_AND_1,
.pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
.pme_type = COUNT_TYPE_OCCURRENCE,
},
- {.pme_name = "IL1_Miss_Cycles",
- .pme_desc = " : L1 Instruction cache miss cycles. Counts the cycles from the miss event until the returned instruction is dispatched or cancelled due to branch misprediction, completion restart, or exceptions (see Note 1). ",
- .pme_code = 0x838,
+ {.pme_name = "L1_ICACHE_MISS_CYCLES_TH1",
+ .pme_desc = "L1 Instruction cache miss cycles. Counts the cycles from the miss event until the returned instruction is dispatched or cancelled due to branch misprediction, completion restart, or exceptions.",
+ .pme_code = 0x84b, /* 2123 */
.pme_enable_word = WORD_0_AND_1,
.pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
.pme_type = COUNT_TYPE_BOTH_TYPE,
},
- {.pme_name = "Dispatch_Blocked",
- .pme_desc = " : Valid instruction available for dispatch, but dispatch is blocked. ",
- .pme_code = 0x83a,
+ {.pme_name = "DISPATCH_BLOCKED_TH1",
+ .pme_desc = "Valid instruction available for dispatch, but dispatch is blocked.",
+ .pme_code = 0x84d, /* 2125 */
.pme_enable_word = WORD_0_AND_1,
.pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
.pme_type = COUNT_TYPE_CUMULATIVE_LEN,
},
- {.pme_name = "Instr_Flushed",
- .pme_desc = " Instruction in pipeline stage EX7 causes a flush. ",
- .pme_code = 0x83d,
+ {.pme_name = "INST_FLUSH_TH1",
+ .pme_desc = "Instruction in pipeline stage EX7 causes a flush.",
+ .pme_code = 0x850, /* 2128 */
.pme_enable_word = WORD_0_AND_1,
.pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
.pme_type = COUNT_TYPE_OCCURRENCE,
},
- {.pme_name = "PPC_Commit",
- .pme_desc = " Two PowerPC instructions committed. For microcode sequences, only the last microcode operation is counted. Committed instructions are counted two at a time. If only one instruction has committed for a given cycle, this event will not be raised until another instruction has been committed in a future cycle. ",
- .pme_code = 0x83f,
+ {.pme_name = "PPC_INST_COMMIT_TH1",
+ .pme_desc = "Two PowerPC instructions committed. For microcode sequences, only the last microcode operation is counted. Committed instructions are counted two at a time. If only one instruction has committed for a given cycle, this event will not be raised until another instruction has been committed in a future cycle.",
+ .pme_code = 0x852, /* 2130 */
.pme_enable_word = WORD_0_AND_1,
.pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
.pme_type = COUNT_TYPE_OCCURRENCE,
},
- {.pme_name = "23_2",
- .pme_desc = " Data effective-address-to-real-address translation (D-ERAT) miss. This event is not speculative. ",
- .pme_code = 0x8fe,
+ {.pme_name = "DATA_ERAT_MISS_TH0",
+ .pme_desc = "Data effective-address-to-real-address translation (D-ERAT) miss. Not speculative.",
+ .pme_code = 0x89a, /* 2202 */
+ .pme_enable_word = WORD_0_AND_1,
+ .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "ST_REQ_TH0",
+ .pme_desc = "Store request counted at the L2 interface. Counts microcoded PPE sequences more than once. (Thread 0 and 1)",
+ .pme_code = 0x89b, /* 2203 */
+ .pme_enable_word = WORD_0_AND_1,
+ .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "LD_VALID_TH0",
+ .pme_desc = "Load valid at a particular pipe stage. Speculative, since flushed operations are counted as well. Counts microcoded PPE sequences more than once. Misaligned flushes might be counted the first time as well. Load operations include all loads that read data from the cache, dcbt and dcbtst. Does not include load Vector/SIMD multimedia extension pattern instructions.",
+ .pme_code = 0x89c, /* 2204 */
+ .pme_enable_word = WORD_0_AND_1,
+ .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "L1_DCACHE_MISS_TH0",
+ .pme_desc = "L1 D-cache load miss. Pulsed when there is a miss request that has a tag miss but not an ERAT miss. Speculative, since flushed operations are counted as well.",
+ .pme_code = 0x89d, /* 2205 */
.pme_enable_word = WORD_0_AND_1,
.pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
.pme_type = COUNT_TYPE_CUMULATIVE_LEN,
},
- {.pme_name = "23_3",
- .pme_desc = " Store request counted at the L2 interface. This counts microcoded PowerPC Processor Element (PPE) sequences more than once (see Note 1 for exceptions). ",
- .pme_code = 0x8ff,
+ {.pme_name = "DATA_ERAT_MISS_TH1",
+ .pme_desc = "Data effective-address-to-real-address translation (D-ERAT) miss. Not speculative.",
+ .pme_code = 0x8aa, /* 2218 */
.pme_enable_word = WORD_0_AND_1,
.pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
.pme_type = COUNT_TYPE_CUMULATIVE_LEN,
},
- {.pme_name = "23_4",
- .pme_desc = " Load valid at a particular pipe stage. This is speculative because flushed operations are also counted. Counts microcoded PPE sequences more than once. Misaligned flushes might be counted the first time as well. Load operations include all loads that read data from the cache, dcbt and dcbtst. This event does not include load Vector/single instruction multiple data (SIMD) multimedia extension pattern instructions. ",
- .pme_code = 0x900,
+ {.pme_name = "LD_VALID_TH1",
+ .pme_desc = "Load valid at a particular pipe stage. Speculative, since flushed operations are counted as well. Counts microcoded PPE sequences more than once. Misaligned flushes might be counted the first time as well. Load operations include all loads that read data from the cache, dcbt and dcbtst. Does not include load Vector/SIMD multimedia extension pattern instructions.",
+ .pme_code = 0x8ac, /* 2220 */
.pme_enable_word = WORD_0_AND_1,
.pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
.pme_type = COUNT_TYPE_CUMULATIVE_LEN,
},
- {.pme_name = "23_5",
- .pme_desc = " L1 D-cache load miss. Pulsed when there is a miss request that has a tag miss but not an effective-address-to-real-address translation (ERAT) miss. This is speculative because flushed operations are counted as well. ",
- .pme_code = 0x901,
+ {.pme_name = "DATA_ERAT_MISS_TH1",
+ .pme_desc = "L1 D-cache load miss. Pulsed when there is a miss request that has a tag miss but not an ERAT miss. Speculative, since flushed operations are counted as well.",
+ .pme_code = 0x8ad, /* 2221 */
.pme_enable_word = WORD_0_AND_1,
.pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
.pme_type = COUNT_TYPE_CUMULATIVE_LEN,
},
+ {.pme_name = "LD_MFC_MMIO",
+ .pme_desc = "Load from MFC memory-mapped I/O (MMIO) space.",
+ .pme_code = 0xc1c, /* 3100 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "ST_MFC_MMIO",
+ .pme_desc = "Stores to MFC MMIO space.",
+ .pme_code = 0xc1d, /* 3101 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "REQ_TOKEN_TYPE",
+ .pme_desc = "Request token for even memory bank numbers 0-14.",
+ .pme_code = 0xc22, /* 3106 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "RCV_8BEAT_DATA",
+ .pme_desc = "Receive 8-beat data from the Element Interconnect Bus (EIB).",
+ .pme_code = 0xc2b, /* 3115 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "SEND_8BEAT_DATA",
+ .pme_desc = "Send 8-beat data to the EIB.",
+ .pme_code = 0xc2c, /* 3116 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "SEND_CMD",
+ .pme_desc = "Send a command to the EIB; includes retried commands.",
+ .pme_code = 0xc2d, /* 3117 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "DATA_GRANT_CYCLES",
+ .pme_desc = "Cycles between data request and data grant.",
+ .pme_code = 0xc2e, /* 3118 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "NCU_ST_Q_NOT_EMPTY_CYCLES",
+ .pme_desc = "The five-entry Non-Cacheable Unit (NCU) Store Command queue not empty.",
+ .pme_code = 0xc33, /* 3123 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "L2_CACHE_HIT",
+ .pme_desc = "Cache hit for core interface unit (CIU) loads and stores.",
+ .pme_code = 0xc80, /* 3200 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "L2_CACHE_MISS",
+ .pme_desc = "Cache miss for CIU loads and stores.",
+ .pme_code = 0xc81, /* 3201 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "L2_LD_MISS",
+ .pme_desc = "CIU load miss.",
+ .pme_code = 0xc84, /* 3204 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "L2_ST_MISS",
+ .pme_desc = "CIU store to Invalid state (miss).",
+ .pme_code = 0xc85, /* 3205 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "L2_LWARX_LDARX_MISS_TH0",
+ .pme_desc = "Load word and reserve indexed (lwarx/ldarx) for Thread 0 hits Invalid cache state",
+ .pme_code = 0xc87, /* 3207 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "L2_STWCX_STDCX_MISS_TH0",
+ .pme_desc = "Store word conditional indexed (stwcx/stdcx) for Thread 0 hits Invalid cache state when reservation is set.",
+ .pme_code = 0xc8e, /* 3214 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "L2_ALL_SNOOP_SM_BUSY",
+ .pme_desc = "All four snoop state machines busy.",
+ .pme_code = 0xc99, /* 3225 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "L2_DCLAIM_GOOD",
+ .pme_desc = "Data line claim (dclaim) that received good combined response; includes store/stcx/dcbz to Shared (S), Shared Last (SL),or Tagged (T) cache state; does not include dcbz to Invalid (I) cache state.",
+ .pme_code = 0xce8, /* 3304 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "L2_DCLAIM_TO_RWITM",
+ .pme_desc = "Dclaim converted into rwitm; may still not get to the bus if stcx is aborted .",
+ .pme_code = 0xcef, /* 3311 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "L2_ST_TO_M_MU_E",
+ .pme_desc = "Store to modified (M), modified unsolicited (MU), or exclusive (E) cache state.",
+ .pme_code = 0xcf0, /* 3312 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "L2_ST_Q_FULL",
+ .pme_desc = "8-entry store queue (STQ) full.",
+ .pme_code = 0xcf1, /* 3313 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "L2_ST_TO_RC_ACKED",
+ .pme_desc = "Store dispatched to RC machine is acknowledged.",
+ .pme_code = 0xcf2, /* 3314 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "L2_GATHERABLE_ST",
+ .pme_desc = "Gatherable store (type = 00000) received from CIU.",
+ .pme_code = 0xcf3, /* 3315 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "L2_SNOOP_PUSH",
+ .pme_desc = "Snoop push.",
+ .pme_code = 0xcf6, /* 3318 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "L2_INTERVENTION_FROM_SL_E_SAME_MODE",
+ .pme_desc = "Send intervention from (SL | E) cache state to a destination within the same CBE chip.",
+ .pme_code = 0xcf7, /* 3319 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "L2_INTERVENTION_FROM_M_MU_SAME_MODE",
+ .pme_desc = "Send intervention from (M | MU) cache state to a destination within the same CBE chip.",
+ .pme_code = 0xcf8, /* 3320 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "L2_SNOOP_RETRY_CONFLICTS",
+ .pme_desc = "Respond with Retry to a snooped request due to one of the following conflicts",
+ .pme_code = 0xcfd, /* 3325 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "L2_SNOOP_RETRY_BUSY",
+ .pme_desc = "Respond with Retry to a snooped request because all snoop machines are busy.",
+ .pme_code = 0xcfe, /* 3326 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "L2_SNOOP_RESP_MMU_TO_EST",
+ .pme_desc = "Snooped response causes a cache state transition from (M | MU) to (E | S | T).",
+ .pme_code = 0xcff, /* 3327 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "L2_SNOOP_RESP_E_TO_S",
+ .pme_desc = "Snooped response causes a cache state transition from E to S.",
+ .pme_code = 0xd00, /* 3328 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "L2_SNOOP_RESP_ESLST_TO_I",
+ .pme_desc = "Snooped response causes a cache state transition from (E | SL | S | T) to Invalid (I).",
+ .pme_code = 0xd01, /* 3329 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "L2_SNOOP_RESP_MMU_TO_I",
+ .pme_desc = "Snooped response causes a cache state transition from (M | MU) to I.",
+ .pme_code = 0xd02, /* 3330 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "L2_LWARX_LDARX_MISS_TH1",
+ .pme_desc = "Load and reserve indexed (lwarx/ldarx) for Thread 1 hits Invalid cache state.",
+ .pme_code = 0xd54, /* 3412 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "L2_STWCX_STDCX_MISS_TH1",
+ .pme_desc = "Store conditional indexed (stwcx/stdcx) for Thread 1 hits Invalid cache state.",
+ .pme_code = 0xd5b, /* 3419 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "NCU_NON_CACHEABLE_ST_ALL",
+ .pme_desc = "Non-cacheable store request received from CIU; includes all synchronization operations such as sync and eieio.",
+ .pme_code = 0xdac, /* 3500 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "NCU_SYNC_REQ",
+ .pme_desc = "sync received from CIU.",
+ .pme_code = 0xdad, /* 3501 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "NCU_NON_CACHEABLE_ST",
+ .pme_desc = "Non-cacheable store request received from CIU; includes only stores.",
+ .pme_code = 0xdb0, /* 3504 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "NCU_EIEIO_REQ",
+ .pme_desc = "eieio received from CIU.",
+ .pme_code = 0xdb2, /* 3506 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "NCU_TLBIE_REQ",
+ .pme_desc = "tlbie received from CIU.",
+ .pme_code = 0xdb3, /* 3507 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "NCU_SYNC_WAIT",
+ .pme_desc = "sync at the bottom of the store queue, while waiting on st_done signal from the Bus Interface Unit (BIU) and sync_done signal from L2.",
+ .pme_code = 0xdb4, /* 3508 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "NCU_LWSYNC_WAIT",
+ .pme_desc = "lwsync at the bottom of the store queue, while waiting for a sync_done signal from the L2.",
+ .pme_code = 0xdb5, /* 3509 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "NCU_EIEIO_WAIT",
+ .pme_desc = "eieio at the bottom of the store queue, while waiting for a st_done signal from the BIU and a sync_done signal from the L2.",
+ .pme_code = 0xdb6, /* 3510 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "NCU_TLBIE_WAIT",
+ .pme_desc = "tlbie at the bottom of the store queue, while waiting for a st_done signal from the BIU.",
+ .pme_code = 0xdb7, /* 3511 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "NCU_COMBINED_NON_CACHEABLE_ST",
+ .pme_desc = "Non-cacheable store combined with the previous non-cacheable store with a contiguous address.",
+ .pme_code = 0xdb8, /* 3512 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "NCU_ALL_ST_GATHER_BUFFS_FULL",
+ .pme_desc = "All four store-gather buffers full.",
+ .pme_code = 0xdbb, /* 3515 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "NCU_LD_REQ",
+ .pme_desc = "Non-cacheable load request received from CIU; includes instruction and data fetches.",
+ .pme_code = 0xdbc, /* 3516 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "NCU_ST_Q_NOT_EMPTY",
+ .pme_desc = "The four-deep store queue not empty.",
+ .pme_code = 0xdbd, /* 3517 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "NCU_ST_Q_FULL",
+ .pme_desc = "The four-deep store queue full.",
+ .pme_code = 0xdbe, /* 3518 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "NCU_AT_LEAST_ONE_ST_GATHER_BUFF_NOT_EMPTY",
+ .pme_desc = "At least one store gather buffer not empty.",
+ .pme_code = 0xdbf, /* 3519 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "SPU_DUAL_INST_COMMITTED",
+ .pme_desc = "A dual instruction is committed.",
+ .pme_code = 0x1004, /* 4100 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "SPU_SINGLE_INST_COMMITTED",
+ .pme_desc = "A single instruction is committed.",
+ .pme_code = 0x1005, /* 4101 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "SPU_PIPE0_INST_COMMITTED",
+ .pme_desc = "A pipeline 0 instruction is committed.",
+ .pme_code = 0x1006, /* 4102 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "SPU_PIPE1_INST_COMMITTED",
+ .pme_desc = "A pipeline 1 instruction is committed.",
+ .pme_code = 0x1007, /* 4103 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "SPU_LS_BUSY",
+ .pme_desc = "Local storage is busy.",
+ .pme_code = 0x1009, /* 4105 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "SPU_DMA_CONFLICT_LD_ST",
+ .pme_desc = "A direct memory access (DMA) might conflict with a load or store.",
+ .pme_code = 0x100a, /* 4106 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "SPU_LS_ST",
+ .pme_desc = "A store instruction to local storage is issued.",
+ .pme_code = 0x100b, /* 4107 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "SPU_LS_LD",
+ .pme_desc = "A load instruction from local storage is issued.",
+ .pme_code = 0x100c, /* 4108 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "SPU_FP_EXCEPTION",
+ .pme_desc = "A floating-point unit exception occurred.",
+ .pme_code = 0x100d, /* 4109 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "SPU_BRANCH_COMMIT",
+ .pme_desc = "A branch instruction is committed.",
+ .pme_code = 0x100e, /* 4110 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "SPU_NON_SEQ_PC",
+ .pme_desc = "A nonsequential change of the SPU program counter has occurred. This can be caused by branch, asynchronous interrupt, stalled wait on channel, error-correction code (ECC) error, and so forth.",
+ .pme_code = 0x100f, /* 4111 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "SPU_BRANCH_NOT_TAKEN",
+ .pme_desc = "A branch was not taken.",
+ .pme_code = 0x1010, /* 4112 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "SPU_BRANCH_MISS_PREDICTION",
+ .pme_desc = "Branch miss prediction. This count is not exact. Certain other code sequences can cause additional pulses on this signal.",
+ .pme_code = 0x1011, /* 4113 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "SPU_BRANCH_HINT_MISS_PREDICTION",
+ .pme_desc = "Branch hint miss prediction. This count is not exact. Certain other code sequences can cause additional pulses on this signal.",
+ .pme_code = 0x1012, /* 4114 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "SPU_INST_SEQ_ERROR",
+ .pme_desc = "Instruction sequence error",
+ .pme_code = 0x1013, /* 4115 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "SPU_STALL_CH_WRITE",
+ .pme_desc = "Stalled waiting on any blocking channel write.",
+ .pme_code = 0x1015, /* 4117 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "SPU_STALL_EXTERNAL_EVENT_CH0",
+ .pme_desc = "Stalled waiting on external event status (Channel 0).",
+ .pme_code = 0x1016, /* 4118 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "SPU_STALL_SIGNAL_1_CH3",
+ .pme_desc = "Stalled waiting on SPU Signal Notification 1 (Channel 3).",
+ .pme_code = 0x1017, /* 4119 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "SPU_STALL_SIGNAL_2_CH4",
+ .pme_desc = "Stalled waiting on SPU Signal Notification 2 (Channel 4).",
+ .pme_code = 0x1018, /* 4120 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "SPU_STALL_DMA_CH21",
+ .pme_desc = "Stalled waiting on DMA Command Opcode or ClassID Register (Channel 21).",
+ .pme_code = 0x1019, /* 4121 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "SPU_STALL_MFC_READ_CH24",
+ .pme_desc = "Stalled waiting on memory flow control (MFC) Read Tag-Group Status (Channel 24).",
+ .pme_code = 0x101a, /* 4122 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "SPU_STALL_MFC_READ_CH25",
+ .pme_desc = "Stalled waiting on MFC Read List Stall-and-Notify Tag Status (Channel 25).",
+ .pme_code = 0x101b, /* 4123 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "SPU_STALL_OUTBOUND_MAILBOX_WRITE_CH28",
+ .pme_desc = "Stalled waiting on SPU Write Outbound Mailbox (Channel 28).",
+ .pme_code = 0x101c, /* 4124 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "SPU_STALL_MAILBOX_CH29",
+ .pme_desc = "Stalled waiting on SPU Mailbox (Channel 29).",
+ .pme_code = 0x1022, /* 4130 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "SPU_TR_STALL_CH",
+ .pme_desc = "Stalled waiting on a channel operation.",
+ .pme_code = 0x10a1, /* 4257 */
+ .pme_enable_word = WORD_NONE,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "SPU_EV_INST_FETCH_STALL",
+ .pme_desc = "Instruction fetch stall",
+ .pme_code = 0x1107, /* 4359 */
+ .pme_enable_word = WORD_NONE,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "SPU_EV_ADDR_TRACE",
+ .pme_desc = "Serialized SPU address (program counter) trace.",
+ .pme_code = 0x110b, /* 4363 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_SPU,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_ATOMIC_LD",
+ .pme_desc = "An atomic load was received from direct memory access controller (DMAC).",
+ .pme_code = 0x13ed, /* 5101 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_ATOMIC_DCLAIM",
+ .pme_desc = "An atomic dclaim was sent to synergistic bus interface (SBI); includes retried requests.",
+ .pme_code = 0x13ee, /* 5102 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_ATOMIC_RWITM",
+ .pme_desc = "An atomic rwitm performed was sent to SBI; includes retried requests.",
+ .pme_code = 0x13ef, /* 5103 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_ATOMIC_LD_CACHE_MISS_MU",
+ .pme_desc = "An atomic load miss caused MU cache state.",
+ .pme_code = 0x13f0, /* 5104 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_ATOMIC_LD_CACHE_MISS_E",
+ .pme_desc = "An atomic load miss caused E cache state.",
+ .pme_code = 0x13f1, /* 5105 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_ATOMIC_LD_CACHE_MISS_SL",
+ .pme_desc = "An atomic load miss caused SL cache state.",
+ .pme_code = 0x13f2, /* 5106 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_ATOMIC_LD_CACHE_HIT",
+ .pme_desc = "An atomic load hits cache.",
+ .pme_code = 0x13f3, /* 5107 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_ATOMIC_LD_CACHE_MISS_INTERVENTION",
+ .pme_desc = "Atomic load misses cache with data intervention; sum of signals 4 and 6 in this group.",
+ .pme_code = 0x13f4, /* 5108 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_ATOMIC_PUTLLXC_CACHE_MISS_WO_INTERVENTION",
+ .pme_desc = "putllc or putlluc misses cache without data intervention; for putllc, counts only when reservation is set for the address.",
+ .pme_code = 0x13fa, /* 5114 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_SNOOP_MACHINE_BUSY",
+ .pme_desc = "Snoop machine busy.",
+ .pme_code = 0x13fd, /* 5117 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MFC_SNOOP_MMU_TO_I",
+ .pme_desc = "A snoop caused cache transition from [M | MU] to I.",
+ .pme_code = 0x13ff, /* 5119 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_SNOOP_ESSL_TO_I",
+ .pme_desc = "A snoop caused cache transition from [E | S | SL] to I.",
+ .pme_code = 0x1401, /* 5121 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_SNOOP_MU_TO_T",
+ .pme_desc = "A snoop caused cache transition from MU to T cache state.",
+ .pme_code = 0x1403, /* 5123 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_SENT_INTERVENTION_LOCAL",
+ .pme_desc = "Sent modified data intervention to a destination within the same CBE chip.",
+ .pme_code = 0x1407, /* 5127 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_ANY_DMA_GET",
+ .pme_desc = "Any flavor of DMA get[] command issued to Synergistic Bus Interface (SBI); sum of signals 17-25 in this group.",
+ .pme_code = 0x1450, /* 5200 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_ANY_DMA_PUT",
+ .pme_desc = "Any flavor of DMA put[] command issued to SBI; sum of signals 2-16 in this group.",
+ .pme_code = 0x1451, /* 5201 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_DMA_PUT",
+ .pme_desc = "DMA put (put) is issued to SBI.",
+ .pme_code = 0x1452, /* 5202 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_DMA_GET",
+ .pme_desc = "DMA get data from effective address to local storage (get) issued to SBI.",
+ .pme_code = 0x1461, /* 5217 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_LD_REQ",
+ .pme_desc = "Load request sent to element interconnect bus (EIB); includes read, read atomic, rwitm, rwitm atomic, and retried commands.",
+ .pme_code = 0x14b8, /* 5304 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_ST_REQ",
+ .pme_desc = "Store request sent to EIB; includes wwf, wwc, wwk, dclaim, dclaim atomic, and retried commands.",
+ .pme_code = 0x14b9, /* 5305 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_RECV_DATA",
+ .pme_desc = "Received data from EIB, including partial cache line data.",
+ .pme_code = 0x14ba, /* 5306 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_SENT_DATA",
+ .pme_desc = "Sent data to EIB, both as a master and a snooper.",
+ .pme_code = 0x14bb, /* 5307 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_SBI_Q_NOT_EMPTY",
+ .pme_desc = "16-deep synergistic bus interface (SBI) queue with outgoing requests not empty; does not include atomic requests.",
+ .pme_code = 0x14bc, /* 5308 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MFC_SBI_Q_FULL",
+ .pme_desc = "16-deep SBI queue with outgoing requests full; does not include atomic requests.",
+ .pme_code = 0x14bd, /* 5309 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MFC_SENT_REQ",
+ .pme_desc = "Sent request to EIB.",
+ .pme_code = 0x14be, /* 5310 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_RECV_DATA_BUS_GRANT",
+ .pme_desc = "Received data bus grant; includes data sent for MMIO operations.",
+ .pme_code = 0x14c0, /* 5312 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_WAIT_DATA_BUS_GRANT",
+ .pme_desc = "Cycles between data bus request and data bus grant.",
+ .pme_code = 0x14c1, /* 5313 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MFC_CMD_O_MEM",
+ .pme_desc = "Command (read or write) for an odd-numbered memory bank; valid only when resource allocation is turned on.",
+ .pme_code = 0x14c2, /* 5314 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_CMD_E_MEM",
+ .pme_desc = "Command (read or write) for an even-numbered memory bank; valid only when resource allocation is turned on.",
+ .pme_code = 0x14c3, /* 5315 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_RECV_RETRY_RESP",
+ .pme_desc = "Request gets the Retry response; includes local and global requests.",
+ .pme_code = 0x14c6, /* 5318 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_SENT_DATA_BUS_REQ",
+ .pme_desc = "Sent data bus request to EIB.",
+ .pme_code = 0x14c7, /* 5319 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_TLB_MISS",
+ .pme_desc = "Translation Lookaside Buffer (TLB) miss without parity or protection errors.",
+ .pme_code = 0x1518, /* 5400 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "MFC_TLB_CYCLES",
+ .pme_desc = "TLB miss (cycles).",
+ .pme_code = 0x1519, /* 5401 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MFC_TLB_HIT",
+ .pme_desc = "TLB hit.",
+ .pme_code = 0x151a, /* 5402 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_READ_RWITM_1",
+ .pme_desc = "Number of read and rwitm commands (including atomic) AC1 to AC0. (Group 1)",
+ .pme_code = 0x17d4, /* 6100 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_DCLAIM_1",
+ .pme_desc = "Number of dclaim commands (including atomic) AC1 to AC0. (Group 1)",
+ .pme_code = 0x17d5, /* 6101 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_WWK_WWC_WWF_1",
+ .pme_desc = "Number of wwk, wwc, and wwf commands from AC1 to AC0. (Group 1)",
+ .pme_code = 0x17d6, /* 6102 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_SYNC_TLBSYNC_EIEIO_1",
+ .pme_desc = "Number of sync, tlbsync, and eieio commands from AC1 to AC0. (Group 1)",
+ .pme_code = 0x17d7, /* 6103 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_TLBIE_1",
+ .pme_desc = "Number of tlbie commands from AC1 to AC0. (Group 1)",
+ .pme_code = 0x17d8, /* 6104 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_PAAM_CAM_HIT_1",
+ .pme_desc = "Previous adjacent address match (PAAM) Content Addressable Memory (CAM) hit. (Group 1)",
+ .pme_code = 0x17df, /* 6111 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_PAAM_CAM_MISS_1",
+ .pme_desc = "PAAM CAM miss. (Group 1)",
+ .pme_code = 0x17e0, /* 6112 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_CMD_REFLECTED_1",
+ .pme_desc = "Command reflected. (Group 1)",
+ .pme_code = 0x17e2, /* 6114 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_READ_RWITM_2",
+ .pme_desc = "Number of read and rwitm commands (including atomic) AC1 to AC0. (Group 2)",
+ .pme_code = 0x17e4, /* 6116 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_DCLAIM_2",
+ .pme_desc = "Number of dclaim commands (including atomic) AC1 to AC0. (Group 2)",
+ .pme_code = 0x17e5, /* 6117 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_WWK_WWC_WWF_2",
+ .pme_desc = "Number of wwk, wwc, and wwf commands from AC1 to AC0. (Group 2)",
+ .pme_code = 0x17e6, /* 6118 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_SYNC_TLBSYNC_EIEIO_2",
+ .pme_desc = "Number of sync, tlbsync, and eieio commands from AC1 to AC0. (Group 2)",
+ .pme_code = 0x17e7, /* 6119 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_TLBIE_2",
+ .pme_desc = "Number of tlbie commands from AC1 to AC0. (Group 2)",
+ .pme_code = 0x17e8, /* 6120 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_PAAM_CAM_HIT_2",
+ .pme_desc = "PAAM CAM hit. (Group 2)",
+ .pme_code = 0x17ef, /* 6127 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_PAAM_CAM_MISS_2",
+ .pme_desc = "PAAM CAM miss. (Group 2)",
+ .pme_code = 0x17f0, /* 6128 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_CMD_REFLECTED_2",
+ .pme_desc = "Command reflected. (Group 2)",
+ .pme_code = 0x17f2, /* 6130 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_LOCAL_CMD_FROM_SPE6",
+ .pme_desc = "Local command from SPE 6.",
+ .pme_code = 0x1839, /* 6201 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_LOCAL_CMD_FROM_SPE4",
+ .pme_desc = "Local command from SPE 4.",
+ .pme_code = 0x183a, /* 6202 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_LOCAL_CME_FROM_SPE2",
+ .pme_desc = "Local command from SPE 2.",
+ .pme_code = 0x183b, /* 6203 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_LOCAL_CMD_FROM_PPE",
+ .pme_desc = "Local command from PPE.",
+ .pme_code = 0x183d, /* 6205 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_LOCAL_CMD_FROM_SPE1",
+ .pme_desc = "Local command from SPE 1.",
+ .pme_code = 0x183e, /* 6206 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_LOCAL_CMD_FROM_SPE3",
+ .pme_desc = "Local command from SPE 3.",
+ .pme_code = 0x183f, /* 6207 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_LOCAL_CMD_FROM_SPE5",
+ .pme_desc = "Local command from SPE 5.",
+ .pme_code = 0x1840, /* 6208 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_LOCAL_CMD_FROM_SPE7",
+ .pme_desc = "Local command from SPE 7.",
+ .pme_code = 0x1841, /* 6209 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE6",
+ .pme_desc = "AC1-to-AC0 global command from SPE 6.",
+ .pme_code = 0x1844, /* 6212 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE4",
+ .pme_desc = "AC1-to-AC0 global command from SPE 4.",
+ .pme_code = 0x1845, /* 6213 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE2",
+ .pme_desc = "AC1-to-AC0 global command from SPE 2.",
+ .pme_code = 0x1846, /* 6214 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE0",
+ .pme_desc = "AC1-to-AC0 global command from SPE 0.",
+ .pme_code = 0x1847, /* 6215 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_GLOBAL_CMD_FROM_PPE",
+ .pme_desc = "AC1-to-AC0 global command from PPE.",
+ .pme_code = 0x1848, /* 6216 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE1",
+ .pme_desc = "AC1-to-AC0 global command from SPE 1.",
+ .pme_code = 0x1849, /* 6217 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE3",
+ .pme_desc = "AC1-to-AC0 global command from SPE 3.",
+ .pme_code = 0x184a, /* 6218 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE5",
+ .pme_desc = "AC1-to-AC0 global command from SPE 5.",
+ .pme_code = 0x184b, /* 6219 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE7",
+ .pme_desc = "AC1-to-AC0 global command from SPE 7",
+ .pme_code = 0x184c, /* 6220 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_AC1_REFLECTING_LOCAL_CMD",
+ .pme_desc = "AC1 is reflecting any local command.",
+ .pme_code = 0x184e, /* 6222 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_AC1_SEND_GLOBAL_CMD",
+ .pme_desc = "AC1 sends a global command to AC0.",
+ .pme_code = 0x184f, /* 6223 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_AC0_REFLECT_GLOBAL_CMD",
+ .pme_desc = "AC0 reflects a global command back to AC1.",
+ .pme_code = 0x1850, /* 6224 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_AC1_REFLECT_CMD_TO_BM",
+ .pme_desc = "AC1 reflects a command back to the bus masters.",
+ .pme_code = 0x1851, /* 6225 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_GRANT_DATA_RING0_1",
+ .pme_desc = "Grant on data ring 0.",
+ .pme_code = 0x189c, /* 6300 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_GRANT_DATA_RING1_1",
+ .pme_desc = "Grant on data ring 1.",
+ .pme_code = 0x189d, /* 6301 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_GRANT_DATA_RING2_1",
+ .pme_desc = "Grant on data ring 2.",
+ .pme_code = 0x189e, /* 6302 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_GRANT_DATA_RING3_1",
+ .pme_desc = "Grant on data ring 3.",
+ .pme_code = 0x189f, /* 6303 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_DATA_RING0_INUSE_1",
+ .pme_desc = "Data ring 0 is in use.",
+ .pme_code = 0x18a0, /* 6304 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_DATA_RING1_INUSE_1",
+ .pme_desc = "Data ring 1 is in use.",
+ .pme_code = 0x18a1, /* 6305 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_DATA_RING2_INUSE_1",
+ .pme_desc = "Data ring 2 is in use.",
+ .pme_code = 0x18a2, /* 6306 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_DATA_RING3_INUSE_1",
+ .pme_desc = "Data ring 3 is in use.",
+ .pme_code = 0x18a3, /* 6307 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_ALL_DATA_RINGS_IDLE_1",
+ .pme_desc = "All data rings are idle.",
+ .pme_code = 0x18a4, /* 6308 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_ONE_DATA_RING_BUSY_1",
+ .pme_desc = "One data ring is busy.",
+ .pme_code = 0x18a5, /* 6309 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_TWO_OR_THREE_DATA_RINGS_BUSY_1",
+ .pme_desc = "Two or three data rings are busy.",
+ .pme_code = 0x18a6, /* 6310 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_ALL_DATA_RINGS_BUSY_1",
+ .pme_desc = "All data rings are busy.",
+ .pme_code = 0x18a7, /* 6311 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_IOIF0_DATA_REQ_PENDING_1",
+ .pme_desc = "BIC(IOIF0) data request pending.",
+ .pme_code = 0x18a8, /* 6312 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_SPE6_DATA_REQ_PENDING_1",
+ .pme_desc = "SPE 6 data request pending.",
+ .pme_code = 0x18a9, /* 6313 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_SPE4_DATA_REQ_PENDING_1",
+ .pme_desc = "SPE 4 data request pending.",
+ .pme_code = 0x18aa, /* 6314 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_SPE2_DATA_REQ_PENDING_1",
+ .pme_desc = "SPE 2 data request pending.",
+ .pme_code = 0x18ab, /* 6315 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_SPE0_DATA_REQ_PENDING_1",
+ .pme_desc = "SPE 0 data request pending.",
+ .pme_code = 0x18ac, /* 6316 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_MIC_DATA_REQ_PENDING_1",
+ .pme_desc = "MIC data request pending.",
+ .pme_code = 0x18ad, /* 6317 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_PPE_DATA_REQ_PENDING_1",
+ .pme_desc = "PPE data request pending.",
+ .pme_code = 0x18ae, /* 6318 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_SPE1_DATA_REQ_PENDING_1",
+ .pme_desc = "SPE 1 data request pending.",
+ .pme_code = 0x18af, /* 6319 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_SPE3_DATA_REQ_PENDING_1",
+ .pme_desc = "SPE 3 data request pending.",
+ .pme_code = 0x18b0, /* 6320 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_SPE5_DATA_REQ_PENDING_1",
+ .pme_desc = "SPE 5 data request pending.",
+ .pme_code = 0x18b1, /* 6321 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_SPE7_DATA_REQ_PENDING_1",
+ .pme_desc = "SPE 7 data request pending.",
+ .pme_code = 0x18b2, /* 6322 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_IOIF0_DATA_DEST_1",
+ .pme_desc = "IOIF0 is data destination.",
+ .pme_code = 0x18b4, /* 6324 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_SPE6_DATA_DEST_1",
+ .pme_desc = "SPE 6 is data destination.",
+ .pme_code = 0x18b5, /* 6325 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_SPE4_DATA_DEST_1",
+ .pme_desc = "SPE 4 is data destination.",
+ .pme_code = 0x18b6, /* 6326 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_SPE2_DATA_DEST_1",
+ .pme_desc = "SPE 2 is data destination.",
+ .pme_code = 0x18b7, /* 6327 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_SPE0_DATA_DEST_1",
+ .pme_desc = "SPE 0 is data destination.",
+ .pme_code = 0x18b8, /* 6328 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_MIC_DATA_DEST_1",
+ .pme_desc = "MIC is data destination.",
+ .pme_code = 0x18b9, /* 6329 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_PPE_DATA_DEST_1",
+ .pme_desc = "PPE is data destination.",
+ .pme_code = 0x18ba, /* 6330 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_SPE1_DATA_DEST_1",
+ .pme_desc = "SPE 1 is data destination.",
+ .pme_code = 0x18bb, /* 6331 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_IOIF0_DATA_REQ_PENDING_2",
+ .pme_desc = "BIC(IOIF0) data request pending.",
+ .pme_code = 0x1900, /* 6400 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_SPE6_DATA_REQ_PENDING_2",
+ .pme_desc = "SPE 6 data request pending.",
+ .pme_code = 0x1901, /* 6401 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_SPE4_DATA_REQ_PENDING_2",
+ .pme_desc = "SPE 4 data request pending.",
+ .pme_code = 0x1902, /* 6402 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_SPE2_DATA_REQ_PENDING_2",
+ .pme_desc = "SPE 2 data request pending.",
+ .pme_code = 0x1903, /* 6403 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_SPE0_DATA_REQ_PENDING_2",
+ .pme_desc = "SPE 0 data request pending.",
+ .pme_code = 0x1904, /* 6404 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_MIC_DATA_REQ_PENDING_2",
+ .pme_desc = "MIC data request pending.",
+ .pme_code = 0x1905, /* 6405 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_PPE_DATA_REQ_PENDING_2",
+ .pme_desc = "PPE data request pending.",
+ .pme_code = 0x1906, /* 6406 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_SPE1_DATA_REQ_PENDING_2",
+ .pme_desc = "SPE 1 data request pending.",
+ .pme_code = 0x1907, /* 6407 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_SPE3_DATA_REQ_PENDING_2",
+ .pme_desc = "SPE 3 data request pending.",
+ .pme_code = 0x1908, /* 6408 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_SPE5_DATA_REQ_PENDING_2",
+ .pme_desc = "SPE 5 data request pending.",
+ .pme_code = 0x1909, /* 6409 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_SPE7_DATA_REQ_PENDING_2",
+ .pme_desc = "SPE 7 data request pending.",
+ .pme_code = 0x190a, /* 6410 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_IOIF1_DATA_REQ_PENDING_2",
+ .pme_desc = "IOIF1 data request pending.",
+ .pme_code = 0x190b, /* 6411 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "EIB_IOIF0_DATA_DEST_2",
+ .pme_desc = "IOIF0 is data destination.",
+ .pme_code = 0x190c, /* 6412 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_SPE6_DATA_DEST_2",
+ .pme_desc = "SPE 6 is data destination.",
+ .pme_code = 0x190d, /* 6413 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_SPE4_DATA_DEST_2",
+ .pme_desc = "SPE 4 is data destination.",
+ .pme_code = 0x190e, /* 6414 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_SPE2_DATA_DEST_2",
+ .pme_desc = "SPE 2 is data destination.",
+ .pme_code = 0x190f, /* 6415 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_SPE0_DATA_DEST_2",
+ .pme_desc = "SPE 0 is data destination.",
+ .pme_code = 0x1910, /* 6416 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_MIC_DATA_DEST_2",
+ .pme_desc = "MIC is data destination.",
+ .pme_code = 0x1911, /* 6417 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_PPE_DATA_DEST_2",
+ .pme_desc = "PPE is data destination.",
+ .pme_code = 0x1912, /* 6418 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_SPE1_DATA_DEST_2",
+ .pme_desc = "SPE 1 is data destination.",
+ .pme_code = 0x1913, /* 6419 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_SPE3_DATA_DEST_2",
+ .pme_desc = "SPE 3 is data destination.",
+ .pme_code = 0x1914, /* 6420 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_SPE5_DATA_DEST_2",
+ .pme_desc = "SPE 5 is data destination.",
+ .pme_code = 0x1915, /* 6421 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_SPE7_DATA_DEST_2",
+ .pme_desc = "SPE 7 is data destination.",
+ .pme_code = 0x1916, /* 6422 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_IOIF1_DATA_DEST_2",
+ .pme_desc = "IOIF1 is data destination.",
+ .pme_code = 0x1917, /* 6423 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_GRANT_DATA_RING0_2",
+ .pme_desc = "Grant on data ring 0.",
+ .pme_code = 0x1918, /* 6424 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_GRANT_DATA_RING1_2",
+ .pme_desc = "Grant on data ring 1.",
+ .pme_code = 0x1919, /* 6425 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_GRANT_DATA_RING2_2",
+ .pme_desc = "Grant on data ring 2.",
+ .pme_code = 0x191a, /* 6426 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_GRANT_DATA_RING3_2",
+ .pme_desc = "Grant on data ring 3.",
+ .pme_code = 0x191b, /* 6427 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "EIB_ALL_DATA_RINGS_IDLE_2",
+ .pme_desc = "All data rings are idle.",
+ .pme_code = 0x191c, /* 6428 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_ONE_DATA_RING_BUSY_2",
+ .pme_desc = "One data ring is busy.",
+ .pme_code = 0x191d, /* 6429 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_TWO_OR_THREE_DATA_RINGS_BUSY_2",
+ .pme_desc = "Two or three data rings are busy.",
+ .pme_code = 0x191e, /* 6430 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_ALL_DATA_RINGS_BUSY_2",
+ .pme_desc = "All four data rings are busy.",
+ .pme_code = 0x191f, /* 6431 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_E_XIO_UNUSED",
+ .pme_desc = "Even XIO token unused by RAG 0.",
+ .pme_code = 0xfe4c, /* 65100 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_O_XIO_UNUSED",
+ .pme_desc = "Odd XIO token unused by RAG 0.",
+ .pme_code = 0xfe4d, /* 65101 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_E_BANK_UNUSED",
+ .pme_desc = "Even bank token unused by RAG 0.",
+ .pme_code = 0xfe4e, /* 65102 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_O_BANK_UNUSED",
+ .pme_desc = "Odd bank token unused by RAG 0.",
+ .pme_code = 0xfe4f, /* 65103 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_TOKEN_GRANTED_SPE0",
+ .pme_desc = "Token granted for SPE 0.",
+ .pme_code = 0xfe54, /* 65108 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_TOKEN_GRANTED_SPE1",
+ .pme_desc = "Token granted for SPE 1.",
+ .pme_code = 0xfe55, /* 65109 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_TOKEN_GRANTED_SPE2",
+ .pme_desc = "Token granted for SPE 2.",
+ .pme_code = 0xfe56, /* 65110 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_TOKEN_GRANTED_SPE3",
+ .pme_desc = "Token granted for SPE 3.",
+ .pme_code = 0xfe57, /* 65111 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_TOKEN_GRANTED_SPE4",
+ .pme_desc = "Token granted for SPE 4.",
+ .pme_code = 0xfe58, /* 65112 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_TOKEN_GRANTED_SPE5",
+ .pme_desc = "Token granted for SPE 5.",
+ .pme_code = 0xfe59, /* 65113 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_TOKEN_GRANTED_SPE6",
+ .pme_desc = "Token granted for SPE 6.",
+ .pme_code = 0xfe5a, /* 65114 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_TOKEN_GRANTED_SPE7",
+ .pme_desc = "Token granted for SPE 7.",
+ .pme_code = 0xfe5b, /* 65115 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_E_XIO_WASTED",
+ .pme_desc = "Even XIO token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register.",
+ .pme_code = 0xfeb0, /* 65200 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_O_XIO_WASTED",
+ .pme_desc = "Odd XIO token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register.",
+ .pme_code = 0xfeb1, /* 65201 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_E_BANK_WASTED",
+ .pme_desc = "Even bank token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register.",
+ .pme_code = 0xfeb2, /* 65202 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_O_BANK_WASTED",
+ .pme_desc = "Odd bank token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register.",
+ .pme_code = 0xfeb3, /* 65203 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAGU_E_XIO_WASTED",
+ .pme_desc = "Even XIO token wasted by RAG U.",
+ .pme_code = 0xfebc, /* 65212 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAGU_O_XIO_WASTED",
+ .pme_desc = "Odd XIO token wasted by RAG U.",
+ .pme_code = 0xfebd, /* 65213 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAGU_E_BANK_WASTED",
+ .pme_desc = "Even bank token wasted by RAG U.",
+ .pme_code = 0xfebe, /* 65214 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAGU_O_BANK_WASTED",
+ .pme_desc = "Odd bank token wasted by RAG U.",
+ .pme_code = 0xfebf, /* 65215 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_E_XIO_RAG1",
+ .pme_desc = "Even XIO token from RAG 0 shared with RAG 1",
+ .pme_code = 0xff14, /* 65300 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_E_XIO_RAG2",
+ .pme_desc = "Even XIO token from RAG 0 shared with RAG 2",
+ .pme_code = 0xff15, /* 65301 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_E_XIO_RAG3",
+ .pme_desc = "Even XIO token from RAG 0 shared with RAG 3",
+ .pme_code = 0xff16, /* 65302 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_O_XIO_RAG1",
+ .pme_desc = "Odd XIO token from RAG 0 shared with RAG 1",
+ .pme_code = 0xff17, /* 65303 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_O_XIO_RAG2",
+ .pme_desc = "Odd XIO token from RAG 0 shared with RAG 2",
+ .pme_code = 0xff18, /* 65304 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_O_XIO_RAG3",
+ .pme_desc = "Odd XIO token from RAG 0 shared with RAG 3",
+ .pme_code = 0xff19, /* 65305 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_E_BANK_RAG1",
+ .pme_desc = "Even bank token from RAG 0 shared with RAG 1",
+ .pme_code = 0xff1a, /* 65306 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_E_BANK_RAG2",
+ .pme_desc = "Even bank token from RAG 0 shared with RAG 2",
+ .pme_code = 0xff1b, /* 65307 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_E_BANK_RAG3",
+ .pme_desc = "Even bank token from RAG 0 shared with RAG 3",
+ .pme_code = 0xff1c, /* 65308 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_O_BANK_RAG1",
+ .pme_desc = "Odd bank token from RAG 0 shared with RAG 1",
+ .pme_code = 0xff1d, /* 65309 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_O_BANK_RAG2",
+ .pme_desc = "Odd bank token from RAG 0 shared with RAG 2",
+ .pme_code = 0xff1e, /* 65310 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_O_BANK_RAG3",
+ .pme_desc = "Odd bank token from RAG 0 shared with RAG 3",
+ .pme_code = 0xff1f, /* 65311 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG1_E_XIO_UNUSED",
+ .pme_desc = "Even XIO token was unused by RAG 1.",
+ .pme_code = 0xff88, /* 65416 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG1_O_XIO_UNUSED",
+ .pme_desc = "Odd XIO token was unused by RAG 1.",
+ .pme_code = 0xff89, /* 65417 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG1_E_BANK_UNUSED",
+ .pme_desc = "Even bank token was unused by RAG 1.",
+ .pme_code = 0xff8a, /* 65418 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG1_O_BANK_UNUSED",
+ .pme_desc = "Odd bank token was unused by RAG 1.",
+ .pme_code = 0xff8b, /* 65419 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_TOKEN_GRANTED_IOC0",
+ .pme_desc = "Token was granted for IOC0.",
+ .pme_code = 0xff91, /* 65425 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_TOKEN_GRANTED_IOC1",
+ .pme_desc = "Token was granted for IOC1.",
+ .pme_code = 0xff92, /* 65426 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG1_E_XIO_WASTED",
+ .pme_desc = "Even XIO token was wasted by RAG 1. This is valid only when UE = 1 in TKM_CR.",
+ .pme_code = 0xffec, /* 65516 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG1_O_XIO_WASTED",
+ .pme_desc = "Odd XIO token was wasted by RAG 1. This is valid only when UE = 1 in TKM_CR.",
+ .pme_code = 0xffed, /* 65517 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG1_E_BANK_WASTED",
+ .pme_desc = "Even bank token was wasted by RAG 1. This is valid only when UE = 1 in TKM_CR.",
+ .pme_code = 0xffee, /* 65518 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG1_O_BANK_WASTED",
+ .pme_desc = "Odd bank token was wasted by RAG 1. This is valid only when UE = 1 in TKM_CR.",
+ .pme_code = 0xffef, /* 65519 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG1_E_XIO_RAG0",
+ .pme_desc = "Even XIO token from RAG 1 shared with RAG 0",
+ .pme_code = 0x10050, /* 65616 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG1_E_XIO_RAG2",
+ .pme_desc = "Even XIO token from RAG 1 shared with RAG 2",
+ .pme_code = 0x10051, /* 65617 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG1_E_XIO_RAG3",
+ .pme_desc = "Even XIO token from RAG 1 shared with RAG 3",
+ .pme_code = 0x10052, /* 65618 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG1_O_XIO_RAG0",
+ .pme_desc = "Odd XIO token from RAG 1 shared with RAG 0",
+ .pme_code = 0x10053, /* 65619 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG1_O_XIO_RAG2",
+ .pme_desc = "Odd XIO token from RAG 1 shared with RAG 2",
+ .pme_code = 0x10054, /* 65620 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG1_O_XIO_RAG3",
+ .pme_desc = "Odd XIO token from RAG 1 shared with RAG 3",
+ .pme_code = 0x10055, /* 65621 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG1_E_BANK_RAG0",
+ .pme_desc = "Even bank token from RAG 1 shared with RAG 0",
+ .pme_code = 0x10056, /* 65622 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG1_E_BANK_RAG2",
+ .pme_desc = "Even bank token from RAG 1 shared with RAG 2",
+ .pme_code = 0x10057, /* 65623 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG1_E_BANK_RAG3",
+ .pme_desc = "Even bank token from RAG 1 shared with RAG 3",
+ .pme_code = 0x10058, /* 65624 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG1_O_BANK_RAG0",
+ .pme_desc = "Odd bank token from RAG 1 shared with RAG 0",
+ .pme_code = 0x10059, /* 65625 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG1_O_BANK_RAG2",
+ .pme_desc = "Odd bank token from RAG 1 shared with RAG 2",
+ .pme_code = 0x1005a, /* 65626 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG1_O_BANK_RAG3",
+ .pme_desc = "Odd bank token from RAG 1 shared with RAG 3",
+ .pme_code = 0x1005b, /* 65627 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAGU_E_XIO_RAG1",
+ .pme_desc = "Even XIO token from RAG U shared with RAG 1",
+ .pme_code = 0x1005c, /* 65628 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAGU_O_XIO_RAG1",
+ .pme_desc = "Odd XIO token from RAG U shared with RAG 1",
+ .pme_code = 0x1005d, /* 65629 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAGU_E_BANK_RAG1",
+ .pme_desc = "Even bank token from RAG U shared with RAG 1",
+ .pme_code = 0x1005e, /* 65630 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAGU_O_BANK_RAG1",
+ .pme_desc = "Odd bank token from RAG U shared with RAG 1",
+ .pme_code = 0x1005f, /* 65631 */
+ .pme_enable_word = WORD_0_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG2_E_XIO_UNUSED",
+ .pme_desc = "Even XIO token unused by RAG 2",
+ .pme_code = 0x100e4, /* 65764 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG2_O_XIO_UNUSED",
+ .pme_desc = "Odd XIO token unused by RAG 2",
+ .pme_code = 0x100e5, /* 65765 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG2_E_BANK_UNUSED",
+ .pme_desc = "Even bank token unused by RAG 2",
+ .pme_code = 0x100e6, /* 65766 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG2_O_BANK_UNUSED",
+ .pme_desc = "Odd bank token unused by RAG 2",
+ .pme_code = 0x100e7, /* 65767 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_IOIF0_IN_TOKEN_UNUSED",
+ .pme_desc = "IOIF0 In token unused by RAG 0",
+ .pme_code = 0x100e8, /* 65768 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_IOIF0_OUT_TOKEN_UNUSED",
+ .pme_desc = "IOIF0 Out token unused by RAG 0",
+ .pme_code = 0x100e9, /* 65769 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_IOIF1_IN_TOKEN_UNUSED",
+ .pme_desc = "IOIF1 In token unused by RAG 0",
+ .pme_code = 0x100ea, /* 65770 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_IOIF1_OUT_TOKEN_UNUSED",
+ .pme_desc = "IOIF1 Out token unused by RAG 0",
+ .pme_code = 0x100eb, /* 65771 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG2_E_XIO_WASTED",
+ .pme_desc = "Even XIO token wasted by RAG 2",
+ .pme_code = 0x10148, /* 65864 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG2_O_XIO_WASTED",
+ .pme_desc = "Odd XIO token wasted by RAG 2",
+ .pme_code = 0x10149, /* 65865 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG2_E_BANK_WASTED",
+ .pme_desc = "Even bank token wasted by RAG 2",
+ .pme_code = 0x1014a, /* 65866 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG2_O_BANK_WASTED",
+ .pme_desc = "Odd bank token wasted by RAG 2",
+ .pme_code = 0x1014b, /* 65867 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG2_E_XIO_RAG0",
+ .pme_desc = "Even XIO token from RAG 2 shared with RAG 0",
+ .pme_code = 0x101ac, /* 65964 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG2_E_XIO_RAG1",
+ .pme_desc = "Even XIO token from RAG 2 shared with RAG 1",
+ .pme_code = 0x101ad, /* 65965 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG2_E_XIO_RAG3",
+ .pme_desc = "Even XIO token from RAG 2 shared with RAG 3",
+ .pme_code = 0x101ae, /* 65966 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG2_O_XIO_RAG0",
+ .pme_desc = "Odd XIO token from RAG 2 shared with RAG 0",
+ .pme_code = 0x101af, /* 65967 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG2_O_XIO_RAG1",
+ .pme_desc = "Odd XIO token from RAG 2 shared with RAG 1",
+ .pme_code = 0x101b0, /* 65968 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG2_O_XIO_RAG3",
+ .pme_desc = "Odd XIO token from RAG 2 shared with RAG 3",
+ .pme_code = 0x101b1, /* 65969 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG2_E_BANK_RAG0",
+ .pme_desc = "Even bank token from RAG 2 shared with RAG 0",
+ .pme_code = 0x101b2, /* 65970 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG2_E_BANK_RAG1",
+ .pme_desc = "Even bank token from RAG 2 shared with RAG 1",
+ .pme_code = 0x101b3, /* 65971 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG2_E_BANK_RAG3",
+ .pme_desc = "Even bank token from RAG 2 shared with RAG 3",
+ .pme_code = 0x101b4, /* 65972 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG2_O_BANK_RAG0",
+ .pme_desc = "Odd bank token from RAG 2 shared with RAG 0",
+ .pme_code = 0x101b5, /* 65973 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG2_O_BANK_RAG1",
+ .pme_desc = "Odd bank token from RAG 2 shared with RAG 1",
+ .pme_code = 0x101b6, /* 65974 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG2_O_BANK_RAG3",
+ .pme_desc = "Odd bank token from RAG 2 shared with RAG 3",
+ .pme_code = 0x101b7, /* 65975 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_IOIF0_IN_TOKEN_WASTED",
+ .pme_desc = "IOIF0 In token wasted by RAG 0",
+ .pme_code = 0x9ef38, /* 651064 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_IOIF0_OUT_TOKEN_WASTED",
+ .pme_desc = "IOIF0 Out token wasted by RAG 0",
+ .pme_code = 0x9ef39, /* 651065 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_IOIF1_IN_TOKEN_WASTED",
+ .pme_desc = "IOIF1 In token wasted by RAG 0",
+ .pme_code = 0x9ef3a, /* 651066 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG0_IOIF1_OUT_TOKEN_WASTED",
+ .pme_desc = "IOIF1 Out token wasted by RAG 0",
+ .pme_code = 0x9ef3b, /* 651067 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG3_E_XIO_UNUSED",
+ .pme_desc = "Even XIO token was unused by RAG 3.",
+ .pme_code = 0x9efac, /* 651180 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG3_O_XIO_UNUSED",
+ .pme_desc = "Odd XIO token was unused by RAG 3.",
+ .pme_code = 0x9efad, /* 651181 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG3_E_BANK_UNUSED",
+ .pme_desc = "Even bank token was unused by RAG 3.",
+ .pme_code = 0x9efae, /* 651182 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG3_O_BANK_UNUSED",
+ .pme_desc = "Odd bank token was unused by RAG 3.",
+ .pme_code = 0x9efaf, /* 651183 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG3_E_XIO_WASTED",
+ .pme_desc = "Even XIO token wasted by RAG 3",
+ .pme_code = 0x9f010, /* 651280 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG3_O_XIO_WASTED",
+ .pme_desc = "Odd XIO token wasted by RAG 3",
+ .pme_code = 0x9f011, /* 651281 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG3_E_BANK_WASTED",
+ .pme_desc = "Even bank token wasted by RAG 3",
+ .pme_code = 0x9f012, /* 651282 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG3_O_BANK_WASTED",
+ .pme_desc = "Odd bank token wasted by RAG 3",
+ .pme_code = 0x9f013, /* 651283 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG3_E_XIO_RAG0",
+ .pme_desc = "Even XIO token from RAG 3 shared with RAG 0",
+ .pme_code = 0x9f074, /* 651380 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG3_E_XIO_RAG1",
+ .pme_desc = "Even XIO token from RAG 3 shared with RAG 1",
+ .pme_code = 0x9f075, /* 651381 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG3_E_XIO_RAG2",
+ .pme_desc = "Even XIO token from RAG 3 shared with RAG 2",
+ .pme_code = 0x9f076, /* 651382 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG3_O_XIO_RAG0",
+ .pme_desc = "Odd XIO token from RAG 3 shared with RAG 0",
+ .pme_code = 0x9f077, /* 651383 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG3_O_XIO_RAG1",
+ .pme_desc = "Odd XIO token from RAG 3 shared with RAG 1",
+ .pme_code = 0x9f078, /* 651384 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG3_O_XIO_RAG2",
+ .pme_desc = "Odd XIO token from RAG 3 shared with RAG 2",
+ .pme_code = 0x9f079, /* 651385 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG3_E_BANK_RAG0",
+ .pme_desc = "Even bank token from RAG 3 shared with RAG 0",
+ .pme_code = 0x9f07a, /* 651386 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG3_E_BANK_RAG1",
+ .pme_desc = "Even bank token from RAG 3 shared with RAG 1",
+ .pme_code = 0x9f07b, /* 651387 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG3_E_BANK_RAG2",
+ .pme_desc = "Even bank token from RAG 3 shared with RAG 2",
+ .pme_code = 0x9f07c, /* 651388 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG3_O_BANK_RAG0",
+ .pme_desc = "Odd bank token from RAG 3 shared with RAG 0",
+ .pme_code = 0x9f07d, /* 651389 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG3_O_BANK_RAG1",
+ .pme_desc = "Odd bank token from RAG 3 shared with RAG 1",
+ .pme_code = 0x9f07e, /* 651390 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "EIB_RAG3_O_BANK_RAG2",
+ .pme_desc = "Odd bank token from RAG 3 shared with RAG 2",
+ .pme_code = 0x9f07f, /* 651391 */
+ .pme_enable_word = WORD_2_ONLY,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO1_READ_CMD_Q_EMPTY",
+ .pme_desc = "XIO1 - Read command queue is empty.",
+ .pme_code = 0x1bc5, /* 7109 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO1_WRITE_CMD_Q_EMPTY",
+ .pme_desc = "XIO1 - Write command queue is empty.",
+ .pme_code = 0x1bc6, /* 7110 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO1_READ_CMD_Q_FULL",
+ .pme_desc = "XIO1 - Read command queue is full.",
+ .pme_code = 0x1bc8, /* 7112 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO1_RESPONDS_READ_RETRY",
+ .pme_desc = "XIO1 - MIC responds with a Retry for a read command because the read command queue is full.",
+ .pme_code = 0x1bc9, /* 7113 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO1_WRITE_CMD_Q_FULL",
+ .pme_desc = "XIO1 - Write command queue is full.",
+ .pme_code = 0x1bca, /* 7114 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO1_RESPONDS_WRITE_RETRY",
+ .pme_desc = "XIO1 - MIC responds with a Retry for a write command because the write command queue is full.",
+ .pme_code = 0x1bcb, /* 7115 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO1_READ_CMD_DISPATCHED",
+ .pme_desc = "XIO1 - Read command dispatched; includes high-priority and fast-path reads.",
+ .pme_code = 0x1bde, /* 7134 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO1_WRITE_CMD_DISPATCHED",
+ .pme_desc = "XIO1 - Write command dispatched.",
+ .pme_code = 0x1bdf, /* 7135 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO1_READ_MOD_WRITE_CMD_DISPATCHED",
+ .pme_desc = "XIO1 - Read-Modify-Write command (data size < 16 bytes) dispatched.",
+ .pme_code = 0x1be0, /* 7136 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO1_REFRESH_DISPATCHED",
+ .pme_desc = "XIO1 - Refresh dispatched.",
+ .pme_code = 0x1be1, /* 7137 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO1_BYTE_MSK_WRITE_CMD_DISPATCHED",
+ .pme_desc = "XIO1 - Byte-masking write command (data size >= 16 bytes) dispatched.",
+ .pme_code = 0x1be3, /* 7139 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO1_WRITE_CMD_DISPATCHED_AFTER_READ",
+ .pme_desc = "XIO1 - Write command dispatched after a read command was previously dispatched.",
+ .pme_code = 0x1be5, /* 7141 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO1_READ_CMD_DISPATCHED_AFTER_WRITE",
+ .pme_desc = "XIO1 - Read command dispatched after a write command was previously dispatched.",
+ .pme_code = 0x1be6, /* 7142 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO0_READ_CMD_Q_EMPTY",
+ .pme_desc = "XIO0 - Read command queue is empty.",
+ .pme_code = 0x1c29, /* 7209 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO0_WRITE_CMD_Q_EMPTY",
+ .pme_desc = "XIO0 - Write command queue is empty.",
+ .pme_code = 0x1c2a, /* 7210 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO0_READ_CMD_Q_FULL",
+ .pme_desc = "XIO0 - Read command queue is full.",
+ .pme_code = 0x1c2c, /* 7212 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO0_RESPONDS_READ_RETRY",
+ .pme_desc = "XIO0 - MIC responds with a Retry for a read command because the read command queue is full.",
+ .pme_code = 0x1c2d, /* 7213 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO0_WRITE_CMD_Q_FULL",
+ .pme_desc = "XIO0 - Write command queue is full.",
+ .pme_code = 0x1c2e, /* 7214 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO0_RESPONDS_WRITE_RETRY",
+ .pme_desc = "XIO0 - MIC responds with a Retry for a write command because the write command queue is full.",
+ .pme_code = 0x1c2f, /* 7215 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO0_READ_CMD_DISPATCHED",
+ .pme_desc = "XIO0 - Read command dispatched; includes high-priority and fast-path reads.",
+ .pme_code = 0x1c42, /* 7234 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO0_WRITE_CMD_DISPATCHED",
+ .pme_desc = "XIO0 - Write command dispatched.",
+ .pme_code = 0x1c43, /* 7235 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO0_READ_MOD_WRITE_CMD_DISPATCHED",
+ .pme_desc = "XIO0 - Read-Modify-Write command (data size < 16 bytes) dispatched.",
+ .pme_code = 0x1c44, /* 7236 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO0_REFRESH_DISPATCHED",
+ .pme_desc = "XIO0 - Refresh dispatched.",
+ .pme_code = 0x1c45, /* 7237 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO0_WRITE_CMD_DISPATCHED_AFTER_READ",
+ .pme_desc = "XIO0 - Write command dispatched after a read command was previously dispatched.",
+ .pme_code = 0x1c49, /* 7241 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO0_READ_CMD_DISPATCHED_AFTER_WRITE",
+ .pme_desc = "XIO0 - Read command dispatched after a write command was previously dispatched.",
+ .pme_code = 0x1c4a, /* 7242 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO0_WRITE_CMD_DISPATCHED_2",
+ .pme_desc = "XIO0 - Write command dispatched.",
+ .pme_code = 0x1ca7, /* 7335 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO0_READ_MOD_WRITE_CMD_DISPATCHED_2",
+ .pme_desc = "XIO0 - Read-Modify-Write command (data size < 16 bytes) dispatched.",
+ .pme_code = 0x1ca8, /* 7336 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO0_REFRESH_DISPATCHED_2",
+ .pme_desc = "XIO0 - Refresh dispatched.",
+ .pme_code = 0x1ca9, /* 7337 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "MIC_XIO0_BYTE_MSK_WRITE_CMD_DISPATCHED",
+ .pme_desc = "XIO0 - Byte-masking write command (data size >= 16 bytes) dispatched.",
+ .pme_code = 0x1cab, /* 7339 */
+ .pme_enable_word = 0xF,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF0_TYPEA_DATA_PLG",
+ .pme_desc = "Type A data physical layer group (PLG). Does not include header-only or credit-only data PLGs. In IOIF mode, counts I/O device read data; in BIF mode, counts all outbound data.",
+ .pme_code = 0x1fb0, /* 8112 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF0_TYPEB_DATA_PLG",
+ .pme_desc = "Type B data PLG. In IOIF mode, counts I/O device read data; in BIF mode, counts all outbound data.",
+ .pme_code = 0x1fb1, /* 8113 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF0_IOIF_TYPEA_DATA_PLG",
+ .pme_desc = "Type A data PLG. Does not include header-only or credit-only PLGs. In IOIF mode, counts CBE store data to I/O device. Does not apply in BIF mode.",
+ .pme_code = 0x1fb2, /* 8114 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF0_IOIF_TYPEB_DATA_PLG",
+ .pme_desc = "Type B data PLG. In IOIF mode, counts CBE store data to an I/O device. Does not apply in BIF mode.",
+ .pme_code = 0x1fb3, /* 8115 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF0_DATA_PLG",
+ .pme_desc = "Data PLG. Does not include header-only or credit-only PLGs.",
+ .pme_code = 0x1fb4, /* 8116 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF0_CMD_PLG",
+ .pme_desc = "Command PLG (no credit-only PLG). In IOIF mode, counts I/O command or reply PLGs. In BIF mode, counts command/ reflected command or snoop/combined responses.",
+ .pme_code = 0x1fb5, /* 8117 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF0_TYPEA_TRANSFER",
+ .pme_desc = "Type A data transfer regardless of length. Can also be used to count Type A data header PLGs (but not credit-only PLGs).",
+ .pme_code = 0x1fb6, /* 8118 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF0_TYPEB_TRANSFER",
+ .pme_desc = "Type B data transfer.",
+ .pme_code = 0x1fb7, /* 8119 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF0_CMD_GREDIT_ONLY_PLG",
+ .pme_desc = "Command-credit-only command PLG in either IOIF or BIF mode.",
+ .pme_code = 0x1fb8, /* 8120 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF0_DATA_CREDIT_ONLY_PLG",
+ .pme_desc = "Data-credit-only data PLG sent in either IOIF or BIF mode.",
+ .pme_code = 0x1fb9, /* 8121 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF0_NON_NULL_ENVLP_SENT",
+ .pme_desc = "Non-null envelope sent (does not include long envelopes).",
+ .pme_code = 0x1fba, /* 8122 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF0_NULL_ENVLP_SENT",
+ .pme_desc = "Null envelope sent.",
+ .pme_code = 0x1fbc, /* 8124 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "BIF_IOIF0_NO_VALID_DATA_SENT",
+ .pme_desc = "No valid data sent this cycle.",
+ .pme_code = 0x1fbd, /* 8125 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "BIF_IOIF0_NORMAL_ENVLP_SENT",
+ .pme_desc = "Normal envelope sent.",
+ .pme_code = 0x1fbe, /* 8126 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "BIF_IOIF0_LONG_ENVLP_SENT",
+ .pme_desc = "Long envelope sent.",
+ .pme_code = 0x1fbf, /* 8127 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "BIF_IOIF0_NULL_PLG_INSERTED",
+ .pme_desc = "A Null PLG inserted in an outgoing envelope.",
+ .pme_code = 0x1fc0, /* 8128 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "BIF_IOIF0_OUTBOUND_ENV_ARRAY_FULL",
+ .pme_desc = "Outbound envelope array is full.",
+ .pme_code = 0x1fc1, /* 8129 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF1_TYPEB_TRANSFER",
+ .pme_desc = "Type B data transfer.",
+ .pme_code = 0x201b, /* 8219 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF0_NULL_ENVLP_RECV",
+ .pme_desc = "Null envelope received.",
+ .pme_code = 0x206d, /* 8301 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "BIF_IOIF0_CMD_PLG_2",
+ .pme_desc = "Command PLG, but not credit-only PLG. In IOIF mode, counts I/O command or reply PLGs. In BIF mode, counts command/reflected command or snoop/combined responses.",
+ .pme_code = 0x207a, /* 8314 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF0_CMD_GREDIT_ONLY_PLG_2",
+ .pme_desc = "Command-credit-only command PLG.",
+ .pme_code = 0x207b, /* 8315 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF0_NORMAL_ENVLP_RECV",
+ .pme_desc = "Normal envelope received is good.",
+ .pme_code = 0x2080, /* 8320 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "BIF_IOIF0_LONG_ENVLP_RECV",
+ .pme_desc = "Long envelope received is good.",
+ .pme_code = 0x2081, /* 8321 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "BIF_IOIF0_DATA_GREDIT_ONLY_PLG_2",
+ .pme_desc = "Data-credit-only data PLG in either IOIF or BIF mode; will count a maximum of one per envelope.",
+ .pme_code = 0x2082, /* 8322 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF0_NON_NULL_ENVLP",
+ .pme_desc = "Non-null envelope; does not include long envelopes; includes retried envelopes.",
+ .pme_code = 0x2083, /* 8323 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF0_DATA_GRANT_RECV",
+ .pme_desc = "Data grant received.",
+ .pme_code = 0x2084, /* 8324 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF0_DATA_PLG_2",
+ .pme_desc = "Data PLG. Does not include header-only or credit-only PLGs.",
+ .pme_code = 0x2088, /* 8328 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF0_TYPEA_TRANSFER_2",
+ .pme_desc = "Type A data transfer regardless of length. Can also be used to count Type A data header PLGs, but not credit-only PLGs.",
+ .pme_code = 0x2089, /* 8329 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF0_TYPEB_TRANSFER_2",
+ .pme_desc = "Type B data transfer.",
+ .pme_code = 0x208a, /* 8330 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF1_NULL_ENVLP_RECV",
+ .pme_desc = "Null envelope received.",
+ .pme_code = 0x20d1, /* 8401 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "BIF_IOIF1_CMD_PLG_2",
+ .pme_desc = "Command PLG (no credit-only PLG). Counts I/O command or reply PLGs.",
+ .pme_code = 0x20de, /* 8414 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF1_CMD_GREDIT_ONLY_PLG_2",
+ .pme_desc = "Command-credit-only command PLG.",
+ .pme_code = 0x20df, /* 8415 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF1_NORMAL_ENVLP_RECV",
+ .pme_desc = "Normal envelope received is good.",
+ .pme_code = 0x20e4, /* 8420 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "BIF_IOIF1_LONG_ENVLP_RECV",
+ .pme_desc = "Long envelope received is good.",
+ .pme_code = 0x20e5, /* 8421 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "BIF_IOIF1_DATA_GREDIT_ONLY_PLG_2",
+ .pme_desc = "Data-credit-only data PLG received; will count a maximum of one per envelope.",
+ .pme_code = 0x20e6, /* 8422 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF1_NON_NULL_ENVLP",
+ .pme_desc = "Non-Null envelope received; does not include long envelopes; includes retried envelopes.",
+ .pme_code = 0x20e7, /* 8423 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF1_DATA_GRANT_RECV",
+ .pme_desc = "Data grant received.",
+ .pme_code = 0x20e8, /* 8424 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF1_DATA_PLG_2",
+ .pme_desc = "Data PLG received. Does not include header-only or credit-only PLGs.",
+ .pme_code = 0x20ec, /* 8428 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF1_TYPEA_TRANSFER_2",
+ .pme_desc = "Type I A data transfer regardless of length. Can also be used to count Type A data header PLGs (but not credit-only PLGs).",
+ .pme_code = 0x20ed, /* 8429 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "BIF_IOIF1_TYPEB_TRANSFER_2",
+ .pme_desc = "Type B data transfer received.",
+ .pme_code = 0x20ee, /* 8430 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "IOC_MMIO_READ_IOIF1",
+ .pme_desc = "Received MMIO read targeted to IOIF1.",
+ .pme_code = 0x213c, /* 8508 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "IOC_MMIO_WRITE_IOIF1",
+ .pme_desc = "Received MMIO write targeted to IOIF1.",
+ .pme_code = 0x213d, /* 8509 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "IOC_MMIO_READ_IOIF0",
+ .pme_desc = "Received MMIO read targeted to IOIF0.",
+ .pme_code = 0x213e, /* 8510 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "IOC_MMIO_WRITE_IOIF0",
+ .pme_desc = "Received MMIO write targeted to IOIF0.",
+ .pme_code = 0x213f, /* 8511 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "IOC_CMD_TO_IOIF0",
+ .pme_desc = "Sent command to IOIF0.",
+ .pme_code = 0x2140, /* 8512 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "IOC_CMD_TO_IOIF1",
+ .pme_desc = "Sent command to IOIF1.",
+ .pme_code = 0x2141, /* 8513 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "IOC_IOIF0_MATRIX3_OCCUPIED",
+ .pme_desc = "IOIF0 Dependency Matrix 3 is occupied by a dependent command.",
+ .pme_code = 0x219d, /* 8605 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "IOC_IOIF0_MATRIX4_OCCUPIED",
+ .pme_desc = "IOIF0 Dependency Matrix 4 is occupied by a dependent command.",
+ .pme_code = 0x219e, /* 8606 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "IOC_IOIF0_MATRIX5_OCCUPIED",
+ .pme_desc = "IOIF0 Dependency Matrix 5 is occupied by a dependent command.",
+ .pme_code = 0x219f, /* 8607 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_BOTH_TYPE,
+ },
+ {.pme_name = "IOC_DMA_READ_IOIF0",
+ .pme_desc = "Received read request from IOIF0.",
+ .pme_code = 0x21a2, /* 8610 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "IOC_DMA_WRITE_IOIF0",
+ .pme_desc = "Received write request from IOIF0.",
+ .pme_code = 0x21a3, /* 8611 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "IOC_INTERRUPT_IOIF0",
+ .pme_desc = "Received interrupt from the IOIF0.",
+ .pme_code = 0x21a6, /* 8614 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "IOC_IOIF0_REQ_TOKEN_E_MEM",
+ .pme_desc = "IOIF0 request for token for even memory banks 0-14.",
+ .pme_code = 0x220c, /* 8716 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "IOC_IOIF0_REQ_TOKEN_O_MEM",
+ .pme_desc = "IOIF0 request for token for odd memory banks 1-15.",
+ .pme_code = 0x220d, /* 8717 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "IOC_IOIF0_REQ_TOKEN_1357",
+ .pme_desc = "IOIF0 request for token type 1, 3, 5, or 7.",
+ .pme_code = 0x220e, /* 8718 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "IOC_IOIF0_REQ_TOKEN_9111315",
+ .pme_desc = "IOIF0 request for token type 9, 11, 13, or 15.",
+ .pme_code = 0x220f, /* 8719 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "IOC_IOIF0_REQ_TOKEN_16",
+ .pme_desc = "IOIF0 request for token type 16.",
+ .pme_code = 0x2214, /* 8724 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "IOC_IOIF0_REQ_TOKEN_17",
+ .pme_desc = "IOIF0 request for token type 17.",
+ .pme_code = 0x2215, /* 8725 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "IOC_IOIF0_REQ_TOKEN_18",
+ .pme_desc = "IOIF0 request for token type 18.",
+ .pme_code = 0x2216, /* 8726 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "IOC_IOIF0_REQ_TOKEN_19",
+ .pme_desc = "IOIF0 request for token type 19.",
+ .pme_code = 0x2217, /* 8727 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_CUMULATIVE_LEN,
+ },
+ {.pme_name = "IOC_IOPT_CACHE_HIT",
+ .pme_desc = "I/O page table cache hit for commands from IOIF.",
+ .pme_code = 0x2260, /* 8800 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "IOC_IOPT_CACHE_MISS",
+ .pme_desc = "I/O page table cache miss for commands from IOIF.",
+ .pme_code = 0x2261, /* 8801 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "IOC_IOST_CACHE_HIT",
+ .pme_desc = "I/O segment table cache hit.",
+ .pme_code = 0x2263, /* 8803 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "IOC_IOST_CACHE_MISS",
+ .pme_desc = "I/O segment table cache miss.",
+ .pme_code = 0x2264, /* 8804 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "IOC_INTERRUPT_FROM_SPU",
+ .pme_desc = "Interrupt received from any SPU (reflected cmd when IIC has sent ACK response).",
+ .pme_code = 0x2278, /* 8824 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "IOC_IIC_INTERRUPT_TO_PPU_TH0",
+ .pme_desc = "Internal interrupt controller (IIC) generated interrupt to PPU thread 0.",
+ .pme_code = 0x2279, /* 8825 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "IOC_IIC_INTERRUPT_TO_PPU_TH1",
+ .pme_desc = "IIC generated interrupt to PPU thread 1.",
+ .pme_code = 0x227a, /* 8826 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "IOC_RECV_EXTERNAL_INTERRUPT_TO_TH0",
+ .pme_desc = "Received external interrupt (using MMIO) from PPU to PPU thread 0.",
+ .pme_code = 0x227b, /* 8827 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
+ {.pme_name = "IOC_RECV_EXTERNAL_INTERRUPT_TO_TH1",
+ .pme_desc = "Received external interrupt (using MMIO) from PPU to PPU thread 1.",
+ .pme_code = 0x227c, /* 8828 */
+ .pme_enable_word = WORD_0_AND_2,
+ .pme_freq = PFM_CELL_PME_FREQ_HALF,
+ .pme_type = COUNT_TYPE_OCCURRENCE,
+ },
};
-#define PME_CELL_EVENT_COUNT (sizeof(cell_pe)/sizeof(pme_cell_entry_t))
+/*--- The number of events : 435 ---*/
+#define PME_CELL_EVENT_COUNT (sizeof(cell_pe)/sizeof(pme_cell_entry_t))
diff --git a/src/libpfm-3.y/lib/core_events.h b/src/libpfm-3.y/lib/core_events.h
index 0e3aa3806b5564a4abf887e04a61958c9fe0e2e7..a701b3ccfc1e934afad95d89bd0e8d974e733dae 100644
--- a/src/libpfm-3.y/lib/core_events.h
+++ b/src/libpfm-3.y/lib/core_events.h
@@ -25,7 +25,7 @@
#define INTEL_CORE_MESI_UMASKS \
{ .pme_uname = "MESI",\
- .pme_udesc = "Any cacheline access",\
+ .pme_udesc = "Any cacheline access (default)",\
.pme_ucode = 0xf\
},\
{ .pme_uname = "I_STATE",\
@@ -87,13 +87,13 @@ static pme_core_entry_t core_pe[]={
},
{.pme_name = "INSTRUCTIONS_RETIRED",
.pme_code = 0x00c0,
- .pme_flags = PFMLIB_CORE_FIXED0|PFMLIB_CORE_PEBS,
- .pme_desc = "count the number of instructions at retirement. For instructions that consists of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Alias to event INST_RETIRED:ANY_P",
+ .pme_flags = PFMLIB_CORE_FIXED0,
+ .pme_desc = "count the number of instructions at retirement. Alias to event INST_RETIRED:ANY_P",
},
{.pme_name = "UNHALTED_REFERENCE_CYCLES",
.pme_code = 0x013c,
- .pme_flags = PFMLIB_CORE_FIXED2,
- .pme_desc = "Unhalted reference cycles. Measures bus cycles. Alias to event CPU_CLK_UNHALTED:BUS",
+ .pme_flags = PFMLIB_CORE_FIXED2_ONLY,
+ .pme_desc = "Unhalted reference cycles. Alias to event CPU_CLK_UNHALTED:REF",
},
{.pme_name = "LAST_LEVEL_CACHE_REFERENCES",
.pme_code = 0x4f2e,
@@ -114,6 +114,9 @@ static pme_core_entry_t core_pe[]={
/*
* END: architected events
*/
+ /*
+ * BEGIN: Core 2 Duo events
+ */
{ .pme_name = "RS_UOPS_DISPATCHED_CYCLES",
.pme_code = 0xa1,
.pme_flags = PFMLIB_CORE_PMC0,
@@ -132,7 +135,7 @@ static pme_core_entry_t core_pe[]={
.pme_ucode = 0x4
},
{ .pme_uname = "PORT_3",
- .pme_udesc = "on port 0",
+ .pme_udesc = "on port 3",
.pme_ucode = 0x8
},
{ .pme_uname = "PORT_4",
@@ -155,9 +158,10 @@ static pme_core_entry_t core_pe[]={
.pme_code = 0xa0,
.pme_desc = "Number of micro-ops dispatched for execution",
},
- /*
- * BEGIN: Core 2 Duo events
- */
+ { .pme_name = "RS_UOPS_DISPATCHED_NONE",
+ .pme_code = 0xa0 | (1 << 23 | 1 << 24),
+ .pme_desc = "Number of of cycles in which no micro-ops is dispatched for execution",
+ },
{ .pme_name = "LOAD_BLOCK",
.pme_code = 0x3,
.pme_flags = 0,
@@ -401,7 +405,7 @@ static pme_core_entry_t core_pe[]={
},
{ .pme_name = "L2_IFETCH",
.pme_code = 0x28,
- .pme_flags = PFMLIB_CORE_CSPEC,
+ .pme_flags = PFMLIB_CORE_CSPEC|PFMLIB_CORE_MESI,
.pme_desc = "L2 cacheable instruction fetch requests",
.pme_umasks = {
INTEL_CORE_MESI_UMASKS,
@@ -411,7 +415,7 @@ static pme_core_entry_t core_pe[]={
},
{ .pme_name = "L2_LD",
.pme_code = 0x29,
- .pme_flags = PFMLIB_CORE_CSPEC,
+ .pme_flags = PFMLIB_CORE_CSPEC|PFMLIB_CORE_MESI,
.pme_desc = "L2 cache reads",
.pme_umasks = {
INTEL_CORE_MESI_UMASKS,
@@ -422,7 +426,7 @@ static pme_core_entry_t core_pe[]={
},
{ .pme_name = "L2_ST",
.pme_code = 0x2a,
- .pme_flags = PFMLIB_CORE_CSPEC,
+ .pme_flags = PFMLIB_CORE_CSPEC|PFMLIB_CORE_MESI,
.pme_desc = "L2 store requests",
.pme_umasks = {
INTEL_CORE_MESI_UMASKS,
@@ -432,7 +436,7 @@ static pme_core_entry_t core_pe[]={
},
{ .pme_name = "L2_LOCK",
.pme_code = 0x2b,
- .pme_flags = PFMLIB_CORE_CSPEC,
+ .pme_flags = PFMLIB_CORE_CSPEC|PFMLIB_CORE_MESI,
.pme_desc = "L2 locked accesses",
.pme_umasks = {
INTEL_CORE_MESI_UMASKS,
@@ -442,7 +446,7 @@ static pme_core_entry_t core_pe[]={
},
{ .pme_name = "L2_RQSTS",
.pme_code = 0x2e,
- .pme_flags = PFMLIB_CORE_CSPEC,
+ .pme_flags = PFMLIB_CORE_CSPEC|PFMLIB_CORE_MESI,
.pme_desc = "L2 cache requests",
.pme_umasks = {
INTEL_CORE_MESI_UMASKS,
@@ -453,7 +457,7 @@ static pme_core_entry_t core_pe[]={
},
{ .pme_name = "L2_REJECT_BUSQ",
.pme_code = 0x30,
- .pme_flags = PFMLIB_CORE_CSPEC,
+ .pme_flags = PFMLIB_CORE_CSPEC|PFMLIB_CORE_MESI,
.pme_desc = "Rejected L2 cache requests",
.pme_umasks = {
INTEL_CORE_MESI_UMASKS,
@@ -483,29 +487,32 @@ static pme_core_entry_t core_pe[]={
},
{ .pme_name = "CPU_CLK_UNHALTED",
.pme_code = 0x3c,
- .pme_flags = 0,
+ .pme_flags = PFMLIB_CORE_UMASK_NCOMBO,
.pme_desc = "Core cycles when core is not halted",
.pme_umasks = {
{ .pme_uname = "CORE_P",
.pme_udesc = "Core cycles when core is not halted",
.pme_ucode = 0x0,
- .pme_flags = PFMLIB_CORE_FIXED1
+ },
+ { .pme_uname = "REF",
+ .pme_udesc = "Reference cycles. This event is not affected by core changes such as P-states or TM2 transitions but counts at the same frequency as the time stamp counter. This event can approximate elapsed time. This event has a constant ratio with the CPU_CLK_UNHALTED:BUS event",
+ .pme_ucode = 0x1,
+ .pme_flags = PFMLIB_CORE_FIXED2_ONLY /* Can only be measured on FIXED_CTR2 */
},
{ .pme_uname = "BUS",
- .pme_udesc = "Bus cycles when core is not halted",
+ .pme_udesc = "Bus cycles when core is not halted. This event can give a measurement of the elapsed time. This events has a constant ratio with CPU_CLK_UNHALTED:REF event, which is the maximum bus to processor frequency ratio",
.pme_ucode = 0x1,
- .pme_flags = PFMLIB_CORE_FIXED2
},
{ .pme_uname = "NO_OTHER",
.pme_udesc = "Bus cycles when core is active and the other is halted",
.pme_ucode = 0x2
}
},
- .pme_numasks = 3
+ .pme_numasks = 4
},
{ .pme_name = "L1D_CACHE_LD",
.pme_code = 0x40,
- .pme_flags = 0,
+ .pme_flags = PFMLIB_CORE_MESI,
.pme_desc = "L1 cacheable data reads",
.pme_umasks = {
INTEL_CORE_MESI_UMASKS
@@ -514,7 +521,7 @@ static pme_core_entry_t core_pe[]={
},
{ .pme_name = "L1D_CACHE_ST",
.pme_code = 0x41,
- .pme_flags = 0,
+ .pme_flags = PFMLIB_CORE_MESI,
.pme_desc = "L1 cacheable data writes",
.pme_umasks = {
INTEL_CORE_MESI_UMASKS
@@ -523,7 +530,7 @@ static pme_core_entry_t core_pe[]={
},
{ .pme_name = "L1D_CACHE_LOCK",
.pme_code = 0x42,
- .pme_flags = 0,
+ .pme_flags = PFMLIB_CORE_MESI,
.pme_desc = "L1 data cacheable locked reads",
.pme_umasks = {
INTEL_CORE_MESI_UMASKS
@@ -593,12 +600,8 @@ static pme_core_entry_t core_pe[]={
.pme_udesc = "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions missing all cache levels",
.pme_ucode = 0x2
},
- { .pme_uname = "STORES",
- .pme_udesc = "Streaming SIMD Extensions (SSE) Weakly-ordered store instructions missing all cache levels",
- .pme_ucode = 0x3
- }
},
- .pme_numasks = 4
+ .pme_numasks = 3
},
{ .pme_name = "LOAD_HIT_PRE",
.pme_code = 0x4c,
@@ -1098,7 +1101,7 @@ static pme_core_entry_t core_pe[]={
{ .pme_uname = "ANY_P",
.pme_udesc = "Instructions retired (precise event)",
.pme_ucode = 0x0,
- .pme_flags = PFMLIB_CORE_PEBS|PFMLIB_CORE_FIXED0
+ .pme_flags = PFMLIB_CORE_PEBS
},
{ .pme_uname = "LOADS",
.pme_udesc = "Instructions retired, which contain a load",
@@ -1134,7 +1137,7 @@ static pme_core_entry_t core_pe[]={
},
{ .pme_name = "UOPS_RETIRED",
.pme_code = 0xc2,
- .pme_flags = PFMLIB_CORE_PEBS,
+ .pme_flags = 0,
.pme_desc = "Fused load+op or load+indirect branch retired",
.pme_umasks = {
{ .pme_uname = "LD_IND_BR",
@@ -1266,7 +1269,7 @@ static pme_core_entry_t core_pe[]={
},
{ .pme_name = "ITLB_MISS_RETIRED",
.pme_code = 0xc9,
- .pme_flags = PFMLIB_CORE_PMC0,
+ .pme_flags = 0,
.pme_desc = "Retired instructions that missed the ITLB"
},
{ .pme_name = "SIMD_COMP_INST_RETIRED",
diff --git a/src/libpfm-3.y/lib/coreduo_events.h b/src/libpfm-3.y/lib/coreduo_events.h
index a7a92e25ce9336581df2b59cc088a9e694ce0a3f..af9b5b79056563d43b4d83eb4b36dc081482f7dc 100644
--- a/src/libpfm-3.y/lib/coreduo_events.h
+++ b/src/libpfm-3.y/lib/coreduo_events.h
@@ -1,4 +1,9 @@
/*
+ * Copyright (c) 2009 Google, Inc
+ * Contributed by Stephane Eranian <eranian@gmail.com>
+ * Contributions by James Ralph <ralph@eecs.utk.edu>
+ *
+ * Based on:
* Copyright (c) 2006 Hewlett-Packard Development Company, L.P.
* Contributed by Stephane Eranian <eranian@hpl.hp.com>
*
@@ -23,183 +28,888 @@
* applications on Linux.
*/
-static pme_gen_ia32_entry_t coreduo_pe[]={
- /*
- * BEGIN architectural perfmon events
- */
-/* 0 */{.pme_name = "UNHALTED_CORE_CYCLES",
+
+#define INTEL_COREDUO_MESI_UMASKS \
+ { .pme_uname = "MESI",\
+ .pme_udesc = "Any cacheline access",\
+ .pme_ucode = 0xf\
+ },\
+ { .pme_uname = "I_STATE",\
+ .pme_udesc = "Invalid cacheline",\
+ .pme_ucode = 0x1\
+ },\
+ { .pme_uname = "S_STATE",\
+ .pme_udesc = "Shared cacheline",\
+ .pme_ucode = 0x2\
+ },\
+ { .pme_uname = "E_STATE",\
+ .pme_udesc = "Exclusive cacheline",\
+ .pme_ucode = 0x4\
+ },\
+ { .pme_uname = "M_STATE",\
+ .pme_udesc = "Modified cacheline",\
+ .pme_ucode = 0x8\
+ }
+
+#define INTEL_COREDUO_SPECIFICITY_UMASKS \
+ { .pme_uname = "SELF",\
+ .pme_udesc = "This core",\
+ .pme_ucode = 0x40\
+ },\
+ { .pme_uname = "BOTH_CORES",\
+ .pme_udesc = "Both cores",\
+ .pme_ucode = 0xc0\
+ }
+
+#define INTEL_COREDUO_HW_PREFETCH_UMASKS \
+ { .pme_uname = "ANY",\
+ .pme_udesc = "All inclusive",\
+ .pme_ucode = 0x30\
+ },\
+ { .pme_uname = "PREFETCH",\
+ .pme_udesc = "Hardware prefetch only",\
+ .pme_ucode = 0x10\
+ }
+
+#define INTEL_COREDUO_AGENT_UMASKS \
+ { .pme_uname = "THIS_AGENT",\
+ .pme_udesc = "This agent",\
+ .pme_ucode = 0x00\
+ },\
+ { .pme_uname = "ALL_AGENTS",\
+ .pme_udesc = "Any agent on the bus",\
+ .pme_ucode = 0x20\
+ }
+
+static pme_coreduo_entry_t coreduo_pe[]={
+ /*
+ * BEGIN architectural perfmon events
+ */
+ /* 0 */{
+ .pme_name = "UNHALTED_CORE_CYCLES",
.pme_code = 0x003c,
.pme_desc = "Unhalted core cycles",
- },
-/* 1 */{.pme_name = "UNHALTED_REFERENCE_CYCLES",
+ },
+ /* 1 */{
+ .pme_name = "UNHALTED_REFERENCE_CYCLES",
.pme_code = 0x013c,
.pme_desc = "Unhalted reference cycles. Measures bus cycles"
- },
-/* 2 */{.pme_name = "INSTRUCTIONS_RETIRED",
+ },
+ /* 2 */{
+ .pme_name = "INSTRUCTIONS_RETIRED",
.pme_code = 0xc0,
.pme_desc = "Instructions retired"
- },
-/* 3 */{.pme_name = "LAST_LEVEL_CACHE_REFERENCE",
+ },
+ /* 3 */{
+ .pme_name = "LAST_LEVEL_CACHE_REFERENCES",
.pme_code = 0x4f2e,
.pme_desc = "Last level of cache references"
- },
-/* 4 */{.pme_name = "LAST_LEVEL_CACHE_MISSES",
+ },
+ /* 4 */{
+ .pme_name = "LAST_LEVEL_CACHE_MISSES",
.pme_code = 0x412e,
.pme_desc = "Last level of cache misses",
- },
-/* 5 */{.pme_name = "BRANCH_INSTRUCTIONS_RETIRED",
+ },
+ /* 5 */{
+ .pme_name = "BRANCH_INSTRUCTIONS_RETIRED",
.pme_code = 0xc4,
.pme_desc = "Branch instructions retired"
- },
-/* 6 */{.pme_name = "MISPREDICTED_BRANCH_RETIRED",
+ },
+ /* 6 */{
+ .pme_name = "MISPREDICTED_BRANCH_RETIRED",
.pme_code = 0xc5,
.pme_desc = "Mispredicted branch instruction retired"
- },
+ },
- /*
- * BEGIN non architectural events
- */
+ /*
+ * BEGIN non architectural events
+ */
-/* 7 */{.pme_name = "LD_BLOCKS",
- .pme_code = 0x03,
- .pme_desc = "Load operations delayed due to store buffer blocks. The preceding store may be blocked due to unknown address, unknown data, or conflict due to partial overlap between the load and store."
- },
-/* 8 */{.pme_name = "SD_DRAINS",
- .pme_code = 0x04,
- .pme_desc = "Cycles while draining store buffers"
- },
-/* 9 */{.pme_name = "MISALIGN_MEM_REF",
- .pme_code = 0x05,
- .pme_desc = "Misaligned data memory references (MOB splits of loads and stores)"
- },
-/* 10 */{.pme_name = "SEG_REG_LOADS",
- .pme_code = 0x06,
- .pme_desc = "Segment register loads"
- },
-/* 11 */{.pme_name = "SSE_PREFETCH",
- .pme_code = 0x7,
- .pme_desc = "SSE software prefetch instruction",
- .pme_flags = PFMLIB_GEN_IA32_UMASK_COMBO,
- .pme_numasks = 3,
- .pme_umasks = {
- { .pme_uname = "NTA",
- .pme_udesc = "prefetchnta retired",
- .pme_ucode = 0x00,
- },
- { .pme_uname = "T1",
- .pme_udesc = "prefetcht1 retired",
- .pme_ucode = 0x01,
- },
- { .pme_uname = "T2",
- .pme_udesc = "prefetcht2 retired",
- .pme_ucode = 0x02,
- }
- }
- },
-/* 12 */{.pme_name = "SSE_NT_STORES_RETIRED",
- .pme_code = 0x0307,
- .pme_desc = "SSE streaming store instructions retired"
- },
-/* 13 */{.pme_name = "L2_ADS",
- .pme_code = 0x21,
- .pme_desc = "L2 address stobes",
- .pme_numasks = 2,
- .pme_umasks = {
- { .pme_uname = "ALL_CORES",
- .pme_udesc = "monitor all cores",
- .pme_ucode = 0x3 << 6, /* 6=14-8, umask relative bit position */
- },
- { .pme_uname = "THIS_CORE",
- .pme_udesc = "monitor this core",
- .pme_ucode = 0x1 << 6,
- },
- }
- },
-/* 14 */{.pme_name = "DBUS_BUSY",
- .pme_code = 0x22,
- .pme_desc = "Core cycle during which data bus was busy (increments by 4)",
- .pme_numasks = 2,
- .pme_umasks = {
- { .pme_uname = "ALL_CORES",
- .pme_udesc = "monitoring all cores",
- .pme_ucode = 0x3 << 6, /* 6=14-8, umask relative bit position */
- },
- { .pme_uname = "THIS_CORE",
- .pme_udesc = "monitoring this core",
- .pme_ucode = 0x1 << 6,
- },
- }
- },
-/* 15 */{.pme_name = "L2_LINES_IN",
- .pme_code = 0x24,
+ { .pme_code = 0x3,
+ .pme_name = "LD_BLOCKS",
+ .pme_desc = "Load operations delayed due to store buffer blocks. The preceding store may be blocked due to unknown address, unknown data, or conflict due to partial overlap between the load and store.",
+ },
+ { .pme_code = 0x4,
+ .pme_name = "SD_DRAINS",
+ .pme_desc = "Cycles while draining store buffers",
+ },
+ { .pme_code = 0x5,
+ .pme_name = "MISALIGN_MEM_REF",
+ .pme_desc = "Misaligned data memory references (MOB splits of loads and stores).",
+ },
+ { .pme_code = 0x6,
+ .pme_name = "SEG_REG_LOADS",
+ .pme_desc = "Segment register loads",
+ },
+ { .pme_code = 0x7,
+ .pme_name = "SSE_PREFETCH",
+ .pme_flags = 0,
+ .pme_desc = "Streaming SIMD Extensions (SSE) Prefetch instructions executed",
+ .pme_umasks = {
+ { .pme_uname = "NTA",
+ .pme_udesc = "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",
+ .pme_ucode = 0x0
+ },
+ { .pme_uname = "T1",
+ .pme_udesc = "SSE software prefetch instruction PREFE0xTCT1 retired",
+ .pme_ucode = 0x01
+ },
+ { .pme_uname = "T2",
+ .pme_udesc = "SSE software prefetch instruction PREFE0xTCT2 retired",
+ .pme_ucode = 0x02
+ },
+ },
+ .pme_numasks = 3
+ },
+ { .pme_name = "SSE_NTSTORES_RET",
+ .pme_desc = "SSE streaming store instruction retired",
+ .pme_code = 0x0307
+ },
+ { .pme_code = 0x10,
+ .pme_name = "FP_COMPS_OP_EXE",
+ .pme_desc = "FP computational Instruction executed. FADD, FSUB, FCOM, FMULs, MUL, IMUL, FDIVs, DIV, IDIV, FPREMs, FSQRT are included; but exclude FADD or FMUL used in the middle of a transcendental instruction.",
+ },
+ { .pme_code = 0x11,
+ .pme_name = "FP_ASSIST",
+ .pme_desc = "FP exceptions experienced microcode assists",
+ .pme_flags = PFMLIB_COREDUO_PMC1
+ },
+ { .pme_code = 0x12,
+ .pme_name = "MUL",
+ .pme_desc = "Multiply operations (a speculative count, including FP and integer multiplies).",
+ .pme_flags = PFMLIB_COREDUO_PMC1
+ },
+ { .pme_code = 0x13,
+ .pme_name = "DIV",
+ .pme_desc = "Divide operations (a speculative count, including FP and integer multiplies). ",
+ .pme_flags = PFMLIB_COREDUO_PMC1
+ },
+ { .pme_code = 0x14,
+ .pme_name = "CYCLES_DIV_BUSY",
+ .pme_desc = "Cycles the divider is busy ",
+ .pme_flags = PFMLIB_COREDUO_PMC0
+ },
+ { .pme_code = 0x21,
+ .pme_name = "L2_ADS",
+ .pme_flags = PFMLIB_COREDUO_CSPEC,
+ .pme_desc = "L2 Address strobes ",
+ .pme_umasks = {
+ INTEL_COREDUO_SPECIFICITY_UMASKS
+ },
+ .pme_numasks = 2
+ },
+ { .pme_code = 0x22,
+ .pme_name = "DBUS_BUSY",
+ .pme_flags = PFMLIB_COREDUO_CSPEC,
+ .pme_desc = "Core cycle during which data buswas busy (increments by 4)",
+ .pme_umasks = {
+ INTEL_COREDUO_SPECIFICITY_UMASKS
+ },
+ .pme_numasks = 2
+ },
+ { .pme_code = 0x23,
+ .pme_name = "DBUS_BUSY_RD",
+ .pme_flags = PFMLIB_COREDUO_CSPEC,
+ .pme_desc = "Cycles data bus is busy transferring data to a core (increments by 4) ",
+ .pme_umasks = {
+ INTEL_COREDUO_SPECIFICITY_UMASKS
+ },
+ .pme_numasks = 2
+ },
+ { .pme_code = 0x24,
+ .pme_name = "L2_LINES_IN",
+ .pme_flags = PFMLIB_COREDUO_CSPEC,
.pme_desc = "L2 cache lines allocated",
- .pme_numasks = 6,
- .pme_umasks = {
- { .pme_uname = "ALL_PREFETCHES_ALL_CORES",
- .pme_udesc = "monitor all types of prefetches on all cores",
- .pme_ucode = (0x3<<4)|(0x3<<6),
- },
- { .pme_uname = "ALL_PREFETCHES_THIS_CORE",
- .pme_udesc = "monitor all types of prefetches on this core",
- .pme_ucode = (0x3<<4)|(0x1<<6),
- },
- { .pme_uname = "HW_PREFETCH_ONLY_ALL_CORES",
- .pme_udesc = "monitor only hardware prefetches on all cores",
- .pme_ucode = (0x1<<4)|(0x3<<6),
- },
- { .pme_uname = "HW_PREFETCH_ONLY_THIS_CORE",
- .pme_udesc = "monitor only hardware prefetches on this core",
- .pme_ucode = (0x1<<4)|(0x1<<6),
- },
- { .pme_uname = "EXCL_HW_PREFETCH_ALL_CORES",
- .pme_udesc = "monitoring exclude hardware prefetches on all cores",
- .pme_ucode = 0x3<<6,
- },
- { .pme_uname = "EXCL_HW_PREFETCH_THIS_CORE",
- .pme_udesc = "monitoring exclude hardware prefetches on this core",
- .pme_ucode = 0x1<<6,
- }
- }
- },
-/* 16 */{.pme_name = "BUS_DRDY_CLOCKS",
- .pme_code = 0x62,
- .pme_desc = "External bus cycles while DRDY is asserted",
- .pme_numasks = 2,
- .pme_umasks = {
- { .pme_uname = "ALL_AGENTS",
- .pme_udesc = "monitoring all agents",
- .pme_ucode = 0x1<<5, /* 5=13-8, umask relative bit position */
- },
- { .pme_uname = "THIS_AGENT",
- .pme_udesc = "monitoring this agent",
- .pme_ucode = 0x0,
- },
- }
- },
-/* 17 */{.pme_name = "BUS_TRANS_RFO",
- .pme_code = 0x66,
- .pme_desc = "Completed read for ownership (RFO) transactions",
- .pme_numasks = 4,
- .pme_umasks = {
- { .pme_uname = "ALL_CORES_ALL_AGENTS",
- .pme_udesc = "monitoring all cores and all agents",
- .pme_ucode = (0x3<<6)|(0x1<<5),
- },
- { .pme_uname = "ALL_CORES_THIS_AGENT",
- .pme_udesc = "monitoring all cores and this agent",
- .pme_ucode = 0x3<<6,
- },
- { .pme_uname = "THIS_CORE_ALL_AGENTS",
- .pme_udesc = "monitoring this core and all agents",
- .pme_ucode = (0x1<<6)|(0x1<<5),
- },
- { .pme_uname = "THIS_CORE_THIS_AGENT",
- .pme_udesc = "monitoring this core and this agent",
- .pme_ucode = 0x1<<6,
- },
- }
- }
+ .pme_umasks = {
+ INTEL_COREDUO_SPECIFICITY_UMASKS,
+ INTEL_COREDUO_HW_PREFETCH_UMASKS
+ },
+ .pme_numasks = 4
+ },
+ { .pme_code = 0x25,
+ .pme_name = "L2_M_LINES_IN",
+ .pme_flags = PFMLIB_COREDUO_CSPEC,
+ .pme_desc = "L2 Modified-state cache lines allocated",
+ .pme_umasks = {
+ INTEL_COREDUO_SPECIFICITY_UMASKS
+ },
+ .pme_numasks = 2
+ },
+ { .pme_code = 0x26,
+ .pme_name = "L2_LINES_OUT",
+ .pme_flags = PFMLIB_COREDUO_CSPEC,
+ .pme_desc = "L2 cache lines evicted ",
+ .pme_umasks = {
+ INTEL_COREDUO_SPECIFICITY_UMASKS,
+ INTEL_COREDUO_HW_PREFETCH_UMASKS
+ },
+ .pme_numasks = 4
+ },
+ { .pme_code = 0x27,
+ .pme_name = "L2_M_LINES_OUT",
+ .pme_flags = PFMLIB_COREDUO_CSPEC,
+ .pme_desc = "L2 Modified-state cache lines evicted ",
+ .pme_umasks = {
+ INTEL_COREDUO_SPECIFICITY_UMASKS,
+ INTEL_COREDUO_HW_PREFETCH_UMASKS
+ },
+ .pme_numasks = 4
+ },
+ { .pme_code = 0x28,
+ .pme_name = "L2_IFETCH",
+ .pme_flags = PFMLIB_COREDUO_CSPEC|PFMLIB_COREDUO_MESI,
+ .pme_desc = "L2 instruction fetches from nstruction fetch unit (includes speculative fetches) ",
+ .pme_umasks = {
+ INTEL_COREDUO_MESI_UMASKS,
+ INTEL_COREDUO_SPECIFICITY_UMASKS
+ },
+ .pme_numasks = 7
+ },
+ { .pme_code = 0x29,
+ .pme_name = "L2_LD",
+ .pme_desc = "L2 cache reads (includes speculation) ",
+ .pme_flags = PFMLIB_COREDUO_CSPEC|PFMLIB_COREDUO_MESI,
+ .pme_umasks = {
+ INTEL_COREDUO_MESI_UMASKS,
+ INTEL_COREDUO_SPECIFICITY_UMASKS
+ },
+ .pme_numasks = 7
+ },
+ { .pme_code = 0x2A,
+ .pme_name = "L2_ST",
+ .pme_flags = PFMLIB_COREDUO_CSPEC|PFMLIB_COREDUO_MESI,
+ .pme_desc = "L2 cache writes (includes speculation)",
+ .pme_umasks = {
+ INTEL_COREDUO_MESI_UMASKS,
+ INTEL_COREDUO_SPECIFICITY_UMASKS
+ },
+ .pme_numasks = 7
+ },
+ { .pme_code = 0x2E,
+ .pme_name = "L2_RQSTS",
+ .pme_flags = PFMLIB_COREDUO_CSPEC|PFMLIB_COREDUO_MESI,
+ .pme_desc = "L2 cache reference requests ",
+ .pme_umasks = {
+ INTEL_COREDUO_MESI_UMASKS,
+ INTEL_COREDUO_SPECIFICITY_UMASKS,
+ INTEL_COREDUO_HW_PREFETCH_UMASKS
+ },
+ .pme_numasks = 9
+ },
+ { .pme_code = 0x30,
+ .pme_name = "L2_REJECT_CYCLES",
+ .pme_flags = PFMLIB_COREDUO_CSPEC|PFMLIB_COREDUO_MESI,
+ .pme_desc = "Cycles L2 is busy and rejecting new requests.",
+ .pme_umasks = {
+ INTEL_COREDUO_MESI_UMASKS,
+ INTEL_COREDUO_SPECIFICITY_UMASKS,
+ INTEL_COREDUO_HW_PREFETCH_UMASKS
+ },
+ .pme_numasks = 9
+ },
+ { .pme_code = 0x32,
+ .pme_name = "L2_NO_REQUEST_CYCLES",
+ .pme_flags = PFMLIB_COREDUO_CSPEC|PFMLIB_COREDUO_MESI,
+ .pme_desc = "Cycles there is no request to access L2.",
+ .pme_umasks = {
+ INTEL_COREDUO_MESI_UMASKS,
+ INTEL_COREDUO_SPECIFICITY_UMASKS,
+ INTEL_COREDUO_HW_PREFETCH_UMASKS
+ },
+ .pme_numasks = 9
+ },
+ { .pme_code = 0x3A,
+ .pme_name = "EST_TRANS_ALL",
+ .pme_desc = "Any Intel Enhanced SpeedStep(R) Technology transitions",
+ },
+ { .pme_code = 0x103A,
+ .pme_name = "EST_TRANS_ALL",
+ .pme_desc = "Intel Enhanced SpeedStep Technology frequency transitions",
+ },
+ { .pme_code = 0x3B,
+ .pme_name = "THERMAL_TRIP",
+ .pme_desc = "Duration in a thermal trip based on the current core clock ",
+ .pme_umasks = {
+ { .pme_uname = "CYCLES",
+ .pme_udesc = "Duration in a thermal trip based on the current core clock",
+ .pme_ucode = 0xC0
+ },
+ { .pme_uname = "TRIPS",
+ .pme_udesc = "Number of thermal trips",
+ .pme_ucode = 0xC0 | (1<<10) /* Edge detect pin (Figure 18-13) */
+ }
+ },
+ .pme_numasks = 2
+ },
+ {
+ .pme_name = "CPU_CLK_UNHALTED",
+ .pme_code = 0x3c,
+ .pme_desc = "Core cycles when core is not halted",
+ .pme_umasks = {
+ { .pme_uname = "NONHLT_REF_CYCLES",
+ .pme_udesc = "Non-halted bus cycles",
+ .pme_ucode = 0x01
+ },
+ { .pme_uname = "SERIAL_EXECUTION_CYCLES",
+ .pme_udesc ="Non-halted bus cycles of this core executing code while the other core is halted",
+ .pme_ucode = 0x02
+ }
+ },
+ .pme_numasks = 2
+ },
+ { .pme_code = 0x40,
+ .pme_name = "DCACHE_CACHE_LD",
+ .pme_desc = "L1 cacheable data read operations",
+ .pme_umasks = {
+ INTEL_COREDUO_MESI_UMASKS
+ },
+ .pme_numasks = 5
+ },
+ { .pme_code = 0x41,
+ .pme_name = "DCACHE_CACHE_ST",
+ .pme_desc = "L1 cacheable data write operations",
+ .pme_umasks = {
+ INTEL_COREDUO_MESI_UMASKS
+ },
+ .pme_numasks = 5
+ },
+ { .pme_code = 0x42,
+ .pme_name = "DCACHE_CACHE_LOCK",
+ .pme_desc = "L1 cacheable lock read operations to invalid state",
+ .pme_umasks = {
+ INTEL_COREDUO_MESI_UMASKS
+ },
+ .pme_numasks = 5
+ },
+ { .pme_code = 0x0143,
+ .pme_name = "DATA_MEM_REF",
+ .pme_desc = "L1 data read and writes of cacheable and non-cacheable types",
+ },
+ { .pme_code = 0x0244,
+ .pme_name = "DATA_MEM_CACHE_REF",
+ .pme_desc = "L1 data cacheable read and write operations.",
+ },
+ { .pme_code = 0x0f45,
+ .pme_name = "DCACHE_REPL",
+ .pme_desc = "L1 data cache line replacements",
+ },
+ { .pme_code = 0x46,
+ .pme_name = "DCACHE_M_REPL",
+ .pme_desc = "L1 data M-state cache line allocated",
+ },
+ { .pme_code = 0x47,
+ .pme_name = "DCACHE_M_EVICT",
+ .pme_desc = "L1 data M-state cache line evicted",
+ },
+ { .pme_code = 0x48,
+ .pme_name = "DCACHE_PEND_MISS",
+ .pme_desc = "Weighted cycles of L1 miss outstanding",
+ },
+ { .pme_code = 0x49,
+ .pme_name = "DTLB_MISS",
+ .pme_desc = "Data references that missed TLB",
+ },
+ { .pme_code = 0x4B,
+ .pme_name = "SSE_PRE_MISS",
+ .pme_flags = 0,
+ .pme_desc = "Streaming SIMD Extensions (SSE) instructions missing all cache levels",
+ .pme_umasks = {
+ { .pme_uname = "NTA_MISS",
+ .pme_udesc = "PREFETCHNTA missed all caches",
+ .pme_ucode = 0x00
+ },
+ { .pme_uname = "T1_MISS",
+ .pme_udesc = "PREFETCHT1 missed all caches",
+ .pme_ucode = 0x01
+ },
+ { .pme_uname = "T2_MISS",
+ .pme_udesc = "PREFETCHT2 missed all caches",
+ .pme_ucode = 0x02
+ },
+ { .pme_uname = "STORES_MISS",
+ .pme_udesc = "SSE streaming store instruction missed all caches",
+ .pme_ucode = 0x03
+ }
+ },
+ .pme_numasks = 4
+ },
+ { .pme_code = 0x4F,
+ .pme_name = "L1_PREF_REQ",
+ .pme_desc = "L1 prefetch requests due to DCU cache misses",
+ },
+ { .pme_code = 0x60,
+ .pme_name = "BUS_REQ_OUTSTANDING",
+ .pme_flags = PFMLIB_COREDUO_CSPEC,
+ .pme_desc = "Weighted cycles of cacheable bus data read requests. This event counts full-line read request from DCU or HW prefetcher, but not RFO, write, instruction fetches, or others.",
+ .pme_umasks = {
+ INTEL_COREDUO_SPECIFICITY_UMASKS,
+ INTEL_COREDUO_AGENT_UMASKS
+ },
+ .pme_numasks = 4
+ /* TODO: umasks bit 12 to include HWP or exclude HWP separately. */,
+ },
+ { .pme_code = 0x61,
+ .pme_name = "BUS_BNR_CLOCKS",
+ .pme_desc = "External bus cycles while BNR asserted",
+ },
+ { .pme_code = 0x62,
+ .pme_name = "BUS_DRDY_CLOCKS",
+ .pme_desc = "External bus cycles while DRDY asserted",
+ .pme_umasks = {
+ INTEL_COREDUO_AGENT_UMASKS
+ },
+ .pme_numasks = 2
+ },
+ { .pme_code = 0x63,
+ .pme_name = "BUS_LOCKS_CLOCKS",
+ .pme_flags = PFMLIB_COREDUO_CSPEC,
+ .pme_desc = "External bus cycles while bus lock signal asserted",
+ .pme_umasks = {
+ INTEL_COREDUO_SPECIFICITY_UMASKS,
+ },
+ .pme_numasks = 2
+ },
+ { .pme_code = 0x4064,
+ .pme_name = "BUS_DATA_RCV",
+ .pme_desc = "External bus cycles while bus lock signal asserted",
+ },
+ { .pme_code = 0x65,
+ .pme_name = "BUS_TRANS_BRD",
+ .pme_flags = PFMLIB_COREDUO_CSPEC,
+ .pme_desc = "Burst read bus transactions (data or code)",
+ .pme_umasks = {
+ INTEL_COREDUO_SPECIFICITY_UMASKS,
+ },
+ .pme_numasks = 2
+ },
+ { .pme_code = 0x66,
+ .pme_name = "BUS_TRANS_RFO",
+ .pme_flags = PFMLIB_COREDUO_CSPEC,
+ .pme_desc = "Completed read for ownership ",
+ .pme_umasks = {
+ INTEL_COREDUO_SPECIFICITY_UMASKS,
+ INTEL_COREDUO_AGENT_UMASKS
+ },
+ .pme_numasks = 4
+ },
+ { .pme_code = 0x68,
+ .pme_name = "BUS_TRANS_IFETCH",
+ .pme_flags = PFMLIB_COREDUO_CSPEC,
+ .pme_desc = "Completed instruction fetch transactions",
+ .pme_umasks = {
+ INTEL_COREDUO_SPECIFICITY_UMASKS,
+ INTEL_COREDUO_AGENT_UMASKS
+ },
+ .pme_numasks = 4
+
+ },
+ { .pme_code = 0x69,
+ .pme_flags = PFMLIB_COREDUO_CSPEC,
+ .pme_name = "BUS_TRANS_INVAL",
+ .pme_desc = "Completed invalidate transactions",
+ .pme_umasks = {
+ INTEL_COREDUO_SPECIFICITY_UMASKS,
+ INTEL_COREDUO_AGENT_UMASKS
+ },
+ .pme_numasks = 4
+ },
+ { .pme_code = 0x6A,
+ .pme_name = "BUS_TRANS_PWR",
+ .pme_flags = PFMLIB_COREDUO_CSPEC,
+ .pme_desc = "Completed partial write transactions",
+ .pme_umasks = {
+ INTEL_COREDUO_SPECIFICITY_UMASKS,
+ INTEL_COREDUO_AGENT_UMASKS
+ },
+ .pme_numasks = 4
+ },
+ { .pme_code = 0x6B,
+ .pme_name = "BUS_TRANS_P",
+ .pme_flags = PFMLIB_COREDUO_CSPEC,
+ .pme_desc = "Completed partial transactions (include partial read + partial write + line write)",
+ .pme_umasks = {
+ INTEL_COREDUO_SPECIFICITY_UMASKS,
+ INTEL_COREDUO_AGENT_UMASKS
+ },
+ .pme_numasks = 4
+ },
+ { .pme_code = 0x6C,
+ .pme_name = "BUS_TRANS_IO",
+ .pme_flags = PFMLIB_COREDUO_CSPEC,
+ .pme_desc = "Completed I/O transactions (read and write)",
+ .pme_umasks = {
+ INTEL_COREDUO_SPECIFICITY_UMASKS,
+ INTEL_COREDUO_AGENT_UMASKS
+ },
+ .pme_numasks = 4
+ },
+ { .pme_code = 0x206D,
+ .pme_name = "BUS_TRANS_DEF",
+ .pme_flags = PFMLIB_COREDUO_CSPEC,
+ .pme_desc = "Completed defer transactions ",
+ .pme_umasks = {
+ INTEL_COREDUO_SPECIFICITY_UMASKS
+ },
+ .pme_numasks = 2
+ },
+ { .pme_code = 0xc067,
+ .pme_name = "BUS_TRANS_WB",
+ .pme_desc = "Completed writeback transactions from DCU (does not include L2 writebacks)",
+ .pme_umasks = {
+ INTEL_COREDUO_AGENT_UMASKS
+ },
+ .pme_numasks = 2
+ },
+ { .pme_code = 0xc06E,
+ .pme_name = "BUS_TRANS_BURST",
+ .pme_desc = "Completed burst transactions (full line transactions include reads, write, RFO, and writebacks) ",
+ /* TODO .pme_umasks = 0xC0, */
+ .pme_umasks = {
+ INTEL_COREDUO_AGENT_UMASKS
+ },
+ .pme_numasks = 2
+ },
+ { .pme_code = 0xc06F,
+ .pme_name = "BUS_TRANS_MEM",
+ .pme_flags = PFMLIB_COREDUO_CSPEC,
+ .pme_desc = "Completed memory transactions. This includes Bus_Trans_Burst + Bus_Trans_P + Bus_Trans_Inval.",
+ .pme_umasks = {
+ INTEL_COREDUO_AGENT_UMASKS
+ },
+ .pme_numasks = 2
+ },
+ { .pme_code = 0xc070,
+ .pme_name = "BUS_TRANS_ANY",
+ .pme_desc = "Any completed bus transactions",
+ .pme_umasks = {
+ INTEL_COREDUO_AGENT_UMASKS
+ },
+ .pme_numasks = 2
+ },
+ { .pme_code = 0x77,
+ .pme_name = "BUS_SNOOPS",
+ .pme_desc = "External bus cycles while bus lock signal asserted",
+ .pme_flags = PFMLIB_COREDUO_MESI,
+ .pme_umasks = {
+ INTEL_COREDUO_MESI_UMASKS,
+ INTEL_COREDUO_AGENT_UMASKS
+ },
+ .pme_numasks = 7
+ },
+ { .pme_code = 0x0178,
+ .pme_name = "DCU_SNOOP_TO_SHARE",
+ .pme_desc = "DCU snoops to share-state L1 cache line due to L1 misses ",
+ .pme_flags = PFMLIB_COREDUO_CSPEC,
+ .pme_umasks = {
+ INTEL_COREDUO_SPECIFICITY_UMASKS
+ },
+ .pme_numasks = 2
+ },
+ { .pme_code = 0x7D,
+ .pme_name = "BUS_NOT_IN_USE",
+ .pme_flags = PFMLIB_COREDUO_CSPEC,
+ .pme_desc = "Number of cycles there is no transaction from the core",
+ .pme_umasks = {
+ INTEL_COREDUO_SPECIFICITY_UMASKS
+ },
+ .pme_numasks = 2
+ },
+ { .pme_code = 0x7E,
+ .pme_name = "BUS_SNOOP_STALL",
+ .pme_desc = "Number of bus cycles while bus snoop is stalled"
+ },
+ { .pme_code = 0x80,
+ .pme_name = "ICACHE_READS",
+ .pme_desc = "Number of instruction fetches from ICache, streaming buffers (both cacheable and uncacheable fetches)"
+ },
+ { .pme_code = 0x81,
+ .pme_name = "ICACHE_MISSES",
+ .pme_desc = "Number of instruction fetch misses from ICache, streaming buffers."
+ },
+ { .pme_code = 0x85,
+ .pme_name = "ITLB_MISSES",
+ .pme_desc = "Number of iITLB misses"
+ },
+ { .pme_code = 0x86,
+ .pme_name = "IFU_MEM_STALL",
+ .pme_desc = "Cycles IFU is stalled while waiting for data from memory"
+ },
+ { .pme_code = 0x87,
+ .pme_name = "ILD_STALL",
+ .pme_desc = "Number of instruction length decoder stalls (Counts number of LCP stalls)"
+ },
+ { .pme_code = 0x88,
+ .pme_name = "BR_INST_EXEC",
+ .pme_desc = "Branch instruction executed (includes speculation)."
+ },
+ { .pme_code = 0x89,
+ .pme_name = "BR_MISSP_EXEC",
+ .pme_desc = "Branch instructions executed and mispredicted at execution (includes branches that do not have prediction or mispredicted)"
+ },
+ { .pme_code = 0x8A,
+ .pme_name = "BR_BAC_MISSP_EXEC",
+ .pme_desc = "Branch instructions executed that were mispredicted at front end"
+ },
+ { .pme_code = 0x8B,
+ .pme_name = "BR_CND_EXEC",
+ .pme_desc = "Conditional branch instructions executed"
+ },
+ { .pme_code = 0x8C,
+ .pme_name = "BR_CND_MISSP_EXEC",
+ .pme_desc = "Conditional branch instructions executed that were mispredicted"
+ },
+ { .pme_code = 0x8D,
+ .pme_name = "BR_IND_EXEC",
+ .pme_desc = "Indirect branch instructions executed"
+ },
+ { .pme_code = 0x8E,
+ .pme_name = "BR_IND_MISSP_EXEC",
+ .pme_desc = "Indirect branch instructions executed that were mispredicted"
+ },
+ { .pme_code = 0x8F,
+ .pme_name = "BR_RET_EXEC",
+ .pme_desc = "Return branch instructions executed"
+ },
+ { .pme_code = 0x90,
+ .pme_name = "BR_RET_MISSP_EXEC",
+ .pme_desc = "Return branch instructions executed that were mispredicted"
+ },
+ { .pme_code = 0x91,
+ .pme_name = "BR_RET_BAC_MISSP_EXEC",
+ .pme_desc = "Return branch instructions executed that were mispredicted at the front end"
+ },
+ { .pme_code = 0x92,
+ .pme_name = "BR_CALL_EXEC",
+ .pme_desc = "Return call instructions executed"
+ },
+ { .pme_code = 0x93,
+ .pme_name = "BR_CALL_MISSP_EXEC",
+ .pme_desc = "Return call instructions executed that were mispredicted"
+ },
+ { .pme_code = 0x94,
+ .pme_name = "BR_IND_CALL_EXEC",
+ .pme_desc = "Indirect call branch instructions executed"
+ },
+ { .pme_code = 0xA2,
+ .pme_name = "RESOURCE_STALL",
+ .pme_desc = "Cycles while there is a resource related stall (renaming, buffer entries) as seen by allocator"
+ },
+ { .pme_code = 0xB0,
+ .pme_name = "MMX_INSTR_EXEC",
+ .pme_desc = "Number of MMX instructions executed (does not include MOVQ and MOVD stores)"
+ },
+ { .pme_code = 0xB1,
+ .pme_name = "SIMD_INT_SAT_EXEC",
+ .pme_desc = "Number of SIMD Integer saturating instructions executed"
+ },
+ { .pme_code = 0xB3,
+ .pme_name = "SIMD_INT_INSTRUCTIONS",
+ .pme_desc = "Number of SIMD Integer instructions executed",
+ .pme_umasks = {
+ { .pme_uname = "MUL",
+ .pme_udesc = "Number of SIMD Integer packed multiply instructions executed",
+ .pme_ucode = 0x01
+ },
+ { .pme_uname = "SHIFT",
+ .pme_udesc = "Number of SIMD Integer packed shift instructions executed",
+ .pme_ucode = 0x02
+ },
+ { .pme_uname = "PACK",
+ .pme_udesc = "Number of SIMD Integer pack operations instruction executed",
+ .pme_ucode = 0x04
+ },
+ { .pme_uname = "UNPACK",
+ .pme_udesc = "Number of SIMD Integer unpack instructions executed",
+ .pme_ucode = 0x08
+ },
+ { .pme_uname = "LOGICAL",
+ .pme_udesc = "Number of SIMD Integer packed logical instructions executed",
+ .pme_ucode = 0x10
+ },
+ { .pme_uname = "ARITHMETIC",
+ .pme_udesc = "Number of SIMD Integer packed arithmetic instructions executed",
+ .pme_ucode = 0x20
+ }
+ },
+ .pme_numasks = 6
+ },
+ { .pme_code = 0xC0,
+ .pme_name = "INSTR_RET",
+ .pme_desc = "Number of instruction retired (Macro fused instruction count as 2)"
+ },
+ { .pme_code = 0xC1,
+ .pme_name = "FP_COMP_INSTR_RET",
+ .pme_desc = "Number of FP compute instructions retired (X87 instruction or instruction that contain X87 operations)",
+ .pme_flags = PFMLIB_COREDUO_PMC0
+ },
+ { .pme_code = 0xC2,
+ .pme_name = "UOPS_RET",
+ .pme_desc = "Number of micro-ops retired (include fused uops)"
+ },
+ { .pme_code = 0xC3,
+ .pme_name = "SMC_DETECTED",
+ .pme_desc = "Number of times self-modifying code condition detected"
+ },
+ { .pme_code = 0xC4,
+ .pme_name = "BR_INSTR_RET",
+ .pme_desc = "Number of branch instructions retired"
+ },
+ { .pme_code = 0xC5,
+ .pme_name = "BR_MISPRED_RET",
+ .pme_desc = "Number of mispredicted branch instructions retired"
+ },
+ { .pme_code = 0xC6,
+ .pme_name = "CYCLES_INT_MASKED",
+ .pme_desc = "Cycles while interrupt is disabled"
+ },
+ { .pme_code = 0xC7,
+ .pme_name = "CYCLES_INT_PEDNING_MASKED",
+ .pme_desc = "Cycles while interrupt is disabled and interrupts are pending"
+ },
+ { .pme_code = 0xC8,
+ .pme_name = "HW_INT_RX",
+ .pme_desc = "Number of hardware interrupts received"
+ },
+ { .pme_code = 0xC9,
+ .pme_name = "BR_TAKEN_RET",
+ .pme_desc = "Number of taken branch instruction retired"
+ },
+ { .pme_code = 0xCA,
+ .pme_name = "BR_MISPRED_TAKEN_RET",
+ .pme_desc = "Number of taken and mispredicted branch instructions retired"
+ },
+ { .pme_code = 0xCC,
+ .pme_name = "FP_MMX_TRANS",
+ .pme_name = "MMX_FP_TRANS",
+ .pme_desc = "Transitions from MMX (TM) Instructions to Floating Point Instructions",
+ .pme_umasks = {
+ { .pme_uname = "TO_FP",
+ .pme_udesc = "Number of transitions from MMX to X87",
+ .pme_ucode = 0x00
+ },
+ { .pme_uname = "TO_MMX",
+ .pme_udesc = "Number of transitions from X87 to MMX",
+ .pme_ucode = 0x01
+ }
+ },
+ .pme_numasks = 2
+ },
+ { .pme_code = 0xCD,
+ .pme_name = "MMX_ASSIST",
+ .pme_desc = "Number of EMMS executed"
+ },
+ { .pme_code = 0xCE,
+ .pme_name = "MMX_INSTR_RET",
+ .pme_desc = "Number of MMX instruction retired"
+ },
+ { .pme_code = 0xD0,
+ .pme_name = "INSTR_DECODED",
+ .pme_desc = "Number of instruction decoded"
+ },
+ { .pme_code = 0xD7,
+ .pme_name = "ESP_UOPS",
+ .pme_desc = "Number of ESP folding instruction decoded"
+ },
+ { .pme_code = 0xD8,
+ .pme_name = "SSE_INSTRUCTIONS_RETIRED",
+ .pme_desc = "Number of SSE/SSE2 instructions retired (packed and scalar)",
+ .pme_umasks = {
+ { .pme_uname = "SINGLE",
+ .pme_udesc = "Number of SSE/SSE2 single precision instructions retired (packed and scalar)",
+ .pme_ucode = 0x00
+ },
+ { .pme_uname = "SCALAR_SINGLE",
+ .pme_udesc = "Number of SSE/SSE2 scalar single precision instructions retired",
+ .pme_ucode = 0x01,
+ },
+ { .pme_uname = "PACKED_DOUBLE",
+ .pme_udesc = "Number of SSE/SSE2 packed double percision instructions retired",
+ .pme_ucode = 0x02,
+ },
+ { .pme_uname = "DOUBLE",
+ .pme_udesc = "Number of SSE/SSE2 scalar double percision instructions retired",
+ .pme_ucode = 0x03,
+ },
+ { .pme_uname = "INT_128",
+ .pme_udesc = "Number of SSE2 128 bit integer instructions retired",
+ .pme_ucode = 0x04,
+ },
+ },
+ .pme_numasks = 5
+ },
+ { .pme_code = 0xD9,
+ .pme_name = "SSE_COMP_INSTRUCTIONS_RETIRED",
+ .pme_desc = "Number of computational SSE/SSE2 instructions retired (does not include AND, OR, XOR)",
+ .pme_umasks = {
+ { .pme_uname = "PACKED_SINGLE",
+ .pme_udesc = "Number of SSE/SSE2 packed single precision compute instructions retired (does not include AND, OR, XOR)",
+ .pme_ucode = 0x00
+ },
+ { .pme_uname = "SCALAR_SINGLE",
+ .pme_udesc = "Number of SSE/SSE2 scalar single precision compute instructions retired (does not include AND, OR, XOR)",
+ .pme_ucode = 0x01
+ },
+ { .pme_uname = "PACKED_DOUBLE",
+ .pme_udesc = "Number of SSE/SSE2 packed double precision compute instructions retired (does not include AND, OR, XOR)",
+ .pme_ucode = 0x02
+ },
+ { .pme_uname = "SCALAR_DOUBLE",
+ .pme_udesc = "Number of SSE/SSE2 scalar double precision compute instructions retired (does not include AND, OR, XOR)",
+ .pme_ucode = 0x03
+ }
+ },
+ .pme_numasks = 4
+ },
+ { .pme_code = 0xDA,
+ .pme_name = "FUSED_UOPS",
+ .pme_desc = "fused uops retired",
+ .pme_umasks = {
+ { .pme_uname = "ALL",
+ .pme_udesc = "All fused uops retired",
+ .pme_ucode = 0x00
+ },
+ { .pme_uname = "LOADS",
+ .pme_udesc = "Fused load uops retired",
+ .pme_ucode = 0x01
+ },
+ { .pme_uname = "STORES",
+ .pme_udesc = "Fused load uops retired",
+ .pme_ucode = 0x02
+ },
+ },
+ .pme_numasks = 3
+ },
+ { .pme_code = 0xDB,
+ .pme_name = "UNFUSION",
+ .pme_desc = "Number of unfusion events in the ROB (due to exception)"
+ },
+ { .pme_code = 0xE0,
+ .pme_name = "BR_INSTR_DECODED",
+ .pme_desc = "Branch instructions decoded"
+ },
+ { .pme_code = 0xE2,
+ .pme_name = "BTB_MISSES",
+ .pme_desc = "Number of branches the BTB did not produce a prediction"
+ },
+ { .pme_code = 0xE4,
+ .pme_name = "BR_BOGUS",
+ .pme_desc = "Number of bogus branches"
+ },
+ { .pme_code = 0xE6,
+ .pme_name = "BACLEARS",
+ .pme_desc = "Number of BAClears asserted"
+ },
+ { .pme_code = 0xF0,
+ .pme_name = "PREF_RQSTS_UP",
+ .pme_desc = "Number of hardware prefetch requests issued in forward streams"
+ },
+ { .pme_code = 0xF8,
+ .pme_name = "PREF_RQSTS_DN",
+ .pme_desc = "Number of hardware prefetch requests issued in backward streams"
+ }
};
-#define PME_COREDUO_UNHALTED_CORE_CYCLES 0
-#define PME_COREDUO_INSTRUCTIONS_RETIRED 2
-#define PME_COREDUO_EVENT_COUNT (sizeof(coreduo_pe)/sizeof(pme_gen_ia32_entry_t))
+
+
+#define PME_COREDUO_UNHALTED_CORE_CYCLES 0
+#define PME_COREDUO_INSTRUCTIONS_RETIRED 2
+#define PME_COREDUO_EVENT_COUNT (sizeof(coreduo_pe)/sizeof(pme_coreduo_entry_t))
diff --git a/src/libpfm-3.y/lib/crayx2_events.h b/src/libpfm-3.y/lib/crayx2_events.h
index 85b0c2b3e2b276c40499746f083cc8ce01112272..16b3d950d272f31a5eaf9123fcf1573efa717c6a 100644
--- a/src/libpfm-3.y/lib/crayx2_events.h
+++ b/src/libpfm-3.y/lib/crayx2_events.h
@@ -267,7 +267,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
/* P Counter 3 Event 3 */
{
.pme_name = "STALL_VU_FUG2",
- .pme_desc = "CPs VU stalled waiting for FUG.",
+ .pme_desc = "CPs VU stalled waiting for FUG 2.",
.pme_code = 15,
.pme_flags = 0x0,
.pme_numasks = 0,
@@ -537,7 +537,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
/* P Counter 8 Event 1 */
{
.pme_name = "VTLB_MISS",
- .pme_desc = "Number of Vector TLB misses.",
+ .pme_desc = "Number of vector TLB misses.",
.pme_code = 33,
.pme_flags = 0x0,
.pme_numasks = 0,
@@ -882,7 +882,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
/* P Counter 14 Event 0 */
{
.pme_name = "VOPS_EXT_FUG3",
- .pme_desc = "Number of V FUG 3 external operations g=20-27 f=25,57,77 compress, merge, bmm.",
+ .pme_desc = "Number of vector FUG 3 external operations g=20-27 f=25,57,77 compress, merge, bmm.",
.pme_code = 56,
.pme_flags = 0x0,
.pme_numasks = 0,
@@ -2921,7 +2921,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
},
/* M Counter 0 Event 0 */
{
- .pme_name = "W_IN_IDLE_01@0",
+ .pme_name = "W_IN_IDLE_0@0",
.pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 0)",
.pme_code = 192,
.pme_flags = 0x0,
@@ -2935,7 +2935,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_IN_IDLE_01@1",
+ .pme_name = "W_IN_IDLE_0@1",
.pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 1)",
.pme_code = 193,
.pme_flags = 0x0,
@@ -2949,7 +2949,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_IN_IDLE_01@2",
+ .pme_name = "W_IN_IDLE_0@2",
.pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 2)",
.pme_code = 194,
.pme_flags = 0x0,
@@ -2963,7 +2963,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_IN_IDLE_01@3",
+ .pme_name = "W_IN_IDLE_0@3",
.pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 3)",
.pme_code = 195,
.pme_flags = 0x0,
@@ -2977,7 +2977,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_IN_IDLE_01@4",
+ .pme_name = "W_IN_IDLE_0@4",
.pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 4)",
.pme_code = 196,
.pme_flags = 0x0,
@@ -2991,7 +2991,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_IN_IDLE_01@5",
+ .pme_name = "W_IN_IDLE_0@5",
.pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 5)",
.pme_code = 197,
.pme_flags = 0x0,
@@ -3005,7 +3005,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_IN_IDLE_01@6",
+ .pme_name = "W_IN_IDLE_0@6",
.pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 6)",
.pme_code = 198,
.pme_flags = 0x0,
@@ -3019,7 +3019,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_IN_IDLE_01@7",
+ .pme_name = "W_IN_IDLE_0@7",
.pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 7)",
.pme_code = 199,
.pme_flags = 0x0,
@@ -3033,7 +3033,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_IN_IDLE_01@8",
+ .pme_name = "W_IN_IDLE_0@8",
.pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 8)",
.pme_code = 200,
.pme_flags = 0x0,
@@ -3047,7 +3047,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_IN_IDLE_01@9",
+ .pme_name = "W_IN_IDLE_0@9",
.pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 9)",
.pme_code = 201,
.pme_flags = 0x0,
@@ -3061,7 +3061,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_IN_IDLE_01@10",
+ .pme_name = "W_IN_IDLE_0@10",
.pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 10)",
.pme_code = 202,
.pme_flags = 0x0,
@@ -3075,7 +3075,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_IN_IDLE_01@11",
+ .pme_name = "W_IN_IDLE_0@11",
.pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 11)",
.pme_code = 203,
.pme_flags = 0x0,
@@ -3089,7 +3089,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_IN_IDLE_01@12",
+ .pme_name = "W_IN_IDLE_0@12",
.pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 12)",
.pme_code = 204,
.pme_flags = 0x0,
@@ -3103,7 +3103,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_IN_IDLE_01@13",
+ .pme_name = "W_IN_IDLE_0@13",
.pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 13)",
.pme_code = 205,
.pme_flags = 0x0,
@@ -3117,7 +3117,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_IN_IDLE_01@14",
+ .pme_name = "W_IN_IDLE_0@14",
.pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 14)",
.pme_code = 206,
.pme_flags = 0x0,
@@ -3131,7 +3131,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_IN_IDLE_01@15",
+ .pme_name = "W_IN_IDLE_0@15",
.pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 15)",
.pme_code = 207,
.pme_flags = 0x0,
@@ -3371,7 +3371,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
},
/* M Counter 0 Event 2 */
{
- .pme_name = "W_OUT_IDLE_03@0",
+ .pme_name = "W_OUT_IDLE_0@0",
.pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 0)",
.pme_code = 224,
.pme_flags = 0x0,
@@ -3385,7 +3385,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_OUT_IDLE_03@1",
+ .pme_name = "W_OUT_IDLE_0@1",
.pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 1)",
.pme_code = 225,
.pme_flags = 0x0,
@@ -3399,7 +3399,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_OUT_IDLE_03@2",
+ .pme_name = "W_OUT_IDLE_0@2",
.pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 2)",
.pme_code = 226,
.pme_flags = 0x0,
@@ -3413,7 +3413,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_OUT_IDLE_03@3",
+ .pme_name = "W_OUT_IDLE_0@3",
.pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 3)",
.pme_code = 227,
.pme_flags = 0x0,
@@ -3427,7 +3427,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_OUT_IDLE_03@4",
+ .pme_name = "W_OUT_IDLE_0@4",
.pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 4)",
.pme_code = 228,
.pme_flags = 0x0,
@@ -3441,7 +3441,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_OUT_IDLE_03@5",
+ .pme_name = "W_OUT_IDLE_0@5",
.pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 5)",
.pme_code = 229,
.pme_flags = 0x0,
@@ -3455,7 +3455,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_OUT_IDLE_03@6",
+ .pme_name = "W_OUT_IDLE_0@6",
.pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 6)",
.pme_code = 230,
.pme_flags = 0x0,
@@ -3469,7 +3469,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_OUT_IDLE_03@7",
+ .pme_name = "W_OUT_IDLE_0@7",
.pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 7)",
.pme_code = 231,
.pme_flags = 0x0,
@@ -3483,7 +3483,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_OUT_IDLE_03@8",
+ .pme_name = "W_OUT_IDLE_0@8",
.pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 8)",
.pme_code = 232,
.pme_flags = 0x0,
@@ -3497,7 +3497,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_OUT_IDLE_03@9",
+ .pme_name = "W_OUT_IDLE_0@9",
.pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 9)",
.pme_code = 233,
.pme_flags = 0x0,
@@ -3511,7 +3511,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_OUT_IDLE_03@10",
+ .pme_name = "W_OUT_IDLE_0@10",
.pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 10)",
.pme_code = 234,
.pme_flags = 0x0,
@@ -3525,7 +3525,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_OUT_IDLE_03@11",
+ .pme_name = "W_OUT_IDLE_0@11",
.pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 11)",
.pme_code = 235,
.pme_flags = 0x0,
@@ -3539,7 +3539,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_OUT_IDLE_03@12",
+ .pme_name = "W_OUT_IDLE_0@12",
.pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 12)",
.pme_code = 236,
.pme_flags = 0x0,
@@ -3553,7 +3553,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_OUT_IDLE_03@13",
+ .pme_name = "W_OUT_IDLE_0@13",
.pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 13)",
.pme_code = 237,
.pme_flags = 0x0,
@@ -3567,7 +3567,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_OUT_IDLE_03@14",
+ .pme_name = "W_OUT_IDLE_0@14",
.pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 14)",
.pme_code = 238,
.pme_flags = 0x0,
@@ -3581,7 +3581,7 @@ static pme_crayx2_entry_t crayx2_pe[ ] =
.pme_nchips = PME_CRAYX2_MEMORY_CHIPS
},
{
- .pme_name = "W_OUT_IDLE_03@15",
+ .pme_name = "W_OUT_IDLE_0@15",
.pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 15)",
.pme_code = 239,
.pme_flags = 0x0,
diff --git a/src/libpfm-3.y/lib/gen_mips64_events.h b/src/libpfm-3.y/lib/gen_mips64_events.h
index 805a8b3c03bc416973ba0547348d7fc108224f58..792823b1de333da76a36af1767228f1708e46b19 100644
--- a/src/libpfm-3.y/lib/gen_mips64_events.h
+++ b/src/libpfm-3.y/lib/gen_mips64_events.h
@@ -1337,7 +1337,7 @@ static pme_gen_mips64_entry_t gen_mips64_r12000_pe[] = {
.pme_counters = 0xf,
.pme_desc = "Instructions graduated"
},
- {.pme_name="QUADWORRDS_WRITEBACK_FROM_SC",
+ {.pme_name="QUADWORDS_WRITEBACK_FROM_SC",
.pme_code = 0x07070707,
.pme_counters = 0xf,
.pme_desc = "Quadwords written back from secondary cache"
diff --git a/src/libpfm-3.y/lib/intel_atom_events.h b/src/libpfm-3.y/lib/intel_atom_events.h
index 9a5f9ed1c398722e75b4a9dea17c97fbd4154976..7ea2e1937cbdbd49685bef3dd6218ff45c443124 100644
--- a/src/libpfm-3.y/lib/intel_atom_events.h
+++ b/src/libpfm-3.y/lib/intel_atom_events.h
@@ -98,7 +98,7 @@ static pme_intel_atom_entry_t intel_atom_pe[]={
.pme_flags = PFMLIB_INTEL_ATOM_FIXED0|PFMLIB_INTEL_ATOM_PEBS,
.pme_desc = "Instructions retired"
},
-/* 3 */{.pme_name = "LAST_LEVEL_CACHE_REFERENCE",
+/* 3 */{.pme_name = "LAST_LEVEL_CACHE_REFERENCES",
.pme_code = 0x4f2e,
.pme_desc = "Last level of cache references"
},
@@ -112,14 +112,926 @@ static pme_intel_atom_entry_t intel_atom_pe[]={
},
/* 6 */{.pme_name = "MISPREDICTED_BRANCH_RETIRED",
.pme_code = 0xc5,
+ .pme_flags = PFMLIB_INTEL_ATOM_PEBS,
.pme_desc = "Mispredicted branch instruction retired"
},
/*
* BEGIN non architectural events
*/
+ { .pme_name = "SIMD_INSTR_RETIRED",
+ .pme_desc = "SIMD Instructions retired",
+ .pme_code = 0xCE,
+ .pme_flags = 0,
+ },
+ { .pme_name = "L2_REJECT_BUSQ",
+ .pme_desc = "Rejected L2 cache requests",
+ .pme_code = 0x30,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_MESI,
+ INTEL_ATOM_CORE,
+ INTEL_ATOM_PREFETCH
+ },
+ .pme_numasks = 9,
+ },
+ { .pme_name = "SIMD_SAT_INSTR_RETIRED",
+ .pme_desc = "Saturated arithmetic instructions retired",
+ .pme_code = 0xCF,
+ .pme_flags = 0,
+ },
+ { .pme_name = "ICACHE",
+ .pme_desc = "Instruction fetches",
+ .pme_code = 0x80,
+ .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO,
+ .pme_umasks = {
+ { .pme_uname = "ACCESSES",
+ .pme_udesc = "Instruction fetches, including uncacheacble fetches",
+ .pme_ucode = 0x3,
+ },
+ { .pme_uname = "MISSES",
+ .pme_udesc = "count all instructions fetches that miss tha icache or produce memory requests. This includes uncacheache fetches. Any instruction fetch miss is counted only once and not once for every cycle it is outstanding",
+ .pme_ucode = 0x2,
+ },
+ },
+ .pme_numasks = 2
+ },
+ { .pme_name = "L2_LOCK",
+ .pme_desc = "L2 locked accesses",
+ .pme_code = 0x2B,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_MESI,
+ INTEL_ATOM_CORE
+ },
+ .pme_numasks = 7
+ },
+ { .pme_name = "UOPS_RETIRED",
+ .pme_desc = "Micro-ops retired",
+ .pme_code = 0xC2,
+ .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO,
+ .pme_umasks = {
+ { .pme_uname = "ANY",
+ .pme_udesc = "Micro-ops retired",
+ .pme_ucode = 0x10,
+ },
+ { .pme_uname = "STALLED_CYCLES",
+ .pme_udesc = "Cycles no micro-ops retired",
+ .pme_ucode = 0x1d010, /* inv=1 cnt_mask=1 */
+ },
+ { .pme_uname = "STALLS",
+ .pme_udesc = "Periods no micro-ops retired",
+ .pme_ucode = 0x1d410, /* inv=1 edge=1, cnt_mask=1 */
+ },
+ },
+ .pme_numasks = 3
+ },
+ { .pme_name = "L2_M_LINES_OUT",
+ .pme_desc = "Modified lines evicted from the L2 cache",
+ .pme_code = 0x27,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_CORE,
+ INTEL_ATOM_PREFETCH
+ },
+ .pme_numasks = 4
+ },
+ { .pme_name = "SIMD_COMP_INST_RETIRED",
+ .pme_desc = "Retired computational Streaming SIMD Extensions (SSE) instructions",
+ .pme_code = 0xCA,
+ .pme_flags = 0,
+ .pme_umasks = {
+ { .pme_uname = "PACKED_SINGLE",
+ .pme_udesc = "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions",
+ .pme_ucode = 0x1,
+ },
+ { .pme_uname = "SCALAR_SINGLE",
+ .pme_udesc = "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions",
+ .pme_ucode = 0x2,
+ },
+ { .pme_uname = "PACKED_DOUBLE",
+ .pme_udesc = "Retired computational Streaming SIMD Extensions 2 (SSE2) packed-double instructions",
+ .pme_ucode = 0x4,
+ },
+ { .pme_uname = "SCALAR_DOUBLE",
+ .pme_udesc = "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions",
+ .pme_ucode = 0x8,
+ },
+ },
+ .pme_numasks = 4
+ },
+ { .pme_name = "SNOOP_STALL_DRV",
+ .pme_desc = "Bus stalled for snoops",
+ .pme_code = 0x7E,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_CORE,
+ INTEL_ATOM_AGENT,
+ },
+ .pme_numasks = 4
+ },
+ { .pme_name = "BUS_TRANS_BURST",
+ .pme_desc = "Burst (full cache-line) bus transactions",
+ .pme_code = 0x6E,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_CORE,
+ INTEL_ATOM_AGENT,
+ },
+ .pme_numasks = 4
+ },
+ { .pme_name = "SIMD_SAT_UOP_EXEC",
+ .pme_desc = "SIMD saturated arithmetic micro-ops executed",
+ .pme_code = 0xB1,
+ .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO,
+ .pme_umasks = {
+ { .pme_uname = "S",
+ .pme_udesc = "SIMD saturated arithmetic micro-ops executed",
+ .pme_ucode = 0x0,
+ },
+ { .pme_uname = "AR",
+ .pme_udesc = "SIMD saturated arithmetic micro-ops retired",
+ .pme_ucode = 0x80,
+ },
+ },
+ .pme_numasks = 2
+ },
+ { .pme_name = "BUS_TRANS_IO",
+ .pme_desc = "IO bus transactions",
+ .pme_code = 0x6C,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_CORE,
+ INTEL_ATOM_AGENT
+ },
+ .pme_numasks = 4
+ },
+ { .pme_name = "BUS_TRANS_RFO",
+ .pme_desc = "RFO bus transactions",
+ .pme_code = 0x66,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_CORE,
+ INTEL_ATOM_AGENT
+ },
+ .pme_numasks = 4
+ },
+ { .pme_name = "SIMD_ASSIST",
+ .pme_desc = "SIMD assists invoked",
+ .pme_code = 0xCD,
+ .pme_flags = 0,
+ },
+ { .pme_name = "INST_RETIRED",
+ .pme_desc = "Instructions retired",
+ .pme_code = 0xC0,
+ .pme_flags = 0,
+ .pme_umasks = {
+ { .pme_uname = "ANY_P",
+ .pme_udesc = "Instructions retired using generic counter (precise event)",
+ .pme_ucode = 0x0,
+ .pme_flags = PFMLIB_INTEL_ATOM_PEBS
+ },
+ },
+ .pme_numasks = 1
+ },
+ { .pme_name = "L1D_CACHE",
+ .pme_desc = "L1 Cacheable Data Reads",
+ .pme_code = 0x40,
+ .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO,
+ .pme_umasks = {
+ { .pme_uname = "LD",
+ .pme_udesc = "L1 Cacheable Data Reads",
+ .pme_ucode = 0x21,
+ },
+ { .pme_uname = "ST",
+ .pme_udesc = "L1 Cacheable Data Writes",
+ .pme_ucode = 0x22,
+ },
+ },
+ .pme_numasks = 2
+ },
+ { .pme_name = "MUL",
+ .pme_desc = "Multiply operations executed",
+ .pme_code = 0x12,
+ .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO,
+ .pme_umasks = {
+ { .pme_uname = "S",
+ .pme_udesc = "Multiply operations executed",
+ .pme_ucode = 0x1,
+ },
+ { .pme_uname = "AR",
+ .pme_udesc = "Multiply operations retired",
+ .pme_ucode = 0x81,
+ },
+ },
+ .pme_numasks = 2
+ },
+ { .pme_name = "DIV",
+ .pme_desc = "Divide operations executed",
+ .pme_code = 0x13,
+ .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO,
+ .pme_umasks = {
+ { .pme_uname = "S",
+ .pme_udesc = "Divide operations executed",
+ .pme_ucode = 0x1,
+ },
+ { .pme_uname = "AR",
+ .pme_udesc = "Divide operations retired",
+ .pme_ucode = 0x81,
+ },
+ },
+ .pme_numasks = 2
+ },
+ { .pme_name = "BUS_TRANS_P",
+ .pme_desc = "Partial bus transactions",
+ .pme_code = 0x6b,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_AGENT,
+ INTEL_ATOM_CORE,
+ },
+ .pme_numasks = 4
+ },
+ { .pme_name = "BUS_IO_WAIT",
+ .pme_desc = "IO requests waiting in the bus queue",
+ .pme_code = 0x7F,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_CORE
+ },
+ .pme_numasks = 2
+ },
+ { .pme_name = "L2_M_LINES_IN",
+ .pme_desc = "L2 cache line modifications",
+ .pme_code = 0x25,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_CORE
+ },
+ .pme_numasks = 2
+ },
+ { .pme_name = "L2_LINES_IN",
+ .pme_desc = "L2 cache misses",
+ .pme_code = 0x24,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_CORE,
+ INTEL_ATOM_PREFETCH
+ },
+ .pme_numasks = 4
+ },
+ { .pme_name = "BUSQ_EMPTY",
+ .pme_desc = "Bus queue is empty",
+ .pme_code = 0x7D,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_CORE
+ },
+ .pme_numasks = 2
+ },
+ { .pme_name = "L2_IFETCH",
+ .pme_desc = "L2 cacheable instruction fetch requests",
+ .pme_code = 0x28,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_MESI,
+ INTEL_ATOM_CORE
+ },
+ .pme_numasks = 7
+ },
+ { .pme_name = "BUS_HITM_DRV",
+ .pme_desc = "HITM signal asserted",
+ .pme_code = 0x7B,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_AGENT
+ },
+ .pme_numasks = 2
+ },
+ { .pme_name = "ITLB",
+ .pme_desc = "ITLB hits",
+ .pme_code = 0x82,
+ .pme_flags = 0,
+ .pme_umasks = {
+ { .pme_uname = "FLUSH",
+ .pme_udesc = "ITLB flushes",
+ .pme_ucode = 0x4,
+ },
+ { .pme_uname = "MISSES",
+ .pme_udesc = "ITLB misses",
+ .pme_ucode = 0x2,
+ },
+ },
+ .pme_numasks = 2
+ },
+ { .pme_name = "BUS_TRANS_MEM",
+ .pme_desc = "Memory bus transactions",
+ .pme_code = 0x6F,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_CORE,
+ INTEL_ATOM_AGENT,
+ },
+ .pme_numasks = 4
+ },
+ { .pme_name = "BUS_TRANS_PWR",
+ .pme_desc = "Partial write bus transaction",
+ .pme_code = 0x6A,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_CORE,
+ INTEL_ATOM_AGENT,
+ },
+ .pme_numasks = 4
+ },
+ { .pme_name = "BR_INST_DECODED",
+ .pme_desc = "Branch instructions decoded",
+ .pme_code = 0x1E0,
+ .pme_flags = 0,
+ },
+ { .pme_name = "BUS_TRANS_INVAL",
+ .pme_desc = "Invalidate bus transactions",
+ .pme_code = 0x69,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_CORE,
+ INTEL_ATOM_AGENT
+ },
+ .pme_numasks = 4
+ },
+ { .pme_name = "SIMD_UOP_TYPE_EXEC",
+ .pme_desc = "SIMD micro-ops executed",
+ .pme_code = 0xB3,
+ .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO,
+ .pme_umasks = {
+ { .pme_uname = "MUL_S",
+ .pme_udesc = "SIMD packed multiply micro-ops executed",
+ .pme_ucode = 0x1,
+ },
+ { .pme_uname = "MUL_AR",
+ .pme_udesc = "SIMD packed multiply micro-ops retired",
+ .pme_ucode = 0x81,
+ },
+ { .pme_uname = "SHIFT_S",
+ .pme_udesc = "SIMD packed shift micro-ops executed",
+ .pme_ucode = 0x2,
+ },
+ { .pme_uname = "SHIFT_AR",
+ .pme_udesc = "SIMD packed shift micro-ops retired",
+ .pme_ucode = 0x82,
+ },
+ { .pme_uname = "PACK_S",
+ .pme_udesc = "SIMD packed micro-ops executed",
+ .pme_ucode = 0x4,
+ },
+ { .pme_uname = "PACK_AR",
+ .pme_udesc = "SIMD packed micro-ops retired",
+ .pme_ucode = 0x84,
+ },
+ { .pme_uname = "UNPACK_S",
+ .pme_udesc = "SIMD unpacked micro-ops executed",
+ .pme_ucode = 0x8,
+ },
+ { .pme_uname = "UNPACK_AR",
+ .pme_udesc = "SIMD unpacked micro-ops retired",
+ .pme_ucode = 0x88,
+ },
+ { .pme_uname = "LOGICAL_S",
+ .pme_udesc = "SIMD packed logical micro-ops executed",
+ .pme_ucode = 0x10,
+ },
+ { .pme_uname = "LOGICAL_AR",
+ .pme_udesc = "SIMD packed logical micro-ops retired",
+ .pme_ucode = 0x90,
+ },
+ { .pme_uname = "ARITHMETIC_S",
+ .pme_udesc = "SIMD packed arithmetic micro-ops executed",
+ .pme_ucode = 0x20,
+ },
+ { .pme_uname = "ARITHMETIC_AR",
+ .pme_udesc = "SIMD packed arithmetic micro-ops retired",
+ .pme_ucode = 0xA0,
+ },
+ },
+ .pme_numasks = 12
+ },
+ { .pme_name = "SIMD_INST_RETIRED",
+ .pme_desc = "Retired Streaming SIMD Extensions (SSE)",
+ .pme_code = 0xC7,
+ .pme_flags = 0,
+ .pme_umasks = {
+ { .pme_uname = "PACKED_SINGLE",
+ .pme_udesc = "Retired Streaming SIMD Extensions (SSE) packed-single instructions",
+ .pme_ucode = 0x1,
+ },
+ { .pme_uname = "SCALAR_SINGLE",
+ .pme_udesc = "Retired Streaming SIMD Extensions (SSE) scalar-single instructions",
+ .pme_ucode = 0x2,
+ },
+ { .pme_uname = "PACKED_DOUBLE",
+ .pme_udesc = "Retired Streaming SIMD Extensions 2 (SSE2) packed-double instructions",
+ .pme_ucode = 0x4,
+ },
+ { .pme_uname = "SCALAR_DOUBLE",
+ .pme_udesc = "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions",
+ .pme_ucode = 0x8,
+ },
+ { .pme_uname = "VECTOR",
+ .pme_udesc = "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions",
+ .pme_ucode = 0x10,
+ },
+ { .pme_uname = "ANY",
+ .pme_udesc = "Retired Streaming SIMD instructions",
+ .pme_ucode = 0x1F,
+ },
+ },
+ .pme_numasks = 6
+ },
+ { .pme_name = "CYCLES_DIV_BUSY",
+ .pme_desc = "Cycles the divider is busy",
+ .pme_code = 0x14,
+ .pme_flags = 0,
+ },
+ { .pme_name = "PREFETCH",
+ .pme_desc = "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed",
+ .pme_code = 0x7,
+ .pme_flags = 0,
+ .pme_umasks = {
+ { .pme_uname = "PREFETCHT0",
+ .pme_udesc = "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed",
+ .pme_ucode = 0x01,
+ },
+ { .pme_uname = "SW_L2",
+ .pme_udesc = "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed",
+ .pme_ucode = 0x06,
+ },
+ { .pme_uname = "PREFETCHNTA",
+ .pme_udesc = "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",
+ .pme_ucode = 0x08,
+ },
+ },
+ .pme_numasks = 3
+ },
+ { .pme_name = "L2_RQSTS",
+ .pme_desc = "L2 cache requests",
+ .pme_code = 0x2E,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_CORE,
+ INTEL_ATOM_PREFETCH,
+ INTEL_ATOM_MESI
+ },
+ .pme_numasks = 9
+ },
+ { .pme_name = "SIMD_UOPS_EXEC",
+ .pme_desc = "SIMD micro-ops executed (excluding stores)",
+ .pme_code = 0xB0,
+ .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO,
+ .pme_umasks = {
+ { .pme_uname = "S",
+ .pme_udesc = "number of SMD saturated arithmetic micro-ops executed",
+ .pme_ucode = 0x0,
+ },
+ { .pme_uname = "AR",
+ .pme_udesc = "number of SIMD saturated arithmetic micro-ops retired",
+ .pme_ucode = 0x80,
+ },
+ },
+ .pme_numasks = 2
+ },
+ { .pme_name = "HW_INT_RCV",
+ .pme_desc = "Hardware interrupts received",
+ .pme_code = 0xC8,
+ .pme_flags = 0,
+ },
+ { .pme_name = "BUS_TRANS_BRD",
+ .pme_desc = "Burst read bus transactions",
+ .pme_code = 0x65,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_AGENT,
+ INTEL_ATOM_CORE
+ },
+ .pme_numasks = 4
+ },
+ { .pme_name = "BOGUS_BR",
+ .pme_desc = "Bogus branches",
+ .pme_code = 0xE4,
+ .pme_flags = 0,
+ },
+ { .pme_name = "BUS_DATA_RCV",
+ .pme_desc = "Bus cycles while processor receives data",
+ .pme_code = 0x64,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_CORE,
+ },
+ .pme_numasks = 2
+ },
+ { .pme_name = "MACHINE_CLEARS",
+ .pme_desc = "Self-Modifying Code detected",
+ .pme_code = 0xC3,
+ .pme_flags = 0,
+ .pme_umasks = {
+ { .pme_uname = "SMC",
+ .pme_udesc = "Self-Modifying Code detected",
+ .pme_ucode = 0x1,
+ },
+ },
+ .pme_numasks = 1
+ },
+ { .pme_name = "BR_INST_RETIRED",
+ .pme_desc = "Retired branch instructions",
+ .pme_code = 0xC4,
+ .pme_flags = 0,
+ .pme_umasks = {
+ { .pme_uname = "ANY",
+ .pme_udesc = "Retired branch instructions",
+ .pme_ucode = 0x0,
+ },
+ { .pme_uname = "PRED_NOT_TAKEN",
+ .pme_udesc = "Retired branch instructions that were predicted not-taken",
+ .pme_ucode = 0x1,
+ },
+ { .pme_uname = "MISPRED_NOT_TAKEN",
+ .pme_udesc = "Retired branch instructions that were mispredicted not-taken",
+ .pme_ucode = 0x2,
+ },
+ { .pme_uname = "PRED_TAKEN",
+ .pme_udesc = "Retired branch instructions that were predicted taken",
+ .pme_ucode = 0x4,
+ },
+ { .pme_uname = "MISPRED_TAKEN",
+ .pme_udesc = "Retired branch instructions that were mispredicted taken",
+ .pme_ucode = 0x8,
+ },
+ { .pme_uname = "MISPRED",
+ .pme_udesc = "Retired mispredicted branch instructions (precise event)",
+ .pme_flags = PFMLIB_INTEL_ATOM_PEBS,
+ .pme_ucode = 0xA,
+ },
+ { .pme_uname = "TAKEN",
+ .pme_udesc = "Retired taken branch instructions",
+ .pme_ucode = 0xC,
+ },
+ { .pme_uname = "ANY1",
+ .pme_udesc = "Retired branch instructions",
+ .pme_ucode = 0xF,
+ },
+ },
+ .pme_numasks = 8
+ },
+ { .pme_name = "L2_ADS",
+ .pme_desc = "Cycles L2 address bus is in use",
+ .pme_code = 0x21,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_CORE
+ },
+ .pme_numasks = 2
+ },
+ { .pme_name = "EIST_TRANS",
+ .pme_desc = "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
+ .pme_code = 0x3A,
+ .pme_flags = 0,
+ },
+ { .pme_name = "BUS_TRANS_WB",
+ .pme_desc = "Explicit writeback bus transactions",
+ .pme_code = 0x67,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_CORE,
+ INTEL_ATOM_AGENT
+ },
+ .pme_numasks = 4
+ },
+ { .pme_name = "MACRO_INSTS",
+ .pme_desc = "Macro instructions decoded",
+ .pme_code = 0xAA,
+ .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO,
+ .pme_umasks = {
+ { .pme_uname = "NON_CISC_DECODED",
+ .pme_udesc = "Non-CISC macro instructions decoded",
+ .pme_ucode = 0x1,
+ },
+ { .pme_uname = "ALL_DECODED",
+ .pme_udesc = "All Instructions decoded",
+ .pme_ucode = 0x3,
+ },
+ },
+ .pme_numasks = 2
+ },
+ { .pme_name = "L2_LINES_OUT",
+ .pme_desc = "L2 cache lines evicted",
+ .pme_code = 0x26,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_CORE,
+ INTEL_ATOM_PREFETCH
+ },
+ .pme_numasks = 4
+ },
+ { .pme_name = "L2_LD",
+ .pme_desc = "L2 cache reads",
+ .pme_code = 0x29,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_CORE,
+ INTEL_ATOM_PREFETCH,
+ INTEL_ATOM_MESI
+ },
+ .pme_numasks = 9
+ },
+ { .pme_name = "SEGMENT_REG_LOADS",
+ .pme_desc = "Number of segment register loads",
+ .pme_code = 0x6,
+ .pme_flags = 0,
+ .pme_umasks = {
+ { .pme_uname = "ANY",
+ .pme_udesc = "Number of segment register loads",
+ .pme_ucode = 0x80,
+ },
+ },
+ .pme_numasks = 1
+ },
+ { .pme_name = "L2_NO_REQ",
+ .pme_desc = "Cycles no L2 cache requests are pending",
+ .pme_code = 0x32,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_CORE
+ },
+ .pme_numasks = 2
+ },
+ { .pme_name = "THERMAL_TRIP",
+ .pme_desc = "Number of thermal trips",
+ .pme_code = 0xC03B,
+ .pme_flags = 0,
+ },
+ { .pme_name = "EXT_SNOOP",
+ .pme_desc = "External snoops",
+ .pme_code = 0x77,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_MESI,
+ INTEL_ATOM_CORE
+ },
+ .pme_numasks = 7
+ },
+ { .pme_name = "BACLEARS",
+ .pme_desc = "BACLEARS asserted",
+ .pme_code = 0xE6,
+ .pme_flags = 0,
+ .pme_umasks = {
+ { .pme_uname = "ANY",
+ .pme_udesc = "BACLEARS asserted",
+ .pme_ucode = 0x1,
+ },
+ },
+ .pme_numasks = 1
+ },
+ { .pme_name = "CYCLES_INT_MASKED",
+ .pme_desc = "Cycles during which interrupts are disabled",
+ .pme_code = 0xC6,
+ .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO,
+ .pme_umasks = {
+ { .pme_uname = "CYCLES_INT_MASKED",
+ .pme_udesc = "Cycles during which interrupts are disabled",
+ .pme_ucode = 0x1,
+ },
+ { .pme_uname = "CYCLES_INT_PENDING_AND_MASKED",
+ .pme_udesc = "Cycles during which interrupts are pending and disabled",
+ .pme_ucode = 0x2,
+ },
+ },
+ .pme_numasks = 2
+ },
+ { .pme_name = "FP_ASSIST",
+ .pme_desc = "Floating point assists",
+ .pme_code = 0x11,
+ .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO,
+ .pme_umasks = {
+ { .pme_uname = "S",
+ .pme_udesc = "Floating point assists for executed instructions",
+ .pme_ucode = 0x1,
+ },
+ { .pme_uname = "AR",
+ .pme_udesc = "Floating point assists for retired instructions",
+ .pme_ucode = 0x81,
+ },
+ },
+ .pme_numasks = 2
+ },
+ { .pme_name = "L2_ST",
+ .pme_desc = "L2 store requests",
+ .pme_code = 0x2A,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_MESI,
+ INTEL_ATOM_CORE
+ },
+ .pme_numasks = 7
+ },
+ { .pme_name = "BUS_TRANS_DEF",
+ .pme_desc = "Deferred bus transactions",
+ .pme_code = 0x6D,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_CORE,
+ INTEL_ATOM_AGENT
+ },
+ .pme_numasks = 4
+ },
+ { .pme_name = "DATA_TLB_MISSES",
+ .pme_desc = "Memory accesses that missed the DTLB",
+ .pme_code = 0x8,
+ .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO,
+ .pme_umasks = {
+ { .pme_uname = "DTLB_MISS",
+ .pme_udesc = "Memory accesses that missed the DTLB",
+ .pme_ucode = 0x7,
+ },
+ { .pme_uname = "DTLB_MISS_LD",
+ .pme_udesc = "DTLB misses due to load operations",
+ .pme_ucode = 0x5,
+ },
+ { .pme_uname = "L0_DTLB_MISS_LD",
+ .pme_udesc = "L0 (micro-TLB) misses due to load operations",
+ .pme_ucode = 0x9,
+ },
+ { .pme_uname = "DTLB_MISS_ST",
+ .pme_udesc = "DTLB misses due to store operations",
+ .pme_ucode = 0x6,
+ },
+ },
+ .pme_numasks = 4
+ },
+ { .pme_name = "BUS_BNR_DRV",
+ .pme_desc = "Number of Bus Not Ready signals asserted",
+ .pme_code = 0x61,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_AGENT
+ },
+ .pme_numasks = 2
+ },
+ { .pme_name = "STORE_FORWARDS",
+ .pme_desc = "All store forwards",
+ .pme_code = 0x2,
+ .pme_flags = 0,
+ .pme_umasks = {
+ { .pme_uname = "GOOD",
+ .pme_udesc = "Good store forwards",
+ .pme_ucode = 0x81,
+ },
+ },
+ .pme_numasks = 1
+ },
+ { .pme_name = "CPU_CLK_UNHALTED",
+ .pme_code = 0x3c,
+ .pme_desc = "Core cycles when core is not halted",
+ .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO,
+ .pme_umasks = {
+ { .pme_uname = "CORE_P",
+ .pme_udesc = "Core cycles when core is not halted",
+ .pme_ucode = 0x0,
+ },
+ { .pme_uname = "BUS",
+ .pme_udesc = "Bus cycles when core is not halted. This event can give a measurement of the elapsed time. This events has a constant ratio with CPU_CLK_UNHALTED:REF event, which is the maximum bus to processor frequency ratio",
+ .pme_ucode = 0x1,
+ },
+ { .pme_uname = "NO_OTHER",
+ .pme_udesc = "Bus cycles when core is active and other is halted",
+ .pme_ucode = 0x2,
+ },
+
+ },
+ .pme_numasks = 3
+ },
+ { .pme_name = "BUS_TRANS_ANY",
+ .pme_desc = "All bus transactions",
+ .pme_code = 0x70,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_CORE,
+ INTEL_ATOM_AGENT
+ },
+ .pme_numasks = 4
+ },
+ { .pme_name = "MEM_LOAD_RETIRED",
+ .pme_desc = "Retired loads that hit the L2 cache (precise event)",
+ .pme_code = 0xCB,
+ .pme_flags = 0,
+ .pme_umasks = {
+ { .pme_uname = "L2_HIT",
+ .pme_udesc = "Retired loads that hit the L2 cache (precise event)",
+ .pme_ucode = 0x1,
+ .pme_flags = PFMLIB_INTEL_ATOM_PEBS
+ },
+ { .pme_uname = "L2_MISS",
+ .pme_udesc = "Retired loads that miss the L2 cache (precise event)",
+ .pme_ucode = 0x2,
+ .pme_flags = PFMLIB_INTEL_ATOM_PEBS
+ },
+ { .pme_uname = "DTLB_MISS",
+ .pme_udesc = "Retired loads that miss the DTLB (precise event)",
+ .pme_ucode = 0x4,
+ .pme_flags = PFMLIB_INTEL_ATOM_PEBS
+ },
+ },
+ .pme_numasks = 3
+ },
+ { .pme_name = "X87_COMP_OPS_EXE",
+ .pme_desc = "Floating point computational micro-ops executed",
+ .pme_code = 0x10,
+ .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO,
+ .pme_umasks = {
+ { .pme_uname = "ANY_S",
+ .pme_udesc = "Floating point computational micro-ops executed",
+ .pme_ucode = 0x1,
+ },
+ { .pme_uname = "ANY_AR",
+ .pme_udesc = "Floating point computational micro-ops retired",
+ .pme_ucode = 0x81,
+ },
+ },
+ .pme_numasks = 2
+ },
+ { .pme_name = "PAGE_WALKS",
+ .pme_desc = "Number of page-walks executed",
+ .pme_code = 0xC,
+ .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO,
+ .pme_umasks = {
+ { .pme_uname = "WALKS",
+ .pme_udesc = "Number of page-walks executed",
+ .pme_ucode = 0x3 | 1ul << 10,
+ },
+ { .pme_uname = "CYCLES",
+ .pme_udesc = "Duration of page-walks in core cycles",
+ .pme_ucode = 0x3,
+ },
+ },
+ .pme_numasks = 2
+ },
+ { .pme_name = "BUS_LOCK_CLOCKS",
+ .pme_desc = "Bus cycles when a LOCK signal is asserted",
+ .pme_code = 0x63,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_AGENT,
+ INTEL_ATOM_CORE
+ },
+ .pme_numasks = 4
+ },
+ { .pme_name = "BUS_REQUEST_OUTSTANDING",
+ .pme_desc = "Outstanding cacheable data read bus requests duration",
+ .pme_code = 0x60,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_AGENT,
+ INTEL_ATOM_CORE
+ },
+ .pme_numasks = 4
+ },
+ { .pme_name = "BUS_TRANS_IFETCH",
+ .pme_desc = "Instruction-fetch bus transactions",
+ .pme_code = 0x68,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_AGENT,
+ INTEL_ATOM_CORE
+ },
+ .pme_numasks = 4
+ },
+ { .pme_name = "BUS_HIT_DRV",
+ .pme_desc = "HIT signal asserted",
+ .pme_code = 0x7A,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_AGENT
+ },
+ .pme_numasks = 2
+ },
+ { .pme_name = "BUS_DRDY_CLOCKS",
+ .pme_desc = "Bus cycles when data is sent on the bus",
+ .pme_code = 0x62,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_AGENT
+ },
+ .pme_numasks = 2
+ },
+ { .pme_name = "L2_DBUS_BUSY",
+ .pme_desc = "Cycles the L2 cache data bus is busy",
+ .pme_code = 0x22,
+ .pme_flags = 0,
+ .pme_umasks = {
+ INTEL_ATOM_CORE
+ },
+ .pme_numasks = 2
+ },
};
-#define PME_INTEL_ATOM_UNHALTED_INTEL_ATOM_CYCLES 0
+#define PME_INTEL_ATOM_UNHALTED_CORE_CYCLES 0
#define PME_INTEL_ATOM_INSTRUCTIONS_RETIRED 2
#define PME_INTEL_ATOM_EVENT_COUNT (sizeof(intel_atom_pe)/sizeof(pme_intel_atom_entry_t))
diff --git a/src/libpfm-3.y/lib/intel_corei7_events.h b/src/libpfm-3.y/lib/intel_corei7_events.h
index 7c706ee2e0ac6c474810bd56ddc288a274578046..5a2c29403b033225e47b0484bcfdbc118c9319fd 100644
--- a/src/libpfm-3.y/lib/intel_corei7_events.h
+++ b/src/libpfm-3.y/lib/intel_corei7_events.h
@@ -32,28 +32,44 @@ static pme_nhm_entry_t corei7_pe[]={
.pme_flags = PFMLIB_NHM_FIXED1,
.pme_desc = "count core clock cycles whenever the clock signal on the specific core is running (not halted). Alias to event CPU_CLK_UNHALTED:THREAD"
},
- {.pme_name = "INSTRUCTIONS_RETIRED",
+ {.pme_name = "INSTRUCTION_RETIRED",
.pme_code = 0x00c0,
.pme_cntmsk = 0x1000f,
.pme_flags = PFMLIB_NHM_FIXED0|PFMLIB_NHM_PEBS,
.pme_desc = "count the number of instructions at retirement. Alias to event INST_RETIRED:ANY_P",
},
+ {.pme_name = "INSTRUCTIONS_RETIRED",
+ .pme_code = 0x00c0,
+ .pme_cntmsk = 0x1000f,
+ .pme_flags = PFMLIB_NHM_FIXED0|PFMLIB_NHM_PEBS,
+ .pme_desc = "This is an alias for INSTRUCTION_RETIRED",
+ },
{.pme_name = "UNHALTED_REFERENCE_CYCLES",
.pme_code = 0x013c,
.pme_cntmsk = 0x40000,
.pme_flags = PFMLIB_NHM_FIXED2_ONLY,
.pme_desc = "Unhalted reference cycles",
},
- {.pme_name = "LAST_LEVEL_CACHE_REFERENCES",
+ {.pme_name = "LLC_REFERENCES",
.pme_code = 0x4f2e,
.pme_cntmsk = 0xf,
.pme_desc = "count each request originating from the core to reference a cache line in the last level cache. The count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to L2_RQSTS:SELF_DEMAND_MESI",
},
- {.pme_name = "LAST_LEVEL_CACHE_MISSES",
+ {.pme_name = "LAST_LEVEL_CACHE_REFERENCES",
+ .pme_code = 0x4f2e,
+ .pme_cntmsk = 0xf,
+ .pme_desc = "This is an alias for LLC_REFERENCES",
+ },
+ {.pme_name = "LLC_MISSES",
.pme_code = 0x412e,
.pme_cntmsk = 0xf,
.pme_desc = "count each cache miss condition for references to the last level cache. The event count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to event L2_RQSTS:SELF_DEMAND_I_STATE",
},
+ {.pme_name = "LAST_LEVEL_CACHE_MISSES",
+ .pme_code = 0x412e,
+ .pme_cntmsk = 0xf,
+ .pme_desc = "This is an alias for LLC_MISSES",
+ },
{.pme_name = "BRANCH_INSTRUCTIONS_RETIRED",
.pme_code = 0x00c4,
.pme_cntmsk = 0xf,
@@ -62,1784 +78,2057 @@ static pme_nhm_entry_t corei7_pe[]={
/*
* BEGIN core specific events
*/
+ { .pme_name = "ARITH",
+ .pme_desc = "Counts arithmetic multiply and divide operations",
+ .pme_code = 0x14,
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
+ { .pme_uname = "CYCLES_DIV_BUSY",
+ .pme_udesc = "Counts the number of cycles the divider is busy executing divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE.",
+ .pme_ucode = 0x01,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "DIV",
+ .pme_udesc = "Counts the number of divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE.",
+ .pme_ucode = 0x01 | (1<<16) | (1<<15) | (1<<10), /* cmask=1 �invert=1 �edge=1 */
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "MUL",
+ .pme_udesc = "Counts the number of multiply operations executed. This includes integer as well as floating point multiply operations but excludes DPPS mul and MPSAD.",
+ .pme_ucode = 0x02,
+ .pme_uflags = 0,
+ },
+ },
+ .pme_numasks = 3
+ },
+
{ .pme_name = "BACLEAR",
- .pme_desc = "BACLEAR asserted with bad target address",
+ .pme_desc = "Branch address calculator",
.pme_code = 0xE6,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "BAD_TARGET",
.pme_udesc = "BACLEAR asserted with bad target address",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "CLEAR",
.pme_udesc = "BACLEAR asserted, regardless of cause",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 2
- },
+ },
{ .pme_name = "BACLEAR_FORCE_IQ",
.pme_desc = "Instruction queue forced BACLEAR",
.pme_code = 0x01A7,
.pme_flags = 0,
- },
+ },
+ { .pme_name = "BOGUS_BR",
+ .pme_desc = "Counts the number of bogus branches.",
+ .pme_code = 0x01E4,
+ .pme_flags = 0,
+ },
{ .pme_name = "BPU_CLEARS",
- .pme_desc = "Early Branch Prediciton Unit clears",
+ .pme_desc = "Branch prediction Unit clears",
.pme_code = 0xE8,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "EARLY",
.pme_udesc = "Early Branch Prediciton Unit clears",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "LATE",
.pme_udesc = "Late Branch Prediction Unit clears",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "ANY",
.pme_udesc = "count any Branch Prediction Unit clears",
.pme_ucode = 0x03,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 3
- },
+ },
{ .pme_name = "BPU_MISSED_CALL_RET",
- .pme_desc = "Branch prediction unit missed call or retur",
+ .pme_desc = "Branch prediction unit missed call or return",
.pme_code = 0x01E5,
.pme_flags = 0,
- },
+ },
{ .pme_name = "BR_INST_DECODED",
.pme_desc = "Branch instructions decoded",
.pme_code = 0x01E0,
.pme_flags = 0,
- },
+ },
{ .pme_name = "BR_INST_EXEC",
.pme_desc = "Branch instructions executed",
.pme_code = 0x88,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "ANY",
.pme_udesc = "Branch instructions executed",
.pme_ucode = 0x7F,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "COND",
.pme_udesc = "Conditional branch instructions executed",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "DIRECT",
.pme_udesc = "Unconditional branches executed",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "DIRECT_NEAR_CALL",
.pme_udesc = "Unconditional call branches executed",
.pme_ucode = 0x10,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "INDIRECT_NEAR_CALL",
.pme_udesc = "Indirect call branches executed",
.pme_ucode = 0x20,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "INDIRECT_NON_CALL",
.pme_udesc = "Indirect non call branches executed",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "NEAR_CALLS",
.pme_udesc = "Call branches executed",
.pme_ucode = 0x30,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "NON_CALLS",
.pme_udesc = "All non call branches executed",
.pme_ucode = 0x07,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "RETURN_NEAR",
.pme_udesc = "Indirect return branches executed",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "TAKEN",
.pme_udesc = "Taken branches executed",
.pme_ucode = 0x40,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 10
- },
+ },
{ .pme_name = "BR_INST_RETIRED",
.pme_desc = "Retired branch instructions",
.pme_code = 0xC4,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "ALL_BRANCHES",
.pme_udesc = "Retired branch instructions (Precise Event)",
.pme_ucode = 0x04,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
{ .pme_uname = "CONDITIONAL",
.pme_udesc = "Retired conditional branch instructions (Precise Event)",
.pme_ucode = 0x01,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
{ .pme_uname = "NEAR_CALL",
.pme_udesc = "Retired near call instructions (Precise Event)",
.pme_ucode = 0x02,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
},
.pme_numasks = 3
- },
+ },
{ .pme_name = "BR_MISP_EXEC",
.pme_desc = "Mispredicted branches executed",
.pme_code = 0x89,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "ANY",
.pme_udesc = "Mispredicted branches executed",
.pme_ucode = 0x7F,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "COND",
.pme_udesc = "Mispredicted conditional branches executed",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "DIRECT",
.pme_udesc = "Mispredicted unconditional branches executed",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "DIRECT_NEAR_CALL",
.pme_udesc = "Mispredicted non call branches executed",
.pme_ucode = 0x10,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "INDIRECT_NEAR_CALL",
.pme_udesc = "Mispredicted indirect call branches executed",
.pme_ucode = 0x20,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "INDIRECT_NON_CALL",
.pme_udesc = "Mispredicted indirect non call branches executed",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "NEAR_CALLS",
.pme_udesc = "Mispredicted call branches executed",
.pme_ucode = 0x30,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "NON_CALLS",
.pme_udesc = "Mispredicted non call branches executed",
.pme_ucode = 0x07,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "RETURN_NEAR",
.pme_udesc = "Mispredicted return branches executed",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "TAKEN",
.pme_udesc = "Mispredicted taken branches executed",
.pme_ucode = 0x40,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 10
- },
+ },
+ { .pme_name = "BR_MISP_RETIRED",
+ .pme_desc = "Count Mispredicted Branch Activity",
+ .pme_code = 0xC5,
+ .pme_flags = 0,
+ .pme_umasks = {
+ { .pme_uname = "NEAR_CALL",
+ .pme_udesc = "Counts mispredicted direct and indirect near unconditional retired calls",
+ .pme_ucode = 0x02,
+ .pme_uflags = 0,
+ },
+ },
+ .pme_numasks = 1
+ },
{ .pme_name = "CACHE_LOCK_CYCLES",
- .pme_desc = "Cycles L1D locked",
+ .pme_desc = "Cache lock cycles",
.pme_code = 0x63,
.pme_flags = PFMLIB_NHM_PMC01,
- .pme_umasks = {
+ .pme_umasks = {
{ .pme_uname = "L1D",
.pme_udesc = "Cycles L1D locked",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "L1D_L2",
.pme_udesc = "Cycles L1D and L2 locked",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 2
- },
+ },
{ .pme_name = "CPU_CLK_UNHALTED",
- .pme_desc = "Cycles when thread is not halted",
+ .pme_desc = "Cycles when processor is not in halted state",
.pme_code = 0x3C,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "THREAD_P",
.pme_udesc = "Cycles when thread is not halted (programmable counter)",
.pme_ucode = 0x00,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "REF_P",
.pme_udesc = "Reference base clock (133 Mhz) cycles when thread is not halted",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 2
- },
+ },
{ .pme_name = "DTLB_LOAD_MISSES",
- .pme_desc = "DTLB load misses",
+ .pme_desc = "Data TLB load misses",
.pme_code = 0x08,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "ANY",
.pme_udesc = "DTLB load misses",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PDE_MISS",
.pme_udesc = "DTLB load miss caused by low part of address",
.pme_ucode = 0x20,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "WALK_COMPLETED",
.pme_udesc = "DTLB load miss page walks complete",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "STLB_HIT",
.pme_udesc = "DTLB second level hit",
.pme_ucode = 0x10,
.pme_uflags = 0,
- },
+ },
+ { .pme_uname = "PDP_MISS",
+ .pme_udesc = "Number of DTLB cache load misses where the high part of the linear to physical address translation was missed",
+ .pme_ucode = 0x40,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "LARGE_WALK_COMPLETED",
+ .pme_udesc = "Counts number of completed large page walks due to load miss in the STLB",
+ .pme_ucode = 0x80,
+ .pme_uflags = 0,
+ },
},
- .pme_numasks = 4
- },
+ .pme_numasks = 6
+ },
{ .pme_name = "DTLB_MISSES",
- .pme_desc = "DTLB misses",
+ .pme_desc = "Data TLB misses",
.pme_code = 0x49,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "ANY",
.pme_udesc = "DTLB misses",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "STLB_HIT",
.pme_udesc = "DTLB first level misses but second level hit",
.pme_ucode = 0x10,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "WALK_COMPLETED",
.pme_udesc = "DTLB miss page walks",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
+ { .pme_uname = "PDE_MISS",
+ .pme_udesc = "Number of DTLB cache misses where the low part of the linear to physical address translation was missed",
+ .pme_ucode = 0x20,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "PDP_MISS",
+ .pme_udesc = "Number of DTLB misses where the high part of the linear to physical address translation was missed",
+ .pme_ucode = 0x40,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "LARGE_WALK_COMPLETED",
+ .pme_udesc = "Counts number of completed large page walks due to misses in the STLB",
+ .pme_ucode = 0x80,
+ .pme_uflags = 0,
+ },
},
- .pme_numasks = 3
- },
+ .pme_numasks = 6
+ },
{ .pme_name = "EPT",
- .pme_desc = "Extended Page Directory Entry miss",
+ .pme_desc = "Extended Page Directory",
.pme_code = 0x4F,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "EPDE_MISS",
.pme_udesc = "Extended Page Directory Entry miss",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "EPDPE_MISS",
.pme_udesc = "Extended Page Directory Pointer miss",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "EPDPE_HIT",
.pme_udesc = "Extended Page Directory Pointer hit",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 3
- },
+ },
{ .pme_name = "ES_REG_RENAMES",
.pme_desc = "ES segment renames",
.pme_code = 0x01D5,
.pme_flags = 0,
- },
+ },
{ .pme_name = "FP_ASSIST",
.pme_desc = "Floating point assists",
.pme_code = 0xF7,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "ALL",
.pme_udesc = "Floating point assists (Precise Event)",
.pme_ucode = 0x01,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
{ .pme_uname = "INPUT",
.pme_udesc = "Floating poiint assists for invalid input value (Precise Event)",
.pme_ucode = 0x04,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
{ .pme_uname = "OUTPUT",
.pme_udesc = "Floating point assists for invalid output value (Precise Event)",
.pme_ucode = 0x02,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
},
.pme_numasks = 3
- },
+ },
{ .pme_name = "FP_COMP_OPS_EXE",
- .pme_desc = "MMX Uops",
+ .pme_desc = "Floating point computational micro-ops",
.pme_code = 0x10,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "MMX",
.pme_udesc = "MMX Uops",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "SSE_DOUBLE_PRECISION",
.pme_udesc = "SSE* FP double precision Uops",
.pme_ucode = 0x80,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "SSE_FP",
.pme_udesc = "SSE and SSE2 FP Uops",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "SSE_FP_PACKED",
.pme_udesc = "SSE FP packed Uops",
.pme_ucode = 0x10,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "SSE_FP_SCALAR",
.pme_udesc = "SSE FP scalar Uops",
.pme_ucode = 0x20,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "SSE_SINGLE_PRECISION",
.pme_udesc = "SSE* FP single precision Uops",
.pme_ucode = 0x40,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "SSE2_INTEGER",
.pme_udesc = "SSE2 integer Uops",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "X87",
.pme_udesc = "Computational floating-point operations executed",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 8
- },
+ },
{ .pme_name = "FP_MMX_TRANS",
- .pme_desc = "All Floating Point to and from MMX transitions",
+ .pme_desc = "Floating Point to and from MMX transitions",
.pme_code = 0xCC,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "ANY",
.pme_udesc = "All Floating Point to and from MMX transitions",
.pme_ucode = 0x03,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "TO_FP",
.pme_udesc = "Transitions from MMX to Floating Point instructions",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "TO_MMX",
.pme_udesc = "Transitions from Floating Point to MMX instructions",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
+ },
+ .pme_numasks = 3
+ },
+ { .pme_name = "HW_INT",
+ .pme_desc = "Hardware interrupts",
+ .pme_code = 0x1D,
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
+ { .pme_uname = "RCV",
+ .pme_udesc = "Number of interrupt received",
+ .pme_ucode = 0x01,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "CYCLES_MASKED",
+ .pme_udesc = "Number of cycles interrupt are masked",
+ .pme_ucode = 0x02,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "CYCLES_PENDING_AND_MASKED",
+ .pme_udesc = "Number of cycles interrupts are pending and masked",
+ .pme_ucode = 0x04,
+ .pme_uflags = 0,
+ },
},
.pme_numasks = 3
- },
+ },
+ { .pme_name = "IFU_IVC",
+ .pme_desc = "Instruction Fetch unit victim cache",
+ .pme_code = 0x81,
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
+ { .pme_uname = "FULL",
+ .pme_udesc = "Instruction Fetche unit victim cache full",
+ .pme_ucode = 0x01,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "L1I_EVICTION",
+ .pme_udesc = "L1 Instruction cache evictions",
+ .pme_ucode = 0x02,
+ .pme_uflags = 0,
+ },
+ },
+ .pme_numasks = 2
+ },
{ .pme_name = "ILD_STALL",
- .pme_desc = "Any Instruction Length Decoder stall cycles",
+ .pme_desc = "Instruction Length Decoder stalls",
.pme_code = 0x87,
.pme_flags = 0,
- .pme_umasks = {
+ .pme_umasks = {
{ .pme_uname = "ANY",
.pme_udesc = "Any Instruction Length Decoder stall cycles",
.pme_ucode = 0x0F,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "IQ_FULL",
.pme_udesc = "Instruction Queue full stall cycles",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "LCP",
.pme_udesc = "Length Change Prefix stall cycles",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "MRU",
.pme_udesc = "Stall cycles due to BPU MRU bypass",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "REGEN",
.pme_udesc = "Regen stall cycles",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 5
- },
+ },
{ .pme_name = "INST_DECODED",
- .pme_desc = "Instructions that must be decoded by decoder 0",
+ .pme_desc = "Instructions decoded",
.pme_code = 0x18,
.pme_flags = 0,
- .pme_umasks = {
+ .pme_umasks = {
{ .pme_uname = "DEC0",
.pme_udesc = "Instructions that must be decoded by decoder 0",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 1
- },
+ },
{ .pme_name = "INST_QUEUE_WRITES",
.pme_desc = "Instructions written to instruction queue.",
.pme_code = 0x0117,
.pme_flags = 0,
- },
+ },
{ .pme_name = "INST_QUEUE_WRITE_CYCLES",
.pme_desc = "Cycles instructions are written to the instruction queue",
.pme_code = 0x011E,
.pme_flags = 0,
- },
+ },
{ .pme_name = "INST_RETIRED",
.pme_desc = "Instructions retired",
.pme_code = 0xC0,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "ANY_P",
.pme_udesc = "Instructions Retired (Precise Event)",
.pme_ucode = 0x00,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
- { .pme_uname = "MMX",
- .pme_udesc = "Retired MMX instructions (Precise Event)",
- .pme_ucode = 0x04,
- .pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
{ .pme_uname = "X87",
.pme_udesc = "Retired floating-point operations (Precise Event)",
.pme_ucode = 0x02,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
},
- .pme_numasks = 3
- },
+ .pme_numasks = 2
+ },
{ .pme_name = "IO_TRANSACTIONS",
.pme_desc = "I/O transactions",
.pme_code = 0x016C,
.pme_flags = 0,
- },
+ },
+ { .pme_name = "ITLB_FLUSH",
+ .pme_desc = "Counts the number of ITLB flushes",
+ .pme_code = 0x01AE,
+ .pme_flags = 0,
+ },
{ .pme_name = "ITLB_MISSES",
- .pme_desc = "ITLB miss",
+ .pme_desc = "Instruction TLB misses",
.pme_code = 0x85,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "ANY",
.pme_udesc = "ITLB miss",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "WALK_COMPLETED",
.pme_udesc = "ITLB miss page walks",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
+ { .pme_uname = "STLB_HIT",
+ .pme_udesc = "Counts the number of ITLB misses that hit in the second level TLB",
+ .pme_ucode = 0x10,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "PDE_MISS",
+ .pme_udesc = "Number of ITLB misses where the low part of the linear to physical address translation was missed",
+ .pme_ucode = 0x20,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "PDP_MISS",
+ .pme_udesc = "Number of ITLB misses where the high part of the linear to physical address translation was missed",
+ .pme_ucode = 0x40,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "LARGE_WALK_COMPLETED",
+ .pme_udesc = "Counts number of completed large page walks due to misses in the STLB",
+ .pme_ucode = 0x80,
+ .pme_uflags = 0,
+ },
},
- .pme_numasks = 2
- },
+ .pme_numasks = 6
+ },
{ .pme_name = "ITLB_MISS_RETIRED",
.pme_desc = "Retired instructions that missed the ITLB (Precise Event)",
.pme_code = 0x20C8,
.pme_flags = PFMLIB_NHM_PEBS,
- },
+ },
{ .pme_name = "L1D",
- .pme_desc = "L1D cache lines replaced in M state",
+ .pme_desc = "L1D cache",
.pme_code = 0x51,
- .pme_flags = PFMLIB_NHM_PMC01,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_PMC01|PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "M_EVICT",
.pme_udesc = "L1D cache lines replaced in M state",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "M_REPL",
.pme_udesc = "L1D cache lines allocated in the M state",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "M_SNOOP_EVICT",
.pme_udesc = "L1D snoop eviction of cache lines in M state",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "REPL",
.pme_udesc = "L1 data cache lines allocated",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 4
- },
+ },
{ .pme_name = "L1D_ALL_REF",
- .pme_desc = "All references to the L1 data cache",
+ .pme_desc = "L1D references",
.pme_code = 0x43,
- .pme_flags = PFMLIB_NHM_PMC01,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_PMC01|PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "ANY",
.pme_udesc = "All references to the L1 data cache",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "CACHEABLE",
.pme_udesc = "L1 data cacheable reads and writes",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 2
- },
+ },
{ .pme_name = "L1D_CACHE_LD",
- .pme_desc = "L1 data cache read in E state",
+ .pme_desc = "L1D cacheable loads. WARNING: event may overcount loads",
.pme_code = 0x40,
- .pme_flags = PFMLIB_NHM_PMC01,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_PMC01|PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "E_STATE",
.pme_udesc = "L1 data cache read in E state",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "I_STATE",
.pme_udesc = "L1 data cache read in I state (misses)",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "M_STATE",
.pme_udesc = "L1 data cache read in M state",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "MESI",
.pme_udesc = "L1 data cache reads",
.pme_ucode = 0x0F,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "S_STATE",
.pme_udesc = "L1 data cache read in S state",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 5
- },
+ },
{ .pme_name = "L1D_CACHE_LOCK",
- .pme_desc = "L1 data cache load locks in E state",
+ .pme_desc = "L1 data cache load lock",
.pme_code = 0x42,
- .pme_flags = PFMLIB_NHM_PMC01,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_PMC01|PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "E_STATE",
.pme_udesc = "L1 data cache load locks in E state",
.pme_ucode = 0x04,
.pme_uflags = 0,
},
{ .pme_uname = "HIT",
- .pme_udesc = "L1 data cache load lock hits",
+ .pme_udesc = "L1 data cache load lock hits. WARNING: overcounts by 3x",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "M_STATE",
- .pme_udesc = "L1 data cache load locks in M state",
+ .pme_udesc = "L1 data cache load locks in M state. WARNING: overcounts by 3x",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "S_STATE",
.pme_udesc = "L1 data cache load locks in S state",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 4
- },
+ },
{ .pme_name = "L1D_CACHE_LOCK_FB_HIT",
.pme_desc = "L1D load lock accepted in fill buffer",
.pme_code = 0x0153,
.pme_flags = PFMLIB_NHM_PMC01,
- },
+ },
{ .pme_name = "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
.pme_desc = "L1D prefetch load lock accepted in fill buffer",
.pme_code = 0x0152,
.pme_flags = PFMLIB_NHM_PMC01,
- },
+ },
{ .pme_name = "L1D_CACHE_ST",
- .pme_desc = "L1 data cache stores in E state",
+ .pme_desc = "L1 data cache stores",
.pme_code = 0x41,
- .pme_flags = PFMLIB_NHM_PMC01,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_PMC01|PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "E_STATE",
.pme_udesc = "L1 data cache stores in E state",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
+ { .pme_uname = "I_STATE",
+ .pme_udesc = "L1 data cache store in the I state",
+ .pme_ucode = 0x01,
+ .pme_uflags = 0,
+ },
{ .pme_uname = "M_STATE",
.pme_udesc = "L1 data cache stores in M state",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "S_STATE",
.pme_udesc = "L1 data cache stores in S state",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
+ { .pme_uname = "MESI",
+ .pme_udesc = "L1 data cache store in all states",
+ .pme_ucode = 0x0F,
+ .pme_uflags = 0,
+ },
},
- .pme_numasks = 3
- },
+ .pme_numasks = 5
+ },
{ .pme_name = "L1D_PREFETCH",
- .pme_desc = "L1D hardware prefetch misses",
+ .pme_desc = "L1D hardware prefetch",
.pme_code = 0x4E,
- .pme_flags = PFMLIB_NHM_PMC01,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_PMC01|PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "MISS",
.pme_udesc = "L1D hardware prefetch misses",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "REQUESTS",
.pme_udesc = "L1D hardware prefetch requests",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "TRIGGERS",
.pme_udesc = "L1D hardware prefetch requests triggered",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 3
- },
+ },
{ .pme_name = "L1D_WB_L2",
- .pme_desc = "L1 writebacks to L2 in E state",
+ .pme_desc = "L1 writebacks to L2",
.pme_code = 0x28,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "E_STATE",
.pme_udesc = "L1 writebacks to L2 in E state",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "I_STATE",
.pme_udesc = "L1 writebacks to L2 in I state (misses)",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "M_STATE",
.pme_udesc = "L1 writebacks to L2 in M state",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "S_STATE",
.pme_udesc = "L1 writebacks to L2 in S state",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "MESI",
.pme_udesc = "All L1 writebacks to L2",
.pme_ucode = 0x0F,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 5
- },
+ },
{ .pme_name = "L1I",
- .pme_desc = "L1I instruction fetch stall cycles",
+ .pme_desc = "L1I instruction fetches",
.pme_code = 0x80,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "CYCLES_STALLED",
.pme_udesc = "L1I instruction fetch stall cycles",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "HITS",
.pme_udesc = "L1I instruction fetch hits",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "MISSES",
.pme_udesc = "L1I instruction fetch misses",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "READS",
.pme_udesc = "L1I Instruction fetches",
.pme_ucode = 0x03,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 4
- },
+ },
+ { .pme_name = "L1I_OPPORTUNISTIC_HITS",
+ .pme_desc = "Opportunistic hits in streaming",
+ .pme_code = 0x0183,
+ .pme_flags = 0,
+ },
{ .pme_name = "L2_DATA_RQSTS",
- .pme_desc = "All L2 data requests",
+ .pme_desc = "L2 data requests",
.pme_code = 0x26,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "ANY",
.pme_udesc = "All L2 data requests",
.pme_ucode = 0xFF,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "DEMAND_E_STATE",
.pme_udesc = "L2 data demand loads in E state",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "DEMAND_I_STATE",
.pme_udesc = "L2 data demand loads in I state (misses)",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "DEMAND_M_STATE",
.pme_udesc = "L2 data demand loads in M state",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "DEMAND_MESI",
.pme_udesc = "L2 data demand requests",
.pme_ucode = 0x0F,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "DEMAND_S_STATE",
.pme_udesc = "L2 data demand loads in S state",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PREFETCH_E_STATE",
.pme_udesc = "L2 data prefetches in E state",
.pme_ucode = 0x40,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PREFETCH_I_STATE",
.pme_udesc = "L2 data prefetches in the I state (misses)",
.pme_ucode = 0x10,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PREFETCH_M_STATE",
.pme_udesc = "L2 data prefetches in M state",
.pme_ucode = 0x80,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PREFETCH_MESI",
.pme_udesc = "All L2 data prefetches",
.pme_ucode = 0xF0,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PREFETCH_S_STATE",
.pme_udesc = "L2 data prefetches in the S state",
.pme_ucode = 0x20,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 11
- },
+ },
+ { .pme_name = "L2_HW_PREFETCH",
+ .pme_desc = "L2 HW prefetches",
+ .pme_code = 0xF3,
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
+ { .pme_uname = "HIT",
+ .pme_udesc = "Count L2 HW prefetcher detector hits",
+ .pme_ucode = 0x01,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "ALLOC",
+ .pme_udesc = "Count L2 HW prefetcher allocations",
+ .pme_ucode = 0x02,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "DATA_TRIGGER",
+ .pme_udesc = "Count L2 HW data prefetcher triggered",
+ .pme_ucode = 0x04,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "CODE_TRIGGER",
+ .pme_udesc = "Count L2 HW code prefetcher triggered",
+ .pme_ucode = 0x08,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "DCA_TRIGGER",
+ .pme_udesc = "Count L2 HW DCA prefetcher triggered",
+ .pme_ucode = 0x10,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "KICK_START",
+ .pme_udesc = "Count L2 HW prefetcher kick started",
+ .pme_ucode = 0x20,
+ .pme_uflags = 0,
+ },
+ },
+ .pme_numasks = 6
+ },
{ .pme_name = "L2_LINES_IN",
- .pme_desc = "L2 lines alloacated",
+ .pme_desc = "L2 lines allocated",
.pme_code = 0xF1,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "ANY",
- .pme_udesc = "L2 lines alloacated",
+ .pme_udesc = "any L2 lines allocated",
.pme_ucode = 0x07,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "E_STATE",
.pme_udesc = "L2 lines allocated in the E state",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "S_STATE",
.pme_udesc = "L2 lines allocated in the S state",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 3
- },
+ },
{ .pme_name = "L2_LINES_OUT",
.pme_desc = "L2 lines evicted",
.pme_code = 0xF2,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "ANY",
.pme_udesc = "L2 lines evicted",
.pme_ucode = 0x0F,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "DEMAND_CLEAN",
.pme_udesc = "L2 lines evicted by a demand request",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "DEMAND_DIRTY",
.pme_udesc = "L2 modified lines evicted by a demand request",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PREFETCH_CLEAN",
.pme_udesc = "L2 lines evicted by a prefetch request",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PREFETCH_DIRTY",
.pme_udesc = "L2 modified lines evicted by a prefetch request",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 5
- },
+ },
{ .pme_name = "L2_RQSTS",
- .pme_desc = "All L2 misses",
+ .pme_desc = "L2 requests",
.pme_code = 0x24,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "MISS",
.pme_udesc = "All L2 misses",
.pme_ucode = 0xAA,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "REFERENCES",
.pme_udesc = "All L2 requests",
.pme_ucode = 0xFF,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "IFETCH_HIT",
.pme_udesc = "L2 instruction fetch hits",
.pme_ucode = 0x10,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "IFETCH_MISS",
.pme_udesc = "L2 instruction fetch misses",
.pme_ucode = 0x20,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "IFETCHES",
.pme_udesc = "L2 instruction fetches",
.pme_ucode = 0x30,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "LD_HIT",
.pme_udesc = "L2 load hits",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "LD_MISS",
.pme_udesc = "L2 load misses",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "LOADS",
.pme_udesc = "L2 requests",
.pme_ucode = 0x03,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PREFETCH_HIT",
.pme_udesc = "L2 prefetch hits",
.pme_ucode = 0x40,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PREFETCH_MISS",
.pme_udesc = "L2 prefetch misses",
.pme_ucode = 0x80,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PREFETCHES",
.pme_udesc = "All L2 prefetches",
.pme_ucode = 0xC0,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "RFO_HIT",
.pme_udesc = "L2 RFO hits",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "RFO_MISS",
.pme_udesc = "L2 RFO misses",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "RFOS",
.pme_udesc = "L2 RFO requests",
.pme_ucode = 0x0C,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 14
- },
+ },
{ .pme_name = "L2_TRANSACTIONS",
- .pme_desc = "All L2 transactions",
+ .pme_desc = "L2 transactions",
.pme_code = 0xF0,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "ANY",
.pme_udesc = "All L2 transactions",
.pme_ucode = 0x80,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "FILL",
.pme_udesc = "L2 fill transactions",
.pme_ucode = 0x20,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "IFETCH",
.pme_udesc = "L2 instruction fetch transactions",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "L1D_WB",
.pme_udesc = "L1D writeback to L2 transactions",
.pme_ucode = 0x10,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "LOAD",
.pme_udesc = "L2 Load transactions",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PREFETCH",
.pme_udesc = "L2 prefetch transactions",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "RFO",
.pme_udesc = "L2 RFO transactions",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "WB",
.pme_udesc = "L2 writeback to LLC transactions",
.pme_ucode = 0x40,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 8
- },
+ },
{ .pme_name = "L2_WRITE",
- .pme_desc = "L2 demand lock RFOs in E state",
+ .pme_desc = "L2 demand lock/store RFO",
.pme_code = 0x27,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "LOCK_E_STATE",
.pme_udesc = "L2 demand lock RFOs in E state",
.pme_ucode = 0x40,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "LOCK_I_STATE",
.pme_udesc = "L2 demand lock RFOs in I state (misses)",
.pme_ucode = 0x10,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "LOCK_S_STATE",
.pme_udesc = "L2 demand lock RFOs in S state",
.pme_ucode = 0x20,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "LOCK_HIT",
.pme_udesc = "All demand L2 lock RFOs that hit the cache",
.pme_ucode = 0xE0,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "LOCK_M_STATE",
.pme_udesc = "L2 demand lock RFOs in M state",
.pme_ucode = 0x80,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "LOCK_MESI",
.pme_udesc = "All demand L2 lock RFOs",
.pme_ucode = 0xF0,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "RFO_HIT",
.pme_udesc = "All L2 demand store RFOs that hit the cache",
.pme_ucode = 0x0E,
.pme_uflags = 0,
- },
+ },
+ { .pme_uname = "RFO_E_STATE",
+ .pme_udesc = "L2 demand store RFOs in the E state (exclusive)",
+ .pme_ucode = 0x04,
+ .pme_uflags = 0,
+ },
{ .pme_uname = "RFO_I_STATE",
.pme_udesc = "L2 demand store RFOs in I state (misses)",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "RFO_M_STATE",
.pme_udesc = "L2 demand store RFOs in M state",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "RFO_MESI",
.pme_udesc = "All L2 demand store RFOs",
.pme_ucode = 0x0F,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "RFO_S_STATE",
.pme_udesc = "L2 demand store RFOs in S state",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
},
- .pme_numasks = 11
- },
+ .pme_numasks = 12
+ },
{ .pme_name = "LARGE_ITLB",
- .pme_desc = "Large ITLB hit",
+ .pme_desc = "Large instruction TLB",
.pme_code = 0x82,
.pme_flags = 0,
- .pme_umasks = {
+ .pme_umasks = {
{ .pme_uname = "HIT",
.pme_udesc = "Large ITLB hit",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 1
- },
+ },
{ .pme_name = "LOAD_DISPATCH",
- .pme_desc = "All loads dispatched",
+ .pme_desc = "Loads dispatched",
.pme_code = 0x13,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "ANY",
.pme_udesc = "All loads dispatched",
.pme_ucode = 0x07,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "MOB",
.pme_udesc = "Loads dispatched from the MOB",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "RS",
.pme_udesc = "Loads dispatched that bypass the MOB",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "RS_DELAYED",
.pme_udesc = "Loads dispatched from stage 305",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 4
- },
+ },
{ .pme_name = "LOAD_HIT_PRE",
.pme_desc = "Load operations conflicting with software prefetches",
.pme_code = 0x014C,
.pme_flags = PFMLIB_NHM_PMC01,
- },
+ },
{ .pme_name = "LONGEST_LAT_CACHE",
.pme_desc = "Longest latency cache reference",
.pme_code = 0x2E,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "REFERENCE",
.pme_udesc = "Longest latency cache reference",
.pme_ucode = 0x4F,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "MISS",
.pme_udesc = "Longest latency cache miss",
.pme_ucode = 0x41,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 2
- },
+ },
{ .pme_name = "LSD",
- .pme_desc = "Cycles when uops were delivered by the LSD",
+ .pme_desc = "Loop stream detector",
.pme_code = 0xA8,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "ACTIVE",
.pme_udesc = "Cycles when uops were delivered by the LSD",
.pme_ucode = 0x01 | (1<<16),
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "INACTIVE",
.pme_udesc = "Cycles no uops were delivered by the LSD",
.pme_ucode = 0x01 | (1<<16)|(1<<15),
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 2
- },
- { .pme_name = "LSD_OVERFLOW",
- .pme_desc = "Loops that cannot stream from the instruction queue",
- .pme_code = 0x0120,
- .pme_flags = 0,
- },
+ },
{ .pme_name = "MACHINE_CLEARS",
- .pme_desc = "Self-Modifying Code detected",
+ .pme_desc = "Machine Clear",
.pme_code = 0xC3,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "SMC",
.pme_udesc = "Self-Modifying Code detected",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "CYCLES",
.pme_udesc = "Cycles machine clear asserted",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "MEM_ORDER",
.pme_udesc = "Execution pipeline restart due to Memory ordering conflicts",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
+ { .pme_uname = "FUSION_ASSIST",
+ .pme_udesc = "Counts the number of macro-fusion assists",
+ .pme_ucode = 0x10,
+ .pme_uflags = 0,
+ },
},
- .pme_numasks = 3
- },
+ .pme_numasks = 4
+ },
{ .pme_name = "MACRO_INSTS",
- .pme_desc = "Instructions decoded",
+ .pme_desc = "Macro-fused instructions",
.pme_code = 0xD0,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "DECODED",
.pme_udesc = "Instructions decoded",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "FUSIONS_DECODED",
.pme_udesc = "Macro-fused instructions decoded",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 2
- },
+ },
+ { .pme_name = "MEMORY_DISAMBIGUATION",
+ .pme_desc = "Memory Disambiguation Activity",
+ .pme_code = 0x09,
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
+ { .pme_uname = "RESET",
+ .pme_udesc = "Counts memory disambiguation reset cycles",
+ .pme_ucode = 0x01,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "WATCHDOG",
+ .pme_udesc = "Counts the number of times the memory disambiguation watchdog kicked in",
+ .pme_ucode = 0x04,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "WATCH_CYCLES",
+ .pme_udesc = "Counts the cycles that the memory disambiguation watchdog is active",
+ .pme_ucode = 0x08,
+ .pme_uflags = 0,
+ },
+ },
+ .pme_numasks = 3
+ },
{ .pme_name = "MEM_INST_RETIRED",
- .pme_desc = "Memory instructions retired above programmed clocks",
+ .pme_desc = "Memory instructions retired",
.pme_code = 0x0B,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "LATENCY_ABOVE_THRESHOLD",
.pme_udesc = "Memory instructions retired above programmed clocks, minimum value threhold is 4, requires PEBS",
.pme_ucode = 0x10,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
{ .pme_uname = "LOADS",
.pme_udesc = "Instructions retired which contains a load (Precise Event)",
.pme_ucode = 0x01,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
{ .pme_uname = "STORES",
.pme_udesc = "Instructions retired which contains a store (Precise Event)",
.pme_ucode = 0x02,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
},
.pme_numasks = 3
- },
+ },
{ .pme_name = "MEM_LOAD_RETIRED",
- .pme_desc = "Retired loads that miss the DTLB",
+ .pme_desc = "Retired loads",
.pme_code = 0xCB,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "DTLB_MISS",
.pme_udesc = "Retired loads that miss the DTLB (Precise Event)",
.pme_ucode = 0x80,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
{ .pme_uname = "HIT_LFB",
.pme_udesc = "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
.pme_ucode = 0x40,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
{ .pme_uname = "L1D_HIT",
.pme_udesc = "Retired loads that hit the L1 data cache (Precise Event)",
.pme_ucode = 0x01,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
{ .pme_uname = "L2_HIT",
.pme_udesc = "Retired loads that hit the L2 cache (Precise Event)",
.pme_ucode = 0x02,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
- { .pme_uname = "LLC_MISS",
+ },
+ { .pme_uname = "L3_MISS",
.pme_udesc = "Retired loads that miss the LLC cache (Precise Event)",
.pme_ucode = 0x10,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
- { .pme_uname = "LLC_UNSHARED_HIT",
+ },
+ { .pme_uname = "LLC_MISS",
+ .pme_udesc = "This is an alias for L3_MISS",
+ .pme_ucode = 0x10,
+ .pme_uflags = PFMLIB_NHM_PEBS,
+ },
+ { .pme_uname = "L3_UNSHARED_HIT",
.pme_udesc = "Retired loads that hit valid versions in the LLC cache (Precise Event)",
.pme_ucode = 0x04,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
+ { .pme_uname = "LLC_UNSHARED_HIT",
+ .pme_udesc = "This is an alias for L3_UNSHARED_HIT",
+ .pme_ucode = 0x04,
+ .pme_uflags = PFMLIB_NHM_PEBS,
+ },
{ .pme_uname = "OTHER_CORE_L2_HIT_HITM",
.pme_udesc = "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
.pme_ucode = 0x08,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
},
- .pme_numasks = 7
- },
+ .pme_numasks = 9
+ },
{ .pme_name = "MEM_STORE_RETIRED",
- .pme_desc = "Retired stores that miss the DTLB",
+ .pme_desc = "Retired stores",
.pme_code = 0x0C,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "DTLB_MISS",
.pme_udesc = "Retired stores that miss the DTLB (Precise Event)",
.pme_ucode = 0x01,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
},
.pme_numasks = 1
- },
+ },
{ .pme_name = "MEM_UNCORE_RETIRED",
- .pme_desc = "Load instructions retired that HIT modified data in sibling core",
+ .pme_desc = "Load instructions retired which hit offcore",
.pme_code = 0x0F,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO|PFMLIB_NHM_EX,
+ .pme_umasks = {
{ .pme_uname = "OTHER_CORE_L2_HITM",
.pme_udesc = "Load instructions retired that HIT modified data in sibling core (Precise Event)",
.pme_ucode = 0x02,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
{ .pme_uname = "REMOTE_CACHE_LOCAL_HOME_HIT",
.pme_udesc = "Load instructions retired remote cache HIT data source (Precise Event)",
.pme_ucode = 0x08,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
{ .pme_uname = "REMOTE_DRAM",
.pme_udesc = "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)",
.pme_ucode = 0x10,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
{ .pme_uname = "LOCAL_DRAM",
.pme_udesc = "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)",
.pme_ucode = 0x20,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
+ /* Model 46 only (must be after common umasks) */
+ { .pme_uname = "L3_DATA_MISS_UNKNOWN",
+ .pme_udesc = "Load instructions retired where the memory reference missed L3 and data source is unknown (Model 46 only, Precise Event)",
+ .pme_ucode = 0x01,
+ .pme_umodel = 46,
+ .pme_uflags = PFMLIB_NHM_PEBS,
+ },
+ /* Model 46 only (must be after common umasks) */
{ .pme_uname = "UNCACHEABLE",
- .pme_udesc = "Load instructions retired IO (Precise Event)",
+ .pme_udesc = "Load instructions retired where the memory reference missed L1, L2, L3 caches and to perform I/O (Model 46 only, Precise Event)",
.pme_ucode = 0x80,
+ .pme_umodel = 46,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
- },
- .pme_numasks = 5
- },
- { .pme_name = "SSE_MEM_EXEC",
- .pme_desc = "Streaming SIMD L1D NTA prefetch miss",
- .pme_code = 0x4B,
- .pme_flags = PFMLIB_NHM_PMC01,
- .pme_umasks = {
- { .pme_uname = "NTA",
- .pme_udesc = "Streaming SIMD L1D NTA prefetch miss",
- .pme_ucode = 0x01,
- .pme_uflags = 0,
- },
+ },
},
- .pme_numasks = 1
- },
+ .pme_numasks = 6 /* patched at runtime for model 46 */
+ },
{ .pme_name = "OFFCORE_REQUESTS",
- .pme_desc = "All offcore requests",
+ .pme_desc = "Offcore memory requests",
.pme_code = 0xB0,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "ANY",
.pme_udesc = "All offcore requests",
.pme_ucode = 0x80,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "ANY_READ",
.pme_udesc = "Offcore read requests",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "ANY_RFO",
.pme_udesc = "Offcore RFO requests",
.pme_ucode = 0x10,
.pme_uflags = 0,
- },
+ },
+ { .pme_uname = "DEMAND_READ_CODE",
+ .pme_udesc = "Counts number of offcore demand code read requests. Does not count L2 prefetch requests.",
+ .pme_ucode = 0x02,
+ .pme_uflags = 0,
+ },
{ .pme_uname = "DEMAND_READ_DATA",
.pme_udesc = "Offcore demand data read requests",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "DEMAND_RFO",
.pme_udesc = "Offcore demand RFO requests",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "L1D_WRITEBACK",
.pme_udesc = "Offcore L1 data cache writebacks",
.pme_ucode = 0x40,
.pme_uflags = 0,
- },
+ },
+ { .pme_uname = "UNCACHED_MEM",
+ .pme_udesc = "Counts number of offcore uncached memory requests",
+ .pme_ucode = 0x20,
+ .pme_uflags = 0,
+ },
},
- .pme_numasks = 6
- },
+ .pme_numasks = 8
+ },
{ .pme_name = "OFFCORE_REQUESTS_SQ_FULL",
.pme_desc = "Counts cycles the Offcore Request buffer or Super Queue is full.",
.pme_code = 0x01B2,
.pme_flags = 0,
- },
+ },
{ .pme_name = "PARTIAL_ADDRESS_ALIAS",
.pme_desc = "False dependencies due to partial address aliasing",
.pme_code = 0x0107,
.pme_flags = 0,
- },
+ },
+ { .pme_name = "PIC_ACCESSES",
+ .pme_desc = "Programmable interrupt controller",
+ .pme_code = 0xBA,
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
+ { .pme_uname = "TPR_READS",
+ .pme_udesc = "Counts number of TPR reads",
+ .pme_ucode = 0x01,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "TPR_WRITES",
+ .pme_udesc = "Counts number of TPR writes",
+ .pme_ucode = 0x02,
+ .pme_uflags = 0,
+ },
+ },
+ .pme_numasks = 2
+ },
{ .pme_name = "RAT_STALLS",
- .pme_desc = "Flag stall cycles",
+ .pme_desc = "Register allocation table stalls",
.pme_code = 0xD2,
.pme_flags = 0,
- .pme_umasks = {
+ .pme_umasks = {
{ .pme_uname = "FLAGS",
.pme_udesc = "Flag stall cycles",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "REGISTERS",
.pme_udesc = "Partial register stall cycles",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "ROB_READ_PORT",
.pme_udesc = "ROB read port stalls cycles",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "SCOREBOARD",
.pme_udesc = "Scoreboard stall cycles",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "ANY",
.pme_udesc = "All RAT stall cycles",
.pme_ucode = 0x0F,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 5
- },
+ },
{ .pme_name = "RESOURCE_STALLS",
- .pme_desc = "FPU control word write stall cycles",
+ .pme_desc = "Processor stalls",
.pme_code = 0xA2,
.pme_flags = 0,
- .pme_umasks = {
+ .pme_umasks = {
{ .pme_uname = "FPCW",
.pme_udesc = "FPU control word write stall cycles",
.pme_ucode = 0x20,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "LOAD",
.pme_udesc = "Load buffer stall cycles",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "MXCSR",
.pme_udesc = "MXCSR rename stall cycles",
.pme_ucode = 0x40,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "RS_FULL",
.pme_udesc = "Reservation Station full stall cycles",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "STORE",
.pme_udesc = "Store buffer stall cycles",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "OTHER",
.pme_udesc = "Other Resource related stall cycles",
.pme_ucode = 0x80,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "ROB_FULL",
.pme_udesc = "ROB full stall cycles",
.pme_ucode = 0x10,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "ANY",
.pme_udesc = "Resource related stall cycles",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 8
- },
+ },
{ .pme_name = "SEG_RENAME_STALLS",
.pme_desc = "Segment rename stall cycles",
.pme_code = 0x01D4,
.pme_flags = 0,
- },
+ },
+ { .pme_name = "SEGMENT_REG_LOADS",
+ .pme_desc = "Counts number of segment register loads",
+ .pme_code = 0x01F8,
+ .pme_flags = 0,
+ },
{ .pme_name = "SIMD_INT_128",
- .pme_desc = "128 bit SIMD integer pack operations",
+ .pme_desc = "128 bit SIMD integer operations",
.pme_code = 0x12,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "PACK",
.pme_udesc = "128 bit SIMD integer pack operations",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PACKED_ARITH",
.pme_udesc = "128 bit SIMD integer arithmetic operations",
.pme_ucode = 0x20,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PACKED_LOGICAL",
.pme_udesc = "128 bit SIMD integer logical operations",
.pme_ucode = 0x10,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PACKED_MPY",
.pme_udesc = "128 bit SIMD integer multiply operations",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PACKED_SHIFT",
.pme_udesc = "128 bit SIMD integer shift operations",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "SHUFFLE_MOVE",
.pme_udesc = "128 bit SIMD integer shuffle/move operations",
.pme_ucode = 0x40,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "UNPACK",
.pme_udesc = "128 bit SIMD integer unpack operations",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 7
- },
+ },
{ .pme_name = "SIMD_INT_64",
- .pme_desc = "SIMD integer 64 bit pack operations",
+ .pme_desc = "64 bit SIMD integer operations",
.pme_code = 0xFD,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "PACK",
.pme_udesc = "SIMD integer 64 bit pack operations",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PACKED_ARITH",
.pme_udesc = "SIMD integer 64 bit arithmetic operations",
.pme_ucode = 0x20,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PACKED_LOGICAL",
.pme_udesc = "SIMD integer 64 bit logical operations",
.pme_ucode = 0x10,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PACKED_MPY",
.pme_udesc = "SIMD integer 64 bit packed multiply operations",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PACKED_SHIFT",
.pme_udesc = "SIMD integer 64 bit shift operations",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "SHUFFLE_MOVE",
.pme_udesc = "SIMD integer 64 bit shuffle/move operations",
.pme_ucode = 0x40,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "UNPACK",
.pme_udesc = "SIMD integer 64 bit unpack operations",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 7
- },
+ },
{ .pme_name = "SNOOP_RESPONSE",
- .pme_desc = "Thread responded HIT to snoop",
+ .pme_desc = "Snoop",
.pme_code = 0xB8,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "HIT",
.pme_udesc = "Thread responded HIT to snoop",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "HITE",
.pme_udesc = "Thread responded HITE to snoop",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "HITM",
.pme_udesc = "Thread responded HITM to snoop",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 3
- },
+ },
{ .pme_name = "SQ_FULL_STALL_CYCLES",
.pme_desc = "Counts cycles the Offcore Request buffer or Super Queue is full and request(s) are outstanding.",
.pme_code = 0x01F6,
.pme_flags = 0,
- },
+ },
{ .pme_name = "SQ_MISC",
- .pme_desc = "Super Queue lock splits across a cache line",
+ .pme_desc = "Super Queue Activity Related to L2 Cache Access",
.pme_code = 0xF4,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
+ { .pme_uname = "PROMOTION",
+ .pme_udesc = "Counts the number of L2 secondary misses that hit the Super Queue",
+ .pme_ucode = 0x01,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "PROMOTION_POST_GO",
+ .pme_udesc = "Counts the number of L2 secondary misses during the Super Queue filling L2",
+ .pme_ucode = 0x02,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "LRU_HINTS",
+ .pme_udesc = "Counts number of Super Queue LRU hints sent to L3",
+ .pme_ucode = 0x04,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "FILL_DROPPED",
+ .pme_udesc = "Counts the number of SQ L2 fills dropped due to L2 busy",
+ .pme_ucode = 0x08,
+ .pme_uflags = 0,
+ },
{ .pme_uname = "SPLIT_LOCK",
.pme_udesc = "Super Queue lock splits across a cache line",
.pme_ucode = 0x10,
.pme_uflags = 0,
- },
+ },
+ },
+ .pme_numasks = 5
+ },
+ { .pme_name = "SSE_MEM_EXEC",
+ .pme_desc = "Streaming SIMD executed",
+ .pme_code = 0x4B,
+ .pme_flags = 0,
+ .pme_umasks = {
+ { .pme_uname = "NTA",
+ .pme_udesc = "Streaming SIMD L1D NTA prefetch miss",
+ .pme_ucode = 0x01,
+ .pme_uflags = 0,
+ },
},
.pme_numasks = 1
- },
+ },
{ .pme_name = "SSEX_UOPS_RETIRED",
- .pme_desc = "SIMD Packed-Double Uops retired",
+ .pme_desc = "SIMD micro-ops retired",
.pme_code = 0xC7,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "PACKED_DOUBLE",
.pme_udesc = "SIMD Packed-Double Uops retired (Precise Event)",
.pme_ucode = 0x04,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
{ .pme_uname = "PACKED_SINGLE",
.pme_udesc = "SIMD Packed-Single Uops retired (Precise Event)",
.pme_ucode = 0x01,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
{ .pme_uname = "SCALAR_DOUBLE",
.pme_udesc = "SIMD Scalar-Double Uops retired (Precise Event)",
.pme_ucode = 0x08,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
{ .pme_uname = "SCALAR_SINGLE",
.pme_udesc = "SIMD Scalar-Single Uops retired (Precise Event)",
.pme_ucode = 0x02,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
{ .pme_uname = "VECTOR_INTEGER",
.pme_udesc = "SIMD Vector Integer Uops retired (Precise Event)",
.pme_ucode = 0x10,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
},
.pme_numasks = 5
- },
+ },
{ .pme_name = "STORE_BLOCKS",
- .pme_desc = "Loads delayed with at-Retirement block code",
+ .pme_desc = "Delayed loads",
.pme_code = 0x06,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "AT_RET",
.pme_udesc = "Loads delayed with at-Retirement block code",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "L1D_BLOCK",
.pme_udesc = "Cacheable loads delayed with L1D block code",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "NOT_STA",
.pme_udesc = "Loads delayed due to a store blocked for unknown data",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "STA",
.pme_udesc = "Loads delayed due to a store blocked for an unknown address",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 4
- },
+ },
{ .pme_name = "TWO_UOP_INSTS_DECODED",
- .pme_desc = "Two Uop instructions decoded",
+ .pme_desc = "Two micro-ops instructions decoded",
.pme_code = 0x0119,
.pme_flags = 0,
- },
+ },
+ { .pme_name = "UOPS_DECODED_DEC0",
+ .pme_desc = "Micro-ops decoded by decoder 0",
+ .pme_code = 0x013D,
+ .pme_flags = 0,
+ },
{ .pme_name = "UOPS_DECODED",
- .pme_desc = "Stack pointer instructions decoded",
+ .pme_desc = "Micro-ops decoded",
.pme_code = 0xD1,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "ESP_FOLDING",
.pme_udesc = "Stack pointer instructions decoded",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "ESP_SYNC",
.pme_udesc = "Stack pointer sync operations",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "MS",
.pme_udesc = "Uops decoded by Microcode Sequencer",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
- { .pme_uname = "STALL_CYCLES",
- .pme_udesc = "Cycles no Uops are decoded",
- .pme_ucode = 0x01 | (1<<16)|(1<<15), /* counter-mask=1, inv=1 */
- .pme_uflags = 0,
- },
+ },
+ { .pme_uname = "MS_CYCLES_ACTIVE",
+ .pme_udesc = "cycles in which at least one uop is decoded by Microcode Sequencer",
+ .pme_ucode = 0x2 | (1<< 16), /* counter-mask = 1 */
+ },
+
},
.pme_numasks = 4
- },
+ },
{ .pme_name = "UOPS_EXECUTED",
- .pme_desc = "Uops executed",
+ .pme_desc = "Micro-ops executed",
.pme_code = 0xB1,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "PORT0",
.pme_udesc = "Uops executed on port 0",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PORT1",
.pme_udesc = "Uops executed on port 1",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PORT2_CORE",
.pme_udesc = "Uops executed on port 2 (core count only)",
.pme_ucode = 0x04,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PORT3_CORE",
.pme_udesc = "Uops executed on port 3 (core count only)",
.pme_ucode = 0x08,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PORT4_CORE",
.pme_udesc = "Uops executed on port 4 (core count only)",
.pme_ucode = 0x10,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PORT5",
.pme_udesc = "Uops executed on port 5",
.pme_ucode = 0x20,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PORT015",
.pme_udesc = "Uops issued on ports 0, 1 or 5",
.pme_ucode = 0x40,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PORT234_CORE",
.pme_udesc = "Uops issued on ports 2, 3 or 4 (core count only)",
.pme_ucode = 0x80,
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "PORT015_STALL_CYCLES",
.pme_udesc = "Cycles no Uops issued on ports 0, 1 or 5",
.pme_ucode = 0x40 | (1<<16) | (1<<15), /* counter-mask=1, inv=1 */
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 9
- },
+ },
{ .pme_name = "UOPS_ISSUED",
- .pme_desc = "Uops issued",
+ .pme_desc = "Micro-ops issued",
.pme_code = 0x0E,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "ANY",
.pme_udesc = "Uops issued",
.pme_ucode = 0x01,
.pme_uflags = 0,
- },
- { .pme_uname = "STALL_CYCLES",
+ },
+ { .pme_uname = "STALLED_CYCLES",
.pme_udesc = "Cycles stalled no issued uops",
.pme_ucode = 0x01 | (1<<16) | (1<<15), /* counter-mask=1, inv=1 */
.pme_uflags = 0,
- },
+ },
{ .pme_uname = "FUSED",
.pme_udesc = "Fused Uops issued",
.pme_ucode = 0x02,
.pme_uflags = 0,
- },
+ },
},
.pme_numasks = 3
- },
+ },
{ .pme_name = "UOPS_RETIRED",
- .pme_desc = "Uops retired",
+ .pme_desc = "Micro-ops retired",
.pme_code = 0xC2,
- .pme_flags = 0,
- .pme_umasks = {
+ .pme_flags = PFMLIB_NHM_UMASK_NCOMBO,
+ .pme_umasks = {
{ .pme_uname = "ANY",
.pme_udesc = "Uops retired (Precise Event)",
.pme_ucode = 0x01,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
{ .pme_uname = "RETIRE_SLOTS",
.pme_udesc = "Retirement slots used (Precise Event)",
.pme_ucode = 0x02,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
{ .pme_uname = "ACTIVE_CYCLES",
.pme_udesc = "Cycles Uops are being retired (Precise Event)",
.pme_ucode = 0x01 | (1<< 16), /* counter mask = 1 */
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
{ .pme_uname = "STALL_CYCLES",
.pme_udesc = "Cycles No Uops retired (Precise Event)",
.pme_ucode = 0x01 | (1<<16) | (1<<15), /* counter-mask=1, inv=1 */
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
{ .pme_uname = "MACRO_FUSED",
.pme_udesc = "Macro-fused Uops retired (Precise Event)",
.pme_ucode = 0x04,
.pme_uflags = PFMLIB_NHM_PEBS,
- },
+ },
},
.pme_numasks = 5
- },
+ },
{ .pme_name = "UOP_UNFUSION",
- .pme_desc = "Uop unfusions due to FP exceptions",
+ .pme_desc = "Micro-ops unfusions due to FP exceptions",
.pme_code = 0x01DB,
.pme_flags = 0,
},
- { .pme_name = "SB_DRAIN",
- .pme_desc = "Store buffer drains",
- .pme_code = 0x04,
- .pme_flags = 0,
- .pme_umasks = {
- { .pme_uname = "CYCLES",
- .pme_udesc = "cycles of store buffer drains",
- .pme_ucode = 0x01,
- .pme_uflags = 0,
- },
- },
- .pme_numasks = 1
- },
/*
* BEGIN OFFCORE_RESPONSE
*/
@@ -1849,82 +2138,92 @@ static pme_nhm_entry_t corei7_pe[]={
.pme_flags = PFMLIB_NHM_OFFCORE_RSP0,
.pme_umasks = {
{ .pme_uname = "DMND_DATA_RD",
- .pme_udesc = "counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches",
+ .pme_udesc = "Request. Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches",
.pme_ucode = 0x01,
.pme_uflags = 0,
},
{ .pme_uname = "DMND_RFO",
- .pme_udesc = "counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO",
+ .pme_udesc = "Request. Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO",
.pme_ucode = 0x02,
.pme_uflags = 0,
},
{ .pme_uname = "DMND_IFETCH",
- .pme_udesc = "counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches",
+ .pme_udesc = "Request. Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches",
.pme_ucode = 0x04,
.pme_uflags = 0,
},
{ .pme_uname = "WB",
- .pme_udesc = "counts the number of writeback (modified to exclusive) transactions",
+ .pme_udesc = "Request. Counts the number of writeback (modified to exclusive) transactions",
.pme_ucode = 0x08,
.pme_uflags = 0,
},
{ .pme_uname = "PF_DATA_RD",
- .pme_udesc = "counts the number of data cacheline reads generated by L2 prefetchers",
+ .pme_udesc = "Request. Counts the number of data cacheline reads generated by L2 prefetchers",
.pme_ucode = 0x10,
.pme_uflags = 0,
},
{ .pme_uname = "PF_RFO",
- .pme_udesc = "counts the number of RFO requests generated by L2 prefetchers",
+ .pme_udesc = "Request. Counts the number of RFO requests generated by L2 prefetchers",
.pme_ucode = 0x20,
.pme_uflags = 0,
},
{ .pme_uname = "PF_IFETCH",
- .pme_udesc = "counts the number of code reads generated by L2 prefetchers",
+ .pme_udesc = "Request. Counts the number of code reads generated by L2 prefetchers",
.pme_ucode = 0x40,
.pme_uflags = 0,
},
{ .pme_uname = "OTHER",
- .pme_udesc = "counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lock",
+ .pme_udesc = "Request. Counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lock",
.pme_ucode = 0x80,
.pme_uflags = 0,
},
+ { .pme_uname = "ANY_REQUEST",
+ .pme_udesc = "Request. Counts any request type",
+ .pme_ucode = 0xff,
+ .pme_uflags = 0,
+ },
{ .pme_uname = "UNCORE_HIT",
- .pme_udesc = "counts L3 Hit: local or remote home requests that hit L3 cache in the uncore with no coherency actions required (snooping)",
+ .pme_udesc = "Response. Counts L3 Hit: local or remote home requests that hit L3 cache in the uncore with no coherency actions required (snooping)",
.pme_ucode = 0x100,
.pme_uflags = 0,
},
{ .pme_uname = "OTHER_CORE_HIT_SNP",
- .pme_udesc = "counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where no modified copies were found (clean)",
+ .pme_udesc = "Response. Counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where no modified copies were found (clean)",
.pme_ucode = 0x200,
.pme_uflags = 0,
},
{ .pme_uname = "OTHER_CORE_HITM",
- .pme_udesc = "counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where modified copies were found (HITM)",
+ .pme_udesc = "Response. Counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where modified copies were found (HITM)",
.pme_ucode = 0x400,
.pme_uflags = 0,
},
{ .pme_uname = "REMOTE_CACHE_FWD",
- .pme_udesc = "counts L3 Miss: local homed requests that missed the L3 cache and was serviced by forwarded data following a cross package snoop where no modified copies found. (Remote home requests are not counted)",
+ .pme_udesc = "Response. Counts L3 Miss: local homed requests that missed the L3 cache and was serviced by forwarded data following a cross package snoop where no modified copies found. (Remote home requests are not counted)",
.pme_ucode = 0x1000,
.pme_uflags = 0,
},
{ .pme_uname = "REMOTE_DRAM",
- .pme_udesc = "counts L3 Miss: remote home requests that missed the L3 cache and were serviced by remote DRAM",
+ .pme_udesc = "Response. Counts L3 Miss: remote home requests that missed the L3 cache and were serviced by remote DRAM",
.pme_ucode = 0x2000,
.pme_uflags = 0,
},
{ .pme_uname = "LOCAL_DRAM",
- .pme_udesc = "counts L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAM",
+ .pme_udesc = "Response. Counts L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAM",
.pme_ucode = 0x4000,
.pme_uflags = 0,
},
{ .pme_uname = "NON_DRAM",
- .pme_udesc = "Non-DRAM requests that were serviced by IOH",
+ .pme_udesc = "Response. Non-DRAM requests that were serviced by IOH",
.pme_ucode = 0x8000,
.pme_uflags = 0,
},
- },
- .pme_numasks = 15
+ { .pme_uname = "ANY_RESPONSE",
+ .pme_udesc = "Response. Counts any response type",
+ .pme_ucode = 0xf700,
+ .pme_uflags = 0,
+ },
+ },
+ .pme_numasks = 17
}
};
#define PME_COREI7_UNHALTED_CORE_CYCLES 0
diff --git a/src/libpfm-3.y/lib/intel_corei7_unc_events.h b/src/libpfm-3.y/lib/intel_corei7_unc_events.h
index 164f4156921a4a3ff62728202d7b90e526eb4999..9f2d2096352dcfdb91a199d44a5b851604f7a4d4 100644
--- a/src/libpfm-3.y/lib/intel_corei7_unc_events.h
+++ b/src/libpfm-3.y/lib/intel_corei7_unc_events.h
@@ -31,8 +31,31 @@ static pme_nhm_entry_t corei7_unc_pe[]={
.pme_code = 0x0000,
.pme_flags = PFMLIB_NHM_UNC_FIXED,
},
+ { .pme_name = "UNC_DRAM_OPEN",
+ .pme_desc = "DRAM open comamnds issued for read or write",
+ .pme_code = 0x60,
+ .pme_flags = PFMLIB_NHM_UNC,
+ .pme_umasks = {
+ { .pme_uname = "CH0",
+ .pme_udesc = "DRAM Channel 0 open comamnds issued for read or write",
+ .pme_ucode = 0x01,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "CH1",
+ .pme_udesc = "DRAM Channel 1 open comamnds issued for read or write",
+ .pme_ucode = 0x02,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "CH2",
+ .pme_udesc = "DRAM Channel 2 open comamnds issued for read or write",
+ .pme_ucode = 0x04,
+ .pme_uflags = 0,
+ },
+ },
+ .pme_numasks = 3
+ },
{ .pme_name = "UNC_DRAM_PAGE_CLOSE",
- .pme_desc = "DRAM Channel 0 page close",
+ .pme_desc = "DRAM page close due to idle timer expiration",
.pme_code = 0x61,
.pme_flags = PFMLIB_NHM_UNC,
.pme_umasks = {
@@ -519,8 +542,36 @@ static pme_nhm_entry_t corei7_unc_pe[]={
.pme_ucode = 0x04,
.pme_uflags = 0,
},
+ { .pme_uname = "IOH",
+ .pme_udesc = "Cycles QHL IOH Tracker is full",
+ .pme_ucode = 0x01,
+ .pme_uflags = 0,
+ },
},
- .pme_numasks = 2
+ .pme_numasks = 3
+ },
+ { .pme_name = "UNC_QHL_CYCLES_NOT_EMPTY",
+ .pme_desc = "Cycles QHL Tracker is not empty",
+ .pme_code = 0x22,
+ .pme_flags = PFMLIB_NHM_UNC,
+ .pme_umasks = {
+ { .pme_uname = "IOH",
+ .pme_udesc = "Cycles QHL IOH is busy",
+ .pme_ucode = 0x01,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "REMOTE",
+ .pme_udesc = "Cycles QHL Remote Tracker is busy",
+ .pme_ucode = 0x02,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "LOCAL",
+ .pme_udesc = "Cycles QHL Local Tracker is busy",
+ .pme_ucode = 0x04,
+ .pme_uflags = 0,
+ },
+ },
+ .pme_numasks = 3
},
{ .pme_name = "UNC_QHL_FRC_ACK_CNFLTS",
.pme_desc = "QHL FrcAckCnflts sent to local home",
@@ -535,6 +586,29 @@ static pme_nhm_entry_t corei7_unc_pe[]={
},
.pme_numasks = 1
},
+ { .pme_name = "UNC_QHL_OCCUPANCY",
+ .pme_desc = "Cycles QHL Tracker Allocate to Deallocate Read Occupancy",
+ .pme_code = 0x23,
+ .pme_flags = PFMLIB_NHM_UNC,
+ .pme_umasks = {
+ { .pme_uname = "IOH",
+ .pme_udesc = "Cycles QHL IOH Tracker Allocate to Deallocate Read Occupancy",
+ .pme_ucode = 0x01,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "REMOTE",
+ .pme_udesc = "Cycles QHL Remote Tracker Allocate to Deallocate Read Occupancy",
+ .pme_ucode = 0x02,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "LOCAL",
+ .pme_udesc = "Cycles QHL Local Tracker Allocate to Deallocate Read Occupancy",
+ .pme_ucode = 0x04,
+ .pme_uflags = 0,
+ },
+ },
+ .pme_numasks = 3
+ },
{ .pme_name = "UNC_QHL_REQUESTS",
.pme_desc = "Quickpath Home Logic local read requests",
.pme_code = 0x20,
@@ -560,8 +634,18 @@ static pme_nhm_entry_t corei7_unc_pe[]={
.pme_ucode = 0x01,
.pme_uflags = 0,
},
+ { .pme_uname = "IOH_WRITES",
+ .pme_udesc = "Quickpath Home Logic IOH write requests",
+ .pme_ucode = 0x02,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "REMOTE_WRITES",
+ .pme_udesc = "Quickpath Home Logic remote write requests",
+ .pme_ucode = 0x08,
+ .pme_uflags = 0,
+ },
},
- .pme_numasks = 4
+ .pme_numasks = 6
},
{ .pme_name = "UNC_QHL_TO_QMC_BYPASS",
.pme_desc = "Number of requests to QMC that bypass QHL",
@@ -569,7 +653,7 @@ static pme_nhm_entry_t corei7_unc_pe[]={
.pme_flags = PFMLIB_NHM_UNC,
},
{ .pme_name = "UNC_QMC_BUSY",
- .pme_desc = "Cycles QMC channel 0 busy with a read request",
+ .pme_desc = "Cycles QMC busy with a read request",
.pme_code = 0x29,
.pme_flags = PFMLIB_NHM_UNC,
.pme_umasks = {
@@ -607,7 +691,7 @@ static pme_nhm_entry_t corei7_unc_pe[]={
.pme_numasks = 6
},
{ .pme_name = "UNC_QMC_CANCEL",
- .pme_desc = "QMC channel 0 cancels",
+ .pme_desc = "QMC cancels",
.pme_code = 0x30,
.pme_flags = PFMLIB_NHM_UNC,
.pme_umasks = {
@@ -635,7 +719,7 @@ static pme_nhm_entry_t corei7_unc_pe[]={
.pme_numasks = 4
},
{ .pme_name = "UNC_QMC_CRITICAL_PRIORITY_READS",
- .pme_desc = "QMC channel 0 critical priority read requests",
+ .pme_desc = "QMC critical priority read requests",
.pme_code = 0x2E,
.pme_flags = PFMLIB_NHM_UNC,
.pme_umasks = {
@@ -663,7 +747,7 @@ static pme_nhm_entry_t corei7_unc_pe[]={
.pme_numasks = 4
},
{ .pme_name = "UNC_QMC_HIGH_PRIORITY_READS",
- .pme_desc = "QMC channel 0 high priority read requests",
+ .pme_desc = "QMC high priority read requests",
.pme_code = 0x2D,
.pme_flags = PFMLIB_NHM_UNC,
.pme_umasks = {
@@ -691,17 +775,17 @@ static pme_nhm_entry_t corei7_unc_pe[]={
.pme_numasks = 4
},
{ .pme_name = "UNC_QMC_ISOC_FULL",
- .pme_desc = "Cycles DRAM channel 0 full with ISOC read requests",
+ .pme_desc = "Cycles DRAM full with isochronous read requests",
.pme_code = 0x28,
.pme_flags = PFMLIB_NHM_UNC,
.pme_umasks = {
{ .pme_uname = "READ_CH0",
- .pme_udesc = "Cycles DRAM channel 0 full with ISOC read requests",
+ .pme_udesc = "Cycles DRAM channel 0 full with isochronous read requests",
.pme_ucode = 0x01,
.pme_uflags = 0,
},
{ .pme_uname = "READ_CH1",
- .pme_udesc = "Cycles DRAM channel 1 full with ISOC read requests",
+ .pme_udesc = "Cycles DRAM channel 1 full with isochronous read requests",
.pme_ucode = 0x02,
.pme_uflags = 0,
},
@@ -728,8 +812,36 @@ static pme_nhm_entry_t corei7_unc_pe[]={
},
.pme_numasks = 6
},
+ { .pme_name = "UNC_IMC_ISOC_OCCUPANCY",
+ .pme_desc = "IMC isochronous (ISOC) Read Occupancy",
+ .pme_code = 0x2B,
+ .pme_flags = PFMLIB_NHM_UNC,
+ .pme_umasks = {
+ { .pme_uname = "CH0",
+ .pme_udesc = "IMC channel 0 isochronous read request occupancy",
+ .pme_ucode = 0x01,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "CH1",
+ .pme_udesc = "IMC channel 1 isochronous read request occupancy",
+ .pme_ucode = 0x02,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "CH2",
+ .pme_udesc = "IMC channel 2 isochronous read request occupancy",
+ .pme_ucode = 0x04,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "ANY",
+ .pme_udesc = "IMC any channel isochronous read request occupancy",
+ .pme_ucode = 0x07,
+ .pme_uflags = 0,
+ },
+ },
+ .pme_numasks = 4
+ },
{ .pme_name = "UNC_QMC_NORMAL_FULL",
- .pme_desc = "Cycles DRAM channel 0 full with normal read requests",
+ .pme_desc = "Cycles DRAM full with normal read requests",
.pme_code = 0x27,
.pme_flags = PFMLIB_NHM_UNC,
.pme_umasks = {
@@ -767,7 +879,7 @@ static pme_nhm_entry_t corei7_unc_pe[]={
.pme_numasks = 6
},
{ .pme_name = "UNC_QMC_NORMAL_READS",
- .pme_desc = "QMC channel 0 normal read requests",
+ .pme_desc = "QMC normal read requests",
.pme_code = 0x2C,
.pme_flags = PFMLIB_NHM_UNC,
.pme_umasks = {
@@ -794,8 +906,31 @@ static pme_nhm_entry_t corei7_unc_pe[]={
},
.pme_numasks = 4
},
+ { .pme_name = "UNC_QMC_OCCUPANCY",
+ .pme_desc = "QMC Occupancy",
+ .pme_code = 0x2A,
+ .pme_flags = PFMLIB_NHM_UNC,
+ .pme_umasks = {
+ { .pme_uname = "CH0",
+ .pme_udesc = "IMC channel 0 normal read request occupancy",
+ .pme_ucode = 0x01,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "CH1",
+ .pme_udesc = "IMC channel 1 normal read request occupancy",
+ .pme_ucode = 0x02,
+ .pme_uflags = 0,
+ },
+ { .pme_uname = "CH2",
+ .pme_udesc = "IMC channel 2 normal read request occupancy",
+ .pme_ucode = 0x04,
+ .pme_uflags = 0,
+ },
+ },
+ .pme_numasks = 3
+ },
{ .pme_name = "UNC_QMC_PRIORITY_UPDATES",
- .pme_desc = "QMC channel 0 priority updates",
+ .pme_desc = "QMC priority updates",
.pme_code = 0x31,
.pme_flags = PFMLIB_NHM_UNC,
.pme_umasks = {
@@ -823,7 +958,7 @@ static pme_nhm_entry_t corei7_unc_pe[]={
.pme_numasks = 4
},
{ .pme_name = "UNC_QMC_WRITES",
- .pme_desc = "QMC channel 0 full cache line writes",
+ .pme_desc = "QMC full cache line writes",
.pme_code = 0x2F,
.pme_flags = PFMLIB_NHM_UNC,
.pme_umasks = {
diff --git a/src/libpfm-3.y/lib/pentium4_events.h b/src/libpfm-3.y/lib/pentium4_events.h
index ba9feee56d543dc758bf3320e41b5acf77acf428..faf87ab79acd3a5055719b75a7986eef70456c60 100644
--- a/src/libpfm-3.y/lib/pentium4_events.h
+++ b/src/libpfm-3.y/lib/pentium4_events.h
@@ -1779,6 +1779,42 @@ pentium4_event_t pentium4_events[] = {
.desc = "The marked uops are bogus.",
.bit = 1,
},
+ {.name = "L1_LD_MISS",
+ .desc = "Virtual mask for L1 cache load miss replays.",
+ .bit = 2,
+ },
+ {.name = "L2_LD_MISS",
+ .desc = "Virtual mask for L2 cache load miss replays.",
+ .bit = 3,
+ },
+ {.name = "DTLB_LD_MISS",
+ .desc = "Virtual mask for DTLB load miss replays.",
+ .bit = 4,
+ },
+ {.name = "DTLB_ST_MISS",
+ .desc = "Virtual mask for DTLB store miss replays.",
+ .bit = 5,
+ },
+ {.name = "DTLB_ALL_MISS",
+ .desc = "Virtual mask for all DTLB miss replays.",
+ .bit = 6,
+ },
+ {.name = "BR_MSP",
+ .desc = "Virtual mask for tagged mispredicted branch replays.",
+ .bit = 7,
+ },
+ {.name = "MOB_LD_REPLAY",
+ .desc = "Virtual mask for MOB load replays.",
+ .bit = 8,
+ },
+ {.name = "SP_LD_RET",
+ .desc = "Virtual mask for split load replays. Use with load_port_replay event.",
+ .bit = 9,
+ },
+ {.name = "SP_ST_RET",
+ .desc = "Virtual mask for split store replays. Use with store_port_replay event.",
+ .bit = 10,
+ },
},
},
@@ -1951,7 +1987,7 @@ pentium4_event_t pentium4_events[] = {
"retired during a clock cycle. Supported on models 3, 4, 6 only",
.event_select = 0x7,
.escr_select = 0x5,
- .allowed_escrs = { 20, 42 },
+ .allowed_escrs = { 21, 42 },
.event_masks = {
{.name = "NBOGUS",
.desc = "Non-bogus instructions.",
@@ -1965,6 +2001,7 @@ pentium4_event_t pentium4_events[] = {
},
};
#define PME_INSTR_COMPLETED 45
+#define PME_REPLAY_EVENT 37
#define PENTIUM4_EVENT_COUNT (sizeof(pentium4_events)/sizeof(pentium4_events[0]))
/* CPU_CLK_UNHALTED uses the global_power_events event.
diff --git a/src/libpfm-3.y/lib/pfmlib_cell.c b/src/libpfm-3.y/lib/pfmlib_cell.c
index 1648f5193541388a56826974ca9a1d727abf274e..07f7446fd519c6ac28120c9a9c4ea88a52877dfc 100644
--- a/src/libpfm-3.y/lib/pfmlib_cell.c
+++ b/src/libpfm-3.y/lib/pfmlib_cell.c
@@ -36,11 +36,16 @@
#include "pfmlib_cell_priv.h" /* architecture private */
#include "cell_events.h" /* PMU private */
+#define SIGNAL_TYPE_CYCLES 0
+#define PM_COUNTER_CTRL_CYLES 0x42C00000U
+
#define PFM_CELL_NUM_PMCS 24
#define PFM_CELL_EVENT_MIN 1
#define PFM_CELL_EVENT_MAX 8
#define PMX_MIN_NUM 1
#define PMX_MAX_NUM 8
+#define PFM_CELL_16BIT_CNTR_EVENT_MAX 8
+#define PFM_CELL_32BIT_CNTR_EVENT_MAX 4
#define COMMON_REG_NUMS 8
@@ -48,21 +53,29 @@
#define ENABLE_WORD1 1
#define ENABLE_WORD2 2
-#define PFM_CELL_GROUP_CONTROL_REG_GROUP0_BIT 30
-#define PFM_CELL_GROUP_CONTROL_REG_GROUP1_BIT 28
+#define PFM_CELL_GRP_CONTROL_REG_GRP0_BIT 30
+#define PFM_CELL_GRP_CONTROL_REG_GRP1_BIT 28
#define PFM_CELL_BASE_WORD_UNIT_FIELD_BIT 24
#define PFM_CELL_WORD_UNIT_FIELD_WIDTH 2
#define PFM_CELL_MAX_WORD_NUMBER 3
-#define PFM_CELL_COUNTER_CONTROL_GROUP1 0x80000000
+#define PFM_CELL_COUNTER_CONTROL_GRP1 0x80000000U
+#define PFM_CELL_DEFAULT_TRIGGER_EVENT_UNIT 0x00555500U
+#define PFM_CELL_PM_CONTROL_16BIT_CNTR_MASK 0x01E00000U
+#define PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_PROBLEM 0x00080000U
+#define PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_SUPERVISOR 0x00000000U
+#define PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_HYPERVISOR 0x00040000U
+#define PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_ALL 0x000C0000U
+#define PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_MASK 0x000C0000U
#define ONLY_WORD(x) \
- ((x == WORD_0_ONLY)||(x == WORD_2_ONLY)) ? x : 0
+ ((x == WORD_0_ONLY)||(x == WORD_2_ONLY)) ? x : 0
struct pfm_cell_signal_group_desc {
unsigned int signal_type;
unsigned int word_type;
unsigned long long word;
unsigned long long freq;
+ unsigned int subunit;
};
#define swap_int(num1, num2) do { \
@@ -71,16 +84,12 @@ struct pfm_cell_signal_group_desc {
num2 = tmp; \
} while(0)
-static int pmx_ctrl_bits;
-
static int
pfm_cell_detect(void)
{
int ret;
char buffer[128];
- pmx_ctrl_bits = 0;
-
ret = __pfm_getcpuinfo_attr("cpu", buffer, sizeof(buffer));
if (ret == -1) {
return PFMLIB_ERR_NOTSUPP;
@@ -93,7 +102,7 @@ pfm_cell_detect(void)
}
static int
-get_pmx_offset(int pmx_num)
+get_pmx_offset(int pmx_num, unsigned int *pmx_ctrl_bits)
{
/* pmx_num==0 -> not specified
* pmx_num==1 -> pm0
@@ -107,8 +116,8 @@ get_pmx_offset(int pmx_num)
/* offset is specified */
offset = (pmx_num - 1);
- if ((~pmx_ctrl_bits >> offset) & 0x1) {
- pmx_ctrl_bits |= (0x1 << offset);
+ if ((~*pmx_ctrl_bits >> offset) & 0x1) {
+ *pmx_ctrl_bits |= (0x1 << offset);
return offset;
} else {
/* offset is used */
@@ -116,10 +125,10 @@ get_pmx_offset(int pmx_num)
}
} else if (pmx_num == 0){
/* offset is not specified */
- while (((pmx_ctrl_bits >> i) & 0x1) && (i < PMX_MAX_NUM)) {
+ while (((*pmx_ctrl_bits >> i) & 0x1) && (i < PMX_MAX_NUM)) {
i++;
}
- pmx_ctrl_bits |= (0x1 << i);
+ *pmx_ctrl_bits |= (0x1 << i);
return i;
}
/* pmx_num is invalid */
@@ -138,14 +147,70 @@ search_enable_word(int word)
return count;
}
+static int get_count_bit(unsigned int type)
+{
+ int count = 0;
+
+ while(type) {
+ if (type & 1) {
+ count++;
+ }
+ type >>= 1;
+ }
+ return count;
+}
+
+
static int
get_debug_bus_word(struct pfm_cell_signal_group_desc *group0, struct pfm_cell_signal_group_desc *group1)
{
- if (group1->signal_type != NONE_SIGNAL) {
+ unsigned int word_type0, word_type1;
+
+ /* search enable word */
+ word_type0 = group0->word_type;
+ word_type1 = group1->word_type;
+
+ if (group1->signal_type == NONE_SIGNAL) {
+ group0->word = search_enable_word(word_type0);
+ goto found;
+ }
+
+ /* swap */
+ if ((get_count_bit(word_type0) > get_count_bit(word_type1)) ||
+ (group0->freq == PFM_CELL_PME_FREQ_SPU)) {
+ swap_int(group0->signal_type, group1->signal_type);
+ swap_int(group0->freq, group1->freq);
+ swap_int(group0->word_type, group1->word_type);
+ swap_int(group0->subunit, group1->subunit);
+ swap_int(word_type0, word_type1);
+ }
+
+ if ((ONLY_WORD(word_type0) != 0) && (word_type0 == word_type1)) {
return PFMLIB_ERR_INVAL;
}
- group0->word = search_enable_word(group0->word_type);
+ if (ONLY_WORD(word_type0)) {
+ group0->word = search_enable_word(ONLY_WORD(word_type0));
+
+ word_type1 &= ~(1UL << (group0->word));
+ group1->word = search_enable_word(word_type1);
+ } else if (ONLY_WORD(word_type1)) {
+ group1->word = search_enable_word(ONLY_WORD(word_type1));
+
+ word_type0 &= ~(1UL << (group1->word));
+ group0->word = search_enable_word(word_type0);
+ } else {
+ group0->word = ENABLE_WORD0;
+ if (word_type1 == WORD_0_AND_1) {
+ group1->word = ENABLE_WORD1;
+ } else if(word_type1 == WORD_0_AND_2) {
+ group1->word = ENABLE_WORD2;
+ } else {
+ return PFMLIB_ERR_INVAL;
+ }
+ }
+
+found:
return PFMLIB_SUCCESS;
}
@@ -159,35 +224,64 @@ static unsigned int get_signal_bit(unsigned long long event_code)
return (event_code & 0x00000000FFFFFFFFULL) % 100;
}
+static int is_spe_signal_group(unsigned int signal_type)
+{
+ if (41 <= signal_type && signal_type <= 56) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
static int
check_signal_type(pfmlib_input_param_t *inp,
- struct pfm_cell_signal_group_desc *group0, struct pfm_cell_signal_group_desc *group1)
+ pfmlib_cell_input_param_t *mod_in,
+ struct pfm_cell_signal_group_desc *group0,
+ struct pfm_cell_signal_group_desc *group1)
{
pfmlib_event_t *e;
unsigned int event_cnt;
int signal_cnt = 0;
int i;
- unsigned int signal_type;
-
+ int cycles_signal_cnt = 0;
+ unsigned int signal_type, subunit;
+
e = inp->pfp_events;
event_cnt = inp->pfp_event_count;
for(i = 0; i < event_cnt; i++) {
signal_type = get_signal_type(cell_pe[e[i].event].pme_code);
-
+
+ if ((signal_type == SIGNAL_SPU_TRIGGER)
+ || (signal_type == SIGNAL_SPU_EVENT)) {
+ continue;
+ }
+
+ if (signal_type == SIGNAL_TYPE_CYCLES) {
+ cycles_signal_cnt = 1;
+ continue;
+ }
+
+ subunit = 0;
+ if (is_spe_signal_group(signal_type)) {
+ subunit = mod_in->pfp_cell_counters[i].spe_subunit;
+ }
switch(signal_cnt) {
case 0:
group0->signal_type = signal_type;
group0->word_type = cell_pe[e[i].event].pme_enable_word;
group0->freq = cell_pe[e[i].event].pme_freq;
+ group0->subunit = subunit;
signal_cnt++;
break;
case 1:
- if (group0->signal_type != signal_type) {
+ if ((group0->signal_type != signal_type) ||
+ (is_spe_signal_group(signal_type) && group0->subunit != subunit)) {
group1->signal_type = signal_type;
group1->word_type = cell_pe[e[i].event].pme_enable_word;
group1->freq = cell_pe[e[i].event].pme_freq;
+ group1->subunit = subunit;
signal_cnt++;
}
@@ -196,21 +290,63 @@ check_signal_type(pfmlib_input_param_t *inp,
case 2:
if ((group0->signal_type != signal_type)
&& (group1->signal_type != signal_type)) {
- DPRINT(("signal count is invalid\n"));
+ DPRINT("signal count is invalid\n");
return PFMLIB_ERR_INVAL;
}
break;
default:
- DPRINT(("signal count is invalid\n"));
+ DPRINT("signal count is invalid\n");
return PFMLIB_ERR_INVAL;
}
}
- return signal_cnt;
+ return (signal_cnt + cycles_signal_cnt);
+}
+
+/*
+ * The assignment between the privilege leve options
+ * and ppu-count-mode field in pm_control register.
+ *
+ * option ppu count mode(pm_control)
+ * ---------------------------------
+ * -u(-3) 0b10 : Problem mode
+ * -k(-0) 0b00 : Supervisor mode
+ * -1 0b00 : Supervisor mode
+ * -2 0b01 : Hypervisor mode
+ * two options 0b11 : Any mode
+ *
+ * Note : Hypervisor-mode and Any-mode don't work on PS3.
+ *
+ */
+static unsigned int get_ppu_count_mode(unsigned int plm)
+{
+ unsigned int ppu_count_mode = 0;
+
+ switch (plm) {
+ case PFM_PLM0:
+ case PFM_PLM1:
+ ppu_count_mode = PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_SUPERVISOR;
+ break;
+
+ case PFM_PLM2:
+ ppu_count_mode = PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_HYPERVISOR;
+ break;
+
+ case PFM_PLM3:
+ ppu_count_mode = PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_PROBLEM;
+ break;
+
+ default :
+ ppu_count_mode = PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_ALL;
+ break;
+ }
+ return ppu_count_mode;
}
static int
-pfm_cell_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_cell_input_param_t *mod_in, pfmlib_output_param_t *outp)
+pfm_cell_dispatch_counters(pfmlib_input_param_t *inp,
+ pfmlib_cell_input_param_t *mod_in,
+ pfmlib_output_param_t *outp)
{
pfmlib_event_t *e;
pfmlib_reg_t *pc, *pd;
@@ -224,91 +360,124 @@ pfm_cell_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_cell_input_param_t
int input_control, polarity, count_cycle, count_enable;
unsigned long long subunit;
int shift0, shift1;
+ unsigned int pmx_ctrl_bits;
+ int max_event_cnt = PFM_CELL_32BIT_CNTR_EVENT_MAX;
count_enable = 1;
-
+
group[0].signal_type = group[1].signal_type = NONE_SIGNAL;
group[0].word = group[1].word = 0L;
group[0].freq = group[1].freq = 0L;
+ group[0].subunit = group[1].subunit = 0;
group[0].word_type = group[1].word_type = WORD_NONE;
event_cnt = inp->pfp_event_count;
e = inp->pfp_events;
pc = outp->pfp_pmcs;
pd = outp->pfp_pmds;
-
+
/* check event_cnt */
- if ((event_cnt < PFM_CELL_EVENT_MIN) || (event_cnt > PFM_CELL_EVENT_MAX)) {
- DPRINT(("event count is invalid\n"));
- return PFMLIB_ERR_INVAL;
- }
+ if (mod_in->control & PFM_CELL_PM_CONTROL_16BIT_CNTR_MASK)
+ max_event_cnt = PFM_CELL_16BIT_CNTR_EVENT_MAX;
+ if (event_cnt < PFM_CELL_EVENT_MIN)
+ return PFMLIB_ERR_NOTFOUND;
+ if (event_cnt > max_event_cnt)
+ return PFMLIB_ERR_TOOMANY;
/* check signal type */
- signal_cnt = check_signal_type(inp, &group[0], &group[1]);
- if (signal_cnt == PFMLIB_ERR_INVAL) {
- DPRINT(("signal type is invalid\n"));
- return PFMLIB_ERR_INVAL;
- }
+ signal_cnt = check_signal_type(inp, mod_in, &group[0], &group[1]);
+ if (signal_cnt == PFMLIB_ERR_INVAL)
+ return PFMLIB_ERR_NOASSIGN;
/* decide debug_bus word */
- if (signal_cnt != 0) {
+ if (signal_cnt != 0 && group[0].signal_type != NONE_SIGNAL) {
ret = get_debug_bus_word(&group[0], &group[1]);
- if (ret != PFMLIB_SUCCESS) {
- return ret;
- }
+ if (ret != PFMLIB_SUCCESS)
+ return PFMLIB_ERR_NOASSIGN;
}
/* common register setting */
- pc[0].reg_num = REG_GROUP_CONTROL;
+ pc[pmcs_cnt].reg_num = REG_GROUP_CONTROL;
if (signal_cnt == 1) {
- pc[0].reg_value = group[0].word << PFM_CELL_GROUP_CONTROL_REG_GROUP0_BIT;
+ pc[pmcs_cnt].reg_value =
+ group[0].word << PFM_CELL_GRP_CONTROL_REG_GRP0_BIT;
} else if (signal_cnt == 2) {
- pc[0].reg_value = (group[0].word << PFM_CELL_GROUP_CONTROL_REG_GROUP0_BIT) |
- (group[1].word << PFM_CELL_GROUP_CONTROL_REG_GROUP1_BIT);
+ pc[pmcs_cnt].reg_value =
+ (group[0].word << PFM_CELL_GRP_CONTROL_REG_GRP0_BIT) |
+ (group[1].word << PFM_CELL_GRP_CONTROL_REG_GRP1_BIT);
}
-
- pc[1].reg_num = REG_DEBUG_BUS_CONTROL;
+ pmcs_cnt++;
+
+ pc[pmcs_cnt].reg_num = REG_DEBUG_BUS_CONTROL;
if (signal_cnt == 1) {
shift0 = PFM_CELL_BASE_WORD_UNIT_FIELD_BIT +
- ((PFM_CELL_MAX_WORD_NUMBER - group[0].word) * PFM_CELL_WORD_UNIT_FIELD_WIDTH);
- pc[1].reg_value = group[0].freq << shift0;
+ ((PFM_CELL_MAX_WORD_NUMBER - group[0].word) *
+ PFM_CELL_WORD_UNIT_FIELD_WIDTH);
+ pc[pmcs_cnt].reg_value = group[0].freq << shift0;
} else if (signal_cnt == 2) {
shift0 = PFM_CELL_BASE_WORD_UNIT_FIELD_BIT +
- ((PFM_CELL_MAX_WORD_NUMBER - group[0].word) * PFM_CELL_WORD_UNIT_FIELD_WIDTH);
+ ((PFM_CELL_MAX_WORD_NUMBER - group[0].word) *
+ PFM_CELL_WORD_UNIT_FIELD_WIDTH);
shift1 = PFM_CELL_BASE_WORD_UNIT_FIELD_BIT +
- ((PFM_CELL_MAX_WORD_NUMBER - group[1].word) * PFM_CELL_WORD_UNIT_FIELD_WIDTH);
- pc[1].reg_value = (group[0].freq << shift0) | (group[1].freq << shift1);
+ ((PFM_CELL_MAX_WORD_NUMBER - group[1].word) *
+ PFM_CELL_WORD_UNIT_FIELD_WIDTH);
+ pc[pmcs_cnt].reg_value = (group[0].freq << shift0) |
+ (group[1].freq << shift1);
}
+ pc[pmcs_cnt].reg_value |= PFM_CELL_DEFAULT_TRIGGER_EVENT_UNIT;
+ pmcs_cnt++;
+
+ pc[pmcs_cnt].reg_num = REG_TRACE_ADDRESS;
+ pc[pmcs_cnt].reg_value = 0;
+ pmcs_cnt++;
+
+ pc[pmcs_cnt].reg_num = REG_EXT_TRACE_TIMER;
+ pc[pmcs_cnt].reg_value = 0;
+ pmcs_cnt++;
+
+ pc[pmcs_cnt].reg_num = REG_PM_STATUS;
+ pc[pmcs_cnt].reg_value = 0;
+ pmcs_cnt++;
+
+ pc[pmcs_cnt].reg_num = REG_PM_CONTROL;
+ pc[pmcs_cnt].reg_value =
+ (mod_in->control & ~PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_MASK) |
+ get_ppu_count_mode(inp->pfp_dfl_plm);
+ pmcs_cnt++;
+
+ pc[pmcs_cnt].reg_num = REG_PM_INTERVAL;
+ pc[pmcs_cnt].reg_value = mod_in->interval;
+ pmcs_cnt++;
+
+ pc[pmcs_cnt].reg_num = REG_PM_START_STOP;
+ pc[pmcs_cnt].reg_value = mod_in->triggers;
+ pmcs_cnt++;
+
+ pmx_ctrl_bits = 0;
- pc[2].reg_num = REG_TRACE_ADDRESS;
- pc[2].reg_value = 0;
-
- pc[3].reg_num = REG_EXT_TRACE_TIMER;
- pc[3].reg_value = 0;
-
- pc[4].reg_num = REG_PM_STATUS;
- pc[4].reg_value = 0;
-
- pc[5].reg_num = REG_PM_CONTROL;
- pc[5].reg_value = mod_in->control;
-
- pc[6].reg_num = REG_PM_INTERVAL;
- pc[6].reg_value = mod_in->interval;
-
- pc[7].reg_num = REG_PM_START_STOP;
- pc[7].reg_value = mod_in->triggers;
-
- pmcs_cnt = COMMON_REG_NUMS;
-
/* pmX register setting */
for(i = 0; i < event_cnt; i++) {
/* PMX_CONTROL */
- pmx_offset = get_pmx_offset(mod_in->pfp_cell_counters[i].pmX_control_num);
+ pmx_offset = get_pmx_offset(mod_in->pfp_cell_counters[i].pmX_control_num,
+ &pmx_ctrl_bits);
if (pmx_offset == PFMLIB_ERR_INVAL) {
- DPRINT(("pmX already used\n"));
+ DPRINT("pmX already used\n");
return PFMLIB_ERR_INVAL;
}
-
+
+ signal_type = get_signal_type(cell_pe[e[i].event].pme_code);
+ if (signal_type == SIGNAL_TYPE_CYCLES) {
+ pc[pmcs_cnt].reg_value = PM_COUNTER_CTRL_CYLES;
+ pc[pmcs_cnt].reg_num = REG_PM0_CONTROL + pmx_offset;
+ pmcs_cnt++;
+ pc[pmcs_cnt].reg_value = cell_pe[e[i].event].pme_code;
+ pc[pmcs_cnt].reg_num = REG_PM0_EVENT + pmx_offset;
+ pmcs_cnt++;
+ pd[i].reg_num = pmx_offset;
+ pd[i].reg_value = 0;
+ continue;
+ }
+
switch(cell_pe[e[i].event].pme_type) {
case COUNT_TYPE_BOTH_TYPE:
case COUNT_TYPE_CUMULATIVE_LEN:
@@ -325,14 +494,12 @@ pfm_cell_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_cell_input_param_t
return PFMLIB_ERR_INVAL;
}
- signal_type = get_signal_type(cell_pe[e[i].event].pme_code);
signal_bit = get_signal_bit(cell_pe[e[i].event].pme_code);
polarity = mod_in->pfp_cell_counters[i].polarity;
input_control = mod_in->pfp_cell_counters[i].input_control;
- if ((41 <= signal_type) && (signal_type <= 56)) {
+ subunit = 0;
+ if (is_spe_signal_group(signal_type)) {
subunit = mod_in->pfp_cell_counters[i].spe_subunit;
- } else {
- subunit = 0;
}
pc[pmcs_cnt].reg_value = ( (signal_bit << (31 - 5))
@@ -342,8 +509,8 @@ pfm_cell_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_cell_input_param_t
| (count_enable << (31 - 9)) );
pc[pmcs_cnt].reg_num = REG_PM0_CONTROL + pmx_offset;
- if (signal_type == group[1].signal_type) {
- pc[pmcs_cnt].reg_value |= PFM_CELL_COUNTER_CONTROL_GROUP1;
+ if (signal_type == group[1].signal_type && subunit == group[1].subunit) {
+ pc[pmcs_cnt].reg_value |= PFM_CELL_COUNTER_CONTROL_GRP1;
}
pmcs_cnt++;
@@ -352,23 +519,25 @@ pfm_cell_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_cell_input_param_t
pc[pmcs_cnt].reg_num = REG_PM0_EVENT + pmx_offset;
/* debug bus word setting */
- if (signal_type == group[0].signal_type) {
+ if (signal_type == group[0].signal_type && subunit == group[0].subunit) {
pc[pmcs_cnt].reg_value = (cell_pe[e[i].event].pme_code |
(group[0].word << 48) | (subunit << 32));
- } else if (signal_type == group[1].signal_type) {
+ } else if (signal_type == group[1].signal_type && subunit == group[1].subunit) {
pc[pmcs_cnt].reg_value = (cell_pe[e[i].event].pme_code |
(group[1].word << 48) | (subunit << 32));
+ } else if ((signal_type == SIGNAL_SPU_TRIGGER)
+ || (signal_type == SIGNAL_SPU_EVENT)) {
+ pc[pmcs_cnt].reg_value = cell_pe[e[i].event].pme_code | (subunit << 32);
} else {
return PFMLIB_ERR_INVAL;
}
pmcs_cnt++;
- }
- /* pmds setting */
- for(i = 0; i < pmx_offset+1; i++) {
- pd[i].reg_num = i;
+
+ /* pmd setting */
+ pd[i].reg_num = pmx_offset;
pd[i].reg_value = 0;
}
-
+
outp->pfp_pmc_count = pmcs_cnt;
outp->pfp_pmd_count = event_cnt;
@@ -379,18 +548,34 @@ static int
pfm_cell_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_output_param_t *outp, void *model_out)
{
pfmlib_cell_input_param_t *mod_in = (pfmlib_cell_input_param_t *)model_in;
+ pfmlib_cell_input_param_t default_model_in;
+ int i;
- if (inp->pfp_dfl_plm & (PFM_PLM1|PFM_PLM2)) {
- DPRINT(("invalid plm=%x\n", inp->pfp_dfl_plm));
- return PFMLIB_ERR_INVAL;
+ if (model_in) {
+ mod_in = (pfmlib_cell_input_param_t *)model_in;
+ } else {
+ mod_in = &default_model_in;
+ mod_in->control = 0x80000000;
+ mod_in->interval = 0;
+ mod_in->triggers = 0;
+ for (i = 0; i < PMU_CELL_NUM_COUNTERS; i++) {
+ mod_in->pfp_cell_counters[i].pmX_control_num = 0;
+ mod_in->pfp_cell_counters[i].spe_subunit = 0;
+ mod_in->pfp_cell_counters[i].polarity = 1;
+ mod_in->pfp_cell_counters[i].input_control = 0;
+ mod_in->pfp_cell_counters[i].cnt_mask = 0;
+ mod_in->pfp_cell_counters[i].flags = 0;
+ }
}
+
return pfm_cell_dispatch_counters(inp, mod_in, outp);
}
static int
pfm_cell_get_event_code(unsigned int i, unsigned int cnt, int *code)
{
- if (cnt != PFMLIB_CNT_FIRST && cnt > 2) {
+// if (cnt != PFMLIB_CNT_FIRST && cnt > 2) {
+ if (cnt != PFMLIB_CNT_FIRST && cnt > cell_support.num_cnt) {
return PFMLIB_ERR_INVAL;
}
@@ -465,6 +650,28 @@ pfm_cell_get_event_desc(unsigned int ev, char **str)
return PFMLIB_SUCCESS;
}
+static int
+pfm_cell_get_cycle_event(pfmlib_event_t *e)
+{
+ int i;
+
+ for (i = 0; i < PME_CELL_EVENT_COUNT; i++) {
+ if (!strcmp(cell_pe[i].pme_name, "CYCLES")) {
+ e->event = i;
+ return PFMLIB_SUCCESS;
+ }
+ }
+ return PFMLIB_ERR_NOTFOUND;
+}
+
+int pfm_cell_spe_event(unsigned int event_index)
+{
+ if (event_index >= PME_CELL_EVENT_COUNT)
+ return 0;
+
+ return is_spe_signal_group(get_signal_type(cell_pe[event_index].pme_code));
+}
+
pfm_pmu_support_t cell_support={
.pmu_name = "CELL",
.pmu_type = PFMLIB_CELL_PMU,
@@ -480,5 +687,6 @@ pfm_pmu_support_t cell_support={
.get_impl_pmcs = pfm_cell_get_impl_pmcs,
.get_impl_pmds = pfm_cell_get_impl_pmds,
.get_impl_counters = pfm_cell_get_impl_counters,
- .get_event_desc = pfm_cell_get_event_desc
+ .get_event_desc = pfm_cell_get_event_desc,
+ .get_cycle_event = pfm_cell_get_cycle_event
};
diff --git a/src/libpfm-3.y/lib/pfmlib_cell_priv.h b/src/libpfm-3.y/lib/pfmlib_cell_priv.h
index 2e062e51a05b486f80b3c4f01dd5547474fb4542..c479aec08bff5a2d50ac18ae5a39d0b8861335ba 100644
--- a/src/libpfm-3.y/lib/pfmlib_cell_priv.h
+++ b/src/libpfm-3.y/lib/pfmlib_cell_priv.h
@@ -65,6 +65,9 @@ typedef struct {
#define REG_PM_START_STOP 0x0017
#define NONE_SIGNAL 0x0000
+#define SIGNAL_SPU 41
+#define SIGNAL_SPU_TRIGGER 42
+#define SIGNAL_SPU_EVENT 43
#define COUNT_TYPE_BOTH_TYPE 1
#define COUNT_TYPE_CUMULATIVE_LEN 2
diff --git a/src/libpfm-3.y/lib/pfmlib_common.c b/src/libpfm-3.y/lib/pfmlib_common.c
index f8224bb8f7c5139e0c383c8b831eb1aca0f43efb..e17b81e0d13524a4b70963fbb80445798aa9a984 100644
--- a/src/libpfm-3.y/lib/pfmlib_common.c
+++ b/src/libpfm-3.y/lib/pfmlib_common.c
@@ -21,7 +21,9 @@
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
+#ifndef _GNU_SOURCE
#define _GNU_SOURCE /* for getline */
+#endif
#include <sys/types.h>
#include <ctype.h>
#include <string.h>
@@ -48,6 +50,9 @@ static pfm_pmu_support_t *supported_pmus[]=
&amd64_support,
&pentium4_support,
&core_support,
+ &intel_atom_support,
+ &intel_nhm_support,
+ &intel_wsm_support,
&gen_ia32_support, /* must always be last for x86-64 */
#endif
@@ -60,6 +65,9 @@ static pfm_pmu_support_t *supported_pmus[]=
&amd64_support,
&pentium4_support,
&core_support,
+ &intel_atom_support,
+ &intel_nhm_support,
+ &intel_wsm_support,
&gen_ia32_support, /* must always be last for i386 */
#endif
@@ -67,6 +75,10 @@ static pfm_pmu_support_t *supported_pmus[]=
&generic_mips64_support,
#endif
+#ifdef CONFIG_PFMLIB_ARCH_SICORTEX
+ &sicortex_support,
+#endif
+
#ifdef CONFIG_PFMLIB_ARCH_POWERPC
&gen_powerpc_support,
#endif
@@ -89,38 +101,105 @@ static pfm_pmu_support_t *supported_pmus[]=
* contains runtime configuration options for the library.
* mostly for debug purposes.
*/
-pfm_config_t pfm_config;
+pfm_config_t pfm_config = {
+ .current = NULL
+};
+
+int forced_pmu = PFMLIB_NO_PMU;
+
+/*
+ * check environment variables for:
+ * LIBPFM_VERBOSE : enable verbose output (must be 1)
+ * LIBPFM_DEBUG : enable debug output (must be 1)
+ */
+static void
+pfm_check_debug_env(void)
+{
+ char *str;
+
+ libpfm_fp = stderr;
+
+ str = getenv("LIBPFM_VERBOSE");
+ if (str && *str >= '0' && *str <= '9') {
+ pfm_config.options.pfm_verbose = *str - '0';
+ pfm_config.options_env_set = 1;
+ }
+
+ str = getenv("LIBPFM_DEBUG");
+ if (str && *str >= '0' && *str <= '9') {
+ pfm_config.options.pfm_debug = *str - '0';
+ pfm_config.options_env_set = 1;
+ }
+
+ str = getenv("LIBPFM_DEBUG_STDOUT");
+ if (str)
+ libpfm_fp = stdout;
+
+ str = getenv("LIBPFM_FORCE_PMU");
+ if (str)
+ forced_pmu = atoi(str);
+}
int
pfm_initialize(void)
{
pfm_pmu_support_t **p = supported_pmus;
+ int ret;
+
+ pfm_check_debug_env();
+ /*
+ * syscall mapping, no failure on error
+ */
+ pfm_init_syscalls();
while(*p) {
- if ((*p)->pmu_detect() == PFMLIB_SUCCESS)
+ DPRINT("trying %s\n", (*p)->pmu_name);
+ /*
+ * check for forced_pmu
+ * pmu_type can never be zero
+ */
+ if ((*p)->pmu_type == forced_pmu) {
+ __pfm_vbprintf("PMU forced to %s\n", (*p)->pmu_name);
+ goto found;
+ }
+
+ if (forced_pmu == PFMLIB_NO_PMU && (*p)->pmu_detect() == PFMLIB_SUCCESS)
goto found;
p++;
}
return PFMLIB_ERR_NOTSUPP;
found:
+ DPRINT("found %s\n", (*p)->pmu_name);
/*
* run a few sanity checks
*/
if ((*p)->pmc_count >= PFMLIB_MAX_PMCS)
return PFMLIB_ERR_NOTSUPP;
+
if ((*p)->pmd_count >= PFMLIB_MAX_PMDS)
return PFMLIB_ERR_NOTSUPP;
+ if ((*p)->pmu_init) {
+ ret = (*p)->pmu_init();
+ if (ret != PFMLIB_SUCCESS)
+ return ret;
+ }
+
pfm_current = *p;
+
return PFMLIB_SUCCESS;
}
int
pfm_set_options(pfmlib_options_t *opt)
{
- if (opt == NULL) return PFMLIB_ERR_INVAL;
-
- pfm_config.options = *opt;
+ if (opt == NULL)
+ return PFMLIB_ERR_INVAL;
+ /*
+ * environment variables override program presets
+ */
+ if (pfm_config.options_env_set == 0)
+ pfm_config.options = *opt;
return PFMLIB_SUCCESS;
}
@@ -256,6 +335,8 @@ pfm_find_event_byname(const char *n, unsigned int *idx)
*/
for(i=0; i < pfm_current->pme_count; i++) {
e = pfm_current->get_event_name(i);
+ if (!e)
+ continue;
if (!strncasecmp(e, n, len)
&& len == strlen(e))
goto found;
@@ -358,13 +439,21 @@ pfm_do_find_event_mask(unsigned int ev, const char *str, unsigned int *mask_idx)
unsigned int i, c, num_masks = 0;
unsigned long mask_val = -1;
char *endptr = NULL;
+ char *mask_name;
+
+ /* empty mask name */
+ if (*str == '\0')
+ return PFMLIB_ERR_UMASK;
num_masks = pfm_num_masks(ev);
for (i = 0; i < num_masks; i++) {
- if (!strcasecmp(pfm_current->get_event_mask_name(ev, i), str)) {
- *mask_idx = i;
- return PFMLIB_SUCCESS;
- }
+ mask_name = pfm_current->get_event_mask_name(ev, i);
+ if (!mask_name)
+ continue;
+ if (strcasecmp(mask_name, str))
+ continue;
+ *mask_idx = i;
+ return PFMLIB_SUCCESS;
}
/* don't give up yet; check for a exact numerical value */
mask_val = strtoul(str, &endptr, 0);
@@ -416,6 +505,10 @@ pfm_add_numeric_masks(pfmlib_event_t *e, const char *str)
char *endptr = NULL;
int ret = PFMLIB_ERR_UMASK;
+ /* empty mask name */
+ if (*str == '\0')
+ return PFMLIB_ERR_UMASK;
+
num_masks = pfm_num_masks(e->event);
/*
@@ -471,17 +564,32 @@ int
pfm_get_event_name(unsigned int i, char *name, size_t maxlen)
{
size_t l, j;
+ char *str;
- if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT;
+ if (PFMLIB_INITIALIZED() == 0)
+ return PFMLIB_ERR_NOINIT;
- if (i >= pfm_current->pme_count || name == NULL || maxlen < 1) return PFMLIB_ERR_INVAL;
+ if (i >= pfm_current->pme_count || name == NULL || maxlen < 1)
+ return PFMLIB_ERR_INVAL;
- strncpy(name, pfm_current->get_event_name(i), maxlen-1);
+ str = pfm_current->get_event_name(i);
+ if (!str)
+ return PFMLIB_ERR_BADHOST;
+ l = strlen(str);
+
+ /*
+ * we fail if buffer is too small, simply because otherwise we
+ * get partial names which are useless for subsequent calls
+ * users mus invoke pfm_get_event_name_max_len() to correctly size
+ * the buffer for this call
+ */
+ if ((maxlen-1) < l)
+ return PFMLIB_ERR_INVAL;
- name[maxlen-1] = '\0';
- l = strlen(name);
for(j=0; j < l; j++)
- name[j] = (char)toupper(name[j]);
+ name[j] = (char)toupper(str[j]);
+
+ name[l] = '\0';
return PFMLIB_SUCCESS;
}
@@ -522,7 +630,7 @@ pfm_get_event_counters(unsigned int i, pfmlib_regmask_t *counters)
int
pfm_get_event_mask_name(unsigned int ev, unsigned int mask, char *name, size_t maxlen)
{
- char *n;
+ char *str;
unsigned int num;
size_t l, j;
@@ -539,15 +647,14 @@ pfm_get_event_mask_name(unsigned int ev, unsigned int mask, char *name, size_t m
if (mask >= num)
return PFMLIB_ERR_INVAL;
- n = pfm_current->get_event_mask_name(ev, mask);
- if (n == NULL)
- return PFMLIB_ERR_INVAL;
-
- l = strlen(n);
+ str = pfm_current->get_event_mask_name(ev, mask);
+ if (!str)
+ return PFMLIB_ERR_BADHOST;
+ l = strlen(str);
if (l >= (maxlen-1))
return PFMLIB_ERR_FULL;
- strcpy(name, n);
+ strcpy(name, str);
/*
* present nice uniform names
@@ -611,7 +718,9 @@ pfm_check_unavail_pmcs(pfmlib_regmask_t *pmcs)
* registers. In other words, invalid registers are ignored
*/
int
-pfm_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_output_param_t *outp, void *model_out)
+pfm_dispatch_events(
+ pfmlib_input_param_t *inp, void *model_in,
+ pfmlib_output_param_t *outp, void *model_out)
{
unsigned count;
unsigned int i;
@@ -620,21 +729,23 @@ pfm_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_output_par
if (PFMLIB_INITIALIZED() == 0)
return PFMLIB_ERR_NOINIT;
- if (inp == NULL || outp == NULL)
+ /* at least one input and one output set must exist */
+ if (!inp && !model_in)
return PFMLIB_ERR_INVAL;
-
- /*
- * the default priv level must be set to something
- */
- if (inp->pfp_dfl_plm == 0)
+ if (!outp && !model_out)
return PFMLIB_ERR_INVAL;
- if (inp->pfp_event_count >= PFMLIB_MAX_PMCS)
+ if (!inp)
+ count = 0;
+ else if (inp->pfp_dfl_plm == 0)
+ /* the default priv level must be set to something */
return PFMLIB_ERR_INVAL;
-
- count = inp->pfp_event_count;
- if (count > pfm_current->num_cnt)
+ else if (inp->pfp_event_count >= PFMLIB_MAX_PMCS)
+ return PFMLIB_ERR_INVAL;
+ else if (inp->pfp_event_count > pfm_current->num_cnt)
return PFMLIB_ERR_NOASSIGN;
+ else
+ count = inp->pfp_event_count;
/*
* check that event and unit masks descriptors are correct
@@ -644,8 +755,10 @@ pfm_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_output_par
if (ret != PFMLIB_SUCCESS)
return ret;
}
+
/* reset output data structure */
- memset(outp, 0, sizeof(*outp));
+ if (outp)
+ memset(outp, 0, sizeof(*outp));
return pfm_current->dispatch_events(inp, model_in, outp, model_out);
}
@@ -791,6 +904,7 @@ pfm_get_max_event_name_len(size_t *len)
{
unsigned int i, j, num_masks;
size_t max = 0, l;
+ char *str;
if (PFMLIB_INITIALIZED() == 0)
return PFMLIB_ERR_NOINIT;
@@ -798,7 +912,10 @@ pfm_get_max_event_name_len(size_t *len)
return PFMLIB_ERR_INVAL;
for(i=0; i < pfm_current->pme_count; i++) {
- l = strlen(pfm_current->get_event_name(i));
+ str = pfm_current->get_event_name(i);
+ if (!str)
+ continue;
+ l = strlen(str);
if (l > max) max = l;
num_masks = pfm_num_masks(i);
@@ -808,7 +925,10 @@ pfm_get_max_event_name_len(size_t *len)
* which is inserted as the unit mask separator
*/
for (j = 0; j < num_masks; j++) {
- l += 1 + strlen(pfm_current->get_event_mask_name(i, j));
+ str = pfm_current->get_event_mask_name(i, j);
+ if (!str)
+ continue;
+ l += 1 + strlen(str);
}
if (l > max) max = l;
}
@@ -905,7 +1025,7 @@ pfm_get_event_mask_code(unsigned int event_idx, unsigned int mask_idx, unsigned
int
pfm_get_full_event_name(pfmlib_event_t *e, char *name, size_t maxlen)
{
- char *n;
+ char *str;
size_t l, j;
int ret;
@@ -926,21 +1046,25 @@ pfm_get_full_event_name(pfmlib_event_t *e, char *name, size_t maxlen)
*/
*name = '\0';
- n = pfm_current->get_event_name(e->event);
- l = strlen(n);
+ str = pfm_current->get_event_name(e->event);
+ if (!str)
+ return PFMLIB_ERR_BADHOST;
+ l = strlen(str);
if (l > (maxlen-1))
return PFMLIB_ERR_FULL;
- strcpy(name, n);
+ strcpy(name, str);
maxlen -= l + 1;
for(j=0; j < e->num_masks; j++) {
- n = pfm_current->get_event_mask_name(e->event, e->unit_masks[j]);
- l = strlen(n);
+ str = pfm_current->get_event_mask_name(e->event, e->unit_masks[j]);
+ if (!str)
+ continue;
+ l = strlen(str);
if (l > (maxlen-1))
return PFMLIB_ERR_FULL;
strcat(name, ":");
- strcat(name, n);
+ strcat(name, str);
maxlen -= l + 1;
}
/*
@@ -992,26 +1116,41 @@ pfm_find_full_event(const char *v, pfmlib_event_t *e)
*/
p = strchr(str, ':');
+ /* If no unit masks available and none specified, we're done */
+
+ if ((j == 0) && (p == NULL)) {
+ free(str);
+ return PFMLIB_SUCCESS;
+ }
+
+ ret = PFMLIB_ERR_UMASK;
/*
* error if:
- * - event has unit masks and none is passed
* - event has no unit mask and at least one is passed
*/
- if ((!p && j) || (p && !j)) {
- ret = PFMLIB_ERR_UMASK;
+ if (p && !j)
goto error;
- }
/*
- * if no unit mask, then we are done
+ * error if:
+ * - event has unit masks, no default unit mask, and none is passed
*/
- if (!j) {
- free(str);
- return PFMLIB_SUCCESS;
+ if (j && !p) {
+ if (pfm_current->has_umask_default
+ && pfm_current->has_umask_default(e->event)) {
+ free(str);
+ return PFMLIB_SUCCESS;
+ }
+ goto error;
}
/* skip : */
p++;
+ /*
+ * separator is passed but there is nothing behind it
+ */
+ if (!*p)
+ goto error;
/* parse unit masks */
for( q = p; q ; p = q) {
diff --git a/src/libpfm-3.y/lib/pfmlib_core.c b/src/libpfm-3.y/lib/pfmlib_core.c
index 8e28d624eea1cc831eea2d5b5c62aefb948b7243..bb13ce698db1c4163292a7c61658fb898926f72c 100644
--- a/src/libpfm-3.y/lib/pfmlib_core.c
+++ b/src/libpfm-3.y/lib/pfmlib_core.c
@@ -78,12 +78,11 @@
#define CORE_CTR_BASE 0xc1
#define FIXED_CTR_BASE 0x309
-#define MAX_COUNTERS 4 /* highest implemented counter */
-
#define PFMLIB_CORE_ALL_FLAGS \
(PFM_CORE_SEL_INV|PFM_CORE_SEL_EDGE)
static pfmlib_regmask_t core_impl_pmcs, core_impl_pmds;
+static int highest_counter;
static int
pfm_core_detect(void)
@@ -109,21 +108,25 @@ pfm_core_detect(void)
if (ret == -1)
return PFMLIB_ERR_NOTSUPP;
- model = atoi(buffer);
- /*
- * XXX: is there a way to identify a Core-based processor?
- * So for now, look for Core 2 only
- */
if (family != 6)
return PFMLIB_ERR_NOTSUPP;
+ model = atoi(buffer);
switch(model) {
case 15: /* Merom */
case 23: /* Penryn */
+ case 29: /* Dunnington */
break;
default:
return PFMLIB_ERR_NOTSUPP;
}
+ return PFMLIB_SUCCESS;
+}
+
+static int
+pfm_core_init(void)
+{
+ int i;
pfm_regmask_set(&core_impl_pmcs, 0);
pfm_regmask_set(&core_impl_pmcs, 1);
@@ -136,6 +139,13 @@ pfm_core_detect(void)
pfm_regmask_set(&core_impl_pmds, 17);
pfm_regmask_set(&core_impl_pmds, 18);
+ /* lbr */
+ pfm_regmask_set(&core_impl_pmds, 19);
+ for(i=0; i < 8; i++)
+ pfm_regmask_set(&core_impl_pmds, i);
+
+ highest_counter = 18;
+
return PFMLIB_SUCCESS;
}
@@ -158,7 +168,7 @@ pfm_core_is_fixed(pfmlib_event_t *e, unsigned int f)
mask = PFMLIB_CORE_FIXED1;
break;
case 2:
- mask = PFMLIB_CORE_FIXED2;
+ mask = PFMLIB_CORE_FIXED2_ONLY;
break;
default:
return 0;
@@ -187,7 +197,7 @@ pfm_core_is_fixed(pfmlib_event_t *e, unsigned int f)
static int
pfm_core_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_core_input_param_t *param, pfmlib_output_param_t *outp)
{
-#define HAS_OPTIONS(x) (cntrs && (cntrs[i].flags || cntrs[i].cnt_mask))
+#define HAS_OPTIONS(x) (cntrs && (cntrs[x].flags || cntrs[x].cnt_mask))
#define is_fixed_pmc(a) (a == 16 || a == 17 || a == 18)
pfmlib_core_counter_t *cntrs;
@@ -198,12 +208,12 @@ pfm_core_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_core_input_param_t
uint64_t val;
unsigned long plm;
unsigned long long fixed_ctr;
- unsigned int npc, npmc0, npmc1;
- unsigned int i, j, n, k, umask, use_pebs = 0, done_pebs;
+ unsigned int npc, npmc0, npmc1, nf2;
+ unsigned int i, j, n, k, ucode, use_pebs = 0, done_pebs;
unsigned int assign_pc[PMU_CORE_NUM_COUNTERS];
unsigned int next_gen, last_gen;
- npc = npmc0 = npmc1 = 0;
+ npc = npmc0 = npmc1 = nf2 = 0;
e = inp->pfp_events;
pc = outp->pfp_pmcs;
@@ -225,50 +235,83 @@ pfm_core_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_core_input_param_t
/*
* error checking
*/
- for(j=0; j < n; j++) {
+ for(i=0; i < n; i++) {
/*
* only supports two priv levels for perf counters
*/
- if (e[j].plm & (PFM_PLM1|PFM_PLM2))
+ if (e[i].plm & (PFM_PLM1|PFM_PLM2))
return PFMLIB_ERR_INVAL;
/*
* check for valid flags
*/
- if (e[j].flags & ~PFMLIB_CORE_ALL_FLAGS)
+ if (cntrs && cntrs[i].flags & ~PFMLIB_CORE_ALL_FLAGS)
return PFMLIB_ERR_INVAL;
- if (core_pe[e[j].event].pme_flags & PFMLIB_CORE_UMASK_NCOMBO
- && e[j].num_masks > 1) {
- DPRINT(("events does not support unit mask combination\n"));
+ if (core_pe[e[i].event].pme_flags & PFMLIB_CORE_UMASK_NCOMBO
+ && e[i].num_masks > 1) {
+ DPRINT("events does not support unit mask combination\n");
return PFMLIB_ERR_NOASSIGN;
}
/*
- * check if PMC0 is available and if only one event is dependent on it
+ * check event-level single register constraint (PMC0, PMC1, FIXED_CTR2)
+ * fail if more than two events requested for the same counter
*/
- if (core_pe[e[j].event].pme_flags & PFMLIB_CORE_PMC0) {
+ if (core_pe[e[i].event].pme_flags & PFMLIB_CORE_PMC0) {
if (++npmc0 > 1) {
- DPRINT(("two events compete for a PMC0\n"));
+ DPRINT("two events compete for a PMC0\n");
return PFMLIB_ERR_NOASSIGN;
}
}
/*
* check if PMC1 is available and if only one event is dependent on it
*/
- if (core_pe[e[j].event].pme_flags & PFMLIB_CORE_PMC1) {
+ if (core_pe[e[i].event].pme_flags & PFMLIB_CORE_PMC1) {
if (++npmc1 > 1) {
- DPRINT(("two events compete for a PMC1\n"));
+ DPRINT("two events compete for a PMC1\n");
return PFMLIB_ERR_NOASSIGN;
}
}
+ /*
+ * UNHALTED_REFERENCE_CYCLES can only be measured on FIXED_CTR2
+ */
+ if (core_pe[e[i].event].pme_flags & PFMLIB_CORE_FIXED2_ONLY) {
+ if (++nf2 > 1) {
+ DPRINT("two events compete for FIXED_CTR2\n");
+ return PFMLIB_ERR_NOASSIGN;
+ }
+ if (HAS_OPTIONS(i)) {
+ DPRINT("fixed counters do not support inversion/counter-mask\n");
+ return PFMLIB_ERR_NOASSIGN;
+ }
+ }
+ /*
+ * unit-mask level constraint checking (PMC0, PMC1, FIXED_CTR2)
+ */
+ for(j=0; j < e[i].num_masks; j++) {
+ unsigned int flags;
+
+ flags = core_pe[e[i].event].pme_umasks[e[i].unit_masks[j]].pme_flags;
+
+ if (flags & PFMLIB_CORE_FIXED2_ONLY) {
+ if (++nf2 > 1) {
+ DPRINT("two events compete for FIXED_CTR2\n");
+ return PFMLIB_ERR_NOASSIGN;
+ }
+ if (HAS_OPTIONS(i)) {
+ DPRINT("fixed counters do not support inversion/counter-mask\n");
+ return PFMLIB_ERR_NOASSIGN;
+ }
+ }
+ }
}
next_gen = 0; /* first generic counter */
last_gen = 1; /* last generic counter */
/*
- * strongest constraint first: works only in IA32_PMC0 or IA32_PMC1
+ * strongest constraint first: works only in IA32_PMC0, IA32_PMC1, FIXED_CTR2
*
* When PEBS is used, we pick the first PEBS event and
* place it into PMC0. Subsequent PEBS events, will go
@@ -281,20 +324,23 @@ pfm_core_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_core_input_param_t
if (pfm_regmask_isset(r_pmcs, 0))
return PFMLIB_ERR_NOASSIGN;
assign_pc[i] = 0;
- next_gen++;
+ next_gen = 1;
done_pebs = 1;
}
if (core_pe[e[i].event].pme_flags & PFMLIB_CORE_PMC1) {
if (pfm_regmask_isset(r_pmcs, 1))
return PFMLIB_ERR_NOASSIGN;
assign_pc[i] = 1;
- next_gen++;
+ if (next_gen == 1)
+ next_gen = 2;
+ else
+ next_gen = 0;
}
}
/*
* next constraint: fixed counters
*
- * We abuse the mapping here fore assign_pc to make it easier
+ * We abuse the mapping here for assign_pc to make it easier
* to provide the correct values for pd[].
* We use:
* - 16 : fixed counter 0 (pmc16, pmd16)
@@ -328,13 +374,16 @@ pfm_core_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_core_input_param_t
for(i=0; i < n; i++) {
if (assign_pc[i] == -1) {
for(; next_gen <= last_gen; next_gen++) {
+DPRINT("i=%d next_gen=%d last=%d isset=%d\n", i, next_gen, last_gen, pfm_regmask_isset(r_pmcs, next_gen));
if (!pfm_regmask_isset(r_pmcs, next_gen))
break;
}
if (next_gen <= last_gen)
assign_pc[i] = next_gen++;
- else
+ else {
+ DPRINT("cannot assign generic counters\n");
return PFMLIB_ERR_NOASSIGN;
+ }
}
}
j = 0;
@@ -398,12 +447,14 @@ pfm_core_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_core_input_param_t
/* if plm is 0, then assume not specified per-event and use default */
plm = e[i].plm ? e[i].plm : inp->pfp_dfl_plm;
- reg.sel_event_select = core_pe[e[i].event].pme_code & 0xff;
+ val = core_pe[e[i].event].pme_code;
- umask = (core_pe[e[i].event].pme_code >> 8) & 0xff;
+ reg.sel_event_select = val & 0xff;
+
+ ucode = (val >> 8) & 0xff;
for(k=0; k < e[i].num_masks; k++) {
- umask |= core_pe[e[i].event].pme_umasks[e[i].unit_masks[k]].pme_ucode;
+ ucode |= core_pe[e[i].event].pme_umasks[e[i].unit_masks[k]].pme_ucode;
}
/*
@@ -412,27 +463,46 @@ pfm_core_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_core_input_param_t
* force to SELF if user did not specify anything
*/
if ((core_pe[e[i].event].pme_flags & PFMLIB_CORE_CSPEC)
- && ((umask & (0x3 << 6)) == 0)) {
- umask |= 1 << 6;
+ && ((ucode & (0x3 << 6)) == 0)) {
+ ucode |= 1 << 6;
+ }
+ /*
+ * for events supporting MESI, a value
+ * of 0 for bits 11:8 (0-3 in our umask) means nothing will be
+ * counted. Therefore, we force a default of 0xf (M,E,S,I).
+ */
+ if ((core_pe[e[i].event].pme_flags & PFMLIB_CORE_MESI)
+ && ((ucode & 0xf) == 0)) {
+ ucode |= 0xf;
}
- reg.sel_unit_mask = umask;
+ val |= ucode << 8;
+
+ reg.sel_unit_mask = ucode;
reg.sel_usr = plm & PFM_PLM3 ? 1 : 0;
reg.sel_os = plm & PFM_PLM0 ? 1 : 0;
reg.sel_en = 1; /* force enable bit to 1 */
reg.sel_int = 1; /* force APIC int to 1 */
+ reg.sel_cnt_mask = val >>24;
+ reg.sel_inv = val >> 23;
+ reg.sel_edge = val >> 18;
+
if (cntrs) {
- /*
- * counter mask is 8-bit wide, do not silently
- * wrap-around
- */
- if (cntrs[i].cnt_mask > 255)
- return PFMLIB_ERR_INVAL;
-
- reg.sel_cnt_mask = cntrs[i].cnt_mask;
- reg.sel_edge = cntrs[i].flags & PFM_CORE_SEL_EDGE ? 1 : 0;
- reg.sel_inv = cntrs[i].flags & PFM_CORE_SEL_INV ? 1 : 0;
+ if (!reg.sel_cnt_mask) {
+ /*
+ * counter mask is 8-bit wide, do not silently
+ * wrap-around
+ */
+ if (cntrs[i].cnt_mask > 255)
+ return PFMLIB_ERR_INVAL;
+ reg.sel_cnt_mask = cntrs[i].cnt_mask;
+ }
+
+ if (!reg.sel_edge)
+ reg.sel_edge = cntrs[i].flags & PFM_CORE_SEL_EDGE ? 1 : 0;
+ if (!reg.sel_inv)
+ reg.sel_inv = cntrs[i].flags & PFM_CORE_SEL_INV ? 1 : 0;
}
pc[npc].reg_num = assign_pc[i];
@@ -633,7 +703,7 @@ pfm_core_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_outpu
pfmlib_core_input_param_t *mod_in = (pfmlib_core_input_param_t *)model_in;
if (inp->pfp_dfl_plm & (PFM_PLM1|PFM_PLM2)) {
- DPRINT(("invalid plm=%x\n", inp->pfp_dfl_plm));
+ DPRINT("invalid plm=%x\n", inp->pfp_dfl_plm);
return PFMLIB_ERR_INVAL;
}
return pfm_core_dispatch_counters(inp, mod_in, outp);
@@ -643,7 +713,7 @@ static int
pfm_core_get_event_code(unsigned int i, unsigned int cnt, int *code)
{
if (cnt != PFMLIB_CNT_FIRST
- && (cnt > MAX_COUNTERS ||
+ && (cnt > highest_counter ||
!pfm_regmask_isset(&core_impl_pmds, cnt)))
return PFMLIB_ERR_INVAL;
@@ -668,7 +738,7 @@ pfm_core_get_event_counters(unsigned int j, pfmlib_regmask_t *counters)
has_f0 = 1;
if (core_pe[j].pme_umasks[i].pme_flags & PFMLIB_CORE_FIXED1)
has_f1 = 1;
- if (core_pe[j].pme_umasks[i].pme_flags & PFMLIB_CORE_FIXED2)
+ if (core_pe[j].pme_umasks[i].pme_flags & PFMLIB_CORE_FIXED2_ONLY)
has_f2 = 1;
}
@@ -677,7 +747,7 @@ pfm_core_get_event_counters(unsigned int j, pfmlib_regmask_t *counters)
if (has_f1 == 0)
has_f1 = core_pe[j].pme_flags & PFMLIB_CORE_FIXED1;
if (has_f2 == 0)
- has_f2 = core_pe[j].pme_flags & PFMLIB_CORE_FIXED2;
+ has_f2 = core_pe[j].pme_flags & PFMLIB_CORE_FIXED2_ONLY;
if (has_f0)
pfm_regmask_set(counters, 16);
@@ -686,9 +756,16 @@ pfm_core_get_event_counters(unsigned int j, pfmlib_regmask_t *counters)
if (has_f2)
pfm_regmask_set(counters, 18);
- pfm_regmask_set(counters, 0);
- if ((core_pe[j].pme_flags & PFMLIB_CORE_PMC0) == 0)
+ /* the event on FIXED_CTR2 is exclusive CPU_CLK_UNHALTED:REF */
+ if (!has_f2) {
+ pfm_regmask_set(counters, 0);
pfm_regmask_set(counters, 1);
+
+ if (core_pe[j].pme_flags & PFMLIB_CORE_PMC0)
+ pfm_regmask_clr(counters, 1);
+ if (core_pe[j].pme_flags & PFMLIB_CORE_PMC1)
+ pfm_regmask_clr(counters, 0);
+ }
}
static void
@@ -706,8 +783,11 @@ pfm_core_get_impl_pmds(pfmlib_regmask_t *impl_pmds)
static void
pfm_core_get_impl_counters(pfmlib_regmask_t *impl_counters)
{
- /* all pmds are counters */
- *impl_counters = core_impl_pmds;
+ pfm_regmask_set(impl_counters, 0);
+ pfm_regmask_set(impl_counters, 1);
+ pfm_regmask_set(impl_counters, 16);
+ pfm_regmask_set(impl_counters, 17);
+ pfm_regmask_set(impl_counters, 18);
}
/*
@@ -825,13 +905,14 @@ pfm_pmu_support_t core_support={
.pmu_type = PFMLIB_CORE_PMU,
.pme_count = PME_CORE_EVENT_COUNT,
.pmc_count = 4,
- .pmd_count = 5,
+ .pmd_count = 14,
.num_cnt = 5,
.get_event_code = pfm_core_get_event_code,
.get_event_name = pfm_core_get_event_name,
.get_event_counters = pfm_core_get_event_counters,
.dispatch_events = pfm_core_dispatch_events,
.pmu_detect = pfm_core_detect,
+ .pmu_init = pfm_core_init,
.get_impl_pmcs = pfm_core_get_impl_pmcs,
.get_impl_pmds = pfm_core_get_impl_pmds,
.get_impl_counters = pfm_core_get_impl_counters,
diff --git a/src/libpfm-3.y/lib/pfmlib_core_priv.h b/src/libpfm-3.y/lib/pfmlib_core_priv.h
index 1db471d712f7c908892a5def404131bf12afa8db..d4b581f48e9814626646faa9271573f0390113fb 100644
--- a/src/libpfm-3.y/lib/pfmlib_core_priv.h
+++ b/src/libpfm-3.y/lib/pfmlib_core_priv.h
@@ -46,13 +46,19 @@ typedef struct {
/*
* pme_flags value (event and unit mask)
*/
+
+/* event or unit-mask level constraints */
+#define PFMLIB_CORE_FIXED0 0x02 /* event supported by FIXED_CTR0, can work on generic counters */
+#define PFMLIB_CORE_FIXED1 0x04 /* event supported by FIXED_CTR1, can work on generic counters */
+#define PFMLIB_CORE_FIXED2_ONLY 0x08 /* works only on FIXED_CTR2 */
+
+/* event-level constraints */
#define PFMLIB_CORE_UMASK_NCOMBO 0x01 /* unit mask cannot be combined (default: combination ok) */
-#define PFMLIB_CORE_FIXED0 0x02 /* event prefers FIXED_CTR0 */
-#define PFMLIB_CORE_FIXED1 0x04 /* event prefers FIXED_CTR0 */
-#define PFMLIB_CORE_FIXED2 0x08 /* event prefers FIXED_CTR0 */
-#define PFMLIB_CORE_PMC0 0x10 /* works only on IA32_PMC0 */
-#define PFMLIB_CORE_PEBS 0x20 /* support PEBS (precise event) */
+
#define PFMLIB_CORE_CSPEC 0x40 /* requires a core specification */
+#define PFMLIB_CORE_PEBS 0x20 /* support PEBS (precise event) */
+#define PFMLIB_CORE_PMC0 0x10 /* works only on IA32_PMC0 */
#define PFMLIB_CORE_PMC1 0x80 /* works only on IA32_PMC1 */
+#define PFMLIB_CORE_MESI 0x100 /* requires MESI */
#endif /* __PFMLIB_CORE_PRIV_H__ */
diff --git a/src/libpfm-3.y/lib/pfmlib_crayx2.c b/src/libpfm-3.y/lib/pfmlib_crayx2.c
index 8a048c2d371a5e5c489401caac7fc429124af969..d8e4c9d6d75414f8560230e51e5a7b8f33aa5cdd 100644
--- a/src/libpfm-3.y/lib/pfmlib_crayx2.c
+++ b/src/libpfm-3.y/lib/pfmlib_crayx2.c
@@ -43,14 +43,14 @@ static int
pfm_crayx2_get_event_code (unsigned int i, unsigned int cnt, int *code)
{
if (cnt != PFMLIB_CNT_FIRST && cnt > crayx2_support.num_cnt) {
- DPRINT (("return: count %d exceeded #counters\n", cnt));
+ DPRINT ("return: count %d exceeded #counters\n", cnt);
return PFMLIB_ERR_INVAL;
} else if (i >= crayx2_support.pme_count) {
- DPRINT (("return: event index %d exceeded #events\n", i));
+ DPRINT ("return: event index %d exceeded #events\n", i);
return PFMLIB_ERR_INVAL;
}
*code = crayx2_pe[i].pme_code;
- DPRINT (("return: event code is %#x\n", *code));
+ DPRINT ("return: event code is %#x\n", *code);
return PFMLIB_SUCCESS;
}
@@ -59,10 +59,10 @@ static char *
pfm_crayx2_get_event_name (unsigned int i)
{
if (i >= crayx2_support.pme_count) {
- DPRINT (("return: event index %d exceeded #events\n", i));
+ DPRINT ("return: event index %d exceeded #events\n", i);
return NULL;
}
- DPRINT (("return: event name '%s'\n", crayx2_pe[i].pme_name));
+ DPRINT ("return: event name '%s'\n", crayx2_pe[i].pme_name);
return (char *) crayx2_pe[i].pme_name;
}
@@ -74,7 +74,7 @@ pfm_crayx2_get_event_counters (unsigned int j, pfmlib_regmask_t *counters)
memset (counters, 0, sizeof (*counters));
- DPRINT (("event counters for %d counters\n", PMU_CRAYX2_NUM_COUNTERS));
+ DPRINT ("event counters for %d counters\n", PMU_CRAYX2_NUM_COUNTERS);
for (i=0; i<PMU_CRAYX2_NUM_COUNTERS; i++) {
pfm_regmask_set (counters, i);
}
@@ -82,25 +82,25 @@ pfm_crayx2_get_event_counters (unsigned int j, pfmlib_regmask_t *counters)
}
static int
-pfm_crayx2_chip_use (uint64_t used[ ], unsigned int n)
+pfm_crayx2_chip_use (uint32_t used[ ], unsigned int n)
{
int i, u = 0;
for (i=0; i<n; i++) {
u += pfmlib_popcnt (used[i]);
}
- DPRINT (("number of counters used on chip %d\n", u));
+ DPRINT ("number of counters used on chip %d\n", u);
return u;
}
static counter_use_t
-pfm_crayx2_counter_use (unsigned int ctr, unsigned int event, uint64_t *used, uint64_t *evmsk)
+pfm_crayx2_counter_use (unsigned int ctr, unsigned int event, uint32_t *used, uint64_t *evmsk)
{
counter_use_t ret = CTR_OK;
if (*used & (1 << ctr)) {
- if (event == PFM_EVENT_GET (*evmsk, event)) {
+ if (event == PFM_EVENT_GET (*evmsk, ctr)) {
ret = CTR_REDUNDANT;
} else {
ret = CTR_CONFLICT;
@@ -116,12 +116,12 @@ static int
pfm_crayx2_dispatch_events (pfmlib_input_param_t *inp, void *model_in, pfmlib_output_param_t *outp, void *model_out)
{
unsigned int i, npmcs = 0, npmds = 0, base_pmc = 0;
- uint64_t Pused[PME_CRAYX2_CPU_CHIPS];
- uint64_t Cused[PME_CRAYX2_CACHE_CHIPS];
- uint64_t Mused[PME_CRAYX2_MEMORY_CHIPS];
+ uint32_t Pused[PME_CRAYX2_CPU_CHIPS];
+ uint32_t Cused[PME_CRAYX2_CACHE_CHIPS];
+ uint32_t Mused[PME_CRAYX2_MEMORY_CHIPS];
uint64_t Pevents = 0, Cevents = 0, Mevents = 0;
- DPRINT (("dispatching event info to the PMCs and PMDs\n"));
+ DPRINT ("dispatching event info to the PMCs and PMDs\n");
/* NOTES:
* Multiplexing is not supported on X2.
@@ -131,11 +131,11 @@ pfm_crayx2_dispatch_events (pfmlib_input_param_t *inp, void *model_in, pfmlib_ou
if (PFMLIB_DEBUG ( )) {
int j;
- DPRINT (("input: pfp_event_count %d pfp_dfl_plm %#x pfp_flags %#x\n", inp->pfp_event_count, inp->pfp_dfl_plm, inp->pfp_flags));
+ DPRINT ("input: pfp_event_count %d pfp_dfl_plm %#x pfp_flags %#x\n", inp->pfp_event_count, inp->pfp_dfl_plm, inp->pfp_flags);
for (i=0; i<inp->pfp_event_count; i++) {
- DPRINT ((" %3d: event %3d plm %#3x flags %#8lx num_masks %d\n", i, inp->pfp_events[i].event, inp->pfp_events[i].plm, inp->pfp_events[i].flags, inp->pfp_events[i].num_masks));
+ DPRINT (" %3d: event %3d plm %#3x flags %#8lx num_masks %d\n", i, inp->pfp_events[i].event, inp->pfp_events[i].plm, inp->pfp_events[i].flags, inp->pfp_events[i].num_masks);
for (j=0; j<inp->pfp_events[i].num_masks; j++) {
- DPRINT ((" unit-mask-%2d: %d\n", j, inp->pfp_events[i].unit_masks[j]));
+ DPRINT (" unit-mask-%2d: %d\n", j, inp->pfp_events[i].unit_masks[j]);
}
}
}
@@ -143,10 +143,10 @@ pfm_crayx2_dispatch_events (pfmlib_input_param_t *inp, void *model_in, pfmlib_ou
/* Better have at least one event specified and not exceed limit.
*/
if (inp->pfp_event_count == 0) {
- DPRINT (("return: event count is 0\n"));
+ DPRINT ("return: event count is 0\n");
return PFMLIB_ERR_INVAL;
} else if (inp->pfp_event_count > PMU_CRAYX2_NUM_COUNTERS) {
- DPRINT (("return: event count exceeds max %d\n", PMU_CRAYX2_NUM_COUNTERS));
+ DPRINT ("return: event count exceeds max %d\n", PMU_CRAYX2_NUM_COUNTERS);
return PFMLIB_ERR_TOOMANY;
}
@@ -171,19 +171,19 @@ pfm_crayx2_dispatch_events (pfmlib_input_param_t *inp, void *model_in, pfmlib_ou
ev = crayx2_pe[code].pme_event;
chipno = crayx2_pe[code].pme_chipno;
- DPRINT (("%3d: code %3d chip %1d ctr %2d ev %1d chipno %2d\n", code, i, chip, ctr, ev, chipno));
+ DPRINT ("%3d: code %3d chip %1d ctr %2d ev %1d chipno %2d\n", code, i, chip, ctr, ev, chipno);
/* These priviledge levels are not recognized.
*/
if (inp->pfp_events[i].plm != 0) {
- DPRINT (("%3d: priviledge level %#x per event not allowed\n", i, inp->pfp_events[i].plm));
+ DPRINT ("%3d: priviledge level %#x per event not allowed\n", i, inp->pfp_events[i].plm);
return PFMLIB_ERR_INVAL;
}
/* No masks exist.
*/
if (inp->pfp_events[i].num_masks > 0) {
- DPRINT (("too many masks for event\n"));
+ DPRINT ("too many masks for event\n");
return PFMLIB_ERR_TOOMANY;
}
@@ -198,21 +198,21 @@ pfm_crayx2_dispatch_events (pfmlib_input_param_t *inp, void *model_in, pfmlib_ou
} else if (chip == PME_CRAYX2_CHIP_MEMORY) {
ret = pfm_crayx2_counter_use (ctr, ev, &Mused[chipno], &Mevents);
} else {
- DPRINT (("return: invalid chip\n"));
+ DPRINT ("return: invalid chip\n");
return PFMLIB_ERR_INVAL;
}
/* Each chip's counter can only count one event.
*/
if (ret == CTR_CONFLICT) {
- DPRINT (("return: ctr conflict\n"));
+ DPRINT ("return: ctr conflict\n");
return PFMLIB_ERR_EVTINCOMP;
} else if (ret == CTR_REDUNDANT) {
#if (CRAYX2_NO_REDUNDANT != 0)
- DPRINT (("return: ctr redundant\n"));
+ DPRINT ("return: ctr redundant\n");
return PFMLIB_ERR_EVTMANY;
#else
- DPRINT (("warning: ctr redundant\n"));
+ DPRINT ("warning: ctr redundant\n");
#endif /* CRAYX2_NO_REDUNDANT */
}
@@ -227,12 +227,12 @@ pfm_crayx2_dispatch_events (pfmlib_input_param_t *inp, void *model_in, pfmlib_ou
outp->pfp_pmd_count = npmds;
if (PFMLIB_DEBUG ( )) {
- DPRINT (("P event mask %#16lx\n", Pevents));
- DPRINT (("C event mask %#16lx\n", Cevents));
- DPRINT (("M event mask %#16lx\n", Mevents));
- DPRINT (("PMDs: pmd_count %d\n", outp->pfp_pmd_count));
+ DPRINT ("P event mask %#16lx\n", Pevents);
+ DPRINT ("C event mask %#16lx\n", Cevents);
+ DPRINT ("M event mask %#16lx\n", Mevents);
+ DPRINT ("PMDs: pmd_count %d\n", outp->pfp_pmd_count);
for (i=0; i<outp->pfp_pmd_count; i++) {
- DPRINT ((" %3d: reg_value %3lld reg_num %3d reg_addr %#16llx\n", i, outp->pfp_pmds[i].reg_value, outp->pfp_pmds[i].reg_num, outp->pfp_pmds[i].reg_addr));
+ DPRINT (" %3d: reg_value %3lld reg_num %3d reg_addr %#16llx\n", i, outp->pfp_pmds[i].reg_value, outp->pfp_pmds[i].reg_num, outp->pfp_pmds[i].reg_addr);
}
}
@@ -240,7 +240,7 @@ pfm_crayx2_dispatch_events (pfmlib_input_param_t *inp, void *model_in, pfmlib_ou
* some counting.
*/
if (pfm_crayx2_chip_use (Pused, PME_CRAYX2_CPU_CHIPS) > 0) {
- uint64_t Pctrl = (PFM_CPU_START | PFM_CPU_CLEAR_ALL);
+ uint64_t Pctrl = PFM_CPU_START;
uint64_t Pen = PFM_ENABLE_RW;
if (inp->pfp_dfl_plm & (PFM_PLM0 | PFM_PLM1)) {
@@ -276,7 +276,7 @@ pfm_crayx2_dispatch_events (pfmlib_input_param_t *inp, void *model_in, pfmlib_ou
npmcs++;
}
if (pfm_crayx2_chip_use (Cused, PME_CRAYX2_CACHE_CHIPS) > 0) {
- uint64_t Cctrl = (PFM_CACHE_START | PFM_CACHE_CLEAR_ALL);
+ uint64_t Cctrl = PFM_CACHE_START;
uint64_t Cen = PFM_ENABLE_RW; /* domains N/A */
/* Second of three Cache PMC registers.
@@ -302,7 +302,7 @@ pfm_crayx2_dispatch_events (pfmlib_input_param_t *inp, void *model_in, pfmlib_ou
npmcs++;
}
if (pfm_crayx2_chip_use (Mused, PME_CRAYX2_MEMORY_CHIPS) > 0) {
- uint64_t Mctrl = (PFM_MEM_START | PFM_MEM_CLEAR_ALL);
+ uint64_t Mctrl = PFM_MEM_START;
uint64_t Men = PFM_ENABLE_RW; /* domains N/A */
/* Third of three Memory PMC registers.
@@ -330,9 +330,9 @@ pfm_crayx2_dispatch_events (pfmlib_input_param_t *inp, void *model_in, pfmlib_ou
outp->pfp_pmc_count = npmcs;
if (PFMLIB_DEBUG ( )) {
- DPRINT (("PMCs: pmc_count %d\n", outp->pfp_pmc_count));
+ DPRINT ("PMCs: pmc_count %d\n", outp->pfp_pmc_count);
for (i=0; i<outp->pfp_pmc_count; i++) {
- DPRINT ((" %3d: reg_value %#16llx reg_num %3d reg_addr %#16llx\n", i, outp->pfp_pmcs[i].reg_value, outp->pfp_pmcs[i].reg_num, outp->pfp_pmcs[i].reg_addr));
+ DPRINT (" %3d: reg_value %#16llx reg_num %3d reg_addr %#16llx\n", i, outp->pfp_pmcs[i].reg_value, outp->pfp_pmcs[i].reg_num, outp->pfp_pmcs[i].reg_addr);
}
}
return PFMLIB_SUCCESS;
@@ -344,23 +344,23 @@ pfm_crayx2_pmu_detect (void)
char buffer[128];
int ret;
- DPRINT (("detect the PMU attributes\n"));
+ DPRINT ("detect the PMU attributes\n");
ret = __pfm_getcpuinfo_attr ("vendor_id", buffer, sizeof(buffer));
if (ret != 0 || strcasecmp (buffer, "Cray") != 0) {
- DPRINT (("return: no 'Cray' vendor_id\n"));
+ DPRINT ("return: no 'Cray' vendor_id\n");
return PFMLIB_ERR_NOTSUPP;
}
ret = __pfm_getcpuinfo_attr ("type", buffer, sizeof(buffer));
if (ret != 0 || strcasecmp (buffer, "craynv2") != 0) {
- DPRINT (("return: no 'craynv2' type\n"));
+ DPRINT ("return: no 'craynv2' type\n");
return PFMLIB_ERR_NOTSUPP;
}
- DPRINT (("Cray X2 nv2 found\n"));
+ DPRINT ("Cray X2 nv2 found\n");
return PFMLIB_SUCCESS;
}
@@ -370,7 +370,7 @@ pfm_crayx2_get_impl_pmcs (pfmlib_regmask_t *impl_pmcs)
{
unsigned int i;
- DPRINT (("entered with PMC_COUNT %d\n", PMU_CRAYX2_PMC_COUNT));
+ DPRINT ("entered with PMC_COUNT %d\n", PMU_CRAYX2_PMC_COUNT);
for (i=0; i<PMU_CRAYX2_PMC_COUNT; i++) {
pfm_regmask_set (impl_pmcs, i);
}
@@ -383,7 +383,7 @@ pfm_crayx2_get_impl_pmds (pfmlib_regmask_t *impl_pmds)
{
unsigned int i;
- DPRINT (("entered with PMD_COUNT %d\n", PMU_CRAYX2_PMD_COUNT));
+ DPRINT ("entered with PMD_COUNT %d\n", PMU_CRAYX2_PMD_COUNT);
for (i=0; i<PMU_CRAYX2_PMD_COUNT; i++) {
pfm_regmask_set (impl_pmds, i);
}
@@ -396,7 +396,7 @@ pfm_crayx2_get_impl_counters (pfmlib_regmask_t *impl_counters)
{
unsigned int i;
- DPRINT (("entered with NUM_COUNTERS %d\n", PMU_CRAYX2_NUM_COUNTERS));
+ DPRINT ("entered with NUM_COUNTERS %d\n", PMU_CRAYX2_NUM_COUNTERS);
for (i=0; i<PMU_CRAYX2_NUM_COUNTERS; i++) {
pfm_regmask_set (impl_counters, i);
}
@@ -408,7 +408,7 @@ static void
pfm_crayx2_get_hw_counter_width (unsigned int *width)
{
*width = PMU_CRAYX2_COUNTER_WIDTH;
- DPRINT (("return: width set to %d\n", *width));
+ DPRINT ("return: width set to %d\n", *width);
return;
}
@@ -419,7 +419,7 @@ pfm_crayx2_get_event_desc (unsigned int ev, char **str)
const char *s = crayx2_pe[ev].pme_desc;
*str = (s == NULL ? NULL : strdup (s));
- DPRINT (("return: event description is '%s'\n", (s == NULL ? "" : s)));
+ DPRINT ("return: event description is '%s'\n", (s == NULL ? "" : s));
return PFMLIB_SUCCESS;
}
@@ -427,14 +427,14 @@ pfm_crayx2_get_event_desc (unsigned int ev, char **str)
static unsigned int
pfm_crayx2_get_num_event_masks (unsigned int ev)
{
- DPRINT (("return: #event masks is %d\n", crayx2_pe[ev].pme_numasks));
+ DPRINT ("return: #event masks is %d\n", crayx2_pe[ev].pme_numasks);
return crayx2_pe[ev].pme_numasks;
}
static char *
pfm_crayx2_get_event_mask_name (unsigned int ev, unsigned int midx)
{
- DPRINT (("return: event mask name is '%s'\n", crayx2_pe[ev].pme_umasks[midx].pme_uname));
+ DPRINT ("return: event mask name is '%s'\n", crayx2_pe[ev].pme_umasks[midx].pme_uname);
return (char *) crayx2_pe[ev].pme_umasks[midx].pme_uname;
}
@@ -442,7 +442,7 @@ static int
pfm_crayx2_get_event_mask_code (unsigned int ev, unsigned int midx, unsigned int *code)
{
*code = crayx2_pe[ev].pme_umasks[midx].pme_ucode;
- DPRINT (("return: event mask code is %#x\n", *code));
+ DPRINT ("return: event mask code is %#x\n", *code);
return PFMLIB_SUCCESS;
}
@@ -453,7 +453,7 @@ pfm_crayx2_get_event_mask_desc (unsigned int ev, unsigned int midx, char **str)
const char *s = crayx2_pe[ev].pme_umasks[midx].pme_udesc;
*str = (s == NULL ? NULL : strdup (s));
- DPRINT (("return: event mask description is '%s'\n", (s == NULL ? "" : s)));
+ DPRINT ("return: event mask description is '%s'\n", (s == NULL ? "" : s));
return PFMLIB_SUCCESS;
}
@@ -462,7 +462,7 @@ static int
pfm_crayx2_get_cycle_event (pfmlib_event_t *e)
{
e->event = PME_CRAYX2_CYCLES;
- DPRINT (("return: event code for cycles %#x\n", e->event));
+ DPRINT ("return: event code for cycles %#x\n", e->event);
return PFMLIB_SUCCESS;
}
@@ -471,7 +471,7 @@ static int
pfm_crayx2_get_inst_retired (pfmlib_event_t *e)
{
e->event = PME_CRAYX2_INSTR_GRADUATED;
- DPRINT (("return: event code for retired instr %#x\n", e->event));
+ DPRINT ("return: event code for retired instr %#x\n", e->event);
return PFMLIB_SUCCESS;
}
diff --git a/src/libpfm-3.y/lib/pfmlib_gen_ia32.c b/src/libpfm-3.y/lib/pfmlib_gen_ia32.c
index d7e62b734a75cedd9e40dd1d08085f4876c6065f..fc616fa059700c29e72d33dfb9bd7d18b1e87772 100644
--- a/src/libpfm-3.y/lib/pfmlib_gen_ia32.c
+++ b/src/libpfm-3.y/lib/pfmlib_gen_ia32.c
@@ -1,11 +1,8 @@
/*
- * pfmlib_gen_ia32.c : Intel architectural PMU v1 and v2
+ * pfmlib_gen_ia32.c : Intel architectural PMU v1, v2, v3
*
* The file provides support for the Intel architectural PMU v1 and v2.
*
- * It also provides support for Core Duo/Core Solo processors which
- * implement the architectural PMU v1 with more than architected events.
- *
* Copyright (c) 2005-2007 Hewlett-Packard Development Company, L.P.
* Contributed by Stephane Eranian <eranian@hpl.hp.com>
*
@@ -47,7 +44,6 @@
#include "pfmlib_gen_ia32_priv.h" /* architecture private */
#include "gen_ia32_events.h" /* architected event table */
-#include "coreduo_events.h" /* Core Duo/Core Solo event table */
/* let's define some handy shortcuts! */
#define sel_event_select perfevtsel.sel_event_select
@@ -57,12 +53,11 @@
#define sel_edge perfevtsel.sel_edge
#define sel_pc perfevtsel.sel_pc
#define sel_int perfevtsel.sel_int
+#define sel_any perfevtsel.sel_any
#define sel_en perfevtsel.sel_en
#define sel_inv perfevtsel.sel_inv
#define sel_cnt_mask perfevtsel.sel_cnt_mask
-pfm_pmu_support_t coreduo_support;
-pfm_pmu_support_t gen_ia32_support;
pfm_pmu_support_t *gen_support;
/*
@@ -107,7 +102,7 @@ pfm_pmu_support_t *gen_support;
#define FIXED_PMD_BASE 16
#define PFMLIB_GEN_IA32_ALL_FLAGS \
- (PFM_GEN_IA32_SEL_INV|PFM_GEN_IA32_SEL_EDGE)
+ (PFM_GEN_IA32_SEL_INV|PFM_GEN_IA32_SEL_EDGE|PFM_GEN_IA32_SEL_ANYTHR)
static char * pfm_gen_ia32_get_event_name(unsigned int i);
@@ -204,8 +199,6 @@ check_arch_pmu(int family)
pmu_eax_t eax;
pmu_edx_t edx;
} eax, ecx, edx, ebx;
- unsigned int num_cnt, i;
- int ret;
/*
* check family number to reject for processors
@@ -229,20 +222,66 @@ check_arch_pmu(int family)
*/
cpuid(0xa, &eax.val, &ebx.val, &ecx.val, &edx.val);
- num_cnt = eax.eax.num_cnt;
- pmu_version = eax.eax.version;
-
/*
- * check version. must be greater than zero
+ * version must be greater than zero
*/
- if (pmu_version < 1)
+ return eax.eax.version < 1 ? PFMLIB_ERR_NOTSUPP : PFMLIB_SUCCESS;
+}
+
+static int
+pfm_gen_ia32_detect(void)
+{
+ int ret, family;
+ char buffer[128];
+
+ ret = __pfm_getcpuinfo_attr("vendor_id", buffer, sizeof(buffer));
+ if (ret == -1)
+ return PFMLIB_ERR_NOTSUPP;
+
+ if (strcmp(buffer, "GenuineIntel"))
return PFMLIB_ERR_NOTSUPP;
+ ret = __pfm_getcpuinfo_attr("cpu family", buffer, sizeof(buffer));
+ if (ret == -1)
+ return PFMLIB_ERR_NOTSUPP;
+
+ family = atoi(buffer);
+
+ return check_arch_pmu(family);
+}
+
+static int
+pfm_gen_ia32_init(void)
+{
+ union {
+ unsigned int val;
+ pmu_eax_t eax;
+ pmu_edx_t edx;
+ } eax, ecx, edx, ebx;
+ unsigned int num_cnt, i;
+ int ret;
+
/*
- * sanity check number of counters
+ * extract architected PMU information
*/
- if (num_cnt == 0)
- return PFMLIB_ERR_NOTSUPP;
+ if (forced_pmu == PFMLIB_NO_PMU) {
+ cpuid(0xa, &eax.val, &ebx.val, &ecx.val, &edx.val);
+ } else {
+ /*
+ * when forced, simulate v2
+ * with 2 generic and 3 fixed counters
+ */
+ eax.eax.version = 3;
+ eax.eax.num_cnt = 2;
+ eax.eax.cnt_width = 40;
+ eax.eax.ebx_length = 0; /* unused */
+ ebx.val = 0;
+ edx.edx.num_cnt = 3;
+ edx.edx.cnt_width = 40;
+ }
+
+ num_cnt = eax.eax.num_cnt;
+ pmu_version = eax.eax.version;
/*
* populate impl_pm* bitmasks for generic counters
@@ -253,7 +292,7 @@ check_arch_pmu(int family)
}
/* check for fixed counters */
- if (pmu_version == 2) {
+ if (pmu_version >= 2) {
/*
* As described in IA-32 Developer's manual vol 3b
* in section 18.12.2.1, early processors supporting
@@ -293,71 +332,6 @@ check_arch_pmu(int family)
return PFMLIB_SUCCESS;
}
-static int
-pfm_gen_ia32_detect(void)
-{
- int ret, family;
- char buffer[128];
-
- ret = __pfm_getcpuinfo_attr("vendor_id", buffer, sizeof(buffer));
- if (ret == -1)
- return PFMLIB_ERR_NOTSUPP;
-
- if (strcmp(buffer, "GenuineIntel"))
- return PFMLIB_ERR_NOTSUPP;
-
- ret = __pfm_getcpuinfo_attr("cpu family", buffer, sizeof(buffer));
- if (ret == -1)
- return PFMLIB_ERR_NOTSUPP;
-
- family = atoi(buffer);
-
- return check_arch_pmu(family);
-}
-
-static int
-pfm_coreduo_detect(void)
-{
- int ret, family, model;
- char buffer[128];
-
- ret = __pfm_getcpuinfo_attr("vendor_id", buffer, sizeof(buffer));
- if (ret == -1)
- return PFMLIB_ERR_NOTSUPP;
-
- if (strcmp(buffer, "GenuineIntel"))
- return PFMLIB_ERR_NOTSUPP;
-
- ret = __pfm_getcpuinfo_attr("cpu family", buffer, sizeof(buffer));
- if (ret == -1)
- return PFMLIB_ERR_NOTSUPP;
-
- family = atoi(buffer);
-
- ret = __pfm_getcpuinfo_attr("model", buffer, sizeof(buffer));
- if (ret == -1)
- return PFMLIB_ERR_NOTSUPP;
-
- model = atoi(buffer);
-
- /*
- * check for core solo/core duo
- */
- if (family == 6 && model == 14) {
- unsigned int i;
- gen_ia32_pe = coreduo_pe;
- gen_support = &coreduo_support;
- gen_ia32_cycle_event = PME_COREDUO_UNHALTED_CORE_CYCLES;
- gen_ia32_inst_retired_event = PME_COREDUO_INSTRUCTIONS_RETIRED;
- for(i=0; i < 2; i++) {
- pfm_regmask_set(&gen_ia32_impl_pmcs, i);
- pfm_regmask_set(&gen_ia32_impl_pmds, i);
- }
- return PFMLIB_SUCCESS;
- }
- return PFMLIB_ERR_NOTSUPP;
-}
-
static int
pfm_gen_ia32_dispatch_counters_v1(pfmlib_input_param_t *inp, pfmlib_gen_ia32_input_param_t *mod_in, pfmlib_output_param_t *outp)
{
@@ -368,7 +342,7 @@ pfm_gen_ia32_dispatch_counters_v1(pfmlib_input_param_t *inp, pfmlib_gen_ia32_inp
pfmlib_reg_t *pc, *pd;
pfmlib_regmask_t *r_pmcs;
unsigned long plm;
- unsigned int i, j, cnt, k, umask;
+ unsigned int i, j, cnt, k, ucode, val;
unsigned int assign[PMU_GEN_IA32_MAX_COUNTERS];
e = inp->pfp_events;
@@ -380,7 +354,7 @@ pfm_gen_ia32_dispatch_counters_v1(pfmlib_input_param_t *inp, pfmlib_gen_ia32_inp
if (PFMLIB_DEBUG()) {
for (j=0; j < cnt; j++) {
- DPRINT(("ev[%d]=%s\n", j, gen_ia32_pe[e[j].event].pme_name));
+ DPRINT("ev[%d]=%s\n", j, gen_ia32_pe[e[j].event].pme_name);
}
}
@@ -389,15 +363,19 @@ pfm_gen_ia32_dispatch_counters_v1(pfmlib_input_param_t *inp, pfmlib_gen_ia32_inp
for(i=0, j=0; j < cnt; j++) {
if (e[j].plm & (PFM_PLM1|PFM_PLM2)) {
- DPRINT(("event=%d invalid plm=%d\n", e[j].event, e[j].plm));
+ DPRINT("event=%d invalid plm=%d\n", e[j].event, e[j].plm);
return PFMLIB_ERR_INVAL;
}
if (e[j].flags & ~PFMLIB_GEN_IA32_ALL_FLAGS) {
- DPRINT(("event=%d invalid flags=0x%lx\n", e[j].event, e[j].flags));
+ DPRINT("event=%d invalid flags=0x%lx\n", e[j].event, e[j].flags);
return PFMLIB_ERR_INVAL;
}
+ if (cntrs && pmu_version != 3 && (cntrs[j].flags & PFM_GEN_IA32_SEL_ANYTHR)) {
+ DPRINT("event=%d anythread requires architectural perfmon v3", e[j].event);
+ return PFMLIB_ERR_INVAL;
+ }
/*
* exclude restricted registers from assignment
*/
@@ -418,23 +396,43 @@ pfm_gen_ia32_dispatch_counters_v1(pfmlib_input_param_t *inp, pfmlib_gen_ia32_inp
/* if plm is 0, then assume not specified per-event and use default */
plm = e[j].plm ? e[j].plm : inp->pfp_dfl_plm;
- reg.sel_event_select = gen_ia32_pe[e[j].event].pme_code & 0xff;
+ val = gen_ia32_pe[e[j].event].pme_code;
- umask = (gen_ia32_pe[e[j].event].pme_code >> 8) & 0xff;
+ reg.sel_event_select = val & 0xff;
- for(k=0; k < e[j].num_masks; k++) {
- umask |= gen_ia32_pe[e[j].event].pme_umasks[e[j].unit_masks[k]].pme_ucode;
- }
- reg.sel_unit_mask = umask;
+ ucode = (val >> 8) & 0xff;
+
+ for(k=0; k < e[j].num_masks; k++)
+ ucode |= gen_ia32_pe[e[j].event].pme_umasks[e[j].unit_masks[k]].pme_ucode;
+
+ val |= ucode << 8;
+
+ reg.sel_unit_mask = ucode; /* use 8 least significant bits */
reg.sel_usr = plm & PFM_PLM3 ? 1 : 0;
reg.sel_os = plm & PFM_PLM0 ? 1 : 0;
reg.sel_en = 1; /* force enable bit to 1 */
reg.sel_int = 1; /* force APIC int to 1 */
+ reg.sel_cnt_mask = val >>24;
+ reg.sel_inv = val >> 23;
+ reg.sel_any = val >> 21;;
+ reg.sel_edge = val >> 18;
+
if (cntrs) {
- reg.sel_cnt_mask = cntrs[j].cnt_mask;
- reg.sel_edge = cntrs[j].flags & PFM_GEN_IA32_SEL_EDGE ? 1 : 0;
- reg.sel_inv = cntrs[j].flags & PFM_GEN_IA32_SEL_INV ? 1 : 0;
+ if (!reg.sel_cnt_mask) {
+ /*
+ * counter mask is 8-bit wide, do not silently
+ * wrap-around
+ */
+ if (cntrs[i].cnt_mask > 255)
+ return PFMLIB_ERR_INVAL;
+ reg.sel_cnt_mask = cntrs[j].cnt_mask;
+ }
+
+ if (!reg.sel_edge)
+ reg.sel_edge = cntrs[j].flags & PFM_GEN_IA32_SEL_EDGE ? 1 : 0;
+ if (!reg.sel_inv)
+ reg.sel_inv = cntrs[j].flags & PFM_GEN_IA32_SEL_INV ? 1 : 0;
}
pc[j].reg_num = assign[j];
@@ -468,8 +466,11 @@ pfm_gen_ia32_dispatch_counters_v1(pfmlib_input_param_t *inp, pfmlib_gen_ia32_inp
return PFMLIB_SUCCESS;
}
+static const char *fixed_event_names[]={ "INSTRUCTIONS_RETIRED", "UNHALTED_CORE_CYCLES ", "UNHALTED_REFERENCE_CYCLES " };
+#define MAX_EVENT_NAMES (sizeof(fixed_event_names)/sizeof(char *))
+
static int
-pfm_gen_ia32_dispatch_counters_v2(pfmlib_input_param_t *inp, pfmlib_gen_ia32_input_param_t *param, pfmlib_output_param_t *outp)
+pfm_gen_ia32_dispatch_counters_v23(pfmlib_input_param_t *inp, pfmlib_gen_ia32_input_param_t *param, pfmlib_output_param_t *outp)
{
#define HAS_OPTIONS(x) (cntrs && (cntrs[i].flags || cntrs[i].cnt_mask))
#define is_fixed_pmc(a) (a > 15)
@@ -483,7 +484,7 @@ pfm_gen_ia32_dispatch_counters_v2(pfmlib_input_param_t *inp, pfmlib_gen_ia32_inp
unsigned long plm;
unsigned int fixed_ctr_mask;
unsigned int npc = 0;
- unsigned int i, j, n, k, umask;
+ unsigned int i, j, n, k, ucode;
unsigned int assign[PMU_GEN_IA32_MAX_COUNTERS];
unsigned int next_gen, last_gen;
@@ -516,8 +517,13 @@ pfm_gen_ia32_dispatch_counters_v2(pfmlib_input_param_t *inp, pfmlib_gen_ia32_inp
/*
* check for valid flags
*/
- if (e[j].flags & ~PFMLIB_GEN_IA32_ALL_FLAGS)
+ if (cntrs && cntrs[j].flags & ~PFMLIB_GEN_IA32_ALL_FLAGS)
return PFMLIB_ERR_INVAL;
+
+ if (cntrs && pmu_version != 3 && (cntrs[j].flags & PFM_GEN_IA32_SEL_ANYTHR)) {
+ DPRINT("event=%d anythread requires architectural perfmon v3", e[j].event);
+ return PFMLIB_ERR_INVAL;
+ }
}
next_gen = 0; /* first generic counter */
@@ -530,8 +536,13 @@ pfm_gen_ia32_dispatch_counters_v2(pfmlib_input_param_t *inp, pfmlib_gen_ia32_inp
if (fixed_ctr_mask) {
for(i=0; i < n; i++) {
/* fixed counters do not support event options (filters) */
- if (HAS_OPTIONS(i))
- continue;
+ if (HAS_OPTIONS(i)) {
+ if (pmu_version != 3)
+ continue;
+ if (cntrs[i].flags != PFM_GEN_IA32_SEL_ANYTHR)
+ continue;
+ /* ok for ANYTHR */
+ }
for(j=0; j < num_fixed_cnt; j++) {
if ((fixed_ctr_mask & (1<<j)) && gen_ia32_pe[e[i].event].pme_fixed == (FIXED_PMD_BASE+j)) {
assign[i] = FIXED_PMD_BASE+j;
@@ -571,6 +582,11 @@ pfm_gen_ia32_dispatch_counters_v2(pfmlib_input_param_t *inp, pfmlib_gen_ia32_inp
val |= 1ULL;
if (plm & PFM_PLM3)
val |= 2ULL;
+
+ /* only possible for v3 */
+ if (cntrs && cntrs[i].flags & PFM_GEN_IA32_SEL_ANYTHR)
+ val |= 4ULL;
+
val |= 1ULL << 3; /* force APIC int (kernel may force it anyway) */
reg.val |= val << ((assign[i]-FIXED_PMD_BASE)<<2);
@@ -590,17 +606,27 @@ pfm_gen_ia32_dispatch_counters_v2(pfmlib_input_param_t *inp, pfmlib_gen_ia32_inp
reg.val);
for(i=0; i < num_fixed_cnt; i++) {
- __pfm_vbprintf(" pmi%d=1 en%d=0x%"PRIx64,
- i, i,
- (reg.val >> (i*4)) & 0x3ULL);
+ if (pmu_version != 3)
+ __pfm_vbprintf(" pmi%d=1 en%d=0x%"PRIx64,
+ i, i,
+ (reg.val >> (i*4)) & 0x3ULL);
+ else
+ __pfm_vbprintf(" pmi%d=1 en%d=0x%"PRIx64 " any%d=%"PRId64,
+ i, i,
+ (reg.val >> (i*4)) & 0x3ULL,
+ i,
+ !!((reg.val >> (i*4)) & 0x4ULL));
}
+
__pfm_vbprintf("] ");
- if ((fixed_ctr_mask & 0x1) == 0)
- __pfm_vbprintf("INSTRUCTIONS_RETIRED ");
- if ((fixed_ctr_mask & 0x2) == 0)
- __pfm_vbprintf("UNHALTED_CORE_CYCLES ");
- if ((fixed_ctr_mask & 0x4) == 0)
- __pfm_vbprintf("UNHALTED_REFERENCE_CYCLES ");
+ for(i=0; i < num_fixed_cnt; i++) {
+ if ((fixed_ctr_mask & (0x1 << i)) == 0) {
+ if (i < MAX_EVENT_NAMES)
+ __pfm_vbprintf("%s ", fixed_event_names[i]);
+ else
+ __pfm_vbprintf("??? ");
+ }
+ }
__pfm_vbprintf("\n");
npc++;
@@ -622,31 +648,44 @@ pfm_gen_ia32_dispatch_counters_v2(pfmlib_input_param_t *inp, pfmlib_gen_ia32_inp
/* if plm is 0, then assume not specified per-event and use default */
plm = e[i].plm ? e[i].plm : inp->pfp_dfl_plm;
- reg.sel_event_select = gen_ia32_pe[e[i].event].pme_code & 0xff;
+ val = gen_ia32_pe[e[i].event].pme_code;
- umask = (gen_ia32_pe[e[i].event].pme_code >> 8) & 0xff;
+ reg.sel_event_select = val & 0xff;
- for(k=0; k < e[i].num_masks; k++) {
- umask |= gen_ia32_pe[e[i].event].pme_umasks[e[i].unit_masks[k]].pme_ucode;
- }
+ ucode = (val >> 8) & 0xff;
- reg.sel_unit_mask = umask;
+ for(k=0; k < e[i].num_masks; k++)
+ ucode |= gen_ia32_pe[e[i].event].pme_umasks[e[i].unit_masks[k]].pme_ucode;
+
+ val |= ucode << 8;
+
+ reg.sel_unit_mask = ucode;
reg.sel_usr = plm & PFM_PLM3 ? 1 : 0;
reg.sel_os = plm & PFM_PLM0 ? 1 : 0;
reg.sel_en = 1; /* force enable bit to 1 */
reg.sel_int = 1; /* force APIC int to 1 */
- if (cntrs) {
- /*
- * counter mask is 8-bit wide, do not silently
- * wrap-around
- */
- if (cntrs[i].cnt_mask > 255)
- return PFMLIB_ERR_INVAL;
+ reg.sel_cnt_mask = val >>24;
+ reg.sel_inv = val >> 23;
+ reg.sel_any = val >> 21;;
+ reg.sel_edge = val >> 18;
- reg.sel_cnt_mask = cntrs[i].cnt_mask;
- reg.sel_edge = cntrs[i].flags & PFM_GEN_IA32_SEL_EDGE ? 1 : 0;
- reg.sel_inv = cntrs[i].flags & PFM_GEN_IA32_SEL_INV ? 1 : 0;
+ if (cntrs) {
+ if (!reg.sel_cnt_mask) {
+ /*
+ * counter mask is 8-bit wide, do not silently
+ * wrap-around
+ */
+ if (cntrs[i].cnt_mask > 255)
+ return PFMLIB_ERR_INVAL;
+ reg.sel_cnt_mask = cntrs[i].cnt_mask;
+ }
+ if (!reg.sel_edge)
+ reg.sel_edge = cntrs[i].flags & PFM_GEN_IA32_SEL_EDGE ? 1 : 0;
+ if (!reg.sel_inv)
+ reg.sel_inv = cntrs[i].flags & PFM_GEN_IA32_SEL_INV ? 1 : 0;
+ if (!reg.sel_any)
+ reg.sel_any = cntrs[i].flags & PFM_GEN_IA32_SEL_ANYTHR? 1 : 0;
}
pc[npc].reg_num = assign[i];
@@ -655,20 +694,37 @@ pfm_gen_ia32_dispatch_counters_v2(pfmlib_input_param_t *inp, pfmlib_gen_ia32_inp
pd[i].reg_num = assign[i];
pd[i].reg_addr = GEN_IA32_CTR_BASE+assign[i];
- __pfm_vbprintf("[PERFEVTSEL%u(pmc%u)=0x%"PRIx64" event_sel=0x%x umask=0x%x os=%d usr=%d en=%d int=%d inv=%d edge=%d cnt_mask=%d] %s\n",
- pc[npc].reg_num,
- pc[npc].reg_num,
- reg.val,
- reg.sel_event_select,
- reg.sel_unit_mask,
- reg.sel_os,
- reg.sel_usr,
- reg.sel_en,
- reg.sel_int,
- reg.sel_inv,
- reg.sel_edge,
- reg.sel_cnt_mask,
- gen_ia32_pe[e[i].event].pme_name);
+ if (pmu_version < 3)
+ __pfm_vbprintf("[PERFEVTSEL%u(pmc%u)=0x%"PRIx64" event_sel=0x%x umask=0x%x os=%d usr=%d en=%d int=%d inv=%d edge=%d cnt_mask=%d] %s\n",
+ pc[npc].reg_num,
+ pc[npc].reg_num,
+ reg.val,
+ reg.sel_event_select,
+ reg.sel_unit_mask,
+ reg.sel_os,
+ reg.sel_usr,
+ reg.sel_en,
+ reg.sel_int,
+ reg.sel_inv,
+ reg.sel_edge,
+ reg.sel_cnt_mask,
+ gen_ia32_pe[e[i].event].pme_name);
+ else
+ __pfm_vbprintf("[PERFEVTSEL%u(pmc%u)=0x%"PRIx64" event_sel=0x%x umask=0x%x os=%d usr=%d en=%d int=%d inv=%d edge=%d cnt_mask=%d anythr=%d] %s\n",
+ pc[npc].reg_num,
+ pc[npc].reg_num,
+ reg.val,
+ reg.sel_event_select,
+ reg.sel_unit_mask,
+ reg.sel_os,
+ reg.sel_usr,
+ reg.sel_en,
+ reg.sel_int,
+ reg.sel_inv,
+ reg.sel_edge,
+ reg.sel_cnt_mask,
+ reg.sel_any,
+ gen_ia32_pe[e[i].event].pme_name);
__pfm_vbprintf("[PMC%u(pmd%u)]\n",
pd[i].reg_num,
@@ -688,17 +744,15 @@ pfm_gen_ia32_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_o
pfmlib_gen_ia32_input_param_t *mod_in = model_in;
if (inp->pfp_dfl_plm & (PFM_PLM1|PFM_PLM2)) {
- DPRINT(("invalid plm=%x\n", inp->pfp_dfl_plm));
+ DPRINT("invalid plm=%x\n", inp->pfp_dfl_plm);
return PFMLIB_ERR_INVAL;
}
- switch(pmu_version) {
- case 1:
- return pfm_gen_ia32_dispatch_counters_v1(inp, mod_in, outp);
- case 2:
- return pfm_gen_ia32_dispatch_counters_v2(inp, mod_in, outp);
- default:
- return PFMLIB_ERR_INVAL;
- }
+
+ /* simplfied v1 (no fixed counters */
+ if (pmu_version == 1)
+ return pfm_gen_ia32_dispatch_counters_v1(inp, mod_in, outp);
+ /* v2 or above */
+ return pfm_gen_ia32_dispatch_counters_v23(inp, mod_in, outp);
}
static int
@@ -844,6 +898,7 @@ pfm_pmu_support_t gen_ia32_support={
.get_event_counters = pfm_gen_ia32_get_event_counters,
.dispatch_events = pfm_gen_ia32_dispatch_events,
.pmu_detect = pfm_gen_ia32_detect,
+ .pmu_init = pfm_gen_ia32_init,
.get_impl_pmcs = pfm_gen_ia32_get_impl_pmcs,
.get_impl_pmds = pfm_gen_ia32_get_impl_pmds,
.get_impl_counters = pfm_gen_ia32_get_impl_counters,
@@ -856,28 +911,3 @@ pfm_pmu_support_t gen_ia32_support={
.get_event_mask_code = pfm_gen_ia32_get_event_mask_code,
.get_event_mask_desc = pfm_gen_ia32_get_event_mask_desc
};
-
-pfm_pmu_support_t coreduo_support={
- .pmu_name = "Intel Core Duo/Core Solo",
- .pmu_type = PFMLIB_COREDUO_PMU,
- .pme_count = PME_COREDUO_EVENT_COUNT,
- .pmc_count = 2,
- .pmd_count = 2,
- .num_cnt = 2,
- .get_event_code = pfm_gen_ia32_get_event_code,
- .get_event_name = pfm_gen_ia32_get_event_name,
- .get_event_counters = pfm_gen_ia32_get_event_counters,
- .dispatch_events = pfm_gen_ia32_dispatch_events,
- .pmu_detect = pfm_coreduo_detect,
- .get_impl_pmcs = pfm_gen_ia32_get_impl_pmcs,
- .get_impl_pmds = pfm_gen_ia32_get_impl_pmds,
- .get_impl_counters = pfm_gen_ia32_get_impl_counters,
- .get_hw_counter_width = pfm_gen_ia32_get_hw_counter_width,
- .get_event_desc = pfm_gen_ia32_get_event_description,
- .get_num_event_masks = pfm_gen_ia32_get_num_event_masks,
- .get_event_mask_name = pfm_gen_ia32_get_event_mask_name,
- .get_event_mask_code = pfm_gen_ia32_get_event_mask_code,
- .get_event_mask_desc = pfm_gen_ia32_get_event_mask_desc,
- .get_cycle_event = pfm_gen_ia32_get_cycle_event,
- .get_inst_retired_event = pfm_gen_ia32_get_inst_retired
-};
diff --git a/src/libpfm-3.y/lib/pfmlib_gen_ia64.c b/src/libpfm-3.y/lib/pfmlib_gen_ia64.c
index 8c6ee2e879e4b37c6f3f9d860f459e6c8ba498f3..9a9789f961ace6efb6fc69fa5ac8285e4f0acb26 100644
--- a/src/libpfm-3.y/lib/pfmlib_gen_ia64.c
+++ b/src/libpfm-3.y/lib/pfmlib_gen_ia64.c
@@ -70,7 +70,7 @@ typedef union {
typedef struct pme_entry {
char *pme_name;
pme_gen_ia64_entry_code_t pme_entry_code; /* event code */
- pfmlib_regmask_bits_t pme_counters[PFMLIB_REG_BV]; /* counter bitmask */
+ pfmlib_regmask_t pme_counters; /* counter bitmask */
} pme_gen_ia64_entry_t;
/* let's define some handy shortcuts ! */
@@ -92,8 +92,8 @@ static pme_gen_ia64_entry_t generic_pe[PME_GEN_COUNT]={
static int pfm_gen_ia64_counter_width;
static int pfm_gen_ia64_counters;
-static pfmlib_regmask_bits_t pfm_gen_ia64_impl_pmcs[PFMLIB_REG_BV];
-static pfmlib_regmask_bits_t pfm_gen_ia64_impl_pmds[PFMLIB_REG_BV];
+static pfmlib_regmask_t pfm_gen_ia64_impl_pmcs;
+static pfmlib_regmask_t pfm_gen_ia64_impl_pmds;
/*
* Description of the PMC register mappings use by
* this module (as reported in pfmlib_reg_t.reg_num):
@@ -112,7 +112,7 @@ static pfmlib_regmask_bits_t pfm_gen_ia64_impl_pmds[PFMLIB_REG_BV];
* range argument is modified
*/
static int
-parse_counter_range(char *range, unsigned long *bitmask)
+parse_counter_range(char *range, pfmlib_regmask_t *b)
{
char *p, c;
int start, end;
@@ -120,12 +120,6 @@ parse_counter_range(char *range, unsigned long *bitmask)
if (range[strlen(range)-1] == '\n')
range[strlen(range)-1] = '\0';
- /*
- * reset bitmask argument
- */
- for (start=0; start < PFMLIB_REG_BV; start++)
- bitmask[start] = 0;
-
while(range) {
p = range;
while (*p && *p != ' ' && *p != '-') p++;
@@ -150,7 +144,7 @@ parse_counter_range(char *range, unsigned long *bitmask)
if (end >= PFMLIB_REG_MAX|| start >= PFMLIB_REG_MAX)
goto invalid;
for (; start <= end; start++)
- bitmask[__PFMLIB_REGMASK_EL(start)] |= __PFMLIB_REGMASK_MASK(start);
+ pfm_regmask_set(b, start);
}
return 0;
invalid:
@@ -199,42 +193,78 @@ pfm_gen_ia64_initialize(void)
continue;
}
if (!strncmp("Cycles count capable", buffer, 20)) {
- if (parse_counter_range(p+2, generic_pe[0].pme_counters) == -1) return -1;
+ if (parse_counter_range(p+2, &generic_pe[0].pme_counters) == -1) return -1;
matches++;
continue;
}
if (!strncmp("Retired bundles count capable", buffer, 29)) {
- if (parse_counter_range(p+2, generic_pe[1].pme_counters) == -1) return -1;
+ if (parse_counter_range(p+2, &generic_pe[1].pme_counters) == -1) return -1;
matches++;
continue;
}
if (!strncmp("Implemented PMC", buffer, 15)) {
- if (parse_counter_range(p+2, pfm_gen_ia64_impl_pmcs) == -1) return -1;
+ if (parse_counter_range(p+2, &pfm_gen_ia64_impl_pmcs) == -1) return -1;
matches++;
continue;
}
if (!strncmp("Implemented PMD", buffer, 15)) {
- if (parse_counter_range(p+2, pfm_gen_ia64_impl_pmds) == -1) return -1;
+ if (parse_counter_range(p+2, &pfm_gen_ia64_impl_pmds) == -1) return -1;
matches++;
continue;
}
}
+ pfm_regmask_weight(&pfm_gen_ia64_impl_pmcs, &generic_ia64_support.pmc_count);
+ pfm_regmask_weight(&pfm_gen_ia64_impl_pmds, &generic_ia64_support.pmd_count);
fclose(fp);
return matches == 8 ? PFMLIB_SUCCESS : PFMLIB_ERR_NOTSUPP;
}
-static int
-pfm_gen_ia64_detect(void)
+static void
+pfm_gen_ia64_forced_initialize(void)
{
- static int initialization_done;
+ unsigned int i;
- if (initialization_done) return 0;
+ pfm_gen_ia64_counter_width = 47;
+ pfm_gen_ia64_counters = 4;
- /* always match */
- if (pfm_gen_ia64_initialize() == -1) return PFMLIB_ERR_NOTSUPP;
+ generic_pe[0].pme_entry_code.pme_vcode = 18;
+ generic_pe[1].pme_entry_code.pme_vcode = 8;
- initialization_done = 1;
+ memset(&pfm_gen_ia64_impl_pmcs, 0, sizeof(pfmlib_regmask_t));
+ memset(&pfm_gen_ia64_impl_pmds, 0, sizeof(pfmlib_regmask_t));
+
+ for(i=0; i < 8; i++)
+ pfm_regmask_set(&pfm_gen_ia64_impl_pmcs, i);
+
+ for(i=4; i < 8; i++)
+ pfm_regmask_set(&pfm_gen_ia64_impl_pmds, i);
+
+ memset(&generic_pe[0].pme_counters, 0, sizeof(pfmlib_regmask_t));
+ memset(&generic_pe[1].pme_counters, 0, sizeof(pfmlib_regmask_t));
+ for(i=4; i < 8; i++) {
+ pfm_regmask_set(&generic_pe[0].pme_counters, i);
+ pfm_regmask_set(&generic_pe[1].pme_counters, i);
+ }
+ generic_ia64_support.pmc_count = 8;
+ generic_ia64_support.pmd_count = 4;
+ generic_ia64_support.num_cnt = 4;
+}
+
+static int
+pfm_gen_ia64_detect(void)
+{
+ /* PMU is architected, so guaranteed to be present */
+ return PFMLIB_SUCCESS;
+}
+
+static int
+pfm_gen_ia64_init(void)
+{
+ if (forced_pmu != PFMLIB_NO_PMU) {
+ pfm_gen_ia64_forced_initialize();
+ } else if (pfm_gen_ia64_initialize() == -1)
+ return PFMLIB_ERR_NOTSUPP;
return PFMLIB_SUCCESS;
}
@@ -261,7 +291,7 @@ valid_assign(unsigned int *as, pfmlib_regmask_t *r_pmcs, unsigned int cnt)
static int
pfm_gen_ia64_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_output_param_t *outp)
{
-#define has_counter(e,b) (generic_pe[e].pme_counters[__PFMLIB_REGMASK_EL(b)] & __PFMLIB_REGMASK_MASK(b) ? (b) : 0)
+#define has_counter(e,b) (pfm_regmask_isset(&generic_pe[e].pme_counters, b) ? b : 0)
unsigned int max_l0, max_l1, max_l2, max_l3;
unsigned int assign[PMU_GEN_IA64_MAX_COUNTERS];
pfm_gen_ia64_pmc_reg_t reg;
@@ -277,15 +307,6 @@ pfm_gen_ia64_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_output_param_t
cnt = inp->pfp_event_count;
r_pmcs = &inp->pfp_unavail_pmcs;
- if (PFMLIB_DEBUG()) {
- for (i=0; i < cnt; i++) {
- DPRINT(("ev[%d]=%s counters=0x%lx\n",
- i,
- generic_pe[e[i].event].pme_name,
- generic_pe[e[i].event].pme_counters[0]));
- }
- }
-
if (cnt > PMU_GEN_IA64_MAX_COUNTERS) return PFMLIB_ERR_TOOMANY;
max_l0 = PMU_GEN_IA64_FIRST_COUNTER + PMU_GEN_IA64_MAX_COUNTERS;
@@ -294,7 +315,7 @@ pfm_gen_ia64_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_output_param_t
max_l3 = PMU_GEN_IA64_FIRST_COUNTER + PMU_GEN_IA64_MAX_COUNTERS*(cnt>3);
if (PFMLIB_DEBUG()) {
- DPRINT(("max_l0=%u max_l1=%u max_l2=%u max_l3=%u\n", max_l0, max_l1, max_l2, max_l3));
+ DPRINT("max_l0=%u max_l1=%u max_l2=%u max_l3=%u\n", max_l0, max_l1, max_l2, max_l3);
}
/*
* This code needs fixing. It is not very pretty and
@@ -399,26 +420,25 @@ static void
pfm_gen_ia64_get_event_counters(unsigned int j, pfmlib_regmask_t *counters)
{
unsigned int i;
- unsigned long m;
memset(counters, 0, sizeof(*counters));
- m = generic_pe[j].pme_counters[0];
- for(i=0; m ; i++, m>>=1) {
- if (m & 0x1) pfm_regmask_set(counters, i);
+ for(i=0; i < pfm_gen_ia64_counters; i++) {
+ if (pfm_regmask_isset(&generic_pe[j].pme_counters, i))
+ pfm_regmask_set(counters, i);
}
}
static void
pfm_gen_ia64_get_impl_pmcs(pfmlib_regmask_t *impl_pmcs)
{
- memcpy(impl_pmcs->bits, pfm_gen_ia64_impl_pmcs, sizeof(*impl_pmcs));
+ *impl_pmcs = pfm_gen_ia64_impl_pmcs;
}
static void
pfm_gen_ia64_get_impl_pmds(pfmlib_regmask_t *impl_pmds)
{
- memcpy(impl_pmds->bits, pfm_gen_ia64_impl_pmds, sizeof(*impl_pmds));
+ *impl_pmds = pfm_gen_ia64_impl_pmds;
}
static void
@@ -480,6 +500,7 @@ pfm_pmu_support_t generic_ia64_support={
.get_event_counters = pfm_gen_ia64_get_event_counters,
.dispatch_events = pfm_gen_ia64_dispatch_events,
.pmu_detect = pfm_gen_ia64_detect,
+ .pmu_init = pfm_gen_ia64_init,
.get_impl_pmcs = pfm_gen_ia64_get_impl_pmcs,
.get_impl_pmds = pfm_gen_ia64_get_impl_pmds,
.get_impl_counters = pfm_gen_ia64_get_impl_counters,
diff --git a/src/libpfm-3.y/lib/pfmlib_gen_mips64.c b/src/libpfm-3.y/lib/pfmlib_gen_mips64.c
index f8353a670ba4ca50fb252afccdd9273d05b0d1b0..0b4190816cb13f49f156b99d3b0f279b8b1c1a36 100644
--- a/src/libpfm-3.y/lib/pfmlib_gen_mips64.c
+++ b/src/libpfm-3.y/lib/pfmlib_gen_mips64.c
@@ -49,7 +49,7 @@
static pme_gen_mips64_entry_t *gen_mips64_pe = NULL;
-static char * pfm_gen_mips64_get_event_name(unsigned int i);
+pfm_pmu_support_t generic_mips64_support;
static int
pfm_gen_mips64_detect(void)
@@ -57,173 +57,177 @@ pfm_gen_mips64_detect(void)
static char mips_name[64] = "";
int ret;
char buffer[128];
- extern pfm_pmu_support_t generic_mips64_support;
ret = __pfm_getcpuinfo_attr("cpu model", buffer, sizeof(buffer));
if (ret == -1)
return PFMLIB_ERR_NOTSUPP;
generic_mips64_support.pmu_name = mips_name;
+ generic_mips64_support.num_cnt = 0;
if (strstr(buffer,"MIPS 20Kc"))
{
- gen_mips64_pe = gen_mips64_20K_pe;
- strcpy(generic_mips64_support.pmu_name,"MIPS20KC"),
- generic_mips64_support.pme_count = (sizeof(gen_mips64_20K_pe)/sizeof(pme_gen_mips64_entry_t));
- generic_mips64_support.pmc_count = 1;
- generic_mips64_support.pmd_count = 1;
- generic_mips64_support.pmu_type = PFMLIB_MIPS_20KC_PMU;
+ gen_mips64_pe = gen_mips64_20K_pe;
+ strcpy(generic_mips64_support.pmu_name,"MIPS20KC"),
+ generic_mips64_support.pme_count = (sizeof(gen_mips64_20K_pe)/sizeof(pme_gen_mips64_entry_t));
+ generic_mips64_support.pmc_count = 1;
+ generic_mips64_support.pmd_count = 1;
+ generic_mips64_support.pmu_type = PFMLIB_MIPS_20KC_PMU;
}
else if (strstr(buffer,"MIPS 24K"))
{
- gen_mips64_pe = gen_mips64_24K_pe;
- strcpy(generic_mips64_support.pmu_name,"MIPS24K"),
- generic_mips64_support.pme_count = (sizeof(gen_mips64_24K_pe)/sizeof(pme_gen_mips64_entry_t));
- generic_mips64_support.pmc_count = 2;
- generic_mips64_support.pmd_count = 2;
- generic_mips64_support.pmu_type = PFMLIB_MIPS_24K_PMU;
+ gen_mips64_pe = gen_mips64_24K_pe;
+ strcpy(generic_mips64_support.pmu_name,"MIPS24K"),
+ generic_mips64_support.pme_count = (sizeof(gen_mips64_24K_pe)/sizeof(pme_gen_mips64_entry_t));
+ generic_mips64_support.pmc_count = 2;
+ generic_mips64_support.pmd_count = 2;
+ generic_mips64_support.pmu_type = PFMLIB_MIPS_24K_PMU;
}
else if (strstr(buffer,"MIPS 25Kf"))
{
- gen_mips64_pe = gen_mips64_25K_pe;
- strcpy(generic_mips64_support.pmu_name,"MIPS25KF"),
- generic_mips64_support.pme_count = (sizeof(gen_mips64_25K_pe)/sizeof(pme_gen_mips64_entry_t));
- generic_mips64_support.pmc_count = 2;
- generic_mips64_support.pmd_count = 2;
- generic_mips64_support.pmu_type = PFMLIB_MIPS_25KF_PMU;
+ gen_mips64_pe = gen_mips64_25K_pe;
+ strcpy(generic_mips64_support.pmu_name,"MIPS25KF"),
+ generic_mips64_support.pme_count = (sizeof(gen_mips64_25K_pe)/sizeof(pme_gen_mips64_entry_t));
+ generic_mips64_support.pmc_count = 2;
+ generic_mips64_support.pmd_count = 2;
+ generic_mips64_support.pmu_type = PFMLIB_MIPS_25KF_PMU;
}
else if (strstr(buffer,"MIPS 34K"))
{
- gen_mips64_pe = gen_mips64_34K_pe;
- strcpy(generic_mips64_support.pmu_name,"MIPS34K"),
- generic_mips64_support.pme_count = (sizeof(gen_mips64_34K_pe)/sizeof(pme_gen_mips64_entry_t));
- generic_mips64_support.pmc_count = 4;
- generic_mips64_support.pmd_count = 4;
- generic_mips64_support.pmu_type = PFMLIB_MIPS_34K_PMU;
+ gen_mips64_pe = gen_mips64_34K_pe;
+ strcpy(generic_mips64_support.pmu_name,"MIPS34K"),
+ generic_mips64_support.pme_count = (sizeof(gen_mips64_34K_pe)/sizeof(pme_gen_mips64_entry_t));
+ generic_mips64_support.pmc_count = 4;
+ generic_mips64_support.pmd_count = 4;
+ generic_mips64_support.pmu_type = PFMLIB_MIPS_34K_PMU;
}
else if (strstr(buffer,"MIPS 5Kc"))
{
- gen_mips64_pe = gen_mips64_5K_pe;
- strcpy(generic_mips64_support.pmu_name,"MIPS5KC"),
- generic_mips64_support.pme_count = (sizeof(gen_mips64_5K_pe)/sizeof(pme_gen_mips64_entry_t));
- generic_mips64_support.pmc_count = 2;
- generic_mips64_support.pmd_count = 2;
- generic_mips64_support.pmu_type = PFMLIB_MIPS_5KC_PMU;
- }
+ gen_mips64_pe = gen_mips64_5K_pe;
+ strcpy(generic_mips64_support.pmu_name,"MIPS5KC"),
+ generic_mips64_support.pme_count = (sizeof(gen_mips64_5K_pe)/sizeof(pme_gen_mips64_entry_t));
+ generic_mips64_support.pmc_count = 2;
+ generic_mips64_support.pmd_count = 2;
+ generic_mips64_support.pmu_type = PFMLIB_MIPS_5KC_PMU;
+ }
#if 0
else if (strstr(buffer,"MIPS 74K"))
{
- gen_mips64_pe = gen_mips64_74K_pe;
- strcpy(generic_mips64_support.pmu_name,"MIPS74K"),
- generic_mips64_support.pme_count = (sizeof(gen_mips64_74K_pe)/sizeof(pme_gen_mips64_entry_t));
- generic_mips64_support.pmc_count = 4;
- generic_mips64_support.pmd_count = 4;
- generic_mips64_support.pmu_type = PFMLIB_MIPS_74K_PMU;
- }
+ gen_mips64_pe = gen_mips64_74K_pe;
+ strcpy(generic_mips64_support.pmu_name,"MIPS74K"),
+ generic_mips64_support.pme_count = (sizeof(gen_mips64_74K_pe)/sizeof(pme_gen_mips64_entry_t));
+ generic_mips64_support.pmc_count = 4;
+ generic_mips64_support.pmd_count = 4;
+ generic_mips64_support.pmu_type = PFMLIB_MIPS_74K_PMU;
+ }
#endif
else if (strstr(buffer,"R10000"))
{
- gen_mips64_pe = gen_mips64_r10000_pe;
- strcpy(generic_mips64_support.pmu_name,"MIPSR10000"),
- generic_mips64_support.pme_count = (sizeof(gen_mips64_r10000_pe)/sizeof(pme_gen_mips64_entry_t));
- generic_mips64_support.pmc_count = 2;
- generic_mips64_support.pmd_count = 2;
- generic_mips64_support.pmu_type = PFMLIB_MIPS_R10000_PMU;
+ gen_mips64_pe = gen_mips64_r10000_pe;
+ strcpy(generic_mips64_support.pmu_name,"MIPSR10000"),
+ generic_mips64_support.pme_count = (sizeof(gen_mips64_r10000_pe)/sizeof(pme_gen_mips64_entry_t));
+ generic_mips64_support.pmc_count = 2;
+ generic_mips64_support.pmd_count = 2;
+ generic_mips64_support.pmu_type = PFMLIB_MIPS_R10000_PMU;
}
else if (strstr(buffer,"R12000"))
{
- gen_mips64_pe = gen_mips64_r12000_pe;
- strcpy(generic_mips64_support.pmu_name,"MIPSR12000"),
- generic_mips64_support.pme_count = (sizeof(gen_mips64_r12000_pe)/sizeof(pme_gen_mips64_entry_t));
- generic_mips64_support.pmc_count = 4;
- generic_mips64_support.pmd_count = 4;
- generic_mips64_support.pmu_type = PFMLIB_MIPS_R12000_PMU;
+ gen_mips64_pe = gen_mips64_r12000_pe;
+ strcpy(generic_mips64_support.pmu_name,"MIPSR12000"),
+ generic_mips64_support.pme_count = (sizeof(gen_mips64_r12000_pe)/sizeof(pme_gen_mips64_entry_t));
+ generic_mips64_support.pmc_count = 4;
+ generic_mips64_support.pmd_count = 4;
+ generic_mips64_support.pmu_type = PFMLIB_MIPS_R12000_PMU;
}
else if (strstr(buffer,"RM7000"))
{
- gen_mips64_pe = gen_mips64_rm7000_pe;
- strcpy(generic_mips64_support.pmu_name,"MIPSRM7000"),
- generic_mips64_support.pme_count = (sizeof(gen_mips64_rm7000_pe)/sizeof(pme_gen_mips64_entry_t));
- generic_mips64_support.pmc_count = 2;
- generic_mips64_support.pmd_count = 2;
- generic_mips64_support.pmu_type = PFMLIB_MIPS_RM7000_PMU;
+ gen_mips64_pe = gen_mips64_rm7000_pe;
+ strcpy(generic_mips64_support.pmu_name,"MIPSRM7000"),
+ generic_mips64_support.pme_count = (sizeof(gen_mips64_rm7000_pe)/sizeof(pme_gen_mips64_entry_t));
+ generic_mips64_support.pmc_count = 2;
+ generic_mips64_support.pmd_count = 2;
+ generic_mips64_support.pmu_type = PFMLIB_MIPS_RM7000_PMU;
}
else if (strstr(buffer,"RM9000"))
{
- gen_mips64_pe = gen_mips64_rm9000_pe;
- strcpy(generic_mips64_support.pmu_name,"MIPSRM9000"),
- generic_mips64_support.pme_count = (sizeof(gen_mips64_rm9000_pe)/sizeof(pme_gen_mips64_entry_t));
- generic_mips64_support.pmc_count = 2;
- generic_mips64_support.pmd_count = 2;
- generic_mips64_support.pmu_type = PFMLIB_MIPS_RM9000_PMU;
+ gen_mips64_pe = gen_mips64_rm9000_pe;
+ strcpy(generic_mips64_support.pmu_name,"MIPSRM9000"),
+ generic_mips64_support.pme_count = (sizeof(gen_mips64_rm9000_pe)/sizeof(pme_gen_mips64_entry_t));
+ generic_mips64_support.pmc_count = 2;
+ generic_mips64_support.pmd_count = 2;
+ generic_mips64_support.pmu_type = PFMLIB_MIPS_RM9000_PMU;
}
else if (strstr(buffer,"SB1"))
{
- gen_mips64_pe = gen_mips64_sb1_pe;
- strcpy(generic_mips64_support.pmu_name,"MIPSSB1"),
- generic_mips64_support.pme_count = (sizeof(gen_mips64_sb1_pe)/sizeof(pme_gen_mips64_entry_t));
- generic_mips64_support.pmc_count = 4;
- generic_mips64_support.pmd_count = 4;
- generic_mips64_support.pmu_type = PFMLIB_MIPS_SB1_PMU;
+ gen_mips64_pe = gen_mips64_sb1_pe;
+ strcpy(generic_mips64_support.pmu_name,"MIPSSB1"),
+ generic_mips64_support.pme_count = (sizeof(gen_mips64_sb1_pe)/sizeof(pme_gen_mips64_entry_t));
+ generic_mips64_support.pmc_count = 4;
+ generic_mips64_support.pmd_count = 4;
+ generic_mips64_support.pmu_type = PFMLIB_MIPS_SB1_PMU;
}
else if (strstr(buffer,"VR5432"))
{
- gen_mips64_pe = gen_mips64_vr5432_pe;
- generic_mips64_support.pme_count = (sizeof(gen_mips64_vr5432_pe)/sizeof(pme_gen_mips64_entry_t));
- strcpy(generic_mips64_support.pmu_name,"MIPSVR5432"),
- generic_mips64_support.pmc_count = 2;
- generic_mips64_support.pmd_count = 2;
- generic_mips64_support.pmu_type = PFMLIB_MIPS_VR5432_PMU;
+ gen_mips64_pe = gen_mips64_vr5432_pe;
+ generic_mips64_support.pme_count = (sizeof(gen_mips64_vr5432_pe)/sizeof(pme_gen_mips64_entry_t));
+ strcpy(generic_mips64_support.pmu_name,"MIPSVR5432"),
+ generic_mips64_support.pmc_count = 2;
+ generic_mips64_support.pmd_count = 2;
+ generic_mips64_support.pmu_type = PFMLIB_MIPS_VR5432_PMU;
}
- else if (strstr(buffer,"MIPS VR5500"))
+ else if (strstr(buffer,"VR5500"))
{
- gen_mips64_pe = gen_mips64_vr5500_pe;
- generic_mips64_support.pme_count = (sizeof(gen_mips64_vr5500_pe)/sizeof(pme_gen_mips64_entry_t));
- strcpy(generic_mips64_support.pmu_name,"MIPSVR5500"),
- generic_mips64_support.pmc_count = 2;
- generic_mips64_support.pmd_count = 2;
- generic_mips64_support.pmu_type = PFMLIB_MIPS_VR5500_PMU;
- }
+ gen_mips64_pe = gen_mips64_vr5500_pe;
+ generic_mips64_support.pme_count = (sizeof(gen_mips64_vr5500_pe)/sizeof(pme_gen_mips64_entry_t));
+ strcpy(generic_mips64_support.pmu_name,"MIPSVR5500"),
+ generic_mips64_support.pmc_count = 2;
+ generic_mips64_support.pmd_count = 2;
+ generic_mips64_support.pmu_type = PFMLIB_MIPS_VR5500_PMU;
+ }
else
- return PFMLIB_ERR_NOTSUPP;
+ return PFMLIB_ERR_NOTSUPP;
+ if (generic_mips64_support.num_cnt == 0)
generic_mips64_support.num_cnt = generic_mips64_support.pmd_count;
+
return PFMLIB_SUCCESS;
}
-static void stuff_regs(pfmlib_event_t *e, int plm, pfmlib_reg_t *pc, pfmlib_reg_t *pd, int cntr, int j)
+static void stuff_regs(pfmlib_event_t *e, int plm, pfmlib_reg_t *pc, pfmlib_reg_t *pd, int cntr, int j, pfmlib_gen_mips64_input_param_t *mod_in)
{
- pfm_gen_mips64_sel_reg_t reg;
- reg.val = 0; /* assume reserved bits are zerooed */
- /* if plm is 0, then assume not specified per-event and use default */
- plm = e[j].plm ? e[j].plm : plm;
- reg.sel_usr = plm & PFM_PLM3 ? 1 : 0;
- reg.sel_os = plm & PFM_PLM0 ? 1 : 0;
- reg.sel_sup = plm & PFM_PLM1 ? 1 : 0;
- reg.sel_exl = plm & PFM_PLM2 ? 1 : 0;
- reg.sel_int = 1; /* force int to 1 */
-
- reg.sel_event_mask = (gen_mips64_pe[e[j].event].pme_code >> (cntr*8)) & 0xff;
- pc[j].reg_num = cntr;
- pc[j].reg_value = reg.val;
- pc[j].reg_addr = cntr*2;
-
- __pfm_vbprintf("[CP0_25_%u(pmc%u)=0x%"PRIx64" event_mask=0x%x usr=%d os=%d sup=%d exl=%d int=1] %s\n",
- pc[j].reg_addr,
- pc[j].reg_num,
- pc[j].reg_value,
- reg.sel_event_mask,
- reg.sel_usr,
- reg.sel_os,
- reg.sel_sup,
- reg.sel_exl,
- gen_mips64_pe[e[j].event].pme_name);
-
- pd[j].reg_num = cntr;
- pd[j].reg_addr = cntr*2 + 1;
-
- __pfm_vbprintf("[CP0_25_%u(pmd%u)]\n",
- pc[j].reg_addr,
- pc[j].reg_num);
+ pfm_gen_mips64_sel_reg_t reg;
+
+ reg.val = 0; /* assume reserved bits are zerooed */
+
+ /* if plm is 0, then assume not specified per-event and use default */
+ plm = e[j].plm ? e[j].plm : plm;
+ reg.sel_usr = plm & PFM_PLM3 ? 1 : 0;
+ reg.sel_os = plm & PFM_PLM0 ? 1 : 0;
+ reg.sel_sup = plm & PFM_PLM1 ? 1 : 0;
+ reg.sel_exl = plm & PFM_PLM2 ? 1 : 0;
+ reg.sel_int = 1; /* force int to 1 */
+
+ reg.sel_event_mask = (gen_mips64_pe[e[j].event].pme_code >> (cntr*8)) & 0xff;
+ pc[j].reg_value = reg.val;
+ pc[j].reg_addr = cntr*2;
+ pc[j].reg_num = cntr;
+
+ __pfm_vbprintf("[CP0_25_%"PRIx64"(pmc%u)=0x%"PRIx64" event_mask=0x%x usr=%d os=%d sup=%d exl=%d int=1] %s\n",
+ pc[j].reg_addr,
+ pc[j].reg_num,
+ pc[j].reg_value,
+ reg.sel_event_mask,
+ reg.sel_usr,
+ reg.sel_os,
+ reg.sel_sup,
+ reg.sel_exl,
+ gen_mips64_pe[e[j].event].pme_name);
+
+ pd[j].reg_num = cntr;
+ pd[j].reg_addr = cntr*2 + 1;
+
+ __pfm_vbprintf("[CP0_25_%u(pmd%u)]\n",
+ pc[j].reg_addr,
+ pc[j].reg_num);
}
/*
* Automatically dispatch events to corresponding counters following constraints.
@@ -246,9 +250,9 @@ pfm_gen_mips64_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_gen_mips64_in
if (cnt > generic_mips64_support.pmc_count) return PFMLIB_ERR_TOOMANY;
if (PFMLIB_DEBUG()) {
- for (j=0; j < cnt; j++) {
- DPRINT(("ev[%d]=%s, counters=0x%x\n", j, gen_mips64_pe[e[j].event].pme_name,gen_mips64_pe[e[j].event].pme_counters));
- }
+ for (j=0; j < cnt; j++) {
+ DPRINT("ev[%d]=%s, counters=0x%x\n", j, gen_mips64_pe[e[j].event].pme_name,gen_mips64_pe[e[j].event].pme_counters);
+ }
}
/* Do rank based allocation, counters that live on 1 reg
@@ -260,24 +264,24 @@ pfm_gen_mips64_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_gen_mips64_in
unsigned int cntr, avail;
if (pfmlib_popcnt(gen_mips64_pe[e[j].event].pme_counters) == i)
{
- /* These counters can be used for this event */
- avail = ~used & gen_mips64_pe[e[j].event].pme_counters;
- DPRINT(("%d: Counters available %x\n",i,avail));
- if (avail == 0x0)
- return PFMLIB_ERR_NOASSIGN;
-
- /* Pick one, mark as used*/
- cntr = ffs(avail) - 1;
- DPRINT(("%d: Chose counter %d\n",i,cntr));
-
- /* Update registers */
- stuff_regs(e,inp->pfp_dfl_plm,pc,pd,cntr,j);
-
- used |= (1 << cntr);
- DPRINT(("%d: Used counters %x\n",i, used));
- }
- }
- }
+ /* These counters can be used for this event */
+ avail = ~used & gen_mips64_pe[e[j].event].pme_counters;
+ DPRINT("Rank %d: Counters available 0x%x\n",i,avail);
+ if (avail == 0x0)
+ return PFMLIB_ERR_NOASSIGN;
+
+ /* Pick one, mark as used*/
+ cntr = ffs(avail) - 1;
+ DPRINT("Rank %d: Chose counter %d\n",i,cntr);
+
+ /* Update registers */
+ stuff_regs(e,inp->pfp_dfl_plm,pc,pd,cntr,j,mod_in);
+
+ used |= (1 << cntr);
+ DPRINT("%d: Used counters 0x%x\n",i, used);
+ }
+ }
+ }
/* number of evtsel registers programmed */
outp->pfp_pmc_count = cnt;
@@ -290,13 +294,7 @@ static int
pfm_gen_mips64_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_output_param_t *outp, void *model_out)
{
pfmlib_gen_mips64_input_param_t *mod_in = (pfmlib_gen_mips64_input_param_t *)model_in;
- /* All PLMS are valid */
-#if 0
- if (inp->pfp_dfl_plm & (PFM_PLM0|PFM_PLM1|PFM_PLM2|PFM_PLM3)) {
- DPRINT(("invalid plm=%x\n", inp->pfp_dfl_plm));
- return PFMLIB_ERR_INVAL;
- }
-#endif
+
return pfm_gen_mips64_dispatch_counters(inp, mod_in, outp);
}
@@ -307,50 +305,41 @@ pfm_gen_mips64_get_event_code(unsigned int i, unsigned int cnt, int *code)
/* check validity of counter index */
if (cnt != PFMLIB_CNT_FIRST) {
- if (cnt < 0 || cnt >= generic_mips64_support.pmc_count)
+ if (cnt < 0 || cnt >= generic_mips64_support.pmc_count)
return PFMLIB_ERR_INVAL; }
else {
- cnt = ffs(gen_mips64_pe[i].pme_counters)-1;
- if (cnt == -1)
- return(PFMLIB_ERR_INVAL);
- }
-
- /* if cnt == 1, shift right by 0, if cnt == 2, shift right by 4 */
+ cnt = ffs(gen_mips64_pe[i].pme_counters)-1;
+ if (cnt == -1)
+ return(PFMLIB_ERR_INVAL);
+ }
+
+ /* if cnt == 1, shift right by 0, if cnt == 2, shift right by 8 */
/* Works on both 5k anf 20K */
if (gen_mips64_pe[i].pme_counters & (1<< cnt))
- *code = 0xff & (gen_mips64_pe[i].pme_code >> (cnt*8));
+ *code = 0xff & (gen_mips64_pe[i].pme_code >> (cnt*8));
else
- return PFMLIB_ERR_INVAL;
+ return PFMLIB_ERR_INVAL;
return PFMLIB_SUCCESS;
}
-/*
- * This function is accessible directly to the user
- */
-int
-pfm_gen_mips64_get_event_umask(unsigned int i, unsigned long *umask)
-{
- extern pfm_pmu_support_t generic_mips64_support;
- if (i >= generic_mips64_support.pme_count || umask == NULL) return PFMLIB_ERR_INVAL;
- *umask = 0; //evt_umask(i);
- return PFMLIB_SUCCESS;
-}
-
static void
pfm_gen_mips64_get_event_counters(unsigned int j, pfmlib_regmask_t *counters)
{
- unsigned int i;
extern pfm_pmu_support_t generic_mips64_support;
+ unsigned int tmp;
memset(counters, 0, sizeof(*counters));
-
- for(i=0; i < generic_mips64_support.pmc_count; i++) {
- pfm_regmask_set(counters, i);
+ tmp = gen_mips64_pe[j].pme_counters;
+
+ while (tmp)
+ {
+ int t = ffs(tmp) - 1;
+ pfm_regmask_set(counters, t);
+ tmp = tmp ^ (1 << t);
+ }
}
-}
-
static void
pfm_gen_mips64_get_impl_perfsel(pfmlib_regmask_t *impl_pmcs)
@@ -378,8 +367,8 @@ pfm_gen_mips64_get_impl_counters(pfmlib_regmask_t *impl_counters)
unsigned int i = 0;
extern pfm_pmu_support_t generic_mips64_support;
- /* counting pmds are contiguous */
- for(i=0; i < generic_mips64_support.pmc_count; i++) pfm_regmask_set(impl_counters, i);
+ for(i=0; i < generic_mips64_support.pmc_count; i++)
+ pfm_regmask_set(impl_counters, i);
}
static void
@@ -410,47 +399,48 @@ pfm_gen_mips64_get_event_description(unsigned int ev, char **str)
static int
pfm_gen_mips64_get_cycle_event(pfmlib_event_t *e)
{
- return pfm_find_full_event("CYCLES",e);
+ return pfm_find_full_event("CYCLES",e);
}
static int
pfm_gen_mips64_get_inst_retired(pfmlib_event_t *e)
{
- if (pfm_current == NULL)
- return(PFMLIB_ERR_NOINIT);
+ if (pfm_current == NULL)
+ return(PFMLIB_ERR_NOINIT);
switch (pfm_current->pmu_type)
{
- case PFMLIB_MIPS_20KC_PMU:
- return pfm_find_full_event("INSNS_COMPLETED",e);
- case PFMLIB_MIPS_24K_PMU:
- return pfm_find_full_event("INSTRUCTIONS",e);
- case PFMLIB_MIPS_25KF_PMU:
- return pfm_find_full_event("INSNS_COMPLETE",e);
- case PFMLIB_MIPS_34K_PMU:
- return pfm_find_full_event("INSTRUCTIONS",e);
- case PFMLIB_MIPS_5KC_PMU:
- return pfm_find_full_event("INSNS_EXECD",e);
- case PFMLIB_MIPS_R10000_PMU:
- case PFMLIB_MIPS_R12000_PMU:
- return pfm_find_full_event("INSTRUCTIONS_GRADUATED",e);
- case PFMLIB_MIPS_RM7000_PMU:
- case PFMLIB_MIPS_RM9000_PMU:
- return pfm_find_full_event("INSTRUCTIONS_ISSUED",e);
- case PFMLIB_MIPS_VR5432_PMU:
- case PFMLIB_MIPS_VR5500_PMU:
- return pfm_find_full_event("INSTRUCTIONS_EXECUTED",e);
- case PFMLIB_MIPS_SB1_PMU:
- return pfm_find_full_event("INSN_SURVIVED_STAGE7",e);
- case PFMLIB_MIPS_74K_PMU:
- default:
- return(PFMLIB_ERR_NOTFOUND);
- }
+ case PFMLIB_MIPS_20KC_PMU:
+ return pfm_find_full_event("INSNS_COMPLETED",e);
+ case PFMLIB_MIPS_24K_PMU:
+ return pfm_find_full_event("INSTRUCTIONS",e);
+ case PFMLIB_MIPS_25KF_PMU:
+ return pfm_find_full_event("INSNS_COMPLETE",e);
+ case PFMLIB_MIPS_34K_PMU:
+ return pfm_find_full_event("INSTRUCTIONS",e);
+ case PFMLIB_MIPS_5KC_PMU:
+ return pfm_find_full_event("INSNS_EXECD",e);
+ case PFMLIB_MIPS_R10000_PMU:
+ case PFMLIB_MIPS_R12000_PMU:
+ return pfm_find_full_event("INSTRUCTIONS_GRADUATED",e);
+ case PFMLIB_MIPS_RM7000_PMU:
+ case PFMLIB_MIPS_RM9000_PMU:
+ return pfm_find_full_event("INSTRUCTIONS_ISSUED",e);
+ case PFMLIB_MIPS_VR5432_PMU:
+ case PFMLIB_MIPS_VR5500_PMU:
+ return pfm_find_full_event("INSTRUCTIONS_EXECUTED",e);
+ case PFMLIB_MIPS_SB1_PMU:
+ return pfm_find_full_event("INSN_SURVIVED_STAGE7",e);
+ default:
+ return(PFMLIB_ERR_NOTFOUND);
+ }
}
+/* SiCortex specific functions */
+
pfm_pmu_support_t generic_mips64_support = {
.pmu_name = NULL,
- .pmu_type = 0,
+ .pmu_type = PFMLIB_UNKNOWN_PMU,
.pme_count = 0,
.pmc_count = 0,
.pmd_count = 0,
@@ -469,4 +459,3 @@ pfm_pmu_support_t generic_mips64_support = {
.get_cycle_event = pfm_gen_mips64_get_cycle_event,
.get_inst_retired_event = pfm_gen_mips64_get_inst_retired
};
-
diff --git a/src/libpfm-3.y/lib/pfmlib_gen_powerpc.c b/src/libpfm-3.y/lib/pfmlib_gen_powerpc.c
index 0d88c31de10b4a2081131ea99af2c713a5ec8532..db5c3f626453f422875b88888b1f2b6785b5389c 100644
--- a/src/libpfm-3.y/lib/pfmlib_gen_powerpc.c
+++ b/src/libpfm-3.y/lib/pfmlib_gen_powerpc.c
@@ -25,7 +25,9 @@
* Support for libpfm for the PowerPC970, POWER4,4+,5,5+,6 processors.
*/
-#define _GNU_SOURCE
+#ifndef _GNU_SOURCE
+ #define _GNU_SOURCE /* for getline */
+#endif
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
@@ -37,12 +39,14 @@
#include "pfmlib_priv.h"
+#include "pfmlib_power_priv.h"
#include "pfmlib_ppc970_priv.h"
#include "pfmlib_ppc970mp_priv.h"
#include "pfmlib_power4_priv.h"
#include "pfmlib_power5_priv.h"
#include "pfmlib_power5+_priv.h"
#include "pfmlib_power6_priv.h"
+#include "pfmlib_power7_priv.h"
#include "ppc970_events.h"
#include "ppc970mp_events.h"
@@ -50,178 +54,80 @@
#include "power5_events.h"
#include "power5+_events.h"
#include "power6_events.h"
+#include "power7_events.h"
+
+#define FIRST_POWER_PMU PFMLIB_PPC970_PMU
+
+static const int num_group_vec[] = {
+ [PFMLIB_PPC970_PMU - FIRST_POWER_PMU] = PPC970_NUM_GROUP_VEC,
+ [PFMLIB_PPC970MP_PMU - FIRST_POWER_PMU] = PPC970MP_NUM_GROUP_VEC,
+ [PFMLIB_POWER4_PMU - FIRST_POWER_PMU] = POWER4_NUM_GROUP_VEC,
+ [PFMLIB_POWER5_PMU - FIRST_POWER_PMU] = POWER5_NUM_GROUP_VEC,
+ [PFMLIB_POWER5p_PMU - FIRST_POWER_PMU] = POWER5p_NUM_GROUP_VEC,
+ [PFMLIB_POWER6_PMU - FIRST_POWER_PMU] = POWER6_NUM_GROUP_VEC,
+ [PFMLIB_POWER7_PMU - FIRST_POWER_PMU] = POWER7_NUM_GROUP_VEC
+};
+
+static const int event_count[] = {
+ [PFMLIB_PPC970_PMU - FIRST_POWER_PMU] = PPC970_PME_EVENT_COUNT,
+ [PFMLIB_PPC970MP_PMU - FIRST_POWER_PMU] = PPC970MP_PME_EVENT_COUNT,
+ [PFMLIB_POWER5_PMU - FIRST_POWER_PMU] = POWER5_PME_EVENT_COUNT,
+ [PFMLIB_POWER5p_PMU - FIRST_POWER_PMU] = POWER5p_PME_EVENT_COUNT,
+ [PFMLIB_POWER6_PMU - FIRST_POWER_PMU] = POWER6_PME_EVENT_COUNT,
+ [PFMLIB_POWER7_PMU - FIRST_POWER_PMU] = POWER7_PME_EVENT_COUNT
+};
+
+unsigned *pmd_priv_vec;
+
+static unsigned long long mmcr0_fc5_6_mask;
+static unsigned long long *mmcr0_counter_mask;
+static unsigned long long *mmcr1_counter_mask;
+static unsigned long long *mmcr0_counter_off_val;
+static unsigned long long *mmcr1_counter_off_val;
-/* Add structures here to define the PMD and PMC mappings. */
+static const pme_power_entry_t *pe;
+static const pmg_power_group_t *groups;
-static int get_num_event_counters() {
+static inline int get_num_event_counters() {
return gen_powerpc_support.pmd_count;
}
-static int get_num_control_regs() {
+static inline int get_num_control_regs() {
return gen_powerpc_support.pmc_count;
}
-static int get_num_group_vec() {
- switch (gen_powerpc_support.pmu_type) {
- case PFMLIB_PPC970_PMU:
- return PPC970_NUM_GROUP_VEC;
- case PFMLIB_PPC970MP_PMU:
- return PPC970MP_NUM_GROUP_VEC;
- case PFMLIB_POWER4_PMU:
- return POWER4_NUM_GROUP_VEC;
- case PFMLIB_POWER5_PMU:
- return POWER5_NUM_GROUP_VEC;
- case PFMLIB_POWER5p_PMU:
- return POWER5p_NUM_GROUP_VEC;
- case PFMLIB_POWER6_PMU:
- return POWER6_NUM_GROUP_VEC;
- }
- return -1;
+static inline const unsigned long long *get_group_vector(int event) {
+ return pe[event].pme_group_vector;
}
-static unsigned long long *get_group_vector(int event) {
- switch (gen_powerpc_support.pmu_type) {
- case PFMLIB_PPC970_PMU:
- return &ppc970_pe[event].pme_group_vector[0];
- case PFMLIB_PPC970MP_PMU:
- return &ppc970mp_pe[event].pme_group_vector[0];
- case PFMLIB_POWER4_PMU:
- return &power4_pe[event].pme_group_vector[0];
- case PFMLIB_POWER5_PMU:
- return &power5_pe[event].pme_group_vector[0];
- case PFMLIB_POWER5p_PMU:
- return &power5p_pe[event].pme_group_vector[0];
- case PFMLIB_POWER6_PMU:
- return &power6_pe[event].pme_group_vector[0];
- }
- return (unsigned long long *)-1;
+static inline int get_event_id(int event, int counter) {
+ return pe[event].pme_event_ids[counter];
}
-static int get_event_id(int event, int counter) {
- switch (gen_powerpc_support.pmu_type) {
- case PFMLIB_PPC970_PMU:
- return ppc970_pe[event].pme_event_ids[counter];
- case PFMLIB_PPC970MP_PMU:
- return ppc970mp_pe[event].pme_event_ids[counter];
- case PFMLIB_POWER4_PMU:
- return power4_pe[event].pme_event_ids[counter];
- case PFMLIB_POWER5_PMU:
- return power5_pe[event].pme_event_ids[counter];
- case PFMLIB_POWER5p_PMU:
- return power5p_pe[event].pme_event_ids[counter];
- case PFMLIB_POWER6_PMU:
- return power6_pe[event].pme_event_ids[counter];
- }
- return -1;
+static inline char *get_event_name(int event) {
+ return pe[event].pme_name;
}
-static char *get_event_name(int event) {
- switch (gen_powerpc_support.pmu_type) {
- case PFMLIB_PPC970_PMU:
- return ppc970_pe[event].pme_name;
- case PFMLIB_PPC970MP_PMU:
- return ppc970mp_pe[event].pme_name;
- case PFMLIB_POWER4_PMU:
- return power4_pe[event].pme_name;
- case PFMLIB_POWER5_PMU:
- return power5_pe[event].pme_name;
- case PFMLIB_POWER5p_PMU:
- return power5p_pe[event].pme_name;
- case PFMLIB_POWER6_PMU:
- return power6_pe[event].pme_name;
- }
- return (char *)-1;
+static inline char *get_long_desc(int event) {
+ return pe[event].pme_long_desc;
}
-static char *get_long_desc(int event) {
- switch (gen_powerpc_support.pmu_type) {
- case PFMLIB_PPC970_PMU:
- return ppc970_pe[event].pme_long_desc;
- case PFMLIB_PPC970MP_PMU:
- return ppc970mp_pe[event].pme_long_desc;
- case PFMLIB_POWER4_PMU:
- return power4_pe[event].pme_long_desc;
- case PFMLIB_POWER5_PMU:
- return power5_pe[event].pme_long_desc;
- case PFMLIB_POWER5p_PMU:
- return power5p_pe[event].pme_long_desc;
- case PFMLIB_POWER6_PMU:
- return power6_pe[event].pme_long_desc;
- }
- return (char *)-1;
+static inline int get_group_event_id(int group, int counter) {
+ return groups[group].pmg_event_ids[counter];
}
-static int get_group_event_id(int group, int counter) {
- switch (gen_powerpc_support.pmu_type) {
- case PFMLIB_PPC970_PMU:
- return ppc970_groups[group].pmg_event_ids[counter];
- case PFMLIB_PPC970MP_PMU:
- return ppc970mp_groups[group].pmg_event_ids[counter];
- case PFMLIB_POWER4_PMU:
- return power4_groups[group].pmg_event_ids[counter];
- case PFMLIB_POWER5_PMU:
- return power5_groups[group].pmg_event_ids[counter];
- case PFMLIB_POWER5p_PMU:
- return power5p_groups[group].pmg_event_ids[counter];
- case PFMLIB_POWER6_PMU:
- return power6_groups[group].pmg_event_ids[counter];
- }
- return -1;
+static inline unsigned long long get_mmcr0(int group) {
+ return groups[group].pmg_mmcr0;
}
-static unsigned long long get_mmcr0(int group) {
- switch (gen_powerpc_support.pmu_type) {
- case PFMLIB_PPC970_PMU:
- return ppc970_groups[group].pmg_mmcr0;
- case PFMLIB_PPC970MP_PMU:
- return ppc970mp_groups[group].pmg_mmcr0;
- case PFMLIB_POWER4_PMU:
- return power4_groups[group].pmg_mmcr0;
- case PFMLIB_POWER5_PMU:
- return power5_groups[group].pmg_mmcr0;
- case PFMLIB_POWER5p_PMU:
- return power5p_groups[group].pmg_mmcr0;
- case PFMLIB_POWER6_PMU:
- return power6_groups[group].pmg_mmcr0;
- }
- return -1;
+static inline unsigned long long get_mmcr1(int group) {
+ return groups[group].pmg_mmcr1;
}
-static unsigned long long get_mmcr1(int group) {
- switch (gen_powerpc_support.pmu_type) {
- case PFMLIB_PPC970_PMU:
- return ppc970_groups[group].pmg_mmcr1;
- case PFMLIB_PPC970MP_PMU:
- return ppc970mp_groups[group].pmg_mmcr1;
- case PFMLIB_POWER4_PMU:
- return power4_groups[group].pmg_mmcr1;
- case PFMLIB_POWER5_PMU:
- return power5_groups[group].pmg_mmcr1;
- case PFMLIB_POWER5p_PMU:
- return power5p_groups[group].pmg_mmcr1;
- case PFMLIB_POWER6_PMU:
- return power6_groups[group].pmg_mmcr1;
- }
- return -1;
-}
-
-static unsigned long long get_mmcra(int group) {
- switch (gen_powerpc_support.pmu_type) {
- case PFMLIB_PPC970_PMU:
- return ppc970_groups[group].pmg_mmcra;
- case PFMLIB_PPC970MP_PMU:
- return ppc970mp_groups[group].pmg_mmcra;
- case PFMLIB_POWER4_PMU:
- return power4_groups[group].pmg_mmcra;
- case PFMLIB_POWER5_PMU:
- return power5_groups[group].pmg_mmcra;
- case PFMLIB_POWER5p_PMU:
- return power5p_groups[group].pmg_mmcra;
- case PFMLIB_POWER6_PMU:
- return power6_groups[group].pmg_mmcra;
- }
- return -1;
+static inline unsigned long long get_mmcra(int group) {
+ return groups[group].pmg_mmcra;
}
+
/**
* pfm_gen_powerpc_get_event_code
@@ -233,8 +139,11 @@ static int pfm_gen_powerpc_get_event_code(unsigned int event,
unsigned int pmd,
int *code)
{
- *code = get_event_id(event, pmd);
- return 0;
+ if (event < event_count[gen_powerpc_support.pmu_type - FIRST_POWER_PMU]) {
+ *code = pe[event].pme_code;
+ return PFMLIB_SUCCESS;
+ } else
+ return PFMLIB_ERR_INVAL;
}
/**
@@ -292,11 +201,11 @@ static void remove_group(unsigned long long *group_vec, int group)
group_vec[group / 64] &= ~(1ULL << (group % 64));
}
-static void intersect_groups(unsigned long long *result, unsigned long long *operand)
+static void intersect_groups(unsigned long long *result, const unsigned long long *operand)
{
int i;
- for (i = 0; i < get_num_group_vec(); i++) {
+ for (i = 0; i < num_group_vec[gen_powerpc_support.pmu_type - FIRST_POWER_PMU]; i++) {
result[i] &= operand[i];
}
}
@@ -305,7 +214,7 @@ static int first_group(unsigned long long *group_vec)
{
int i, bit;
- for (i = 0; i < get_num_group_vec(); i++) {
+ for (i = 0; i < num_group_vec[gen_powerpc_support.pmu_type - FIRST_POWER_PMU]; i++) {
bit = ffsll(group_vec[i]);
if (bit) {
return (bit - 1) + (i * 64);
@@ -367,7 +276,49 @@ static unsigned long long power4_mmcr1_counter_mask[POWER4_NUM_EVENT_COUNTERS] =
0x1fUL << (63 - 61) /* PMC8 */
};
-/* These masks are used on POWER5,5+,5++,6 */
+static unsigned long long power4_mmcr0_counter_off_val[POWER4_NUM_EVENT_COUNTERS] = {
+ 0, /* PMC1 */
+ 0, /* PMC2 */
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0
+};
+static unsigned long long power4_mmcr1_counter_off_val[POWER4_NUM_EVENT_COUNTERS] = {
+ 0,
+ 0,
+ 0, /* PMC3 */
+ 0, /* PMC4 */
+ 0, /* PMC5 */
+ 0, /* PMC6 */
+ 0, /* PMC7 */
+ 0 /* PMC8 */
+};
+
+static unsigned long long ppc970_mmcr0_counter_off_val[POWER4_NUM_EVENT_COUNTERS] = {
+ 0x8UL << (63 - 55), /* PMC1 */
+ 0x8UL << (63 - 62), /* PMC2 */
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0
+};
+static unsigned long long ppc970_mmcr1_counter_off_val[POWER4_NUM_EVENT_COUNTERS] = {
+ 0,
+ 0,
+ 0x8UL << (63 - 36), /* PMC3 */
+ 0x8UL << (63 - 41), /* PMC4 */
+ 0x8UL << (63 - 46), /* PMC5 */
+ 0x8UL << (63 - 51), /* PMC6 */
+ 0x8UL << (63 - 56), /* PMC7 */
+ 0x8UL << (63 - 61) /* PMC8 */
+};
+
+/* These masks are used on POWER5,5+,5++,6,7 */
static unsigned long long power5_mmcr0_counter_mask[POWER5_NUM_EVENT_COUNTERS] = {
0,
0,
@@ -381,16 +332,28 @@ static unsigned long long power5_mmcr1_counter_mask[POWER5_NUM_EVENT_COUNTERS] =
0xffUL << (63 - 47), /* PMC2 */
0xffUL << (63 - 55), /* PMC3 */
0xffUL << (63 - 63), /* PMC4 */
- 0,
- 0
+ 0,
+ 0
};
+static unsigned long long power5_mmcr0_counter_off_val[POWER5_NUM_EVENT_COUNTERS] = {
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0
+};
-unsigned *pmd_priv_vec;
+static unsigned long long power5_mmcr1_counter_off_val[POWER5_NUM_EVENT_COUNTERS] = {
+ 0, /* PMC1 */
+ 0, /* PMC2 */
+ 0, /* PMC3 */
+ 0, /* PMC4 */
+ 0,
+ 0
+};
-static unsigned long long mmcr0_fc5_6_mask;
-static unsigned long long *mmcr0_counter_mask;
-static unsigned long long *mmcr1_counter_mask;
/**
* pfm_gen_powerpc_dispatch_events
@@ -401,6 +364,7 @@ static unsigned long long *mmcr1_counter_mask;
static int pfm_gen_powerpc_dispatch_events(pfmlib_input_param_t *input,
void *model_input,
pfmlib_output_param_t *output,
+
void *model_output)
{
/* model_input and model_output are unused on POWER */
@@ -408,13 +372,15 @@ static int pfm_gen_powerpc_dispatch_events(pfmlib_input_param_t *input,
int i, j, group;
int counters_used = 0;
unsigned long long mmcr0_val, mmcr1_val;
- unsigned long long *group_vector = malloc(sizeof(unsigned long long) * get_num_group_vec());
+ unsigned long long group_vector[num_group_vec[gen_powerpc_support.pmu_type - FIRST_POWER_PMU]];
+ unsigned int plm;
+
+ plm = (input->pfp_events[0].plm != 0) ? input->pfp_events[0].plm : input->pfp_dfl_plm;
/*
* Verify that all of the privilege level masks are identical, as
* we cannot have mixed levels on POWER
*/
- unsigned int plm = (input->pfp_events[0].plm != 0) ? input->pfp_events[0].plm : input->pfp_dfl_plm;
for (i = 1; i < input->pfp_event_count; i++) {
if (input->pfp_events[i].plm == 0) {
@@ -428,10 +394,12 @@ static int pfm_gen_powerpc_dispatch_events(pfmlib_input_param_t *input,
}
/* start by setting all of the groups as available */
- memset(group_vector, 0xff, sizeof(unsigned long long) * get_num_group_vec());
+ memset(group_vector, 0xff, sizeof(unsigned long long) * num_group_vec[gen_powerpc_support.pmu_type - FIRST_POWER_PMU]);
for (i = 0; i < input->pfp_event_count; i++) {
+ mmcr0_val |= mmcr0_counter_off_val[i];
intersect_groups(group_vector, get_group_vector(input->pfp_events[i].event));
+ mmcr1_val |= mmcr1_counter_off_val[i];
}
group = first_group(group_vector);
while (group != -1) {
@@ -462,6 +430,7 @@ static int pfm_gen_powerpc_dispatch_events(pfmlib_input_param_t *input,
output->pfp_pmds[i].reg_num = j + 1;
output->pfp_pmds[i].reg_reserved1 = 0;
output->pfp_pmd_count = i + 1;
+
/* Find the next counter */
break;
}
@@ -477,10 +446,10 @@ static int pfm_gen_powerpc_dispatch_events(pfmlib_input_param_t *input,
break;
try_next_group: ;
}
- if (group == -1) {
+ if (group == -1)
/* We did not find a group that meets the constraints */
return PFMLIB_ERR_NOASSIGN;
- }
+
/* We now have a group that meets the constraints */
mmcr0_val = get_mmcr0(group);
@@ -488,11 +457,13 @@ try_next_group: ;
for (i = 0; i < get_num_event_counters(); i++) {
if (! (counters_used & (1 << i))) {
/*
- * This counter is not used, so zero out that
- * selector
+ * This counter is not used, so set that
+ * selector to its off value.
*/
mmcr0_val &= ~mmcr0_counter_mask[i];
+ mmcr0_val |= mmcr0_counter_off_val[i];
mmcr1_val &= ~mmcr1_counter_mask[i];
+ mmcr1_val |= mmcr1_counter_off_val[i];
}
}
/*
@@ -548,7 +519,7 @@ try_next_group: ;
/* We always use the same number of control regs */
output->pfp_pmc_count = get_num_control_regs();
-
+
return PFMLIB_SUCCESS;
}
@@ -570,7 +541,7 @@ try_next_group: ;
static int pfm_gen_powerpc_pmu_detect(void)
{
if (__is_processor(PV_970) || __is_processor(PV_970FX) || __is_processor(PV_970GX)) {
- gen_powerpc_support.pmu_type = PFMLIB_POWER4_PMU;
+ gen_powerpc_support.pmu_type = PFMLIB_PPC970_PMU;
gen_powerpc_support.pmu_name = "PPC970";
gen_powerpc_support.pme_count = PPC970_PME_EVENT_COUNT;
gen_powerpc_support.pmd_count = PPC970_NUM_EVENT_COUNTERS;
@@ -579,7 +550,11 @@ static int pfm_gen_powerpc_pmu_detect(void)
mmcr0_fc5_6_mask = 0;
mmcr0_counter_mask = power4_mmcr0_counter_mask;
mmcr1_counter_mask = power4_mmcr1_counter_mask;
+ mmcr0_counter_off_val = ppc970_mmcr0_counter_off_val;
+ mmcr1_counter_off_val = ppc970_mmcr1_counter_off_val;
pmd_priv_vec = gq_pmd_priv_vec;
+ pe = ppc970_pe;
+ groups = ppc970_groups;
return PFMLIB_SUCCESS;
}
if (__is_processor(PV_970MP)) {
@@ -592,11 +567,15 @@ static int pfm_gen_powerpc_pmu_detect(void)
mmcr0_fc5_6_mask = 0;
mmcr0_counter_mask = power4_mmcr0_counter_mask;
mmcr1_counter_mask = power4_mmcr1_counter_mask;
+ mmcr0_counter_off_val = ppc970_mmcr0_counter_off_val;
+ mmcr1_counter_off_val = ppc970_mmcr1_counter_off_val;
pmd_priv_vec = gq_pmd_priv_vec;
+ pe = ppc970mp_pe;
+ groups = ppc970mp_groups;
return PFMLIB_SUCCESS;
}
if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p)) {
- gen_powerpc_support.pmu_type = PFMLIB_POWER4_PMU;
+ gen_powerpc_support.pmu_type = PFMLIB_PPC970_PMU;
gen_powerpc_support.pmu_name = "POWER4";
gen_powerpc_support.pme_count = POWER4_PME_EVENT_COUNT;
gen_powerpc_support.pmd_count = POWER4_NUM_EVENT_COUNTERS;
@@ -605,7 +584,13 @@ static int pfm_gen_powerpc_pmu_detect(void)
mmcr0_fc5_6_mask = 0;
mmcr0_counter_mask = power4_mmcr0_counter_mask;
mmcr1_counter_mask = power4_mmcr1_counter_mask;
+ mmcr0_counter_off_val = ppc970_mmcr0_counter_off_val;
+ mmcr1_counter_off_val = ppc970_mmcr1_counter_off_val;
+ mmcr0_counter_off_val = power4_mmcr0_counter_off_val;
+ mmcr1_counter_off_val = power4_mmcr1_counter_off_val;
pmd_priv_vec = gq_pmd_priv_vec;
+ pe = power4_pe;
+ groups = power4_groups;
return PFMLIB_SUCCESS;
}
if (__is_processor(PV_POWER5)) {
@@ -616,9 +601,15 @@ static int pfm_gen_powerpc_pmu_detect(void)
gen_powerpc_support.pmc_count = POWER5_NUM_CONTROL_REGS;
gen_powerpc_support.num_cnt = POWER5_NUM_EVENT_COUNTERS;
mmcr0_fc5_6_mask = MMCR0_FC5_6;
+ mmcr0_counter_off_val = ppc970_mmcr0_counter_off_val;
+ mmcr1_counter_off_val = ppc970_mmcr1_counter_off_val;
mmcr0_counter_mask = power5_mmcr0_counter_mask;
mmcr1_counter_mask = power5_mmcr1_counter_mask;
+ mmcr0_counter_off_val = power5_mmcr0_counter_off_val;
+ mmcr1_counter_off_val = power5_mmcr1_counter_off_val;
pmd_priv_vec = gr_pmd_priv_vec;
+ pe = power5_pe;
+ groups = power5_groups;
return PFMLIB_SUCCESS;
}
if (__is_processor(PV_POWER5p)) {
@@ -627,9 +618,13 @@ static int pfm_gen_powerpc_pmu_detect(void)
gen_powerpc_support.pme_count = POWER5p_PME_EVENT_COUNT;
gen_powerpc_support.pmd_count = POWER5p_NUM_EVENT_COUNTERS;
gen_powerpc_support.pmc_count = POWER5p_NUM_CONTROL_REGS;
+ mmcr0_counter_off_val = power4_mmcr0_counter_off_val;
+ mmcr1_counter_off_val = power4_mmcr1_counter_off_val;
gen_powerpc_support.num_cnt = POWER5p_NUM_EVENT_COUNTERS;
mmcr0_counter_mask = power5_mmcr0_counter_mask;
mmcr1_counter_mask = power5_mmcr1_counter_mask;
+ mmcr0_counter_off_val = power5_mmcr0_counter_off_val;
+ mmcr1_counter_off_val = power5_mmcr1_counter_off_val;
if (PVR_VER(mfspr(SPRN_PVR)) >= 0x300) {
/* this is a newer, GS model POWER5+ */
mmcr0_fc5_6_mask = 0;
@@ -638,6 +633,10 @@ static int pfm_gen_powerpc_pmu_detect(void)
mmcr0_fc5_6_mask = MMCR0_FC5_6;
pmd_priv_vec = gr_pmd_priv_vec;
}
+ mmcr0_counter_off_val = power5_mmcr0_counter_off_val;
+ mmcr1_counter_off_val = power5_mmcr1_counter_off_val;
+ pe = power5p_pe;
+ groups = power5p_groups;
return PFMLIB_SUCCESS;
}
if (__is_processor(PV_POWER6)) {
@@ -650,9 +649,35 @@ static int pfm_gen_powerpc_pmu_detect(void)
mmcr0_fc5_6_mask = 0;
mmcr0_counter_mask = power5_mmcr0_counter_mask;
mmcr1_counter_mask = power5_mmcr1_counter_mask;
+ mmcr0_counter_off_val = power5_mmcr0_counter_off_val;
+ mmcr1_counter_off_val = power5_mmcr1_counter_off_val;
+ mmcr0_counter_off_val = power5_mmcr0_counter_off_val;
+ mmcr1_counter_off_val = power5_mmcr1_counter_off_val;
pmd_priv_vec = gs_pmd_priv_vec;
+ pe = power6_pe;
+ groups = power6_groups;
return PFMLIB_SUCCESS;
}
+ if (__is_processor(PV_POWER7)) {
+ gen_powerpc_support.pmu_type = PFMLIB_POWER7_PMU;
+ gen_powerpc_support.pmu_name = "POWER7";
+ gen_powerpc_support.pme_count = POWER7_PME_EVENT_COUNT;
+ gen_powerpc_support.pmd_count = POWER7_NUM_EVENT_COUNTERS;
+ gen_powerpc_support.pmc_count = POWER7_NUM_CONTROL_REGS;
+ gen_powerpc_support.num_cnt = POWER7_NUM_EVENT_COUNTERS;
+ mmcr0_fc5_6_mask = 0;
+ mmcr0_counter_mask = power5_mmcr0_counter_mask;
+ mmcr1_counter_mask = power5_mmcr1_counter_mask;
+ mmcr0_counter_off_val = power5_mmcr0_counter_off_val;
+ mmcr1_counter_off_val = power5_mmcr1_counter_off_val;
+ mmcr0_counter_off_val = power5_mmcr0_counter_off_val;
+ mmcr1_counter_off_val = power5_mmcr1_counter_off_val;
+ pmd_priv_vec = gr_pmd_priv_vec;
+ pe = power7_pe;
+ groups = power7_groups;
+ return PFMLIB_SUCCESS;
+ }
+
return PFMLIB_ERR_NOTSUPP;
}
@@ -670,6 +695,7 @@ static void pfm_gen_powerpc_get_impl_pmcs(pfmlib_regmask_t *impl_pmcs)
/**
* pfm_gen_powerpc_get_impl_pmds
*
+
* Set the appropriate bit in the impl_pmcs bitmask for each PMD that's
* available.
**/
@@ -753,6 +779,9 @@ pfm_gen_powerpc_get_cycle_event(pfmlib_event_t *e)
case PFMLIB_POWER6_PMU:
e->event = POWER6_PME_PM_RUN_CYC;
break;
+ case PFMLIB_POWER7_PMU:
+ e->event = POWER7_PME_PM_RUN_CYC;
+ break;
default:
/* perhaps gen_powerpc_suport.pmu_type wasn't initialized? */
return PFMLIB_ERR_NOINIT;
@@ -780,10 +809,13 @@ pfm_gen_powerpc_get_inst_retired(pfmlib_event_t *e)
e->event = POWER5_PME_PM_INST_CMPL;
break;
case PFMLIB_POWER5p_PMU:
- e->event = POWER5p_PME_PM_RUN_INST_CMPL;
+ e->event = POWER5p_PME_PM_INST_CMPL;
break;
case PFMLIB_POWER6_PMU:
- e->event = POWER6_PME_PM_RUN_INST_CMPL;
+ e->event = POWER6_PME_PM_INST_CMPL;
+ break;
+ case PFMLIB_POWER7_PMU:
+ e->event = POWER7_PME_PM_INST_CMPL;
break;
default:
/* perhaps gen_powerpc_suport.pmu_type wasn't initialized? */
@@ -800,7 +832,7 @@ pfm_gen_powerpc_get_inst_retired(pfmlib_event_t *e)
pfm_pmu_support_t gen_powerpc_support = {
/* the next 6 fields are initialized in pfm_gen_powerpc_pmu_detect */
.pmu_name = NULL,
- .pmu_type = 0,
+ .pmu_type = PFMLIB_UNKNOWN_PMU,
.pme_count = 0,
.pmd_count = 0,
.pmc_count = 0,
diff --git a/src/libpfm-3.y/lib/pfmlib_i386_p6.c b/src/libpfm-3.y/lib/pfmlib_i386_p6.c
index 44b25f41de885f35f36651bd8081ca0c0adf23d9..4afcb790d963189d90a285a4499484bb2e47525d 100644
--- a/src/libpfm-3.y/lib/pfmlib_i386_p6.c
+++ b/src/libpfm-3.y/lib/pfmlib_i386_p6.c
@@ -113,9 +113,16 @@ pfm_i386_p6_detect_ppro(void)
if (model != 1)
return PFMLIB_ERR_NOTSUPP;
+ return PFMLIB_SUCCESS;
+}
+
+static int
+pfm_i386_p6_init_ppro(void)
+{
i386_pe = i386_ppro_pe;
i386_p6_cycle_event = PME_I386_PPRO_CPU_CLK_UNHALTED;
i386_p6_inst_retired_event = PME_I386_PPRO_INST_RETIRED;
+
return PFMLIB_SUCCESS;
}
@@ -137,14 +144,10 @@ pfm_i386_p6_detect_pii(void)
return PFMLIB_ERR_NOTSUPP;
model = atoi(buffer);
-
switch(model) {
case 3: /* Pentium II */
case 5: /* Pentium II Deschutes */
case 6: /* Pentium II Mendocino */
- i386_pe = i386_pII_pe;
- i386_p6_cycle_event = PME_I386_PII_CPU_CLK_UNHALTED;
- i386_p6_inst_retired_event = PME_I386_PII_INST_RETIRED;
break;
default:
return PFMLIB_ERR_NOTSUPP;
@@ -152,6 +155,16 @@ pfm_i386_p6_detect_pii(void)
return PFMLIB_SUCCESS;
}
+static int
+pfm_i386_p6_init_pii(void)
+{
+
+ i386_pe = i386_pII_pe;
+ i386_p6_cycle_event = PME_I386_PII_CPU_CLK_UNHALTED;
+ i386_p6_inst_retired_event = PME_I386_PII_INST_RETIRED;
+ return PFMLIB_SUCCESS;
+}
+
/*
* detect Pentium III
*/
@@ -174,12 +187,8 @@ pfm_i386_p6_detect_piii(void)
switch(model) {
case 7: /* Pentium III Katmai */
case 8: /* Pentium III Coppermine */
- case 9: /* Mobile Pentium III */
case 10:/* Pentium III Cascades */
case 11:/* Pentium III Tualatin */
- i386_pe = i386_pIII_pe;
- i386_p6_cycle_event = PME_I386_PIII_CPU_CLK_UNHALTED;
- i386_p6_inst_retired_event = PME_I386_PIII_INST_RETIRED;
break;
default:
return PFMLIB_ERR_NOTSUPP;
@@ -187,6 +196,16 @@ pfm_i386_p6_detect_piii(void)
return PFMLIB_SUCCESS;
}
+static int
+pfm_i386_p6_init_piii(void)
+{
+ i386_pe = i386_pIII_pe;
+ i386_p6_cycle_event = PME_I386_PIII_CPU_CLK_UNHALTED;
+ i386_p6_inst_retired_event = PME_I386_PIII_INST_RETIRED;
+
+ return PFMLIB_SUCCESS;
+}
+
/*
* detect Pentium M
*/
@@ -205,9 +224,20 @@ pfm_i386_p6_detect_pm(void)
return PFMLIB_ERR_NOTSUPP;
model = atoi(buffer);
- if (model != 13)
- return PFMLIB_ERR_NOTSUPP;
+ switch (model) {
+ case 9:
+ case 13:
+ break;
+ default:
+ return PFMLIB_ERR_NOTSUPP;
+ }
+ return PFMLIB_SUCCESS;
+}
+
+static int
+pfm_i386_p6_init_pm(void)
+{
i386_pe = i386_pm_pe;
i386_p6_cycle_event = PME_I386_PM_CPU_CLK_UNHALTED;
i386_p6_inst_retired_event = PME_I386_PM_INST_RETIRED;
@@ -240,7 +270,7 @@ pfm_i386_p6_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_i386_p6_input_pa
if (PFMLIB_DEBUG()) {
for (j=0; j < cnt; j++) {
- DPRINT(("ev[%d]=%s\n", j, i386_pe[e[j].event].pme_name));
+ DPRINT("ev[%d]=%s\n", j, i386_pe[e[j].event].pme_name);
}
}
@@ -250,19 +280,19 @@ pfm_i386_p6_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_i386_p6_input_pa
pfm_i386_p6_get_impl_counters(&impl_cntrs);
pfm_regmask_andnot(&avail_cntrs, &impl_cntrs, &inp->pfp_unavail_pmcs);
- DPRINT(("impl=0x%lx avail=0x%lx unavail=0x%lx\n", impl_cntrs.bits[0], avail_cntrs.bits[0], inp->pfp_unavail_pmcs.bits[0]));
+ DPRINT("impl=0x%lx avail=0x%lx unavail=0x%lx\n", impl_cntrs.bits[0], avail_cntrs.bits[0], inp->pfp_unavail_pmcs.bits[0]);
for(j=0; j < cnt; j++) {
/*
* P6 only supports two priv levels for perf counters
*/
if (e[j].plm & (PFM_PLM1|PFM_PLM2)) {
- DPRINT(("event=%d invalid plm=%d\n", e[j].event, e[j].plm));
+ DPRINT("event=%d invalid plm=%d\n", e[j].event, e[j].plm);
return PFMLIB_ERR_INVAL;
}
- if (e[j].flags & ~PFMLIB_I386_P6_ALL_FLAGS) {
- DPRINT(("event=%d invalid flags=0x%lx\n", e[j].event, e[j].flags));
+ if (cntrs && cntrs[j].flags & ~PFMLIB_I386_P6_ALL_FLAGS) {
+ DPRINT("event=%d invalid flags=0x%lx\n", e[j].event, e[j].flags);
return PFMLIB_ERR_INVAL;
}
@@ -270,7 +300,7 @@ pfm_i386_p6_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_i386_p6_input_pa
* check illegal unit masks combination
*/
if (e[j].num_masks > 1 && PFMLIB_I386_P6_HAS_COMBO(e[j].event) == 0) {
- DPRINT(("event does not support unit mask combination\n"));
+ DPRINT("event does not support unit mask combination\n");
return PFMLIB_ERR_FEATCOMB;
}
}
@@ -396,7 +426,7 @@ pfm_i386_p6_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_ou
pfmlib_i386_p6_input_param_t *mod_in = (pfmlib_i386_p6_input_param_t *)model_in;
if (inp->pfp_dfl_plm & (PFM_PLM1|PFM_PLM2)) {
- DPRINT(("invalid plm=%x\n", inp->pfp_dfl_plm));
+ DPRINT("invalid plm=%x\n", inp->pfp_dfl_plm);
return PFMLIB_ERR_INVAL;
}
return pfm_i386_p6_dispatch_counters(inp, mod_in, outp);
@@ -545,6 +575,7 @@ pfm_pmu_support_t i386_pii_support={
.get_event_counters = pfm_i386_p6_get_event_counters,
.dispatch_events = pfm_i386_p6_dispatch_events,
.pmu_detect = pfm_i386_p6_detect_pii,
+ .pmu_init = pfm_i386_p6_init_pii,
.get_impl_pmcs = pfm_i386_p6_get_impl_perfsel,
.get_impl_pmds = pfm_i386_p6_get_impl_perfctr,
.get_impl_counters = pfm_i386_p6_get_impl_counters,
@@ -571,6 +602,7 @@ pfm_pmu_support_t i386_p6_support={
.get_event_counters = pfm_i386_p6_get_event_counters,
.dispatch_events = pfm_i386_p6_dispatch_events,
.pmu_detect = pfm_i386_p6_detect_piii,
+ .pmu_init = pfm_i386_p6_init_piii,
.get_impl_pmcs = pfm_i386_p6_get_impl_perfsel,
.get_impl_pmds = pfm_i386_p6_get_impl_perfctr,
.get_impl_counters = pfm_i386_p6_get_impl_counters,
@@ -596,6 +628,7 @@ pfm_pmu_support_t i386_ppro_support={
.get_event_counters = pfm_i386_p6_get_event_counters,
.dispatch_events = pfm_i386_p6_dispatch_events,
.pmu_detect = pfm_i386_p6_detect_ppro,
+ .pmu_init = pfm_i386_p6_init_ppro,
.get_impl_pmcs = pfm_i386_p6_get_impl_perfsel,
.get_impl_pmds = pfm_i386_p6_get_impl_perfctr,
.get_impl_counters = pfm_i386_p6_get_impl_counters,
@@ -623,6 +656,7 @@ pfm_pmu_support_t i386_pm_support={
.get_event_counters = pfm_i386_p6_get_event_counters,
.dispatch_events = pfm_i386_p6_dispatch_events,
.pmu_detect = pfm_i386_p6_detect_pm,
+ .pmu_init = pfm_i386_p6_init_pm,
.get_impl_pmcs = pfm_i386_p6_get_impl_perfsel,
.get_impl_pmds = pfm_i386_p6_get_impl_perfctr,
.get_impl_counters = pfm_i386_p6_get_impl_counters,
diff --git a/src/libpfm-3.y/lib/pfmlib_intel_atom.c b/src/libpfm-3.y/lib/pfmlib_intel_atom.c
index fdc82e6d9114490548d94c9c9ba3f10473cfad55..a5695333821cbca9efa4c70b1f0fbd231f8734b0 100644
--- a/src/libpfm-3.y/lib/pfmlib_intel_atom.c
+++ b/src/libpfm-3.y/lib/pfmlib_intel_atom.c
@@ -123,6 +123,8 @@ pfm_intel_atom_detect(void)
static int
pfm_intel_atom_init(void)
{
+ int i;
+
/* generic counters */
pfm_regmask_set(&intel_atom_impl_pmcs, 0);
pfm_regmask_set(&intel_atom_impl_pmds, 0);
@@ -137,6 +139,13 @@ pfm_intel_atom_init(void)
pfm_regmask_set(&intel_atom_impl_pmds, 17);
pfm_regmask_set(&intel_atom_impl_pmds, 18);
+ /* lbr */
+ pfm_regmask_set(&intel_atom_impl_pmds, 19);
+ for(i=0; i < 16; i++)
+ pfm_regmask_set(&intel_atom_impl_pmds, i);
+
+ highest_counter = 18;
+
/* PEBS */
pfm_regmask_set(&intel_atom_impl_pmcs, 17);
@@ -239,7 +248,7 @@ pfm_intel_atom_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_intel_atom_in
/*
* check for valid flags
*/
- if (e[i].flags & ~PFMLIB_INTEL_ATOM_ALL_FLAGS)
+ if (cntrs && cntrs[i].flags & ~PFMLIB_INTEL_ATOM_ALL_FLAGS)
return PFMLIB_ERR_INVAL;
if (intel_atom_pe[e[i].event].pme_flags & PFMLIB_INTEL_ATOM_UMASK_NCOMBO
@@ -275,8 +284,8 @@ pfm_intel_atom_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_intel_atom_in
DPRINT("two events compete for FIXED_CTR2\n");
return PFMLIB_ERR_NOASSIGN;
}
- if (HAS_OPTIONS(i)) {
- DPRINT("fixed counters do not support inversion/counter-mask\n");
+ if (cntrs && ((cntrs[i].flags & (PFM_INTEL_ATOM_SEL_EDGE|PFM_INTEL_ATOM_SEL_INV)) || cntrs[i].cnt_mask)) {
+ DPRINT("UNHALTED_REFERENCE_CYCLES only accepts anythr filter\n");
return PFMLIB_ERR_NOASSIGN;
}
}
@@ -345,9 +354,12 @@ pfm_intel_atom_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_intel_atom_in
if (fixed_ctr) {
for(i=0; i < n; i++) {
/* fixed counters do not support event options (filters) */
- if (HAS_OPTIONS(i) || (use_pebs && pfm_intel_atom_has_pebs(e+i)))
- continue;
-
+ if (HAS_OPTIONS(i)) {
+ if (use_pebs && pfm_intel_atom_has_pebs(e+i))
+ continue;
+ if (cntrs[i].flags != PFM_INTEL_ATOM_SEL_ANYTHR)
+ continue;
+ }
if ((fixed_ctr & 0x1) && pfm_intel_atom_is_fixed(e+i, 0)) {
assign_pc[i] = 16;
fixed_ctr &= ~1;
@@ -394,6 +406,8 @@ pfm_intel_atom_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_intel_atom_in
val |= 1ULL;
if (plm & PFM_PLM3)
val |= 2ULL;
+ if (cntrs && cntrs[i].flags & PFM_INTEL_ATOM_SEL_ANYTHR)
+ val |= 4ULL;
val |= 1ULL << 3; /* force APIC int (kernel may force it anyway) */
reg.val |= val << ((assign_pc[i]-16)<<2);
@@ -405,12 +419,15 @@ pfm_intel_atom_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_intel_atom_in
pc[npc].reg_addr = 0x38D;
pc[npc].reg_alt_addr = 0x38D;
- __pfm_vbprintf("[FIXED_CTRL(pmc%u)=0x%"PRIx64" pmi0=1 en0=0x%"PRIx64" pmi1=1 en1=0x%"PRIx64" pmi2=1 en2=0x%"PRIx64"] ",
+ __pfm_vbprintf("[FIXED_CTRL(pmc%u)=0x%"PRIx64" pmi0=1 en0=0x%"PRIx64" any0=%d pmi1=1 en1=0x%"PRIx64" any1=%d pmi2=1 en2=0x%"PRIx64" any2=%d] ",
pc[npc].reg_num,
reg.val,
reg.val & 0x3ULL,
+ !!(reg.val & 0x4ULL),
(reg.val>>4) & 0x3ULL,
- (reg.val>>8) & 0x3ULL);
+ !!((reg.val>>4) & 0x4ULL),
+ (reg.val>>8) & 0x3ULL,
+ !!((reg.val>>8) & 0x4ULL));
if ((fixed_ctr & 0x1) == 0)
__pfm_vbprintf("INSTRUCTIONS_RETIRED ");
@@ -639,8 +656,11 @@ pfm_intel_atom_get_impl_pmds(pfmlib_regmask_t *impl_pmds)
static void
pfm_intel_atom_get_impl_counters(pfmlib_regmask_t *impl_counters)
{
- /* all pmds are counters */
- *impl_counters = intel_atom_impl_pmds;
+ pfm_regmask_set(impl_counters, 0);
+ pfm_regmask_set(impl_counters, 1);
+ pfm_regmask_set(impl_counters, 16);
+ pfm_regmask_set(impl_counters, 17);
+ pfm_regmask_set(impl_counters, 18);
}
/*
@@ -718,7 +738,7 @@ pfm_intel_atom_get_event_mask_code(unsigned int ev, unsigned int midx, unsigned
static int
pfm_intel_atom_get_cycle_event(pfmlib_event_t *e)
{
- e->event = PME_INTEL_ATOM_UNHALTED_INTEL_ATOM_CYCLES;
+ e->event = PME_INTEL_ATOM_UNHALTED_CORE_CYCLES;
return PFMLIB_SUCCESS;
}
@@ -762,7 +782,7 @@ pfm_pmu_support_t intel_atom_support={
.pmu_type = PFMLIB_INTEL_ATOM_PMU,
.pme_count = PME_INTEL_ATOM_EVENT_COUNT,
.pmc_count = 4,
- .pmd_count = 5,
+ .pmd_count = 22,
.num_cnt = 5,
.get_event_code = pfm_intel_atom_get_event_code,
.get_event_name = pfm_intel_atom_get_event_name,
diff --git a/src/libpfm-3.y/lib/pfmlib_intel_nhm_priv.h b/src/libpfm-3.y/lib/pfmlib_intel_nhm_priv.h
index 55bb6884826ee9e978365c60a71c35e11da7d3d6..0a28c781f501783b8ec36e0f1746aae4c0dcb755 100644
--- a/src/libpfm-3.y/lib/pfmlib_intel_nhm_priv.h
+++ b/src/libpfm-3.y/lib/pfmlib_intel_nhm_priv.h
@@ -33,6 +33,7 @@ typedef struct {
unsigned int pme_cntmsk; /* counter mask */
unsigned int pme_ucode; /* unit mask code */
unsigned int pme_uflags; /* unit mask flags */
+ unsigned int pme_umodel; /* CPU model for this umask */
} pme_nhm_umask_t;
typedef struct {
@@ -59,5 +60,8 @@ typedef struct {
#define PFMLIB_NHM_PEBS 0x040 /* support PEBS (precise event) */
#define PFMLIB_NHM_UNC 0x080 /* uncore event */
#define PFMLIB_NHM_UNC_FIXED 0x100 /* uncore fixed event */
+#define PFMLIB_NHM_OFFCORE_RSP1 0x200 /* requires OFFCORE_RSP1 register */
+#define PFMLIB_NHM_PMC0 0x400 /* works only on IA32_PMC0 */
+#define PFMLIB_NHM_EX 0x800 /* has Nehalem-EX specific unit masks */
#endif /* __PFMLIB_NHM_PRIV_H__ */
diff --git a/src/libpfm-3.y/lib/pfmlib_itanium.c b/src/libpfm-3.y/lib/pfmlib_itanium.c
index daaf5fc4f7c2e55914330fe64ec25097e172b9e8..28e245ab04f5ae4d37d0f92ba13072d711045041 100644
--- a/src/libpfm-3.y/lib/pfmlib_itanium.c
+++ b/src/libpfm-3.y/lib/pfmlib_itanium.c
@@ -139,8 +139,8 @@ pfm_ita_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *m
if (PFMLIB_DEBUG()) {
for (m=0; m < cnt; m++) {
- DPRINT(("ev[%d]=%s counters=0x%lx\n", m, itanium_pe[e[m].event].pme_name,
- itanium_pe[e[m].event].pme_counters));
+ DPRINT("ev[%d]=%s counters=0x%lx\n", m, itanium_pe[e[m].event].pme_name,
+ itanium_pe[e[m].event].pme_counters);
}
}
if (cnt > PMU_ITA_NUM_COUNTERS) return PFMLIB_ERR_TOOMANY;
@@ -150,7 +150,7 @@ pfm_ita_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *m
max_l2 = PMU_ITA_FIRST_COUNTER + PMU_ITA_NUM_COUNTERS*(cnt>2);
max_l3 = PMU_ITA_FIRST_COUNTER + PMU_ITA_NUM_COUNTERS*(cnt>3);
- DPRINT(("max_l0=%u max_l1=%u max_l2=%u max_l3=%u\n", max_l0, max_l1, max_l2, max_l3));
+ DPRINT("max_l0=%u max_l1=%u max_l2=%u max_l3=%u\n", max_l0, max_l1, max_l2, max_l3);
/*
* This code needs fixing. It is not very pretty and
* won't handle more than 4 counters if more become
@@ -267,7 +267,7 @@ pfm_dispatch_iear(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in, p
param->pfp_ita_iear.ear_umask = evt_umask(inp->pfp_events[iear_idx].event);
param->pfp_ita_iear.ear_ism = PFMLIB_ITA_ISM_BOTH; /* force both instruction sets */
- DPRINT(("I-EAR event with no info\n"));
+ DPRINT("I-EAR event with no info\n");
}
/* sanity check on the mode */
@@ -355,7 +355,7 @@ pfm_dispatch_dear(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in, p
param->pfp_ita_dear.ear_umask = evt_umask(inp->pfp_events[dear_idx].event);
param->pfp_ita_dear.ear_ism = PFMLIB_ITA_ISM_BOTH; /* force both instruction sets */
- DPRINT(("D-EAR event with no info\n"));
+ DPRINT("D-EAR event with no info\n");
}
@@ -518,7 +518,7 @@ pfm_dispatch_btb(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in, pf
param->pfp_ita_btb.btb_tac = 0x1; /* capture TAC */
param->pfp_ita_btb.btb_bac = 0x1; /* capture BAC */
- DPRINT(("BTB event with no info\n"));
+ DPRINT("BTB event with no info\n");
}
/*
@@ -610,16 +610,16 @@ do_normal_rr(unsigned long start, unsigned long end,
size = end - start;
- DPRINT(("start=0x%016lx end=0x%016lx size=0x%lx bytes (%lu bundles) nbr=%d dir=%d\n",
- start, end, size, size >> 4, nbr, dir));
+ DPRINT("start=0x%016lx end=0x%016lx size=0x%lx bytes (%lu bundles) nbr=%d dir=%d\n",
+ start, end, size, size >> 4, nbr, dir);
p2 = pfm_ia64_fls(size);
c = ALIGN_DOWN(end, p2);
- DPRINT(("largest power of two possible: 2^%d=0x%lx, crossing=0x%016lx\n",
+ DPRINT("largest power of two possible: 2^%d=0x%lx, crossing=0x%016lx\n",
p2,
- 1UL << p2, c));
+ 1UL << p2, c);
if ((c - (1UL<<p2)) >= start) {
l_addr = c - (1UL << p2);
@@ -635,31 +635,31 @@ do_normal_rr(unsigned long start, unsigned long end,
l_size = l_addr - start;
r_size = end - l_addr-(1UL<<p2);
- DPRINT(("largest chunk: 2^%d=0x%lx @0x%016lx-0x%016lx\n", p2, 1UL<<p2, l_addr, l_addr+(1UL<<p2)));
- if (l_size) DPRINT(("before: 0x%016lx-0x%016lx\n", start, l_addr));
- if (r_size) DPRINT(("after : 0x%016lx-0x%016lx\n", l_addr+(1UL<<p2), end));
+ DPRINT("largest chunk: 2^%d=0x%lx @0x%016lx-0x%016lx\n", p2, 1UL<<p2, l_addr, l_addr+(1UL<<p2));
+ if (l_size) DPRINT("before: 0x%016lx-0x%016lx\n", start, l_addr);
+ if (r_size) DPRINT("after : 0x%016lx-0x%016lx\n", l_addr+(1UL<<p2), end);
if (dir == 0 && l_size != 0 && nbr == 1) {
p2++;
l_addr = end - (1UL << p2);
if (PFMLIB_DEBUG()) {
l_offs = start - l_addr;
- DPRINT((">>l_offs: 0x%lx\n", l_offs));
+ DPRINT(">>l_offs: 0x%lx\n", l_offs);
}
} else if (dir == 1 && r_size != 0 && nbr == 1) {
p2++;
l_addr = start;
if (PFMLIB_DEBUG()) {
r_offs = l_addr+(1UL<<p2) - end;
- DPRINT((">>r_offs: 0x%lx\n", r_offs));
+ DPRINT(">>r_offs: 0x%lx\n", r_offs);
}
}
l_size = l_addr - start;
r_size = end - l_addr-(1UL<<p2);
- DPRINT((">>largest chunk: 2^%d @0x%016lx-0x%016lx\n", p2, l_addr, l_addr+(1UL<<p2)));
- if (l_size && !l_offs) DPRINT((">>before: 0x%016lx-0x%016lx\n", start, l_addr));
- if (r_size && !r_offs) DPRINT((">>after : 0x%016lx-0x%016lx\n", l_addr+(1UL<<p2), end));
+ DPRINT(">>largest chunk: 2^%d @0x%016lx-0x%016lx\n", p2, l_addr, l_addr+(1UL<<p2));
+ if (l_size && !l_offs) DPRINT(">>before: 0x%016lx-0x%016lx\n", start, l_addr);
+ if (r_size && !r_offs) DPRINT(">>after : 0x%016lx-0x%016lx\n", l_addr+(1UL<<p2), end);
/*
* we initialize the mask to full 0 and
@@ -774,7 +774,7 @@ compute_normal_rr(pfmlib_ita_input_rr_t *irr, int dfl_plm, int n, int *base_idx,
&br_index,
®_idx, in_rr->rr_plm ? in_rr->rr_plm : dfl_plm);
- DPRINT(("br_index=%d reg_idx=%d\n", br_index, reg_idx));
+ DPRINT("br_index=%d reg_idx=%d\n", br_index, reg_idx);
/*
* compute offsets
*/
@@ -830,7 +830,7 @@ pfm_dispatch_irange(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in,
if (n_intervals < 1) return PFMLIB_ERR_IRRINVAL;
- DPRINT(("n_intervals=%d\n", n_intervals));
+ DPRINT("n_intervals=%d\n", n_intervals);
ret = compute_normal_rr(irr, inp->pfp_dfl_plm, n_intervals, &base_idx, orr);
if (ret != PFMLIB_SUCCESS) {
@@ -882,7 +882,7 @@ pfm_dispatch_drange(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in,
if (n_intervals < 1) return PFMLIB_ERR_DRRINVAL;
- DPRINT(("n_intervals=%d\n", n_intervals));
+ DPRINT("n_intervals=%d\n", n_intervals);
ret = compute_normal_rr(irr, inp->pfp_dfl_plm, n_intervals, &base_idx, orr);
if (ret != PFMLIB_SUCCESS) {
diff --git a/src/libpfm-3.y/lib/pfmlib_itanium2.c b/src/libpfm-3.y/lib/pfmlib_itanium2.c
index 0ad757b86677ac56e904015ff6dcf491a166895e..7b7b517ee759236e74b93cec125c0c813c85e5bc 100644
--- a/src/libpfm-3.y/lib/pfmlib_itanium2.c
+++ b/src/libpfm-3.y/lib/pfmlib_itanium2.c
@@ -229,7 +229,7 @@ static unsigned int
check_inst_retired_events(pfmlib_input_param_t *inp, unsigned long *retired_mask)
{
int code;
- int c;
+ int c, ret;
unsigned int i, count, found = 0;
unsigned long umask, mask;
@@ -238,9 +238,11 @@ check_inst_retired_events(pfmlib_input_param_t *inp, unsigned long *retired_mask
count = inp->pfp_event_count;
mask = 0;
for(i=0; i < count; i++) {
- pfm_get_event_code(inp->pfp_events[i].event, &c);
+ ret = pfm_get_event_code(inp->pfp_events[i].event, &c);
if (c == code) {
- pfm_ita2_get_event_umask(inp->pfp_events[i].event, &umask);
+ ret = pfm_ita2_get_event_umask(inp->pfp_events[i].event, &umask);
+ if (ret != PFMLIB_SUCCESS)
+ break;
switch(umask) {
case 0: mask |= 1;
break;
@@ -398,7 +400,7 @@ valid_assign(pfmlib_event_t *e, unsigned int *as, pfmlib_regmask_t *r_pmcs, unsi
umask = evt_umask(e[i].event);
- DPRINT(("pmc4_evt=%d pmc4_umask=0x%lx cnt_list[%d]=%d grp=%d umask=0x%lx\n", pmc4_evt, pmc4_umask, i, e[i].event,evt_grp(e[i].event), umask));
+ DPRINT("pmc4_evt=%d pmc4_umask=0x%lx cnt_list[%d]=%d grp=%d umask=0x%lx\n", pmc4_evt, pmc4_umask, i, e[i].event,evt_grp(e[i].event), umask);
if (as[i] != 4 && evt_grp(e[i].event) == PFMLIB_ITA2_EVT_L2_CACHE_GRP && umask != 0 && umask != pmc4_umask) break;
}
@@ -407,7 +409,7 @@ valid_assign(pfmlib_event_t *e, unsigned int *as, pfmlib_regmask_t *r_pmcs, unsi
return PFMLIB_SUCCESS;
do_failure:
- DPRINT(("%s : failure %d\n", __FUNCTION__, failure));
+ DPRINT("%s : failure %d\n", __FUNCTION__, failure);
return PFMLIB_ERR_NOASSIGN;
}
@@ -480,8 +482,8 @@ pfm_ita2_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t
if (PFMLIB_DEBUG())
for (m=0; m < cnt; m++) {
- DPRINT(("ev[%d]=%s counters=0x%lx\n", m, itanium2_pe[e[m].event].pme_name,
- itanium2_pe[e[m].event].pme_counters));
+ DPRINT("ev[%d]=%s counters=0x%lx\n", m, itanium2_pe[e[m].event].pme_name,
+ itanium2_pe[e[m].event].pme_counters);
}
if (cnt > PMU_ITA2_NUM_COUNTERS) return PFMLIB_ERR_TOOMANY;
@@ -497,7 +499,7 @@ pfm_ita2_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t
max_l2 = PMU_ITA2_FIRST_COUNTER + PMU_ITA2_NUM_COUNTERS*(cnt>2);
max_l3 = PMU_ITA2_FIRST_COUNTER + PMU_ITA2_NUM_COUNTERS*(cnt>3);
- DPRINT(("max_l0=%u max_l1=%u max_l2=%u max_l3=%u\n", max_l0, max_l1, max_l2, max_l3));
+ DPRINT("max_l0=%u max_l1=%u max_l2=%u max_l3=%u\n", max_l0, max_l1, max_l2, max_l3);
/*
* For now, worst case in the loop nest: 4! (factorial)
*/
@@ -556,7 +558,7 @@ done:
pc[j].reg_addr = pc[j].reg_alt_addr = assign[j];
pd[j].reg_num = assign[j];
- pd[j].reg_addr = pd[j].reg_addr = assign[j];
+ pd[j].reg_addr = pd[j].reg_alt_addr = assign[j];
__pfm_vbprintf("[PMC%u(pmc%u)=0x%06lx thres=%d es=0x%02x plm=%d umask=0x%x pm=%d ism=0x%x oi=%d] %s\n",
assign[j],
@@ -615,7 +617,7 @@ pfm_dispatch_iear(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in,
param->pfp_ita2_iear.ear_umask = evt_umask(inp->pfp_events[i].event);
param->pfp_ita2_iear.ear_ism = PFMLIB_ITA2_ISM_BOTH; /* force both instruction sets */
- DPRINT(("I-EAR event with no info\n"));
+ DPRINT("I-EAR event with no info\n");
}
/*
@@ -639,7 +641,7 @@ pfm_dispatch_iear(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in,
reg.pmc10_ita2_cache_reg.iear_umask = param->pfp_ita2_iear.ear_umask;
reg.pmc10_ita2_cache_reg.iear_ism = param->pfp_ita2_iear.ear_ism;
} else {
- DPRINT(("ALAT mode not supported in I-EAR mode\n"));
+ DPRINT("ALAT mode not supported in I-EAR mode\n");
return PFMLIB_ERR_INVAL;
}
@@ -719,7 +721,7 @@ pfm_dispatch_dear(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in,
param->pfp_ita2_dear.ear_umask = evt_umask(inp->pfp_events[i].event);
param->pfp_ita2_dear.ear_ism = PFMLIB_ITA2_ISM_BOTH; /* force both instruction sets */
- DPRINT(("D-EAR event with no info\n"));
+ DPRINT("D-EAR event with no info\n");
}
/* sanity check on the mode */
@@ -813,7 +815,7 @@ pfm_dispatch_opcm(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in,
pc[pos].reg_num = 8;
pc[pos].reg_value = reg.pmc_val;
- pc[pos].reg_addr = pc[pos].reg_addr = 8;
+ pc[pos].reg_addr = pc[pos].reg_alt_addr = 8;
pos++;
/*
@@ -954,7 +956,7 @@ pfm_dispatch_btb(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in, p
}
}
- DPRINT(("found_btb=%d found_bar_dear=%d\n", found_btb, found_bad_dear));
+ DPRINT("found_btb=%d found_bar_dear=%d\n", found_btb, found_bad_dear);
/*
* did not find D-EAR TLB/ALAT event, need to check param structure
@@ -990,7 +992,7 @@ pfm_dispatch_btb(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in, p
param->pfp_ita2_btb.btb_ppm = 0x3; /* all branches */
param->pfp_ita2_btb.btb_brt = 0x0; /* all branches */
- DPRINT(("BTB event with no info\n"));
+ DPRINT("BTB event with no info\n");
}
/*
@@ -1074,16 +1076,16 @@ do_normal_rr(unsigned long start, unsigned long end,
size = end - start;
- DPRINT(("start=0x%016lx end=0x%016lx size=0x%lx bytes (%lu bundles) nbr=%d dir=%d\n",
- start, end, size, size >> 4, nbr, dir));
+ DPRINT("start=0x%016lx end=0x%016lx size=0x%lx bytes (%lu bundles) nbr=%d dir=%d\n",
+ start, end, size, size >> 4, nbr, dir);
p2 = pfm_ia64_fls(size);
c = ALIGN_DOWN(end, p2);
- DPRINT(("largest power of two possible: 2^%d=0x%lx, crossing=0x%016lx\n",
+ DPRINT("largest power of two possible: 2^%d=0x%lx, crossing=0x%016lx\n",
p2,
- 1UL << p2, c));
+ 1UL << p2, c);
if ((c - (1UL<<p2)) >= start) {
l_addr = c - (1UL << p2);
@@ -1337,11 +1339,11 @@ compute_single_rr(pfmlib_ita2_input_rr_t *irr, int dfl_plm, int *base_idx, pfmli
m++;
}
- DPRINT(("size=%ld, l=%d m=%d, internal: 0x%lx full: 0x%lx\n",
+ DPRINT("size=%ld, l=%d m=%d, internal: 0x%lx full: 0x%lx\n",
size,
l, m,
1UL << l,
- 1UL << m));
+ 1UL << m);
for (; m < 64; m++) {
p_start = ALIGN_DOWN(start, m);
@@ -1350,7 +1352,7 @@ compute_single_rr(pfmlib_ita2_input_rr_t *irr, int dfl_plm, int *base_idx, pfmli
}
return PFMLIB_ERR_IRRINVAL;
found:
- DPRINT(("m=%d p_start=0x%lx p_end=0x%lx\n", m, p_start,p_end));
+ DPRINT("m=%d p_start=0x%lx p_end=0x%lx\n", m, p_start,p_end);
/* when the event is not IA64_INST_RETIRED, then we MUST use ibrp0 */
br[0].reg_num = reg_idx;
@@ -1412,7 +1414,7 @@ compute_normal_rr(pfmlib_ita2_input_rr_t *irr, int dfl_plm, int n, int *base_idx
&br_index,
®_idx, in_rr->rr_plm ? in_rr->rr_plm : dfl_plm);
- DPRINT(("br_index=%d reg_idx=%d\n", br_index, reg_idx));
+ DPRINT("br_index=%d reg_idx=%d\n", br_index, reg_idx);
/*
* compute offsets
@@ -1481,8 +1483,8 @@ pfm_dispatch_irange(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in
fine_mode = irr->rr_flags & PFMLIB_ITA2_RR_NO_FINE_MODE ?
0 : check_fine_mode_possible(irr, n_intervals);
- DPRINT(("n_intervals=%d retired_only=%d retired_count=%d prefetch_count=%d fine_mode=%d\n",
- n_intervals, retired_only, retired_count, prefetch_count, fine_mode));
+ DPRINT("n_intervals=%d retired_only=%d retired_count=%d prefetch_count=%d fine_mode=%d\n",
+ n_intervals, retired_only, retired_count, prefetch_count, fine_mode);
/*
* On Itanium2, there are more constraints on what can be measured with irange.
diff --git a/src/libpfm-3.y/lib/pfmlib_montecito.c b/src/libpfm-3.y/lib/pfmlib_montecito.c
index 588b39c44099f09f5db7ec82a4aa057eb36e12a0..ae67640a4693c6771d8988bea0bda392ff0894ee 100644
--- a/src/libpfm-3.y/lib/pfmlib_montecito.c
+++ b/src/libpfm-3.y/lib/pfmlib_montecito.c
@@ -102,8 +102,6 @@ static char * pfm_mont_get_event_name(unsigned int i);
* values on the fly given the base.
*/
-static void pfm_mont_get_impl_counters(pfmlib_regmask_t *impl_counters);
-
static int
pfm_mont_detect(void)
{
@@ -156,7 +154,7 @@ check_cross_groups(pfmlib_input_param_t *inp, unsigned int *l1d_event,
s = evt_set(e[i].event);
if (g != PFMLIB_MONT_EVT_L1D_CACHE_GRP) continue;
- DPRINT(("i=%u g=%d s=%d\n", i, g, s));
+ DPRINT("i=%u g=%d s=%d\n", i, g, s);
l1d_event_idx = i;
for (j=i+1; j < cnt; j++) {
if (evt_grp(e[j].event) != g) continue;
@@ -479,8 +477,8 @@ pfm_mont_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t
if (PFMLIB_DEBUG())
for (m=0; m < cnt; m++) {
- DPRINT(("ev[%d]=%s counters=0x%lx\n", m, montecito_pe[e[m].event].pme_name,
- montecito_pe[e[m].event].pme_counters));
+ DPRINT("ev[%d]=%s counters=0x%lx\n", m, montecito_pe[e[m].event].pme_name,
+ montecito_pe[e[m].event].pme_counters);
}
if (cnt > PMU_MONT_NUM_COUNTERS) return PFMLIB_ERR_TOOMANY;
@@ -499,18 +497,18 @@ pfm_mont_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t
* - cancel events are compatible
*/
- DPRINT(("l1d_set=%u l2d_set1_mask=0x%lx l2d_set2_mask=0x%lx\n", l1d_set, l2d_set1_mask, l2d_set2_mask));
+ DPRINT("l1d_set=%u l2d_set1_mask=0x%lx l2d_set2_mask=0x%lx\n", l1d_set, l2d_set1_mask, l2d_set2_mask);
/*
* first, place L1D cache event in PMC5
*
* this is the strongest constraint
*/
- pfm_mont_get_impl_counters(&impl_cntrs);
+ pfm_get_impl_counters(&impl_cntrs);
pfm_regmask_andnot(&avail_cntrs, &impl_cntrs, &inp->pfp_unavail_pmcs);
not_assigned_events = 0;
- DPRINT(("avail_cntrs=0x%lx\n", avail_cntrs.bits[0]));
+ DPRINT("avail_cntrs=0x%lx\n", avail_cntrs.bits[0]);
/*
* we do not check ALL_THRD here because at least
@@ -567,12 +565,12 @@ pfm_mont_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t
if (i != l1d_set)
not_assigned_events |= evt_mask;
- DPRINT(("phase 1: i=%u avail_cntrs=0x%lx l2d_set1_p=%d l2d_set2_p=%d not_assigned=0x%lx\n",
+ DPRINT("phase 1: i=%u avail_cntrs=0x%lx l2d_set1_p=%d l2d_set2_p=%d not_assigned=0x%lx\n",
i,
avail_cntrs.bits[0],
l2d_set1_p,
l2d_set2_p,
- not_assigned_events));
+ not_assigned_events);
}
/*
* assign BUS_* ER_* events (work only in PMC4-PMC9)
@@ -594,8 +592,8 @@ pfm_mont_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t
if ((cnt_mask & 0x1) == 0)
continue;
- DPRINT(("phase 2: i=%d j=%d cnt_mask=0x%lx avail_cntrs=0x%lx not_assigned_evnts=0x%lx\n",
- i, j, cnt_mask, avail_cntrs.bits[0], not_assigned_events));
+ DPRINT("phase 2: i=%d j=%d cnt_mask=0x%lx avail_cntrs=0x%lx not_assigned_evnts=0x%lx\n",
+ i, j, cnt_mask, avail_cntrs.bits[0], not_assigned_events);
if (!pfm_regmask_isset(&avail_cntrs, j))
continue;
@@ -615,14 +613,14 @@ pfm_mont_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t
max_cnt = PMU_MONT_FIRST_COUNTER + PMU_MONT_NUM_COUNTERS;
for (i=0, j=0; evt_mask ; i++, evt_mask >>=1) {
- DPRINT(("phase 3a: i=%d j=%d evt_mask=0x%lx avail_cntrs=0x%lx not_assigned_evnts=0x%lx\n",
- i, j, evt_mask, avail_cntrs.bits[0], not_assigned_events));
+ DPRINT("phase 3a: i=%d j=%d evt_mask=0x%lx avail_cntrs=0x%lx not_assigned_evnts=0x%lx\n",
+ i, j, evt_mask, avail_cntrs.bits[0], not_assigned_events);
if ((evt_mask & 0x1) == 0)
continue;
while(j < max_cnt && !pfm_regmask_isset(&avail_cntrs, j)) {
- DPRINT(("phase 3: i=%d j=%d evt_mask=0x%lx avail_cntrs=0x%lx not_assigned_evnts=0x%lx\n",
- i, j, evt_mask, avail_cntrs.bits[0], not_assigned_events));
+ DPRINT("phase 3: i=%d j=%d evt_mask=0x%lx avail_cntrs=0x%lx not_assigned_evnts=0x%lx\n",
+ i, j, evt_mask, avail_cntrs.bits[0], not_assigned_events);
j++;
}
@@ -640,7 +638,7 @@ pfm_mont_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t
* XXX: we do not support .all placement just yet
*/
if (param && param->pfp_mont_counters[j].flags & PFMLIB_MONT_FL_EVT_ALL_THRD) {
- DPRINT((".all mode is not yet supported by libpfm\n"));
+ DPRINT(".all mode is not yet supported by libpfm\n");
return PFMLIB_ERR_NOTSUPP;
}
@@ -738,7 +736,7 @@ pfm_dispatch_iear(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in,
param->pfp_mont_iear.ear_umask = evt_umask(inp->pfp_events[i].event);
- DPRINT(("I-EAR event with no info\n"));
+ DPRINT("I-EAR event with no info\n");
}
/*
@@ -760,7 +758,7 @@ pfm_dispatch_iear(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in,
reg.pmc37_mont_cache_reg.iear_ct = 0x1;
reg.pmc37_mont_cache_reg.iear_umask = param->pfp_mont_iear.ear_umask;
} else {
- DPRINT(("ALAT mode not supported in I-EAR mode\n"));
+ DPRINT("ALAT mode not supported in I-EAR mode\n");
return PFMLIB_ERR_INVAL;
}
if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 37))
@@ -768,7 +766,7 @@ pfm_dispatch_iear(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in,
pc[pos1].reg_num = 37; /* PMC37 is I-EAR config register */
pc[pos1].reg_value = reg.pmc_val;
- pc[pos1].reg_addr = pc[pos1].reg_addr = 37;
+ pc[pos1].reg_addr = pc[pos1].reg_alt_addr = 37;
pos1++;
pd[pos2].reg_num = 34;
@@ -837,7 +835,7 @@ pfm_dispatch_dear(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in,
param->pfp_mont_dear.ear_umask = evt_umask(inp->pfp_events[i].event);
- DPRINT(("D-EAR event with no info\n"));
+ DPRINT("D-EAR event with no info\n");
}
/* sanity check on the mode */
@@ -1121,7 +1119,7 @@ pfm_dispatch_etb(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in, p
}
}
- DPRINT(("found_etb=%d found_bar_dear=%d\n", found_etb, found_bad_dear));
+ DPRINT("found_etb=%d found_bar_dear=%d\n", found_etb, found_bad_dear);
/*
* did not find D-EAR TLB/ALAT event, need to check param structure
@@ -1156,7 +1154,7 @@ pfm_dispatch_etb(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in, p
param->pfp_mont_etb.etb_ppm = 0x3; /* all branches */
param->pfp_mont_etb.etb_brt = 0x0; /* all branches */
- DPRINT(("ETB event with no info\n"));
+ DPRINT("ETB event with no info\n");
}
/*
@@ -1244,16 +1242,16 @@ do_normal_rr(unsigned long start, unsigned long end,
size = end - start;
- DPRINT(("start=0x%016lx end=0x%016lx size=0x%lx bytes (%lu bundles) nbr=%d dir=%d\n",
- start, end, size, size >> 4, nbr, dir));
+ DPRINT("start=0x%016lx end=0x%016lx size=0x%lx bytes (%lu bundles) nbr=%d dir=%d\n",
+ start, end, size, size >> 4, nbr, dir);
p2 = pfm_ia64_fls(size);
c = ALIGN_DOWN(end, p2);
- DPRINT(("largest power of two possible: 2^%d=0x%lx, crossing=0x%016lx\n",
+ DPRINT("largest power of two possible: 2^%d=0x%lx, crossing=0x%016lx\n",
p2,
- 1UL << p2, c));
+ 1UL << p2, c);
if ((c - (1UL<<p2)) >= start) {
l_addr = c - (1UL << p2);
@@ -1506,11 +1504,11 @@ compute_single_rr(pfmlib_mont_input_rr_t *irr, int dfl_plm, int *base_idx, pfmli
m++;
}
- DPRINT(("size=%ld, l=%d m=%d, internal: 0x%lx full: 0x%lx\n",
+ DPRINT("size=%ld, l=%d m=%d, internal: 0x%lx full: 0x%lx\n",
size,
l, m,
1UL << l,
- 1UL << m));
+ 1UL << m);
for (; m < 64; m++) {
p_start = ALIGN_DOWN(start, m);
@@ -1519,7 +1517,7 @@ compute_single_rr(pfmlib_mont_input_rr_t *irr, int dfl_plm, int *base_idx, pfmli
}
return PFMLIB_ERR_IRRINVAL;
found:
- DPRINT(("m=%d p_start=0x%lx p_end=0x%lx\n", m, p_start,p_end));
+ DPRINT("m=%d p_start=0x%lx p_end=0x%lx\n", m, p_start,p_end);
/* when the event is not IA64_INST_RETIRED, then we MUST use ibrp0 */
br[0].reg_num = reg_idx;
@@ -1581,7 +1579,7 @@ compute_normal_rr(pfmlib_mont_input_rr_t *irr, int dfl_plm, int n, int *base_idx
&br_index,
®_idx, in_rr->rr_plm ? in_rr->rr_plm : dfl_plm);
- DPRINT(("br_index=%d reg_idx=%d\n", br_index, reg_idx));
+ DPRINT("br_index=%d reg_idx=%d\n", br_index, reg_idx);
/*
* compute offsets
@@ -1651,8 +1649,8 @@ pfm_dispatch_irange(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in
0 : check_fine_mode_possible(irr, n_intervals);
- DPRINT(("n_intervals=%d retired_only=%d retired_count=%d fine_mode=%d\n",
- n_intervals, retired_only, retired_count, fine_mode));
+ DPRINT("n_intervals=%d retired_only=%d retired_count=%d fine_mode=%d\n",
+ n_intervals, retired_only, retired_count, fine_mode);
/*
* On montecito, there are more constraints on what can be measured with irange.
*
@@ -1687,7 +1685,7 @@ pfm_dispatch_irange(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in
if (ret)
return ret;
- DPRINT(("prefetch_count=%u base_idx=%d dup=%d\n", prefetch_count, base_idx, dup));
+ DPRINT("prefetch_count=%u base_idx=%d dup=%d\n", prefetch_count, base_idx, dup);
/*
* CPU_OP_CYCLES.QUAL supports code range restrictions but it returns
diff --git a/src/libpfm-3.y/lib/pfmlib_os_linux.c b/src/libpfm-3.y/lib/pfmlib_os_linux.c
index 22b038b2d1b2926f18a883e275c8c44d4eb9352b..3faf96bff69ec087bf210df70060c888773836fb 100644
--- a/src/libpfm-3.y/lib/pfmlib_os_linux.c
+++ b/src/libpfm-3.y/lib/pfmlib_os_linux.c
@@ -21,34 +21,26 @@
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
+#ifndef _GNU_SOURCE
#define _GNU_SOURCE /* for getline */
+#endif
#include <sys/types.h>
#include <stdint.h>
#include <stdio.h>
+#include <stdarg.h>
#include <string.h>
#include <stdlib.h>
#include <unistd.h>
-#include <syscall.h>
+#include <errno.h>
#include <sys/utsname.h>
#include <perfmon/perfmon.h>
#include <perfmon/pfmlib.h>
#include "pfmlib_priv.h"
-#define PFM_pfm_create_context (sys_base+0)
-#define PFM_pfm_write_pmcs (sys_base+1)
-#define PFM_pfm_write_pmds (sys_base+2)
-#define PFM_pfm_read_pmds (sys_base+3)
-#define PFM_pfm_load_context (sys_base+4)
-#define PFM_pfm_start (sys_base+5)
-#define PFM_pfm_stop (sys_base+6)
-#define PFM_pfm_restart (sys_base+7)
-#define PFM_pfm_create_evtsets (sys_base+8)
-#define PFM_pfm_getinfo_evtsets (sys_base+9)
-#define PFM_pfm_delete_evtsets (sys_base+10)
-#define PFM_pfm_unload_context (sys_base+11)
-
-static int sys_base; /* syscall base */
+int _pfmlib_sys_base; /* syscall base */
+int _pfmlib_major_version; /* kernel perfmon major version */
+int _pfmlib_minor_version; /* kernel perfmon minor version */
/*
* helper function to retrieve one value from /proc/cpuinfo
@@ -112,216 +104,184 @@ error:
return ret;
}
-int
-pfm_create_context(pfarg_ctx_t *ctx, char *name, void *smpl_arg, size_t smpl_size)
-{
-#ifdef PFMLIB_VERSION_22
- /*
- * In perfmon v2.2, the pfm_create_context() call had a different return value.
- * It used to return errno, now it returns the file descriptor.
- */
- int r = syscall (PFM_pfm_create_context, ctx, smpl_arg, smpl_size);
- return (r < 0 ? r : ctx->ctx_fd);
-#else
- return (int)syscall(PFM_pfm_create_context, ctx, name, smpl_arg, smpl_size);
-#endif
-}
-
-int
-pfm_write_pmcs(int fd, pfarg_pmc_t *pmcs, int count)
-{
- return (int)syscall(PFM_pfm_write_pmcs, fd, pmcs, count);
-}
-
-int
-pfm_write_pmds(int fd, pfarg_pmd_t *pmds, int count)
-{
- return (int)syscall(PFM_pfm_write_pmds, fd, pmds, count);
-}
-
-int
-pfm_read_pmds(int fd, pfarg_pmd_t *pmds, int count)
-{
- return (int)syscall(PFM_pfm_read_pmds, fd, pmds, count);
-}
-
-int
-pfm_load_context(int fd, pfarg_load_t *load)
-{
- return (int)syscall(PFM_pfm_load_context, fd, load);
-}
-
-int
-pfm_start(int fd, pfarg_start_t *start)
-{
- return (int)syscall(PFM_pfm_start, fd, start);
-}
-
-int
-pfm_stop(int fd)
-{
- return (int)syscall(PFM_pfm_stop, fd);
-}
-
-int
-pfm_restart(int fd)
-{
- return (int)syscall(PFM_pfm_restart, fd);
-}
-
-int
-pfm_create_evtsets(int fd, pfarg_setdesc_t *setd, int count)
-{
- return (int)syscall(PFM_pfm_create_evtsets, fd, setd, count);
-}
-
-int
-pfm_delete_evtsets(int fd, pfarg_setdesc_t *setd, int count)
-{
- return (int)syscall(PFM_pfm_delete_evtsets, fd, setd, count);
-}
-
-int
-pfm_getinfo_evtsets(int fd, pfarg_setinfo_t *info, int count)
-{
- return (int)syscall(PFM_pfm_getinfo_evtsets, fd, info, count);
-}
-
-int
-pfm_unload_context(int fd)
-{
- return (int)syscall(PFM_pfm_unload_context, fd);
-}
-
#if defined(__x86_64__)
-static void adjust_sys_base(int version)
+static void adjust__pfmlib_sys_base(int version)
{
#ifdef CONFIG_PFMLIB_ARCH_CRAYXT
- sys_base = 273;
+ _pfmlib_sys_base = 273;
#else
switch(version) {
+ case 29:
+ case 28:
+ case 27:
+ _pfmlib_sys_base = 295;
+ break;
+ case 26:
case 25:
- sys_base = 288;
+ _pfmlib_sys_base = 288;
break;
case 24:
default: /* 2.6.24 as default */
- sys_base = 286;
+ _pfmlib_sys_base = 286;
}
#endif
}
#elif defined(__i386__)
-static void adjust_sys_base(int version)
+static void adjust__pfmlib_sys_base(int version)
{
switch(version) {
+ case 29:
+ case 28:
+ case 27:
+ _pfmlib_sys_base = 333;
+ break;
+ case 26:
case 25:
- sys_base = 327;
+ _pfmlib_sys_base = 327;
break;
case 24:
default: /* 2.6.24 as default */
- sys_base = 327;
+ _pfmlib_sys_base = 325;
}
}
#elif defined(__mips__)
#if (_MIPS_SIM == _ABIN32) || (_MIPS_SIM == _MIPS_SIM_NABI32)
-static void adjust_sys_base(int version)
+static void adjust__pfmlib_sys_base(int version)
{
- sys_base = 6000;
+ _pfmlib_sys_base = 6000;
#ifdef CONFIG_PFMLIB_ARCH_SICORTEX
- sys_base += 279;
+ _pfmlib_sys_base += 279;
#else
switch(version) {
+ case 29:
+ case 28:
+ case 27:
+ _pfmlib_sys_base += 293;
+ break;
+ case 26:
case 25:
- sys_base += 287;
+ _pfmlib_sys_base += 287;
break;
case 24:
default: /* 2.6.24 as default */
- sys_base += 284;
+ _pfmlib_sys_base += 284;
}
#endif
}
-#elif (_MIPS_SIM == _ABI32) || (_MIPS_SIM == _MIPS_SIM_ABI32)
-static void adjust_sys_base(int version)
+#elif (_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _MIPS_SIM_ABI32)
+static void adjust__pfmlib_sys_base(int version)
{
- sys_base = 4000;
+ _pfmlib_sys_base = 4000;
#ifdef CONFIG_PFMLIB_ARCH_SICORTEX
- sys_base += 316;
+ _pfmlib_sys_base += 316;
#else
switch(version) {
+ case 29:
+ case 28:
+ case 27:
+ _pfmlib_sys_base += 330;
+ break;
+ case 26:
case 25:
- sys_base += 324;
+ _pfmlib_sys_base += 324;
break;
case 24:
default: /* 2.6.24 as default */
- sys_base += 321;
+ _pfmlib_sys_base += 321;
}
#endif
}
#elif (_MIPS_SIM == _ABI64) || (_MIPS_SIM == _MIPS_SIM_ABI64)
-static void adjust_sys_base(int version)
+static void adjust__pfmlib_sys_base(int version)
{
- sys_base = 5000;
+ _pfmlib_sys_base = 5000;
#ifdef CONFIG_PFMLIB_ARCH_SICORTEX
- sys_base += 275;
+ _pfmlib_sys_base += 275;
#else
switch(version) {
+ case 29:
+ case 28:
+ case 27:
+ _pfmlib_sys_base += 289;
+ break;
+ case 26:
case 25:
- sys_base += 283;
+ _pfmlib_sys_base += 283;
break;
case 24:
default: /* 2.6.24 as default */
- sys_base += 280;
+ _pfmlib_sys_base += 280;
}
#endif
}
#endif
#elif defined(__ia64__)
-static void adjust_sys_base(int version)
+static void adjust__pfmlib_sys_base(int version)
{
switch(version) {
+ case 29:
+ case 28:
+ case 27:
+ _pfmlib_sys_base = 1319;
+ break;
+ case 26:
case 25:
- sys_base = 1313;
+ _pfmlib_sys_base = 1313;
break;
case 24:
default: /* 2.6.24 as default */
- sys_base = 1310;
+ _pfmlib_sys_base = 1310;
}
}
#elif defined(__powerpc__)
-static void adjust_sys_base(int version)
+static void adjust__pfmlib_sys_base(int version)
{
switch(version) {
+ case 29:
+ case 28:
+ case 27:
+ _pfmlib_sys_base = 319;
+ break;
+ case 26:
case 25:
- sys_base = 313;
+ _pfmlib_sys_base = 313;
break;
case 24:
default: /* 2.6.24 as default */
- sys_base = 310;
+ _pfmlib_sys_base = 310;
}
}
#elif defined(__sparc__)
-static void adjust_sys_base(int version)
+static void adjust__pfmlib_sys_base(int version)
{
switch(version) {
+ case 28:
+ _pfmlib_sys_base = 324;
+ break;
+ case 27:
+ _pfmlib_sys_base = 323;
+ break;
+ case 26:
case 25:
- sys_base = 317;
+ _pfmlib_sys_base = 317;
break;
case 24:
default: /* 2.6.24 as default */
- sys_base = 310;
+ _pfmlib_sys_base = 310;
}
}
#elif defined(__crayx2)
-static inline void adjust_sys_base(int version)
+static inline void adjust__pfmlib_sys_base(int version)
{
- sys_base = 294;
+ _pfmlib_sys_base = 294;
}
#else
-static inline void adjust_sys_base(int version)
+static inline void adjust__pfmlib_sys_base(int version)
{}
#endif
-void
-pfm_init_syscalls(void)
+static void
+pfm_init_syscalls_hardcoded(void)
{
struct utsname b;
char *p, *s;
@@ -365,21 +325,70 @@ pfm_init_syscalls(void)
/* v is subversion: 23, 24 25 */
v = atoi(s);
- adjust_sys_base(v);
- __pfm_vbprintf("sycall base %d\n", sys_base);
+ adjust__pfmlib_sys_base(v);
}
-#ifdef __ia64__
-#define __PFMLIB_OS_COMPILE
-#include <perfmon/pfmlib.h>
+static int
+pfm_init_syscalls_sysfs(void)
+{
+ FILE *fp;
+ int ret;
-/*
- * this is the old perfmon2 interface, maintained for backward
- * compatibility reasons with older applications. This is for IA-64 ONLY.
- */
-int
-perfmonctl(int fd, int cmd, void *arg, int narg)
+ fp = fopen("/sys/kernel/perfmon/syscall", "r");
+ if (!fp)
+ return -1;
+
+ ret = fscanf(fp, "%d", &_pfmlib_sys_base);
+
+ fclose(fp);
+ return ret == 1 ? 0 : -1;
+}
+static int
+pfm_init_version_sysfs(void)
+{
+ FILE *fp;
+ char *p;
+ char v[8];
+ int ret;
+
+ fp = fopen("/sys/kernel/perfmon/version", "r");
+ if (!fp)
+ return -1;
+
+ ret = fscanf(fp, "%s", v);
+ if (ret != 1)
+ goto skip;
+ p = strchr(v, '.');
+ if (p) {
+ *p++ = '\0';
+ _pfmlib_major_version = atoi(v);
+ _pfmlib_minor_version = atoi(p);
+ }
+skip:
+ fclose(fp);
+ return ret == 1 ? 0 : -1;
+}
+
+
+void
+pfm_init_syscalls(void)
{
- return syscall(__NR_perfmonctl, fd, cmd, arg, narg);
+ int ret;
+
+ /*
+ * first try via sysfs
+ */
+ ret = pfm_init_syscalls_sysfs();
+ if (ret)
+ pfm_init_syscalls_hardcoded();
+
+ ret = pfm_init_version_sysfs();
+ if (ret) {
+ _pfmlib_major_version = 3;
+ _pfmlib_minor_version = 0;
+ }
+ __pfm_vbprintf("sycall base %d\n", _pfmlib_sys_base);
+ __pfm_vbprintf("major version %d\nminor version %d\n",
+ _pfmlib_major_version,
+ _pfmlib_minor_version);
}
-#endif /* __ia64__ */
diff --git a/src/libpfm-3.y/lib/pfmlib_os_linux_v3.c b/src/libpfm-3.y/lib/pfmlib_os_linux_v3.c
index 8187ba8a689a31af5e4225822588ce2568e655a7..c418a64529cbe3451012912a93e086f48aa0eb6d 100644
--- a/src/libpfm-3.y/lib/pfmlib_os_linux_v3.c
+++ b/src/libpfm-3.y/lib/pfmlib_os_linux_v3.c
@@ -60,6 +60,11 @@ pfm_create(int flags, pfarg_sinfo_t *sif, ...)
size_t smpl_size = 0;
int ret;
+ if (_pfmlib_major_version < 3) {
+ errno = ENOSYS;
+ return -1;
+ }
+
if (flags & PFM_FL_SMPL_FMT)
va_start(ap, sif);
@@ -80,35 +85,47 @@ pfm_create(int flags, pfarg_sinfo_t *sif, ...)
int
pfm_write(int fd, int flags, int type, void *pms, size_t sz)
{
+ if (_pfmlib_major_version < 3)
+ return -ENOSYS;
return (int)syscall(PFM_pfm_write, fd, flags, type, pms, sz);
}
int
pfm_read(int fd, int flags, int type, void *pms, size_t sz)
{
+ if (_pfmlib_major_version < 3)
+ return -ENOSYS;
return (int)syscall(PFM_pfm_read, fd, flags, type, pms, sz);
}
int
pfm_create_sets(int fd, int flags, pfarg_set_desc_t *setd, size_t sz)
{
+ if (_pfmlib_major_version < 3)
+ return -ENOSYS;
return (int)syscall(PFM_pfm_create_sets, fd, flags, setd, sz);
}
int
pfm_getinfo_sets(int fd, int flags, pfarg_set_info_t *info, size_t sz)
{
+ if (_pfmlib_major_version < 3)
+ return -ENOSYS;
return (int)syscall(PFM_pfm_getinfo_sets, fd, flags, info, sz);
}
int
pfm_attach(int fd, int flags, int target)
{
+ if (_pfmlib_major_version < 3)
+ return -ENOSYS;
return (int)syscall(PFM_pfm_attach, fd, flags, target);
}
int
pfm_set_state(int fd, int flags, int state)
{
+ if (_pfmlib_major_version < 3)
+ return -ENOSYS;
return (int)syscall(PFM_pfm_set_state, fd, flags, state);
}
diff --git a/src/libpfm-3.y/lib/pfmlib_pentium4.c b/src/libpfm-3.y/lib/pfmlib_pentium4.c
index 3fda90abe2986d416e642ce6f410a132f4742c33..b7f15a651058d8ca74edd6c9cc1b88a6bf195064 100644
--- a/src/libpfm-3.y/lib/pfmlib_pentium4.c
+++ b/src/libpfm-3.y/lib/pfmlib_pentium4.c
@@ -26,7 +26,9 @@
* Support for libpfm for the Pentium4/Xeon/EM64T processor family (family=15).
*/
-#define _GNU_SOURCE
+#ifndef _GNU_SOURCE
+ #define _GNU_SOURCE /* for getline */
+#endif
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
@@ -113,6 +115,9 @@ static p4_regmap_t p4_pmc_regmap[]={
/* 64 */ P4_REGMAP(0x3f1, "PEBS_ENABLE"),
};
+#define PMC_PEBS_MATRIX_VERT 63
+#define PMC_PEBS_ENABLE 64
+
static p4_regmap_t p4_pmd_regmap[]={
/* 0 */ P4_REGMAP(0x300, "BPU_CTR0"),
/* 1 */ P4_REGMAP(0x301, "BPU_CTR1"),
@@ -134,6 +139,52 @@ static p4_regmap_t p4_pmd_regmap[]={
/* 17 */ P4_REGMAP(0x311, "IQ_CTR5"),
};
+/* This array provides values for the PEBS_ENABLE and PEBS_MATRIX_VERT
+ registers to support a series of metric for replay_event.
+ The first two entries are dummies; the remaining 9 correspond to
+ virtual bit masks in the replay_event definition and map onto Intel
+ documentation.
+*/
+
+#define P4_REPLAY_REAL_MASK 0x00000003
+#define P4_REPLAY_VIRT_MASK 0x00000FFC
+
+static pentium4_replay_regs_t p4_replay_regs[]={
+/* 0 */ {.enb = 0, /* dummy */
+ .mat_vert = 0,
+ },
+/* 1 */ {.enb = 0, /* dummy */
+ .mat_vert = 0,
+ },
+/* 2 */ {.enb = 0x01000001, /* 1stL_cache_load_miss_retired */
+ .mat_vert = 0x00000001,
+ },
+/* 3 */ {.enb = 0x01000002, /* 2ndL_cache_load_miss_retired */
+ .mat_vert = 0x00000001,
+ },
+/* 4 */ {.enb = 0x01000004, /* DTLB_load_miss_retired */
+ .mat_vert = 0x00000001,
+ },
+/* 5 */ {.enb = 0x01000004, /* DTLB_store_miss_retired */
+ .mat_vert = 0x00000002,
+ },
+/* 6 */ {.enb = 0x01000004, /* DTLB_all_miss_retired */
+ .mat_vert = 0x00000003,
+ },
+/* 7 */ {.enb = 0x01018001, /* Tagged_mispred_branch */
+ .mat_vert = 0x00000010,
+ },
+/* 8 */ {.enb = 0x01000200, /* MOB_load_replay_retired */
+ .mat_vert = 0x00000001,
+ },
+/* 9 */ {.enb = 0x01000400, /* split_load_retired */
+ .mat_vert = 0x00000001,
+ },
+/* 10 */ {.enb = 0x01000400, /* split_store_retired */
+ .mat_vert = 0x00000002,
+ },
+};
+
static int p4_model;
/**
@@ -270,7 +321,7 @@ static int pentium4_dispatch_events(pfmlib_input_param_t *input,
{
unsigned int assigned_pmcs[PENTIUM4_NUM_PMCS] = {0};
unsigned int event, event_mask, mask;
- unsigned int tag_value, tag_enable;
+ unsigned int bit, tag_value, tag_enable;
unsigned int plm;
unsigned int i, j, k, m, n;
int escr, escr_pmc;
@@ -361,13 +412,14 @@ static int pentium4_dispatch_events(pfmlib_input_param_t *input,
tag_enable = 0;
for (n = 0; n < input->pfp_events[i].num_masks; n++) {
mask = input->pfp_events[i].unit_masks[n];
- if (mask < EVENT_MASK_BITS &&
- pentium4_events[event].event_masks[mask].name) {
- event_mask |= (1 << pentium4_events[event].event_masks[mask].bit);
+ bit = pentium4_events[event].event_masks[mask].bit;
+ if (bit < EVENT_MASK_BITS &&
+ pentium4_events[event].event_masks[mask].name) {
+ event_mask |= (1 << bit);
}
- if (mask >= EVENT_MASK_BITS &&
- pentium4_events[event].event_masks[mask].name) {
- tag_value |= (1 << (pentium4_events[event].event_masks[mask].bit - EVENT_MASK_BITS));
+ if (bit >= EVENT_MASK_BITS &&
+ pentium4_events[event].event_masks[mask].name) {
+ tag_value |= (1 << (bit - EVENT_MASK_BITS));
tag_enable = 1;
}
}
@@ -404,7 +456,32 @@ static int pentium4_dispatch_events(pfmlib_input_param_t *input,
cccr_value.bits.cascade = 0; /* FIXME: How do we handle "cascading" counters? */
cccr_value.bits.overflow = 0;
- /* Set up the PMCs in the
+ /* Special processing for the replay event:
+ Remove virtual mask bits from actual mask;
+ scan mask bit list and OR bit values for each virtual mask
+ into the PEBS ENABLE and PEBS MATRIX VERT registers */
+ if (event == PME_REPLAY_EVENT) {
+ escr_value.bits.event_mask &= P4_REPLAY_REAL_MASK; /* remove virtual mask bits */
+ if (event_mask & P4_REPLAY_VIRT_MASK) { /* find a valid virtual mask */
+ output->pfp_pmcs[j].reg_value = 0;
+ output->pfp_pmcs[j].reg_num = PMC_PEBS_ENABLE;
+ output->pfp_pmcs[j].reg_addr = p4_pmc_regmap[PMC_PEBS_ENABLE].addr;
+ output->pfp_pmcs[j+1].reg_value = 0;
+ output->pfp_pmcs[j+1].reg_num = PMC_PEBS_MATRIX_VERT;
+ output->pfp_pmcs[j+1].reg_addr = p4_pmc_regmap[PMC_PEBS_MATRIX_VERT].addr;
+ for (n = 0; n < input->pfp_events[i].num_masks; n++) {
+ mask = input->pfp_events[i].unit_masks[n];
+ if (mask > 1 && mask < 11) { /* process each valid mask we find */
+ output->pfp_pmcs[j].reg_value |= p4_replay_regs[mask].enb;
+ output->pfp_pmcs[j+1].reg_value |= p4_replay_regs[mask].mat_vert;
+ }
+ }
+ j += 2;
+ output->pfp_pmc_count += 2;
+ }
+ }
+
+ /* Set up the PMCs in the
* output->pfp_pmcs array.
*/
output->pfp_pmcs[j].reg_num = escr_pmc;
diff --git a/src/libpfm-3.y/lib/pfmlib_pentium4_priv.h b/src/libpfm-3.y/lib/pfmlib_pentium4_priv.h
index dd71d635f1081dc5838f8b580ac030b14134b171..2c36547d6b529cc478b708d7a0f3d6a91a6c10e7 100644
--- a/src/libpfm-3.y/lib/pfmlib_pentium4_priv.h
+++ b/src/libpfm-3.y/lib/pfmlib_pentium4_priv.h
@@ -86,6 +86,28 @@ typedef struct {
int allowed_escrs[MAX_ESCRS_PER_CCCR];
} pentium4_cccr_reg_t;
+/**
+ * pentium4_replay_regs_t
+ *
+ * Describe one pair of PEBS registers for use with the replay_event event.
+ *
+ * "p4_replay_regs" is a flat array of these structures
+ * that defines all the PEBS pairs per Table A-10 of
+ * the Intel System Programming Guide Vol 3B.
+ *
+ * @enb: value for the PEBS_ENABLE register for a given replay metric.
+ * @mat_vert: value for the PEBS_MATRIX_VERT register for a given metric.
+ * The replay_event event defines a series of virtual mask bits
+ * that serve as indexes into this array. The values at that index
+ * provide information programmed into the PEBS registers to count
+ * specific metrics available to the replay_event event.
+ **/
+
+typedef struct {
+ int enb;
+ int mat_vert;
+} pentium4_replay_regs_t;
+
/**
* pentium4_pmc_t
*
diff --git a/src/libpfm-3.y/lib/pfmlib_power4_priv.h b/src/libpfm-3.y/lib/pfmlib_power4_priv.h
index 995c69c6d1cf519967d2bc43c8e5b87dff283f6d..85f8ec21f5d4785639819954ff92322c065834ad 100644
--- a/src/libpfm-3.y/lib/pfmlib_power4_priv.h
+++ b/src/libpfm-3.y/lib/pfmlib_power4_priv.h
@@ -25,23 +25,6 @@
#define POWER4_NUM_GROUP_VEC 1
#define POWER4_NUM_CONTROL_REGS 3
-typedef struct {
- char *pme_name;
- char *pme_short_desc;
- char *pme_long_desc;
- int pme_event_ids[POWER4_NUM_EVENT_COUNTERS];
- unsigned long long pme_group_vector[POWER4_NUM_GROUP_VEC];
-} pme_power4_entry_t;
-
-typedef struct {
- char *pmg_name;
- char *pmg_desc;
- int pmg_event_ids[POWER4_NUM_EVENT_COUNTERS];
- unsigned long long pmg_mmcr0;
- unsigned long long pmg_mmcr1;
- unsigned long long pmg_mmcra;
-} pmg_power4_group_t;
-
#endif
diff --git a/src/libpfm-3.y/lib/pfmlib_power5+_priv.h b/src/libpfm-3.y/lib/pfmlib_power5+_priv.h
index 891ea0eef57f186b25184042cb27e8a46630d351..a51fafc77b49a5d08f60f88016c625b1653ff4bc 100644
--- a/src/libpfm-3.y/lib/pfmlib_power5+_priv.h
+++ b/src/libpfm-3.y/lib/pfmlib_power5+_priv.h
@@ -25,23 +25,6 @@
#define POWER5p_NUM_GROUP_VEC 3
#define POWER5p_NUM_CONTROL_REGS 3
-typedef struct {
- char *pme_name;
- char *pme_short_desc;
- char *pme_long_desc;
- int pme_event_ids[POWER5p_NUM_EVENT_COUNTERS];
- unsigned long long pme_group_vector[POWER5p_NUM_GROUP_VEC];
-} pme_power5p_entry_t;
-
-typedef struct {
- char *pmg_name;
- char *pmg_desc;
- int pmg_event_ids[POWER5p_NUM_EVENT_COUNTERS];
- unsigned long long pmg_mmcr0;
- unsigned long long pmg_mmcr1;
- unsigned long long pmg_mmcra;
-} pmg_power5p_group_t;
-
#endif
diff --git a/src/libpfm-3.y/lib/pfmlib_power5_priv.h b/src/libpfm-3.y/lib/pfmlib_power5_priv.h
index 078bab008a02c4aee3f7bcf46b1aeae625e9a1d8..3da1c9ad8506468b0c3283f3ca3684afe8d0b0e5 100644
--- a/src/libpfm-3.y/lib/pfmlib_power5_priv.h
+++ b/src/libpfm-3.y/lib/pfmlib_power5_priv.h
@@ -25,23 +25,6 @@
#define POWER5_NUM_GROUP_VEC 3
#define POWER5_NUM_CONTROL_REGS 3
-typedef struct {
- char *pme_name;
- char *pme_short_desc;
- char *pme_long_desc;
- int pme_event_ids[POWER5_NUM_EVENT_COUNTERS];
- unsigned long long pme_group_vector[POWER5_NUM_GROUP_VEC];
-} pme_power5_entry_t;
-
-typedef struct {
- char *pmg_name;
- char *pmg_desc;
- int pmg_event_ids[POWER5_NUM_EVENT_COUNTERS];
- unsigned long long pmg_mmcr0;
- unsigned long long pmg_mmcr1;
- unsigned long long pmg_mmcra;
-} pmg_power5_group_t;
-
#endif
diff --git a/src/libpfm-3.y/lib/pfmlib_power6_priv.h b/src/libpfm-3.y/lib/pfmlib_power6_priv.h
index 4881cd4d2e2116fc9f64e3c13909d52e698daa5d..31ca536b9a77cda9d8e0e5330e72b8b5b1069952 100644
--- a/src/libpfm-3.y/lib/pfmlib_power6_priv.h
+++ b/src/libpfm-3.y/lib/pfmlib_power6_priv.h
@@ -25,23 +25,6 @@
#define POWER6_NUM_GROUP_VEC 4
#define POWER6_NUM_CONTROL_REGS 3
-typedef struct {
- char *pme_name;
- char *pme_short_desc;
- char *pme_long_desc;
- int pme_event_ids[POWER6_NUM_EVENT_COUNTERS];
- unsigned long long pme_group_vector[POWER6_NUM_GROUP_VEC];
-} pme_power6_entry_t;
-
-typedef struct {
- char *pmg_name;
- char *pmg_desc;
- int pmg_event_ids[POWER6_NUM_EVENT_COUNTERS];
- unsigned long long pmg_mmcr0;
- unsigned long long pmg_mmcr1;
- unsigned long long pmg_mmcra;
-} pmg_power6_group_t;
-
#endif
diff --git a/src/libpfm-3.y/lib/pfmlib_ppc970_priv.h b/src/libpfm-3.y/lib/pfmlib_ppc970_priv.h
index f07ac005f993f64b8b9201b081b515133374f13e..eb90b1327b5a0b9c1f638e84363a4bde022a9587 100644
--- a/src/libpfm-3.y/lib/pfmlib_ppc970_priv.h
+++ b/src/libpfm-3.y/lib/pfmlib_ppc970_priv.h
@@ -25,23 +25,6 @@
#define PPC970_NUM_GROUP_VEC 1
#define PPC970_NUM_CONTROL_REGS 3
-typedef struct {
- char *pme_name;
- char *pme_short_desc;
- char *pme_long_desc;
- int pme_event_ids[PPC970_NUM_EVENT_COUNTERS];
- unsigned long long pme_group_vector[PPC970_NUM_GROUP_VEC];
-} pme_ppc970_entry_t;
-
-typedef struct {
- char *pmg_name;
- char *pmg_desc;
- int pmg_event_ids[PPC970_NUM_EVENT_COUNTERS];
- unsigned long long pmg_mmcr0;
- unsigned long long pmg_mmcr1;
- unsigned long long pmg_mmcra;
-} pmg_ppc970_group_t;
-
#endif
diff --git a/src/libpfm-3.y/lib/pfmlib_ppc970mp_priv.h b/src/libpfm-3.y/lib/pfmlib_ppc970mp_priv.h
index 28a4833ccd884450d59e4b2f9c540158da239a0d..759977cf537efbc7cb25b77a652e5d70d6d5806b 100644
--- a/src/libpfm-3.y/lib/pfmlib_ppc970mp_priv.h
+++ b/src/libpfm-3.y/lib/pfmlib_ppc970mp_priv.h
@@ -25,23 +25,6 @@
#define PPC970MP_NUM_GROUP_VEC 1
#define PPC970MP_NUM_CONTROL_REGS 3
-typedef struct {
- char *pme_name;
- char *pme_short_desc;
- char *pme_long_desc;
- int pme_event_ids[PPC970MP_NUM_EVENT_COUNTERS];
- unsigned long long pme_group_vector[PPC970MP_NUM_GROUP_VEC];
-} pme_ppc970mp_entry_t;
-
-typedef struct {
- char *pmg_name;
- char *pmg_desc;
- int pmg_event_ids[PPC970MP_NUM_EVENT_COUNTERS];
- unsigned long long pmg_mmcr0;
- unsigned long long pmg_mmcr1;
- unsigned long long pmg_mmcra;
-} pmg_ppc970mp_group_t;
-
#endif
diff --git a/src/libpfm-3.y/lib/pfmlib_priv.c b/src/libpfm-3.y/lib/pfmlib_priv.c
index 7cc3c7c47aaa12c878c19ef00c5d524bb7bfddc7..045f985502e2bff2717716d155d9fb7d3c2ae6ee 100644
--- a/src/libpfm-3.y/lib/pfmlib_priv.c
+++ b/src/libpfm-3.y/lib/pfmlib_priv.c
@@ -21,7 +21,6 @@
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
-#define _GNU_SOURCE /* for getline */
#include <sys/types.h>
#include <ctype.h>
#include <string.h>
@@ -34,6 +33,14 @@
#include "pfmlib_priv.h"
+/*
+ * file for all libpfm verbose and debug output
+ *
+ * By default, it is set to stderr, unless the
+ * PFMLIB_DEBUG_STDOUT environment variable is set
+ */
+FILE *libpfm_fp;
+
/*
* by convention all internal utility function must be prefixed by __
*/
@@ -50,72 +57,10 @@ __pfm_vbprintf(const char *fmt, ...)
return;
va_start(ap, fmt);
- vfprintf(stderr, fmt, ap);
+ vfprintf(libpfm_fp, fmt, ap);
va_end(ap);
}
-/*
- * helper function to retrieve one value from /proc/cpuinfo
- * for internal libpfm use only
- * attr: the attribute (line) to look for
- * ret_buf: a buffer to store the value of the attribute (as a string)
- * maxlen : number of bytes of capacity in ret_buf
- *
- * ret_buf is null terminated.
- *
- * Return:
- * 0 : attribute found, ret_buf populated
- * -1: attribute not found
- */
-int
-__pfm_getcpuinfo_attr(const char *attr, char *ret_buf, size_t maxlen)
-{
- FILE *fp = NULL;
- int ret = -1;
- size_t attr_len, buf_len = 0;
- char *p, *value = NULL;
- char *buffer = NULL;
-
- if (attr == NULL || ret_buf == NULL || maxlen < 1)
- return -1;
-
- attr_len = strlen(attr);
-
- fp = fopen("/proc/cpuinfo", "r");
- if (fp == NULL)
- return -1;
-
- while(getline(&buffer, &buf_len, fp) != -1){
-
- /* skip blank lines */
- if (*buffer == '\n')
- continue;
-
- p = strchr(buffer, ':');
- if (p == NULL)
- goto error;
-
- /*
- * p+2: +1 = space, +2= firt character
- * strlen()-1 gets rid of \n
- */
- *p = '\0';
- value = p+2;
-
- value[strlen(value)-1] = '\0';
-
- if (!strncmp(attr, buffer, attr_len))
- break;
- }
- strncpy(ret_buf, value, maxlen-1);
- ret_buf[maxlen-1] = '\0';
- ret = 0;
-error:
- free(buffer);
- fclose(fp);
- return ret;
-}
-
int
__pfm_check_event(pfmlib_event_t *e)
{
@@ -132,6 +77,17 @@ __pfm_check_event(pfmlib_event_t *e)
if (e->unit_masks[j] >= n)
return PFMLIB_ERR_UMASK;
}
- /* need to specify at least one umask */
- return n && j == 0 ? PFMLIB_ERR_UMASK : PFMLIB_SUCCESS;
+ /*
+ * if event has umask, but non specified by user, then
+ * return:
+ * - error if no default umask is defined
+ * - success if default umask exists for event
+ */
+ if (n && j == 0) {
+ if (pfm_current->has_umask_default
+ && pfm_current->has_umask_default(e->event))
+ return PFMLIB_SUCCESS;
+ return PFMLIB_ERR_UMASK;
+ }
+ return PFMLIB_SUCCESS;
}
diff --git a/src/libpfm-3.y/lib/pfmlib_sparc.c b/src/libpfm-3.y/lib/pfmlib_sparc.c
index ff2a06257bac9e3a7dd0c31dd74822b5d32842bf..60caf3f506aca0d73847e5050bac6d5d6588b68b 100644
--- a/src/libpfm-3.y/lib/pfmlib_sparc.c
+++ b/src/libpfm-3.y/lib/pfmlib_sparc.c
@@ -28,7 +28,9 @@
* Support for libpfm for Sparc processors.
*/
-#define _GNU_SOURCE
+#ifndef _GNU_SOURCE
+ #define _GNU_SOURCE /* for getline */
+#endif
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
@@ -517,7 +519,7 @@ pfm_sparc_get_inst_retired(pfmlib_event_t *e)
pfm_pmu_support_t sparc_support = {
/* the next 3 fields are initialized in pfm_sparc_pmu_detect */
.pmu_name = NULL,
- .pmu_type = 0,
+ .pmu_type = PFMLIB_UNKNOWN_PMU,
.pme_count = 0,
.pmd_count = 2,
diff --git a/src/libpfm-3.y/lib/power4_events.h b/src/libpfm-3.y/lib/power4_events.h
index 8fc16dc707913b09b596451ee06d9b39555a3106..cc7150c6b186830c5b2034347beaf1ddf5766e37 100644
--- a/src/libpfm-3.y/lib/power4_events.h
+++ b/src/libpfm-3.y/lib/power4_events.h
@@ -20,2211 +20,3261 @@
* hand.
*
*/
-static pme_power4_entry_t power4_pe[] = {
#define POWER4_PME_PM_MRK_LSU_SRQ_INST_VALID 0
+#define POWER4_PME_PM_FPU1_SINGLE 1
+#define POWER4_PME_PM_DC_PREF_OUT_STREAMS 2
+#define POWER4_PME_PM_FPU0_STALL3 3
+#define POWER4_PME_PM_TB_BIT_TRANS 4
+#define POWER4_PME_PM_GPR_MAP_FULL_CYC 5
+#define POWER4_PME_PM_MRK_ST_CMPL 6
+#define POWER4_PME_PM_MRK_LSU_FLUSH_LRQ 7
+#define POWER4_PME_PM_FPU0_STF 8
+#define POWER4_PME_PM_FPU1_FMA 9
+#define POWER4_PME_PM_L2SA_MOD_TAG 10
+#define POWER4_PME_PM_MRK_DATA_FROM_L275_SHR 11
+#define POWER4_PME_PM_1INST_CLB_CYC 12
+#define POWER4_PME_PM_LSU1_FLUSH_ULD 13
+#define POWER4_PME_PM_MRK_INST_FIN 14
+#define POWER4_PME_PM_MRK_LSU0_FLUSH_UST 15
+#define POWER4_PME_PM_FPU_FDIV 16
+#define POWER4_PME_PM_LSU_LRQ_S0_ALLOC 17
+#define POWER4_PME_PM_FPU0_FULL_CYC 18
+#define POWER4_PME_PM_FPU_SINGLE 19
+#define POWER4_PME_PM_FPU0_FMA 20
+#define POWER4_PME_PM_MRK_LSU1_FLUSH_ULD 21
+#define POWER4_PME_PM_LSU1_FLUSH_LRQ 22
+#define POWER4_PME_PM_L2SA_ST_HIT 23
+#define POWER4_PME_PM_L2SB_SHR_INV 24
+#define POWER4_PME_PM_DTLB_MISS 25
+#define POWER4_PME_PM_MRK_ST_MISS_L1 26
+#define POWER4_PME_PM_EXT_INT 27
+#define POWER4_PME_PM_MRK_LSU1_FLUSH_LRQ 28
+#define POWER4_PME_PM_MRK_ST_GPS 29
+#define POWER4_PME_PM_GRP_DISP_SUCCESS 30
+#define POWER4_PME_PM_LSU1_LDF 31
+#define POWER4_PME_PM_FAB_CMD_ISSUED 32
+#define POWER4_PME_PM_LSU0_SRQ_STFWD 33
+#define POWER4_PME_PM_CR_MAP_FULL_CYC 34
+#define POWER4_PME_PM_MRK_LSU0_FLUSH_ULD 35
+#define POWER4_PME_PM_LSU_DERAT_MISS 36
+#define POWER4_PME_PM_FPU0_SINGLE 37
+#define POWER4_PME_PM_FPU1_FDIV 38
+#define POWER4_PME_PM_FPU1_FEST 39
+#define POWER4_PME_PM_FPU0_FRSP_FCONV 40
+#define POWER4_PME_PM_MRK_ST_CMPL_INT 41
+#define POWER4_PME_PM_FXU_FIN 42
+#define POWER4_PME_PM_FPU_STF 43
+#define POWER4_PME_PM_DSLB_MISS 44
+#define POWER4_PME_PM_DATA_FROM_L275_SHR 45
+#define POWER4_PME_PM_FXLS1_FULL_CYC 46
+#define POWER4_PME_PM_L3B0_DIR_MIS 47
+#define POWER4_PME_PM_2INST_CLB_CYC 48
+#define POWER4_PME_PM_MRK_STCX_FAIL 49
+#define POWER4_PME_PM_LSU_LMQ_LHR_MERGE 50
+#define POWER4_PME_PM_FXU0_BUSY_FXU1_IDLE 51
+#define POWER4_PME_PM_L3B1_DIR_REF 52
+#define POWER4_PME_PM_MRK_LSU_FLUSH_UST 53
+#define POWER4_PME_PM_MRK_DATA_FROM_L25_SHR 54
+#define POWER4_PME_PM_LSU_FLUSH_ULD 55
+#define POWER4_PME_PM_MRK_BRU_FIN 56
+#define POWER4_PME_PM_IERAT_XLATE_WR 57
+#define POWER4_PME_PM_LSU0_BUSY 58
+#define POWER4_PME_PM_L2SA_ST_REQ 59
+#define POWER4_PME_PM_DATA_FROM_MEM 60
+#define POWER4_PME_PM_FPR_MAP_FULL_CYC 61
+#define POWER4_PME_PM_FPU1_FULL_CYC 62
+#define POWER4_PME_PM_FPU0_FIN 63
+#define POWER4_PME_PM_3INST_CLB_CYC 64
+#define POWER4_PME_PM_DATA_FROM_L35 65
+#define POWER4_PME_PM_L2SA_SHR_INV 66
+#define POWER4_PME_PM_MRK_LSU_FLUSH_SRQ 67
+#define POWER4_PME_PM_THRESH_TIMEO 68
+#define POWER4_PME_PM_FPU_FSQRT 69
+#define POWER4_PME_PM_MRK_LSU0_FLUSH_LRQ 70
+#define POWER4_PME_PM_FXLS0_FULL_CYC 71
+#define POWER4_PME_PM_DATA_TABLEWALK_CYC 72
+#define POWER4_PME_PM_FPU0_ALL 73
+#define POWER4_PME_PM_FPU0_FEST 74
+#define POWER4_PME_PM_DATA_FROM_L25_MOD 75
+#define POWER4_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 76
+#define POWER4_PME_PM_FPU_FEST 77
+#define POWER4_PME_PM_0INST_FETCH 78
+#define POWER4_PME_PM_LARX_LSU1 79
+#define POWER4_PME_PM_LD_MISS_L1_LSU0 80
+#define POWER4_PME_PM_L1_PREF 81
+#define POWER4_PME_PM_FPU1_STALL3 82
+#define POWER4_PME_PM_BRQ_FULL_CYC 83
+#define POWER4_PME_PM_LARX 84
+#define POWER4_PME_PM_MRK_DATA_FROM_L35 85
+#define POWER4_PME_PM_WORK_HELD 86
+#define POWER4_PME_PM_MRK_LD_MISS_L1_LSU0 87
+#define POWER4_PME_PM_FXU_IDLE 88
+#define POWER4_PME_PM_INST_CMPL 89
+#define POWER4_PME_PM_LSU1_FLUSH_UST 90
+#define POWER4_PME_PM_LSU0_FLUSH_ULD 91
+#define POWER4_PME_PM_INST_FROM_L2 92
+#define POWER4_PME_PM_DATA_FROM_L3 93
+#define POWER4_PME_PM_FPU0_DENORM 94
+#define POWER4_PME_PM_FPU1_FMOV_FEST 95
+#define POWER4_PME_PM_GRP_DISP_REJECT 96
+#define POWER4_PME_PM_INST_FETCH_CYC 97
+#define POWER4_PME_PM_LSU_LDF 98
+#define POWER4_PME_PM_INST_DISP 99
+#define POWER4_PME_PM_L2SA_MOD_INV 100
+#define POWER4_PME_PM_DATA_FROM_L25_SHR 101
+#define POWER4_PME_PM_FAB_CMD_RETRIED 102
+#define POWER4_PME_PM_L1_DCACHE_RELOAD_VALID 103
+#define POWER4_PME_PM_MRK_GRP_ISSUED 104
+#define POWER4_PME_PM_FPU_FULL_CYC 105
+#define POWER4_PME_PM_FPU_FMA 106
+#define POWER4_PME_PM_MRK_CRU_FIN 107
+#define POWER4_PME_PM_MRK_LSU1_FLUSH_UST 108
+#define POWER4_PME_PM_MRK_FXU_FIN 109
+#define POWER4_PME_PM_BR_ISSUED 110
+#define POWER4_PME_PM_EE_OFF 111
+#define POWER4_PME_PM_INST_FROM_L3 112
+#define POWER4_PME_PM_ITLB_MISS 113
+#define POWER4_PME_PM_FXLS_FULL_CYC 114
+#define POWER4_PME_PM_FXU1_BUSY_FXU0_IDLE 115
+#define POWER4_PME_PM_GRP_DISP_VALID 116
+#define POWER4_PME_PM_L2SC_ST_HIT 117
+#define POWER4_PME_PM_MRK_GRP_DISP 118
+#define POWER4_PME_PM_L2SB_MOD_TAG 119
+#define POWER4_PME_PM_INST_FROM_L25_L275 120
+#define POWER4_PME_PM_LSU_FLUSH_UST 121
+#define POWER4_PME_PM_L2SB_ST_HIT 122
+#define POWER4_PME_PM_FXU1_FIN 123
+#define POWER4_PME_PM_L3B1_DIR_MIS 124
+#define POWER4_PME_PM_4INST_CLB_CYC 125
+#define POWER4_PME_PM_GRP_CMPL 126
+#define POWER4_PME_PM_DC_PREF_L2_CLONE_L3 127
+#define POWER4_PME_PM_FPU_FRSP_FCONV 128
+#define POWER4_PME_PM_5INST_CLB_CYC 129
+#define POWER4_PME_PM_MRK_LSU0_FLUSH_SRQ 130
+#define POWER4_PME_PM_MRK_LSU_FLUSH_ULD 131
+#define POWER4_PME_PM_8INST_CLB_CYC 132
+#define POWER4_PME_PM_LSU_LMQ_FULL_CYC 133
+#define POWER4_PME_PM_ST_REF_L1_LSU0 134
+#define POWER4_PME_PM_LSU0_DERAT_MISS 135
+#define POWER4_PME_PM_LSU_SRQ_SYNC_CYC 136
+#define POWER4_PME_PM_FPU_STALL3 137
+#define POWER4_PME_PM_MRK_DATA_FROM_L2 138
+#define POWER4_PME_PM_FPU0_FMOV_FEST 139
+#define POWER4_PME_PM_LSU0_FLUSH_SRQ 140
+#define POWER4_PME_PM_LD_REF_L1_LSU0 141
+#define POWER4_PME_PM_L2SC_SHR_INV 142
+#define POWER4_PME_PM_LSU1_FLUSH_SRQ 143
+#define POWER4_PME_PM_LSU_LMQ_S0_ALLOC 144
+#define POWER4_PME_PM_ST_REF_L1 145
+#define POWER4_PME_PM_LSU_SRQ_EMPTY_CYC 146
+#define POWER4_PME_PM_FPU1_STF 147
+#define POWER4_PME_PM_L3B0_DIR_REF 148
+#define POWER4_PME_PM_RUN_CYC 149
+#define POWER4_PME_PM_LSU_LMQ_S0_VALID 150
+#define POWER4_PME_PM_LSU_LRQ_S0_VALID 151
+#define POWER4_PME_PM_LSU0_LDF 152
+#define POWER4_PME_PM_MRK_IMR_RELOAD 153
+#define POWER4_PME_PM_7INST_CLB_CYC 154
+#define POWER4_PME_PM_MRK_GRP_TIMEO 155
+#define POWER4_PME_PM_FPU_FMOV_FEST 156
+#define POWER4_PME_PM_GRP_DISP_BLK_SB_CYC 157
+#define POWER4_PME_PM_XER_MAP_FULL_CYC 158
+#define POWER4_PME_PM_ST_MISS_L1 159
+#define POWER4_PME_PM_STOP_COMPLETION 160
+#define POWER4_PME_PM_MRK_GRP_CMPL 161
+#define POWER4_PME_PM_ISLB_MISS 162
+#define POWER4_PME_PM_CYC 163
+#define POWER4_PME_PM_LD_MISS_L1_LSU1 164
+#define POWER4_PME_PM_STCX_FAIL 165
+#define POWER4_PME_PM_LSU1_SRQ_STFWD 166
+#define POWER4_PME_PM_GRP_DISP 167
+#define POWER4_PME_PM_DATA_FROM_L2 168
+#define POWER4_PME_PM_L2_PREF 169
+#define POWER4_PME_PM_FPU0_FPSCR 170
+#define POWER4_PME_PM_FPU1_DENORM 171
+#define POWER4_PME_PM_MRK_DATA_FROM_L25_MOD 172
+#define POWER4_PME_PM_L2SB_ST_REQ 173
+#define POWER4_PME_PM_L2SB_MOD_INV 174
+#define POWER4_PME_PM_FPU0_FSQRT 175
+#define POWER4_PME_PM_LD_REF_L1 176
+#define POWER4_PME_PM_MRK_L1_RELOAD_VALID 177
+#define POWER4_PME_PM_L2SB_SHR_MOD 178
+#define POWER4_PME_PM_INST_FROM_L1 179
+#define POWER4_PME_PM_1PLUS_PPC_CMPL 180
+#define POWER4_PME_PM_EE_OFF_EXT_INT 181
+#define POWER4_PME_PM_L2SC_SHR_MOD 182
+#define POWER4_PME_PM_LSU_LRQ_FULL_CYC 183
+#define POWER4_PME_PM_IC_PREF_INSTALL 184
+#define POWER4_PME_PM_MRK_LSU1_FLUSH_SRQ 185
+#define POWER4_PME_PM_GCT_FULL_CYC 186
+#define POWER4_PME_PM_INST_FROM_MEM 187
+#define POWER4_PME_PM_FXU_BUSY 188
+#define POWER4_PME_PM_ST_REF_L1_LSU1 189
+#define POWER4_PME_PM_MRK_LD_MISS_L1 190
+#define POWER4_PME_PM_MRK_LSU1_INST_FIN 191
+#define POWER4_PME_PM_L1_WRITE_CYC 192
+#define POWER4_PME_PM_BIQ_IDU_FULL_CYC 193
+#define POWER4_PME_PM_MRK_LSU0_INST_FIN 194
+#define POWER4_PME_PM_L2SC_ST_REQ 195
+#define POWER4_PME_PM_LSU1_BUSY 196
+#define POWER4_PME_PM_FPU_ALL 197
+#define POWER4_PME_PM_LSU_SRQ_S0_ALLOC 198
+#define POWER4_PME_PM_GRP_MRK 199
+#define POWER4_PME_PM_FPU1_FIN 200
+#define POWER4_PME_PM_DC_PREF_STREAM_ALLOC 201
+#define POWER4_PME_PM_BR_MPRED_CR 202
+#define POWER4_PME_PM_BR_MPRED_TA 203
+#define POWER4_PME_PM_CRQ_FULL_CYC 204
+#define POWER4_PME_PM_INST_FROM_PREF 205
+#define POWER4_PME_PM_LD_MISS_L1 206
+#define POWER4_PME_PM_STCX_PASS 207
+#define POWER4_PME_PM_DC_INV_L2 208
+#define POWER4_PME_PM_LSU_SRQ_FULL_CYC 209
+#define POWER4_PME_PM_LSU0_FLUSH_LRQ 210
+#define POWER4_PME_PM_LSU_SRQ_S0_VALID 211
+#define POWER4_PME_PM_LARX_LSU0 212
+#define POWER4_PME_PM_GCT_EMPTY_CYC 213
+#define POWER4_PME_PM_FPU1_ALL 214
+#define POWER4_PME_PM_FPU1_FSQRT 215
+#define POWER4_PME_PM_FPU_FIN 216
+#define POWER4_PME_PM_L2SA_SHR_MOD 217
+#define POWER4_PME_PM_MRK_LD_MISS_L1_LSU1 218
+#define POWER4_PME_PM_LSU_SRQ_STFWD 219
+#define POWER4_PME_PM_FXU0_FIN 220
+#define POWER4_PME_PM_MRK_FPU_FIN 221
+#define POWER4_PME_PM_LSU_BUSY 222
+#define POWER4_PME_PM_INST_FROM_L35 223
+#define POWER4_PME_PM_FPU1_FRSP_FCONV 224
+#define POWER4_PME_PM_SNOOP_TLBIE 225
+#define POWER4_PME_PM_FPU0_FDIV 226
+#define POWER4_PME_PM_LD_REF_L1_LSU1 227
+#define POWER4_PME_PM_MRK_DATA_FROM_L275_MOD 228
+#define POWER4_PME_PM_HV_CYC 229
+#define POWER4_PME_PM_6INST_CLB_CYC 230
+#define POWER4_PME_PM_LR_CTR_MAP_FULL_CYC 231
+#define POWER4_PME_PM_L2SC_MOD_INV 232
+#define POWER4_PME_PM_FPU_DENORM 233
+#define POWER4_PME_PM_DATA_FROM_L275_MOD 234
+#define POWER4_PME_PM_LSU1_DERAT_MISS 235
+#define POWER4_PME_PM_IC_PREF_REQ 236
+#define POWER4_PME_PM_MRK_LSU_FIN 237
+#define POWER4_PME_PM_MRK_DATA_FROM_L3 238
+#define POWER4_PME_PM_MRK_DATA_FROM_MEM 239
+#define POWER4_PME_PM_LSU0_FLUSH_UST 240
+#define POWER4_PME_PM_LSU_FLUSH_LRQ 241
+#define POWER4_PME_PM_LSU_FLUSH_SRQ 242
+#define POWER4_PME_PM_L2SC_MOD_TAG 243
+
+
+static const int power4_event_ids[][POWER4_NUM_EVENT_COUNTERS] = {
+ [ POWER4_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { -1, -1, 68, 68, -1, -1, 68, 68 },
+ [ POWER4_PME_PM_FPU1_SINGLE ] = { 23, 23, -1, -1, 23, 23, -1, -1 },
+ [ POWER4_PME_PM_DC_PREF_OUT_STREAMS ] = { -1, -1, 14, 14, -1, -1, 14, 14 },
+ [ POWER4_PME_PM_FPU0_STALL3 ] = { 15, 15, -1, -1, 15, 15, -1, -1 },
+ [ POWER4_PME_PM_TB_BIT_TRANS ] = { -1, -1, -1, -1, -1, -1, -1, 86 },
+ [ POWER4_PME_PM_GPR_MAP_FULL_CYC ] = { -1, -1, 33, 33, -1, -1, 33, 33 },
+ [ POWER4_PME_PM_MRK_ST_CMPL ] = { 93, -1, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_MRK_LSU_FLUSH_LRQ ] = { -1, -1, 81, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_FPU0_STF ] = { 16, 16, -1, -1, 16, 16, -1, -1 },
+ [ POWER4_PME_PM_FPU1_FMA ] = { 20, 20, -1, -1, 20, 20, -1, -1 },
+ [ POWER4_PME_PM_L2SA_MOD_TAG ] = { 38, 38, -1, -1, 38, 38, -1, -1 },
+ [ POWER4_PME_PM_MRK_DATA_FROM_L275_SHR ] = { -1, -1, -1, -1, -1, 90, -1, -1 },
+ [ POWER4_PME_PM_1INST_CLB_CYC ] = { -1, -1, 0, 0, -1, -1, 0, 0 },
+ [ POWER4_PME_PM_LSU1_FLUSH_ULD ] = { 63, 63, -1, -1, 63, 63, -1, -1 },
+ [ POWER4_PME_PM_MRK_INST_FIN ] = { -1, -1, -1, -1, -1, -1, 82, -1 },
+ [ POWER4_PME_PM_MRK_LSU0_FLUSH_UST ] = { -1, -1, 61, 61, -1, -1, 61, 61 },
+ [ POWER4_PME_PM_FPU_FDIV ] = { 84, -1, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_LSU_LRQ_S0_ALLOC ] = { 68, 68, -1, -1, 68, 68, -1, -1 },
+ [ POWER4_PME_PM_FPU0_FULL_CYC ] = { 13, 13, -1, -1, 13, 13, -1, -1 },
+ [ POWER4_PME_PM_FPU_SINGLE ] = { -1, -1, -1, -1, 87, -1, -1, -1 },
+ [ POWER4_PME_PM_FPU0_FMA ] = { 11, 11, -1, -1, 11, 11, -1, -1 },
+ [ POWER4_PME_PM_MRK_LSU1_FLUSH_ULD ] = { -1, -1, 65, 65, -1, -1, 65, 65 },
+ [ POWER4_PME_PM_LSU1_FLUSH_LRQ ] = { 61, 61, -1, -1, 61, 61, -1, -1 },
+ [ POWER4_PME_PM_L2SA_ST_HIT ] = { -1, -1, 37, 37, -1, -1, 37, 37 },
+ [ POWER4_PME_PM_L2SB_SHR_INV ] = { 43, 43, -1, -1, 43, 43, -1, -1 },
+ [ POWER4_PME_PM_DTLB_MISS ] = { 6, 6, -1, -1, 6, 6, -1, -1 },
+ [ POWER4_PME_PM_MRK_ST_MISS_L1 ] = { 76, 76, -1, -1, 76, 76, -1, -1 },
+ [ POWER4_PME_PM_EXT_INT ] = { -1, -1, -1, -1, -1, -1, -1, 76 },
+ [ POWER4_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { -1, -1, 63, 63, -1, -1, 63, 63 },
+ [ POWER4_PME_PM_MRK_ST_GPS ] = { -1, -1, -1, -1, -1, 93, -1, -1 },
+ [ POWER4_PME_PM_GRP_DISP_SUCCESS ] = { -1, -1, -1, -1, 89, -1, -1, -1 },
+ [ POWER4_PME_PM_LSU1_LDF ] = { -1, -1, 20, 20, -1, -1, 20, 20 },
+ [ POWER4_PME_PM_FAB_CMD_ISSUED ] = { -1, -1, 17, 17, -1, -1, 17, 17 },
+ [ POWER4_PME_PM_LSU0_SRQ_STFWD ] = { 59, 59, -1, -1, 59, 59, -1, -1 },
+ [ POWER4_PME_PM_CR_MAP_FULL_CYC ] = { 2, 2, -1, -1, 2, 2, -1, -1 },
+ [ POWER4_PME_PM_MRK_LSU0_FLUSH_ULD ] = { -1, -1, 60, 60, -1, -1, 60, 60 },
+ [ POWER4_PME_PM_LSU_DERAT_MISS ] = { -1, -1, -1, -1, -1, 88, -1, -1 },
+ [ POWER4_PME_PM_FPU0_SINGLE ] = { 14, 14, -1, -1, 14, 14, -1, -1 },
+ [ POWER4_PME_PM_FPU1_FDIV ] = { 19, 19, -1, -1, 19, 19, -1, -1 },
+ [ POWER4_PME_PM_FPU1_FEST ] = { -1, -1, 26, 26, -1, -1, 26, 26 },
+ [ POWER4_PME_PM_FPU0_FRSP_FCONV ] = { -1, -1, 25, 25, -1, -1, 25, 25 },
+ [ POWER4_PME_PM_MRK_ST_CMPL_INT ] = { -1, -1, 82, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_FXU_FIN ] = { -1, -1, 77, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_FPU_STF ] = { -1, -1, -1, -1, -1, 84, -1, -1 },
+ [ POWER4_PME_PM_DSLB_MISS ] = { 5, 5, -1, -1, 5, 5, -1, -1 },
+ [ POWER4_PME_PM_DATA_FROM_L275_SHR ] = { -1, -1, -1, -1, -1, 82, -1, -1 },
+ [ POWER4_PME_PM_FXLS1_FULL_CYC ] = { -1, -1, 85, 86, -1, -1, 85, 87 },
+ [ POWER4_PME_PM_L3B0_DIR_MIS ] = { 49, 49, -1, -1, 49, 49, -1, -1 },
+ [ POWER4_PME_PM_2INST_CLB_CYC ] = { -1, -1, 1, 1, -1, -1, 1, 1 },
+ [ POWER4_PME_PM_MRK_STCX_FAIL ] = { 75, 75, -1, -1, 75, 75, -1, -1 },
+ [ POWER4_PME_PM_LSU_LMQ_LHR_MERGE ] = { 67, 67, -1, -1, 67, 67, -1, -1 },
+ [ POWER4_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { -1, -1, -1, -1, -1, -1, 76, -1 },
+ [ POWER4_PME_PM_L3B1_DIR_REF ] = { 52, 52, -1, -1, 52, 52, -1, -1 },
+ [ POWER4_PME_PM_MRK_LSU_FLUSH_UST ] = { -1, -1, -1, -1, -1, -1, 83, -1 },
+ [ POWER4_PME_PM_MRK_DATA_FROM_L25_SHR ] = { -1, -1, -1, -1, 93, -1, -1, -1 },
+ [ POWER4_PME_PM_LSU_FLUSH_ULD ] = { 88, -1, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_MRK_BRU_FIN ] = { -1, 89, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_IERAT_XLATE_WR ] = { 31, 31, -1, -1, 31, 31, -1, -1 },
+ [ POWER4_PME_PM_LSU0_BUSY ] = { -1, -1, 50, 50, -1, -1, 50, 50 },
+ [ POWER4_PME_PM_L2SA_ST_REQ ] = { -1, -1, 38, 38, -1, -1, 38, 38 },
+ [ POWER4_PME_PM_DATA_FROM_MEM ] = { -1, 82, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_FPR_MAP_FULL_CYC ] = { 7, 7, -1, -1, 7, 7, -1, -1 },
+ [ POWER4_PME_PM_FPU1_FULL_CYC ] = { 22, 22, -1, -1, 22, 22, -1, -1 },
+ [ POWER4_PME_PM_FPU0_FIN ] = { -1, -1, 22, 22, -1, -1, 22, 22 },
+ [ POWER4_PME_PM_3INST_CLB_CYC ] = { -1, -1, 2, 2, -1, -1, 2, 2 },
+ [ POWER4_PME_PM_DATA_FROM_L35 ] = { -1, -1, 74, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_L2SA_SHR_INV ] = { 39, 39, -1, -1, 39, 39, -1, -1 },
+ [ POWER4_PME_PM_MRK_LSU_FLUSH_SRQ ] = { -1, -1, -1, 85, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_THRESH_TIMEO ] = { -1, 91, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_FPU_FSQRT ] = { -1, -1, -1, -1, -1, 83, -1, -1 },
+ [ POWER4_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { -1, -1, 58, 58, -1, -1, 58, 58 },
+ [ POWER4_PME_PM_FXLS0_FULL_CYC ] = { -1, -1, 30, 30, -1, -1, 30, 30 },
+ [ POWER4_PME_PM_DATA_TABLEWALK_CYC ] = { -1, -1, 12, 12, -1, -1, 12, 12 },
+ [ POWER4_PME_PM_FPU0_ALL ] = { 8, 8, -1, -1, 8, 8, -1, -1 },
+ [ POWER4_PME_PM_FPU0_FEST ] = { -1, -1, 21, 21, -1, -1, 21, 21 },
+ [ POWER4_PME_PM_DATA_FROM_L25_MOD ] = { -1, -1, -1, -1, -1, -1, -1, 75 },
+ [ POWER4_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { -1, 88, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_FPU_FEST ] = { -1, -1, 75, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_0INST_FETCH ] = { -1, -1, -1, -1, -1, -1, -1, 73 },
+ [ POWER4_PME_PM_LARX_LSU1 ] = { -1, -1, 45, 45, -1, -1, 45, 45 },
+ [ POWER4_PME_PM_LD_MISS_L1_LSU0 ] = { -1, -1, 46, 46, -1, -1, 46, 46 },
+ [ POWER4_PME_PM_L1_PREF ] = { -1, -1, 35, 35, -1, -1, 35, 35 },
+ [ POWER4_PME_PM_FPU1_STALL3 ] = { 24, 24, -1, -1, 24, 24, -1, -1 },
+ [ POWER4_PME_PM_BRQ_FULL_CYC ] = { 1, 1, -1, -1, 1, 1, -1, -1 },
+ [ POWER4_PME_PM_LARX ] = { -1, -1, -1, 79, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_MRK_DATA_FROM_L35 ] = { -1, -1, 80, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_WORK_HELD ] = { -1, 92, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { 73, 73, -1, -1, 73, 73, -1, -1 },
+ [ POWER4_PME_PM_FXU_IDLE ] = { -1, -1, -1, -1, 88, -1, -1, -1 },
+ [ POWER4_PME_PM_INST_CMPL ] = { 86, -1, -1, 77, -1, 86, 78, 81 },
+ [ POWER4_PME_PM_LSU1_FLUSH_UST ] = { 64, 64, -1, -1, 64, 64, -1, -1 },
+ [ POWER4_PME_PM_LSU0_FLUSH_ULD ] = { 57, 57, -1, -1, 57, 57, -1, -1 },
+ [ POWER4_PME_PM_INST_FROM_L2 ] = { -1, -1, 78, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_DATA_FROM_L3 ] = { 82, -1, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_FPU0_DENORM ] = { 9, 9, -1, -1, 9, 9, -1, -1 },
+ [ POWER4_PME_PM_FPU1_FMOV_FEST ] = { -1, -1, 28, 28, -1, -1, 28, 28 },
+ [ POWER4_PME_PM_GRP_DISP_REJECT ] = { 27, 27, -1, -1, 27, 27, -1, 80 },
+ [ POWER4_PME_PM_INST_FETCH_CYC ] = { 33, 33, -1, -1, 33, 33, -1, -1 },
+ [ POWER4_PME_PM_LSU_LDF ] = { -1, -1, -1, -1, -1, -1, -1, 78 },
+ [ POWER4_PME_PM_INST_DISP ] = { 32, 32, -1, -1, 32, 32, -1, -1 },
+ [ POWER4_PME_PM_L2SA_MOD_INV ] = { 37, 37, -1, -1, 37, 37, -1, -1 },
+ [ POWER4_PME_PM_DATA_FROM_L25_SHR ] = { -1, -1, -1, -1, 83, -1, -1, -1 },
+ [ POWER4_PME_PM_FAB_CMD_RETRIED ] = { -1, -1, 18, 18, -1, -1, 18, 18 },
+ [ POWER4_PME_PM_L1_DCACHE_RELOAD_VALID ] = { 36, 36, -1, -1, 36, 36, -1, -1 },
+ [ POWER4_PME_PM_MRK_GRP_ISSUED ] = { -1, -1, -1, -1, -1, 92, -1, -1 },
+ [ POWER4_PME_PM_FPU_FULL_CYC ] = { -1, -1, -1, -1, 86, -1, -1, -1 },
+ [ POWER4_PME_PM_FPU_FMA ] = { -1, 83, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_MRK_CRU_FIN ] = { -1, -1, -1, 82, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_MRK_LSU1_FLUSH_UST ] = { -1, -1, 66, 66, -1, -1, 66, 66 },
+ [ POWER4_PME_PM_MRK_FXU_FIN ] = { -1, -1, -1, -1, -1, 91, -1, -1 },
+ [ POWER4_PME_PM_BR_ISSUED ] = { -1, -1, 8, 8, -1, -1, 8, 8 },
+ [ POWER4_PME_PM_EE_OFF ] = { -1, -1, 15, 15, -1, -1, 15, 15 },
+ [ POWER4_PME_PM_INST_FROM_L3 ] = { -1, -1, -1, -1, 91, -1, -1, -1 },
+ [ POWER4_PME_PM_ITLB_MISS ] = { 35, 35, -1, -1, 35, 35, -1, -1 },
+ [ POWER4_PME_PM_FXLS_FULL_CYC ] = { -1, -1, -1, -1, -1, -1, -1, 79 },
+ [ POWER4_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { -1, -1, -1, 76, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_GRP_DISP_VALID ] = { 28, 28, -1, -1, 28, 28, -1, -1 },
+ [ POWER4_PME_PM_L2SC_ST_HIT ] = { -1, -1, 41, 41, -1, -1, 41, 41 },
+ [ POWER4_PME_PM_MRK_GRP_DISP ] = { 91, -1, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_L2SB_MOD_TAG ] = { 42, 42, -1, -1, 42, 42, -1, -1 },
+ [ POWER4_PME_PM_INST_FROM_L25_L275 ] = { -1, 86, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_LSU_FLUSH_UST ] = { -1, 87, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_L2SB_ST_HIT ] = { -1, -1, 39, 39, -1, -1, 39, 39 },
+ [ POWER4_PME_PM_FXU1_FIN ] = { -1, -1, 32, 32, -1, -1, 32, 32 },
+ [ POWER4_PME_PM_L3B1_DIR_MIS ] = { 51, 51, -1, -1, 51, 51, -1, -1 },
+ [ POWER4_PME_PM_4INST_CLB_CYC ] = { -1, -1, 3, 3, -1, -1, 3, 3 },
+ [ POWER4_PME_PM_GRP_CMPL ] = { -1, -1, -1, -1, -1, -1, 77, -1 },
+ [ POWER4_PME_PM_DC_PREF_L2_CLONE_L3 ] = { 3, 3, -1, -1, 3, 3, -1, -1 },
+ [ POWER4_PME_PM_FPU_FRSP_FCONV ] = { -1, -1, -1, -1, -1, -1, 75, -1 },
+ [ POWER4_PME_PM_5INST_CLB_CYC ] = { -1, -1, 4, 4, -1, -1, 4, 4 },
+ [ POWER4_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { -1, -1, 59, 59, -1, -1, 59, 59 },
+ [ POWER4_PME_PM_MRK_LSU_FLUSH_ULD ] = { -1, -1, -1, -1, -1, -1, -1, 85 },
+ [ POWER4_PME_PM_8INST_CLB_CYC ] = { -1, -1, 7, 7, -1, -1, 7, 7 },
+ [ POWER4_PME_PM_LSU_LMQ_FULL_CYC ] = { 66, 66, -1, -1, 66, 66, -1, -1 },
+ [ POWER4_PME_PM_ST_REF_L1_LSU0 ] = { -1, -1, 71, 71, -1, -1, 71, 71 },
+ [ POWER4_PME_PM_LSU0_DERAT_MISS ] = { 54, 54, -1, -1, 54, 54, -1, -1 },
+ [ POWER4_PME_PM_LSU_SRQ_SYNC_CYC ] = { -1, -1, 56, 56, -1, -1, 56, 56 },
+ [ POWER4_PME_PM_FPU_STALL3 ] = { -1, 84, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_MRK_DATA_FROM_L2 ] = { -1, -1, -1, 83, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_FPU0_FMOV_FEST ] = { -1, -1, 23, 23, -1, -1, 23, 23 },
+ [ POWER4_PME_PM_LSU0_FLUSH_SRQ ] = { 56, 56, -1, -1, 56, 56, -1, -1 },
+ [ POWER4_PME_PM_LD_REF_L1_LSU0 ] = { -1, -1, 48, 48, -1, -1, 48, 48 },
+ [ POWER4_PME_PM_L2SC_SHR_INV ] = { 47, 47, -1, -1, 47, 47, -1, -1 },
+ [ POWER4_PME_PM_LSU1_FLUSH_SRQ ] = { 62, 62, -1, -1, 62, 62, -1, -1 },
+ [ POWER4_PME_PM_LSU_LMQ_S0_ALLOC ] = { -1, -1, 52, 52, -1, -1, 52, 52 },
+ [ POWER4_PME_PM_ST_REF_L1 ] = { -1, -1, -1, -1, -1, -1, 84, -1 },
+ [ POWER4_PME_PM_LSU_SRQ_EMPTY_CYC ] = { -1, -1, -1, 81, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_FPU1_STF ] = { 25, 25, -1, -1, 25, 25, -1, -1 },
+ [ POWER4_PME_PM_L3B0_DIR_REF ] = { 50, 50, -1, -1, 50, 50, -1, -1 },
+ [ POWER4_PME_PM_RUN_CYC ] = { 94, -1, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_LSU_LMQ_S0_VALID ] = { -1, -1, 53, 53, -1, -1, 53, 53 },
+ [ POWER4_PME_PM_LSU_LRQ_S0_VALID ] = { 69, 69, -1, -1, 69, 69, -1, -1 },
+ [ POWER4_PME_PM_LSU0_LDF ] = { -1, -1, 19, 19, -1, -1, 19, 19 },
+ [ POWER4_PME_PM_MRK_IMR_RELOAD ] = { 72, 72, -1, -1, 72, 72, -1, -1 },
+ [ POWER4_PME_PM_7INST_CLB_CYC ] = { -1, -1, 6, 6, -1, -1, 6, 6 },
+ [ POWER4_PME_PM_MRK_GRP_TIMEO ] = { -1, -1, -1, -1, 94, -1, -1, -1 },
+ [ POWER4_PME_PM_FPU_FMOV_FEST ] = { -1, -1, -1, -1, -1, -1, -1, 77 },
+ [ POWER4_PME_PM_GRP_DISP_BLK_SB_CYC ] = { -1, -1, 34, 34, -1, -1, 34, 34 },
+ [ POWER4_PME_PM_XER_MAP_FULL_CYC ] = { 80, 80, -1, -1, 80, 80, -1, -1 },
+ [ POWER4_PME_PM_ST_MISS_L1 ] = { 79, 79, 70, 70, 79, 79, 70, 70 },
+ [ POWER4_PME_PM_STOP_COMPLETION ] = { -1, -1, 83, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_MRK_GRP_CMPL ] = { -1, -1, -1, 84, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_ISLB_MISS ] = { 34, 34, -1, -1, 34, 34, -1, -1 },
+ [ POWER4_PME_PM_CYC ] = { 81, 81, 73, 73, 82, 81, 73, 74 },
+ [ POWER4_PME_PM_LD_MISS_L1_LSU1 ] = { -1, -1, 47, 47, -1, -1, 47, 47 },
+ [ POWER4_PME_PM_STCX_FAIL ] = { 78, 78, -1, -1, 78, 78, -1, -1 },
+ [ POWER4_PME_PM_LSU1_SRQ_STFWD ] = { 65, 65, -1, -1, 65, 65, -1, -1 },
+ [ POWER4_PME_PM_GRP_DISP ] = { -1, 85, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_DATA_FROM_L2 ] = { -1, -1, -1, 74, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_L2_PREF ] = { -1, -1, 43, 43, -1, -1, 43, 43 },
+ [ POWER4_PME_PM_FPU0_FPSCR ] = { -1, -1, 24, 24, -1, -1, 24, 24 },
+ [ POWER4_PME_PM_FPU1_DENORM ] = { 18, 18, -1, -1, 18, 18, -1, -1 },
+ [ POWER4_PME_PM_MRK_DATA_FROM_L25_MOD ] = { -1, -1, -1, -1, -1, -1, -1, 83 },
+ [ POWER4_PME_PM_L2SB_ST_REQ ] = { -1, -1, 40, 40, -1, -1, 40, 40 },
+ [ POWER4_PME_PM_L2SB_MOD_INV ] = { 41, 41, -1, -1, 41, 41, -1, -1 },
+ [ POWER4_PME_PM_FPU0_FSQRT ] = { 12, 12, -1, -1, 12, 12, -1, -1 },
+ [ POWER4_PME_PM_LD_REF_L1 ] = { -1, -1, -1, -1, -1, -1, -1, 82 },
+ [ POWER4_PME_PM_MRK_L1_RELOAD_VALID ] = { -1, -1, 57, 57, -1, -1, 57, 57 },
+ [ POWER4_PME_PM_L2SB_SHR_MOD ] = { 44, 44, -1, -1, 44, 44, -1, -1 },
+ [ POWER4_PME_PM_INST_FROM_L1 ] = { -1, -1, -1, -1, -1, 87, -1, -1 },
+ [ POWER4_PME_PM_1PLUS_PPC_CMPL ] = { -1, -1, -1, -1, 81, -1, -1, -1 },
+ [ POWER4_PME_PM_EE_OFF_EXT_INT ] = { -1, -1, 16, 16, -1, -1, 16, 16 },
+ [ POWER4_PME_PM_L2SC_SHR_MOD ] = { 48, 48, -1, -1, 48, 48, -1, -1 },
+ [ POWER4_PME_PM_LSU_LRQ_FULL_CYC ] = { -1, -1, 54, 54, -1, -1, 54, 54 },
+ [ POWER4_PME_PM_IC_PREF_INSTALL ] = { 29, 29, -1, -1, 29, 29, -1, -1 },
+ [ POWER4_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { -1, -1, 64, 64, -1, -1, 64, 64 },
+ [ POWER4_PME_PM_GCT_FULL_CYC ] = { 26, 26, -1, -1, 26, 26, -1, -1 },
+ [ POWER4_PME_PM_INST_FROM_MEM ] = { 87, -1, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_FXU_BUSY ] = { -1, -1, -1, -1, -1, 85, -1, -1 },
+ [ POWER4_PME_PM_ST_REF_L1_LSU1 ] = { -1, -1, 72, 72, -1, -1, 72, 72 },
+ [ POWER4_PME_PM_MRK_LD_MISS_L1 ] = { 92, -1, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_MRK_LSU1_INST_FIN ] = { -1, -1, 67, 67, -1, -1, 67, 67 },
+ [ POWER4_PME_PM_L1_WRITE_CYC ] = { -1, -1, 36, 36, -1, -1, 36, 36 },
+ [ POWER4_PME_PM_BIQ_IDU_FULL_CYC ] = { 0, 0, -1, -1, 0, 0, -1, -1 },
+ [ POWER4_PME_PM_MRK_LSU0_INST_FIN ] = { -1, -1, 62, 62, -1, -1, 62, 62 },
+ [ POWER4_PME_PM_L2SC_ST_REQ ] = { -1, -1, 42, 42, -1, -1, 42, 42 },
+ [ POWER4_PME_PM_LSU1_BUSY ] = { -1, -1, 51, 51, -1, -1, 51, 51 },
+ [ POWER4_PME_PM_FPU_ALL ] = { -1, -1, -1, -1, 84, -1, -1, -1 },
+ [ POWER4_PME_PM_LSU_SRQ_S0_ALLOC ] = { 70, 70, -1, -1, 70, 70, -1, -1 },
+ [ POWER4_PME_PM_GRP_MRK ] = { -1, -1, -1, -1, 90, -1, -1, -1 },
+ [ POWER4_PME_PM_FPU1_FIN ] = { -1, -1, 27, 27, -1, -1, 27, 27 },
+ [ POWER4_PME_PM_DC_PREF_STREAM_ALLOC ] = { 4, 4, -1, -1, 4, 4, -1, -1 },
+ [ POWER4_PME_PM_BR_MPRED_CR ] = { -1, -1, 9, 9, -1, -1, 9, 9 },
+ [ POWER4_PME_PM_BR_MPRED_TA ] = { -1, -1, 10, 10, -1, -1, 10, 10 },
+ [ POWER4_PME_PM_CRQ_FULL_CYC ] = { -1, -1, 11, 11, -1, -1, 11, 11 },
+ [ POWER4_PME_PM_INST_FROM_PREF ] = { -1, -1, -1, -1, -1, -1, 79, -1 },
+ [ POWER4_PME_PM_LD_MISS_L1 ] = { -1, -1, 79, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_STCX_PASS ] = { -1, -1, 69, 69, -1, -1, 69, 69 },
+ [ POWER4_PME_PM_DC_INV_L2 ] = { -1, -1, 13, 13, -1, -1, 13, 13 },
+ [ POWER4_PME_PM_LSU_SRQ_FULL_CYC ] = { -1, -1, 55, 55, -1, -1, 55, 55 },
+ [ POWER4_PME_PM_LSU0_FLUSH_LRQ ] = { 55, 55, -1, -1, 55, 55, -1, -1 },
+ [ POWER4_PME_PM_LSU_SRQ_S0_VALID ] = { 71, 71, -1, -1, 71, 71, -1, -1 },
+ [ POWER4_PME_PM_LARX_LSU0 ] = { -1, -1, 44, 44, -1, -1, 44, 44 },
+ [ POWER4_PME_PM_GCT_EMPTY_CYC ] = { 85, -1, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_FPU1_ALL ] = { 17, 17, -1, -1, 17, 17, -1, -1 },
+ [ POWER4_PME_PM_FPU1_FSQRT ] = { 21, 21, -1, -1, 21, 21, -1, -1 },
+ [ POWER4_PME_PM_FPU_FIN ] = { -1, -1, -1, 75, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_L2SA_SHR_MOD ] = { 40, 40, -1, -1, 40, 40, -1, -1 },
+ [ POWER4_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { 74, 74, -1, -1, 74, 74, -1, -1 },
+ [ POWER4_PME_PM_LSU_SRQ_STFWD ] = { 89, -1, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_FXU0_FIN ] = { -1, -1, 31, 31, -1, -1, 31, 31 },
+ [ POWER4_PME_PM_MRK_FPU_FIN ] = { -1, -1, -1, -1, -1, -1, 81, -1 },
+ [ POWER4_PME_PM_LSU_BUSY ] = { -1, -1, -1, 80, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_INST_FROM_L35 ] = { -1, -1, -1, 78, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_FPU1_FRSP_FCONV ] = { -1, -1, 29, 29, -1, -1, 29, 29 },
+ [ POWER4_PME_PM_SNOOP_TLBIE ] = { 77, 77, -1, -1, 77, 77, -1, -1 },
+ [ POWER4_PME_PM_FPU0_FDIV ] = { 10, 10, -1, -1, 10, 10, -1, -1 },
+ [ POWER4_PME_PM_LD_REF_L1_LSU1 ] = { -1, -1, 49, 49, -1, -1, 49, 49 },
+ [ POWER4_PME_PM_MRK_DATA_FROM_L275_MOD ] = { -1, -1, -1, -1, -1, -1, 80, -1 },
+ [ POWER4_PME_PM_HV_CYC ] = { -1, -1, 84, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_6INST_CLB_CYC ] = { -1, -1, 5, 5, -1, -1, 5, 5 },
+ [ POWER4_PME_PM_LR_CTR_MAP_FULL_CYC ] = { 53, 53, -1, -1, 53, 53, -1, -1 },
+ [ POWER4_PME_PM_L2SC_MOD_INV ] = { 45, 45, -1, -1, 45, 45, -1, -1 },
+ [ POWER4_PME_PM_FPU_DENORM ] = { 83, -1, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_DATA_FROM_L275_MOD ] = { -1, -1, -1, -1, -1, -1, 74, -1 },
+ [ POWER4_PME_PM_LSU1_DERAT_MISS ] = { 60, 60, -1, -1, 60, 60, -1, -1 },
+ [ POWER4_PME_PM_IC_PREF_REQ ] = { 30, 30, -1, -1, 30, 30, -1, -1 },
+ [ POWER4_PME_PM_MRK_LSU_FIN ] = { -1, -1, -1, -1, -1, -1, -1, 84 },
+ [ POWER4_PME_PM_MRK_DATA_FROM_L3 ] = { 90, -1, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_MRK_DATA_FROM_MEM ] = { -1, 90, -1, -1, -1, -1, -1, -1 },
+ [ POWER4_PME_PM_LSU0_FLUSH_UST ] = { 58, 58, -1, -1, 58, 58, -1, -1 },
+ [ POWER4_PME_PM_LSU_FLUSH_LRQ ] = { -1, -1, -1, -1, -1, 89, -1, -1 },
+ [ POWER4_PME_PM_LSU_FLUSH_SRQ ] = { -1, -1, -1, -1, 92, -1, -1, -1 },
+ [ POWER4_PME_PM_L2SC_MOD_TAG ] = { 46, 46, -1, -1, 46, 46, -1, -1 }
+};
+
+static const unsigned long long power4_group_vecs[][POWER4_NUM_GROUP_VEC] = {
+ [ POWER4_PME_PM_MRK_LSU_SRQ_INST_VALID ] = {
+ 0x0000100000000000ULL
+ },
+ [ POWER4_PME_PM_FPU1_SINGLE ] = {
+ 0x0000000080000000ULL
+ },
+ [ POWER4_PME_PM_DC_PREF_OUT_STREAMS ] = {
+ 0x0000010000000000ULL
+ },
+ [ POWER4_PME_PM_FPU0_STALL3 ] = {
+ 0x0000000100000000ULL
+ },
+ [ POWER4_PME_PM_TB_BIT_TRANS ] = {
+ 0x0000020000000000ULL
+ },
+ [ POWER4_PME_PM_GPR_MAP_FULL_CYC ] = {
+ 0x0000000000000010ULL
+ },
+ [ POWER4_PME_PM_MRK_ST_CMPL ] = {
+ 0x0000100000000000ULL
+ },
+ [ POWER4_PME_PM_MRK_LSU_FLUSH_LRQ ] = {
+ 0x0000200000000000ULL
+ },
+ [ POWER4_PME_PM_FPU0_STF ] = {
+ 0x0000000080000000ULL
+ },
+ [ POWER4_PME_PM_FPU1_FMA ] = {
+ 0x0000000010000000ULL
+ },
+ [ POWER4_PME_PM_L2SA_MOD_TAG ] = {
+ 0x0000000000000800ULL
+ },
+ [ POWER4_PME_PM_MRK_DATA_FROM_L275_SHR ] = {
+ 0x0000c00000000000ULL
+ },
+ [ POWER4_PME_PM_1INST_CLB_CYC ] = {
+ 0x0000000000010000ULL
+ },
+ [ POWER4_PME_PM_LSU1_FLUSH_ULD ] = {
+ 0x0000001000000000ULL
+ },
+ [ POWER4_PME_PM_MRK_INST_FIN ] = {
+ 0x0008040000000000ULL
+ },
+ [ POWER4_PME_PM_MRK_LSU0_FLUSH_UST ] = {
+ 0x0002000000000000ULL
+ },
+ [ POWER4_PME_PM_FPU_FDIV ] = {
+ 0x1020000000004000ULL
+ },
+ [ POWER4_PME_PM_LSU_LRQ_S0_ALLOC ] = {
+ 0x0000000000800000ULL
+ },
+ [ POWER4_PME_PM_FPU0_FULL_CYC ] = {
+ 0x0000000000080000ULL
+ },
+ [ POWER4_PME_PM_FPU_SINGLE ] = {
+ 0x0000000000000000ULL
+ },
+ [ POWER4_PME_PM_FPU0_FMA ] = {
+ 0x0000000010000000ULL
+ },
+ [ POWER4_PME_PM_MRK_LSU1_FLUSH_ULD ] = {
+ 0x0002000000000000ULL
+ },
+ [ POWER4_PME_PM_LSU1_FLUSH_LRQ ] = {
+ 0x0000000800000000ULL
+ },
+ [ POWER4_PME_PM_L2SA_ST_HIT ] = {
+ 0x0000000000000800ULL
+ },
+ [ POWER4_PME_PM_L2SB_SHR_INV ] = {
+ 0x0000000000001000ULL
+ },
+ [ POWER4_PME_PM_DTLB_MISS ] = {
+ 0x0900000000000100ULL
+ },
+ [ POWER4_PME_PM_MRK_ST_MISS_L1 ] = {
+ 0x0002000000000000ULL
+ },
+ [ POWER4_PME_PM_EXT_INT ] = {
+ 0x0000000000200000ULL
+ },
+ [ POWER4_PME_PM_MRK_LSU1_FLUSH_LRQ ] = {
+ 0x0004000000000000ULL
+ },
+ [ POWER4_PME_PM_MRK_ST_GPS ] = {
+ 0x0000100000000000ULL
+ },
+ [ POWER4_PME_PM_GRP_DISP_SUCCESS ] = {
+ 0x0000000000020000ULL
+ },
+ [ POWER4_PME_PM_LSU1_LDF ] = {
+ 0x0000000080000000ULL
+ },
+ [ POWER4_PME_PM_FAB_CMD_ISSUED ] = {
+ 0x0000000000000400ULL
+ },
+ [ POWER4_PME_PM_LSU0_SRQ_STFWD ] = {
+ 0x0000004000000000ULL
+ },
+ [ POWER4_PME_PM_CR_MAP_FULL_CYC ] = {
+ 0x0000000000040000ULL
+ },
+ [ POWER4_PME_PM_MRK_LSU0_FLUSH_ULD ] = {
+ 0x0002000000000000ULL
+ },
+ [ POWER4_PME_PM_LSU_DERAT_MISS ] = {
+ 0x0000000000000300ULL
+ },
+ [ POWER4_PME_PM_FPU0_SINGLE ] = {
+ 0x0000000080000000ULL
+ },
+ [ POWER4_PME_PM_FPU1_FDIV ] = {
+ 0x0000000010000000ULL
+ },
+ [ POWER4_PME_PM_FPU1_FEST ] = {
+ 0x0000000040000000ULL
+ },
+ [ POWER4_PME_PM_FPU0_FRSP_FCONV ] = {
+ 0x0000000010000000ULL
+ },
+ [ POWER4_PME_PM_MRK_ST_CMPL_INT ] = {
+ 0x0000100000000000ULL
+ },
+ [ POWER4_PME_PM_FXU_FIN ] = {
+ 0x0020000000000000ULL
+ },
+ [ POWER4_PME_PM_FPU_STF ] = {
+ 0x1040000000008000ULL
+ },
+ [ POWER4_PME_PM_DSLB_MISS ] = {
+ 0x0000000000000200ULL
+ },
+ [ POWER4_PME_PM_DATA_FROM_L275_SHR ] = {
+ 0x0200000001000020ULL
+ },
+ [ POWER4_PME_PM_FXLS1_FULL_CYC ] = {
+ 0x0000000000000000ULL
+ },
+ [ POWER4_PME_PM_L3B0_DIR_MIS ] = {
+ 0x0000000000000400ULL
+ },
+ [ POWER4_PME_PM_2INST_CLB_CYC ] = {
+ 0x0000000000010000ULL
+ },
+ [ POWER4_PME_PM_MRK_STCX_FAIL ] = {
+ 0x0008000000000000ULL
+ },
+ [ POWER4_PME_PM_LSU_LMQ_LHR_MERGE ] = {
+ 0x0010000400000000ULL
+ },
+ [ POWER4_PME_PM_FXU0_BUSY_FXU1_IDLE ] = {
+ 0x0000000200000000ULL
+ },
+ [ POWER4_PME_PM_L3B1_DIR_REF ] = {
+ 0x0000000000000400ULL
+ },
+ [ POWER4_PME_PM_MRK_LSU_FLUSH_UST ] = {
+ 0x0000000000000000ULL
+ },
+ [ POWER4_PME_PM_MRK_DATA_FROM_L25_SHR ] = {
+ 0x0000c00000000000ULL
+ },
+ [ POWER4_PME_PM_LSU_FLUSH_ULD ] = {
+ 0x0000000000000080ULL
+ },
+ [ POWER4_PME_PM_MRK_BRU_FIN ] = {
+ 0x0000080000000000ULL
+ },
+ [ POWER4_PME_PM_IERAT_XLATE_WR ] = {
+ 0x0000000000000300ULL
+ },
+ [ POWER4_PME_PM_LSU0_BUSY ] = {
+ 0x0000000000800000ULL
+ },
+ [ POWER4_PME_PM_L2SA_ST_REQ ] = {
+ 0x0000000000000800ULL
+ },
+ [ POWER4_PME_PM_DATA_FROM_MEM ] = {
+ 0x0400000002000020ULL
+ },
+ [ POWER4_PME_PM_FPR_MAP_FULL_CYC ] = {
+ 0x0000000000000010ULL
+ },
+ [ POWER4_PME_PM_FPU1_FULL_CYC ] = {
+ 0x0000000000080000ULL
+ },
+ [ POWER4_PME_PM_FPU0_FIN ] = {
+ 0x1040000120000000ULL
+ },
+ [ POWER4_PME_PM_3INST_CLB_CYC ] = {
+ 0x0000000000010000ULL
+ },
+ [ POWER4_PME_PM_DATA_FROM_L35 ] = {
+ 0x0600000002000020ULL
+ },
+ [ POWER4_PME_PM_L2SA_SHR_INV ] = {
+ 0x0000000000000800ULL
+ },
+ [ POWER4_PME_PM_MRK_LSU_FLUSH_SRQ ] = {
+ 0x0000200000000000ULL
+ },
+ [ POWER4_PME_PM_THRESH_TIMEO ] = {
+ 0x0010040000000000ULL
+ },
+ [ POWER4_PME_PM_FPU_FSQRT ] = {
+ 0x0020000000004000ULL
+ },
+ [ POWER4_PME_PM_MRK_LSU0_FLUSH_LRQ ] = {
+ 0x0004000000000000ULL
+ },
+ [ POWER4_PME_PM_FXLS0_FULL_CYC ] = {
+ 0x0000000000080000ULL
+ },
+ [ POWER4_PME_PM_DATA_TABLEWALK_CYC ] = {
+ 0x0000000400000100ULL
+ },
+ [ POWER4_PME_PM_FPU0_ALL ] = {
+ 0x0000000020000000ULL
+ },
+ [ POWER4_PME_PM_FPU0_FEST ] = {
+ 0x0000000040000000ULL
+ },
+ [ POWER4_PME_PM_DATA_FROM_L25_MOD ] = {
+ 0x0600000001000020ULL
+ },
+ [ POWER4_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = {
+ 0x0800020000000000ULL
+ },
+ [ POWER4_PME_PM_FPU_FEST ] = {
+ 0x0000000000004000ULL
+ },
+ [ POWER4_PME_PM_0INST_FETCH ] = {
+ 0x0000000004000040ULL
+ },
+ [ POWER4_PME_PM_LARX_LSU1 ] = {
+ 0x0000000000400000ULL
+ },
+ [ POWER4_PME_PM_LD_MISS_L1_LSU0 ] = {
+ 0x0000001000000000ULL
+ },
+ [ POWER4_PME_PM_L1_PREF ] = {
+ 0x0000010000000000ULL
+ },
+ [ POWER4_PME_PM_FPU1_STALL3 ] = {
+ 0x0000000100000000ULL
+ },
+ [ POWER4_PME_PM_BRQ_FULL_CYC ] = {
+ 0x0080000000000010ULL
+ },
+ [ POWER4_PME_PM_LARX ] = {
+ 0x0000000000000000ULL
+ },
+ [ POWER4_PME_PM_MRK_DATA_FROM_L35 ] = {
+ 0x0001400000000000ULL
+ },
+ [ POWER4_PME_PM_WORK_HELD ] = {
+ 0x0000000000200000ULL
+ },
+ [ POWER4_PME_PM_MRK_LD_MISS_L1_LSU0 ] = {
+ 0x0004000000000000ULL
+ },
+ [ POWER4_PME_PM_FXU_IDLE ] = {
+ 0x0000000200000000ULL
+ },
+ [ POWER4_PME_PM_INST_CMPL ] = {
+ 0x7fffb7ffffffff9fULL
+ },
+ [ POWER4_PME_PM_LSU1_FLUSH_UST ] = {
+ 0x0000002000000000ULL
+ },
+ [ POWER4_PME_PM_LSU0_FLUSH_ULD ] = {
+ 0x0000001000000000ULL
+ },
+ [ POWER4_PME_PM_INST_FROM_L2 ] = {
+ 0x000000000c000040ULL
+ },
+ [ POWER4_PME_PM_DATA_FROM_L3 ] = {
+ 0x0400000002000020ULL
+ },
+ [ POWER4_PME_PM_FPU0_DENORM ] = {
+ 0x0000000040000000ULL
+ },
+ [ POWER4_PME_PM_FPU1_FMOV_FEST ] = {
+ 0x0000000040000000ULL
+ },
+ [ POWER4_PME_PM_GRP_DISP_REJECT ] = {
+ 0x0000000000100001ULL
+ },
+ [ POWER4_PME_PM_INST_FETCH_CYC ] = {
+ 0x0000000000000008ULL
+ },
+ [ POWER4_PME_PM_LSU_LDF ] = {
+ 0x1040000000008000ULL
+ },
+ [ POWER4_PME_PM_INST_DISP ] = {
+ 0x0000000000140006ULL
+ },
+ [ POWER4_PME_PM_L2SA_MOD_INV ] = {
+ 0x0000000000000800ULL
+ },
+ [ POWER4_PME_PM_DATA_FROM_L25_SHR ] = {
+ 0x0600000001000020ULL
+ },
+ [ POWER4_PME_PM_FAB_CMD_RETRIED ] = {
+ 0x0000000000000400ULL
+ },
+ [ POWER4_PME_PM_L1_DCACHE_RELOAD_VALID ] = {
+ 0x0000008003000000ULL
+ },
+ [ POWER4_PME_PM_MRK_GRP_ISSUED ] = {
+ 0x0018240000000000ULL
+ },
+ [ POWER4_PME_PM_FPU_FULL_CYC ] = {
+ 0x0040000000000010ULL
+ },
+ [ POWER4_PME_PM_FPU_FMA ] = {
+ 0x1020000000004000ULL
+ },
+ [ POWER4_PME_PM_MRK_CRU_FIN ] = {
+ 0x0000080000000000ULL
+ },
+ [ POWER4_PME_PM_MRK_LSU1_FLUSH_UST ] = {
+ 0x0002000000000000ULL
+ },
+ [ POWER4_PME_PM_MRK_FXU_FIN ] = {
+ 0x0000080000000000ULL
+ },
+ [ POWER4_PME_PM_BR_ISSUED ] = {
+ 0x6080000000000008ULL
+ },
+ [ POWER4_PME_PM_EE_OFF ] = {
+ 0x0000000000200000ULL
+ },
+ [ POWER4_PME_PM_INST_FROM_L3 ] = {
+ 0x000000000c000040ULL
+ },
+ [ POWER4_PME_PM_ITLB_MISS ] = {
+ 0x0100000000000100ULL
+ },
+ [ POWER4_PME_PM_FXLS_FULL_CYC ] = {
+ 0x0000000200000010ULL
+ },
+ [ POWER4_PME_PM_FXU1_BUSY_FXU0_IDLE ] = {
+ 0x0000000200000000ULL
+ },
+ [ POWER4_PME_PM_GRP_DISP_VALID ] = {
+ 0x0000000000100000ULL
+ },
+ [ POWER4_PME_PM_L2SC_ST_HIT ] = {
+ 0x0000000000002000ULL
+ },
+ [ POWER4_PME_PM_MRK_GRP_DISP ] = {
+ 0x0000080000000000ULL
+ },
+ [ POWER4_PME_PM_L2SB_MOD_TAG ] = {
+ 0x0000000000001000ULL
+ },
+ [ POWER4_PME_PM_INST_FROM_L25_L275 ] = {
+ 0x0000000008000040ULL
+ },
+ [ POWER4_PME_PM_LSU_FLUSH_UST ] = {
+ 0x0000000000000080ULL
+ },
+ [ POWER4_PME_PM_L2SB_ST_HIT ] = {
+ 0x0000000000001000ULL
+ },
+ [ POWER4_PME_PM_FXU1_FIN ] = {
+ 0x0000000000100000ULL
+ },
+ [ POWER4_PME_PM_L3B1_DIR_MIS ] = {
+ 0x0000000000000400ULL
+ },
+ [ POWER4_PME_PM_4INST_CLB_CYC ] = {
+ 0x0000000000010000ULL
+ },
+ [ POWER4_PME_PM_GRP_CMPL ] = {
+ 0x0010020000000001ULL
+ },
+ [ POWER4_PME_PM_DC_PREF_L2_CLONE_L3 ] = {
+ 0x0000010000000000ULL
+ },
+ [ POWER4_PME_PM_FPU_FRSP_FCONV ] = {
+ 0x0000000000008000ULL
+ },
+ [ POWER4_PME_PM_5INST_CLB_CYC ] = {
+ 0x0000000000020000ULL
+ },
+ [ POWER4_PME_PM_MRK_LSU0_FLUSH_SRQ ] = {
+ 0x0004000000000000ULL
+ },
+ [ POWER4_PME_PM_MRK_LSU_FLUSH_ULD ] = {
+ 0x0000200000000000ULL
+ },
+ [ POWER4_PME_PM_8INST_CLB_CYC ] = {
+ 0x0000000000020000ULL
+ },
+ [ POWER4_PME_PM_LSU_LMQ_FULL_CYC ] = {
+ 0x0000000400000000ULL
+ },
+ [ POWER4_PME_PM_ST_REF_L1_LSU0 ] = {
+ 0x0000006000000000ULL
+ },
+ [ POWER4_PME_PM_LSU0_DERAT_MISS ] = {
+ 0x0000008000000000ULL
+ },
+ [ POWER4_PME_PM_LSU_SRQ_SYNC_CYC ] = {
+ 0x0000000400000200ULL
+ },
+ [ POWER4_PME_PM_FPU_STALL3 ] = {
+ 0x0040000000008000ULL
+ },
+ [ POWER4_PME_PM_MRK_DATA_FROM_L2 ] = {
+ 0x0001c00000000000ULL
+ },
+ [ POWER4_PME_PM_FPU0_FMOV_FEST ] = {
+ 0x0000000040000000ULL
+ },
+ [ POWER4_PME_PM_LSU0_FLUSH_SRQ ] = {
+ 0x0000000800000000ULL
+ },
+ [ POWER4_PME_PM_LD_REF_L1_LSU0 ] = {
+ 0x0000001000000000ULL
+ },
+ [ POWER4_PME_PM_L2SC_SHR_INV ] = {
+ 0x0000000000002000ULL
+ },
+ [ POWER4_PME_PM_LSU1_FLUSH_SRQ ] = {
+ 0x0000000800000000ULL
+ },
+ [ POWER4_PME_PM_LSU_LMQ_S0_ALLOC ] = {
+ 0x0010000400000200ULL
+ },
+ [ POWER4_PME_PM_ST_REF_L1 ] = {
+ 0x4900000000000086ULL
+ },
+ [ POWER4_PME_PM_LSU_SRQ_EMPTY_CYC ] = {
+ 0x0000000000000000ULL
+ },
+ [ POWER4_PME_PM_FPU1_STF ] = {
+ 0x0000000080000000ULL
+ },
+ [ POWER4_PME_PM_L3B0_DIR_REF ] = {
+ 0x0000000000000400ULL
+ },
+ [ POWER4_PME_PM_RUN_CYC ] = {
+ 0x0000000000000001ULL
+ },
+ [ POWER4_PME_PM_LSU_LMQ_S0_VALID ] = {
+ 0x0010000400000100ULL
+ },
+ [ POWER4_PME_PM_LSU_LRQ_S0_VALID ] = {
+ 0x0000000000800000ULL
+ },
+ [ POWER4_PME_PM_LSU0_LDF ] = {
+ 0x0000000080000000ULL
+ },
+ [ POWER4_PME_PM_MRK_IMR_RELOAD ] = {
+ 0x0002000000000000ULL
+ },
+ [ POWER4_PME_PM_7INST_CLB_CYC ] = {
+ 0x0000000000020000ULL
+ },
+ [ POWER4_PME_PM_MRK_GRP_TIMEO ] = {
+ 0x0000300000000000ULL
+ },
+ [ POWER4_PME_PM_FPU_FMOV_FEST ] = {
+ 0x0020000000004000ULL
+ },
+ [ POWER4_PME_PM_GRP_DISP_BLK_SB_CYC ] = {
+ 0x0000000000040000ULL
+ },
+ [ POWER4_PME_PM_XER_MAP_FULL_CYC ] = {
+ 0x0000000000040000ULL
+ },
+ [ POWER4_PME_PM_ST_MISS_L1 ] = {
+ 0x6900006000000000ULL
+ },
+ [ POWER4_PME_PM_STOP_COMPLETION ] = {
+ 0x0000000000200001ULL
+ },
+ [ POWER4_PME_PM_MRK_GRP_CMPL ] = {
+ 0x0000140000000000ULL
+ },
+ [ POWER4_PME_PM_ISLB_MISS ] = {
+ 0x0000000000000200ULL
+ },
+ [ POWER4_PME_PM_CYC ] = {
+ 0x7fffbfffffffff9fULL
+ },
+ [ POWER4_PME_PM_LD_MISS_L1_LSU1 ] = {
+ 0x0000001000000000ULL
+ },
+ [ POWER4_PME_PM_STCX_FAIL ] = {
+ 0x0000000000400000ULL
+ },
+ [ POWER4_PME_PM_LSU1_SRQ_STFWD ] = {
+ 0x0000004000000000ULL
+ },
+ [ POWER4_PME_PM_GRP_DISP ] = {
+ 0x0000000000000000ULL
+ },
+ [ POWER4_PME_PM_DATA_FROM_L2 ] = {
+ 0x0600000003000020ULL
+ },
+ [ POWER4_PME_PM_L2_PREF ] = {
+ 0x0000010000000000ULL
+ },
+ [ POWER4_PME_PM_FPU0_FPSCR ] = {
+ 0x0000000100000000ULL
+ },
+ [ POWER4_PME_PM_FPU1_DENORM ] = {
+ 0x0000000040000000ULL
+ },
+ [ POWER4_PME_PM_MRK_DATA_FROM_L25_MOD ] = {
+ 0x0000c00000000000ULL
+ },
+ [ POWER4_PME_PM_L2SB_ST_REQ ] = {
+ 0x0000000000001000ULL
+ },
+ [ POWER4_PME_PM_L2SB_MOD_INV ] = {
+ 0x0000000000001000ULL
+ },
+ [ POWER4_PME_PM_FPU0_FSQRT ] = {
+ 0x0000000020000000ULL
+ },
+ [ POWER4_PME_PM_LD_REF_L1 ] = {
+ 0x4900000000000086ULL
+ },
+ [ POWER4_PME_PM_MRK_L1_RELOAD_VALID ] = {
+ 0x0001800000000000ULL
+ },
+ [ POWER4_PME_PM_L2SB_SHR_MOD ] = {
+ 0x0000000000001000ULL
+ },
+ [ POWER4_PME_PM_INST_FROM_L1 ] = {
+ 0x000000000c000040ULL
+ },
+ [ POWER4_PME_PM_1PLUS_PPC_CMPL ] = {
+ 0x0000020000410001ULL
+ },
+ [ POWER4_PME_PM_EE_OFF_EXT_INT ] = {
+ 0x0000000000200000ULL
+ },
+ [ POWER4_PME_PM_L2SC_SHR_MOD ] = {
+ 0x0000000000002000ULL
+ },
+ [ POWER4_PME_PM_LSU_LRQ_FULL_CYC ] = {
+ 0x0000000000080000ULL
+ },
+ [ POWER4_PME_PM_IC_PREF_INSTALL ] = {
+ 0x0000000000000000ULL
+ },
+ [ POWER4_PME_PM_MRK_LSU1_FLUSH_SRQ ] = {
+ 0x0004000000000000ULL
+ },
+ [ POWER4_PME_PM_GCT_FULL_CYC ] = {
+ 0x0000000000000010ULL
+ },
+ [ POWER4_PME_PM_INST_FROM_MEM ] = {
+ 0x0000000008000040ULL
+ },
+ [ POWER4_PME_PM_FXU_BUSY ] = {
+ 0x0000000200000000ULL
+ },
+ [ POWER4_PME_PM_ST_REF_L1_LSU1 ] = {
+ 0x0000006000000000ULL
+ },
+ [ POWER4_PME_PM_MRK_LD_MISS_L1 ] = {
+ 0x0000240000000000ULL
+ },
+ [ POWER4_PME_PM_MRK_LSU1_INST_FIN ] = {
+ 0x0008000000000000ULL
+ },
+ [ POWER4_PME_PM_L1_WRITE_CYC ] = {
+ 0x0080000000000008ULL
+ },
+ [ POWER4_PME_PM_BIQ_IDU_FULL_CYC ] = {
+ 0x0080000000000008ULL
+ },
+ [ POWER4_PME_PM_MRK_LSU0_INST_FIN ] = {
+ 0x0008000000000000ULL
+ },
+ [ POWER4_PME_PM_L2SC_ST_REQ ] = {
+ 0x0000000000002000ULL
+ },
+ [ POWER4_PME_PM_LSU1_BUSY ] = {
+ 0x0000000000800000ULL
+ },
+ [ POWER4_PME_PM_FPU_ALL ] = {
+ 0x0000000000008000ULL
+ },
+ [ POWER4_PME_PM_LSU_SRQ_S0_ALLOC ] = {
+ 0x0000000000800000ULL
+ },
+ [ POWER4_PME_PM_GRP_MRK ] = {
+ 0x00000c0000000000ULL
+ },
+ [ POWER4_PME_PM_FPU1_FIN ] = {
+ 0x1040000120000000ULL
+ },
+ [ POWER4_PME_PM_DC_PREF_STREAM_ALLOC ] = {
+ 0x0000010000000000ULL
+ },
+ [ POWER4_PME_PM_BR_MPRED_CR ] = {
+ 0x2080000000000008ULL
+ },
+ [ POWER4_PME_PM_BR_MPRED_TA ] = {
+ 0x2080000000000008ULL
+ },
+ [ POWER4_PME_PM_CRQ_FULL_CYC ] = {
+ 0x0000000000040000ULL
+ },
+ [ POWER4_PME_PM_INST_FROM_PREF ] = {
+ 0x0000000004000040ULL
+ },
+ [ POWER4_PME_PM_LD_MISS_L1 ] = {
+ 0x6900000000000006ULL
+ },
+ [ POWER4_PME_PM_STCX_PASS ] = {
+ 0x0000000000400000ULL
+ },
+ [ POWER4_PME_PM_DC_INV_L2 ] = {
+ 0x0000002000000006ULL
+ },
+ [ POWER4_PME_PM_LSU_SRQ_FULL_CYC ] = {
+ 0x0000000000080000ULL
+ },
+ [ POWER4_PME_PM_LSU0_FLUSH_LRQ ] = {
+ 0x0000000800000000ULL
+ },
+ [ POWER4_PME_PM_LSU_SRQ_S0_VALID ] = {
+ 0x0000000000800000ULL
+ },
+ [ POWER4_PME_PM_LARX_LSU0 ] = {
+ 0x0000000000400000ULL
+ },
+ [ POWER4_PME_PM_GCT_EMPTY_CYC ] = {
+ 0x0000020000200000ULL
+ },
+ [ POWER4_PME_PM_FPU1_ALL ] = {
+ 0x0000000020000000ULL
+ },
+ [ POWER4_PME_PM_FPU1_FSQRT ] = {
+ 0x0000000020000000ULL
+ },
+ [ POWER4_PME_PM_FPU_FIN ] = {
+ 0x0020000000004000ULL
+ },
+ [ POWER4_PME_PM_L2SA_SHR_MOD ] = {
+ 0x0000000000000800ULL
+ },
+ [ POWER4_PME_PM_MRK_LD_MISS_L1_LSU1 ] = {
+ 0x0004000000000000ULL
+ },
+ [ POWER4_PME_PM_LSU_SRQ_STFWD ] = {
+ 0x0000000000000000ULL
+ },
+ [ POWER4_PME_PM_FXU0_FIN ] = {
+ 0x0000000000100000ULL
+ },
+ [ POWER4_PME_PM_MRK_FPU_FIN ] = {
+ 0x0000080000000000ULL
+ },
+ [ POWER4_PME_PM_LSU_BUSY ] = {
+ 0x0000000000000000ULL
+ },
+ [ POWER4_PME_PM_INST_FROM_L35 ] = {
+ 0x000000000c000040ULL
+ },
+ [ POWER4_PME_PM_FPU1_FRSP_FCONV ] = {
+ 0x0000000010000000ULL
+ },
+ [ POWER4_PME_PM_SNOOP_TLBIE ] = {
+ 0x0000000000400000ULL
+ },
+ [ POWER4_PME_PM_FPU0_FDIV ] = {
+ 0x0000000010000000ULL
+ },
+ [ POWER4_PME_PM_LD_REF_L1_LSU1 ] = {
+ 0x0000001000000000ULL
+ },
+ [ POWER4_PME_PM_MRK_DATA_FROM_L275_MOD ] = {
+ 0x0001c00000000000ULL
+ },
+ [ POWER4_PME_PM_HV_CYC ] = {
+ 0x0000020000000000ULL
+ },
+ [ POWER4_PME_PM_6INST_CLB_CYC ] = {
+ 0x0000000000020000ULL
+ },
+ [ POWER4_PME_PM_LR_CTR_MAP_FULL_CYC ] = {
+ 0x0000000000040000ULL
+ },
+ [ POWER4_PME_PM_L2SC_MOD_INV ] = {
+ 0x0000000000002000ULL
+ },
+ [ POWER4_PME_PM_FPU_DENORM ] = {
+ 0x0000000000008000ULL
+ },
+ [ POWER4_PME_PM_DATA_FROM_L275_MOD ] = {
+ 0x0200000003000020ULL
+ },
+ [ POWER4_PME_PM_LSU1_DERAT_MISS ] = {
+ 0x0000008000000000ULL
+ },
+ [ POWER4_PME_PM_IC_PREF_REQ ] = {
+ 0x0000000000000000ULL
+ },
+ [ POWER4_PME_PM_MRK_LSU_FIN ] = {
+ 0x0000080000000000ULL
+ },
+ [ POWER4_PME_PM_MRK_DATA_FROM_L3 ] = {
+ 0x0001400000000000ULL
+ },
+ [ POWER4_PME_PM_MRK_DATA_FROM_MEM ] = {
+ 0x0001400000000000ULL
+ },
+ [ POWER4_PME_PM_LSU0_FLUSH_UST ] = {
+ 0x0000002000000000ULL
+ },
+ [ POWER4_PME_PM_LSU_FLUSH_LRQ ] = {
+ 0x0000000000000080ULL
+ },
+ [ POWER4_PME_PM_LSU_FLUSH_SRQ ] = {
+ 0x0000000000000080ULL
+ },
+ [ POWER4_PME_PM_L2SC_MOD_TAG ] = {
+ 0x0000000000002000ULL
+ }
+};
+
+static const pme_power_entry_t power4_pe[] = {
[ POWER4_PME_PM_MRK_LSU_SRQ_INST_VALID ] = {
.pme_name = "PM_MRK_LSU_SRQ_INST_VALID",
+ .pme_code = 0x933,
.pme_short_desc = "Marked instruction valid in SRQ",
.pme_long_desc = "This signal is asserted every cycle when a marked request is resident in the Store Request Queue",
- .pme_event_ids = { -1, -1, 68, 68, -1, -1, 68, 68 },
- .pme_group_vector = {
- 0x0000100000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU_SRQ_INST_VALID],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU_SRQ_INST_VALID]
},
-#define POWER4_PME_PM_FPU1_SINGLE 1
[ POWER4_PME_PM_FPU1_SINGLE ] = {
.pme_name = "PM_FPU1_SINGLE",
+ .pme_code = 0x127,
.pme_short_desc = "FPU1 executed single precision instruction",
.pme_long_desc = "This signal is active for one cycle when fp1 is executing single precision instruction.",
- .pme_event_ids = { 23, 23, -1, -1, 23, 23, -1, -1 },
- .pme_group_vector = {
- 0x0000000080000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_SINGLE],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_SINGLE]
},
-#define POWER4_PME_PM_DC_PREF_OUT_STREAMS 2
[ POWER4_PME_PM_DC_PREF_OUT_STREAMS ] = {
.pme_name = "PM_DC_PREF_OUT_STREAMS",
+ .pme_code = 0xc36,
.pme_short_desc = "Out of prefetch streams",
.pme_long_desc = "A new prefetch stream was detected, but no more stream entries were available",
- .pme_event_ids = { -1, -1, 14, 14, -1, -1, 14, 14 },
- .pme_group_vector = {
- 0x0000010000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_DC_PREF_OUT_STREAMS],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DC_PREF_OUT_STREAMS]
},
-#define POWER4_PME_PM_FPU0_STALL3 3
[ POWER4_PME_PM_FPU0_STALL3 ] = {
.pme_name = "PM_FPU0_STALL3",
+ .pme_code = 0x121,
.pme_short_desc = "FPU0 stalled in pipe3",
.pme_long_desc = "This signal indicates that fp0 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. ",
- .pme_event_ids = { 15, 15, -1, -1, 15, 15, -1, -1 },
- .pme_group_vector = {
- 0x0000000100000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_STALL3],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_STALL3]
},
-#define POWER4_PME_PM_TB_BIT_TRANS 4
[ POWER4_PME_PM_TB_BIT_TRANS ] = {
.pme_name = "PM_TB_BIT_TRANS",
+ .pme_code = 0x8005,
.pme_short_desc = "Time Base bit transition",
.pme_long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 ",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 86 },
- .pme_group_vector = {
- 0x0000020000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_TB_BIT_TRANS],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_TB_BIT_TRANS]
},
-#define POWER4_PME_PM_GPR_MAP_FULL_CYC 5
[ POWER4_PME_PM_GPR_MAP_FULL_CYC ] = {
.pme_name = "PM_GPR_MAP_FULL_CYC",
+ .pme_code = 0x235,
.pme_short_desc = "Cycles GPR mapper full",
.pme_long_desc = "The ISU sends a signal indicating that the gpr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.",
- .pme_event_ids = { -1, -1, 33, 33, -1, -1, 33, 33 },
- .pme_group_vector = {
- 0x0000000000000010ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_GPR_MAP_FULL_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_GPR_MAP_FULL_CYC]
},
-#define POWER4_PME_PM_MRK_ST_CMPL 6
[ POWER4_PME_PM_MRK_ST_CMPL ] = {
.pme_name = "PM_MRK_ST_CMPL",
+ .pme_code = 0x1003,
.pme_short_desc = "Marked store instruction completed",
.pme_long_desc = "A sampled store has completed (data home)",
- .pme_event_ids = { 93, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000100000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_ST_CMPL],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_ST_CMPL]
},
-#define POWER4_PME_PM_MRK_LSU_FLUSH_LRQ 7
[ POWER4_PME_PM_MRK_LSU_FLUSH_LRQ ] = {
.pme_name = "PM_MRK_LSU_FLUSH_LRQ",
+ .pme_code = 0x3910,
.pme_short_desc = "Marked LRQ flushes",
.pme_long_desc = "A marked load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { -1, -1, 81, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000200000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU_FLUSH_LRQ],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU_FLUSH_LRQ]
},
-#define POWER4_PME_PM_FPU0_STF 8
[ POWER4_PME_PM_FPU0_STF ] = {
.pme_name = "PM_FPU0_STF",
+ .pme_code = 0x122,
.pme_short_desc = "FPU0 executed store instruction",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing a store instruction.",
- .pme_event_ids = { 16, 16, -1, -1, 16, 16, -1, -1 },
- .pme_group_vector = {
- 0x0000000080000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_STF],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_STF]
},
-#define POWER4_PME_PM_FPU1_FMA 9
[ POWER4_PME_PM_FPU1_FMA ] = {
.pme_name = "PM_FPU1_FMA",
+ .pme_code = 0x105,
.pme_short_desc = "FPU1 executed multiply-add instruction",
.pme_long_desc = "This signal is active for one cycle when fp1 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 20, 20, -1, -1, 20, 20, -1, -1 },
- .pme_group_vector = {
- 0x0000000010000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_FMA],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_FMA]
},
-#define POWER4_PME_PM_L2SA_MOD_TAG 10
[ POWER4_PME_PM_L2SA_MOD_TAG ] = {
.pme_name = "PM_L2SA_MOD_TAG",
+ .pme_code = 0xf06,
.pme_short_desc = "L2 slice A transition from modified to tagged",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.",
- .pme_event_ids = { 38, 38, -1, -1, 38, 38, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000800ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SA_MOD_TAG],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SA_MOD_TAG]
},
-#define POWER4_PME_PM_MRK_DATA_FROM_L275_SHR 11
[ POWER4_PME_PM_MRK_DATA_FROM_L275_SHR ] = {
.pme_name = "PM_MRK_DATA_FROM_L275_SHR",
+ .pme_code = 0x6c76,
.pme_short_desc = "Marked data loaded from L2.75 shared",
.pme_long_desc = "DL1 was reloaded with shared (T) data from the L2 of another MCM due to a marked demand load",
- .pme_event_ids = { -1, -1, -1, -1, -1, 90, -1, -1 },
- .pme_group_vector = {
- 0x0000c00000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_DATA_FROM_L275_SHR],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_DATA_FROM_L275_SHR]
},
-#define POWER4_PME_PM_1INST_CLB_CYC 12
[ POWER4_PME_PM_1INST_CLB_CYC ] = {
.pme_name = "PM_1INST_CLB_CYC",
+ .pme_code = 0x450,
.pme_short_desc = "Cycles 1 instruction in CLB",
.pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.",
- .pme_event_ids = { -1, -1, 0, 0, -1, -1, 0, 0 },
- .pme_group_vector = {
- 0x0000000000010000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_1INST_CLB_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_1INST_CLB_CYC]
},
-#define POWER4_PME_PM_LSU1_FLUSH_ULD 13
[ POWER4_PME_PM_LSU1_FLUSH_ULD ] = {
.pme_name = "PM_LSU1_FLUSH_ULD",
+ .pme_code = 0xc04,
.pme_short_desc = "LSU1 unaligned load flushes",
.pme_long_desc = "A load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { 63, 63, -1, -1, 63, 63, -1, -1 },
- .pme_group_vector = {
- 0x0000001000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU1_FLUSH_ULD],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU1_FLUSH_ULD]
},
-#define POWER4_PME_PM_MRK_INST_FIN 14
[ POWER4_PME_PM_MRK_INST_FIN ] = {
.pme_name = "PM_MRK_INST_FIN",
+ .pme_code = 0x7005,
.pme_short_desc = "Marked instruction finished",
.pme_long_desc = "One of the execution units finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 82, -1 },
- .pme_group_vector = {
- 0x0008040000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_INST_FIN],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_INST_FIN]
},
-#define POWER4_PME_PM_MRK_LSU0_FLUSH_UST 15
[ POWER4_PME_PM_MRK_LSU0_FLUSH_UST ] = {
.pme_name = "PM_MRK_LSU0_FLUSH_UST",
+ .pme_code = 0x911,
.pme_short_desc = "LSU0 marked unaligned store flushes",
.pme_long_desc = "A marked store was flushed from unit 0 because it was unaligned",
- .pme_event_ids = { -1, -1, 61, 61, -1, -1, 61, 61 },
- .pme_group_vector = {
- 0x0002000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU0_FLUSH_UST],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU0_FLUSH_UST]
},
-#define POWER4_PME_PM_FPU_FDIV 16
[ POWER4_PME_PM_FPU_FDIV ] = {
.pme_name = "PM_FPU_FDIV",
+ .pme_code = 0x1100,
.pme_short_desc = "FPU executed FDIV instruction",
.pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when FPU is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs. Combined Unit 0 + Unit 1",
- .pme_event_ids = { 84, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x1020000000004000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_FDIV],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_FDIV]
},
-#define POWER4_PME_PM_LSU_LRQ_S0_ALLOC 17
[ POWER4_PME_PM_LSU_LRQ_S0_ALLOC ] = {
.pme_name = "PM_LSU_LRQ_S0_ALLOC",
+ .pme_code = 0xc26,
.pme_short_desc = "LRQ slot 0 allocated",
.pme_long_desc = "LRQ slot zero was allocated",
- .pme_event_ids = { 68, 68, -1, -1, 68, 68, -1, -1 },
- .pme_group_vector = {
- 0x0000000000800000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_LRQ_S0_ALLOC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_LRQ_S0_ALLOC]
},
-#define POWER4_PME_PM_FPU0_FULL_CYC 18
[ POWER4_PME_PM_FPU0_FULL_CYC ] = {
.pme_name = "PM_FPU0_FULL_CYC",
+ .pme_code = 0x203,
.pme_short_desc = "Cycles FPU0 issue queue full",
.pme_long_desc = "The issue queue for FPU unit 0 cannot accept any more instructions. Issue is stopped",
- .pme_event_ids = { 13, 13, -1, -1, 13, 13, -1, -1 },
- .pme_group_vector = {
- 0x0000000000080000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_FULL_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_FULL_CYC]
},
-#define POWER4_PME_PM_FPU_SINGLE 19
[ POWER4_PME_PM_FPU_SINGLE ] = {
.pme_name = "PM_FPU_SINGLE",
+ .pme_code = 0x5120,
.pme_short_desc = "FPU executed single precision instruction",
.pme_long_desc = "FPU is executing single precision instruction. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, -1, -1, 87, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_SINGLE],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_SINGLE]
},
-#define POWER4_PME_PM_FPU0_FMA 20
[ POWER4_PME_PM_FPU0_FMA ] = {
.pme_name = "PM_FPU0_FMA",
+ .pme_code = 0x101,
.pme_short_desc = "FPU0 executed multiply-add instruction",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 11, 11, -1, -1, 11, 11, -1, -1 },
- .pme_group_vector = {
- 0x0000000010000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_FMA],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_FMA]
},
-#define POWER4_PME_PM_MRK_LSU1_FLUSH_ULD 21
[ POWER4_PME_PM_MRK_LSU1_FLUSH_ULD ] = {
.pme_name = "PM_MRK_LSU1_FLUSH_ULD",
+ .pme_code = 0x914,
.pme_short_desc = "LSU1 marked unaligned load flushes",
.pme_long_desc = "A marked load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { -1, -1, 65, 65, -1, -1, 65, 65 },
- .pme_group_vector = {
- 0x0002000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU1_FLUSH_ULD],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU1_FLUSH_ULD]
},
-#define POWER4_PME_PM_LSU1_FLUSH_LRQ 22
[ POWER4_PME_PM_LSU1_FLUSH_LRQ ] = {
.pme_name = "PM_LSU1_FLUSH_LRQ",
+ .pme_code = 0xc06,
.pme_short_desc = "LSU1 LRQ flushes",
.pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { 61, 61, -1, -1, 61, 61, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU1_FLUSH_LRQ],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU1_FLUSH_LRQ]
},
-#define POWER4_PME_PM_L2SA_ST_HIT 23
[ POWER4_PME_PM_L2SA_ST_HIT ] = {
.pme_name = "PM_L2SA_ST_HIT",
+ .pme_code = 0xf11,
.pme_short_desc = "L2 slice A store hits",
.pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A,B, and C.",
- .pme_event_ids = { -1, -1, 37, 37, -1, -1, 37, 37 },
- .pme_group_vector = {
- 0x0000000000000800ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SA_ST_HIT],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SA_ST_HIT]
},
-#define POWER4_PME_PM_L2SB_SHR_INV 24
[ POWER4_PME_PM_L2SB_SHR_INV ] = {
.pme_name = "PM_L2SB_SHR_INV",
+ .pme_code = 0xf21,
.pme_short_desc = "L2 slice B transition from shared to invalid",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.",
- .pme_event_ids = { 43, 43, -1, -1, 43, 43, -1, -1 },
- .pme_group_vector = {
- 0x0000000000001000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SB_SHR_INV],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SB_SHR_INV]
},
-#define POWER4_PME_PM_DTLB_MISS 25
[ POWER4_PME_PM_DTLB_MISS ] = {
.pme_name = "PM_DTLB_MISS",
+ .pme_code = 0x904,
.pme_short_desc = "Data TLB misses",
.pme_long_desc = "A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.",
- .pme_event_ids = { 6, 6, -1, -1, 6, 6, -1, -1 },
- .pme_group_vector = {
- 0x0900000000000100ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_DTLB_MISS],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DTLB_MISS]
},
-#define POWER4_PME_PM_MRK_ST_MISS_L1 26
[ POWER4_PME_PM_MRK_ST_MISS_L1 ] = {
.pme_name = "PM_MRK_ST_MISS_L1",
+ .pme_code = 0x923,
.pme_short_desc = "Marked L1 D cache store misses",
.pme_long_desc = "A marked store missed the dcache",
- .pme_event_ids = { 76, 76, -1, -1, 76, 76, -1, -1 },
- .pme_group_vector = {
- 0x0002000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_ST_MISS_L1],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_ST_MISS_L1]
},
-#define POWER4_PME_PM_EXT_INT 27
[ POWER4_PME_PM_EXT_INT ] = {
.pme_name = "PM_EXT_INT",
+ .pme_code = 0x8002,
.pme_short_desc = "External interrupts",
.pme_long_desc = "An external interrupt occurred",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 76 },
- .pme_group_vector = {
- 0x0000000000200000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_EXT_INT],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_EXT_INT]
},
-#define POWER4_PME_PM_MRK_LSU1_FLUSH_LRQ 28
[ POWER4_PME_PM_MRK_LSU1_FLUSH_LRQ ] = {
.pme_name = "PM_MRK_LSU1_FLUSH_LRQ",
+ .pme_code = 0x916,
.pme_short_desc = "LSU1 marked LRQ flushes",
.pme_long_desc = "A marked load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { -1, -1, 63, 63, -1, -1, 63, 63 },
- .pme_group_vector = {
- 0x0004000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU1_FLUSH_LRQ],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU1_FLUSH_LRQ]
},
-#define POWER4_PME_PM_MRK_ST_GPS 29
[ POWER4_PME_PM_MRK_ST_GPS ] = {
.pme_name = "PM_MRK_ST_GPS",
+ .pme_code = 0x6003,
.pme_short_desc = "Marked store sent to GPS",
.pme_long_desc = "A sampled store has been sent to the memory subsystem",
- .pme_event_ids = { -1, -1, -1, -1, -1, 93, -1, -1 },
- .pme_group_vector = {
- 0x0000100000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_ST_GPS],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_ST_GPS]
},
-#define POWER4_PME_PM_GRP_DISP_SUCCESS 30
[ POWER4_PME_PM_GRP_DISP_SUCCESS ] = {
.pme_name = "PM_GRP_DISP_SUCCESS",
+ .pme_code = 0x5001,
.pme_short_desc = "Group dispatch success",
.pme_long_desc = "Number of groups sucessfully dispatched (not rejected)",
- .pme_event_ids = { -1, -1, -1, -1, 89, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000020000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_GRP_DISP_SUCCESS],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_GRP_DISP_SUCCESS]
},
-#define POWER4_PME_PM_LSU1_LDF 31
[ POWER4_PME_PM_LSU1_LDF ] = {
.pme_name = "PM_LSU1_LDF",
+ .pme_code = 0x934,
.pme_short_desc = "LSU1 executed Floating Point load instruction",
.pme_long_desc = "A floating point load was executed from LSU unit 1",
- .pme_event_ids = { -1, -1, 20, 20, -1, -1, 20, 20 },
- .pme_group_vector = {
- 0x0000000080000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU1_LDF],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU1_LDF]
},
-#define POWER4_PME_PM_FAB_CMD_ISSUED 32
[ POWER4_PME_PM_FAB_CMD_ISSUED ] = {
.pme_name = "PM_FAB_CMD_ISSUED",
+ .pme_code = 0xf16,
.pme_short_desc = "Fabric command issued",
.pme_long_desc = "A bus command was issued on the MCM to MCM fabric from the local (this chip's) Fabric Bus Controller. This event is scaled to the fabric frequency and must be adjusted for a true count. i.e. if the fabric is running 2:1, divide the count by 2.",
- .pme_event_ids = { -1, -1, 17, 17, -1, -1, 17, 17 },
- .pme_group_vector = {
- 0x0000000000000400ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FAB_CMD_ISSUED],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FAB_CMD_ISSUED]
},
-#define POWER4_PME_PM_LSU0_SRQ_STFWD 33
[ POWER4_PME_PM_LSU0_SRQ_STFWD ] = {
.pme_name = "PM_LSU0_SRQ_STFWD",
+ .pme_code = 0xc20,
.pme_short_desc = "LSU0 SRQ store forwarded",
.pme_long_desc = "Data from a store instruction was forwarded to a load on unit 0",
- .pme_event_ids = { 59, 59, -1, -1, 59, 59, -1, -1 },
- .pme_group_vector = {
- 0x0000004000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU0_SRQ_STFWD],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU0_SRQ_STFWD]
},
-#define POWER4_PME_PM_CR_MAP_FULL_CYC 34
[ POWER4_PME_PM_CR_MAP_FULL_CYC ] = {
.pme_name = "PM_CR_MAP_FULL_CYC",
+ .pme_code = 0x204,
.pme_short_desc = "Cycles CR logical operation mapper full",
.pme_long_desc = "The ISU sends a signal indicating that the cr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.",
- .pme_event_ids = { 2, 2, -1, -1, 2, 2, -1, -1 },
- .pme_group_vector = {
- 0x0000000000040000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_CR_MAP_FULL_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_CR_MAP_FULL_CYC]
},
-#define POWER4_PME_PM_MRK_LSU0_FLUSH_ULD 35
[ POWER4_PME_PM_MRK_LSU0_FLUSH_ULD ] = {
.pme_name = "PM_MRK_LSU0_FLUSH_ULD",
+ .pme_code = 0x910,
.pme_short_desc = "LSU0 marked unaligned load flushes",
.pme_long_desc = "A marked load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { -1, -1, 60, 60, -1, -1, 60, 60 },
- .pme_group_vector = {
- 0x0002000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU0_FLUSH_ULD],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU0_FLUSH_ULD]
},
-#define POWER4_PME_PM_LSU_DERAT_MISS 36
[ POWER4_PME_PM_LSU_DERAT_MISS ] = {
.pme_name = "PM_LSU_DERAT_MISS",
+ .pme_code = 0x6900,
.pme_short_desc = "DERAT misses",
.pme_long_desc = "Total D-ERAT Misses (Unit 0 + Unit 1). Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.",
- .pme_event_ids = { -1, -1, -1, -1, -1, 88, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000300ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_DERAT_MISS],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_DERAT_MISS]
},
-#define POWER4_PME_PM_FPU0_SINGLE 37
[ POWER4_PME_PM_FPU0_SINGLE ] = {
.pme_name = "PM_FPU0_SINGLE",
+ .pme_code = 0x123,
.pme_short_desc = "FPU0 executed single precision instruction",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing single precision instruction.",
- .pme_event_ids = { 14, 14, -1, -1, 14, 14, -1, -1 },
- .pme_group_vector = {
- 0x0000000080000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_SINGLE],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_SINGLE]
},
-#define POWER4_PME_PM_FPU1_FDIV 38
[ POWER4_PME_PM_FPU1_FDIV ] = {
.pme_name = "PM_FPU1_FDIV",
+ .pme_code = 0x104,
.pme_short_desc = "FPU1 executed FDIV instruction",
.pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp1 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.",
- .pme_event_ids = { 19, 19, -1, -1, 19, 19, -1, -1 },
- .pme_group_vector = {
- 0x0000000010000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_FDIV],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_FDIV]
},
-#define POWER4_PME_PM_FPU1_FEST 39
[ POWER4_PME_PM_FPU1_FEST ] = {
.pme_name = "PM_FPU1_FEST",
+ .pme_code = 0x116,
.pme_short_desc = "FPU1 executed FEST instruction",
.pme_long_desc = "This signal is active for one cycle when fp1 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ",
- .pme_event_ids = { -1, -1, 26, 26, -1, -1, 26, 26 },
- .pme_group_vector = {
- 0x0000000040000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_FEST],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_FEST]
},
-#define POWER4_PME_PM_FPU0_FRSP_FCONV 40
[ POWER4_PME_PM_FPU0_FRSP_FCONV ] = {
.pme_name = "PM_FPU0_FRSP_FCONV",
+ .pme_code = 0x111,
.pme_short_desc = "FPU0 executed FRSP or FCONV instructions",
.pme_long_desc = "fThis signal is active for one cycle when fp0 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { -1, -1, 25, 25, -1, -1, 25, 25 },
- .pme_group_vector = {
- 0x0000000010000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_FRSP_FCONV],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_FRSP_FCONV]
},
-#define POWER4_PME_PM_MRK_ST_CMPL_INT 41
[ POWER4_PME_PM_MRK_ST_CMPL_INT ] = {
.pme_name = "PM_MRK_ST_CMPL_INT",
+ .pme_code = 0x3003,
.pme_short_desc = "Marked store completed with intervention",
.pme_long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention",
- .pme_event_ids = { -1, -1, 82, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000100000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_ST_CMPL_INT],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_ST_CMPL_INT]
},
-#define POWER4_PME_PM_FXU_FIN 42
[ POWER4_PME_PM_FXU_FIN ] = {
.pme_name = "PM_FXU_FIN",
+ .pme_code = 0x3230,
.pme_short_desc = "FXU produced a result",
.pme_long_desc = "The fixed point unit (Unit 0 + Unit 1) finished a marked instruction. Instructions that finish may not necessary complete.",
- .pme_event_ids = { -1, -1, 77, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0020000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FXU_FIN],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FXU_FIN]
},
-#define POWER4_PME_PM_FPU_STF 43
[ POWER4_PME_PM_FPU_STF ] = {
.pme_name = "PM_FPU_STF",
+ .pme_code = 0x6120,
.pme_short_desc = "FPU executed store instruction",
.pme_long_desc = "FPU is executing a store instruction. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, -1, -1, -1, 84, -1, -1 },
- .pme_group_vector = {
- 0x1040000000008000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_STF],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_STF]
},
-#define POWER4_PME_PM_DSLB_MISS 44
[ POWER4_PME_PM_DSLB_MISS ] = {
.pme_name = "PM_DSLB_MISS",
+ .pme_code = 0x905,
.pme_short_desc = "Data SLB misses",
.pme_long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve",
- .pme_event_ids = { 5, 5, -1, -1, 5, 5, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000200ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_DSLB_MISS],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DSLB_MISS]
},
-#define POWER4_PME_PM_DATA_FROM_L275_SHR 45
[ POWER4_PME_PM_DATA_FROM_L275_SHR ] = {
.pme_name = "PM_DATA_FROM_L275_SHR",
+ .pme_code = 0x6c66,
.pme_short_desc = "Data loaded from L2.75 shared",
.pme_long_desc = "DL1 was reloaded with shared (T) data from the L2 of another MCM due to a demand load",
- .pme_event_ids = { -1, -1, -1, -1, -1, 82, -1, -1 },
- .pme_group_vector = {
- 0x0200000001000020ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_DATA_FROM_L275_SHR],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DATA_FROM_L275_SHR]
},
-#define POWER4_PME_PM_FXLS1_FULL_CYC 46
[ POWER4_PME_PM_FXLS1_FULL_CYC ] = {
.pme_name = "PM_FXLS1_FULL_CYC",
+ .pme_code = 0x214,
.pme_short_desc = "Cycles FXU1/LS1 queue full",
.pme_long_desc = "The issue queue for FXU/LSU unit 1 cannot accept any more instructions. Issue is stopped",
- .pme_event_ids = { -1, -1, 85, 86, -1, -1, 85, 87 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FXLS1_FULL_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FXLS1_FULL_CYC]
},
-#define POWER4_PME_PM_L3B0_DIR_MIS 47
[ POWER4_PME_PM_L3B0_DIR_MIS ] = {
.pme_name = "PM_L3B0_DIR_MIS",
+ .pme_code = 0xf01,
.pme_short_desc = "L3 bank 0 directory misses",
.pme_long_desc = "A reference was made to the local L3 directory by a local CPU and it missed in the L3. Only requests from on-MCM CPUs are counted. This event is scaled to the L3 speed and the count must be scaled. i.e. if the L3 is running 3:1, divide the count by 3",
- .pme_event_ids = { 49, 49, -1, -1, 49, 49, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000400ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L3B0_DIR_MIS],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L3B0_DIR_MIS]
},
-#define POWER4_PME_PM_2INST_CLB_CYC 48
[ POWER4_PME_PM_2INST_CLB_CYC ] = {
.pme_name = "PM_2INST_CLB_CYC",
+ .pme_code = 0x451,
.pme_short_desc = "Cycles 2 instructions in CLB",
.pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.",
- .pme_event_ids = { -1, -1, 1, 1, -1, -1, 1, 1 },
- .pme_group_vector = {
- 0x0000000000010000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_2INST_CLB_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_2INST_CLB_CYC]
},
-#define POWER4_PME_PM_MRK_STCX_FAIL 49
[ POWER4_PME_PM_MRK_STCX_FAIL ] = {
.pme_name = "PM_MRK_STCX_FAIL",
+ .pme_code = 0x925,
.pme_short_desc = "Marked STCX failed",
.pme_long_desc = "A marked stcx (stwcx or stdcx) failed",
- .pme_event_ids = { 75, 75, -1, -1, 75, 75, -1, -1 },
- .pme_group_vector = {
- 0x0008000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_STCX_FAIL],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_STCX_FAIL]
},
-#define POWER4_PME_PM_LSU_LMQ_LHR_MERGE 50
[ POWER4_PME_PM_LSU_LMQ_LHR_MERGE ] = {
.pme_name = "PM_LSU_LMQ_LHR_MERGE",
+ .pme_code = 0x926,
.pme_short_desc = "LMQ LHR merges",
.pme_long_desc = "A dcache miss occured for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.",
- .pme_event_ids = { 67, 67, -1, -1, 67, 67, -1, -1 },
- .pme_group_vector = {
- 0x0010000400000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_LMQ_LHR_MERGE],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_LMQ_LHR_MERGE]
},
-#define POWER4_PME_PM_FXU0_BUSY_FXU1_IDLE 51
[ POWER4_PME_PM_FXU0_BUSY_FXU1_IDLE ] = {
.pme_name = "PM_FXU0_BUSY_FXU1_IDLE",
+ .pme_code = 0x7002,
.pme_short_desc = "FXU0 busy FXU1 idle",
.pme_long_desc = "FXU0 is busy while FXU1 was idle",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 76, -1 },
- .pme_group_vector = {
- 0x0000000200000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FXU0_BUSY_FXU1_IDLE],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FXU0_BUSY_FXU1_IDLE]
},
-#define POWER4_PME_PM_L3B1_DIR_REF 52
[ POWER4_PME_PM_L3B1_DIR_REF ] = {
.pme_name = "PM_L3B1_DIR_REF",
+ .pme_code = 0xf02,
.pme_short_desc = "L3 bank 1 directory references",
.pme_long_desc = "A reference was made to the local L3 directory by a local CPU. Only requests from on-MCM CPUs are counted. This event is scaled to the L3 speed and the count must be scaled. i.e. if the L3 is running 3:1, divide the count by 3",
- .pme_event_ids = { 52, 52, -1, -1, 52, 52, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000400ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L3B1_DIR_REF],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L3B1_DIR_REF]
},
-#define POWER4_PME_PM_MRK_LSU_FLUSH_UST 53
[ POWER4_PME_PM_MRK_LSU_FLUSH_UST ] = {
.pme_name = "PM_MRK_LSU_FLUSH_UST",
+ .pme_code = 0x7910,
.pme_short_desc = "Marked unaligned store flushes",
.pme_long_desc = "A marked store was flushed because it was unaligned",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 83, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU_FLUSH_UST],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU_FLUSH_UST]
},
-#define POWER4_PME_PM_MRK_DATA_FROM_L25_SHR 54
[ POWER4_PME_PM_MRK_DATA_FROM_L25_SHR ] = {
.pme_name = "PM_MRK_DATA_FROM_L25_SHR",
+ .pme_code = 0x5c76,
.pme_short_desc = "Marked data loaded from L2.5 shared",
.pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a marked demand load",
- .pme_event_ids = { -1, -1, -1, -1, 93, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000c00000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_DATA_FROM_L25_SHR],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_DATA_FROM_L25_SHR]
},
-#define POWER4_PME_PM_LSU_FLUSH_ULD 55
[ POWER4_PME_PM_LSU_FLUSH_ULD ] = {
.pme_name = "PM_LSU_FLUSH_ULD",
+ .pme_code = 0x1c00,
.pme_short_desc = "LRQ unaligned load flushes",
.pme_long_desc = "A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { 88, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000080ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_FLUSH_ULD],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_FLUSH_ULD]
},
-#define POWER4_PME_PM_MRK_BRU_FIN 56
[ POWER4_PME_PM_MRK_BRU_FIN ] = {
.pme_name = "PM_MRK_BRU_FIN",
+ .pme_code = 0x2005,
.pme_short_desc = "Marked instruction BRU processing finished",
.pme_long_desc = "The branch unit finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, 89, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000080000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_BRU_FIN],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_BRU_FIN]
},
-#define POWER4_PME_PM_IERAT_XLATE_WR 57
[ POWER4_PME_PM_IERAT_XLATE_WR ] = {
.pme_name = "PM_IERAT_XLATE_WR",
+ .pme_code = 0x327,
.pme_short_desc = "Translation written to ierat",
.pme_long_desc = "This signal will be asserted each time the I-ERAT is written. This indicates that an ERAT miss has been serviced. ERAT misses will initiate a sequence resulting in the ERAT being written. ERAT misses that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed, This should be a fairly accurate count of ERAT missed (best available).",
- .pme_event_ids = { 31, 31, -1, -1, 31, 31, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000300ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_IERAT_XLATE_WR],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_IERAT_XLATE_WR]
},
-#define POWER4_PME_PM_LSU0_BUSY 58
[ POWER4_PME_PM_LSU0_BUSY ] = {
.pme_name = "PM_LSU0_BUSY",
+ .pme_code = 0xc33,
.pme_short_desc = "LSU0 busy",
.pme_long_desc = "LSU unit 0 is busy rejecting instructions",
- .pme_event_ids = { -1, -1, 50, 50, -1, -1, 50, 50 },
- .pme_group_vector = {
- 0x0000000000800000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU0_BUSY],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU0_BUSY]
},
-#define POWER4_PME_PM_L2SA_ST_REQ 59
[ POWER4_PME_PM_L2SA_ST_REQ ] = {
.pme_name = "PM_L2SA_ST_REQ",
+ .pme_code = 0xf10,
.pme_short_desc = "L2 slice A store requests",
.pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C.",
- .pme_event_ids = { -1, -1, 38, 38, -1, -1, 38, 38 },
- .pme_group_vector = {
- 0x0000000000000800ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SA_ST_REQ],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SA_ST_REQ]
},
-#define POWER4_PME_PM_DATA_FROM_MEM 60
[ POWER4_PME_PM_DATA_FROM_MEM ] = {
.pme_name = "PM_DATA_FROM_MEM",
+ .pme_code = 0x2c66,
.pme_short_desc = "Data loaded from memory",
.pme_long_desc = "DL1 was reloaded from memory due to a demand load",
- .pme_event_ids = { -1, 82, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0400000002000020ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_DATA_FROM_MEM],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DATA_FROM_MEM]
},
-#define POWER4_PME_PM_FPR_MAP_FULL_CYC 61
[ POWER4_PME_PM_FPR_MAP_FULL_CYC ] = {
.pme_name = "PM_FPR_MAP_FULL_CYC",
+ .pme_code = 0x201,
.pme_short_desc = "Cycles FPR mapper full",
.pme_long_desc = "The ISU sends a signal indicating that the FPR mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.",
- .pme_event_ids = { 7, 7, -1, -1, 7, 7, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000010ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPR_MAP_FULL_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPR_MAP_FULL_CYC]
},
-#define POWER4_PME_PM_FPU1_FULL_CYC 62
[ POWER4_PME_PM_FPU1_FULL_CYC ] = {
.pme_name = "PM_FPU1_FULL_CYC",
+ .pme_code = 0x207,
.pme_short_desc = "Cycles FPU1 issue queue full",
.pme_long_desc = "The issue queue for FPU unit 1 cannot accept any more instructions. Issue is stopped",
- .pme_event_ids = { 22, 22, -1, -1, 22, 22, -1, -1 },
- .pme_group_vector = {
- 0x0000000000080000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_FULL_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_FULL_CYC]
},
-#define POWER4_PME_PM_FPU0_FIN 63
[ POWER4_PME_PM_FPU0_FIN ] = {
.pme_name = "PM_FPU0_FIN",
+ .pme_code = 0x113,
.pme_short_desc = "FPU0 produced a result",
.pme_long_desc = "fp0 finished, produced a result This only indicates finish, not completion. ",
- .pme_event_ids = { -1, -1, 22, 22, -1, -1, 22, 22 },
- .pme_group_vector = {
- 0x1040000120000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_FIN],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_FIN]
},
-#define POWER4_PME_PM_3INST_CLB_CYC 64
[ POWER4_PME_PM_3INST_CLB_CYC ] = {
.pme_name = "PM_3INST_CLB_CYC",
+ .pme_code = 0x452,
.pme_short_desc = "Cycles 3 instructions in CLB",
.pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.",
- .pme_event_ids = { -1, -1, 2, 2, -1, -1, 2, 2 },
- .pme_group_vector = {
- 0x0000000000010000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_3INST_CLB_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_3INST_CLB_CYC]
},
-#define POWER4_PME_PM_DATA_FROM_L35 65
[ POWER4_PME_PM_DATA_FROM_L35 ] = {
.pme_name = "PM_DATA_FROM_L35",
+ .pme_code = 0x3c66,
.pme_short_desc = "Data loaded from L3.5",
.pme_long_desc = "DL1 was reloaded from the L3 of another MCM due to a demand load",
- .pme_event_ids = { -1, -1, 74, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0600000002000020ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_DATA_FROM_L35],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DATA_FROM_L35]
},
-#define POWER4_PME_PM_L2SA_SHR_INV 66
[ POWER4_PME_PM_L2SA_SHR_INV ] = {
.pme_name = "PM_L2SA_SHR_INV",
+ .pme_code = 0xf05,
.pme_short_desc = "L2 slice A transition from shared to invalid",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.",
- .pme_event_ids = { 39, 39, -1, -1, 39, 39, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000800ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SA_SHR_INV],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SA_SHR_INV]
},
-#define POWER4_PME_PM_MRK_LSU_FLUSH_SRQ 67
[ POWER4_PME_PM_MRK_LSU_FLUSH_SRQ ] = {
.pme_name = "PM_MRK_LSU_FLUSH_SRQ",
+ .pme_code = 0x4910,
.pme_short_desc = "Marked SRQ flushes",
.pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { -1, -1, -1, 85, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000200000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU_FLUSH_SRQ],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU_FLUSH_SRQ]
},
-#define POWER4_PME_PM_THRESH_TIMEO 68
[ POWER4_PME_PM_THRESH_TIMEO ] = {
.pme_name = "PM_THRESH_TIMEO",
+ .pme_code = 0x2003,
.pme_short_desc = "Threshold timeout",
.pme_long_desc = "The threshold timer expired",
- .pme_event_ids = { -1, 91, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0010040000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_THRESH_TIMEO],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_THRESH_TIMEO]
},
-#define POWER4_PME_PM_FPU_FSQRT 69
[ POWER4_PME_PM_FPU_FSQRT ] = {
.pme_name = "PM_FPU_FSQRT",
+ .pme_code = 0x6100,
.pme_short_desc = "FPU executed FSQRT instruction",
.pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when FPU is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, -1, -1, -1, 83, -1, -1 },
- .pme_group_vector = {
- 0x0020000000004000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_FSQRT],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_FSQRT]
},
-#define POWER4_PME_PM_MRK_LSU0_FLUSH_LRQ 70
[ POWER4_PME_PM_MRK_LSU0_FLUSH_LRQ ] = {
.pme_name = "PM_MRK_LSU0_FLUSH_LRQ",
+ .pme_code = 0x912,
.pme_short_desc = "LSU0 marked LRQ flushes",
.pme_long_desc = "A marked load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { -1, -1, 58, 58, -1, -1, 58, 58 },
- .pme_group_vector = {
- 0x0004000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU0_FLUSH_LRQ],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU0_FLUSH_LRQ]
},
-#define POWER4_PME_PM_FXLS0_FULL_CYC 71
[ POWER4_PME_PM_FXLS0_FULL_CYC ] = {
.pme_name = "PM_FXLS0_FULL_CYC",
+ .pme_code = 0x210,
.pme_short_desc = "Cycles FXU0/LS0 queue full",
.pme_long_desc = "The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped",
- .pme_event_ids = { -1, -1, 30, 30, -1, -1, 30, 30 },
- .pme_group_vector = {
- 0x0000000000080000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FXLS0_FULL_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FXLS0_FULL_CYC]
},
-#define POWER4_PME_PM_DATA_TABLEWALK_CYC 72
[ POWER4_PME_PM_DATA_TABLEWALK_CYC ] = {
.pme_name = "PM_DATA_TABLEWALK_CYC",
+ .pme_code = 0x936,
.pme_short_desc = "Cycles doing data tablewalks",
.pme_long_desc = "This signal is asserted every cycle when a tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.",
- .pme_event_ids = { -1, -1, 12, 12, -1, -1, 12, 12 },
- .pme_group_vector = {
- 0x0000000400000100ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_DATA_TABLEWALK_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DATA_TABLEWALK_CYC]
},
-#define POWER4_PME_PM_FPU0_ALL 73
[ POWER4_PME_PM_FPU0_ALL ] = {
.pme_name = "PM_FPU0_ALL",
+ .pme_code = 0x103,
.pme_short_desc = "FPU0 executed add",
.pme_long_desc = " mult",
- .pme_event_ids = { 8, 8, -1, -1, 8, 8, -1, -1 },
- .pme_group_vector = {
- 0x0000000020000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_ALL],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_ALL]
},
-#define POWER4_PME_PM_FPU0_FEST 74
[ POWER4_PME_PM_FPU0_FEST ] = {
.pme_name = "PM_FPU0_FEST",
+ .pme_code = 0x112,
.pme_short_desc = "FPU0 executed FEST instruction",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ",
- .pme_event_ids = { -1, -1, 21, 21, -1, -1, 21, 21 },
- .pme_group_vector = {
- 0x0000000040000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_FEST],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_FEST]
},
-#define POWER4_PME_PM_DATA_FROM_L25_MOD 75
[ POWER4_PME_PM_DATA_FROM_L25_MOD ] = {
.pme_name = "PM_DATA_FROM_L25_MOD",
+ .pme_code = 0x8c66,
.pme_short_desc = "Data loaded from L2.5 modified",
.pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a demand load",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 75 },
- .pme_group_vector = {
- 0x0600000001000020ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_DATA_FROM_L25_MOD],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DATA_FROM_L25_MOD]
},
-#define POWER4_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 76
[ POWER4_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = {
.pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC",
+ .pme_code = 0x2002,
.pme_short_desc = "Cycles LMQ and SRQ empty",
.pme_long_desc = "Cycles when both the LMQ and SRQ are empty (LSU is idle)",
- .pme_event_ids = { -1, 88, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0800020000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC]
},
-#define POWER4_PME_PM_FPU_FEST 77
[ POWER4_PME_PM_FPU_FEST ] = {
.pme_name = "PM_FPU_FEST",
+ .pme_code = 0x3110,
.pme_short_desc = "FPU executed FEST instruction",
.pme_long_desc = "This signal is active for one cycle when executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. Combined Unit 0 + Unit 1.",
- .pme_event_ids = { -1, -1, 75, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000004000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_FEST],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_FEST]
},
-#define POWER4_PME_PM_0INST_FETCH 78
[ POWER4_PME_PM_0INST_FETCH ] = {
.pme_name = "PM_0INST_FETCH",
+ .pme_code = 0x8327,
.pme_short_desc = "No instructions fetched",
.pme_long_desc = "No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 73 },
- .pme_group_vector = {
- 0x0000000004000040ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_0INST_FETCH],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_0INST_FETCH]
},
-#define POWER4_PME_PM_LARX_LSU1 79
[ POWER4_PME_PM_LARX_LSU1 ] = {
.pme_name = "PM_LARX_LSU1",
+ .pme_code = 0xc77,
.pme_short_desc = "Larx executed on LSU1",
.pme_long_desc = "Invalid event, larx instructions are never executed on unit 1",
- .pme_event_ids = { -1, -1, 45, 45, -1, -1, 45, 45 },
- .pme_group_vector = {
- 0x0000000000400000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LARX_LSU1],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LARX_LSU1]
},
-#define POWER4_PME_PM_LD_MISS_L1_LSU0 80
[ POWER4_PME_PM_LD_MISS_L1_LSU0 ] = {
.pme_name = "PM_LD_MISS_L1_LSU0",
+ .pme_code = 0xc12,
.pme_short_desc = "LSU0 L1 D cache load misses",
.pme_long_desc = "A load, executing on unit 0, missed the dcache",
- .pme_event_ids = { -1, -1, 46, 46, -1, -1, 46, 46 },
- .pme_group_vector = {
- 0x0000001000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LD_MISS_L1_LSU0],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LD_MISS_L1_LSU0]
},
-#define POWER4_PME_PM_L1_PREF 81
[ POWER4_PME_PM_L1_PREF ] = {
.pme_name = "PM_L1_PREF",
+ .pme_code = 0xc35,
.pme_short_desc = "L1 cache data prefetches",
.pme_long_desc = "A request to prefetch data into the L1 was made",
- .pme_event_ids = { -1, -1, 35, 35, -1, -1, 35, 35 },
- .pme_group_vector = {
- 0x0000010000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L1_PREF],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L1_PREF]
},
-#define POWER4_PME_PM_FPU1_STALL3 82
[ POWER4_PME_PM_FPU1_STALL3 ] = {
.pme_name = "PM_FPU1_STALL3",
+ .pme_code = 0x125,
.pme_short_desc = "FPU1 stalled in pipe3",
.pme_long_desc = "This signal indicates that fp1 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. ",
- .pme_event_ids = { 24, 24, -1, -1, 24, 24, -1, -1 },
- .pme_group_vector = {
- 0x0000000100000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_STALL3],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_STALL3]
},
-#define POWER4_PME_PM_BRQ_FULL_CYC 83
[ POWER4_PME_PM_BRQ_FULL_CYC ] = {
.pme_name = "PM_BRQ_FULL_CYC",
+ .pme_code = 0x205,
.pme_short_desc = "Cycles branch queue full",
.pme_long_desc = "The ISU sends a signal indicating that the issue queue that feeds the ifu br unit cannot accept any more group (queue is full of groups).",
- .pme_event_ids = { 1, 1, -1, -1, 1, 1, -1, -1 },
- .pme_group_vector = {
- 0x0080000000000010ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_BRQ_FULL_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_BRQ_FULL_CYC]
},
-#define POWER4_PME_PM_LARX 84
[ POWER4_PME_PM_LARX ] = {
.pme_name = "PM_LARX",
+ .pme_code = 0x4c70,
.pme_short_desc = "Larx executed",
.pme_long_desc = "A Larx (lwarx or ldarx) was executed. This is the combined count from LSU0 + LSU1, but these instructions only execute on LSU0",
- .pme_event_ids = { -1, -1, -1, 79, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LARX],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LARX]
},
-#define POWER4_PME_PM_MRK_DATA_FROM_L35 85
[ POWER4_PME_PM_MRK_DATA_FROM_L35 ] = {
.pme_name = "PM_MRK_DATA_FROM_L35",
+ .pme_code = 0x3c76,
.pme_short_desc = "Marked data loaded from L3.5",
.pme_long_desc = "DL1 was reloaded from the L3 of another MCM due to a marked demand load",
- .pme_event_ids = { -1, -1, 80, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0001400000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_DATA_FROM_L35],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_DATA_FROM_L35]
},
-#define POWER4_PME_PM_WORK_HELD 86
[ POWER4_PME_PM_WORK_HELD ] = {
.pme_name = "PM_WORK_HELD",
+ .pme_code = 0x2001,
.pme_short_desc = "Work held",
.pme_long_desc = "RAS Unit has signaled completion to stop and there are groups waiting to complete",
- .pme_event_ids = { -1, 92, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000200000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_WORK_HELD],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_WORK_HELD]
},
-#define POWER4_PME_PM_MRK_LD_MISS_L1_LSU0 87
[ POWER4_PME_PM_MRK_LD_MISS_L1_LSU0 ] = {
.pme_name = "PM_MRK_LD_MISS_L1_LSU0",
+ .pme_code = 0x920,
.pme_short_desc = "LSU0 L1 D cache load misses",
.pme_long_desc = "A marked load, executing on unit 0, missed the dcache",
- .pme_event_ids = { 73, 73, -1, -1, 73, 73, -1, -1 },
- .pme_group_vector = {
- 0x0004000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LD_MISS_L1_LSU0],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LD_MISS_L1_LSU0]
},
-#define POWER4_PME_PM_FXU_IDLE 88
[ POWER4_PME_PM_FXU_IDLE ] = {
.pme_name = "PM_FXU_IDLE",
+ .pme_code = 0x5002,
.pme_short_desc = "FXU idle",
.pme_long_desc = "FXU0 and FXU1 are both idle",
- .pme_event_ids = { -1, -1, -1, -1, 88, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000200000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FXU_IDLE],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FXU_IDLE]
},
-#define POWER4_PME_PM_INST_CMPL 89
[ POWER4_PME_PM_INST_CMPL ] = {
.pme_name = "PM_INST_CMPL",
+ .pme_code = 0x8001,
.pme_short_desc = "Instructions completed",
.pme_long_desc = "Number of Eligible Instructions that completed. ",
- .pme_event_ids = { 86, -1, -1, 77, -1, 86, 78, 81 },
- .pme_group_vector = {
- 0x7fffb7ffffffff9fULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_INST_CMPL],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_INST_CMPL]
},
-#define POWER4_PME_PM_LSU1_FLUSH_UST 90
[ POWER4_PME_PM_LSU1_FLUSH_UST ] = {
.pme_name = "PM_LSU1_FLUSH_UST",
+ .pme_code = 0xc05,
.pme_short_desc = "LSU1 unaligned store flushes",
.pme_long_desc = "A store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)",
- .pme_event_ids = { 64, 64, -1, -1, 64, 64, -1, -1 },
- .pme_group_vector = {
- 0x0000002000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU1_FLUSH_UST],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU1_FLUSH_UST]
},
-#define POWER4_PME_PM_LSU0_FLUSH_ULD 91
[ POWER4_PME_PM_LSU0_FLUSH_ULD ] = {
.pme_name = "PM_LSU0_FLUSH_ULD",
+ .pme_code = 0xc00,
.pme_short_desc = "LSU0 unaligned load flushes",
.pme_long_desc = "A load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { 57, 57, -1, -1, 57, 57, -1, -1 },
- .pme_group_vector = {
- 0x0000001000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU0_FLUSH_ULD],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU0_FLUSH_ULD]
},
-#define POWER4_PME_PM_INST_FROM_L2 92
[ POWER4_PME_PM_INST_FROM_L2 ] = {
.pme_name = "PM_INST_FROM_L2",
+ .pme_code = 0x3327,
.pme_short_desc = "Instructions fetched from L2",
.pme_long_desc = "An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions",
- .pme_event_ids = { -1, -1, 78, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x000000000c000040ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_INST_FROM_L2],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_INST_FROM_L2]
},
-#define POWER4_PME_PM_DATA_FROM_L3 93
[ POWER4_PME_PM_DATA_FROM_L3 ] = {
.pme_name = "PM_DATA_FROM_L3",
+ .pme_code = 0x1c66,
.pme_short_desc = "Data loaded from L3",
.pme_long_desc = "DL1 was reloaded from the local L3 due to a demand load",
- .pme_event_ids = { 82, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0400000002000020ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_DATA_FROM_L3],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DATA_FROM_L3]
},
-#define POWER4_PME_PM_FPU0_DENORM 94
[ POWER4_PME_PM_FPU0_DENORM ] = {
.pme_name = "PM_FPU0_DENORM",
+ .pme_code = 0x120,
.pme_short_desc = "FPU0 received denormalized data",
.pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.",
- .pme_event_ids = { 9, 9, -1, -1, 9, 9, -1, -1 },
- .pme_group_vector = {
- 0x0000000040000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_DENORM],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_DENORM]
},
-#define POWER4_PME_PM_FPU1_FMOV_FEST 95
[ POWER4_PME_PM_FPU1_FMOV_FEST ] = {
.pme_name = "PM_FPU1_FMOV_FEST",
+ .pme_code = 0x114,
.pme_short_desc = "FPU1 executing FMOV or FEST instructions",
.pme_long_desc = "This signal is active for one cycle when fp1 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ",
- .pme_event_ids = { -1, -1, 28, 28, -1, -1, 28, 28 },
- .pme_group_vector = {
- 0x0000000040000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_FMOV_FEST],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_FMOV_FEST]
},
-#define POWER4_PME_PM_GRP_DISP_REJECT 96
[ POWER4_PME_PM_GRP_DISP_REJECT ] = {
.pme_name = "PM_GRP_DISP_REJECT",
+ .pme_code = 0x8003,
.pme_short_desc = "Group dispatch rejected",
.pme_long_desc = "A group that previously attempted dispatch was rejected.",
- .pme_event_ids = { 27, 27, -1, -1, 27, 27, -1, 80 },
- .pme_group_vector = {
- 0x0000000000100001ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_GRP_DISP_REJECT],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_GRP_DISP_REJECT]
},
-#define POWER4_PME_PM_INST_FETCH_CYC 97
[ POWER4_PME_PM_INST_FETCH_CYC ] = {
.pme_name = "PM_INST_FETCH_CYC",
+ .pme_code = 0x323,
.pme_short_desc = "Cycles at least 1 instruction fetched",
.pme_long_desc = "Asserted each cycle when the IFU sends at least one instruction to the IDU. ",
- .pme_event_ids = { 33, 33, -1, -1, 33, 33, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000008ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_INST_FETCH_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_INST_FETCH_CYC]
},
-#define POWER4_PME_PM_LSU_LDF 98
[ POWER4_PME_PM_LSU_LDF ] = {
.pme_name = "PM_LSU_LDF",
+ .pme_code = 0x8930,
.pme_short_desc = "LSU executed Floating Point load instruction",
.pme_long_desc = "LSU executed Floating Point load instruction",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 78 },
- .pme_group_vector = {
- 0x1040000000008000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_LDF],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_LDF]
},
-#define POWER4_PME_PM_INST_DISP 99
[ POWER4_PME_PM_INST_DISP ] = {
.pme_name = "PM_INST_DISP",
+ .pme_code = 0x221,
.pme_short_desc = "Instructions dispatched",
.pme_long_desc = "The ISU sends the number of instructions dispatched.",
- .pme_event_ids = { 32, 32, -1, -1, 32, 32, -1, -1 },
- .pme_group_vector = {
- 0x0000000000140006ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_INST_DISP],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_INST_DISP]
},
-#define POWER4_PME_PM_L2SA_MOD_INV 100
[ POWER4_PME_PM_L2SA_MOD_INV ] = {
.pme_name = "PM_L2SA_MOD_INV",
+ .pme_code = 0xf07,
.pme_short_desc = "L2 slice A transition from modified to invalid",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.",
- .pme_event_ids = { 37, 37, -1, -1, 37, 37, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000800ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SA_MOD_INV],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SA_MOD_INV]
},
-#define POWER4_PME_PM_DATA_FROM_L25_SHR 101
[ POWER4_PME_PM_DATA_FROM_L25_SHR ] = {
.pme_name = "PM_DATA_FROM_L25_SHR",
+ .pme_code = 0x5c66,
.pme_short_desc = "Data loaded from L2.5 shared",
.pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a demand load",
- .pme_event_ids = { -1, -1, -1, -1, 83, -1, -1, -1 },
- .pme_group_vector = {
- 0x0600000001000020ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_DATA_FROM_L25_SHR],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DATA_FROM_L25_SHR]
},
-#define POWER4_PME_PM_FAB_CMD_RETRIED 102
[ POWER4_PME_PM_FAB_CMD_RETRIED ] = {
.pme_name = "PM_FAB_CMD_RETRIED",
+ .pme_code = 0xf17,
.pme_short_desc = "Fabric command retried",
.pme_long_desc = "A bus command on the MCM to MCM fabric was retried. This event is the total count of all retried fabric commands for the local MCM (all four chips report the same value). This event is scaled to the fabric frequency and must be adjusted for a true count. i.e. if the fabric is running 2:1, divide the count by 2.",
- .pme_event_ids = { -1, -1, 18, 18, -1, -1, 18, 18 },
- .pme_group_vector = {
- 0x0000000000000400ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FAB_CMD_RETRIED],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FAB_CMD_RETRIED]
},
-#define POWER4_PME_PM_L1_DCACHE_RELOAD_VALID 103
[ POWER4_PME_PM_L1_DCACHE_RELOAD_VALID ] = {
.pme_name = "PM_L1_DCACHE_RELOAD_VALID",
+ .pme_code = 0xc64,
.pme_short_desc = "L1 reload data source valid",
.pme_long_desc = "The data source information is valid",
- .pme_event_ids = { 36, 36, -1, -1, 36, 36, -1, -1 },
- .pme_group_vector = {
- 0x0000008003000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L1_DCACHE_RELOAD_VALID],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L1_DCACHE_RELOAD_VALID]
},
-#define POWER4_PME_PM_MRK_GRP_ISSUED 104
[ POWER4_PME_PM_MRK_GRP_ISSUED ] = {
.pme_name = "PM_MRK_GRP_ISSUED",
+ .pme_code = 0x6005,
.pme_short_desc = "Marked group issued",
.pme_long_desc = "A sampled instruction was issued",
- .pme_event_ids = { -1, -1, -1, -1, -1, 92, -1, -1 },
- .pme_group_vector = {
- 0x0018240000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_GRP_ISSUED],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_GRP_ISSUED]
},
-#define POWER4_PME_PM_FPU_FULL_CYC 105
[ POWER4_PME_PM_FPU_FULL_CYC ] = {
.pme_name = "PM_FPU_FULL_CYC",
+ .pme_code = 0x5200,
.pme_short_desc = "Cycles FPU issue queue full",
.pme_long_desc = "Cycles when one or both FPU issue queues are full",
- .pme_event_ids = { -1, -1, -1, -1, 86, -1, -1, -1 },
- .pme_group_vector = {
- 0x0040000000000010ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_FULL_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_FULL_CYC]
},
-#define POWER4_PME_PM_FPU_FMA 106
[ POWER4_PME_PM_FPU_FMA ] = {
.pme_name = "PM_FPU_FMA",
+ .pme_code = 0x2100,
.pme_short_desc = "FPU executed multiply-add instruction",
.pme_long_desc = "This signal is active for one cycle when FPU is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, 83, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x1020000000004000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_FMA],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_FMA]
},
-#define POWER4_PME_PM_MRK_CRU_FIN 107
[ POWER4_PME_PM_MRK_CRU_FIN ] = {
.pme_name = "PM_MRK_CRU_FIN",
+ .pme_code = 0x4005,
.pme_short_desc = "Marked instruction CRU processing finished",
.pme_long_desc = "The Condition Register Unit finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, -1, -1, 82, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000080000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_CRU_FIN],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_CRU_FIN]
},
-#define POWER4_PME_PM_MRK_LSU1_FLUSH_UST 108
[ POWER4_PME_PM_MRK_LSU1_FLUSH_UST ] = {
.pme_name = "PM_MRK_LSU1_FLUSH_UST",
+ .pme_code = 0x915,
.pme_short_desc = "LSU1 marked unaligned store flushes",
.pme_long_desc = "A marked store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)",
- .pme_event_ids = { -1, -1, 66, 66, -1, -1, 66, 66 },
- .pme_group_vector = {
- 0x0002000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU1_FLUSH_UST],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU1_FLUSH_UST]
},
-#define POWER4_PME_PM_MRK_FXU_FIN 109
[ POWER4_PME_PM_MRK_FXU_FIN ] = {
.pme_name = "PM_MRK_FXU_FIN",
+ .pme_code = 0x6004,
.pme_short_desc = "Marked instruction FXU processing finished",
.pme_long_desc = "One of the Fixed Point Units finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, -1, -1, -1, -1, 91, -1, -1 },
- .pme_group_vector = {
- 0x0000080000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_FXU_FIN],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_FXU_FIN]
},
-#define POWER4_PME_PM_BR_ISSUED 110
[ POWER4_PME_PM_BR_ISSUED ] = {
.pme_name = "PM_BR_ISSUED",
+ .pme_code = 0x330,
.pme_short_desc = "Branches issued",
.pme_long_desc = "This signal will be asserted each time the ISU issues a branch instruction. This signal will be asserted each time the ISU selects a branch instruction to issue.",
- .pme_event_ids = { -1, -1, 8, 8, -1, -1, 8, 8 },
- .pme_group_vector = {
- 0x6080000000000008ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_BR_ISSUED],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_BR_ISSUED]
},
-#define POWER4_PME_PM_EE_OFF 111
[ POWER4_PME_PM_EE_OFF ] = {
.pme_name = "PM_EE_OFF",
+ .pme_code = 0x233,
.pme_short_desc = "Cycles MSR(EE) bit off",
.pme_long_desc = "The number of Cycles MSR(EE) bit was off.",
- .pme_event_ids = { -1, -1, 15, 15, -1, -1, 15, 15 },
- .pme_group_vector = {
- 0x0000000000200000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_EE_OFF],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_EE_OFF]
},
-#define POWER4_PME_PM_INST_FROM_L3 112
[ POWER4_PME_PM_INST_FROM_L3 ] = {
.pme_name = "PM_INST_FROM_L3",
+ .pme_code = 0x5327,
.pme_short_desc = "Instruction fetched from L3",
.pme_long_desc = "An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions",
- .pme_event_ids = { -1, -1, -1, -1, 91, -1, -1, -1 },
- .pme_group_vector = {
- 0x000000000c000040ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_INST_FROM_L3],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_INST_FROM_L3]
},
-#define POWER4_PME_PM_ITLB_MISS 113
[ POWER4_PME_PM_ITLB_MISS ] = {
.pme_name = "PM_ITLB_MISS",
+ .pme_code = 0x900,
.pme_short_desc = "Instruction TLB misses",
.pme_long_desc = "A TLB miss for an Instruction Fetch has occurred",
- .pme_event_ids = { 35, 35, -1, -1, 35, 35, -1, -1 },
- .pme_group_vector = {
- 0x0100000000000100ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_ITLB_MISS],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_ITLB_MISS]
},
-#define POWER4_PME_PM_FXLS_FULL_CYC 114
[ POWER4_PME_PM_FXLS_FULL_CYC ] = {
.pme_name = "PM_FXLS_FULL_CYC",
+ .pme_code = 0x8210,
.pme_short_desc = "Cycles FXLS queue is full",
.pme_long_desc = "Cycles when one or both FXU/LSU issue queue are full",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 79 },
- .pme_group_vector = {
- 0x0000000200000010ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FXLS_FULL_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FXLS_FULL_CYC]
},
-#define POWER4_PME_PM_FXU1_BUSY_FXU0_IDLE 115
[ POWER4_PME_PM_FXU1_BUSY_FXU0_IDLE ] = {
.pme_name = "PM_FXU1_BUSY_FXU0_IDLE",
+ .pme_code = 0x4002,
.pme_short_desc = "FXU1 busy FXU0 idle",
.pme_long_desc = "FXU0 was idle while FXU1 was busy",
- .pme_event_ids = { -1, -1, -1, 76, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000200000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FXU1_BUSY_FXU0_IDLE],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FXU1_BUSY_FXU0_IDLE]
},
-#define POWER4_PME_PM_GRP_DISP_VALID 116
[ POWER4_PME_PM_GRP_DISP_VALID ] = {
.pme_name = "PM_GRP_DISP_VALID",
+ .pme_code = 0x223,
.pme_short_desc = "Group dispatch valid",
.pme_long_desc = "Dispatch has been attempted for a valid group. Some groups may be rejected. The total number of successful dispatches is the number of dispatch valid minus dispatch reject.",
- .pme_event_ids = { 28, 28, -1, -1, 28, 28, -1, -1 },
- .pme_group_vector = {
- 0x0000000000100000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_GRP_DISP_VALID],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_GRP_DISP_VALID]
},
-#define POWER4_PME_PM_L2SC_ST_HIT 117
[ POWER4_PME_PM_L2SC_ST_HIT ] = {
.pme_name = "PM_L2SC_ST_HIT",
+ .pme_code = 0xf15,
.pme_short_desc = "L2 slice C store hits",
.pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A,B, and C.",
- .pme_event_ids = { -1, -1, 41, 41, -1, -1, 41, 41 },
- .pme_group_vector = {
- 0x0000000000002000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SC_ST_HIT],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SC_ST_HIT]
},
-#define POWER4_PME_PM_MRK_GRP_DISP 118
[ POWER4_PME_PM_MRK_GRP_DISP ] = {
.pme_name = "PM_MRK_GRP_DISP",
+ .pme_code = 0x1002,
.pme_short_desc = "Marked group dispatched",
.pme_long_desc = "A group containing a sampled instruction was dispatched",
- .pme_event_ids = { 91, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000080000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_GRP_DISP],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_GRP_DISP]
},
-#define POWER4_PME_PM_L2SB_MOD_TAG 119
[ POWER4_PME_PM_L2SB_MOD_TAG ] = {
.pme_name = "PM_L2SB_MOD_TAG",
+ .pme_code = 0xf22,
.pme_short_desc = "L2 slice B transition from modified to tagged",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.",
- .pme_event_ids = { 42, 42, -1, -1, 42, 42, -1, -1 },
- .pme_group_vector = {
- 0x0000000000001000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SB_MOD_TAG],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SB_MOD_TAG]
},
-#define POWER4_PME_PM_INST_FROM_L25_L275 120
[ POWER4_PME_PM_INST_FROM_L25_L275 ] = {
.pme_name = "PM_INST_FROM_L25_L275",
+ .pme_code = 0x2327,
.pme_short_desc = "Instruction fetched from L2.5/L2.75",
.pme_long_desc = "An instruction fetch group was fetched from the L2 of another chip. Fetch Groups can contain up to 8 instructions",
- .pme_event_ids = { -1, 86, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000008000040ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_INST_FROM_L25_L275],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_INST_FROM_L25_L275]
},
-#define POWER4_PME_PM_LSU_FLUSH_UST 121
[ POWER4_PME_PM_LSU_FLUSH_UST ] = {
.pme_name = "PM_LSU_FLUSH_UST",
+ .pme_code = 0x2c00,
.pme_short_desc = "SRQ unaligned store flushes",
.pme_long_desc = "A store was flushed because it was unaligned",
- .pme_event_ids = { -1, 87, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000080ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_FLUSH_UST],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_FLUSH_UST]
},
-#define POWER4_PME_PM_L2SB_ST_HIT 122
[ POWER4_PME_PM_L2SB_ST_HIT ] = {
.pme_name = "PM_L2SB_ST_HIT",
+ .pme_code = 0xf13,
.pme_short_desc = "L2 slice B store hits",
.pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A,B, and C.",
- .pme_event_ids = { -1, -1, 39, 39, -1, -1, 39, 39 },
- .pme_group_vector = {
- 0x0000000000001000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SB_ST_HIT],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SB_ST_HIT]
},
-#define POWER4_PME_PM_FXU1_FIN 123
[ POWER4_PME_PM_FXU1_FIN ] = {
.pme_name = "PM_FXU1_FIN",
+ .pme_code = 0x236,
.pme_short_desc = "FXU1 produced a result",
.pme_long_desc = "The Fixed Point unit 1 finished an instruction and produced a result",
- .pme_event_ids = { -1, -1, 32, 32, -1, -1, 32, 32 },
- .pme_group_vector = {
- 0x0000000000100000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FXU1_FIN],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FXU1_FIN]
},
-#define POWER4_PME_PM_L3B1_DIR_MIS 124
[ POWER4_PME_PM_L3B1_DIR_MIS ] = {
.pme_name = "PM_L3B1_DIR_MIS",
+ .pme_code = 0xf03,
.pme_short_desc = "L3 bank 1 directory misses",
.pme_long_desc = "A reference was made to the local L3 directory by a local CPU and it missed in the L3. Only requests from on-MCM CPUs are counted. This event is scaled to the L3 speed and the count must be scaled. i.e. if the L3 is running 3:1, divide the count by 3",
- .pme_event_ids = { 51, 51, -1, -1, 51, 51, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000400ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L3B1_DIR_MIS],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L3B1_DIR_MIS]
},
-#define POWER4_PME_PM_4INST_CLB_CYC 125
[ POWER4_PME_PM_4INST_CLB_CYC ] = {
.pme_name = "PM_4INST_CLB_CYC",
+ .pme_code = 0x453,
.pme_short_desc = "Cycles 4 instructions in CLB",
.pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.",
- .pme_event_ids = { -1, -1, 3, 3, -1, -1, 3, 3 },
- .pme_group_vector = {
- 0x0000000000010000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_4INST_CLB_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_4INST_CLB_CYC]
},
-#define POWER4_PME_PM_GRP_CMPL 126
[ POWER4_PME_PM_GRP_CMPL ] = {
.pme_name = "PM_GRP_CMPL",
+ .pme_code = 0x7003,
.pme_short_desc = "Group completed",
.pme_long_desc = "A group completed. Microcoded instructions that span multiple groups will generate this event once per group.",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 77, -1 },
- .pme_group_vector = {
- 0x0010020000000001ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_GRP_CMPL],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_GRP_CMPL]
},
-#define POWER4_PME_PM_DC_PREF_L2_CLONE_L3 127
[ POWER4_PME_PM_DC_PREF_L2_CLONE_L3 ] = {
.pme_name = "PM_DC_PREF_L2_CLONE_L3",
+ .pme_code = 0xc27,
.pme_short_desc = "L2 prefetch cloned with L3",
.pme_long_desc = "A prefetch request was made to the L2 with a cloned request sent to the L3",
- .pme_event_ids = { 3, 3, -1, -1, 3, 3, -1, -1 },
- .pme_group_vector = {
- 0x0000010000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_DC_PREF_L2_CLONE_L3],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DC_PREF_L2_CLONE_L3]
},
-#define POWER4_PME_PM_FPU_FRSP_FCONV 128
[ POWER4_PME_PM_FPU_FRSP_FCONV ] = {
.pme_name = "PM_FPU_FRSP_FCONV",
+ .pme_code = 0x7110,
.pme_short_desc = "FPU executed FRSP or FCONV instructions",
.pme_long_desc = "This signal is active for one cycle when executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 75, -1 },
- .pme_group_vector = {
- 0x0000000000008000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_FRSP_FCONV],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_FRSP_FCONV]
},
-#define POWER4_PME_PM_5INST_CLB_CYC 129
[ POWER4_PME_PM_5INST_CLB_CYC ] = {
.pme_name = "PM_5INST_CLB_CYC",
+ .pme_code = 0x454,
.pme_short_desc = "Cycles 5 instructions in CLB",
.pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.",
- .pme_event_ids = { -1, -1, 4, 4, -1, -1, 4, 4 },
- .pme_group_vector = {
- 0x0000000000020000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_5INST_CLB_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_5INST_CLB_CYC]
},
-#define POWER4_PME_PM_MRK_LSU0_FLUSH_SRQ 130
[ POWER4_PME_PM_MRK_LSU0_FLUSH_SRQ ] = {
.pme_name = "PM_MRK_LSU0_FLUSH_SRQ",
+ .pme_code = 0x913,
.pme_short_desc = "LSU0 marked SRQ flushes",
.pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { -1, -1, 59, 59, -1, -1, 59, 59 },
- .pme_group_vector = {
- 0x0004000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU0_FLUSH_SRQ],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU0_FLUSH_SRQ]
},
-#define POWER4_PME_PM_MRK_LSU_FLUSH_ULD 131
[ POWER4_PME_PM_MRK_LSU_FLUSH_ULD ] = {
.pme_name = "PM_MRK_LSU_FLUSH_ULD",
+ .pme_code = 0x8910,
.pme_short_desc = "Marked unaligned load flushes",
.pme_long_desc = "A marked load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 85 },
- .pme_group_vector = {
- 0x0000200000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU_FLUSH_ULD],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU_FLUSH_ULD]
},
-#define POWER4_PME_PM_8INST_CLB_CYC 132
[ POWER4_PME_PM_8INST_CLB_CYC ] = {
.pme_name = "PM_8INST_CLB_CYC",
+ .pme_code = 0x457,
.pme_short_desc = "Cycles 8 instructions in CLB",
.pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.",
- .pme_event_ids = { -1, -1, 7, 7, -1, -1, 7, 7 },
- .pme_group_vector = {
- 0x0000000000020000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_8INST_CLB_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_8INST_CLB_CYC]
},
-#define POWER4_PME_PM_LSU_LMQ_FULL_CYC 133
[ POWER4_PME_PM_LSU_LMQ_FULL_CYC ] = {
.pme_name = "PM_LSU_LMQ_FULL_CYC",
+ .pme_code = 0x927,
.pme_short_desc = "Cycles LMQ full",
.pme_long_desc = "The LMQ was full",
- .pme_event_ids = { 66, 66, -1, -1, 66, 66, -1, -1 },
- .pme_group_vector = {
- 0x0000000400000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_LMQ_FULL_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_LMQ_FULL_CYC]
},
-#define POWER4_PME_PM_ST_REF_L1_LSU0 134
[ POWER4_PME_PM_ST_REF_L1_LSU0 ] = {
.pme_name = "PM_ST_REF_L1_LSU0",
+ .pme_code = 0xc11,
.pme_short_desc = "LSU0 L1 D cache store references",
.pme_long_desc = "A store executed on unit 0",
- .pme_event_ids = { -1, -1, 71, 71, -1, -1, 71, 71 },
- .pme_group_vector = {
- 0x0000006000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_ST_REF_L1_LSU0],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_ST_REF_L1_LSU0]
},
-#define POWER4_PME_PM_LSU0_DERAT_MISS 135
[ POWER4_PME_PM_LSU0_DERAT_MISS ] = {
.pme_name = "PM_LSU0_DERAT_MISS",
+ .pme_code = 0x902,
.pme_short_desc = "LSU0 DERAT misses",
.pme_long_desc = "A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.",
- .pme_event_ids = { 54, 54, -1, -1, 54, 54, -1, -1 },
- .pme_group_vector = {
- 0x0000008000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU0_DERAT_MISS],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU0_DERAT_MISS]
},
-#define POWER4_PME_PM_LSU_SRQ_SYNC_CYC 136
[ POWER4_PME_PM_LSU_SRQ_SYNC_CYC ] = {
.pme_name = "PM_LSU_SRQ_SYNC_CYC",
+ .pme_code = 0x932,
.pme_short_desc = "SRQ sync duration",
.pme_long_desc = "This signal is asserted every cycle when a sync is in the SRQ.",
- .pme_event_ids = { -1, -1, 56, 56, -1, -1, 56, 56 },
- .pme_group_vector = {
- 0x0000000400000200ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_SRQ_SYNC_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_SRQ_SYNC_CYC]
},
-#define POWER4_PME_PM_FPU_STALL3 137
[ POWER4_PME_PM_FPU_STALL3 ] = {
.pme_name = "PM_FPU_STALL3",
+ .pme_code = 0x2120,
.pme_short_desc = "FPU stalled in pipe3",
.pme_long_desc = "FPU has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, 84, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0040000000008000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_STALL3],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_STALL3]
},
-#define POWER4_PME_PM_MRK_DATA_FROM_L2 138
[ POWER4_PME_PM_MRK_DATA_FROM_L2 ] = {
.pme_name = "PM_MRK_DATA_FROM_L2",
+ .pme_code = 0x4c76,
.pme_short_desc = "Marked data loaded from L2",
.pme_long_desc = "DL1 was reloaded from the local L2 due to a marked demand load",
- .pme_event_ids = { -1, -1, -1, 83, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0001c00000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_DATA_FROM_L2],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_DATA_FROM_L2]
},
-#define POWER4_PME_PM_FPU0_FMOV_FEST 139
[ POWER4_PME_PM_FPU0_FMOV_FEST ] = {
.pme_name = "PM_FPU0_FMOV_FEST",
+ .pme_code = 0x110,
.pme_short_desc = "FPU0 executed FMOV or FEST instructions",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ",
- .pme_event_ids = { -1, -1, 23, 23, -1, -1, 23, 23 },
- .pme_group_vector = {
- 0x0000000040000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_FMOV_FEST],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_FMOV_FEST]
},
-#define POWER4_PME_PM_LSU0_FLUSH_SRQ 140
[ POWER4_PME_PM_LSU0_FLUSH_SRQ ] = {
.pme_name = "PM_LSU0_FLUSH_SRQ",
+ .pme_code = 0xc03,
.pme_short_desc = "LSU0 SRQ flushes",
.pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { 56, 56, -1, -1, 56, 56, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU0_FLUSH_SRQ],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU0_FLUSH_SRQ]
},
-#define POWER4_PME_PM_LD_REF_L1_LSU0 141
[ POWER4_PME_PM_LD_REF_L1_LSU0 ] = {
.pme_name = "PM_LD_REF_L1_LSU0",
+ .pme_code = 0xc10,
.pme_short_desc = "LSU0 L1 D cache load references",
.pme_long_desc = "A load executed on unit 0",
- .pme_event_ids = { -1, -1, 48, 48, -1, -1, 48, 48 },
- .pme_group_vector = {
- 0x0000001000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LD_REF_L1_LSU0],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LD_REF_L1_LSU0]
},
-#define POWER4_PME_PM_L2SC_SHR_INV 142
[ POWER4_PME_PM_L2SC_SHR_INV ] = {
.pme_name = "PM_L2SC_SHR_INV",
+ .pme_code = 0xf25,
.pme_short_desc = "L2 slice C transition from shared to invalid",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.",
- .pme_event_ids = { 47, 47, -1, -1, 47, 47, -1, -1 },
- .pme_group_vector = {
- 0x0000000000002000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SC_SHR_INV],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SC_SHR_INV]
},
-#define POWER4_PME_PM_LSU1_FLUSH_SRQ 143
[ POWER4_PME_PM_LSU1_FLUSH_SRQ ] = {
.pme_name = "PM_LSU1_FLUSH_SRQ",
+ .pme_code = 0xc07,
.pme_short_desc = "LSU1 SRQ flushes",
.pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. ",
- .pme_event_ids = { 62, 62, -1, -1, 62, 62, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU1_FLUSH_SRQ],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU1_FLUSH_SRQ]
},
-#define POWER4_PME_PM_LSU_LMQ_S0_ALLOC 144
[ POWER4_PME_PM_LSU_LMQ_S0_ALLOC ] = {
.pme_name = "PM_LSU_LMQ_S0_ALLOC",
+ .pme_code = 0x935,
.pme_short_desc = "LMQ slot 0 allocated",
.pme_long_desc = "The first entry in the LMQ was allocated.",
- .pme_event_ids = { -1, -1, 52, 52, -1, -1, 52, 52 },
- .pme_group_vector = {
- 0x0010000400000200ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_LMQ_S0_ALLOC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_LMQ_S0_ALLOC]
},
-#define POWER4_PME_PM_ST_REF_L1 145
[ POWER4_PME_PM_ST_REF_L1 ] = {
.pme_name = "PM_ST_REF_L1",
+ .pme_code = 0x7c10,
.pme_short_desc = "L1 D cache store references",
.pme_long_desc = "Total DL1 Store references",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 84, -1 },
- .pme_group_vector = {
- 0x4900000000000086ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_ST_REF_L1],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_ST_REF_L1]
},
-#define POWER4_PME_PM_LSU_SRQ_EMPTY_CYC 146
[ POWER4_PME_PM_LSU_SRQ_EMPTY_CYC ] = {
.pme_name = "PM_LSU_SRQ_EMPTY_CYC",
+ .pme_code = 0x4003,
.pme_short_desc = "Cycles SRQ empty",
.pme_long_desc = "The Store Request Queue is empty",
- .pme_event_ids = { -1, -1, -1, 81, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_SRQ_EMPTY_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_SRQ_EMPTY_CYC]
},
-#define POWER4_PME_PM_FPU1_STF 147
[ POWER4_PME_PM_FPU1_STF ] = {
.pme_name = "PM_FPU1_STF",
+ .pme_code = 0x126,
.pme_short_desc = "FPU1 executed store instruction",
.pme_long_desc = "This signal is active for one cycle when fp1 is executing a store instruction.",
- .pme_event_ids = { 25, 25, -1, -1, 25, 25, -1, -1 },
- .pme_group_vector = {
- 0x0000000080000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_STF],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_STF]
},
-#define POWER4_PME_PM_L3B0_DIR_REF 148
[ POWER4_PME_PM_L3B0_DIR_REF ] = {
.pme_name = "PM_L3B0_DIR_REF",
+ .pme_code = 0xf00,
.pme_short_desc = "L3 bank 0 directory references",
.pme_long_desc = "A reference was made to the local L3 directory by a local CPU. Only requests from on-MCM CPUs are counted. This event is scaled to the L3 speed and the count must be scaled. i.e. if the L3 is running 3:1, divide the count by 3",
- .pme_event_ids = { 50, 50, -1, -1, 50, 50, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000400ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L3B0_DIR_REF],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L3B0_DIR_REF]
},
-#define POWER4_PME_PM_RUN_CYC 149
[ POWER4_PME_PM_RUN_CYC ] = {
.pme_name = "PM_RUN_CYC",
+ .pme_code = 0x1005,
.pme_short_desc = "Run cycles",
.pme_long_desc = "Processor Cycles gated by the run latch",
- .pme_event_ids = { 94, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000001ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_RUN_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_RUN_CYC]
},
-#define POWER4_PME_PM_LSU_LMQ_S0_VALID 150
[ POWER4_PME_PM_LSU_LMQ_S0_VALID ] = {
.pme_name = "PM_LSU_LMQ_S0_VALID",
+ .pme_code = 0x931,
.pme_short_desc = "LMQ slot 0 valid",
.pme_long_desc = "This signal is asserted every cycle when the first entry in the LMQ is valid. The LMQ had eight entries that are allocated FIFO",
- .pme_event_ids = { -1, -1, 53, 53, -1, -1, 53, 53 },
- .pme_group_vector = {
- 0x0010000400000100ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_LMQ_S0_VALID],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_LMQ_S0_VALID]
},
-#define POWER4_PME_PM_LSU_LRQ_S0_VALID 151
[ POWER4_PME_PM_LSU_LRQ_S0_VALID ] = {
.pme_name = "PM_LSU_LRQ_S0_VALID",
+ .pme_code = 0xc22,
.pme_short_desc = "LRQ slot 0 valid",
.pme_long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.",
- .pme_event_ids = { 69, 69, -1, -1, 69, 69, -1, -1 },
- .pme_group_vector = {
- 0x0000000000800000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_LRQ_S0_VALID],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_LRQ_S0_VALID]
},
-#define POWER4_PME_PM_LSU0_LDF 152
[ POWER4_PME_PM_LSU0_LDF ] = {
.pme_name = "PM_LSU0_LDF",
+ .pme_code = 0x930,
.pme_short_desc = "LSU0 executed Floating Point load instruction",
.pme_long_desc = "A floating point load was executed from LSU unit 0",
- .pme_event_ids = { -1, -1, 19, 19, -1, -1, 19, 19 },
- .pme_group_vector = {
- 0x0000000080000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU0_LDF],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU0_LDF]
},
-#define POWER4_PME_PM_MRK_IMR_RELOAD 153
[ POWER4_PME_PM_MRK_IMR_RELOAD ] = {
.pme_name = "PM_MRK_IMR_RELOAD",
+ .pme_code = 0x922,
.pme_short_desc = "Marked IMR reloaded",
.pme_long_desc = "A DL1 reload occured due to marked load",
- .pme_event_ids = { 72, 72, -1, -1, 72, 72, -1, -1 },
- .pme_group_vector = {
- 0x0002000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_IMR_RELOAD],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_IMR_RELOAD]
},
-#define POWER4_PME_PM_7INST_CLB_CYC 154
[ POWER4_PME_PM_7INST_CLB_CYC ] = {
.pme_name = "PM_7INST_CLB_CYC",
+ .pme_code = 0x456,
.pme_short_desc = "Cycles 7 instructions in CLB",
.pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.",
- .pme_event_ids = { -1, -1, 6, 6, -1, -1, 6, 6 },
- .pme_group_vector = {
- 0x0000000000020000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_7INST_CLB_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_7INST_CLB_CYC]
},
-#define POWER4_PME_PM_MRK_GRP_TIMEO 155
[ POWER4_PME_PM_MRK_GRP_TIMEO ] = {
.pme_name = "PM_MRK_GRP_TIMEO",
+ .pme_code = 0x5005,
.pme_short_desc = "Marked group completion timeout",
.pme_long_desc = "The sampling timeout expired indicating that the previously sampled instruction is no longer in the processor",
- .pme_event_ids = { -1, -1, -1, -1, 94, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000300000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_GRP_TIMEO],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_GRP_TIMEO]
},
-#define POWER4_PME_PM_FPU_FMOV_FEST 156
[ POWER4_PME_PM_FPU_FMOV_FEST ] = {
.pme_name = "PM_FPU_FMOV_FEST",
+ .pme_code = 0x8110,
.pme_short_desc = "FPU executing FMOV or FEST instructions",
.pme_long_desc = "This signal is active for one cycle when executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ . Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 77 },
- .pme_group_vector = {
- 0x0020000000004000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_FMOV_FEST],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_FMOV_FEST]
},
-#define POWER4_PME_PM_GRP_DISP_BLK_SB_CYC 157
[ POWER4_PME_PM_GRP_DISP_BLK_SB_CYC ] = {
.pme_name = "PM_GRP_DISP_BLK_SB_CYC",
+ .pme_code = 0x231,
.pme_short_desc = "Cycles group dispatch blocked by scoreboard",
.pme_long_desc = "The ISU sends a signal indicating that dispatch is blocked by scoreboard.",
- .pme_event_ids = { -1, -1, 34, 34, -1, -1, 34, 34 },
- .pme_group_vector = {
- 0x0000000000040000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_GRP_DISP_BLK_SB_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_GRP_DISP_BLK_SB_CYC]
},
-#define POWER4_PME_PM_XER_MAP_FULL_CYC 158
[ POWER4_PME_PM_XER_MAP_FULL_CYC ] = {
.pme_name = "PM_XER_MAP_FULL_CYC",
+ .pme_code = 0x202,
.pme_short_desc = "Cycles XER mapper full",
.pme_long_desc = "The ISU sends a signal indicating that the xer mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.",
- .pme_event_ids = { 80, 80, -1, -1, 80, 80, -1, -1 },
- .pme_group_vector = {
- 0x0000000000040000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_XER_MAP_FULL_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_XER_MAP_FULL_CYC]
},
-#define POWER4_PME_PM_ST_MISS_L1 159
[ POWER4_PME_PM_ST_MISS_L1 ] = {
.pme_name = "PM_ST_MISS_L1",
+ .pme_code = 0xc23,
.pme_short_desc = "L1 D cache store misses",
.pme_long_desc = "A store missed the dcache",
- .pme_event_ids = { 79, 79, 70, 70, 79, 79, 70, 70 },
- .pme_group_vector = {
- 0x6900006000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_ST_MISS_L1],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_ST_MISS_L1]
},
-#define POWER4_PME_PM_STOP_COMPLETION 160
[ POWER4_PME_PM_STOP_COMPLETION ] = {
.pme_name = "PM_STOP_COMPLETION",
+ .pme_code = 0x3001,
.pme_short_desc = "Completion stopped",
.pme_long_desc = "RAS Unit has signaled completion to stop",
- .pme_event_ids = { -1, -1, 83, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000200001ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_STOP_COMPLETION],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_STOP_COMPLETION]
},
-#define POWER4_PME_PM_MRK_GRP_CMPL 161
[ POWER4_PME_PM_MRK_GRP_CMPL ] = {
.pme_name = "PM_MRK_GRP_CMPL",
+ .pme_code = 0x4004,
.pme_short_desc = "Marked group completed",
.pme_long_desc = "A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group.",
- .pme_event_ids = { -1, -1, -1, 84, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000140000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_GRP_CMPL],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_GRP_CMPL]
},
-#define POWER4_PME_PM_ISLB_MISS 162
[ POWER4_PME_PM_ISLB_MISS ] = {
.pme_name = "PM_ISLB_MISS",
+ .pme_code = 0x901,
.pme_short_desc = "Instruction SLB misses",
.pme_long_desc = "A SLB miss for an instruction fetch as occurred",
- .pme_event_ids = { 34, 34, -1, -1, 34, 34, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000200ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_ISLB_MISS],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_ISLB_MISS]
},
-#define POWER4_PME_PM_CYC 163
[ POWER4_PME_PM_CYC ] = {
.pme_name = "PM_CYC",
+ .pme_code = 0x7,
.pme_short_desc = "Processor cycles",
.pme_long_desc = "Processor cycles",
- .pme_event_ids = { 81, 81, 73, 73, 82, 81, 73, 74 },
- .pme_group_vector = {
- 0x7fffbfffffffff9fULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_CYC]
},
-#define POWER4_PME_PM_LD_MISS_L1_LSU1 164
[ POWER4_PME_PM_LD_MISS_L1_LSU1 ] = {
.pme_name = "PM_LD_MISS_L1_LSU1",
+ .pme_code = 0xc16,
.pme_short_desc = "LSU1 L1 D cache load misses",
.pme_long_desc = "A load, executing on unit 1, missed the dcache",
- .pme_event_ids = { -1, -1, 47, 47, -1, -1, 47, 47 },
- .pme_group_vector = {
- 0x0000001000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LD_MISS_L1_LSU1],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LD_MISS_L1_LSU1]
},
-#define POWER4_PME_PM_STCX_FAIL 165
[ POWER4_PME_PM_STCX_FAIL ] = {
.pme_name = "PM_STCX_FAIL",
+ .pme_code = 0x921,
.pme_short_desc = "STCX failed",
.pme_long_desc = "A stcx (stwcx or stdcx) failed",
- .pme_event_ids = { 78, 78, -1, -1, 78, 78, -1, -1 },
- .pme_group_vector = {
- 0x0000000000400000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_STCX_FAIL],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_STCX_FAIL]
},
-#define POWER4_PME_PM_LSU1_SRQ_STFWD 166
[ POWER4_PME_PM_LSU1_SRQ_STFWD ] = {
.pme_name = "PM_LSU1_SRQ_STFWD",
+ .pme_code = 0xc24,
.pme_short_desc = "LSU1 SRQ store forwarded",
.pme_long_desc = "Data from a store instruction was forwarded to a load on unit 1",
- .pme_event_ids = { 65, 65, -1, -1, 65, 65, -1, -1 },
- .pme_group_vector = {
- 0x0000004000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU1_SRQ_STFWD],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU1_SRQ_STFWD]
},
-#define POWER4_PME_PM_GRP_DISP 167
[ POWER4_PME_PM_GRP_DISP ] = {
.pme_name = "PM_GRP_DISP",
+ .pme_code = 0x2004,
.pme_short_desc = "Group dispatches",
.pme_long_desc = "A group was dispatched",
- .pme_event_ids = { -1, 85, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_GRP_DISP],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_GRP_DISP]
},
-#define POWER4_PME_PM_DATA_FROM_L2 168
[ POWER4_PME_PM_DATA_FROM_L2 ] = {
.pme_name = "PM_DATA_FROM_L2",
+ .pme_code = 0x4c66,
.pme_short_desc = "Data loaded from L2",
.pme_long_desc = "DL1 was reloaded from the local L2 due to a demand load",
- .pme_event_ids = { -1, -1, -1, 74, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0600000003000020ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_DATA_FROM_L2],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DATA_FROM_L2]
},
-#define POWER4_PME_PM_L2_PREF 169
[ POWER4_PME_PM_L2_PREF ] = {
.pme_name = "PM_L2_PREF",
+ .pme_code = 0xc34,
.pme_short_desc = "L2 cache prefetches",
.pme_long_desc = "A request to prefetch data into L2 was made",
- .pme_event_ids = { -1, -1, 43, 43, -1, -1, 43, 43 },
- .pme_group_vector = {
- 0x0000010000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2_PREF],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2_PREF]
},
-#define POWER4_PME_PM_FPU0_FPSCR 170
[ POWER4_PME_PM_FPU0_FPSCR ] = {
.pme_name = "PM_FPU0_FPSCR",
+ .pme_code = 0x130,
.pme_short_desc = "FPU0 executed FPSCR instruction",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing fpscr move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*. mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs",
- .pme_event_ids = { -1, -1, 24, 24, -1, -1, 24, 24 },
- .pme_group_vector = {
- 0x0000000100000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_FPSCR],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_FPSCR]
},
-#define POWER4_PME_PM_FPU1_DENORM 171
[ POWER4_PME_PM_FPU1_DENORM ] = {
.pme_name = "PM_FPU1_DENORM",
+ .pme_code = 0x124,
.pme_short_desc = "FPU1 received denormalized data",
.pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.",
- .pme_event_ids = { 18, 18, -1, -1, 18, 18, -1, -1 },
- .pme_group_vector = {
- 0x0000000040000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_DENORM],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_DENORM]
},
-#define POWER4_PME_PM_MRK_DATA_FROM_L25_MOD 172
[ POWER4_PME_PM_MRK_DATA_FROM_L25_MOD ] = {
.pme_name = "PM_MRK_DATA_FROM_L25_MOD",
+ .pme_code = 0x8c76,
.pme_short_desc = "Marked data loaded from L2.5 modified",
.pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a marked demand load",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 83 },
- .pme_group_vector = {
- 0x0000c00000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_DATA_FROM_L25_MOD],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_DATA_FROM_L25_MOD]
},
-#define POWER4_PME_PM_L2SB_ST_REQ 173
[ POWER4_PME_PM_L2SB_ST_REQ ] = {
.pme_name = "PM_L2SB_ST_REQ",
+ .pme_code = 0xf12,
.pme_short_desc = "L2 slice B store requests",
.pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C.",
- .pme_event_ids = { -1, -1, 40, 40, -1, -1, 40, 40 },
- .pme_group_vector = {
- 0x0000000000001000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SB_ST_REQ],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SB_ST_REQ]
},
-#define POWER4_PME_PM_L2SB_MOD_INV 174
[ POWER4_PME_PM_L2SB_MOD_INV ] = {
.pme_name = "PM_L2SB_MOD_INV",
+ .pme_code = 0xf23,
.pme_short_desc = "L2 slice B transition from modified to invalid",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.",
- .pme_event_ids = { 41, 41, -1, -1, 41, 41, -1, -1 },
- .pme_group_vector = {
- 0x0000000000001000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SB_MOD_INV],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SB_MOD_INV]
},
-#define POWER4_PME_PM_FPU0_FSQRT 175
[ POWER4_PME_PM_FPU0_FSQRT ] = {
.pme_name = "PM_FPU0_FSQRT",
+ .pme_code = 0x102,
.pme_short_desc = "FPU0 executed FSQRT instruction",
.pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp0 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 12, 12, -1, -1, 12, 12, -1, -1 },
- .pme_group_vector = {
- 0x0000000020000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_FSQRT],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_FSQRT]
},
-#define POWER4_PME_PM_LD_REF_L1 176
[ POWER4_PME_PM_LD_REF_L1 ] = {
.pme_name = "PM_LD_REF_L1",
+ .pme_code = 0x8c10,
.pme_short_desc = "L1 D cache load references",
.pme_long_desc = "Total DL1 Load references",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 82 },
- .pme_group_vector = {
- 0x4900000000000086ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LD_REF_L1],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LD_REF_L1]
},
-#define POWER4_PME_PM_MRK_L1_RELOAD_VALID 177
[ POWER4_PME_PM_MRK_L1_RELOAD_VALID ] = {
.pme_name = "PM_MRK_L1_RELOAD_VALID",
+ .pme_code = 0xc74,
.pme_short_desc = "Marked L1 reload data source valid",
.pme_long_desc = "The source information is valid and is for a marked load",
- .pme_event_ids = { -1, -1, 57, 57, -1, -1, 57, 57 },
- .pme_group_vector = {
- 0x0001800000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_L1_RELOAD_VALID],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_L1_RELOAD_VALID]
},
-#define POWER4_PME_PM_L2SB_SHR_MOD 178
[ POWER4_PME_PM_L2SB_SHR_MOD ] = {
.pme_name = "PM_L2SB_SHR_MOD",
+ .pme_code = 0xf20,
.pme_short_desc = "L2 slice B transition from shared to modified",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. ",
- .pme_event_ids = { 44, 44, -1, -1, 44, 44, -1, -1 },
- .pme_group_vector = {
- 0x0000000000001000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SB_SHR_MOD],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SB_SHR_MOD]
},
-#define POWER4_PME_PM_INST_FROM_L1 179
[ POWER4_PME_PM_INST_FROM_L1 ] = {
.pme_name = "PM_INST_FROM_L1",
+ .pme_code = 0x6327,
.pme_short_desc = "Instruction fetched from L1",
.pme_long_desc = "An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions",
- .pme_event_ids = { -1, -1, -1, -1, -1, 87, -1, -1 },
- .pme_group_vector = {
- 0x000000000c000040ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_INST_FROM_L1],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_INST_FROM_L1]
},
-#define POWER4_PME_PM_1PLUS_PPC_CMPL 180
[ POWER4_PME_PM_1PLUS_PPC_CMPL ] = {
.pme_name = "PM_1PLUS_PPC_CMPL",
+ .pme_code = 0x5003,
.pme_short_desc = "One or more PPC instruction completed",
.pme_long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.",
- .pme_event_ids = { -1, -1, -1, -1, 81, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000020000410001ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_1PLUS_PPC_CMPL],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_1PLUS_PPC_CMPL]
},
-#define POWER4_PME_PM_EE_OFF_EXT_INT 181
[ POWER4_PME_PM_EE_OFF_EXT_INT ] = {
.pme_name = "PM_EE_OFF_EXT_INT",
+ .pme_code = 0x237,
.pme_short_desc = "Cycles MSR(EE) bit off and external interrupt pending",
.pme_long_desc = "Cycles MSR(EE) bit off and external interrupt pending",
- .pme_event_ids = { -1, -1, 16, 16, -1, -1, 16, 16 },
- .pme_group_vector = {
- 0x0000000000200000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_EE_OFF_EXT_INT],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_EE_OFF_EXT_INT]
},
-#define POWER4_PME_PM_L2SC_SHR_MOD 182
[ POWER4_PME_PM_L2SC_SHR_MOD ] = {
.pme_name = "PM_L2SC_SHR_MOD",
+ .pme_code = 0xf24,
.pme_short_desc = "L2 slice C transition from shared to modified",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. ",
- .pme_event_ids = { 48, 48, -1, -1, 48, 48, -1, -1 },
- .pme_group_vector = {
- 0x0000000000002000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SC_SHR_MOD],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SC_SHR_MOD]
},
-#define POWER4_PME_PM_LSU_LRQ_FULL_CYC 183
[ POWER4_PME_PM_LSU_LRQ_FULL_CYC ] = {
.pme_name = "PM_LSU_LRQ_FULL_CYC",
+ .pme_code = 0x212,
.pme_short_desc = "Cycles LRQ full",
.pme_long_desc = "The isu sends this signal when the lrq is full.",
- .pme_event_ids = { -1, -1, 54, 54, -1, -1, 54, 54 },
- .pme_group_vector = {
- 0x0000000000080000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_LRQ_FULL_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_LRQ_FULL_CYC]
},
-#define POWER4_PME_PM_IC_PREF_INSTALL 184
[ POWER4_PME_PM_IC_PREF_INSTALL ] = {
.pme_name = "PM_IC_PREF_INSTALL",
+ .pme_code = 0x325,
.pme_short_desc = "Instruction prefetched installed in prefetch buffer",
.pme_long_desc = "This signal is asserted when a prefetch buffer entry (line) is allocated but the request is not a demand fetch.",
- .pme_event_ids = { 29, 29, -1, -1, 29, 29, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_IC_PREF_INSTALL],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_IC_PREF_INSTALL]
},
-#define POWER4_PME_PM_MRK_LSU1_FLUSH_SRQ 185
[ POWER4_PME_PM_MRK_LSU1_FLUSH_SRQ ] = {
.pme_name = "PM_MRK_LSU1_FLUSH_SRQ",
+ .pme_code = 0x917,
.pme_short_desc = "LSU1 marked SRQ flushes",
.pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { -1, -1, 64, 64, -1, -1, 64, 64 },
- .pme_group_vector = {
- 0x0004000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU1_FLUSH_SRQ],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU1_FLUSH_SRQ]
},
-#define POWER4_PME_PM_GCT_FULL_CYC 186
[ POWER4_PME_PM_GCT_FULL_CYC ] = {
.pme_name = "PM_GCT_FULL_CYC",
+ .pme_code = 0x200,
.pme_short_desc = "Cycles GCT full",
.pme_long_desc = "The ISU sends a signal indicating the gct is full. ",
- .pme_event_ids = { 26, 26, -1, -1, 26, 26, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000010ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_GCT_FULL_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_GCT_FULL_CYC]
},
-#define POWER4_PME_PM_INST_FROM_MEM 187
[ POWER4_PME_PM_INST_FROM_MEM ] = {
.pme_name = "PM_INST_FROM_MEM",
+ .pme_code = 0x1327,
.pme_short_desc = "Instruction fetched from memory",
.pme_long_desc = "An instruction fetch group was fetched from memory. Fetch Groups can contain up to 8 instructions",
- .pme_event_ids = { 87, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000008000040ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_INST_FROM_MEM],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_INST_FROM_MEM]
},
-#define POWER4_PME_PM_FXU_BUSY 188
[ POWER4_PME_PM_FXU_BUSY ] = {
.pme_name = "PM_FXU_BUSY",
+ .pme_code = 0x6002,
.pme_short_desc = "FXU busy",
.pme_long_desc = "FXU0 and FXU1 are both busy",
- .pme_event_ids = { -1, -1, -1, -1, -1, 85, -1, -1 },
- .pme_group_vector = {
- 0x0000000200000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FXU_BUSY],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FXU_BUSY]
},
-#define POWER4_PME_PM_ST_REF_L1_LSU1 189
[ POWER4_PME_PM_ST_REF_L1_LSU1 ] = {
.pme_name = "PM_ST_REF_L1_LSU1",
+ .pme_code = 0xc15,
.pme_short_desc = "LSU1 L1 D cache store references",
.pme_long_desc = "A store executed on unit 1",
- .pme_event_ids = { -1, -1, 72, 72, -1, -1, 72, 72 },
- .pme_group_vector = {
- 0x0000006000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_ST_REF_L1_LSU1],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_ST_REF_L1_LSU1]
},
-#define POWER4_PME_PM_MRK_LD_MISS_L1 190
[ POWER4_PME_PM_MRK_LD_MISS_L1 ] = {
.pme_name = "PM_MRK_LD_MISS_L1",
+ .pme_code = 0x1920,
.pme_short_desc = "Marked L1 D cache load misses",
.pme_long_desc = "Marked L1 D cache load misses",
- .pme_event_ids = { 92, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000240000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LD_MISS_L1],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LD_MISS_L1]
},
-#define POWER4_PME_PM_MRK_LSU1_INST_FIN 191
[ POWER4_PME_PM_MRK_LSU1_INST_FIN ] = {
.pme_name = "PM_MRK_LSU1_INST_FIN",
+ .pme_code = 0xc32,
.pme_short_desc = "LSU1 finished a marked instruction",
.pme_long_desc = "LSU unit 1 finished a marked instruction",
- .pme_event_ids = { -1, -1, 67, 67, -1, -1, 67, 67 },
- .pme_group_vector = {
- 0x0008000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU1_INST_FIN],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU1_INST_FIN]
},
-#define POWER4_PME_PM_L1_WRITE_CYC 192
[ POWER4_PME_PM_L1_WRITE_CYC ] = {
.pme_name = "PM_L1_WRITE_CYC",
+ .pme_code = 0x333,
.pme_short_desc = "Cycles writing to instruction L1",
.pme_long_desc = "This signal is asserted each cycle a cache write is active.",
- .pme_event_ids = { -1, -1, 36, 36, -1, -1, 36, 36 },
- .pme_group_vector = {
- 0x0080000000000008ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L1_WRITE_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L1_WRITE_CYC]
},
-#define POWER4_PME_PM_BIQ_IDU_FULL_CYC 193
[ POWER4_PME_PM_BIQ_IDU_FULL_CYC ] = {
.pme_name = "PM_BIQ_IDU_FULL_CYC",
+ .pme_code = 0x324,
.pme_short_desc = "Cycles BIQ or IDU full",
.pme_long_desc = "This signal will be asserted each time either the IDU is full or the BIQ is full.",
- .pme_event_ids = { 0, 0, -1, -1, 0, 0, -1, -1 },
- .pme_group_vector = {
- 0x0080000000000008ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_BIQ_IDU_FULL_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_BIQ_IDU_FULL_CYC]
},
-#define POWER4_PME_PM_MRK_LSU0_INST_FIN 194
[ POWER4_PME_PM_MRK_LSU0_INST_FIN ] = {
.pme_name = "PM_MRK_LSU0_INST_FIN",
+ .pme_code = 0xc31,
.pme_short_desc = "LSU0 finished a marked instruction",
.pme_long_desc = "LSU unit 0 finished a marked instruction",
- .pme_event_ids = { -1, -1, 62, 62, -1, -1, 62, 62 },
- .pme_group_vector = {
- 0x0008000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU0_INST_FIN],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU0_INST_FIN]
},
-#define POWER4_PME_PM_L2SC_ST_REQ 195
[ POWER4_PME_PM_L2SC_ST_REQ ] = {
.pme_name = "PM_L2SC_ST_REQ",
+ .pme_code = 0xf14,
.pme_short_desc = "L2 slice C store requests",
.pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C.",
- .pme_event_ids = { -1, -1, 42, 42, -1, -1, 42, 42 },
- .pme_group_vector = {
- 0x0000000000002000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SC_ST_REQ],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SC_ST_REQ]
},
-#define POWER4_PME_PM_LSU1_BUSY 196
[ POWER4_PME_PM_LSU1_BUSY ] = {
.pme_name = "PM_LSU1_BUSY",
+ .pme_code = 0xc37,
.pme_short_desc = "LSU1 busy",
.pme_long_desc = "LSU unit 1 is busy rejecting instructions ",
- .pme_event_ids = { -1, -1, 51, 51, -1, -1, 51, 51 },
- .pme_group_vector = {
- 0x0000000000800000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU1_BUSY],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU1_BUSY]
},
-#define POWER4_PME_PM_FPU_ALL 197
[ POWER4_PME_PM_FPU_ALL ] = {
.pme_name = "PM_FPU_ALL",
+ .pme_code = 0x5100,
.pme_short_desc = "FPU executed add",
.pme_long_desc = " mult",
- .pme_event_ids = { -1, -1, -1, -1, 84, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000008000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_ALL],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_ALL]
},
-#define POWER4_PME_PM_LSU_SRQ_S0_ALLOC 198
[ POWER4_PME_PM_LSU_SRQ_S0_ALLOC ] = {
.pme_name = "PM_LSU_SRQ_S0_ALLOC",
+ .pme_code = 0xc25,
.pme_short_desc = "SRQ slot 0 allocated",
.pme_long_desc = "SRQ Slot zero was allocated",
- .pme_event_ids = { 70, 70, -1, -1, 70, 70, -1, -1 },
- .pme_group_vector = {
- 0x0000000000800000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_SRQ_S0_ALLOC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_SRQ_S0_ALLOC]
},
-#define POWER4_PME_PM_GRP_MRK 199
[ POWER4_PME_PM_GRP_MRK ] = {
.pme_name = "PM_GRP_MRK",
+ .pme_code = 0x5004,
.pme_short_desc = "Group marked in IDU",
.pme_long_desc = "A group was sampled (marked)",
- .pme_event_ids = { -1, -1, -1, -1, 90, -1, -1, -1 },
- .pme_group_vector = {
- 0x00000c0000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_GRP_MRK],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_GRP_MRK]
},
-#define POWER4_PME_PM_FPU1_FIN 200
[ POWER4_PME_PM_FPU1_FIN ] = {
.pme_name = "PM_FPU1_FIN",
+ .pme_code = 0x117,
.pme_short_desc = "FPU1 produced a result",
.pme_long_desc = "fp1 finished, produced a result. This only indicates finish, not completion. ",
- .pme_event_ids = { -1, -1, 27, 27, -1, -1, 27, 27 },
- .pme_group_vector = {
- 0x1040000120000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_FIN],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_FIN]
},
-#define POWER4_PME_PM_DC_PREF_STREAM_ALLOC 201
[ POWER4_PME_PM_DC_PREF_STREAM_ALLOC ] = {
.pme_name = "PM_DC_PREF_STREAM_ALLOC",
+ .pme_code = 0x907,
.pme_short_desc = "D cache new prefetch stream allocated",
.pme_long_desc = "A new Prefetch Stream was allocated",
- .pme_event_ids = { 4, 4, -1, -1, 4, 4, -1, -1 },
- .pme_group_vector = {
- 0x0000010000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_DC_PREF_STREAM_ALLOC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DC_PREF_STREAM_ALLOC]
},
-#define POWER4_PME_PM_BR_MPRED_CR 202
[ POWER4_PME_PM_BR_MPRED_CR ] = {
.pme_name = "PM_BR_MPRED_CR",
+ .pme_code = 0x331,
.pme_short_desc = "Branch mispredictions due CR bit setting",
.pme_long_desc = "This signal is asserted when the branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This signal is asserted after a branch issue event and will result in a branch redirect flush if not overridden by a flush of an older instruction.",
- .pme_event_ids = { -1, -1, 9, 9, -1, -1, 9, 9 },
- .pme_group_vector = {
- 0x2080000000000008ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_BR_MPRED_CR],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_BR_MPRED_CR]
},
-#define POWER4_PME_PM_BR_MPRED_TA 203
[ POWER4_PME_PM_BR_MPRED_TA ] = {
.pme_name = "PM_BR_MPRED_TA",
+ .pme_code = 0x332,
.pme_short_desc = "Branch mispredictions due to target address",
.pme_long_desc = "branch miss predict due to a target address prediction. This signal will be asserted each time the branch execution unit detects an incorrect target address prediction. This signal will be asserted after a valid branch execution unit issue and will cause a branch mispredict flush unless a flush is detected from an older instruction.",
- .pme_event_ids = { -1, -1, 10, 10, -1, -1, 10, 10 },
- .pme_group_vector = {
- 0x2080000000000008ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_BR_MPRED_TA],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_BR_MPRED_TA]
},
-#define POWER4_PME_PM_CRQ_FULL_CYC 204
[ POWER4_PME_PM_CRQ_FULL_CYC ] = {
.pme_name = "PM_CRQ_FULL_CYC",
+ .pme_code = 0x211,
.pme_short_desc = "Cycles CR issue queue full",
.pme_long_desc = "The ISU sends a signal indicating that the issue queue that feeds the ifu cr unit cannot accept any more group (queue is full of groups).",
- .pme_event_ids = { -1, -1, 11, 11, -1, -1, 11, 11 },
- .pme_group_vector = {
- 0x0000000000040000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_CRQ_FULL_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_CRQ_FULL_CYC]
},
-#define POWER4_PME_PM_INST_FROM_PREF 205
[ POWER4_PME_PM_INST_FROM_PREF ] = {
.pme_name = "PM_INST_FROM_PREF",
+ .pme_code = 0x7327,
.pme_short_desc = "Instructions fetched from prefetch",
.pme_long_desc = "An instruction fetch group was fetched from the prefetch buffer. Fetch Groups can contain up to 8 instructions",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 79, -1 },
- .pme_group_vector = {
- 0x0000000004000040ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_INST_FROM_PREF],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_INST_FROM_PREF]
},
-#define POWER4_PME_PM_LD_MISS_L1 206
[ POWER4_PME_PM_LD_MISS_L1 ] = {
.pme_name = "PM_LD_MISS_L1",
+ .pme_code = 0x3c10,
.pme_short_desc = "L1 D cache load misses",
.pme_long_desc = "Total DL1 Load references that miss the DL1",
- .pme_event_ids = { -1, -1, 79, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x6900000000000006ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LD_MISS_L1],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LD_MISS_L1]
},
-#define POWER4_PME_PM_STCX_PASS 207
[ POWER4_PME_PM_STCX_PASS ] = {
.pme_name = "PM_STCX_PASS",
+ .pme_code = 0xc75,
.pme_short_desc = "Stcx passes",
.pme_long_desc = "A stcx (stwcx or stdcx) instruction was successful",
- .pme_event_ids = { -1, -1, 69, 69, -1, -1, 69, 69 },
- .pme_group_vector = {
- 0x0000000000400000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_STCX_PASS],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_STCX_PASS]
},
-#define POWER4_PME_PM_DC_INV_L2 208
[ POWER4_PME_PM_DC_INV_L2 ] = {
.pme_name = "PM_DC_INV_L2",
+ .pme_code = 0xc17,
.pme_short_desc = "L1 D cache entries invalidated from L2",
.pme_long_desc = "A dcache invalidated was received from the L2 because a line in L2 was castout.",
- .pme_event_ids = { -1, -1, 13, 13, -1, -1, 13, 13 },
- .pme_group_vector = {
- 0x0000002000000006ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_DC_INV_L2],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DC_INV_L2]
},
-#define POWER4_PME_PM_LSU_SRQ_FULL_CYC 209
[ POWER4_PME_PM_LSU_SRQ_FULL_CYC ] = {
.pme_name = "PM_LSU_SRQ_FULL_CYC",
+ .pme_code = 0x213,
.pme_short_desc = "Cycles SRQ full",
.pme_long_desc = "The isu sends this signal when the srq is full.",
- .pme_event_ids = { -1, -1, 55, 55, -1, -1, 55, 55 },
- .pme_group_vector = {
- 0x0000000000080000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_SRQ_FULL_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_SRQ_FULL_CYC]
},
-#define POWER4_PME_PM_LSU0_FLUSH_LRQ 210
[ POWER4_PME_PM_LSU0_FLUSH_LRQ ] = {
.pme_name = "PM_LSU0_FLUSH_LRQ",
+ .pme_code = 0xc02,
.pme_short_desc = "LSU0 LRQ flushes",
.pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { 55, 55, -1, -1, 55, 55, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU0_FLUSH_LRQ],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU0_FLUSH_LRQ]
},
-#define POWER4_PME_PM_LSU_SRQ_S0_VALID 211
[ POWER4_PME_PM_LSU_SRQ_S0_VALID ] = {
.pme_name = "PM_LSU_SRQ_S0_VALID",
+ .pme_code = 0xc21,
.pme_short_desc = "SRQ slot 0 valid",
.pme_long_desc = "This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.",
- .pme_event_ids = { 71, 71, -1, -1, 71, 71, -1, -1 },
- .pme_group_vector = {
- 0x0000000000800000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_SRQ_S0_VALID],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_SRQ_S0_VALID]
},
-#define POWER4_PME_PM_LARX_LSU0 212
[ POWER4_PME_PM_LARX_LSU0 ] = {
.pme_name = "PM_LARX_LSU0",
+ .pme_code = 0xc73,
.pme_short_desc = "Larx executed on LSU0",
.pme_long_desc = "A larx (lwarx or ldarx) was executed on side 0 (there is no coresponding unit 1 event since larx instructions can only execute on unit 0)",
- .pme_event_ids = { -1, -1, 44, 44, -1, -1, 44, 44 },
- .pme_group_vector = {
- 0x0000000000400000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LARX_LSU0],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LARX_LSU0]
},
-#define POWER4_PME_PM_GCT_EMPTY_CYC 213
[ POWER4_PME_PM_GCT_EMPTY_CYC ] = {
.pme_name = "PM_GCT_EMPTY_CYC",
+ .pme_code = 0x1004,
.pme_short_desc = "Cycles GCT empty",
.pme_long_desc = "The Global Completion Table is completely empty",
- .pme_event_ids = { 85, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000020000200000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_GCT_EMPTY_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_GCT_EMPTY_CYC]
},
-#define POWER4_PME_PM_FPU1_ALL 214
[ POWER4_PME_PM_FPU1_ALL ] = {
.pme_name = "PM_FPU1_ALL",
+ .pme_code = 0x107,
.pme_short_desc = "FPU1 executed add",
.pme_long_desc = " mult",
- .pme_event_ids = { 17, 17, -1, -1, 17, 17, -1, -1 },
- .pme_group_vector = {
- 0x0000000020000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_ALL],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_ALL]
},
-#define POWER4_PME_PM_FPU1_FSQRT 215
[ POWER4_PME_PM_FPU1_FSQRT ] = {
.pme_name = "PM_FPU1_FSQRT",
+ .pme_code = 0x106,
.pme_short_desc = "FPU1 executed FSQRT instruction",
.pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp1 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 21, 21, -1, -1, 21, 21, -1, -1 },
- .pme_group_vector = {
- 0x0000000020000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_FSQRT],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_FSQRT]
},
-#define POWER4_PME_PM_FPU_FIN 216
[ POWER4_PME_PM_FPU_FIN ] = {
.pme_name = "PM_FPU_FIN",
+ .pme_code = 0x4110,
.pme_short_desc = "FPU produced a result",
.pme_long_desc = "FPU finished, produced a result This only indicates finish, not completion. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, -1, 75, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0020000000004000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_FIN],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_FIN]
},
-#define POWER4_PME_PM_L2SA_SHR_MOD 217
[ POWER4_PME_PM_L2SA_SHR_MOD ] = {
.pme_name = "PM_L2SA_SHR_MOD",
+ .pme_code = 0xf04,
.pme_short_desc = "L2 slice A transition from shared to modified",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. ",
- .pme_event_ids = { 40, 40, -1, -1, 40, 40, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000800ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SA_SHR_MOD],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SA_SHR_MOD]
},
-#define POWER4_PME_PM_MRK_LD_MISS_L1_LSU1 218
[ POWER4_PME_PM_MRK_LD_MISS_L1_LSU1 ] = {
.pme_name = "PM_MRK_LD_MISS_L1_LSU1",
+ .pme_code = 0x924,
.pme_short_desc = "LSU1 L1 D cache load misses",
.pme_long_desc = "A marked load, executing on unit 1, missed the dcache",
- .pme_event_ids = { 74, 74, -1, -1, 74, 74, -1, -1 },
- .pme_group_vector = {
- 0x0004000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LD_MISS_L1_LSU1],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LD_MISS_L1_LSU1]
},
-#define POWER4_PME_PM_LSU_SRQ_STFWD 219
[ POWER4_PME_PM_LSU_SRQ_STFWD ] = {
.pme_name = "PM_LSU_SRQ_STFWD",
+ .pme_code = 0x1c20,
.pme_short_desc = "SRQ store forwarded",
.pme_long_desc = "Data from a store instruction was forwarded to a load",
- .pme_event_ids = { 89, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_SRQ_STFWD],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_SRQ_STFWD]
},
-#define POWER4_PME_PM_FXU0_FIN 220
[ POWER4_PME_PM_FXU0_FIN ] = {
.pme_name = "PM_FXU0_FIN",
+ .pme_code = 0x232,
.pme_short_desc = "FXU0 produced a result",
.pme_long_desc = "The Fixed Point unit 0 finished an instruction and produced a result",
- .pme_event_ids = { -1, -1, 31, 31, -1, -1, 31, 31 },
- .pme_group_vector = {
- 0x0000000000100000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FXU0_FIN],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FXU0_FIN]
},
-#define POWER4_PME_PM_MRK_FPU_FIN 221
[ POWER4_PME_PM_MRK_FPU_FIN ] = {
.pme_name = "PM_MRK_FPU_FIN",
+ .pme_code = 0x7004,
.pme_short_desc = "Marked instruction FPU processing finished",
.pme_long_desc = "One of the Floating Point Units finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 81, -1 },
- .pme_group_vector = {
- 0x0000080000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_FPU_FIN],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_FPU_FIN]
},
-#define POWER4_PME_PM_LSU_BUSY 222
[ POWER4_PME_PM_LSU_BUSY ] = {
.pme_name = "PM_LSU_BUSY",
+ .pme_code = 0x4c30,
.pme_short_desc = "LSU busy",
.pme_long_desc = "LSU (unit 0 + unit 1) is busy rejecting instructions ",
- .pme_event_ids = { -1, -1, -1, 80, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_BUSY],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_BUSY]
},
-#define POWER4_PME_PM_INST_FROM_L35 223
[ POWER4_PME_PM_INST_FROM_L35 ] = {
.pme_name = "PM_INST_FROM_L35",
+ .pme_code = 0x4327,
.pme_short_desc = "Instructions fetched from L3.5",
.pme_long_desc = "An instruction fetch group was fetched from the L3 of another module. Fetch Groups can contain up to 8 instructions",
- .pme_event_ids = { -1, -1, -1, 78, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x000000000c000040ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_INST_FROM_L35],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_INST_FROM_L35]
},
-#define POWER4_PME_PM_FPU1_FRSP_FCONV 224
[ POWER4_PME_PM_FPU1_FRSP_FCONV ] = {
.pme_name = "PM_FPU1_FRSP_FCONV",
+ .pme_code = 0x115,
.pme_short_desc = "FPU1 executed FRSP or FCONV instructions",
.pme_long_desc = "fThis signal is active for one cycle when fp1 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { -1, -1, 29, 29, -1, -1, 29, 29 },
- .pme_group_vector = {
- 0x0000000010000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_FRSP_FCONV],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_FRSP_FCONV]
},
-#define POWER4_PME_PM_SNOOP_TLBIE 225
[ POWER4_PME_PM_SNOOP_TLBIE ] = {
.pme_name = "PM_SNOOP_TLBIE",
+ .pme_code = 0x903,
.pme_short_desc = "Snoop TLBIE",
.pme_long_desc = "A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.",
- .pme_event_ids = { 77, 77, -1, -1, 77, 77, -1, -1 },
- .pme_group_vector = {
- 0x0000000000400000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_SNOOP_TLBIE],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_SNOOP_TLBIE]
},
-#define POWER4_PME_PM_FPU0_FDIV 226
[ POWER4_PME_PM_FPU0_FDIV ] = {
.pme_name = "PM_FPU0_FDIV",
+ .pme_code = 0x100,
.pme_short_desc = "FPU0 executed FDIV instruction",
.pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp0 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.",
- .pme_event_ids = { 10, 10, -1, -1, 10, 10, -1, -1 },
- .pme_group_vector = {
- 0x0000000010000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_FDIV],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_FDIV]
},
-#define POWER4_PME_PM_LD_REF_L1_LSU1 227
[ POWER4_PME_PM_LD_REF_L1_LSU1 ] = {
.pme_name = "PM_LD_REF_L1_LSU1",
+ .pme_code = 0xc14,
.pme_short_desc = "LSU1 L1 D cache load references",
.pme_long_desc = "A load executed on unit 1",
- .pme_event_ids = { -1, -1, 49, 49, -1, -1, 49, 49 },
- .pme_group_vector = {
- 0x0000001000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LD_REF_L1_LSU1],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LD_REF_L1_LSU1]
},
-#define POWER4_PME_PM_MRK_DATA_FROM_L275_MOD 228
[ POWER4_PME_PM_MRK_DATA_FROM_L275_MOD ] = {
.pme_name = "PM_MRK_DATA_FROM_L275_MOD",
+ .pme_code = 0x7c76,
.pme_short_desc = "Marked data loaded from L2.75 modified",
.pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of another MCM due to a marked demand load. ",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 80, -1 },
- .pme_group_vector = {
- 0x0001c00000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_DATA_FROM_L275_MOD],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_DATA_FROM_L275_MOD]
},
-#define POWER4_PME_PM_HV_CYC 229
[ POWER4_PME_PM_HV_CYC ] = {
.pme_name = "PM_HV_CYC",
+ .pme_code = 0x3004,
.pme_short_desc = "Hypervisor Cycles",
.pme_long_desc = "Cycles when the processor is executing in Hypervisor (MSR[HV] = 0 and MSR[PR]=0)",
- .pme_event_ids = { -1, -1, 84, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000020000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_HV_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_HV_CYC]
},
-#define POWER4_PME_PM_6INST_CLB_CYC 230
[ POWER4_PME_PM_6INST_CLB_CYC ] = {
.pme_name = "PM_6INST_CLB_CYC",
+ .pme_code = 0x455,
.pme_short_desc = "Cycles 6 instructions in CLB",
.pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.",
- .pme_event_ids = { -1, -1, 5, 5, -1, -1, 5, 5 },
- .pme_group_vector = {
- 0x0000000000020000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_6INST_CLB_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_6INST_CLB_CYC]
},
-#define POWER4_PME_PM_LR_CTR_MAP_FULL_CYC 231
[ POWER4_PME_PM_LR_CTR_MAP_FULL_CYC ] = {
.pme_name = "PM_LR_CTR_MAP_FULL_CYC",
+ .pme_code = 0x206,
.pme_short_desc = "Cycles LR/CTR mapper full",
.pme_long_desc = "The ISU sends a signal indicating that the lr/ctr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.",
- .pme_event_ids = { 53, 53, -1, -1, 53, 53, -1, -1 },
- .pme_group_vector = {
- 0x0000000000040000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LR_CTR_MAP_FULL_CYC],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LR_CTR_MAP_FULL_CYC]
},
-#define POWER4_PME_PM_L2SC_MOD_INV 232
[ POWER4_PME_PM_L2SC_MOD_INV ] = {
.pme_name = "PM_L2SC_MOD_INV",
+ .pme_code = 0xf27,
.pme_short_desc = "L2 slice C transition from modified to invalid",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.",
- .pme_event_ids = { 45, 45, -1, -1, 45, 45, -1, -1 },
- .pme_group_vector = {
- 0x0000000000002000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SC_MOD_INV],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SC_MOD_INV]
},
-#define POWER4_PME_PM_FPU_DENORM 233
[ POWER4_PME_PM_FPU_DENORM ] = {
.pme_name = "PM_FPU_DENORM",
+ .pme_code = 0x1120,
.pme_short_desc = "FPU received denormalized data",
.pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized. Combined Unit 0 + Unit 1",
- .pme_event_ids = { 83, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000008000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_DENORM],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_DENORM]
},
-#define POWER4_PME_PM_DATA_FROM_L275_MOD 234
[ POWER4_PME_PM_DATA_FROM_L275_MOD ] = {
.pme_name = "PM_DATA_FROM_L275_MOD",
+ .pme_code = 0x7c66,
.pme_short_desc = "Data loaded from L2.75 modified",
.pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of another MCM due to a demand load. ",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 74, -1 },
- .pme_group_vector = {
- 0x0200000003000020ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_DATA_FROM_L275_MOD],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DATA_FROM_L275_MOD]
},
-#define POWER4_PME_PM_LSU1_DERAT_MISS 235
[ POWER4_PME_PM_LSU1_DERAT_MISS ] = {
.pme_name = "PM_LSU1_DERAT_MISS",
+ .pme_code = 0x906,
.pme_short_desc = "LSU1 DERAT misses",
.pme_long_desc = "A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.",
- .pme_event_ids = { 60, 60, -1, -1, 60, 60, -1, -1 },
- .pme_group_vector = {
- 0x0000008000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU1_DERAT_MISS],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU1_DERAT_MISS]
},
-#define POWER4_PME_PM_IC_PREF_REQ 236
[ POWER4_PME_PM_IC_PREF_REQ ] = {
.pme_name = "PM_IC_PREF_REQ",
+ .pme_code = 0x326,
.pme_short_desc = "Instruction prefetch requests",
.pme_long_desc = "Asserted when a non-canceled prefetch is made to the cache interface unit (CIU).",
- .pme_event_ids = { 30, 30, -1, -1, 30, 30, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_IC_PREF_REQ],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_IC_PREF_REQ]
},
-#define POWER4_PME_PM_MRK_LSU_FIN 237
[ POWER4_PME_PM_MRK_LSU_FIN ] = {
.pme_name = "PM_MRK_LSU_FIN",
+ .pme_code = 0x8004,
.pme_short_desc = "Marked instruction LSU processing finished",
.pme_long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 84 },
- .pme_group_vector = {
- 0x0000080000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU_FIN],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU_FIN]
},
-#define POWER4_PME_PM_MRK_DATA_FROM_L3 238
[ POWER4_PME_PM_MRK_DATA_FROM_L3 ] = {
.pme_name = "PM_MRK_DATA_FROM_L3",
+ .pme_code = 0x1c76,
.pme_short_desc = "Marked data loaded from L3",
.pme_long_desc = "DL1 was reloaded from the local L3 due to a marked demand load",
- .pme_event_ids = { 90, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0001400000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_DATA_FROM_L3],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_DATA_FROM_L3]
},
-#define POWER4_PME_PM_MRK_DATA_FROM_MEM 239
[ POWER4_PME_PM_MRK_DATA_FROM_MEM ] = {
.pme_name = "PM_MRK_DATA_FROM_MEM",
+ .pme_code = 0x2c76,
.pme_short_desc = "Marked data loaded from memory",
.pme_long_desc = "DL1 was reloaded from memory due to a marked demand load",
- .pme_event_ids = { -1, 90, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0001400000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_DATA_FROM_MEM],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_DATA_FROM_MEM]
},
-#define POWER4_PME_PM_LSU0_FLUSH_UST 240
[ POWER4_PME_PM_LSU0_FLUSH_UST ] = {
.pme_name = "PM_LSU0_FLUSH_UST",
+ .pme_code = 0xc01,
.pme_short_desc = "LSU0 unaligned store flushes",
.pme_long_desc = "A store was flushed from unit 0 because it was unaligned (crossed a 4k boundary)",
- .pme_event_ids = { 58, 58, -1, -1, 58, 58, -1, -1 },
- .pme_group_vector = {
- 0x0000002000000000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU0_FLUSH_UST],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU0_FLUSH_UST]
},
-#define POWER4_PME_PM_LSU_FLUSH_LRQ 241
[ POWER4_PME_PM_LSU_FLUSH_LRQ ] = {
.pme_name = "PM_LSU_FLUSH_LRQ",
+ .pme_code = 0x6c00,
.pme_short_desc = "LRQ flushes",
.pme_long_desc = "A load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { -1, -1, -1, -1, -1, 89, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000080ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_FLUSH_LRQ],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_FLUSH_LRQ]
},
-#define POWER4_PME_PM_LSU_FLUSH_SRQ 242
[ POWER4_PME_PM_LSU_FLUSH_SRQ ] = {
.pme_name = "PM_LSU_FLUSH_SRQ",
+ .pme_code = 0x5c00,
.pme_short_desc = "SRQ flushes",
.pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { -1, -1, -1, -1, 92, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000080ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_FLUSH_SRQ],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_FLUSH_SRQ]
},
-#define POWER4_PME_PM_L2SC_MOD_TAG 243
[ POWER4_PME_PM_L2SC_MOD_TAG ] = {
.pme_name = "PM_L2SC_MOD_TAG",
+ .pme_code = 0xf26,
.pme_short_desc = "L2 slice C transition from modified to tagged",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.",
- .pme_event_ids = { 46, 46, -1, -1, 46, 46, -1, -1 },
- .pme_group_vector = {
- 0x0000000000002000ULL }
+ .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SC_MOD_TAG],
+ .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SC_MOD_TAG]
}
};
#define POWER4_PME_EVENT_COUNT 244
-static pmg_power4_group_t power4_groups[] = {
+static const int power4_group_event_ids[][POWER4_NUM_EVENT_COUNTERS] = {
+ [ 0 ] = { 94, 81, 83, 77, 81, 81, 77, 80 },
+ [ 1 ] = { 81, 81, 79, 13, 32, 86, 84, 82 },
+ [ 2 ] = { 86, 81, 79, 13, 32, 86, 84, 82 },
+ [ 3 ] = { 86, 0, 8, 9, 33, 81, 10, 36 },
+ [ 4 ] = { 7, 1, 33, 77, 86, 26, 73, 79 },
+ [ 5 ] = { 82, 82, 74, 74, 83, 82, 74, 75 },
+ [ 6 ] = { 87, 86, 78, 78, 91, 87, 79, 73 },
+ [ 7 ] = { 88, 87, 73, 77, 92, 89, 84, 82 },
+ [ 8 ] = { 35, 6, 12, 53, 31, 88, 78, 74 },
+ [ 9 ] = { 34, 5, 56, 52, 31, 88, 78, 74 },
+ [ 10 ] = { 50, 49, 17, 18, 52, 51, 78, 74 },
+ [ 11 ] = { 38, 39, 38, 37, 40, 37, 78, 74 },
+ [ 12 ] = { 42, 43, 40, 39, 44, 41, 78, 74 },
+ [ 13 ] = { 46, 47, 42, 41, 48, 45, 78, 74 },
+ [ 14 ] = { 84, 83, 75, 75, 82, 83, 78, 77 },
+ [ 15 ] = { 83, 84, 73, 77, 84, 84, 75, 78 },
+ [ 16 ] = { 86, 81, 0, 1, 81, 81, 2, 3 },
+ [ 17 ] = { 86, 81, 4, 5, 89, 81, 6, 7 },
+ [ 18 ] = { 80, 2, 11, 34, 53, 32, 78, 74 },
+ [ 19 ] = { 13, 22, 30, 30, 82, 86, 54, 55 },
+ [ 20 ] = { 32, 81, 31, 32, 28, 27, 78, 74 },
+ [ 21 ] = { 85, 92, 83, 16, 82, 86, 15, 76 },
+ [ 22 ] = { 77, 78, 69, 73, 81, 86, 44, 45 },
+ [ 23 ] = { 71, 70, 50, 51, 69, 68, 78, 74 },
+ [ 24 ] = { 86, 36, 73, 74, 83, 82, 74, 75 },
+ [ 25 ] = { 82, 82, 74, 74, 36, 81, 74, 81 },
+ [ 26 ] = { 86, 81, 78, 78, 91, 87, 79, 73 },
+ [ 27 ] = { 87, 86, 78, 78, 91, 87, 73, 81 },
+ [ 28 ] = { 10, 19, 25, 29, 11, 20, 78, 74 },
+ [ 29 ] = { 12, 21, 22, 27, 8, 17, 78, 74 },
+ [ 30 ] = { 9, 18, 23, 28, 82, 86, 21, 26 },
+ [ 31 ] = { 14, 23, 19, 20, 16, 25, 73, 81 },
+ [ 32 ] = { 15, 24, 22, 27, 82, 86, 73, 24 },
+ [ 33 ] = { 86, 81, 76, 76, 88, 85, 76, 79 },
+ [ 34 ] = { 67, 66, 52, 53, 82, 86, 56, 12 },
+ [ 35 ] = { 55, 61, 73, 73, 56, 62, 78, 74 },
+ [ 36 ] = { 57, 63, 48, 49, 82, 86, 46, 47 },
+ [ 37 ] = { 58, 64, 71, 72, 82, 86, 70, 13 },
+ [ 38 ] = { 59, 65, 71, 72, 79, 81, 78, 74 },
+ [ 39 ] = { 54, 60, 73, 73, 36, 81, 78, 74 },
+ [ 40 ] = { 4, 3, 43, 35, 82, 86, 73, 14 },
+ [ 41 ] = { 85, 88, 84, 73, 81, 86, 77, 86 },
+ [ 42 ] = { 92, 91, 73, 84, 90, 92, 82, 81 },
+ [ 43 ] = { 91, 89, 73, 82, 90, 91, 81, 84 },
+ [ 44 ] = { 93, 81, 82, 84, 94, 93, 68, 81 },
+ [ 45 ] = { 92, 81, 81, 85, 94, 92, 78, 85 },
+ [ 46 ] = { 90, 90, 80, 83, 93, 90, 80, 83 },
+ [ 47 ] = { 86, 81, 57, 83, 93, 90, 80, 83 },
+ [ 48 ] = { 90, 90, 80, 83, 82, 86, 80, 57 },
+ [ 49 ] = { 76, 72, 60, 65, 82, 86, 61, 66 },
+ [ 50 ] = { 73, 74, 58, 63, 82, 86, 59, 64 },
+ [ 51 ] = { 75, 81, 62, 67, 82, 92, 82, 81 },
+ [ 52 ] = { 67, 91, 53, 77, 82, 92, 77, 52 },
+ [ 53 ] = { 84, 83, 77, 75, 82, 83, 78, 77 },
+ [ 54 ] = { 81, 84, 22, 77, 86, 84, 27, 78 },
+ [ 55 ] = { 86, 0, 8, 9, 1, 81, 10, 36 },
+ [ 56 ] = { 6, 35, 79, 70, 82, 86, 84, 82 },
+ [ 57 ] = { 86, 81, 74, 74, 83, 82, 74, 75 },
+ [ 58 ] = { 82, 82, 74, 74, 83, 81, 78, 75 },
+ [ 59 ] = { 6, 88, 79, 70, 82, 86, 84, 82 },
+ [ 60 ] = { 84, 83, 22, 27, 82, 84, 78, 78 },
+ [ 61 ] = { 86, 81, 79, 8, 79, 81, 9, 10 },
+ [ 62 ] = { 86, 81, 79, 8, 82, 79, 84, 82 }
+};
+
+static const pmg_power_group_t power4_groups[] = {
[ 0 ] = {
.pmg_name = "pm_slice0",
.pmg_desc = "Time Slice 0",
- .pmg_event_ids = { 94, 81, 83, 77, 81, 81, 77, 80 },
+ .pmg_event_ids = power4_group_event_ids[0],
.pmg_mmcr0 = 0x0000000000000d0eULL,
.pmg_mmcr1 = 0x000000004a5675acULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2232,7 +3282,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 1 ] = {
.pmg_name = "pm_eprof",
.pmg_desc = "Group for use with eprof",
- .pmg_event_ids = { 81, 81, 79, 13, 32, 86, 84, 82 },
+ .pmg_event_ids = power4_group_event_ids[1],
.pmg_mmcr0 = 0x000000000000070eULL,
.pmg_mmcr1 = 0x1003400045f29420ULL,
.pmg_mmcra = 0x0000000000002001ULL
@@ -2240,7 +3290,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 2 ] = {
.pmg_name = "pm_basic",
.pmg_desc = "Basic performance indicators",
- .pmg_event_ids = { 86, 81, 79, 13, 32, 86, 84, 82 },
+ .pmg_event_ids = power4_group_event_ids[2],
.pmg_mmcr0 = 0x000000000000090eULL,
.pmg_mmcr1 = 0x1003400045f29420ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2248,7 +3298,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 3 ] = {
.pmg_name = "pm_ifu",
.pmg_desc = "IFU events",
- .pmg_event_ids = { 86, 0, 8, 9, 33, 81, 10, 36 },
+ .pmg_event_ids = power4_group_event_ids[3],
.pmg_mmcr0 = 0x0000000000000938ULL,
.pmg_mmcr1 = 0x80000000c6767d6cULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2256,7 +3306,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 4 ] = {
.pmg_name = "pm_isu",
.pmg_desc = "ISU Queue full events",
- .pmg_event_ids = { 7, 1, 33, 77, 86, 26, 73, 79 },
+ .pmg_event_ids = power4_group_event_ids[4],
.pmg_mmcr0 = 0x000000000000112aULL,
.pmg_mmcr1 = 0x50041000ea5103a0ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2264,7 +3314,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 5 ] = {
.pmg_name = "pm_lsource",
.pmg_desc = "Information on data source",
- .pmg_event_ids = { 82, 82, 74, 74, 83, 82, 74, 75 },
+ .pmg_event_ids = power4_group_event_ids[5],
.pmg_mmcr0 = 0x0000000000000e1cULL,
.pmg_mmcr1 = 0x0010c000739ce738ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2272,7 +3322,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 6 ] = {
.pmg_name = "pm_isource",
.pmg_desc = "Instruction Source information",
- .pmg_event_ids = { 87, 86, 78, 78, 91, 87, 79, 73 },
+ .pmg_event_ids = power4_group_event_ids[6],
.pmg_mmcr0 = 0x0000000000000f1eULL,
.pmg_mmcr1 = 0x800000007bdef7bcULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2280,7 +3330,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 7 ] = {
.pmg_name = "pm_lsu",
.pmg_desc = "Information on the Load Store Unit",
- .pmg_event_ids = { 88, 87, 73, 77, 92, 89, 84, 82 },
+ .pmg_event_ids = power4_group_event_ids[7],
.pmg_mmcr0 = 0x0000000000000810ULL,
.pmg_mmcr1 = 0x000f00003a508420ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2288,7 +3338,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 8 ] = {
.pmg_name = "pm_xlate1",
.pmg_desc = "Translation Events",
- .pmg_event_ids = { 35, 6, 12, 53, 31, 88, 78, 74 },
+ .pmg_event_ids = power4_group_event_ids[8],
.pmg_mmcr0 = 0x0000000000001028ULL,
.pmg_mmcr1 = 0x81082000f67e849cULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2296,7 +3346,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 9 ] = {
.pmg_name = "pm_xlate2",
.pmg_desc = "Translation Events",
- .pmg_event_ids = { 34, 5, 56, 52, 31, 88, 78, 74 },
+ .pmg_event_ids = power4_group_event_ids[9],
.pmg_mmcr0 = 0x000000000000112aULL,
.pmg_mmcr1 = 0x81082000d77e849cULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2304,7 +3354,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 10 ] = {
.pmg_name = "pm_gps1",
.pmg_desc = "L3 Events",
- .pmg_event_ids = { 50, 49, 17, 18, 52, 51, 78, 74 },
+ .pmg_event_ids = power4_group_event_ids[10],
.pmg_mmcr0 = 0x0000000000001022ULL,
.pmg_mmcr1 = 0x00000c00b5e5349cULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2312,7 +3362,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 11 ] = {
.pmg_name = "pm_l2a",
.pmg_desc = "L2 SliceA events",
- .pmg_event_ids = { 38, 39, 38, 37, 40, 37, 78, 74 },
+ .pmg_event_ids = power4_group_event_ids[11],
.pmg_mmcr0 = 0x000000000000162aULL,
.pmg_mmcr1 = 0x00000c008469749cULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2320,7 +3370,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 12 ] = {
.pmg_name = "pm_l2b",
.pmg_desc = "L2 SliceB events",
- .pmg_event_ids = { 42, 43, 40, 39, 44, 41, 78, 74 },
+ .pmg_event_ids = power4_group_event_ids[12],
.pmg_mmcr0 = 0x0000000000001a32ULL,
.pmg_mmcr1 = 0x0000060094f1b49cULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2328,7 +3378,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 13 ] = {
.pmg_name = "pm_l2c",
.pmg_desc = "L2 SliceC events",
- .pmg_event_ids = { 46, 47, 42, 41, 48, 45, 78, 74 },
+ .pmg_event_ids = power4_group_event_ids[13],
.pmg_mmcr0 = 0x0000000000001e3aULL,
.pmg_mmcr1 = 0x00000600a579f49cULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2336,7 +3386,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 14 ] = {
.pmg_name = "pm_fpu1",
.pmg_desc = "Floating Point events",
- .pmg_event_ids = { 84, 83, 75, 75, 82, 83, 78, 77 },
+ .pmg_event_ids = power4_group_event_ids[14],
.pmg_mmcr0 = 0x0000000000000810ULL,
.pmg_mmcr1 = 0x00000000420e84a0ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2344,7 +3394,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 15 ] = {
.pmg_name = "pm_fpu2",
.pmg_desc = "Floating Point events",
- .pmg_event_ids = { 83, 84, 73, 77, 84, 84, 75, 78 },
+ .pmg_event_ids = power4_group_event_ids[15],
.pmg_mmcr0 = 0x0000000000000810ULL,
.pmg_mmcr1 = 0x010020e83a508420ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2352,7 +3402,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 16 ] = {
.pmg_name = "pm_idu1",
.pmg_desc = "Instruction Decode Unit events",
- .pmg_event_ids = { 86, 81, 0, 1, 81, 81, 2, 3 },
+ .pmg_event_ids = power4_group_event_ids[16],
.pmg_mmcr0 = 0x000000000000090eULL,
.pmg_mmcr1 = 0x040100008456794cULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2360,7 +3410,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 17 ] = {
.pmg_name = "pm_idu2",
.pmg_desc = "Instruction Decode Unit events",
- .pmg_event_ids = { 86, 81, 4, 5, 89, 81, 6, 7 },
+ .pmg_event_ids = power4_group_event_ids[17],
.pmg_mmcr0 = 0x000000000000090eULL,
.pmg_mmcr1 = 0x04010000a5527b5cULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2368,7 +3418,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 18 ] = {
.pmg_name = "pm_isu_rename",
.pmg_desc = "ISU Rename Pool Events",
- .pmg_event_ids = { 80, 2, 11, 34, 53, 32, 78, 74 },
+ .pmg_event_ids = power4_group_event_ids[18],
.pmg_mmcr0 = 0x0000000000001228ULL,
.pmg_mmcr1 = 0x100550008e6d949cULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2376,7 +3426,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 19 ] = {
.pmg_name = "pm_isu_queues1",
.pmg_desc = "ISU Queue Full Events",
- .pmg_event_ids = { 13, 22, 30, 30, 82, 86, 54, 55 },
+ .pmg_event_ids = power4_group_event_ids[19],
.pmg_mmcr0 = 0x000000000000132eULL,
.pmg_mmcr1 = 0x10050000850e994cULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2384,7 +3434,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 20 ] = {
.pmg_name = "pm_isu_flow",
.pmg_desc = "ISU Instruction Flow Events",
- .pmg_event_ids = { 32, 81, 31, 32, 28, 27, 78, 74 },
+ .pmg_event_ids = power4_group_event_ids[20],
.pmg_mmcr0 = 0x000000000000190eULL,
.pmg_mmcr1 = 0x10005000d7b7c49cULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2392,7 +3442,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 21 ] = {
.pmg_name = "pm_isu_work",
.pmg_desc = "ISU Indicators of Work Blockage",
- .pmg_event_ids = { 85, 92, 83, 16, 82, 86, 15, 76 },
+ .pmg_event_ids = power4_group_event_ids[21],
.pmg_mmcr0 = 0x0000000000000c12ULL,
.pmg_mmcr1 = 0x100010004fce9da8ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2400,7 +3450,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 22 ] = {
.pmg_name = "pm_serialize",
.pmg_desc = "LSU Serializing Events",
- .pmg_event_ids = { 77, 78, 69, 73, 81, 86, 44, 45 },
+ .pmg_event_ids = power4_group_event_ids[22],
.pmg_mmcr0 = 0x0000000000001332ULL,
.pmg_mmcr1 = 0x0118b000e9d69dfcULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2408,7 +3458,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 23 ] = {
.pmg_name = "pm_lsubusy",
.pmg_desc = "LSU Busy Events",
- .pmg_event_ids = { 71, 70, 50, 51, 69, 68, 78, 74 },
+ .pmg_event_ids = power4_group_event_ids[23],
.pmg_mmcr0 = 0x000000000000193aULL,
.pmg_mmcr1 = 0x0000f000dff5e49cULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2416,7 +3466,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 24 ] = {
.pmg_name = "pm_lsource2",
.pmg_desc = "Information on data source",
- .pmg_event_ids = { 86, 36, 73, 74, 83, 82, 74, 75 },
+ .pmg_event_ids = power4_group_event_ids[24],
.pmg_mmcr0 = 0x0000000000000938ULL,
.pmg_mmcr1 = 0x0010c0003b9ce738ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2424,7 +3474,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 25 ] = {
.pmg_name = "pm_lsource3",
.pmg_desc = "Information on data source",
- .pmg_event_ids = { 82, 82, 74, 74, 36, 81, 74, 81 },
+ .pmg_event_ids = power4_group_event_ids[25],
.pmg_mmcr0 = 0x0000000000000e1cULL,
.pmg_mmcr1 = 0x0010c00073b87724ULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2432,7 +3482,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 26 ] = {
.pmg_name = "pm_isource2",
.pmg_desc = "Instruction Source information",
- .pmg_event_ids = { 86, 81, 78, 78, 91, 87, 79, 73 },
+ .pmg_event_ids = power4_group_event_ids[26],
.pmg_mmcr0 = 0x000000000000090eULL,
.pmg_mmcr1 = 0x800000007bdef7bcULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2440,7 +3490,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 27 ] = {
.pmg_name = "pm_isource3",
.pmg_desc = "Instruction Source information",
- .pmg_event_ids = { 87, 86, 78, 78, 91, 87, 73, 81 },
+ .pmg_event_ids = power4_group_event_ids[27],
.pmg_mmcr0 = 0x0000000000000f1eULL,
.pmg_mmcr1 = 0x800000007bdef3a4ULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2448,7 +3498,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 28 ] = {
.pmg_name = "pm_fpu3",
.pmg_desc = "Floating Point events by unit",
- .pmg_event_ids = { 10, 19, 25, 29, 11, 20, 78, 74 },
+ .pmg_event_ids = power4_group_event_ids[28],
.pmg_mmcr0 = 0x0000000000001028ULL,
.pmg_mmcr1 = 0x000000008d63549cULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2456,7 +3506,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 29 ] = {
.pmg_name = "pm_fpu4",
.pmg_desc = "Floating Point events by unit",
- .pmg_event_ids = { 12, 21, 22, 27, 8, 17, 78, 74 },
+ .pmg_event_ids = power4_group_event_ids[29],
.pmg_mmcr0 = 0x000000000000122cULL,
.pmg_mmcr1 = 0x000000009de7749cULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2464,7 +3514,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 30 ] = {
.pmg_name = "pm_fpu5",
.pmg_desc = "Floating Point events by unit",
- .pmg_event_ids = { 9, 18, 23, 28, 82, 86, 21, 26 },
+ .pmg_event_ids = power4_group_event_ids[30],
.pmg_mmcr0 = 0x0000000000001838ULL,
.pmg_mmcr1 = 0x00000000850e9958ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2472,7 +3522,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 31 ] = {
.pmg_name = "pm_fpu6",
.pmg_desc = "Floating Point events by unit",
- .pmg_event_ids = { 14, 23, 19, 20, 16, 25, 73, 81 },
+ .pmg_event_ids = power4_group_event_ids[31],
.pmg_mmcr0 = 0x0000000000001b3eULL,
.pmg_mmcr1 = 0x01002000c735e3a4ULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2480,7 +3530,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 32 ] = {
.pmg_name = "pm_fpu7",
.pmg_desc = "Floating Point events by unit",
- .pmg_event_ids = { 15, 24, 22, 27, 82, 86, 73, 24 },
+ .pmg_event_ids = power4_group_event_ids[32],
.pmg_mmcr0 = 0x000000000000193aULL,
.pmg_mmcr1 = 0x000000009dce93e0ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2488,7 +3538,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 33 ] = {
.pmg_name = "pm_fxu",
.pmg_desc = "Fix Point Unit events",
- .pmg_event_ids = { 86, 81, 76, 76, 88, 85, 76, 79 },
+ .pmg_event_ids = power4_group_event_ids[33],
.pmg_mmcr0 = 0x000000000000090eULL,
.pmg_mmcr1 = 0x400000024294a520ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2496,7 +3546,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 34 ] = {
.pmg_name = "pm_lsu_lmq",
.pmg_desc = "LSU Load Miss Queue Events",
- .pmg_event_ids = { 67, 66, 52, 53, 82, 86, 56, 12 },
+ .pmg_event_ids = power4_group_event_ids[34],
.pmg_mmcr0 = 0x0000000000001e3eULL,
.pmg_mmcr1 = 0x0100a000ee4e9d78ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2504,7 +3554,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 35 ] = {
.pmg_name = "pm_lsu_flush",
.pmg_desc = "LSU Flush Events",
- .pmg_event_ids = { 55, 61, 73, 73, 56, 62, 78, 74 },
+ .pmg_event_ids = power4_group_event_ids[35],
.pmg_mmcr0 = 0x000000000000122cULL,
.pmg_mmcr1 = 0x000c000039e7749cULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2512,7 +3562,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 36 ] = {
.pmg_name = "pm_lsu_load1",
.pmg_desc = "LSU Load Events",
- .pmg_event_ids = { 57, 63, 48, 49, 82, 86, 46, 47 },
+ .pmg_event_ids = power4_group_event_ids[36],
.pmg_mmcr0 = 0x0000000000001028ULL,
.pmg_mmcr1 = 0x000f0000850e9958ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2520,7 +3570,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 37 ] = {
.pmg_name = "pm_lsu_store1",
.pmg_desc = "LSU Store Events",
- .pmg_event_ids = { 58, 64, 71, 72, 82, 86, 70, 13 },
+ .pmg_event_ids = power4_group_event_ids[37],
.pmg_mmcr0 = 0x000000000000112aULL,
.pmg_mmcr1 = 0x000f00008d4e99dcULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2528,7 +3578,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 38 ] = {
.pmg_name = "pm_lsu_store2",
.pmg_desc = "LSU Store Events",
- .pmg_event_ids = { 59, 65, 71, 72, 79, 81, 78, 74 },
+ .pmg_event_ids = power4_group_event_ids[38],
.pmg_mmcr0 = 0x0000000000001838ULL,
.pmg_mmcr1 = 0x0003c0008d76749cULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2536,7 +3586,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 39 ] = {
.pmg_name = "pm_lsu7",
.pmg_desc = "Information on the Load Store Unit",
- .pmg_event_ids = { 54, 60, 73, 73, 36, 81, 78, 74 },
+ .pmg_event_ids = power4_group_event_ids[39],
.pmg_mmcr0 = 0x000000000000122cULL,
.pmg_mmcr1 = 0x0118c00039f8749cULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2544,7 +3594,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 40 ] = {
.pmg_name = "pm_dpfetch",
.pmg_desc = "Data Prefetch Events",
- .pmg_event_ids = { 4, 3, 43, 35, 82, 86, 73, 14 },
+ .pmg_event_ids = power4_group_event_ids[40],
.pmg_mmcr0 = 0x000000000000173eULL,
.pmg_mmcr1 = 0x0108f000e74e93f8ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2552,7 +3602,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 41 ] = {
.pmg_name = "pm_misc",
.pmg_desc = "Misc Events for testing",
- .pmg_event_ids = { 85, 88, 84, 73, 81, 86, 77, 86 },
+ .pmg_event_ids = power4_group_event_ids[41],
.pmg_mmcr0 = 0x0000000000000c14ULL,
.pmg_mmcr1 = 0x0000000061d695b4ULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2560,7 +3610,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 42 ] = {
.pmg_name = "pm_mark1",
.pmg_desc = "Information on marked instructions",
- .pmg_event_ids = { 92, 91, 73, 84, 90, 92, 82, 81 },
+ .pmg_event_ids = power4_group_event_ids[42],
.pmg_mmcr0 = 0x0000000000000816ULL,
.pmg_mmcr1 = 0x010080803b18d6a4ULL,
.pmg_mmcra = 0x0000000000722001ULL
@@ -2568,7 +3618,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 43 ] = {
.pmg_name = "pm_mark2",
.pmg_desc = "Marked Instructions Processing Flow",
- .pmg_event_ids = { 91, 89, 73, 82, 90, 91, 81, 84 },
+ .pmg_event_ids = power4_group_event_ids[43],
.pmg_mmcr0 = 0x0000000000000a1aULL,
.pmg_mmcr1 = 0x000000003b58c630ULL,
.pmg_mmcra = 0x0000000000002001ULL
@@ -2576,7 +3626,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 44 ] = {
.pmg_name = "pm_mark3",
.pmg_desc = "Marked Stores Processing Flow",
- .pmg_event_ids = { 93, 81, 82, 84, 94, 93, 68, 81 },
+ .pmg_event_ids = power4_group_event_ids[44],
.pmg_mmcr0 = 0x0000000000000b0eULL,
.pmg_mmcr1 = 0x010020005b1abda4ULL,
.pmg_mmcra = 0x0000000000022001ULL
@@ -2584,7 +3634,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 45 ] = {
.pmg_name = "pm_mark4",
.pmg_desc = "Marked Loads Processing FLow",
- .pmg_event_ids = { 92, 81, 81, 85, 94, 92, 78, 85 },
+ .pmg_event_ids = power4_group_event_ids[45],
.pmg_mmcr0 = 0x000000000000080eULL,
.pmg_mmcr1 = 0x01028080421ad4a0ULL,
.pmg_mmcra = 0x0000000000002001ULL
@@ -2592,7 +3642,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 46 ] = {
.pmg_name = "pm_mark_lsource",
.pmg_desc = "Information on marked data source",
- .pmg_event_ids = { 90, 90, 80, 83, 93, 90, 80, 83 },
+ .pmg_event_ids = power4_group_event_ids[46],
.pmg_mmcr0 = 0x0000000000000e1cULL,
.pmg_mmcr1 = 0x00103000739ce738ULL,
.pmg_mmcra = 0x0000000000002001ULL
@@ -2600,7 +3650,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 47 ] = {
.pmg_name = "pm_mark_lsource2",
.pmg_desc = "Information on marked data source",
- .pmg_event_ids = { 86, 81, 57, 83, 93, 90, 80, 83 },
+ .pmg_event_ids = power4_group_event_ids[47],
.pmg_mmcr0 = 0x000000000000090eULL,
.pmg_mmcr1 = 0x00103000e39ce738ULL,
.pmg_mmcra = 0x0000000000002001ULL
@@ -2608,7 +3658,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 48 ] = {
.pmg_name = "pm_mark_lsource3",
.pmg_desc = "Information on marked data source",
- .pmg_event_ids = { 90, 90, 80, 83, 82, 86, 80, 57 },
+ .pmg_event_ids = power4_group_event_ids[48],
.pmg_mmcr0 = 0x0000000000000e1cULL,
.pmg_mmcr1 = 0x00103000738e9770ULL,
.pmg_mmcra = 0x0000000000002001ULL
@@ -2616,7 +3666,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 49 ] = {
.pmg_name = "pm_lsu_mark1",
.pmg_desc = "Load Store Unit Marked Events",
- .pmg_event_ids = { 76, 72, 60, 65, 82, 86, 61, 66 },
+ .pmg_event_ids = power4_group_event_ids[49],
.pmg_mmcr0 = 0x0000000000001b34ULL,
.pmg_mmcr1 = 0x01028000850e98d4ULL,
.pmg_mmcra = 0x0000000000022001ULL
@@ -2624,7 +3674,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 50 ] = {
.pmg_name = "pm_lsu_mark2",
.pmg_desc = "Load Store Unit Marked Events",
- .pmg_event_ids = { 73, 74, 58, 63, 82, 86, 59, 64 },
+ .pmg_event_ids = power4_group_event_ids[50],
.pmg_mmcr0 = 0x0000000000001838ULL,
.pmg_mmcr1 = 0x01028000958e99dcULL,
.pmg_mmcra = 0x0000000000022001ULL
@@ -2632,7 +3682,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 51 ] = {
.pmg_name = "pm_lsu_mark3",
.pmg_desc = "Load Store Unit Marked Events",
- .pmg_event_ids = { 75, 81, 62, 67, 82, 92, 82, 81 },
+ .pmg_event_ids = power4_group_event_ids[51],
.pmg_mmcr0 = 0x0000000000001d0eULL,
.pmg_mmcr1 = 0x0100b000ce8ed6a4ULL,
.pmg_mmcra = 0x0000000000022001ULL
@@ -2640,7 +3690,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 52 ] = {
.pmg_name = "pm_threshold",
.pmg_desc = "Group for pipeline threshold studies",
- .pmg_event_ids = { 67, 91, 53, 77, 82, 92, 77, 52 },
+ .pmg_event_ids = power4_group_event_ids[52],
.pmg_mmcr0 = 0x0000000000001e16ULL,
.pmg_mmcr1 = 0x0100a000ca4ed5f4ULL,
.pmg_mmcra = 0x0000000000722001ULL
@@ -2648,7 +3698,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 53 ] = {
.pmg_name = "pm_pe_bench1",
.pmg_desc = "PE Benchmarker group for FP analysis",
- .pmg_event_ids = { 84, 83, 77, 75, 82, 83, 78, 77 },
+ .pmg_event_ids = power4_group_event_ids[53],
.pmg_mmcr0 = 0x0000000000000810ULL,
.pmg_mmcr1 = 0x10001002420e84a0ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2656,7 +3706,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 54 ] = {
.pmg_name = "pm_pe_bench2",
.pmg_desc = "PE Benchmarker group for FP stalls analysis",
- .pmg_event_ids = { 81, 84, 22, 77, 86, 84, 27, 78 },
+ .pmg_event_ids = power4_group_event_ids[54],
.pmg_mmcr0 = 0x0000000000000710ULL,
.pmg_mmcr1 = 0x110420689a508ba0ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2664,7 +3714,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 55 ] = {
.pmg_name = "pm_pe_bench3",
.pmg_desc = "PE Benchmarker group for branch analysis",
- .pmg_event_ids = { 86, 0, 8, 9, 1, 81, 10, 36 },
+ .pmg_event_ids = power4_group_event_ids[55],
.pmg_mmcr0 = 0x0000000000000938ULL,
.pmg_mmcr1 = 0x90040000c66a7d6cULL,
.pmg_mmcra = 0x0000000000022000ULL
@@ -2672,7 +3722,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 56 ] = {
.pmg_name = "pm_pe_bench4",
.pmg_desc = "PE Benchmarker group for L1 and TLB analysis",
- .pmg_event_ids = { 6, 35, 79, 70, 82, 86, 84, 82 },
+ .pmg_event_ids = power4_group_event_ids[56],
.pmg_mmcr0 = 0x0000000000001420ULL,
.pmg_mmcr1 = 0x010b000044ce9420ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2680,7 +3730,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 57 ] = {
.pmg_name = "pm_pe_bench5",
.pmg_desc = "PE Benchmarker group for L2 analysis",
- .pmg_event_ids = { 86, 81, 74, 74, 83, 82, 74, 75 },
+ .pmg_event_ids = power4_group_event_ids[57],
.pmg_mmcr0 = 0x000000000000090eULL,
.pmg_mmcr1 = 0x0010c000739ce738ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2688,7 +3738,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 58 ] = {
.pmg_name = "pm_pe_bench6",
.pmg_desc = "PE Benchmarker group for L3 analysis",
- .pmg_event_ids = { 82, 82, 74, 74, 83, 81, 78, 75 },
+ .pmg_event_ids = power4_group_event_ids[58],
.pmg_mmcr0 = 0x0000000000000e1cULL,
.pmg_mmcr1 = 0x0010c000739c74b8ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2696,7 +3746,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 59 ] = {
.pmg_name = "pm_hpmcount1",
.pmg_desc = "Hpmcount group for L1 and TLB behavior analysis",
- .pmg_event_ids = { 6, 88, 79, 70, 82, 86, 84, 82 },
+ .pmg_event_ids = power4_group_event_ids[59],
.pmg_mmcr0 = 0x0000000000001414ULL,
.pmg_mmcr1 = 0x010b000044ce9420ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2704,7 +3754,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 60 ] = {
.pmg_name = "pm_hpmcount2",
.pmg_desc = "Hpmcount group for computation intensity analysis",
- .pmg_event_ids = { 84, 83, 22, 27, 82, 84, 78, 78 },
+ .pmg_event_ids = power4_group_event_ids[60],
.pmg_mmcr0 = 0x0000000000000810ULL,
.pmg_mmcr1 = 0x010020289dce84a0ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2712,7 +3762,7 @@ static pmg_power4_group_t power4_groups[] = {
[ 61 ] = {
.pmg_name = "pm_l1andbr",
.pmg_desc = "L1 misses and branch misspredict analysis",
- .pmg_event_ids = { 86, 81, 79, 8, 79, 81, 9, 10 },
+ .pmg_event_ids = power4_group_event_ids[61],
.pmg_mmcr0 = 0x000000000000090eULL,
.pmg_mmcr1 = 0x8003c00046367ce8ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2720,11 +3770,12 @@ static pmg_power4_group_t power4_groups[] = {
[ 62 ] = {
.pmg_name = "Instruction mix: loads",
.pmg_desc = " stores and branches",
- .pmg_event_ids = { 86, 81, 79, 8, 82, 79, 84, 82 },
+ .pmg_event_ids = power4_group_event_ids[62],
.pmg_mmcr0 = 0x000000000000090eULL,
.pmg_mmcr1 = 0x8003c000460fb420ULL,
.pmg_mmcra = 0x0000000000002000ULL
}
};
+
#endif
diff --git a/src/libpfm-3.y/lib/power5+_events.h b/src/libpfm-3.y/lib/power5+_events.h
index a5e868d5de2392568312fae196d2c4a2c429bedd..34f3398a57ffc35435c949dddbb77833202fdf06 100644
--- a/src/libpfm-3.y/lib/power5+_events.h
+++ b/src/libpfm-3.y/lib/power5+_events.h
@@ -20,5328 +20,7459 @@
* hand.
*
*/
-static pme_power5p_entry_t power5p_pe[] = {
#define POWER5p_PME_PM_LSU_REJECT_RELOAD_CDF 0
+#define POWER5p_PME_PM_FPU1_SINGLE 1
+#define POWER5p_PME_PM_L3SB_REF 2
+#define POWER5p_PME_PM_THRD_PRIO_DIFF_3or4_CYC 3
+#define POWER5p_PME_PM_INST_FROM_L275_SHR 4
+#define POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD 5
+#define POWER5p_PME_PM_DTLB_MISS_4K 6
+#define POWER5p_PME_PM_CLB_FULL_CYC 7
+#define POWER5p_PME_PM_MRK_ST_CMPL 8
+#define POWER5p_PME_PM_LSU_FLUSH_LRQ_FULL 9
+#define POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR 10
+#define POWER5p_PME_PM_1INST_CLB_CYC 11
+#define POWER5p_PME_PM_MEM_SPEC_RD_CANCEL 12
+#define POWER5p_PME_PM_MRK_DTLB_MISS_16M 13
+#define POWER5p_PME_PM_FPU_FDIV 14
+#define POWER5p_PME_PM_FPU_SINGLE 15
+#define POWER5p_PME_PM_FPU0_FMA 16
+#define POWER5p_PME_PM_SLB_MISS 17
+#define POWER5p_PME_PM_LSU1_FLUSH_LRQ 18
+#define POWER5p_PME_PM_L2SA_ST_HIT 19
+#define POWER5p_PME_PM_DTLB_MISS 20
+#define POWER5p_PME_PM_BR_PRED_TA 21
+#define POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD_CYC 22
+#define POWER5p_PME_PM_CMPLU_STALL_FXU 23
+#define POWER5p_PME_PM_EXT_INT 24
+#define POWER5p_PME_PM_MRK_LSU1_FLUSH_LRQ 25
+#define POWER5p_PME_PM_MRK_ST_GPS 26
+#define POWER5p_PME_PM_LSU1_LDF 27
+#define POWER5p_PME_PM_FAB_CMD_ISSUED 28
+#define POWER5p_PME_PM_LSU0_SRQ_STFWD 29
+#define POWER5p_PME_PM_CR_MAP_FULL_CYC 30
+#define POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL 31
+#define POWER5p_PME_PM_MRK_LSU0_FLUSH_ULD 32
+#define POWER5p_PME_PM_LSU_FLUSH_SRQ_FULL 33
+#define POWER5p_PME_PM_MEM_RQ_DISP_Q16to19 34
+#define POWER5p_PME_PM_FLUSH_IMBAL 35
+#define POWER5p_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC 36
+#define POWER5p_PME_PM_DATA_FROM_L35_MOD 37
+#define POWER5p_PME_PM_MEM_HI_PRIO_WR_CMPL 38
+#define POWER5p_PME_PM_FPU1_FDIV 39
+#define POWER5p_PME_PM_MEM_RQ_DISP 40
+#define POWER5p_PME_PM_FPU0_FRSP_FCONV 41
+#define POWER5p_PME_PM_LWSYNC_HELD 42
+#define POWER5p_PME_PM_FXU_FIN 43
+#define POWER5p_PME_PM_DSLB_MISS 44
+#define POWER5p_PME_PM_DATA_FROM_L275_SHR 45
+#define POWER5p_PME_PM_FXLS1_FULL_CYC 46
+#define POWER5p_PME_PM_THRD_SEL_T0 47
+#define POWER5p_PME_PM_PTEG_RELOAD_VALID 48
+#define POWER5p_PME_PM_MRK_STCX_FAIL 49
+#define POWER5p_PME_PM_LSU_LMQ_LHR_MERGE 50
+#define POWER5p_PME_PM_2INST_CLB_CYC 51
+#define POWER5p_PME_PM_FAB_PNtoVN_DIRECT 52
+#define POWER5p_PME_PM_PTEG_FROM_L2MISS 53
+#define POWER5p_PME_PM_CMPLU_STALL_LSU 54
+#define POWER5p_PME_PM_MRK_DSLB_MISS 55
+#define POWER5p_PME_PM_LSU_FLUSH_ULD 56
+#define POWER5p_PME_PM_PTEG_FROM_LMEM 57
+#define POWER5p_PME_PM_MRK_BRU_FIN 58
+#define POWER5p_PME_PM_MEM_WQ_DISP_WRITE 59
+#define POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD_CYC 60
+#define POWER5p_PME_PM_LSU1_NCLD 61
+#define POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER 62
+#define POWER5p_PME_PM_SNOOP_PW_RETRY_WQ_PWQ 63
+#define POWER5p_PME_PM_FPU1_FULL_CYC 64
+#define POWER5p_PME_PM_FPR_MAP_FULL_CYC 65
+#define POWER5p_PME_PM_L3SA_ALL_BUSY 66
+#define POWER5p_PME_PM_3INST_CLB_CYC 67
+#define POWER5p_PME_PM_MEM_PWQ_DISP_Q2or3 68
+#define POWER5p_PME_PM_L2SA_SHR_INV 69
+#define POWER5p_PME_PM_THRESH_TIMEO 70
+#define POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL 71
+#define POWER5p_PME_PM_THRD_SEL_OVER_GCT_IMBAL 72
+#define POWER5p_PME_PM_FPU_FSQRT 73
+#define POWER5p_PME_PM_PMC1_OVERFLOW 74
+#define POWER5p_PME_PM_MRK_LSU0_FLUSH_LRQ 75
+#define POWER5p_PME_PM_L3SC_SNOOP_RETRY 76
+#define POWER5p_PME_PM_DATA_TABLEWALK_CYC 77
+#define POWER5p_PME_PM_THRD_PRIO_6_CYC 78
+#define POWER5p_PME_PM_FPU_FEST 79
+#define POWER5p_PME_PM_FAB_M1toP1_SIDECAR_EMPTY 80
+#define POWER5p_PME_PM_MRK_DATA_FROM_RMEM 81
+#define POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD_CYC 82
+#define POWER5p_PME_PM_MEM_PWQ_DISP 83
+#define POWER5p_PME_PM_FAB_P1toM1_SIDECAR_EMPTY 84
+#define POWER5p_PME_PM_LD_MISS_L1_LSU0 85
+#define POWER5p_PME_PM_SNOOP_PARTIAL_RTRY_QFULL 86
+#define POWER5p_PME_PM_FPU1_STALL3 87
+#define POWER5p_PME_PM_GCT_USAGE_80to99_CYC 88
+#define POWER5p_PME_PM_WORK_HELD 89
+#define POWER5p_PME_PM_INST_CMPL 90
+#define POWER5p_PME_PM_LSU1_FLUSH_UST 91
+#define POWER5p_PME_PM_FXU_IDLE 92
+#define POWER5p_PME_PM_LSU0_FLUSH_ULD 93
+#define POWER5p_PME_PM_LSU1_REJECT_LMQ_FULL 94
+#define POWER5p_PME_PM_GRP_DISP_REJECT 95
+#define POWER5p_PME_PM_PTEG_FROM_L25_SHR 96
+#define POWER5p_PME_PM_L2SA_MOD_INV 97
+#define POWER5p_PME_PM_FAB_CMD_RETRIED 98
+#define POWER5p_PME_PM_L3SA_SHR_INV 99
+#define POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL 100
+#define POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_ADDR 101
+#define POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL 102
+#define POWER5p_PME_PM_PTEG_FROM_L375_MOD 103
+#define POWER5p_PME_PM_MRK_LSU1_FLUSH_UST 104
+#define POWER5p_PME_PM_BR_ISSUED 105
+#define POWER5p_PME_PM_MRK_GRP_BR_REDIR 106
+#define POWER5p_PME_PM_EE_OFF 107
+#define POWER5p_PME_PM_IERAT_XLATE_WR_LP 108
+#define POWER5p_PME_PM_DTLB_REF_64K 109
+#define POWER5p_PME_PM_MEM_RQ_DISP_Q4to7 110
+#define POWER5p_PME_PM_MEM_FAST_PATH_RD_DISP 111
+#define POWER5p_PME_PM_INST_FROM_L3 112
+#define POWER5p_PME_PM_ITLB_MISS 113
+#define POWER5p_PME_PM_FXU1_BUSY_FXU0_IDLE 114
+#define POWER5p_PME_PM_DTLB_REF_4K 115
+#define POWER5p_PME_PM_FXLS_FULL_CYC 116
+#define POWER5p_PME_PM_GRP_DISP_VALID 117
+#define POWER5p_PME_PM_LSU_FLUSH_UST 118
+#define POWER5p_PME_PM_FXU1_FIN 119
+#define POWER5p_PME_PM_THRD_PRIO_4_CYC 120
+#define POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD 121
+#define POWER5p_PME_PM_4INST_CLB_CYC 122
+#define POWER5p_PME_PM_MRK_DTLB_REF_16M 123
+#define POWER5p_PME_PM_INST_FROM_L375_MOD 124
+#define POWER5p_PME_PM_GRP_CMPL 125
+#define POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_ADDR 126
+#define POWER5p_PME_PM_FPU1_1FLOP 127
+#define POWER5p_PME_PM_FPU_FRSP_FCONV 128
+#define POWER5p_PME_PM_L3SC_REF 129
+#define POWER5p_PME_PM_5INST_CLB_CYC 130
+#define POWER5p_PME_PM_THRD_L2MISS_BOTH_CYC 131
+#define POWER5p_PME_PM_MEM_PW_GATH 132
+#define POWER5p_PME_PM_DTLB_REF_16G 133
+#define POWER5p_PME_PM_FAB_DCLAIM_ISSUED 134
+#define POWER5p_PME_PM_FAB_PNtoNN_SIDECAR 135
+#define POWER5p_PME_PM_GRP_IC_MISS 136
+#define POWER5p_PME_PM_INST_FROM_L35_SHR 137
+#define POWER5p_PME_PM_LSU_LMQ_FULL_CYC 138
+#define POWER5p_PME_PM_MRK_DATA_FROM_L2_CYC 139
+#define POWER5p_PME_PM_LSU_SRQ_SYNC_CYC 140
+#define POWER5p_PME_PM_LSU0_BUSY_REJECT 141
+#define POWER5p_PME_PM_LSU_REJECT_ERAT_MISS 142
+#define POWER5p_PME_PM_MRK_DATA_FROM_RMEM_CYC 143
+#define POWER5p_PME_PM_DATA_FROM_L375_SHR 144
+#define POWER5p_PME_PM_PTEG_FROM_L25_MOD 145
+#define POWER5p_PME_PM_FPU0_FMOV_FEST 146
+#define POWER5p_PME_PM_THRD_PRIO_7_CYC 147
+#define POWER5p_PME_PM_LSU1_FLUSH_SRQ 148
+#define POWER5p_PME_PM_LD_REF_L1_LSU0 149
+#define POWER5p_PME_PM_L2SC_RCST_DISP 150
+#define POWER5p_PME_PM_CMPLU_STALL_DIV 151
+#define POWER5p_PME_PM_MEM_RQ_DISP_Q12to15 152
+#define POWER5p_PME_PM_INST_FROM_L375_SHR 153
+#define POWER5p_PME_PM_ST_REF_L1 154
+#define POWER5p_PME_PM_L3SB_ALL_BUSY 155
+#define POWER5p_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY 156
+#define POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR_CYC 157
+#define POWER5p_PME_PM_FAB_HOLDtoNN_EMPTY 158
+#define POWER5p_PME_PM_DATA_FROM_LMEM 159
+#define POWER5p_PME_PM_RUN_CYC 160
+#define POWER5p_PME_PM_PTEG_FROM_RMEM 161
+#define POWER5p_PME_PM_L2SC_RCLD_DISP 162
+#define POWER5p_PME_PM_LSU_LRQ_S0_VALID 163
+#define POWER5p_PME_PM_LSU0_LDF 164
+#define POWER5p_PME_PM_PMC3_OVERFLOW 165
+#define POWER5p_PME_PM_MRK_IMR_RELOAD 166
+#define POWER5p_PME_PM_MRK_GRP_TIMEO 167
+#define POWER5p_PME_PM_ST_MISS_L1 168
+#define POWER5p_PME_PM_STOP_COMPLETION 169
+#define POWER5p_PME_PM_LSU_BUSY_REJECT 170
+#define POWER5p_PME_PM_ISLB_MISS 171
+#define POWER5p_PME_PM_CYC 172
+#define POWER5p_PME_PM_THRD_ONE_RUN_CYC 173
+#define POWER5p_PME_PM_GRP_BR_REDIR_NONSPEC 174
+#define POWER5p_PME_PM_LSU1_SRQ_STFWD 175
+#define POWER5p_PME_PM_L3SC_MOD_INV 176
+#define POWER5p_PME_PM_L2_PREF 177
+#define POWER5p_PME_PM_GCT_NOSLOT_BR_MPRED 178
+#define POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD 179
+#define POWER5p_PME_PM_L2SB_ST_REQ 180
+#define POWER5p_PME_PM_L2SB_MOD_INV 181
+#define POWER5p_PME_PM_MRK_L1_RELOAD_VALID 182
+#define POWER5p_PME_PM_L3SB_HIT 183
+#define POWER5p_PME_PM_L2SB_SHR_MOD 184
+#define POWER5p_PME_PM_EE_OFF_EXT_INT 185
+#define POWER5p_PME_PM_1PLUS_PPC_CMPL 186
+#define POWER5p_PME_PM_L2SC_SHR_MOD 187
+#define POWER5p_PME_PM_PMC6_OVERFLOW 188
+#define POWER5p_PME_PM_IC_PREF_INSTALL 189
+#define POWER5p_PME_PM_LSU_LRQ_FULL_CYC 190
+#define POWER5p_PME_PM_TLB_MISS 191
+#define POWER5p_PME_PM_GCT_FULL_CYC 192
+#define POWER5p_PME_PM_FXU_BUSY 193
+#define POWER5p_PME_PM_MRK_DATA_FROM_L3_CYC 194
+#define POWER5p_PME_PM_LSU_REJECT_LMQ_FULL 195
+#define POWER5p_PME_PM_LSU_SRQ_S0_ALLOC 196
+#define POWER5p_PME_PM_GRP_MRK 197
+#define POWER5p_PME_PM_INST_FROM_L25_SHR 198
+#define POWER5p_PME_PM_DC_PREF_STREAM_ALLOC 199
+#define POWER5p_PME_PM_FPU1_FIN 200
+#define POWER5p_PME_PM_BR_MPRED_TA 201
+#define POWER5p_PME_PM_MRK_DTLB_REF_64K 202
+#define POWER5p_PME_PM_RUN_INST_CMPL 203
+#define POWER5p_PME_PM_CRQ_FULL_CYC 204
+#define POWER5p_PME_PM_L2SA_RCLD_DISP 205
+#define POWER5p_PME_PM_SNOOP_WR_RETRY_QFULL 206
+#define POWER5p_PME_PM_MRK_DTLB_REF_4K 207
+#define POWER5p_PME_PM_LSU_SRQ_S0_VALID 208
+#define POWER5p_PME_PM_LSU0_FLUSH_LRQ 209
+#define POWER5p_PME_PM_INST_FROM_L275_MOD 210
+#define POWER5p_PME_PM_GCT_EMPTY_CYC 211
+#define POWER5p_PME_PM_LARX_LSU0 212
+#define POWER5p_PME_PM_THRD_PRIO_DIFF_5or6_CYC 213
+#define POWER5p_PME_PM_SNOOP_RETRY_1AHEAD 214
+#define POWER5p_PME_PM_FPU1_FSQRT 215
+#define POWER5p_PME_PM_MRK_LD_MISS_L1_LSU1 216
+#define POWER5p_PME_PM_MRK_FPU_FIN 217
+#define POWER5p_PME_PM_THRD_PRIO_5_CYC 218
+#define POWER5p_PME_PM_MRK_DATA_FROM_LMEM 219
+#define POWER5p_PME_PM_SNOOP_TLBIE 220
+#define POWER5p_PME_PM_FPU1_FRSP_FCONV 221
+#define POWER5p_PME_PM_DTLB_MISS_16G 222
+#define POWER5p_PME_PM_L3SB_SNOOP_RETRY 223
+#define POWER5p_PME_PM_FAB_VBYPASS_EMPTY 224
+#define POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD 225
+#define POWER5p_PME_PM_L2SB_RCST_DISP 226
+#define POWER5p_PME_PM_6INST_CLB_CYC 227
+#define POWER5p_PME_PM_FLUSH 228
+#define POWER5p_PME_PM_L2SC_MOD_INV 229
+#define POWER5p_PME_PM_FPU_DENORM 230
+#define POWER5p_PME_PM_L3SC_HIT 231
+#define POWER5p_PME_PM_SNOOP_WR_RETRY_RQ 232
+#define POWER5p_PME_PM_LSU1_REJECT_SRQ 233
+#define POWER5p_PME_PM_L3SC_ALL_BUSY 234
+#define POWER5p_PME_PM_IC_PREF_REQ 235
+#define POWER5p_PME_PM_MRK_GRP_IC_MISS 236
+#define POWER5p_PME_PM_GCT_NOSLOT_IC_MISS 237
+#define POWER5p_PME_PM_MRK_DATA_FROM_L3 238
+#define POWER5p_PME_PM_GCT_NOSLOT_SRQ_FULL 239
+#define POWER5p_PME_PM_CMPLU_STALL_DCACHE_MISS 240
+#define POWER5p_PME_PM_THRD_SEL_OVER_ISU_HOLD 241
+#define POWER5p_PME_PM_LSU_FLUSH_LRQ 242
+#define POWER5p_PME_PM_THRD_PRIO_2_CYC 243
+#define POWER5p_PME_PM_L3SA_MOD_INV 244
+#define POWER5p_PME_PM_LSU_FLUSH_SRQ 245
+#define POWER5p_PME_PM_MRK_LSU_SRQ_INST_VALID 246
+#define POWER5p_PME_PM_L3SA_REF 247
+#define POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL 248
+#define POWER5p_PME_PM_FPU0_STALL3 249
+#define POWER5p_PME_PM_TB_BIT_TRANS 250
+#define POWER5p_PME_PM_GPR_MAP_FULL_CYC 251
+#define POWER5p_PME_PM_MRK_LSU_FLUSH_LRQ 252
+#define POWER5p_PME_PM_FPU0_STF 253
+#define POWER5p_PME_PM_MRK_DTLB_MISS 254
+#define POWER5p_PME_PM_FPU1_FMA 255
+#define POWER5p_PME_PM_L2SA_MOD_TAG 256
+#define POWER5p_PME_PM_LSU1_FLUSH_ULD 257
+#define POWER5p_PME_PM_MRK_INST_FIN 258
+#define POWER5p_PME_PM_MRK_LSU0_FLUSH_UST 259
+#define POWER5p_PME_PM_FPU0_FULL_CYC 260
+#define POWER5p_PME_PM_LSU_LRQ_S0_ALLOC 261
+#define POWER5p_PME_PM_MRK_LSU1_FLUSH_ULD 262
+#define POWER5p_PME_PM_MRK_DTLB_REF 263
+#define POWER5p_PME_PM_BR_UNCOND 264
+#define POWER5p_PME_PM_THRD_SEL_OVER_L2MISS 265
+#define POWER5p_PME_PM_L2SB_SHR_INV 266
+#define POWER5p_PME_PM_MEM_LO_PRIO_WR_CMPL 267
+#define POWER5p_PME_PM_MRK_DTLB_MISS_64K 268
+#define POWER5p_PME_PM_MRK_ST_MISS_L1 269
+#define POWER5p_PME_PM_L3SC_MOD_TAG 270
+#define POWER5p_PME_PM_GRP_DISP_SUCCESS 271
+#define POWER5p_PME_PM_THRD_PRIO_DIFF_1or2_CYC 272
+#define POWER5p_PME_PM_IC_DEMAND_L2_BHT_REDIRECT 273
+#define POWER5p_PME_PM_LSU_DERAT_MISS 274
+#define POWER5p_PME_PM_MEM_WQ_DISP_Q8to15 275
+#define POWER5p_PME_PM_FPU0_SINGLE 276
+#define POWER5p_PME_PM_THRD_PRIO_1_CYC 277
+#define POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_OTHER 278
+#define POWER5p_PME_PM_SNOOP_RD_RETRY_RQ 279
+#define POWER5p_PME_PM_FAB_HOLDtoVN_EMPTY 280
+#define POWER5p_PME_PM_FPU1_FEST 281
+#define POWER5p_PME_PM_SNOOP_DCLAIM_RETRY_QFULL 282
+#define POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR_CYC 283
+#define POWER5p_PME_PM_MRK_ST_CMPL_INT 284
+#define POWER5p_PME_PM_FLUSH_BR_MPRED 285
+#define POWER5p_PME_PM_MRK_DTLB_MISS_16G 286
+#define POWER5p_PME_PM_FPU_STF 287
+#define POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR 288
+#define POWER5p_PME_PM_CMPLU_STALL_FPU 289
+#define POWER5p_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC 290
+#define POWER5p_PME_PM_GCT_NOSLOT_CYC 291
+#define POWER5p_PME_PM_FXU0_BUSY_FXU1_IDLE 292
+#define POWER5p_PME_PM_PTEG_FROM_L35_SHR 293
+#define POWER5p_PME_PM_MRK_DTLB_REF_16G 294
+#define POWER5p_PME_PM_MRK_LSU_FLUSH_UST 295
+#define POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR 296
+#define POWER5p_PME_PM_L3SA_HIT 297
+#define POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR 298
+#define POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_ADDR 299
+#define POWER5p_PME_PM_IERAT_XLATE_WR 300
+#define POWER5p_PME_PM_L2SA_ST_REQ 301
+#define POWER5p_PME_PM_INST_FROM_LMEM 302
+#define POWER5p_PME_PM_THRD_SEL_T1 303
+#define POWER5p_PME_PM_IC_DEMAND_L2_BR_REDIRECT 304
+#define POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR_CYC 305
+#define POWER5p_PME_PM_FPU0_1FLOP 306
+#define POWER5p_PME_PM_PTEG_FROM_L2 307
+#define POWER5p_PME_PM_MEM_PW_CMPL 308
+#define POWER5p_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC 309
+#define POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER 310
+#define POWER5p_PME_PM_MRK_DTLB_MISS_4K 311
+#define POWER5p_PME_PM_FPU0_FIN 312
+#define POWER5p_PME_PM_L3SC_SHR_INV 313
+#define POWER5p_PME_PM_GRP_BR_REDIR 314
+#define POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL 315
+#define POWER5p_PME_PM_MRK_LSU_FLUSH_SRQ 316
+#define POWER5p_PME_PM_PTEG_FROM_L275_SHR 317
+#define POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL 318
+#define POWER5p_PME_PM_SNOOP_RD_RETRY_WQ 319
+#define POWER5p_PME_PM_FAB_DCLAIM_RETRIED 320
+#define POWER5p_PME_PM_LSU0_NCLD 321
+#define POWER5p_PME_PM_LSU1_BUSY_REJECT 322
+#define POWER5p_PME_PM_FXLS0_FULL_CYC 323
+#define POWER5p_PME_PM_DTLB_REF_16M 324
+#define POWER5p_PME_PM_FPU0_FEST 325
+#define POWER5p_PME_PM_GCT_USAGE_60to79_CYC 326
+#define POWER5p_PME_PM_DATA_FROM_L25_MOD 327
+#define POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR 328
+#define POWER5p_PME_PM_LSU0_REJECT_ERAT_MISS 329
+#define POWER5p_PME_PM_DATA_FROM_L375_MOD 330
+#define POWER5p_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 331
+#define POWER5p_PME_PM_DTLB_MISS_64K 332
+#define POWER5p_PME_PM_LSU0_REJECT_RELOAD_CDF 333
+#define POWER5p_PME_PM_0INST_FETCH 334
+#define POWER5p_PME_PM_LSU1_REJECT_RELOAD_CDF 335
+#define POWER5p_PME_PM_MEM_WQ_DISP_Q0to7 336
+#define POWER5p_PME_PM_L1_PREF 337
+#define POWER5p_PME_PM_MRK_DATA_FROM_LMEM_CYC 338
+#define POWER5p_PME_PM_BRQ_FULL_CYC 339
+#define POWER5p_PME_PM_GRP_IC_MISS_NONSPEC 340
+#define POWER5p_PME_PM_PTEG_FROM_L275_MOD 341
+#define POWER5p_PME_PM_MRK_LD_MISS_L1_LSU0 342
+#define POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR_CYC 343
+#define POWER5p_PME_PM_DATA_FROM_L3 344
+#define POWER5p_PME_PM_INST_FROM_L2 345
+#define POWER5p_PME_PM_LSU_FLUSH 346
+#define POWER5p_PME_PM_PMC2_OVERFLOW 347
+#define POWER5p_PME_PM_FPU0_DENORM 348
+#define POWER5p_PME_PM_FPU1_FMOV_FEST 349
+#define POWER5p_PME_PM_INST_FETCH_CYC 350
+#define POWER5p_PME_PM_INST_DISP 351
+#define POWER5p_PME_PM_LSU_LDF 352
+#define POWER5p_PME_PM_DATA_FROM_L25_SHR 353
+#define POWER5p_PME_PM_L1_DCACHE_RELOAD_VALID 354
+#define POWER5p_PME_PM_MEM_WQ_DISP_DCLAIM 355
+#define POWER5p_PME_PM_MRK_GRP_ISSUED 356
+#define POWER5p_PME_PM_FPU_FULL_CYC 357
+#define POWER5p_PME_PM_INST_FROM_L35_MOD 358
+#define POWER5p_PME_PM_FPU_FMA 359
+#define POWER5p_PME_PM_THRD_PRIO_3_CYC 360
+#define POWER5p_PME_PM_MRK_CRU_FIN 361
+#define POWER5p_PME_PM_SNOOP_WR_RETRY_WQ 362
+#define POWER5p_PME_PM_CMPLU_STALL_REJECT 363
+#define POWER5p_PME_PM_MRK_FXU_FIN 364
+#define POWER5p_PME_PM_LSU1_REJECT_ERAT_MISS 365
+#define POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_OTHER 366
+#define POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY 367
+#define POWER5p_PME_PM_PMC4_OVERFLOW 368
+#define POWER5p_PME_PM_L3SA_SNOOP_RETRY 369
+#define POWER5p_PME_PM_PTEG_FROM_L35_MOD 370
+#define POWER5p_PME_PM_INST_FROM_L25_MOD 371
+#define POWER5p_PME_PM_THRD_SMT_HANG 372
+#define POWER5p_PME_PM_CMPLU_STALL_ERAT_MISS 373
+#define POWER5p_PME_PM_L3SA_MOD_TAG 374
+#define POWER5p_PME_PM_INST_FROM_L2MISS 375
+#define POWER5p_PME_PM_FLUSH_SYNC 376
+#define POWER5p_PME_PM_MRK_GRP_DISP 377
+#define POWER5p_PME_PM_MEM_RQ_DISP_Q8to11 378
+#define POWER5p_PME_PM_L2SC_ST_HIT 379
+#define POWER5p_PME_PM_L2SB_MOD_TAG 380
+#define POWER5p_PME_PM_CLB_EMPTY_CYC 381
+#define POWER5p_PME_PM_L2SB_ST_HIT 382
+#define POWER5p_PME_PM_MEM_NONSPEC_RD_CANCEL 383
+#define POWER5p_PME_PM_BR_PRED_CR_TA 384
+#define POWER5p_PME_PM_MRK_LSU0_FLUSH_SRQ 385
+#define POWER5p_PME_PM_MRK_LSU_FLUSH_ULD 386
+#define POWER5p_PME_PM_INST_DISP_ATTEMPT 387
+#define POWER5p_PME_PM_INST_FROM_RMEM 388
+#define POWER5p_PME_PM_ST_REF_L1_LSU0 389
+#define POWER5p_PME_PM_LSU0_DERAT_MISS 390
+#define POWER5p_PME_PM_FPU_STALL3 391
+#define POWER5p_PME_PM_L2SB_RCLD_DISP 392
+#define POWER5p_PME_PM_BR_PRED_CR 393
+#define POWER5p_PME_PM_MRK_DATA_FROM_L2 394
+#define POWER5p_PME_PM_LSU0_FLUSH_SRQ 395
+#define POWER5p_PME_PM_FAB_PNtoNN_DIRECT 396
+#define POWER5p_PME_PM_IOPS_CMPL 397
+#define POWER5p_PME_PM_L2SA_RCST_DISP 398
+#define POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_OTHER 399
+#define POWER5p_PME_PM_L2SC_SHR_INV 400
+#define POWER5p_PME_PM_SNOOP_RETRY_AB_COLLISION 401
+#define POWER5p_PME_PM_FAB_PNtoVN_SIDECAR 402
+#define POWER5p_PME_PM_LSU0_REJECT_LMQ_FULL 403
+#define POWER5p_PME_PM_LSU_LMQ_S0_ALLOC 404
+#define POWER5p_PME_PM_SNOOP_PW_RETRY_RQ 405
+#define POWER5p_PME_PM_DTLB_REF 406
+#define POWER5p_PME_PM_PTEG_FROM_L3 407
+#define POWER5p_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY 408
+#define POWER5p_PME_PM_LSU_SRQ_EMPTY_CYC 409
+#define POWER5p_PME_PM_FPU1_STF 410
+#define POWER5p_PME_PM_LSU_LMQ_S0_VALID 411
+#define POWER5p_PME_PM_GCT_USAGE_00to59_CYC 412
+#define POWER5p_PME_PM_FPU_FMOV_FEST 413
+#define POWER5p_PME_PM_DATA_FROM_L2MISS 414
+#define POWER5p_PME_PM_XER_MAP_FULL_CYC 415
+#define POWER5p_PME_PM_GRP_DISP_BLK_SB_CYC 416
+#define POWER5p_PME_PM_FLUSH_SB 417
+#define POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR 418
+#define POWER5p_PME_PM_MRK_GRP_CMPL 419
+#define POWER5p_PME_PM_SUSPENDED 420
+#define POWER5p_PME_PM_SNOOP_RD_RETRY_QFULL 421
+#define POWER5p_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC 422
+#define POWER5p_PME_PM_DATA_FROM_L35_SHR 423
+#define POWER5p_PME_PM_L3SB_MOD_INV 424
+#define POWER5p_PME_PM_STCX_FAIL 425
+#define POWER5p_PME_PM_LD_MISS_L1_LSU1 426
+#define POWER5p_PME_PM_GRP_DISP 427
+#define POWER5p_PME_PM_DC_PREF_DST 428
+#define POWER5p_PME_PM_FPU1_DENORM 429
+#define POWER5p_PME_PM_FPU0_FPSCR 430
+#define POWER5p_PME_PM_DATA_FROM_L2 431
+#define POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR 432
+#define POWER5p_PME_PM_FPU_1FLOP 433
+#define POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER 434
+#define POWER5p_PME_PM_FPU0_FSQRT 435
+#define POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL 436
+#define POWER5p_PME_PM_LD_REF_L1 437
+#define POWER5p_PME_PM_INST_FROM_L1 438
+#define POWER5p_PME_PM_TLBIE_HELD 439
+#define POWER5p_PME_PM_DC_PREF_OUT_OF_STREAMS 440
+#define POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD_CYC 441
+#define POWER5p_PME_PM_MRK_LSU1_FLUSH_SRQ 442
+#define POWER5p_PME_PM_MEM_RQ_DISP_Q0to3 443
+#define POWER5p_PME_PM_ST_REF_L1_LSU1 444
+#define POWER5p_PME_PM_MRK_LD_MISS_L1 445
+#define POWER5p_PME_PM_L1_WRITE_CYC 446
+#define POWER5p_PME_PM_L2SC_ST_REQ 447
+#define POWER5p_PME_PM_CMPLU_STALL_FDIV 448
+#define POWER5p_PME_PM_THRD_SEL_OVER_CLB_EMPTY 449
+#define POWER5p_PME_PM_BR_MPRED_CR 450
+#define POWER5p_PME_PM_L3SB_MOD_TAG 451
+#define POWER5p_PME_PM_MRK_DATA_FROM_L2MISS 452
+#define POWER5p_PME_PM_LSU_REJECT_SRQ 453
+#define POWER5p_PME_PM_LD_MISS_L1 454
+#define POWER5p_PME_PM_INST_FROM_PREF 455
+#define POWER5p_PME_PM_STCX_PASS 456
+#define POWER5p_PME_PM_DC_INV_L2 457
+#define POWER5p_PME_PM_LSU_SRQ_FULL_CYC 458
+#define POWER5p_PME_PM_FPU_FIN 459
+#define POWER5p_PME_PM_LSU_SRQ_STFWD 460
+#define POWER5p_PME_PM_L2SA_SHR_MOD 461
+#define POWER5p_PME_PM_0INST_CLB_CYC 462
+#define POWER5p_PME_PM_FXU0_FIN 463
+#define POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL 464
+#define POWER5p_PME_PM_THRD_GRP_CMPL_BOTH_CYC 465
+#define POWER5p_PME_PM_PMC5_OVERFLOW 466
+#define POWER5p_PME_PM_FPU0_FDIV 467
+#define POWER5p_PME_PM_PTEG_FROM_L375_SHR 468
+#define POWER5p_PME_PM_HV_CYC 469
+#define POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY 470
+#define POWER5p_PME_PM_THRD_PRIO_DIFF_0_CYC 471
+#define POWER5p_PME_PM_LR_CTR_MAP_FULL_CYC 472
+#define POWER5p_PME_PM_L3SB_SHR_INV 473
+#define POWER5p_PME_PM_DATA_FROM_RMEM 474
+#define POWER5p_PME_PM_DATA_FROM_L275_MOD 475
+#define POWER5p_PME_PM_LSU0_REJECT_SRQ 476
+#define POWER5p_PME_PM_LSU1_DERAT_MISS 477
+#define POWER5p_PME_PM_MRK_LSU_FIN 478
+#define POWER5p_PME_PM_DTLB_MISS_16M 479
+#define POWER5p_PME_PM_LSU0_FLUSH_UST 480
+#define POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY 481
+#define POWER5p_PME_PM_L2SC_MOD_TAG 482
+
+
+static const int power5p_event_ids[][POWER5p_NUM_EVENT_COUNTERS] = {
+ [ POWER5p_PME_PM_LSU_REJECT_RELOAD_CDF ] = { -1, 243, 240, -1, -1, -1 },
+ [ POWER5p_PME_PM_FPU1_SINGLE ] = { 82, 81, 81, 83, -1, -1 },
+ [ POWER5p_PME_PM_L3SB_REF ] = { 188, 185, 184, 183, -1, -1 },
+ [ POWER5p_PME_PM_THRD_PRIO_DIFF_3or4_CYC ] = { 343, 338, 336, 332, -1, -1 },
+ [ POWER5p_PME_PM_INST_FROM_L275_SHR ] = { -1, -1, 115, -1, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD ] = { 274, -1, -1, 268, -1, -1 },
+ [ POWER5p_PME_PM_DTLB_MISS_4K ] = { 32, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_CLB_FULL_CYC ] = { 14, 13, 13, 14, -1, -1 },
+ [ POWER5p_PME_PM_MRK_ST_CMPL ] = { 299, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_LSU_FLUSH_LRQ_FULL ] = { 232, 231, 230, 227, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR ] = { -1, -1, 265, -1, -1, -1 },
+ [ POWER5p_PME_PM_1INST_CLB_CYC ] = { 1, 1, 1, 2, -1, -1 },
+ [ POWER5p_PME_PM_MEM_SPEC_RD_CANCEL ] = { 264, 263, 259, 258, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DTLB_MISS_16M ] = { -1, -1, 273, -1, -1, -1 },
+ [ POWER5p_PME_PM_FPU_FDIV ] = { 87, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_FPU_SINGLE ] = { 90, -1, -1, 90, -1, -1 },
+ [ POWER5p_PME_PM_FPU0_FMA ] = { 63, 62, 62, 64, -1, -1 },
+ [ POWER5p_PME_PM_SLB_MISS ] = { -1, 307, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_LSU1_FLUSH_LRQ ] = { 220, 216, 216, 215, -1, -1 },
+ [ POWER5p_PME_PM_L2SA_ST_HIT ] = { 142, 139, 138, 137, -1, -1 },
+ [ POWER5p_PME_PM_DTLB_MISS ] = { 31, 30, 30, 31, -1, -1 },
+ [ POWER5p_PME_PM_BR_PRED_TA ] = { 203, 11, 351, 348, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD_CYC ] = { -1, -1, -1, 269, -1, -1 },
+ [ POWER5p_PME_PM_CMPLU_STALL_FXU ] = { -1, 16, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_EXT_INT ] = { -1, -1, -1, 37, -1, -1 },
+ [ POWER5p_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { 292, 292, 286, 289, -1, -1 },
+ [ POWER5p_PME_PM_MRK_ST_GPS ] = { -1, 299, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_LSU1_LDF ] = { 224, 220, 220, 219, -1, -1 },
+ [ POWER5p_PME_PM_FAB_CMD_ISSUED ] = { 37, 36, 36, 38, -1, -1 },
+ [ POWER5p_PME_PM_LSU0_SRQ_STFWD ] = { 217, 213, 213, 212, -1, -1 },
+ [ POWER5p_PME_PM_CR_MAP_FULL_CYC ] = { 16, 19, 15, 20, -1, -1 },
+ [ POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL ] = { 137, 134, 133, 132, -1, -1 },
+ [ POWER5p_PME_PM_MRK_LSU0_FLUSH_ULD ] = { 290, 290, 284, 287, -1, -1 },
+ [ POWER5p_PME_PM_LSU_FLUSH_SRQ_FULL ] = { 234, 232, 231, 229, -1, -1 },
+ [ POWER5p_PME_PM_MEM_RQ_DISP_Q16to19 ] = { 360, 353, 352, 246, -1, -1 },
+ [ POWER5p_PME_PM_FLUSH_IMBAL ] = { 54, 53, 53, 55, -1, -1 },
+ [ POWER5p_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC ] = { 346, 341, 339, 335, -1, -1 },
+ [ POWER5p_PME_PM_DATA_FROM_L35_MOD ] = { -1, 22, 21, -1, -1, -1 },
+ [ POWER5p_PME_PM_MEM_HI_PRIO_WR_CMPL ] = { 253, 252, 248, 247, -1, -1 },
+ [ POWER5p_PME_PM_FPU1_FDIV ] = { 74, 73, 73, 75, -1, -1 },
+ [ POWER5p_PME_PM_MEM_RQ_DISP ] = { 261, 260, 256, 255, -1, -1 },
+ [ POWER5p_PME_PM_FPU0_FRSP_FCONV ] = { 66, 65, 65, 67, -1, -1 },
+ [ POWER5p_PME_PM_LWSYNC_HELD ] = { 250, 249, 245, 244, -1, -1 },
+ [ POWER5p_PME_PM_FXU_FIN ] = { -1, -1, 93, -1, -1, -1 },
+ [ POWER5p_PME_PM_DSLB_MISS ] = { 30, 29, 29, 30, -1, -1 },
+ [ POWER5p_PME_PM_DATA_FROM_L275_SHR ] = { -1, -1, 18, -1, -1, -1 },
+ [ POWER5p_PME_PM_FXLS1_FULL_CYC ] = { 92, 90, 89, 92, -1, -1 },
+ [ POWER5p_PME_PM_THRD_SEL_T0 ] = { 352, 347, 345, 341, -1, -1 },
+ [ POWER5p_PME_PM_PTEG_RELOAD_VALID ] = { 311, 306, 305, 303, -1, -1 },
+ [ POWER5p_PME_PM_MRK_STCX_FAIL ] = { 298, 298, 293, 297, -1, -1 },
+ [ POWER5p_PME_PM_LSU_LMQ_LHR_MERGE ] = { 238, 235, 233, 232, -1, -1 },
+ [ POWER5p_PME_PM_2INST_CLB_CYC ] = { 3, 2, 2, 3, -1, -1 },
+ [ POWER5p_PME_PM_FAB_PNtoVN_DIRECT ] = { 49, 48, 48, 50, -1, -1 },
+ [ POWER5p_PME_PM_PTEG_FROM_L2MISS ] = { -1, -1, 300, -1, -1, -1 },
+ [ POWER5p_PME_PM_CMPLU_STALL_LSU ] = { -1, 17, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DSLB_MISS ] = { 276, 278, 271, 273, -1, -1 },
+ [ POWER5p_PME_PM_LSU_FLUSH_ULD ] = { 235, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_PTEG_FROM_LMEM ] = { -1, 305, 304, -1, -1, -1 },
+ [ POWER5p_PME_PM_MRK_BRU_FIN ] = { -1, 268, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_MEM_WQ_DISP_WRITE ] = { 268, 267, 263, 262, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD_CYC ] = { -1, -1, -1, 266, -1, -1 },
+ [ POWER5p_PME_PM_LSU1_NCLD ] = { 225, 221, 221, 220, -1, -1 },
+ [ POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER ] = { 132, 129, 128, 127, -1, -1 },
+ [ POWER5p_PME_PM_SNOOP_PW_RETRY_WQ_PWQ ] = { 316, 311, 309, 307, -1, -1 },
+ [ POWER5p_PME_PM_FPU1_FULL_CYC ] = { 81, 80, 80, 82, -1, -1 },
+ [ POWER5p_PME_PM_FPR_MAP_FULL_CYC ] = { 57, 56, 56, 58, -1, -1 },
+ [ POWER5p_PME_PM_L3SA_ALL_BUSY ] = { 177, 174, 173, 172, -1, -1 },
+ [ POWER5p_PME_PM_3INST_CLB_CYC ] = { 4, 3, 3, 4, -1, -1 },
+ [ POWER5p_PME_PM_MEM_PWQ_DISP_Q2or3 ] = { 257, 250, 252, 251, -1, -1 },
+ [ POWER5p_PME_PM_L2SA_SHR_INV ] = { 140, 137, 136, 135, -1, -1 },
+ [ POWER5p_PME_PM_THRESH_TIMEO ] = { -1, -1, 348, -1, -1, -1 },
+ [ POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL ] = { 139, 136, 135, 134, -1, -1 },
+ [ POWER5p_PME_PM_THRD_SEL_OVER_GCT_IMBAL ] = { 349, 344, 342, 338, -1, -1 },
+ [ POWER5p_PME_PM_FPU_FSQRT ] = { -1, 86, 86, -1, -1, -1 },
+ [ POWER5p_PME_PM_PMC1_OVERFLOW ] = { -1, 301, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { 288, 288, 282, 285, -1, -1 },
+ [ POWER5p_PME_PM_L3SC_SNOOP_RETRY ] = { 197, 194, 193, 192, -1, -1 },
+ [ POWER5p_PME_PM_DATA_TABLEWALK_CYC ] = { 25, 24, 24, 25, -1, -1 },
+ [ POWER5p_PME_PM_THRD_PRIO_6_CYC ] = { 339, 334, 332, 328, -1, -1 },
+ [ POWER5p_PME_PM_FPU_FEST ] = { 88, -1, -1, 87, -1, -1 },
+ [ POWER5p_PME_PM_FAB_M1toP1_SIDECAR_EMPTY ] = { 43, 42, 42, 44, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_RMEM ] = { 275, -1, -1, 271, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD_CYC ] = { -1, -1, -1, 267, -1, -1 },
+ [ POWER5p_PME_PM_MEM_PWQ_DISP ] = { 256, 255, 251, 250, -1, -1 },
+ [ POWER5p_PME_PM_FAB_P1toM1_SIDECAR_EMPTY ] = { 45, 44, 44, 46, -1, -1 },
+ [ POWER5p_PME_PM_LD_MISS_L1_LSU0 ] = { 199, 196, 196, 194, -1, -1 },
+ [ POWER5p_PME_PM_SNOOP_PARTIAL_RTRY_QFULL ] = { 314, 309, 307, 305, -1, -1 },
+ [ POWER5p_PME_PM_FPU1_STALL3 ] = { 83, 82, 82, 84, -1, -1 },
+ [ POWER5p_PME_PM_GCT_USAGE_80to99_CYC ] = { -1, -1, 96, -1, -1, -1 },
+ [ POWER5p_PME_PM_WORK_HELD ] = { -1, -1, -1, 345, -1, -1 },
+ [ POWER5p_PME_PM_INST_CMPL ] = { 303, 302, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_LSU1_FLUSH_UST ] = { 223, 219, 219, 218, -1, -1 },
+ [ POWER5p_PME_PM_FXU_IDLE ] = { 96, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_LSU0_FLUSH_ULD ] = { 209, 205, 205, 204, -1, -1 },
+ [ POWER5p_PME_PM_LSU1_REJECT_LMQ_FULL ] = { 227, 223, 223, 222, -1, -1 },
+ [ POWER5p_PME_PM_GRP_DISP_REJECT ] = { 104, 104, 102, 103, -1, -1 },
+ [ POWER5p_PME_PM_PTEG_FROM_L25_SHR ] = { 305, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_L2SA_MOD_INV ] = { 128, 125, 124, 123, -1, -1 },
+ [ POWER5p_PME_PM_FAB_CMD_RETRIED ] = { 38, 37, 37, 39, -1, -1 },
+ [ POWER5p_PME_PM_L3SA_SHR_INV ] = { 182, 179, 178, 177, -1, -1 },
+ [ POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL ] = { 155, 152, 151, 150, -1, -1 },
+ [ POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_ADDR ] = { 135, 132, 131, 130, -1, -1 },
+ [ POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL ] = { 133, 130, 129, 128, -1, -1 },
+ [ POWER5p_PME_PM_PTEG_FROM_L375_MOD ] = { 309, -1, -1, 301, -1, -1 },
+ [ POWER5p_PME_PM_MRK_LSU1_FLUSH_UST ] = { 295, 295, 289, 292, -1, -1 },
+ [ POWER5p_PME_PM_BR_ISSUED ] = { 9, 8, 8, 9, -1, -1 },
+ [ POWER5p_PME_PM_MRK_GRP_BR_REDIR ] = { -1, 283, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_EE_OFF ] = { 35, 34, 34, 35, -1, -1 },
+ [ POWER5p_PME_PM_IERAT_XLATE_WR_LP ] = { 114, 112, 111, 111, -1, -1 },
+ [ POWER5p_PME_PM_DTLB_REF_64K ] = { -1, 33, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_MEM_RQ_DISP_Q4to7 ] = { 262, 259, 258, 257, -1, -1 },
+ [ POWER5p_PME_PM_MEM_FAST_PATH_RD_DISP ] = { 251, 354, 246, 245, -1, -1 },
+ [ POWER5p_PME_PM_INST_FROM_L3 ] = { 121, -1, 116, -1, -1, -1 },
+ [ POWER5p_PME_PM_ITLB_MISS ] = { 124, 121, 120, 119, -1, -1 },
+ [ POWER5p_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { -1, -1, -1, 95, -1, -1 },
+ [ POWER5p_PME_PM_DTLB_REF_4K ] = { 34, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_FXLS_FULL_CYC ] = { 93, -1, -1, 93, -1, -1 },
+ [ POWER5p_PME_PM_GRP_DISP_VALID ] = { 105, 105, 104, 104, -1, -1 },
+ [ POWER5p_PME_PM_LSU_FLUSH_UST ] = { -1, 233, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_FXU1_FIN ] = { 95, 92, 92, 96, -1, -1 },
+ [ POWER5p_PME_PM_THRD_PRIO_4_CYC ] = { 337, 332, 330, 326, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD ] = { -1, 273, 268, -1, -1, -1 },
+ [ POWER5p_PME_PM_4INST_CLB_CYC ] = { 5, 4, 4, 5, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DTLB_REF_16M ] = { -1, -1, 275, -1, -1, -1 },
+ [ POWER5p_PME_PM_INST_FROM_L375_MOD ] = { -1, -1, -1, 116, -1, -1 },
+ [ POWER5p_PME_PM_GRP_CMPL ] = { -1, -1, 100, -1, -1, -1 },
+ [ POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_ADDR ] = { 167, 164, 163, 162, -1, -1 },
+ [ POWER5p_PME_PM_FPU1_1FLOP ] = { 72, 71, 71, 73, -1, -1 },
+ [ POWER5p_PME_PM_FPU_FRSP_FCONV ] = { -1, 85, 85, -1, -1, -1 },
+ [ POWER5p_PME_PM_L3SC_REF ] = { 195, 192, 191, 190, -1, -1 },
+ [ POWER5p_PME_PM_5INST_CLB_CYC ] = { 6, 5, 5, 6, -1, -1 },
+ [ POWER5p_PME_PM_THRD_L2MISS_BOTH_CYC ] = { 332, 328, 326, 322, -1, -1 },
+ [ POWER5p_PME_PM_MEM_PW_GATH ] = { 259, 258, 254, 253, -1, -1 },
+ [ POWER5p_PME_PM_DTLB_REF_16G ] = { -1, -1, -1, 34, -1, -1 },
+ [ POWER5p_PME_PM_FAB_DCLAIM_ISSUED ] = { 39, 38, 38, 40, -1, -1 },
+ [ POWER5p_PME_PM_FAB_PNtoNN_SIDECAR ] = { 48, 47, 47, 49, -1, -1 },
+ [ POWER5p_PME_PM_GRP_IC_MISS ] = { 106, 106, 105, 105, -1, -1 },
+ [ POWER5p_PME_PM_INST_FROM_L35_SHR ] = { 122, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_LSU_LMQ_FULL_CYC ] = { 237, 234, 232, 231, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L2_CYC ] = { -1, 272, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_LSU_SRQ_SYNC_CYC ] = { 249, 248, 244, 243, -1, -1 },
+ [ POWER5p_PME_PM_LSU0_BUSY_REJECT ] = { 205, 201, 201, 200, -1, -1 },
+ [ POWER5p_PME_PM_LSU_REJECT_ERAT_MISS ] = { 244, -1, -1, 238, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = { -1, -1, -1, 272, -1, -1 },
+ [ POWER5p_PME_PM_DATA_FROM_L375_SHR ] = { -1, -1, 22, -1, -1, -1 },
+ [ POWER5p_PME_PM_PTEG_FROM_L25_MOD ] = { -1, 303, 298, -1, -1, -1 },
+ [ POWER5p_PME_PM_FPU0_FMOV_FEST ] = { 64, 63, 63, 65, -1, -1 },
+ [ POWER5p_PME_PM_THRD_PRIO_7_CYC ] = { 340, 335, 333, 329, -1, -1 },
+ [ POWER5p_PME_PM_LSU1_FLUSH_SRQ ] = { 221, 217, 217, 216, -1, -1 },
+ [ POWER5p_PME_PM_LD_REF_L1_LSU0 ] = { 202, 198, 198, 197, -1, -1 },
+ [ POWER5p_PME_PM_L2SC_RCST_DISP ] = { 166, 163, 162, 161, -1, -1 },
+ [ POWER5p_PME_PM_CMPLU_STALL_DIV ] = { -1, -1, -1, 15, -1, -1 },
+ [ POWER5p_PME_PM_MEM_RQ_DISP_Q12to15 ] = { 359, 262, 255, 248, -1, -1 },
+ [ POWER5p_PME_PM_INST_FROM_L375_SHR ] = { -1, -1, 117, -1, -1, -1 },
+ [ POWER5p_PME_PM_ST_REF_L1 ] = { -1, 323, 322, -1, -1, -1 },
+ [ POWER5p_PME_PM_L3SB_ALL_BUSY ] = { 184, 181, 180, 179, -1, -1 },
+ [ POWER5p_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY ] = { 46, 45, 45, 47, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR_CYC ] = { -1, 271, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_FAB_HOLDtoNN_EMPTY ] = { 41, 40, 40, 42, -1, -1 },
+ [ POWER5p_PME_PM_DATA_FROM_LMEM ] = { -1, 23, 23, -1, -1, -1 },
+ [ POWER5p_PME_PM_RUN_CYC ] = { 312, -1, -1, -1, -1, 0 },
+ [ POWER5p_PME_PM_PTEG_FROM_RMEM ] = { 310, -1, -1, 302, -1, -1 },
+ [ POWER5p_PME_PM_L2SC_RCLD_DISP ] = { 162, 159, 158, 157, -1, -1 },
+ [ POWER5p_PME_PM_LSU_LRQ_S0_VALID ] = { 243, 241, 239, 237, -1, -1 },
+ [ POWER5p_PME_PM_LSU0_LDF ] = { 211, 207, 207, 206, -1, -1 },
+ [ POWER5p_PME_PM_PMC3_OVERFLOW ] = { -1, -1, -1, 299, -1, -1 },
+ [ POWER5p_PME_PM_MRK_IMR_RELOAD ] = { 283, 284, 277, 281, -1, -1 },
+ [ POWER5p_PME_PM_MRK_GRP_TIMEO ] = { -1, -1, -1, 280, -1, -1 },
+ [ POWER5p_PME_PM_ST_MISS_L1 ] = { 327, 322, 321, 318, -1, -1 },
+ [ POWER5p_PME_PM_STOP_COMPLETION ] = { -1, -1, 320, -1, -1, -1 },
+ [ POWER5p_PME_PM_LSU_BUSY_REJECT ] = { -1, 227, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_ISLB_MISS ] = { 123, 120, 119, 118, -1, -1 },
+ [ POWER5p_PME_PM_CYC ] = { 17, 20, 16, 21, -1, -1 },
+ [ POWER5p_PME_PM_THRD_ONE_RUN_CYC ] = { 333, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_GRP_BR_REDIR_NONSPEC ] = { 102, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_LSU1_SRQ_STFWD ] = { 230, 226, 226, 225, -1, -1 },
+ [ POWER5p_PME_PM_L3SC_MOD_INV ] = { 193, 190, 189, 188, -1, -1 },
+ [ POWER5p_PME_PM_L2_PREF ] = { 176, 173, 172, 171, -1, -1 },
+ [ POWER5p_PME_PM_GCT_NOSLOT_BR_MPRED ] = { -1, -1, -1, 98, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD ] = { -1, 269, 264, -1, -1, -1 },
+ [ POWER5p_PME_PM_L2SB_ST_REQ ] = { 159, 156, 155, 154, -1, -1 },
+ [ POWER5p_PME_PM_L2SB_MOD_INV ] = { 144, 141, 140, 139, -1, -1 },
+ [ POWER5p_PME_PM_MRK_L1_RELOAD_VALID ] = { 284, 285, 279, 282, -1, -1 },
+ [ POWER5p_PME_PM_L3SB_HIT ] = { 185, 182, 181, 180, -1, -1 },
+ [ POWER5p_PME_PM_L2SB_SHR_MOD ] = { 157, 154, 153, 152, -1, -1 },
+ [ POWER5p_PME_PM_EE_OFF_EXT_INT ] = { 36, 35, 35, 36, -1, -1 },
+ [ POWER5p_PME_PM_1PLUS_PPC_CMPL ] = { 2, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_L2SC_SHR_MOD ] = { 173, 170, 169, 168, -1, -1 },
+ [ POWER5p_PME_PM_PMC6_OVERFLOW ] = { -1, -1, 297, -1, -1, -1 },
+ [ POWER5p_PME_PM_IC_PREF_INSTALL ] = { 252, 251, 108, 108, -1, -1 },
+ [ POWER5p_PME_PM_LSU_LRQ_FULL_CYC ] = { 241, 239, 237, 235, -1, -1 },
+ [ POWER5p_PME_PM_TLB_MISS ] = { 356, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_GCT_FULL_CYC ] = { 97, 96, 94, 97, -1, -1 },
+ [ POWER5p_PME_PM_FXU_BUSY ] = { -1, 93, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L3_CYC ] = { -1, 276, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_LSU_REJECT_LMQ_FULL ] = { -1, 242, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_LSU_SRQ_S0_ALLOC ] = { 247, 245, 242, 241, -1, -1 },
+ [ POWER5p_PME_PM_GRP_MRK ] = { 109, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_INST_FROM_L25_SHR ] = { 119, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_DC_PREF_STREAM_ALLOC ] = { 29, 28, 28, 29, -1, -1 },
+ [ POWER5p_PME_PM_FPU1_FIN ] = { 76, 75, 75, 77, -1, -1 },
+ [ POWER5p_PME_PM_BR_MPRED_TA ] = { 11, 10, 10, 11, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DTLB_REF_64K ] = { -1, 282, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_RUN_INST_CMPL ] = { -1, -1, -1, -1, 0, -1 },
+ [ POWER5p_PME_PM_CRQ_FULL_CYC ] = { 15, 18, 14, 19, -1, -1 },
+ [ POWER5p_PME_PM_L2SA_RCLD_DISP ] = { 130, 127, 126, 125, -1, -1 },
+ [ POWER5p_PME_PM_SNOOP_WR_RETRY_QFULL ] = { 322, 317, 315, 313, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DTLB_REF_4K ] = { 280, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_LSU_SRQ_S0_VALID ] = { 248, 246, 243, 242, -1, -1 },
+ [ POWER5p_PME_PM_LSU0_FLUSH_LRQ ] = { 207, 203, 203, 202, -1, -1 },
+ [ POWER5p_PME_PM_INST_FROM_L275_MOD ] = { -1, -1, -1, 115, -1, -1 },
+ [ POWER5p_PME_PM_GCT_EMPTY_CYC ] = { -1, 95, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_LARX_LSU0 ] = { 198, 195, 194, 193, -1, -1 },
+ [ POWER5p_PME_PM_THRD_PRIO_DIFF_5or6_CYC ] = { 344, 339, 337, 333, -1, -1 },
+ [ POWER5p_PME_PM_SNOOP_RETRY_1AHEAD ] = { 320, 315, 313, 311, -1, -1 },
+ [ POWER5p_PME_PM_FPU1_FSQRT ] = { 80, 79, 79, 81, -1, -1 },
+ [ POWER5p_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { 287, 287, 281, 284, -1, -1 },
+ [ POWER5p_PME_PM_MRK_FPU_FIN ] = { -1, -1, 276, -1, -1, -1 },
+ [ POWER5p_PME_PM_THRD_PRIO_5_CYC ] = { 338, 333, 331, 327, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_LMEM ] = { -1, 277, 270, -1, -1, -1 },
+ [ POWER5p_PME_PM_SNOOP_TLBIE ] = { 321, 316, 314, 312, -1, -1 },
+ [ POWER5p_PME_PM_FPU1_FRSP_FCONV ] = { 79, 78, 78, 80, -1, -1 },
+ [ POWER5p_PME_PM_DTLB_MISS_16G ] = { -1, -1, -1, 32, -1, -1 },
+ [ POWER5p_PME_PM_L3SB_SNOOP_RETRY ] = { 190, 187, 186, 185, -1, -1 },
+ [ POWER5p_PME_PM_FAB_VBYPASS_EMPTY ] = { 51, 50, 50, 52, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD ] = { 271, -1, -1, 265, -1, -1 },
+ [ POWER5p_PME_PM_L2SB_RCST_DISP ] = { 150, 147, 146, 145, -1, -1 },
+ [ POWER5p_PME_PM_6INST_CLB_CYC ] = { 7, 6, 6, 7, -1, -1 },
+ [ POWER5p_PME_PM_FLUSH ] = { 52, 51, 51, 53, -1, -1 },
+ [ POWER5p_PME_PM_L2SC_MOD_INV ] = { 160, 157, 156, 155, -1, -1 },
+ [ POWER5p_PME_PM_FPU_DENORM ] = { 86, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_L3SC_HIT ] = { 192, 189, 188, 187, -1, -1 },
+ [ POWER5p_PME_PM_SNOOP_WR_RETRY_RQ ] = { 323, 318, 316, 314, -1, -1 },
+ [ POWER5p_PME_PM_LSU1_REJECT_SRQ ] = { 229, 225, 225, 224, -1, -1 },
+ [ POWER5p_PME_PM_L3SC_ALL_BUSY ] = { 191, 188, 187, 186, -1, -1 },
+ [ POWER5p_PME_PM_IC_PREF_REQ ] = { 112, 110, 109, 109, -1, -1 },
+ [ POWER5p_PME_PM_MRK_GRP_IC_MISS ] = { -1, -1, -1, 279, -1, -1 },
+ [ POWER5p_PME_PM_GCT_NOSLOT_IC_MISS ] = { -1, 97, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L3 ] = { 272, -1, 267, -1, -1, -1 },
+ [ POWER5p_PME_PM_GCT_NOSLOT_SRQ_FULL ] = { -1, -1, 95, -1, -1, -1 },
+ [ POWER5p_PME_PM_CMPLU_STALL_DCACHE_MISS ] = { -1, 14, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_THRD_SEL_OVER_ISU_HOLD ] = { 350, 345, 343, 339, -1, -1 },
+ [ POWER5p_PME_PM_LSU_FLUSH_LRQ ] = { -1, 230, 229, -1, -1, -1 },
+ [ POWER5p_PME_PM_THRD_PRIO_2_CYC ] = { 335, 330, 328, 324, -1, -1 },
+ [ POWER5p_PME_PM_L3SA_MOD_INV ] = { 179, 176, 175, 174, -1, -1 },
+ [ POWER5p_PME_PM_LSU_FLUSH_SRQ ] = { 233, -1, -1, 228, -1, -1 },
+ [ POWER5p_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { 297, 297, 292, 296, -1, -1 },
+ [ POWER5p_PME_PM_L3SA_REF ] = { 181, 178, 177, 176, -1, -1 },
+ [ POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL ] = { 171, 168, 167, 166, -1, -1 },
+ [ POWER5p_PME_PM_FPU0_STALL3 ] = { 70, 69, 69, 71, -1, -1 },
+ [ POWER5p_PME_PM_TB_BIT_TRANS ] = { 331, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_GPR_MAP_FULL_CYC ] = { 100, 99, 97, 99, -1, -1 },
+ [ POWER5p_PME_PM_MRK_LSU_FLUSH_LRQ ] = { -1, -1, 290, -1, -1, -1 },
+ [ POWER5p_PME_PM_FPU0_STF ] = { 71, 70, 70, 72, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DTLB_MISS ] = { 277, 279, 272, 274, -1, -1 },
+ [ POWER5p_PME_PM_FPU1_FMA ] = { 77, 76, 76, 78, -1, -1 },
+ [ POWER5p_PME_PM_L2SA_MOD_TAG ] = { 129, 126, 125, 124, -1, -1 },
+ [ POWER5p_PME_PM_LSU1_FLUSH_ULD ] = { 222, 218, 218, 217, -1, -1 },
+ [ POWER5p_PME_PM_MRK_INST_FIN ] = { -1, -1, 278, -1, -1, -1 },
+ [ POWER5p_PME_PM_MRK_LSU0_FLUSH_UST ] = { 291, 291, 285, 288, -1, -1 },
+ [ POWER5p_PME_PM_FPU0_FULL_CYC ] = { 68, 67, 67, 69, -1, -1 },
+ [ POWER5p_PME_PM_LSU_LRQ_S0_ALLOC ] = { 242, 240, 238, 236, -1, -1 },
+ [ POWER5p_PME_PM_MRK_LSU1_FLUSH_ULD ] = { 294, 294, 288, 291, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DTLB_REF ] = { 279, 281, 274, 276, -1, -1 },
+ [ POWER5p_PME_PM_BR_UNCOND ] = { 12, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_THRD_SEL_OVER_L2MISS ] = { 351, 346, 344, 340, -1, -1 },
+ [ POWER5p_PME_PM_L2SB_SHR_INV ] = { 156, 153, 152, 151, -1, -1 },
+ [ POWER5p_PME_PM_MEM_LO_PRIO_WR_CMPL ] = { 255, 254, 250, 249, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DTLB_MISS_64K ] = { -1, 280, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_MRK_ST_MISS_L1 ] = { 300, 300, 295, 298, -1, -1 },
+ [ POWER5p_PME_PM_L3SC_MOD_TAG ] = { 194, 191, 190, 189, -1, -1 },
+ [ POWER5p_PME_PM_GRP_DISP_SUCCESS ] = { -1, -1, 103, -1, -1, -1 },
+ [ POWER5p_PME_PM_THRD_PRIO_DIFF_1or2_CYC ] = { 342, 337, 335, 331, -1, -1 },
+ [ POWER5p_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { 110, 108, 106, 106, -1, -1 },
+ [ POWER5p_PME_PM_LSU_DERAT_MISS ] = { -1, 228, 227, -1, -1, -1 },
+ [ POWER5p_PME_PM_MEM_WQ_DISP_Q8to15 ] = { 266, 265, 261, 260, -1, -1 },
+ [ POWER5p_PME_PM_FPU0_SINGLE ] = { 69, 68, 68, 70, -1, -1 },
+ [ POWER5p_PME_PM_THRD_PRIO_1_CYC ] = { 334, 329, 327, 323, -1, -1 },
+ [ POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_OTHER ] = { 168, 165, 164, 163, -1, -1 },
+ [ POWER5p_PME_PM_SNOOP_RD_RETRY_RQ ] = { 318, 313, 311, 309, -1, -1 },
+ [ POWER5p_PME_PM_FAB_HOLDtoVN_EMPTY ] = { 42, 41, 41, 43, -1, -1 },
+ [ POWER5p_PME_PM_FPU1_FEST ] = { 75, 74, 74, 76, -1, -1 },
+ [ POWER5p_PME_PM_SNOOP_DCLAIM_RETRY_QFULL ] = { 313, 308, 306, 304, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR_CYC ] = { -1, 270, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_MRK_ST_CMPL_INT ] = { -1, -1, 294, -1, -1, -1 },
+ [ POWER5p_PME_PM_FLUSH_BR_MPRED ] = { 53, 52, 52, 54, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DTLB_MISS_16G ] = { -1, -1, -1, 275, -1, -1 },
+ [ POWER5p_PME_PM_FPU_STF ] = { -1, 88, 87, -1, -1, -1 },
+ [ POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR ] = { 147, 144, 143, 142, -1, -1 },
+ [ POWER5p_PME_PM_CMPLU_STALL_FPU ] = { -1, -1, -1, 17, -1, -1 },
+ [ POWER5p_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC ] = { 345, 340, 338, 334, -1, -1 },
+ [ POWER5p_PME_PM_GCT_NOSLOT_CYC ] = { 98, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { -1, -1, 90, -1, -1, -1 },
+ [ POWER5p_PME_PM_PTEG_FROM_L35_SHR ] = { 308, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DTLB_REF_16G ] = { -1, -1, -1, 277, -1, -1 },
+ [ POWER5p_PME_PM_MRK_LSU_FLUSH_UST ] = { -1, 296, 291, -1, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR ] = { 270, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_L3SA_HIT ] = { 178, 175, 174, 173, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR ] = { 273, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_ADDR ] = { 151, 148, 147, 146, -1, -1 },
+ [ POWER5p_PME_PM_IERAT_XLATE_WR ] = { 113, 111, 110, 110, -1, -1 },
+ [ POWER5p_PME_PM_L2SA_ST_REQ ] = { 143, 140, 139, 138, -1, -1 },
+ [ POWER5p_PME_PM_INST_FROM_LMEM ] = { -1, 119, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_THRD_SEL_T1 ] = { 353, 348, 346, 342, -1, -1 },
+ [ POWER5p_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { 111, 109, 107, 107, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR_CYC ] = { -1, 274, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_FPU0_1FLOP ] = { 58, 57, 57, 59, -1, -1 },
+ [ POWER5p_PME_PM_PTEG_FROM_L2 ] = { 304, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_MEM_PW_CMPL ] = { 258, 257, 253, 252, -1, -1 },
+ [ POWER5p_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC ] = { 347, 342, 340, 336, -1, -1 },
+ [ POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER ] = { 148, 145, 144, 143, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DTLB_MISS_4K ] = { 278, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_FPU0_FIN ] = { 62, 61, 61, 63, -1, -1 },
+ [ POWER5p_PME_PM_L3SC_SHR_INV ] = { 196, 193, 192, 191, -1, -1 },
+ [ POWER5p_PME_PM_GRP_BR_REDIR ] = { 101, 100, 98, 100, -1, -1 },
+ [ POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL ] = { 165, 162, 161, 160, -1, -1 },
+ [ POWER5p_PME_PM_MRK_LSU_FLUSH_SRQ ] = { -1, -1, -1, 294, -1, -1 },
+ [ POWER5p_PME_PM_PTEG_FROM_L275_SHR ] = { -1, -1, 299, -1, -1, -1 },
+ [ POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL ] = { 149, 146, 145, 144, -1, -1 },
+ [ POWER5p_PME_PM_SNOOP_RD_RETRY_WQ ] = { 319, 314, 312, 310, -1, -1 },
+ [ POWER5p_PME_PM_FAB_DCLAIM_RETRIED ] = { 40, 39, 39, 41, -1, -1 },
+ [ POWER5p_PME_PM_LSU0_NCLD ] = { 212, 208, 208, 207, -1, -1 },
+ [ POWER5p_PME_PM_LSU1_BUSY_REJECT ] = { 218, 214, 214, 213, -1, -1 },
+ [ POWER5p_PME_PM_FXLS0_FULL_CYC ] = { 91, 89, 88, 91, -1, -1 },
+ [ POWER5p_PME_PM_DTLB_REF_16M ] = { -1, -1, 33, -1, -1, -1 },
+ [ POWER5p_PME_PM_FPU0_FEST ] = { 61, 60, 60, 62, -1, -1 },
+ [ POWER5p_PME_PM_GCT_USAGE_60to79_CYC ] = { -1, 98, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_DATA_FROM_L25_MOD ] = { -1, 21, 17, -1, -1, -1 },
+ [ POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR ] = { 163, 160, 159, 158, -1, -1 },
+ [ POWER5p_PME_PM_LSU0_REJECT_ERAT_MISS ] = { 213, 209, 209, 208, -1, -1 },
+ [ POWER5p_PME_PM_DATA_FROM_L375_MOD ] = { 23, -1, -1, 23, -1, -1 },
+ [ POWER5p_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { -1, 238, 236, -1, -1, -1 },
+ [ POWER5p_PME_PM_DTLB_MISS_64K ] = { -1, 31, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_LSU0_REJECT_RELOAD_CDF ] = { 215, 211, 211, 210, -1, -1 },
+ [ POWER5p_PME_PM_0INST_FETCH ] = { -1, -1, -1, 1, -1, -1 },
+ [ POWER5p_PME_PM_LSU1_REJECT_RELOAD_CDF ] = { 228, 224, 224, 223, -1, -1 },
+ [ POWER5p_PME_PM_MEM_WQ_DISP_Q0to7 ] = { 265, 264, 260, 259, -1, -1 },
+ [ POWER5p_PME_PM_L1_PREF ] = { 126, 123, 122, 121, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = { -1, -1, -1, 270, -1, -1 },
+ [ POWER5p_PME_PM_BRQ_FULL_CYC ] = { 8, 7, 7, 8, -1, -1 },
+ [ POWER5p_PME_PM_GRP_IC_MISS_NONSPEC ] = { 108, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_PTEG_FROM_L275_MOD ] = { 306, -1, -1, 300, -1, -1 },
+ [ POWER5p_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { 286, 286, 280, 283, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR_CYC ] = { -1, 275, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_DATA_FROM_L3 ] = { 21, -1, 20, -1, -1, -1 },
+ [ POWER5p_PME_PM_INST_FROM_L2 ] = { 118, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_LSU_FLUSH ] = { 231, 229, 228, 226, -1, -1 },
+ [ POWER5p_PME_PM_PMC2_OVERFLOW ] = { -1, -1, 296, -1, -1, -1 },
+ [ POWER5p_PME_PM_FPU0_DENORM ] = { 59, 58, 58, 60, -1, -1 },
+ [ POWER5p_PME_PM_FPU1_FMOV_FEST ] = { 78, 77, 77, 79, -1, -1 },
+ [ POWER5p_PME_PM_INST_FETCH_CYC ] = { 117, 115, 114, 114, -1, -1 },
+ [ POWER5p_PME_PM_INST_DISP ] = { -1, -1, 113, 113, -1, -1 },
+ [ POWER5p_PME_PM_LSU_LDF ] = { 236, -1, -1, 230, -1, -1 },
+ [ POWER5p_PME_PM_DATA_FROM_L25_SHR ] = { 19, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_L1_DCACHE_RELOAD_VALID ] = { 125, 122, 121, 120, -1, -1 },
+ [ POWER5p_PME_PM_MEM_WQ_DISP_DCLAIM ] = { 267, 266, 262, 261, -1, -1 },
+ [ POWER5p_PME_PM_MRK_GRP_ISSUED ] = { 282, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_FPU_FULL_CYC ] = { 89, -1, -1, 89, -1, -1 },
+ [ POWER5p_PME_PM_INST_FROM_L35_MOD ] = { -1, 118, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_FPU_FMA ] = { -1, 84, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_THRD_PRIO_3_CYC ] = { 336, 331, 329, 325, -1, -1 },
+ [ POWER5p_PME_PM_MRK_CRU_FIN ] = { -1, -1, -1, 263, -1, -1 },
+ [ POWER5p_PME_PM_SNOOP_WR_RETRY_WQ ] = { 324, 319, 317, 315, -1, -1 },
+ [ POWER5p_PME_PM_CMPLU_STALL_REJECT ] = { -1, -1, -1, 18, -1, -1 },
+ [ POWER5p_PME_PM_MRK_FXU_FIN ] = { -1, 94, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_LSU1_REJECT_ERAT_MISS ] = { 226, 222, 222, 221, -1, -1 },
+ [ POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_OTHER ] = { 152, 149, 148, 147, -1, -1 },
+ [ POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY ] = { 170, 167, 166, 165, -1, -1 },
+ [ POWER5p_PME_PM_PMC4_OVERFLOW ] = { 301, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_L3SA_SNOOP_RETRY ] = { 183, 180, 179, 178, -1, -1 },
+ [ POWER5p_PME_PM_PTEG_FROM_L35_MOD ] = { -1, 304, 302, -1, -1, -1 },
+ [ POWER5p_PME_PM_INST_FROM_L25_MOD ] = { -1, 117, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_THRD_SMT_HANG ] = { 354, 349, 347, 343, -1, -1 },
+ [ POWER5p_PME_PM_CMPLU_STALL_ERAT_MISS ] = { -1, -1, -1, 16, -1, -1 },
+ [ POWER5p_PME_PM_L3SA_MOD_TAG ] = { 180, 177, 176, 175, -1, -1 },
+ [ POWER5p_PME_PM_INST_FROM_L2MISS ] = { 120, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_FLUSH_SYNC ] = { 56, 55, 55, 57, -1, -1 },
+ [ POWER5p_PME_PM_MRK_GRP_DISP ] = { 281, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_MEM_RQ_DISP_Q8to11 ] = { 263, 261, 247, 349, -1, -1 },
+ [ POWER5p_PME_PM_L2SC_ST_HIT ] = { 174, 171, 170, 169, -1, -1 },
+ [ POWER5p_PME_PM_L2SB_MOD_TAG ] = { 145, 142, 141, 140, -1, -1 },
+ [ POWER5p_PME_PM_CLB_EMPTY_CYC ] = { 13, 12, 12, 13, -1, -1 },
+ [ POWER5p_PME_PM_L2SB_ST_HIT ] = { 158, 155, 154, 153, -1, -1 },
+ [ POWER5p_PME_PM_MEM_NONSPEC_RD_CANCEL ] = { 254, 253, 249, 351, -1, -1 },
+ [ POWER5p_PME_PM_BR_PRED_CR_TA ] = { -1, -1, -1, 12, -1, -1 },
+ [ POWER5p_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { 289, 289, 283, 286, -1, -1 },
+ [ POWER5p_PME_PM_MRK_LSU_FLUSH_ULD ] = { 296, -1, -1, 295, -1, -1 },
+ [ POWER5p_PME_PM_INST_DISP_ATTEMPT ] = { 116, 114, 354, 254, -1, -1 },
+ [ POWER5p_PME_PM_INST_FROM_RMEM ] = { -1, -1, -1, 117, -1, -1 },
+ [ POWER5p_PME_PM_ST_REF_L1_LSU0 ] = { 328, 324, 323, 319, -1, -1 },
+ [ POWER5p_PME_PM_LSU0_DERAT_MISS ] = { 206, 202, 202, 201, -1, -1 },
+ [ POWER5p_PME_PM_FPU_STALL3 ] = { -1, 87, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_L2SB_RCLD_DISP ] = { 146, 143, 142, 141, -1, -1 },
+ [ POWER5p_PME_PM_BR_PRED_CR ] = { 358, 352, 11, 347, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L2 ] = { 269, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_LSU0_FLUSH_SRQ ] = { 208, 204, 204, 203, -1, -1 },
+ [ POWER5p_PME_PM_FAB_PNtoNN_DIRECT ] = { 47, 46, 46, 48, -1, -1 },
+ [ POWER5p_PME_PM_IOPS_CMPL ] = { 115, 113, 112, 112, -1, -1 },
+ [ POWER5p_PME_PM_L2SA_RCST_DISP ] = { 134, 131, 130, 129, -1, -1 },
+ [ POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_OTHER ] = { 136, 133, 132, 131, -1, -1 },
+ [ POWER5p_PME_PM_L2SC_SHR_INV ] = { 172, 169, 168, 167, -1, -1 },
+ [ POWER5p_PME_PM_SNOOP_RETRY_AB_COLLISION ] = { 361, 355, 353, 350, -1, -1 },
+ [ POWER5p_PME_PM_FAB_PNtoVN_SIDECAR ] = { 50, 49, 49, 51, -1, -1 },
+ [ POWER5p_PME_PM_LSU0_REJECT_LMQ_FULL ] = { 214, 210, 210, 209, -1, -1 },
+ [ POWER5p_PME_PM_LSU_LMQ_S0_ALLOC ] = { 239, 236, 234, 233, -1, -1 },
+ [ POWER5p_PME_PM_SNOOP_PW_RETRY_RQ ] = { 315, 310, 308, 306, -1, -1 },
+ [ POWER5p_PME_PM_DTLB_REF ] = { 33, 32, 32, 33, -1, -1 },
+ [ POWER5p_PME_PM_PTEG_FROM_L3 ] = { 307, -1, 301, -1, -1, -1 },
+ [ POWER5p_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY ] = { 44, 43, 43, 45, -1, -1 },
+ [ POWER5p_PME_PM_LSU_SRQ_EMPTY_CYC ] = { -1, -1, -1, 239, -1, -1 },
+ [ POWER5p_PME_PM_FPU1_STF ] = { 84, 83, 83, 85, -1, -1 },
+ [ POWER5p_PME_PM_LSU_LMQ_S0_VALID ] = { 240, 237, 235, 234, -1, -1 },
+ [ POWER5p_PME_PM_GCT_USAGE_00to59_CYC ] = { 99, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_FPU_FMOV_FEST ] = { -1, -1, 84, -1, -1, -1 },
+ [ POWER5p_PME_PM_DATA_FROM_L2MISS ] = { -1, -1, 19, -1, -1, -1 },
+ [ POWER5p_PME_PM_XER_MAP_FULL_CYC ] = { 357, 351, 350, 346, -1, -1 },
+ [ POWER5p_PME_PM_GRP_DISP_BLK_SB_CYC ] = { 103, 103, 101, 102, -1, -1 },
+ [ POWER5p_PME_PM_FLUSH_SB ] = { 55, 54, 54, 56, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR ] = { -1, -1, 269, -1, -1, -1 },
+ [ POWER5p_PME_PM_MRK_GRP_CMPL ] = { -1, -1, -1, 278, -1, -1 },
+ [ POWER5p_PME_PM_SUSPENDED ] = { 330, 326, 325, 321, -1, -1 },
+ [ POWER5p_PME_PM_SNOOP_RD_RETRY_QFULL ] = { 317, 312, 310, 308, -1, -1 },
+ [ POWER5p_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC ] = { 107, 101, 99, 101, -1, -1 },
+ [ POWER5p_PME_PM_DATA_FROM_L35_SHR ] = { 22, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_L3SB_MOD_INV ] = { 186, 183, 182, 181, -1, -1 },
+ [ POWER5p_PME_PM_STCX_FAIL ] = { 325, 320, 318, 316, -1, -1 },
+ [ POWER5p_PME_PM_LD_MISS_L1_LSU1 ] = { 200, 199, 199, 198, -1, -1 },
+ [ POWER5p_PME_PM_GRP_DISP ] = { -1, 102, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_DC_PREF_DST ] = { 28, 27, 27, 28, -1, -1 },
+ [ POWER5p_PME_PM_FPU1_DENORM ] = { 73, 72, 72, 74, -1, -1 },
+ [ POWER5p_PME_PM_FPU0_FPSCR ] = { 65, 64, 64, 66, -1, -1 },
+ [ POWER5p_PME_PM_DATA_FROM_L2 ] = { 18, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR ] = { 131, 128, 127, 126, -1, -1 },
+ [ POWER5p_PME_PM_FPU_1FLOP ] = { 85, -1, -1, 86, -1, -1 },
+ [ POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER ] = { 164, 161, 160, 159, -1, -1 },
+ [ POWER5p_PME_PM_FPU0_FSQRT ] = { 67, 66, 66, 68, -1, -1 },
+ [ POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL ] = { 169, 166, 165, 164, -1, -1 },
+ [ POWER5p_PME_PM_LD_REF_L1 ] = { 201, -1, -1, 196, -1, -1 },
+ [ POWER5p_PME_PM_INST_FROM_L1 ] = { -1, 116, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_TLBIE_HELD ] = { 355, 350, 349, 344, -1, -1 },
+ [ POWER5p_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { 27, 26, 26, 27, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD_CYC ] = { -1, -1, -1, 264, -1, -1 },
+ [ POWER5p_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { 293, 293, 287, 290, -1, -1 },
+ [ POWER5p_PME_PM_MEM_RQ_DISP_Q0to3 ] = { 260, 256, 257, 256, -1, -1 },
+ [ POWER5p_PME_PM_ST_REF_L1_LSU1 ] = { 329, 325, 324, 320, -1, -1 },
+ [ POWER5p_PME_PM_MRK_LD_MISS_L1 ] = { 285, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_L1_WRITE_CYC ] = { 127, 124, 123, 122, -1, -1 },
+ [ POWER5p_PME_PM_L2SC_ST_REQ ] = { 175, 172, 171, 170, -1, -1 },
+ [ POWER5p_PME_PM_CMPLU_STALL_FDIV ] = { -1, 15, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_THRD_SEL_OVER_CLB_EMPTY ] = { 348, 343, 341, 337, -1, -1 },
+ [ POWER5p_PME_PM_BR_MPRED_CR ] = { 10, 9, 9, 10, -1, -1 },
+ [ POWER5p_PME_PM_L3SB_MOD_TAG ] = { 187, 184, 183, 182, -1, -1 },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L2MISS ] = { -1, -1, 266, -1, -1, -1 },
+ [ POWER5p_PME_PM_LSU_REJECT_SRQ ] = { 245, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_LD_MISS_L1 ] = { -1, -1, 195, -1, -1, -1 },
+ [ POWER5p_PME_PM_INST_FROM_PREF ] = { -1, -1, 118, -1, -1, -1 },
+ [ POWER5p_PME_PM_STCX_PASS ] = { 326, 321, 319, 317, -1, -1 },
+ [ POWER5p_PME_PM_DC_INV_L2 ] = { 26, 25, 25, 26, -1, -1 },
+ [ POWER5p_PME_PM_LSU_SRQ_FULL_CYC ] = { 246, 244, 241, 240, -1, -1 },
+ [ POWER5p_PME_PM_FPU_FIN ] = { -1, -1, -1, 88, -1, -1 },
+ [ POWER5p_PME_PM_LSU_SRQ_STFWD ] = { -1, 247, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_L2SA_SHR_MOD ] = { 141, 138, 137, 136, -1, -1 },
+ [ POWER5p_PME_PM_0INST_CLB_CYC ] = { 0, 0, 0, 0, -1, -1 },
+ [ POWER5p_PME_PM_FXU0_FIN ] = { 94, 91, 91, 94, -1, -1 },
+ [ POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL ] = { 153, 150, 149, 148, -1, -1 },
+ [ POWER5p_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = { -1, 327, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_PMC5_OVERFLOW ] = { 302, -1, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_FPU0_FDIV ] = { 60, 59, 59, 61, -1, -1 },
+ [ POWER5p_PME_PM_PTEG_FROM_L375_SHR ] = { -1, -1, 303, -1, -1, -1 },
+ [ POWER5p_PME_PM_HV_CYC ] = { -1, 107, -1, -1, -1, -1 },
+ [ POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY ] = { 138, 135, 134, 133, -1, -1 },
+ [ POWER5p_PME_PM_THRD_PRIO_DIFF_0_CYC ] = { 341, 336, 334, 330, -1, -1 },
+ [ POWER5p_PME_PM_LR_CTR_MAP_FULL_CYC ] = { 204, 200, 200, 199, -1, -1 },
+ [ POWER5p_PME_PM_L3SB_SHR_INV ] = { 189, 186, 185, 184, -1, -1 },
+ [ POWER5p_PME_PM_DATA_FROM_RMEM ] = { 24, -1, -1, 24, -1, -1 },
+ [ POWER5p_PME_PM_DATA_FROM_L275_MOD ] = { 20, -1, -1, 22, -1, -1 },
+ [ POWER5p_PME_PM_LSU0_REJECT_SRQ ] = { 216, 212, 212, 211, -1, -1 },
+ [ POWER5p_PME_PM_LSU1_DERAT_MISS ] = { 219, 215, 215, 214, -1, -1 },
+ [ POWER5p_PME_PM_MRK_LSU_FIN ] = { -1, -1, -1, 293, -1, -1 },
+ [ POWER5p_PME_PM_DTLB_MISS_16M ] = { -1, -1, 31, -1, -1, -1 },
+ [ POWER5p_PME_PM_LSU0_FLUSH_UST ] = { 210, 206, 206, 205, -1, -1 },
+ [ POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY ] = { 154, 151, 150, 149, -1, -1 },
+ [ POWER5p_PME_PM_L2SC_MOD_TAG ] = { 161, 158, 157, 156, -1, -1 }
+};
+
+static const unsigned long long power5p_group_vecs[][POWER5p_NUM_GROUP_VEC] = {
+ [ POWER5p_PME_PM_LSU_REJECT_RELOAD_CDF ] = {
+ 0x0000000000080000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU1_SINGLE ] = {
+ 0x0000000000000000ULL,
+ 0x0000000002000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L3SB_REF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000008000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_THRD_PRIO_DIFF_3or4_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_INST_FROM_L275_SHR ] = {
+ 0x0200000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x2000000000000000ULL,
+ 0x0080000000000000ULL
+ },
+ [ POWER5p_PME_PM_DTLB_MISS_4K ] = {
+ 0x0001000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_CLB_FULL_CYC ] = {
+ 0x0000000000001000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_ST_CMPL ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000100000000008ULL
+ },
+ [ POWER5p_PME_PM_LSU_FLUSH_LRQ_FULL ] = {
+ 0x0000000010000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR ] = {
+ 0x0000000000000000ULL,
+ 0x0400000000000000ULL,
+ 0x0000000800000000ULL
+ },
+ [ POWER5p_PME_PM_1INST_CLB_CYC ] = {
+ 0x0000000000002000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MEM_SPEC_RD_CANCEL ] = {
+ 0x0000000000000000ULL,
+ 0x0001000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DTLB_MISS_16M ] = {
+ 0x0000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x0000028000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU_FDIV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000020000ULL,
+ 0x0000000000410000ULL
+ },
+ [ POWER5p_PME_PM_FPU_SINGLE ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000100000ULL,
+ 0x0000000000008000ULL
+ },
+ [ POWER5p_PME_PM_FPU0_FMA ] = {
+ 0x0000000000000000ULL,
+ 0x0000000004000000ULL,
+ 0x0000000000001000ULL
+ },
+ [ POWER5p_PME_PM_SLB_MISS ] = {
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU1_FLUSH_LRQ ] = {
+ 0x0000000000800000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SA_ST_HIT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000002ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_DTLB_MISS ] = {
+ 0x0002100000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000004000080ULL
+ },
+ [ POWER5p_PME_PM_BR_PRED_TA ] = {
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000400ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x2000000000000000ULL,
+ 0x0000004000000000ULL
+ },
+ [ POWER5p_PME_PM_CMPLU_STALL_FXU ] = {
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_EXT_INT ] = {
+ 0x0000000000000000ULL,
+ 0x0002000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_LSU1_FLUSH_LRQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0020000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_ST_GPS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000200000000010ULL
+ },
+ [ POWER5p_PME_PM_LSU1_LDF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000002000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FAB_CMD_ISSUED ] = {
+ 0x0000000000000000ULL,
+ 0x0000010000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU0_SRQ_STFWD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_CR_MAP_FULL_CYC ] = {
+ 0x0000000800000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000001ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_LSU0_FLUSH_ULD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0008000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU_FLUSH_SRQ_FULL ] = {
+ 0x0000000010000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MEM_RQ_DISP_Q16to19 ] = {
+ 0x0000000000000000ULL,
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FLUSH_IMBAL ] = {
+ 0x0000000000108000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000400000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_DATA_FROM_L35_MOD ] = {
+ 0x0040000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MEM_HI_PRIO_WR_CMPL ] = {
+ 0x0000000000000000ULL,
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU1_FDIV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000800000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MEM_RQ_DISP ] = {
+ 0x0000000000000000ULL,
+ 0x0001000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU0_FRSP_FCONV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000800000ULL,
+ 0x0000000000001000ULL
+ },
+ [ POWER5p_PME_PM_LWSYNC_HELD ] = {
+ 0x0000000000020000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FXU_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000040000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_DSLB_MISS ] = {
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_DATA_FROM_L275_SHR ] = {
+ 0x0020000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FXLS1_FULL_CYC ] = {
+ 0x0000000400000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_THRD_SEL_T0 ] = {
+ 0x0000000000000000ULL,
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_PTEG_RELOAD_VALID ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_STCX_FAIL ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0020000000000010ULL
+ },
+ [ POWER5p_PME_PM_LSU_LMQ_LHR_MERGE ] = {
+ 0x0000000000000200ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_2INST_CLB_CYC ] = {
+ 0x0000000000000008ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FAB_PNtoVN_DIRECT ] = {
+ 0x0000000000000000ULL,
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_PTEG_FROM_L2MISS ] = {
+ 0x2000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_CMPLU_STALL_LSU ] = {
+ 0x0000000020000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DSLB_MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000040000000003ULL
+ },
+ [ POWER5p_PME_PM_LSU_FLUSH_ULD ] = {
+ 0x0000000002000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_PTEG_FROM_LMEM ] = {
+ 0x2000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_BRU_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0040000000000000ULL,
+ 0x0090000000000000ULL
+ },
+ [ POWER5p_PME_PM_MEM_WQ_DISP_WRITE ] = {
+ 0x0000000000000000ULL,
+ 0x0004000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x1000000000000000ULL,
+ 0x0000002000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU1_NCLD ] = {
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER ] = {
+ 0x8000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_SNOOP_PW_RETRY_WQ_PWQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU1_FULL_CYC ] = {
+ 0x0000000400000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPR_MAP_FULL_CYC ] = {
+ 0x0000001000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L3SA_ALL_BUSY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000004000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_3INST_CLB_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MEM_PWQ_DISP_Q2or3 ] = {
+ 0x0000000000000000ULL,
+ 0x0008000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SA_SHR_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000800ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_THRESH_TIMEO ] = {
+ 0x0000000000000000ULL,
+ 0x0010000000000000ULL,
+ 0x0000000020000000ULL
+ },
+ [ POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000002ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_THRD_SEL_OVER_GCT_IMBAL ] = {
+ 0x0000000000000000ULL,
+ 0x0000004000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU_FSQRT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000040000ULL,
+ 0x0000000000410000ULL
+ },
+ [ POWER5p_PME_PM_PMC1_OVERFLOW ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_LSU0_FLUSH_LRQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0010000000000000ULL
+ },
+ [ POWER5p_PME_PM_L3SC_SNOOP_RETRY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000010000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_DATA_TABLEWALK_CYC ] = {
+ 0x0000100000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_THRD_PRIO_6_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU_FEST ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000020000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FAB_M1toP1_SIDECAR_EMPTY ] = {
+ 0x0000000000000000ULL,
+ 0x0000080000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_RMEM ] = {
+ 0x0000000000000000ULL,
+ 0x0400000000000000ULL,
+ 0x0000800000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD_CYC ] = {
+ 0x0000000000000008ULL,
+ 0x0200000000000000ULL,
+ 0x0000000400000000ULL
+ },
+ [ POWER5p_PME_PM_MEM_PWQ_DISP ] = {
+ 0x0000000000000000ULL,
+ 0x0008000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FAB_P1toM1_SIDECAR_EMPTY ] = {
+ 0x0000000000000000ULL,
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LD_MISS_L1_LSU0 ] = {
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_SNOOP_PARTIAL_RTRY_QFULL ] = {
+ 0x0000000000000000ULL,
+ 0x0000100000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU1_STALL3 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000001000000ULL,
+ 0x0000000000000800ULL
+ },
+ [ POWER5p_PME_PM_GCT_USAGE_80to99_CYC ] = {
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_WORK_HELD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_INST_CMPL ] = {
+ 0x0000000000000001ULL,
+ 0x0000000000000000ULL,
+ 0x0ffffffff9880000ULL
+ },
+ [ POWER5p_PME_PM_LSU1_FLUSH_UST ] = {
+ 0x0000000008000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FXU_IDLE ] = {
+ 0x0000000000000000ULL,
+ 0x0000000020000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU0_FLUSH_ULD ] = {
+ 0x0000000004000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU1_REJECT_LMQ_FULL ] = {
+ 0x0000000000040000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_GRP_DISP_REJECT ] = {
+ 0x0000000000000004ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_PTEG_FROM_L25_SHR ] = {
+ 0x0800000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SA_MOD_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000800ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FAB_CMD_RETRIED ] = {
+ 0x0000000000000000ULL,
+ 0x0000010000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L3SA_SHR_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000100ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000010ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_ADDR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000001ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL ] = {
+ 0x8000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_PTEG_FROM_L375_MOD ] = {
+ 0x1000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_LSU1_FLUSH_UST ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0004000000000000ULL
+ },
+ [ POWER5p_PME_PM_BR_ISSUED ] = {
+ 0x0000000002040000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000400ULL
+ },
+ [ POWER5p_PME_PM_MRK_GRP_BR_REDIR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000040000000ULL,
+ 0x0800000000000000ULL
+ },
+ [ POWER5p_PME_PM_EE_OFF ] = {
+ 0x0000000000000000ULL,
+ 0x0000080000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_IERAT_XLATE_WR_LP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_DTLB_REF_64K ] = {
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MEM_RQ_DISP_Q4to7 ] = {
+ 0x0000000000000000ULL,
+ 0x0002000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MEM_FAST_PATH_RD_DISP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_INST_FROM_L3 ] = {
+ 0x0080000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_ITLB_MISS ] = {
+ 0x0000000000200000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000080ULL
+ },
+ [ POWER5p_PME_PM_FXU1_BUSY_FXU0_IDLE ] = {
+ 0x0000000000000000ULL,
+ 0x0000000020000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_DTLB_REF_4K ] = {
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FXLS_FULL_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000040000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_GRP_DISP_VALID ] = {
+ 0x0000000000000004ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU_FLUSH_UST ] = {
+ 0x0000000002100000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FXU1_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_THRD_PRIO_4_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0200000000000000ULL,
+ 0x0000000400000000ULL
+ },
+ [ POWER5p_PME_PM_4INST_CLB_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DTLB_REF_16M ] = {
+ 0x0000000000000000ULL,
+ 0x4000000000000000ULL,
+ 0x0000050000000002ULL
+ },
+ [ POWER5p_PME_PM_INST_FROM_L375_MOD ] = {
+ 0x0400000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_GRP_CMPL ] = {
+ 0x0000000000000002ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_ADDR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU1_1FLOP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000008000000ULL,
+ 0x0000000000002000ULL
+ },
+ [ POWER5p_PME_PM_FPU_FRSP_FCONV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000040000ULL,
+ 0x0000000000010000ULL
+ },
+ [ POWER5p_PME_PM_L3SC_REF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000010000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_5INST_CLB_CYC ] = {
+ 0x0000000000000010ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_THRD_L2MISS_BOTH_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000001000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MEM_PW_GATH ] = {
+ 0x0000000000000000ULL,
+ 0x0008000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_DTLB_REF_16G ] = {
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FAB_DCLAIM_ISSUED ] = {
+ 0x0000000000000000ULL,
+ 0x0000010000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FAB_PNtoNN_SIDECAR ] = {
+ 0x0000000000000000ULL,
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_GRP_IC_MISS ] = {
+ 0x0000010000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_INST_FROM_L35_SHR ] = {
+ 0x0400000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU_LMQ_FULL_CYC ] = {
+ 0x0000000200000400ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L2_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0080000000000000ULL,
+ 0x0008000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU_SRQ_SYNC_CYC ] = {
+ 0x0000000000000100ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU0_BUSY_REJECT ] = {
+ 0x0000004000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU_REJECT_ERAT_MISS ] = {
+ 0x0000000000008000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0400000000000000ULL,
+ 0x0000000800000000ULL
+ },
+ [ POWER5p_PME_PM_DATA_FROM_L375_SHR ] = {
+ 0x0040000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_PTEG_FROM_L25_MOD ] = {
+ 0x0800000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU0_FMOV_FEST ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000400000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_THRD_PRIO_7_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU1_FLUSH_SRQ ] = {
+ 0x0000000001000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LD_REF_L1_LSU0 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SC_RCST_DISP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_CMPLU_STALL_DIV ] = {
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MEM_RQ_DISP_Q12to15 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_INST_FROM_L375_SHR ] = {
+ 0x0400000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_ST_REF_L1 ] = {
+ 0x0004200000000000ULL,
+ 0x0000000000000000ULL,
+ 0x00000000092040e0ULL
+ },
+ [ POWER5p_PME_PM_L3SB_ALL_BUSY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000004000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY ] = {
+ 0x0000000000000000ULL,
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x1400000000000000ULL,
+ 0x0000002800000000ULL
+ },
+ [ POWER5p_PME_PM_FAB_HOLDtoNN_EMPTY ] = {
+ 0x0000000000000000ULL,
+ 0x0000080000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_DATA_FROM_LMEM ] = {
+ 0x0018000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000010000140ULL
+ },
+ [ POWER5p_PME_PM_RUN_CYC ] = {
+ 0xffffffffffffffffULL,
+ 0xffffffffffffffffULL,
+ 0x0fffffffffffffffULL
+ },
+ [ POWER5p_PME_PM_PTEG_FROM_RMEM ] = {
+ 0x2000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SC_RCLD_DISP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000020ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU_LRQ_S0_VALID ] = {
+ 0x0000000000000080ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU0_LDF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000012000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_PMC3_OVERFLOW ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_IMR_RELOAD ] = {
+ 0x0000000000000000ULL,
+ 0x0010000000000000ULL,
+ 0x0000400200000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_GRP_TIMEO ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000200000000010ULL
+ },
+ [ POWER5p_PME_PM_ST_MISS_L1 ] = {
+ 0x0004200000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000008100100ULL
+ },
+ [ POWER5p_PME_PM_STOP_COMPLETION ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU_BUSY_REJECT ] = {
+ 0x0000000000002000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_ISLB_MISS ] = {
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_CYC ] = {
+ 0x0002000040000003ULL,
+ 0x0000008000000000ULL,
+ 0x000000001eb40201ULL
+ },
+ [ POWER5p_PME_PM_THRD_ONE_RUN_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000001000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_GRP_BR_REDIR_NONSPEC ] = {
+ 0x0000080000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU1_SRQ_STFWD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L3SC_MOD_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000400ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2_PREF ] = {
+ 0x0000000000006000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000200ULL
+ },
+ [ POWER5p_PME_PM_GCT_NOSLOT_BR_MPRED ] = {
+ 0x0000000000000020ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0080000000000000ULL,
+ 0x0080000100000000ULL
+ },
+ [ POWER5p_PME_PM_L2SB_ST_REQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000010ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SB_MOD_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000001000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_L1_RELOAD_VALID ] = {
+ 0x0000000000000000ULL,
+ 0x0040000000000000ULL,
+ 0x0000000080000000ULL
+ },
+ [ POWER5p_PME_PM_L3SB_HIT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000008000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SB_SHR_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000001000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_EE_OFF_EXT_INT ] = {
+ 0x0000000000000000ULL,
+ 0x0001000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_1PLUS_PPC_CMPL ] = {
+ 0x0000000000000002ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SC_SHR_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000002000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_PMC6_OVERFLOW ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_IC_PREF_INSTALL ] = {
+ 0x0000008000001000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU_LRQ_FULL_CYC ] = {
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_TLB_MISS ] = {
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000200000ULL
+ },
+ [ POWER5p_PME_PM_GCT_FULL_CYC ] = {
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FXU_BUSY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000020000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L3_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0200000000000000ULL,
+ 0x0000000400000000ULL
+ },
+ [ POWER5p_PME_PM_LSU_REJECT_LMQ_FULL ] = {
+ 0x0000000000008000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU_SRQ_S0_ALLOC ] = {
+ 0x0000000000000100ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_GRP_MRK ] = {
+ 0x0000000020000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_INST_FROM_L25_SHR ] = {
+ 0x0200000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_DC_PREF_STREAM_ALLOC ] = {
+ 0x0000000000000800ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU1_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000080000ULL,
+ 0x000000000000a000ULL
+ },
+ [ POWER5p_PME_PM_BR_MPRED_TA ] = {
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DTLB_REF_64K ] = {
+ 0x0000000000000000ULL,
+ 0x4000000000000000ULL,
+ 0x0000010000000000ULL
+ },
+ [ POWER5p_PME_PM_RUN_INST_CMPL ] = {
+ 0xffffffffffffffffULL,
+ 0xffffffffffffffffULL,
+ 0x0fffffffffffffffULL
+ },
+ [ POWER5p_PME_PM_CRQ_FULL_CYC ] = {
+ 0x0000000800000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SA_RCLD_DISP ] = {
+ 0x8000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_SNOOP_WR_RETRY_QFULL ] = {
+ 0x0000000000000000ULL,
+ 0x0000100000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DTLB_REF_4K ] = {
+ 0x0000000000000000ULL,
+ 0x4000000000000000ULL,
+ 0x0002040000000002ULL
+ },
+ [ POWER5p_PME_PM_LSU_SRQ_S0_VALID ] = {
+ 0x0000000000000100ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU0_FLUSH_LRQ ] = {
+ 0x0000000000800000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_INST_FROM_L275_MOD ] = {
+ 0x0200000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_GCT_EMPTY_CYC ] = {
+ 0x0000000000000002ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LARX_LSU0 ] = {
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_THRD_PRIO_DIFF_5or6_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_SNOOP_RETRY_1AHEAD ] = {
+ 0x0000000000000000ULL,
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU1_FSQRT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000200000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_LD_MISS_L1_LSU1 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0040000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_FPU_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0400200000000010ULL
+ },
+ [ POWER5p_PME_PM_THRD_PRIO_5_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000400000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_LMEM ] = {
+ 0x0000000000000000ULL,
+ 0x0800000000000000ULL,
+ 0x0000001000000000ULL
+ },
+ [ POWER5p_PME_PM_SNOOP_TLBIE ] = {
+ 0x0000000000000000ULL,
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU1_FRSP_FCONV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000004800000ULL,
+ 0x0000000000001000ULL
+ },
+ [ POWER5p_PME_PM_DTLB_MISS_16G ] = {
+ 0x0001000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L3SB_SNOOP_RETRY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000004000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FAB_VBYPASS_EMPTY ] = {
+ 0x0000000000000000ULL,
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x1000000000000000ULL,
+ 0x0001000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SB_RCST_DISP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000008ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_6INST_CLB_CYC ] = {
+ 0x0000000000000010ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FLUSH ] = {
+ 0x0008000000080000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SC_MOD_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000002000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU_DENORM ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000080000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L3SC_HIT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000010000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_SNOOP_WR_RETRY_RQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU1_REJECT_SRQ ] = {
+ 0x0000000000004000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L3SC_ALL_BUSY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000010000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_IC_PREF_REQ ] = {
+ 0x0000008000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000200ULL
+ },
+ [ POWER5p_PME_PM_MRK_GRP_IC_MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0040000000000000ULL,
+ 0x0000000080000000ULL
+ },
+ [ POWER5p_PME_PM_GCT_NOSLOT_IC_MISS ] = {
+ 0x0000000000000020ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L3 ] = {
+ 0x0000000000000000ULL,
+ 0x0200000000000000ULL,
+ 0x0000400000000000ULL
+ },
+ [ POWER5p_PME_PM_GCT_NOSLOT_SRQ_FULL ] = {
+ 0x0000000000000020ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_CMPLU_STALL_DCACHE_MISS ] = {
+ 0x0000000040000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_THRD_SEL_OVER_ISU_HOLD ] = {
+ 0x0000000000000000ULL,
+ 0x0000008000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU_FLUSH_LRQ ] = {
+ 0x0000000000400000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_THRD_PRIO_2_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000400000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L3SA_MOD_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000100ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU_FLUSH_SRQ ] = {
+ 0x0000000000400000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_LSU_SRQ_INST_VALID ] = {
+ 0x0000000000000010ULL,
+ 0x0000000000000000ULL,
+ 0x0200000000000000ULL
+ },
+ [ POWER5p_PME_PM_L3SA_REF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000008000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000080ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU0_STALL3 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000001000000ULL,
+ 0x0000000000000800ULL
+ },
+ [ POWER5p_PME_PM_TB_BIT_TRANS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_GPR_MAP_FULL_CYC ] = {
+ 0x0000000800000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_LSU_FLUSH_LRQ ] = {
+ 0x0000000010000000ULL,
+ 0x0000000000000000ULL,
+ 0x0100000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU0_STF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000010000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DTLB_MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000800000000001ULL
+ },
+ [ POWER5p_PME_PM_FPU1_FMA ] = {
+ 0x0000000000000000ULL,
+ 0x0000000004000000ULL,
+ 0x0000000000001000ULL
+ },
+ [ POWER5p_PME_PM_L2SA_MOD_TAG ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000800ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU1_FLUSH_ULD ] = {
+ 0x0000000004000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_INST_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0020000000000000ULL,
+ 0x0800000040000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_LSU0_FLUSH_UST ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0008000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU0_FULL_CYC ] = {
+ 0x0000000400000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU_LRQ_S0_ALLOC ] = {
+ 0x0000000000000080ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_LSU1_FLUSH_ULD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0004000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DTLB_REF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0001000000000001ULL
+ },
+ [ POWER5p_PME_PM_BR_UNCOND ] = {
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000400ULL
+ },
+ [ POWER5p_PME_PM_THRD_SEL_OVER_L2MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0000008000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SB_SHR_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000001000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MEM_LO_PRIO_WR_CMPL ] = {
+ 0x0000000000000000ULL,
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DTLB_MISS_64K ] = {
+ 0x0000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x0000028000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_ST_MISS_L1 ] = {
+ 0x0000000000000000ULL,
+ 0x0020000000000000ULL,
+ 0x0040000000000008ULL
+ },
+ [ POWER5p_PME_PM_L3SC_MOD_TAG ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000400ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_GRP_DISP_SUCCESS ] = {
+ 0x4000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_THRD_PRIO_DIFF_1or2_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = {
+ 0x0000004000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU_DERAT_MISS ] = {
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MEM_WQ_DISP_Q8to15 ] = {
+ 0x0000000000000000ULL,
+ 0x0004000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU0_SINGLE ] = {
+ 0x0000000000000000ULL,
+ 0x0000000002000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_THRD_PRIO_1_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000800000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_OTHER ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_SNOOP_RD_RETRY_RQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FAB_HOLDtoVN_EMPTY ] = {
+ 0x0000000000000000ULL,
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU1_FEST ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000200000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_SNOOP_DCLAIM_RETRY_QFULL ] = {
+ 0x0000000000000000ULL,
+ 0x0000100000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0100000000000000ULL,
+ 0x0000400000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_ST_CMPL_INT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000080000000004ULL
+ },
+ [ POWER5p_PME_PM_FLUSH_BR_MPRED ] = {
+ 0x0000080000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DTLB_MISS_16G ] = {
+ 0x0000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x0000028000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU_STF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000100000ULL,
+ 0x00000000020a8000ULL
+ },
+ [ POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000004ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_CMPLU_STALL_FPU ] = {
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000400000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_GCT_NOSLOT_CYC ] = {
+ 0x0000000000000020ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FXU0_BUSY_FXU1_IDLE ] = {
+ 0x0000000000000000ULL,
+ 0x0000000020000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_PTEG_FROM_L35_SHR ] = {
+ 0x1000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DTLB_REF_16G ] = {
+ 0x0000000000000000ULL,
+ 0x4000000000000000ULL,
+ 0x0000010000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_LSU_FLUSH_UST ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0100100000000008ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR ] = {
+ 0x0000000000000000ULL,
+ 0x0100000000000000ULL,
+ 0x0000000200000000ULL
+ },
+ [ POWER5p_PME_PM_L3SA_HIT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000008000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR ] = {
+ 0x0000000000000000ULL,
+ 0x0800000000000000ULL,
+ 0x0000001000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_ADDR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000008ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_IERAT_XLATE_WR ] = {
+ 0x0000008000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SA_ST_REQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000002ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_INST_FROM_LMEM ] = {
+ 0x0100000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_THRD_SEL_T1 ] = {
+ 0x0000000000000000ULL,
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = {
+ 0x0000004000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0800000000000000ULL,
+ 0x0000800000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU0_1FLOP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000008000000ULL,
+ 0x0000000000002000ULL
+ },
+ [ POWER5p_PME_PM_PTEG_FROM_L2 ] = {
+ 0x2000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MEM_PW_CMPL ] = {
+ 0x0000000000000000ULL,
+ 0x0008000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000800000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000004ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DTLB_MISS_4K ] = {
+ 0x0000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x0005000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU0_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000008080000ULL,
+ 0x000000000000a800ULL
+ },
+ [ POWER5p_PME_PM_L3SC_SHR_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000400ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_GRP_BR_REDIR ] = {
+ 0x0000080000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000020ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_LSU_FLUSH_SRQ ] = {
+ 0x0000000000008000ULL,
+ 0x0000000000000000ULL,
+ 0x0100000000000000ULL
+ },
+ [ POWER5p_PME_PM_PTEG_FROM_L275_SHR ] = {
+ 0x0800000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000004ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_SNOOP_RD_RETRY_WQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FAB_DCLAIM_RETRIED ] = {
+ 0x0000000000000000ULL,
+ 0x0000010000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU0_NCLD ] = {
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU1_BUSY_REJECT ] = {
+ 0x0000004000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FXLS0_FULL_CYC ] = {
+ 0x0000000400000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_DTLB_REF_16M ] = {
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU0_FEST ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000200000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_GCT_USAGE_60to79_CYC ] = {
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_DATA_FROM_L25_MOD ] = {
+ 0x0020000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000020ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU0_REJECT_ERAT_MISS ] = {
+ 0x0000000000020000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_DATA_FROM_L375_MOD ] = {
+ 0x0040000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = {
+ 0x0000000000000600ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_DTLB_MISS_64K ] = {
+ 0x0001000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU0_REJECT_RELOAD_CDF ] = {
+ 0x0000000000010000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_0INST_FETCH ] = {
+ 0x0100008000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU1_REJECT_RELOAD_CDF ] = {
+ 0x0000000000010000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MEM_WQ_DISP_Q0to7 ] = {
+ 0x0000000000000000ULL,
+ 0x0004000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L1_PREF ] = {
+ 0x0000000000001000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000200ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0800000000000000ULL,
+ 0x0000001000000000ULL
+ },
+ [ POWER5p_PME_PM_BRQ_FULL_CYC ] = {
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_GRP_IC_MISS_NONSPEC ] = {
+ 0x0000010000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_PTEG_FROM_L275_MOD ] = {
+ 0x0800000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_LD_MISS_L1_LSU0 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0040000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x2000000000000000ULL,
+ 0x0000004000000000ULL
+ },
+ [ POWER5p_PME_PM_DATA_FROM_L3 ] = {
+ 0x0018000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000140ULL
+ },
+ [ POWER5p_PME_PM_INST_FROM_L2 ] = {
+ 0x0100000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU_FLUSH ] = {
+ 0x000000000dc80000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_PMC2_OVERFLOW ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU0_DENORM ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000400000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU1_FMOV_FEST ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000400000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_INST_FETCH_CYC ] = {
+ 0x0000000000000800ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_INST_DISP ] = {
+ 0x0000000000000005ULL,
+ 0x0000000000000000ULL,
+ 0x0000000001080000ULL
+ },
+ [ POWER5p_PME_PM_LSU_LDF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000100000ULL,
+ 0x0000000000080000ULL
+ },
+ [ POWER5p_PME_PM_DATA_FROM_L25_SHR ] = {
+ 0x0020000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L1_DCACHE_RELOAD_VALID ] = {
+ 0x0000010000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MEM_WQ_DISP_DCLAIM ] = {
+ 0x0000000000000000ULL,
+ 0x0004000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_GRP_ISSUED ] = {
+ 0x0000000000000000ULL,
+ 0x0040000000000000ULL,
+ 0x0000000080000000ULL
+ },
+ [ POWER5p_PME_PM_FPU_FULL_CYC ] = {
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_INST_FROM_L35_MOD ] = {
+ 0x0400000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU_FMA ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000020000ULL,
+ 0x0000000002424000ULL
+ },
+ [ POWER5p_PME_PM_THRD_PRIO_3_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_CRU_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000080000000004ULL
+ },
+ [ POWER5p_PME_PM_SNOOP_WR_RETRY_WQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_CMPLU_STALL_REJECT ] = {
+ 0x0000000020000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_FXU_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0400000000040000ULL
+ },
+ [ POWER5p_PME_PM_LSU1_REJECT_ERAT_MISS ] = {
+ 0x0000000000020000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_OTHER ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000008ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000080ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_PMC4_OVERFLOW ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L3SA_SNOOP_RETRY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000004000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_PTEG_FROM_L35_MOD ] = {
+ 0x1000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_INST_FROM_L25_MOD ] = {
+ 0x0200000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_THRD_SMT_HANG ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_CMPLU_STALL_ERAT_MISS ] = {
+ 0x0000000040000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L3SA_MOD_TAG ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000100ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_INST_FROM_L2MISS ] = {
+ 0x0000000000000800ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FLUSH_SYNC ] = {
+ 0x0000000000200000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_GRP_DISP ] = {
+ 0x0000000000000000ULL,
+ 0x0030000040000000ULL,
+ 0x0000000060000000ULL
+ },
+ [ POWER5p_PME_PM_MEM_RQ_DISP_Q8to11 ] = {
+ 0x0000000000000000ULL,
+ 0x0002000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SC_ST_HIT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000080ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SB_MOD_TAG ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000001000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_CLB_EMPTY_CYC ] = {
+ 0x0000000000000008ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SB_ST_HIT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000010ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MEM_NONSPEC_RD_CANCEL ] = {
+ 0x0000000000000000ULL,
+ 0x0001000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_BR_PRED_CR_TA ] = {
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_LSU0_FLUSH_SRQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0012000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_LSU_FLUSH_ULD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000100000000008ULL
+ },
+ [ POWER5p_PME_PM_INST_DISP_ATTEMPT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000100000ULL
+ },
+ [ POWER5p_PME_PM_INST_FROM_RMEM ] = {
+ 0x0080000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_ST_REF_L1_LSU0 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU0_DERAT_MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU_STALL3 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000080000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SB_RCLD_DISP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000004ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_BR_PRED_CR ] = {
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000400ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L2 ] = {
+ 0x0000000000000000ULL,
+ 0x0080000000000000ULL,
+ 0x0200000100000000ULL
+ },
+ [ POWER5p_PME_PM_LSU0_FLUSH_SRQ ] = {
+ 0x0000000001000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FAB_PNtoNN_DIRECT ] = {
+ 0x0000000000000000ULL,
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_IOPS_CMPL ] = {
+ 0x01080911fff53010ULL,
+ 0x110020f81d100700ULL,
+ 0x0002002000000006ULL
+ },
+ [ POWER5p_PME_PM_L2SA_RCST_DISP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000001ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_OTHER ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000001ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SC_SHR_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000002000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_SNOOP_RETRY_AB_COLLISION ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FAB_PNtoVN_SIDECAR ] = {
+ 0x0000000000000000ULL,
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU0_REJECT_LMQ_FULL ] = {
+ 0x0000000000040000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU_LMQ_S0_ALLOC ] = {
+ 0x0000000000000080ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_SNOOP_PW_RETRY_RQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_DTLB_REF ] = {
+ 0x0002000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_PTEG_FROM_L3 ] = {
+ 0x4000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY ] = {
+ 0x0000000000000000ULL,
+ 0x0000080000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU_SRQ_EMPTY_CYC ] = {
+ 0x0000000000000600ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU1_STF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000010000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU_LMQ_S0_VALID ] = {
+ 0x0000000000000080ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_GCT_USAGE_00to59_CYC ] = {
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU_FMOV_FEST ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000020000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_DATA_FROM_L2MISS ] = {
+ 0x0010000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_XER_MAP_FULL_CYC ] = {
+ 0x0000001000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_GRP_DISP_BLK_SB_CYC ] = {
+ 0x0000000000000004ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FLUSH_SB ] = {
+ 0x0000000000200000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR ] = {
+ 0x0000000000000000ULL,
+ 0x2000000000000000ULL,
+ 0x0000004000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_GRP_CMPL ] = {
+ 0x0000000000000000ULL,
+ 0x0020000000000000ULL,
+ 0x0800000040000000ULL
+ },
+ [ POWER5p_PME_PM_SUSPENDED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_SNOOP_RD_RETRY_QFULL ] = {
+ 0x0000000000000000ULL,
+ 0x0000100000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC ] = {
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_DATA_FROM_L35_SHR ] = {
+ 0x0040000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L3SB_MOD_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000200ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_STCX_FAIL ] = {
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LD_MISS_L1_LSU1 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_GRP_DISP ] = {
+ 0x4000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_DC_PREF_DST ] = {
+ 0x0000000000004000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU1_DENORM ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000400000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU0_FPSCR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000001000000ULL,
+ 0x0000000000000800ULL
+ },
+ [ POWER5p_PME_PM_DATA_FROM_L2 ] = {
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000020ULL
+ },
+ [ POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR ] = {
+ 0x8000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU_1FLOP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000040000ULL,
+ 0x0000000000424000ULL
+ },
+ [ POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000020ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU0_FSQRT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000200000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LD_REF_L1 ] = {
+ 0x0004100000000000ULL,
+ 0x0000000000000000ULL,
+ 0x00000000052040e0ULL
+ },
+ [ POWER5p_PME_PM_INST_FROM_L1 ] = {
+ 0x0080000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000020ULL
+ },
+ [ POWER5p_PME_PM_TLBIE_HELD ] = {
+ 0x0000000000020000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_DC_PREF_OUT_OF_STREAMS ] = {
+ 0x0000000000000800ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0080000000000000ULL,
+ 0x0000000100000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_LSU1_FLUSH_SRQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0020000000000000ULL
+ },
+ [ POWER5p_PME_PM_MEM_RQ_DISP_Q0to3 ] = {
+ 0x0000000000000000ULL,
+ 0x0002000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_ST_REF_L1_LSU1 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_LD_MISS_L1 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000080000000004ULL
+ },
+ [ POWER5p_PME_PM_L1_WRITE_CYC ] = {
+ 0x0000000000010000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SC_ST_REQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000080ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_CMPLU_STALL_FDIV ] = {
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_THRD_SEL_OVER_CLB_EMPTY ] = {
+ 0x0000000000000000ULL,
+ 0x0000004000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_BR_MPRED_CR ] = {
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L3SB_MOD_TAG ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000200ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_DATA_FROM_L2MISS ] = {
+ 0x0000001000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0200000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU_REJECT_SRQ ] = {
+ 0x0000000000080000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LD_MISS_L1 ] = {
+ 0x0004100000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000004900100ULL
+ },
+ [ POWER5p_PME_PM_INST_FROM_PREF ] = {
+ 0x0080000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_STCX_PASS ] = {
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_DC_INV_L2 ] = {
+ 0x4000000000100000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000800000ULL
+ },
+ [ POWER5p_PME_PM_LSU_SRQ_FULL_CYC ] = {
+ 0x0000000000000500ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0100000000040000ULL,
+ 0x0000000202070000ULL
+ },
+ [ POWER5p_PME_PM_LSU_SRQ_STFWD ] = {
+ 0x0000000000000200ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SA_SHR_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000800ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_0INST_CLB_CYC ] = {
+ 0x0000000000000008ULL,
+ 0x0000004000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FXU0_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000008ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000001000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_PMC5_OVERFLOW ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_FPU0_FDIV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000800000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_PTEG_FROM_L375_SHR ] = {
+ 0x1000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_HV_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000800000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000002ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_THRD_PRIO_DIFF_0_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LR_CTR_MAP_FULL_CYC ] = {
+ 0x0000000800000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L3SB_SHR_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000200ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_DATA_FROM_RMEM ] = {
+ 0x0010000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000010000000ULL
+ },
+ [ POWER5p_PME_PM_DATA_FROM_L275_MOD ] = {
+ 0x0020000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU0_REJECT_SRQ ] = {
+ 0x0000000000004000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU1_DERAT_MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_MRK_LSU_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0010000000000000ULL,
+ 0x0400000020000000ULL
+ },
+ [ POWER5p_PME_PM_DTLB_MISS_16M ] = {
+ 0x0001000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_LSU0_FLUSH_UST ] = {
+ 0x0000000008000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000010ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5p_PME_PM_L2SC_MOD_TAG ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000002000ULL,
+ 0x0000000000000000ULL
+ }
+};
+
+static const pme_power_entry_t power5p_pe[] = {
[ POWER5p_PME_PM_LSU_REJECT_RELOAD_CDF ] = {
.pme_name = "PM_LSU_REJECT_RELOAD_CDF",
+ .pme_code = 0x2c4090,
.pme_short_desc = "LSU reject due to reload CDF or tag update collision",
.pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions because of Critical Data Forward. When critical data arrives from the storage system it is formatted and immediately forwarded, bypassing the data cache, to the destination register using the result bus. Any instruction the requires the result bus in the same cycle is rejected. Tag update rejects are caused when an instruction requires access to the Dcache directory or ERAT in the same system when they are being updated. Combined Unit 0 + 1.",
- .pme_event_ids = { -1, 243, 240, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000080000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_REJECT_RELOAD_CDF],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_REJECT_RELOAD_CDF]
},
-#define POWER5p_PME_PM_FPU1_SINGLE 1
[ POWER5p_PME_PM_FPU1_SINGLE ] = {
.pme_name = "PM_FPU1_SINGLE",
+ .pme_code = 0x20e7,
.pme_short_desc = "FPU1 executed single precision instruction",
.pme_long_desc = "FPU1 has executed a single precision instruction.",
- .pme_event_ids = { 82, 81, 81, 83, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000002000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_SINGLE],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_SINGLE]
},
-#define POWER5p_PME_PM_L3SB_REF 2
[ POWER5p_PME_PM_L3SB_REF ] = {
.pme_name = "PM_L3SB_REF",
+ .pme_code = 0x701c4,
.pme_short_desc = "L3 slice B references",
.pme_long_desc = "Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice",
- .pme_event_ids = { 188, 185, 184, 183, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000008000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SB_REF],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SB_REF]
},
-#define POWER5p_PME_PM_THRD_PRIO_DIFF_3or4_CYC 3
[ POWER5p_PME_PM_THRD_PRIO_DIFF_3or4_CYC ] = {
.pme_name = "PM_THRD_PRIO_DIFF_3or4_CYC",
+ .pme_code = 0x430e5,
.pme_short_desc = "Cycles thread priority difference is 3 or 4",
.pme_long_desc = "Cycles when this thread's priority is higher than the other thread's priority by 3 or 4.",
- .pme_event_ids = { 343, 338, 336, 332, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000200000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_DIFF_3or4_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_DIFF_3or4_CYC]
},
-#define POWER5p_PME_PM_INST_FROM_L275_SHR 4
[ POWER5p_PME_PM_INST_FROM_L275_SHR ] = {
.pme_name = "PM_INST_FROM_L275_SHR",
+ .pme_code = 0x322096,
.pme_short_desc = "Instruction fetched from L2.75 shared",
.pme_long_desc = "An instruction fetch group was fetched with shared (T) data from the L2 on a different module than this processor is located. Fetch groups can contain up to 8 instructions",
- .pme_event_ids = { -1, -1, 115, -1, -1, -1 },
- .pme_group_vector = {
- 0x0200000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L275_SHR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L275_SHR]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD 5
[ POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD ] = {
.pme_name = "PM_MRK_DATA_FROM_L375_MOD",
+ .pme_code = 0x1c70a7,
.pme_short_desc = "Marked data loaded from L3.75 modified",
.pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on a different module than this processor is located due to a marked load.",
- .pme_event_ids = { 274, -1, -1, 268, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x2000000000000000ULL,
- 0x0080000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD]
},
-#define POWER5p_PME_PM_DTLB_MISS_4K 6
[ POWER5p_PME_PM_DTLB_MISS_4K ] = {
.pme_name = "PM_DTLB_MISS_4K",
+ .pme_code = 0x1c208d,
.pme_short_desc = "Data TLB miss for 4K page",
.pme_long_desc = "Data TLB references to 4KB pages that missed the TLB. Page size is determined at TLB reload time.",
- .pme_event_ids = { 32, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0001000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DTLB_MISS_4K],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DTLB_MISS_4K]
},
-#define POWER5p_PME_PM_CLB_FULL_CYC 7
[ POWER5p_PME_PM_CLB_FULL_CYC ] = {
.pme_name = "PM_CLB_FULL_CYC",
+ .pme_code = 0x220e5,
.pme_short_desc = "Cycles CLB full",
.pme_long_desc = "Cycles when both thread's CLB is full.",
- .pme_event_ids = { 14, 13, 13, 14, -1, -1 },
- .pme_group_vector = {
- 0x0000000000001000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CLB_FULL_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CLB_FULL_CYC]
},
-#define POWER5p_PME_PM_MRK_ST_CMPL 8
[ POWER5p_PME_PM_MRK_ST_CMPL ] = {
.pme_name = "PM_MRK_ST_CMPL",
+ .pme_code = 0x100003,
.pme_short_desc = "Marked store instruction completed",
.pme_long_desc = "A sampled store has completed (data home)",
- .pme_event_ids = { 299, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000100000000008ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_ST_CMPL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_ST_CMPL]
},
-#define POWER5p_PME_PM_LSU_FLUSH_LRQ_FULL 9
[ POWER5p_PME_PM_LSU_FLUSH_LRQ_FULL ] = {
.pme_name = "PM_LSU_FLUSH_LRQ_FULL",
+ .pme_code = 0x320e7,
.pme_short_desc = "Flush caused by LRQ full",
.pme_long_desc = "This thread was flushed at dispatch because its Load Request Queue was full. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.",
- .pme_event_ids = { 232, 231, 230, 227, -1, -1 },
- .pme_group_vector = {
- 0x0000000010000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_FLUSH_LRQ_FULL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_FLUSH_LRQ_FULL]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR 10
[ POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR ] = {
.pme_name = "PM_MRK_DATA_FROM_L275_SHR",
+ .pme_code = 0x3c7097,
.pme_short_desc = "Marked data loaded from L2.75 shared",
.pme_long_desc = "The processor's Data Cache was reloaded with shared (T) data from the L2 on a different module than this processor is located due to a marked load.",
- .pme_event_ids = { -1, -1, 265, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0400000000000000ULL,
- 0x0000000800000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR]
},
-#define POWER5p_PME_PM_1INST_CLB_CYC 11
[ POWER5p_PME_PM_1INST_CLB_CYC ] = {
.pme_name = "PM_1INST_CLB_CYC",
+ .pme_code = 0x400c1,
.pme_short_desc = "Cycles 1 instruction in CLB",
.pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.",
- .pme_event_ids = { 1, 1, 1, 2, -1, -1 },
- .pme_group_vector = {
- 0x0000000000002000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_1INST_CLB_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_1INST_CLB_CYC]
},
-#define POWER5p_PME_PM_MEM_SPEC_RD_CANCEL 12
[ POWER5p_PME_PM_MEM_SPEC_RD_CANCEL ] = {
.pme_name = "PM_MEM_SPEC_RD_CANCEL",
+ .pme_code = 0x721e6,
.pme_short_desc = "Speculative memory read cancelled",
.pme_long_desc = "Speculative memory read cancelled (i.e. cresp = sourced by L2/L3)",
- .pme_event_ids = { 264, 263, 259, 258, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0001000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_SPEC_RD_CANCEL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_SPEC_RD_CANCEL]
},
-#define POWER5p_PME_PM_MRK_DTLB_MISS_16M 13
[ POWER5p_PME_PM_MRK_DTLB_MISS_16M ] = {
.pme_name = "PM_MRK_DTLB_MISS_16M",
+ .pme_code = 0x3c608d,
.pme_short_desc = "Marked Data TLB misses for 16M page",
.pme_long_desc = "Marked Data TLB misses for 16M page",
- .pme_event_ids = { -1, -1, 273, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x8000000000000000ULL,
- 0x0000028000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DTLB_MISS_16M],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DTLB_MISS_16M]
},
-#define POWER5p_PME_PM_FPU_FDIV 14
[ POWER5p_PME_PM_FPU_FDIV ] = {
.pme_name = "PM_FPU_FDIV",
+ .pme_code = 0x100088,
.pme_short_desc = "FPU executed FDIV instruction",
.pme_long_desc = "The floating point unit has executed a divide instruction. This could be fdiv, fdivs, fdiv., fdivs.. Combined Unit 0 + Unit 1.",
- .pme_event_ids = { 87, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000020000ULL,
- 0x0000000000410000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_FDIV],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_FDIV]
},
-#define POWER5p_PME_PM_FPU_SINGLE 15
[ POWER5p_PME_PM_FPU_SINGLE ] = {
.pme_name = "PM_FPU_SINGLE",
+ .pme_code = 0x102090,
.pme_short_desc = "FPU executed single precision instruction",
.pme_long_desc = "FPU is executing single precision instruction. Combined Unit 0 + Unit 1.",
- .pme_event_ids = { 90, -1, -1, 90, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000100000ULL,
- 0x0000000000008000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_SINGLE],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_SINGLE]
},
-#define POWER5p_PME_PM_FPU0_FMA 16
[ POWER5p_PME_PM_FPU0_FMA ] = {
.pme_name = "PM_FPU0_FMA",
+ .pme_code = 0xc1,
.pme_short_desc = "FPU0 executed multiply-add instruction",
.pme_long_desc = "The floating point unit has executed a multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 63, 62, 62, 64, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000004000000ULL,
- 0x0000000000001000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_FMA],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_FMA]
},
-#define POWER5p_PME_PM_SLB_MISS 17
[ POWER5p_PME_PM_SLB_MISS ] = {
.pme_name = "PM_SLB_MISS",
+ .pme_code = 0x280088,
.pme_short_desc = "SLB misses",
.pme_long_desc = "Total of all Segment Lookaside Buffer (SLB) misses, Instructions + Data.",
- .pme_event_ids = { -1, 307, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000020000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SLB_MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SLB_MISS]
},
-#define POWER5p_PME_PM_LSU1_FLUSH_LRQ 18
[ POWER5p_PME_PM_LSU1_FLUSH_LRQ ] = {
.pme_name = "PM_LSU1_FLUSH_LRQ",
+ .pme_code = 0xc00c6,
.pme_short_desc = "LSU1 LRQ flushes",
.pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { 220, 216, 216, 215, -1, -1 },
- .pme_group_vector = {
- 0x0000000000800000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_FLUSH_LRQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_FLUSH_LRQ]
},
-#define POWER5p_PME_PM_L2SA_ST_HIT 19
[ POWER5p_PME_PM_L2SA_ST_HIT ] = {
.pme_name = "PM_L2SA_ST_HIT",
+ .pme_code = 0x733e0,
.pme_short_desc = "L2 slice A store hits",
.pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A, B, and C.",
- .pme_event_ids = { 142, 139, 138, 137, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000002ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_ST_HIT],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_ST_HIT]
},
-#define POWER5p_PME_PM_DTLB_MISS 20
[ POWER5p_PME_PM_DTLB_MISS ] = {
.pme_name = "PM_DTLB_MISS",
+ .pme_code = 0x800c4,
.pme_short_desc = "Data TLB misses",
.pme_long_desc = "Data TLB misses, all page sizes.",
- .pme_event_ids = { 31, 30, 30, 31, -1, -1 },
- .pme_group_vector = {
- 0x0002100000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000004000080ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DTLB_MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DTLB_MISS]
},
-#define POWER5p_PME_PM_BR_PRED_TA 21
[ POWER5p_PME_PM_BR_PRED_TA ] = {
.pme_name = "PM_BR_PRED_TA",
+ .pme_code = 0x230e3,
.pme_short_desc = "A conditional branch was predicted",
.pme_long_desc = " target prediction",
- .pme_event_ids = { 203, 11, 351, 348, -1, -1 },
- .pme_group_vector = {
- 0x0000040000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000400ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_BR_PRED_TA],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_BR_PRED_TA]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD_CYC 22
[ POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L375_MOD_CYC",
+ .pme_code = 0x4c70a7,
.pme_short_desc = "Marked load latency from L3.75 modified",
.pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
- .pme_event_ids = { -1, -1, -1, 269, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x2000000000000000ULL,
- 0x0000004000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD_CYC]
},
-#define POWER5p_PME_PM_CMPLU_STALL_FXU 23
[ POWER5p_PME_PM_CMPLU_STALL_FXU ] = {
.pme_name = "PM_CMPLU_STALL_FXU",
+ .pme_code = 0x211099,
.pme_short_desc = "Completion stall caused by FXU instruction",
.pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point instruction.",
- .pme_event_ids = { -1, 16, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000080000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CMPLU_STALL_FXU],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CMPLU_STALL_FXU]
},
-#define POWER5p_PME_PM_EXT_INT 24
[ POWER5p_PME_PM_EXT_INT ] = {
.pme_name = "PM_EXT_INT",
+ .pme_code = 0x400003,
.pme_short_desc = "External interrupts",
.pme_long_desc = "An interrupt due to an external exception occurred",
- .pme_event_ids = { -1, -1, -1, 37, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0002000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_EXT_INT],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_EXT_INT]
},
-#define POWER5p_PME_PM_MRK_LSU1_FLUSH_LRQ 25
[ POWER5p_PME_PM_MRK_LSU1_FLUSH_LRQ ] = {
.pme_name = "PM_MRK_LSU1_FLUSH_LRQ",
+ .pme_code = 0x810c6,
.pme_short_desc = "LSU1 marked LRQ flushes",
.pme_long_desc = "A marked load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { 292, 292, 286, 289, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0020000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU1_FLUSH_LRQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU1_FLUSH_LRQ]
},
-#define POWER5p_PME_PM_MRK_ST_GPS 26
[ POWER5p_PME_PM_MRK_ST_GPS ] = {
.pme_name = "PM_MRK_ST_GPS",
+ .pme_code = 0x200003,
.pme_short_desc = "Marked store sent to GPS",
.pme_long_desc = "A sampled store has been sent to the memory subsystem",
- .pme_event_ids = { -1, 299, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000200000000010ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_ST_GPS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_ST_GPS]
},
-#define POWER5p_PME_PM_LSU1_LDF 27
[ POWER5p_PME_PM_LSU1_LDF ] = {
.pme_name = "PM_LSU1_LDF",
+ .pme_code = 0xc50c4,
.pme_short_desc = "LSU1 executed Floating Point load instruction",
.pme_long_desc = "A floating point load was executed by LSU1",
- .pme_event_ids = { 224, 220, 220, 219, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000002000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_LDF],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_LDF]
},
-#define POWER5p_PME_PM_FAB_CMD_ISSUED 28
[ POWER5p_PME_PM_FAB_CMD_ISSUED ] = {
.pme_name = "PM_FAB_CMD_ISSUED",
+ .pme_code = 0x700c7,
.pme_short_desc = "Fabric command issued",
.pme_long_desc = "Incremented when a chip issues a command on its SnoopA address bus. Each of the two address busses (SnoopA and SnoopB) is capable of one transaction per fabric cycle (one fabric cycle = 2 cpu cycles in normal 2:1 mode), but each chip can only drive the SnoopA bus, and can only drive one transaction every two fabric cycles (i.e., every four cpu cycles). In MCM-based systems, two chips interleave their accesses to each of the two fabric busses (SnoopA, SnoopB) to reach a peak capability of one transaction per cpu clock cycle. The two chips that drive SnoopB are wired so that the chips refer to the bus as SnoopA but it is connected to the other two chips as SnoopB. Note that this event will only be recorded by the FBC on the chip that sourced the operation. The signal is delivered at FBC speed and the count must be scaled.",
- .pme_event_ids = { 37, 36, 36, 38, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000010000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_CMD_ISSUED],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_CMD_ISSUED]
},
-#define POWER5p_PME_PM_LSU0_SRQ_STFWD 29
[ POWER5p_PME_PM_LSU0_SRQ_STFWD ] = {
.pme_name = "PM_LSU0_SRQ_STFWD",
+ .pme_code = 0xc60e1,
.pme_short_desc = "LSU0 SRQ store forwarded",
.pme_long_desc = "Data from a store instruction was forwarded to a load on unit 0. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.",
- .pme_event_ids = { 217, 213, 213, 212, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_SRQ_STFWD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_SRQ_STFWD]
},
-#define POWER5p_PME_PM_CR_MAP_FULL_CYC 30
[ POWER5p_PME_PM_CR_MAP_FULL_CYC ] = {
.pme_name = "PM_CR_MAP_FULL_CYC",
+ .pme_code = 0x100c4,
.pme_short_desc = "Cycles CR logical operation mapper full",
.pme_long_desc = "The Conditional Register mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.",
- .pme_event_ids = { 16, 19, 15, 20, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CR_MAP_FULL_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CR_MAP_FULL_CYC]
},
-#define POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL 31
[ POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL ] = {
.pme_name = "PM_L2SA_RCST_DISP_FAIL_RC_FULL",
+ .pme_code = 0x722e0,
.pme_short_desc = "L2 slice A RC store dispatch attempt failed due to all RC full",
.pme_long_desc = "A Read/Claim dispatch for a store failed because all RC machines are busy.",
- .pme_event_ids = { 137, 134, 133, 132, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000001ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL]
},
-#define POWER5p_PME_PM_MRK_LSU0_FLUSH_ULD 32
[ POWER5p_PME_PM_MRK_LSU0_FLUSH_ULD ] = {
.pme_name = "PM_MRK_LSU0_FLUSH_ULD",
+ .pme_code = 0x810c1,
.pme_short_desc = "LSU0 marked unaligned load flushes",
.pme_long_desc = "A marked load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { 290, 290, 284, 287, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0008000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU0_FLUSH_ULD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU0_FLUSH_ULD]
},
-#define POWER5p_PME_PM_LSU_FLUSH_SRQ_FULL 33
[ POWER5p_PME_PM_LSU_FLUSH_SRQ_FULL ] = {
.pme_name = "PM_LSU_FLUSH_SRQ_FULL",
+ .pme_code = 0x330e0,
.pme_short_desc = "Flush caused by SRQ full",
.pme_long_desc = "This thread was flushed at dispatch because its Store Request Queue was full. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.",
- .pme_event_ids = { 234, 232, 231, 229, -1, -1 },
- .pme_group_vector = {
- 0x0000000010000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_FLUSH_SRQ_FULL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_FLUSH_SRQ_FULL]
},
-#define POWER5p_PME_PM_MEM_RQ_DISP_Q16to19 34
[ POWER5p_PME_PM_MEM_RQ_DISP_Q16to19 ] = {
.pme_name = "PM_MEM_RQ_DISP_Q16to19",
+ .pme_code = 0x727e6,
.pme_short_desc = "Memory read queue dispatched to queues 16-19",
.pme_long_desc = "A memory operation was dispatched to read queue 16,17,18 or 19. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 360, 353, 352, 246, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000800000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_RQ_DISP_Q16to19],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_RQ_DISP_Q16to19]
},
-#define POWER5p_PME_PM_FLUSH_IMBAL 35
[ POWER5p_PME_PM_FLUSH_IMBAL ] = {
.pme_name = "PM_FLUSH_IMBAL",
+ .pme_code = 0x330e3,
.pme_short_desc = "Flush caused by thread GCT imbalance",
.pme_long_desc = "This thread has been flushed at dispatch because it is stalled and a GCT imbalance exists. GCT thresholds are set in the TSCR register. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.",
- .pme_event_ids = { 54, 53, 53, 55, -1, -1 },
- .pme_group_vector = {
- 0x0000000000108000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FLUSH_IMBAL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FLUSH_IMBAL]
},
-#define POWER5p_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC 36
[ POWER5p_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC ] = {
.pme_name = "PM_THRD_PRIO_DIFF_minus3or4_CYC",
+ .pme_code = 0x430e1,
.pme_short_desc = "Cycles thread priority difference is -3 or -4",
.pme_long_desc = "Cycles when this thread's priority is lower than the other thread's priority by 3 or 4.",
- .pme_event_ids = { 346, 341, 339, 335, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000400000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC]
},
-#define POWER5p_PME_PM_DATA_FROM_L35_MOD 37
[ POWER5p_PME_PM_DATA_FROM_L35_MOD ] = {
.pme_name = "PM_DATA_FROM_L35_MOD",
+ .pme_code = 0x2c309e,
.pme_short_desc = "Data loaded from L3.5 modified",
.pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on the same module as this processor is located due to a demand load.",
- .pme_event_ids = { -1, 22, 21, -1, -1, -1 },
- .pme_group_vector = {
- 0x0040000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_L35_MOD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_L35_MOD]
},
-#define POWER5p_PME_PM_MEM_HI_PRIO_WR_CMPL 38
[ POWER5p_PME_PM_MEM_HI_PRIO_WR_CMPL ] = {
.pme_name = "PM_MEM_HI_PRIO_WR_CMPL",
+ .pme_code = 0x726e6,
.pme_short_desc = "High priority write completed",
.pme_long_desc = "A memory write, which was upgraded to high priority, completed. Writes can be upgraded to high priority to ensure that read traffic does not lock out writes. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 253, 252, 248, 247, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000400000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_HI_PRIO_WR_CMPL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_HI_PRIO_WR_CMPL]
},
-#define POWER5p_PME_PM_FPU1_FDIV 39
[ POWER5p_PME_PM_FPU1_FDIV ] = {
.pme_name = "PM_FPU1_FDIV",
+ .pme_code = 0xc4,
.pme_short_desc = "FPU1 executed FDIV instruction",
.pme_long_desc = "FPU1 has executed a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.",
- .pme_event_ids = { 74, 73, 73, 75, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000800000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_FDIV],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_FDIV]
},
-#define POWER5p_PME_PM_MEM_RQ_DISP 40
[ POWER5p_PME_PM_MEM_RQ_DISP ] = {
.pme_name = "PM_MEM_RQ_DISP",
+ .pme_code = 0x701c6,
.pme_short_desc = "Memory read queue dispatched",
.pme_long_desc = "A memory read was dispatched. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 261, 260, 256, 255, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0001000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_RQ_DISP],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_RQ_DISP]
},
-#define POWER5p_PME_PM_FPU0_FRSP_FCONV 41
[ POWER5p_PME_PM_FPU0_FRSP_FCONV ] = {
.pme_name = "PM_FPU0_FRSP_FCONV",
+ .pme_code = 0x10c1,
.pme_short_desc = "FPU0 executed FRSP or FCONV instructions",
.pme_long_desc = "FPU0 has executed a frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 66, 65, 65, 67, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000800000ULL,
- 0x0000000000001000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_FRSP_FCONV],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_FRSP_FCONV]
},
-#define POWER5p_PME_PM_LWSYNC_HELD 42
[ POWER5p_PME_PM_LWSYNC_HELD ] = {
.pme_name = "PM_LWSYNC_HELD",
+ .pme_code = 0x130e0,
.pme_short_desc = "LWSYNC held at dispatch",
.pme_long_desc = "Cycles a LWSYNC instruction was held at dispatch. LWSYNC instructions are held at dispatch until all previous loads are done and all previous stores have issued. LWSYNC enters the Store Request Queue and is sent to the storage subsystem but does not wait for a response.",
- .pme_event_ids = { 250, 249, 245, 244, -1, -1 },
- .pme_group_vector = {
- 0x0000000000020000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LWSYNC_HELD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LWSYNC_HELD]
},
-#define POWER5p_PME_PM_FXU_FIN 43
[ POWER5p_PME_PM_FXU_FIN ] = {
.pme_name = "PM_FXU_FIN",
+ .pme_code = 0x313088,
.pme_short_desc = "FXU produced a result",
.pme_long_desc = "The fixed point unit (Unit 0 + Unit 1) finished an instruction. Instructions that finish may not necessary complete.",
- .pme_event_ids = { -1, -1, 93, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000040000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FXU_FIN],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FXU_FIN]
},
-#define POWER5p_PME_PM_DSLB_MISS 44
[ POWER5p_PME_PM_DSLB_MISS ] = {
.pme_name = "PM_DSLB_MISS",
+ .pme_code = 0x800c5,
.pme_short_desc = "Data SLB misses",
.pme_long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve.",
- .pme_event_ids = { 30, 29, 29, 30, -1, -1 },
- .pme_group_vector = {
- 0x0000400000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DSLB_MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DSLB_MISS]
},
-#define POWER5p_PME_PM_DATA_FROM_L275_SHR 45
[ POWER5p_PME_PM_DATA_FROM_L275_SHR ] = {
.pme_name = "PM_DATA_FROM_L275_SHR",
+ .pme_code = 0x3c3097,
.pme_short_desc = "Data loaded from L2.75 shared",
.pme_long_desc = "The processor's Data Cache was reloaded with shared (T) data from the L2 on a different module than this processor is located due to a demand load.",
- .pme_event_ids = { -1, -1, 18, -1, -1, -1 },
- .pme_group_vector = {
- 0x0020000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_L275_SHR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_L275_SHR]
},
-#define POWER5p_PME_PM_FXLS1_FULL_CYC 46
[ POWER5p_PME_PM_FXLS1_FULL_CYC ] = {
.pme_name = "PM_FXLS1_FULL_CYC",
+ .pme_code = 0x110c4,
.pme_short_desc = "Cycles FXU1/LS1 queue full",
.pme_long_desc = "The issue queue that feeds the Fixed Point unit 1 / Load Store Unit 1 is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.",
- .pme_event_ids = { 92, 90, 89, 92, -1, -1 },
- .pme_group_vector = {
- 0x0000000400000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FXLS1_FULL_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FXLS1_FULL_CYC]
},
-#define POWER5p_PME_PM_THRD_SEL_T0 47
[ POWER5p_PME_PM_THRD_SEL_T0 ] = {
.pme_name = "PM_THRD_SEL_T0",
+ .pme_code = 0x410c0,
.pme_short_desc = "Decode selected thread 0",
.pme_long_desc = "Thread selection picked thread 0 for decode.",
- .pme_event_ids = { 352, 347, 345, 341, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000002000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_SEL_T0],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_SEL_T0]
},
-#define POWER5p_PME_PM_PTEG_RELOAD_VALID 48
[ POWER5p_PME_PM_PTEG_RELOAD_VALID ] = {
.pme_name = "PM_PTEG_RELOAD_VALID",
+ .pme_code = 0x830e4,
.pme_short_desc = "PTEG reload valid",
.pme_long_desc = "A Page Table Entry was loaded into the TLB.",
- .pme_event_ids = { 311, 306, 305, 303, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_RELOAD_VALID],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_RELOAD_VALID]
},
-#define POWER5p_PME_PM_MRK_STCX_FAIL 49
[ POWER5p_PME_PM_MRK_STCX_FAIL ] = {
.pme_name = "PM_MRK_STCX_FAIL",
+ .pme_code = 0x820e6,
.pme_short_desc = "Marked STCX failed",
.pme_long_desc = "A marked stcx (stwcx or stdcx) failed",
- .pme_event_ids = { 298, 298, 293, 297, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0020000000000010ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_STCX_FAIL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_STCX_FAIL]
},
-#define POWER5p_PME_PM_LSU_LMQ_LHR_MERGE 50
[ POWER5p_PME_PM_LSU_LMQ_LHR_MERGE ] = {
.pme_name = "PM_LSU_LMQ_LHR_MERGE",
+ .pme_code = 0xc70e5,
.pme_short_desc = "LMQ LHR merges",
.pme_long_desc = "A data cache miss occurred for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.",
- .pme_event_ids = { 238, 235, 233, 232, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000200ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_LMQ_LHR_MERGE],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_LMQ_LHR_MERGE]
},
-#define POWER5p_PME_PM_2INST_CLB_CYC 51
[ POWER5p_PME_PM_2INST_CLB_CYC ] = {
.pme_name = "PM_2INST_CLB_CYC",
+ .pme_code = 0x400c2,
.pme_short_desc = "Cycles 2 instructions in CLB",
.pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.",
- .pme_event_ids = { 3, 2, 2, 3, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000008ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_2INST_CLB_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_2INST_CLB_CYC]
},
-#define POWER5p_PME_PM_FAB_PNtoVN_DIRECT 52
[ POWER5p_PME_PM_FAB_PNtoVN_DIRECT ] = {
.pme_name = "PM_FAB_PNtoVN_DIRECT",
+ .pme_code = 0x723e7,
.pme_short_desc = "PN to VN beat went straight to its destination",
.pme_long_desc = "Fabric Data beats that the base chip takes the inbound PN data and passes it through to the outbound VN bus without going into a sidecar. The signal is delivered at FBC speed and the count must be scaled accordingly.",
- .pme_event_ids = { 49, 48, 48, 50, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000040000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_PNtoVN_DIRECT],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_PNtoVN_DIRECT]
},
-#define POWER5p_PME_PM_PTEG_FROM_L2MISS 53
[ POWER5p_PME_PM_PTEG_FROM_L2MISS ] = {
.pme_name = "PM_PTEG_FROM_L2MISS",
+ .pme_code = 0x38309b,
.pme_short_desc = "PTEG loaded from L2 miss",
.pme_long_desc = "A Page Table Entry was loaded into the TLB but not from the local L2.",
- .pme_event_ids = { -1, -1, 300, -1, -1, -1 },
- .pme_group_vector = {
- 0x2000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_L2MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_L2MISS]
},
-#define POWER5p_PME_PM_CMPLU_STALL_LSU 54
[ POWER5p_PME_PM_CMPLU_STALL_LSU ] = {
.pme_name = "PM_CMPLU_STALL_LSU",
+ .pme_code = 0x211098,
.pme_short_desc = "Completion stall caused by LSU instruction",
.pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a load/store instruction.",
- .pme_event_ids = { -1, 17, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000020000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CMPLU_STALL_LSU],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CMPLU_STALL_LSU]
},
-#define POWER5p_PME_PM_MRK_DSLB_MISS 55
[ POWER5p_PME_PM_MRK_DSLB_MISS ] = {
.pme_name = "PM_MRK_DSLB_MISS",
+ .pme_code = 0xc50c7,
.pme_short_desc = "Marked Data SLB misses",
.pme_long_desc = "A Data SLB miss was caused by a marked instruction.",
- .pme_event_ids = { 276, 278, 271, 273, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000040000000003ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DSLB_MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DSLB_MISS]
},
-#define POWER5p_PME_PM_LSU_FLUSH_ULD 56
[ POWER5p_PME_PM_LSU_FLUSH_ULD ] = {
.pme_name = "PM_LSU_FLUSH_ULD",
+ .pme_code = 0x1c0088,
.pme_short_desc = "LRQ unaligned load flushes",
.pme_long_desc = "A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1). Combined Unit 0 + 1.",
- .pme_event_ids = { 235, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000002000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_FLUSH_ULD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_FLUSH_ULD]
},
-#define POWER5p_PME_PM_PTEG_FROM_LMEM 57
[ POWER5p_PME_PM_PTEG_FROM_LMEM ] = {
.pme_name = "PM_PTEG_FROM_LMEM",
+ .pme_code = 0x283087,
.pme_short_desc = "PTEG loaded from local memory",
.pme_long_desc = "A Page Table Entry was loaded into the TLB from memory attached to the same module this proccessor is located on.",
- .pme_event_ids = { -1, 305, 304, -1, -1, -1 },
- .pme_group_vector = {
- 0x2000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_LMEM],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_LMEM]
},
-#define POWER5p_PME_PM_MRK_BRU_FIN 58
[ POWER5p_PME_PM_MRK_BRU_FIN ] = {
.pme_name = "PM_MRK_BRU_FIN",
+ .pme_code = 0x200005,
.pme_short_desc = "Marked instruction BRU processing finished",
.pme_long_desc = "The branch unit finished a marked instruction. Instructions that finish may not necessary complete.",
- .pme_event_ids = { -1, 268, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0040000000000000ULL,
- 0x0090000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_BRU_FIN],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_BRU_FIN]
},
-#define POWER5p_PME_PM_MEM_WQ_DISP_WRITE 59
[ POWER5p_PME_PM_MEM_WQ_DISP_WRITE ] = {
.pme_name = "PM_MEM_WQ_DISP_WRITE",
+ .pme_code = 0x703c6,
.pme_short_desc = "Memory write queue dispatched due to write",
.pme_long_desc = "A memory write was dispatched to a write queue. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 268, 267, 263, 262, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0004000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_WQ_DISP_WRITE],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_WQ_DISP_WRITE]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD_CYC 60
[ POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L275_MOD_CYC",
+ .pme_code = 0x4c70a3,
.pme_short_desc = "Marked load latency from L2.75 modified",
.pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
- .pme_event_ids = { -1, -1, -1, 266, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x1000000000000000ULL,
- 0x0000002000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD_CYC]
},
-#define POWER5p_PME_PM_LSU1_NCLD 61
[ POWER5p_PME_PM_LSU1_NCLD ] = {
.pme_name = "PM_LSU1_NCLD",
+ .pme_code = 0xc50c5,
.pme_short_desc = "LSU1 non-cacheable loads",
.pme_long_desc = "A non-cacheable load was executed by Unit 0.",
- .pme_event_ids = { 225, 221, 221, 220, -1, -1 },
- .pme_group_vector = {
- 0x0000002000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_NCLD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_NCLD]
},
-#define POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER 62
[ POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER ] = {
.pme_name = "PM_L2SA_RCLD_DISP_FAIL_OTHER",
+ .pme_code = 0x731e0,
.pme_short_desc = "L2 slice A RC load dispatch attempt failed due to other reasons",
.pme_long_desc = "A Read/Claim dispatch for a load failed for some reason other than Full or Collision conditions.",
- .pme_event_ids = { 132, 129, 128, 127, -1, -1 },
- .pme_group_vector = {
- 0x8000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER]
},
-#define POWER5p_PME_PM_SNOOP_PW_RETRY_WQ_PWQ 63
[ POWER5p_PME_PM_SNOOP_PW_RETRY_WQ_PWQ ] = {
.pme_name = "PM_SNOOP_PW_RETRY_WQ_PWQ",
+ .pme_code = 0x717c6,
.pme_short_desc = "Snoop partial-write retry due to collision with active write or partial-write queue",
.pme_long_desc = "A snoop request for a partial write to memory was retried because it matched the cache line of an active write or partial write. When this happens the snoop request is retried and the active write is changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 316, 311, 309, 307, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000800000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_PW_RETRY_WQ_PWQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_PW_RETRY_WQ_PWQ]
},
-#define POWER5p_PME_PM_FPU1_FULL_CYC 64
[ POWER5p_PME_PM_FPU1_FULL_CYC ] = {
.pme_name = "PM_FPU1_FULL_CYC",
+ .pme_code = 0x100c7,
.pme_short_desc = "Cycles FPU1 issue queue full",
.pme_long_desc = "The issue queue for FPU1 cannot accept any more instructions. Dispatch to this issue queue is stopped",
- .pme_event_ids = { 81, 80, 80, 82, -1, -1 },
- .pme_group_vector = {
- 0x0000000400000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_FULL_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_FULL_CYC]
},
-#define POWER5p_PME_PM_FPR_MAP_FULL_CYC 65
[ POWER5p_PME_PM_FPR_MAP_FULL_CYC ] = {
.pme_name = "PM_FPR_MAP_FULL_CYC",
+ .pme_code = 0x100c1,
.pme_short_desc = "Cycles FPR mapper full",
.pme_long_desc = "The floating point unit has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations.",
- .pme_event_ids = { 57, 56, 56, 58, -1, -1 },
- .pme_group_vector = {
- 0x0000001000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPR_MAP_FULL_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPR_MAP_FULL_CYC]
},
-#define POWER5p_PME_PM_L3SA_ALL_BUSY 66
[ POWER5p_PME_PM_L3SA_ALL_BUSY ] = {
.pme_name = "PM_L3SA_ALL_BUSY",
+ .pme_code = 0x721e3,
.pme_short_desc = "L3 slice A active for every cycle all CI/CO machines busy",
.pme_long_desc = "Cycles All Castin/Castout machines are busy.",
- .pme_event_ids = { 177, 174, 173, 172, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000004000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SA_ALL_BUSY],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SA_ALL_BUSY]
},
-#define POWER5p_PME_PM_3INST_CLB_CYC 67
[ POWER5p_PME_PM_3INST_CLB_CYC ] = {
.pme_name = "PM_3INST_CLB_CYC",
+ .pme_code = 0x400c3,
.pme_short_desc = "Cycles 3 instructions in CLB",
.pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.",
- .pme_event_ids = { 4, 3, 3, 4, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000080000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_3INST_CLB_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_3INST_CLB_CYC]
},
-#define POWER5p_PME_PM_MEM_PWQ_DISP_Q2or3 68
[ POWER5p_PME_PM_MEM_PWQ_DISP_Q2or3 ] = {
.pme_name = "PM_MEM_PWQ_DISP_Q2or3",
+ .pme_code = 0x734e6,
.pme_short_desc = "Memory partial-write queue dispatched to Write Queue 2 or 3",
.pme_long_desc = "Memory partial-write queue dispatched to Write Queue 2 or 3. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 257, 250, 252, 251, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0008000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_PWQ_DISP_Q2or3],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_PWQ_DISP_Q2or3]
},
-#define POWER5p_PME_PM_L2SA_SHR_INV 69
[ POWER5p_PME_PM_L2SA_SHR_INV ] = {
.pme_name = "PM_L2SA_SHR_INV",
+ .pme_code = 0x710c0,
.pme_short_desc = "L2 slice A transition from shared to invalid",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A, B, and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.",
- .pme_event_ids = { 140, 137, 136, 135, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000800ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_SHR_INV],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_SHR_INV]
},
-#define POWER5p_PME_PM_THRESH_TIMEO 70
[ POWER5p_PME_PM_THRESH_TIMEO ] = {
.pme_name = "PM_THRESH_TIMEO",
+ .pme_code = 0x30000b,
.pme_short_desc = "Threshold timeout",
.pme_long_desc = "The threshold timer expired",
- .pme_event_ids = { -1, -1, 348, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0010000000000000ULL,
- 0x0000000020000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRESH_TIMEO],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRESH_TIMEO]
},
-#define POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL 71
[ POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL ] = {
.pme_name = "PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL",
+ .pme_code = 0x713c0,
.pme_short_desc = "L2 slice A RC dispatch attempt failed due to all CO busy",
.pme_long_desc = "A Read/Claim dispatch was rejected because all Castout machines were busy.",
- .pme_event_ids = { 139, 136, 135, 134, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000002ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL]
},
-#define POWER5p_PME_PM_THRD_SEL_OVER_GCT_IMBAL 72
[ POWER5p_PME_PM_THRD_SEL_OVER_GCT_IMBAL ] = {
.pme_name = "PM_THRD_SEL_OVER_GCT_IMBAL",
+ .pme_code = 0x410c4,
.pme_short_desc = "Thread selection overrides caused by GCT imbalance",
.pme_long_desc = "Thread selection was overridden because of a GCT imbalance.",
- .pme_event_ids = { 349, 344, 342, 338, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000004000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_SEL_OVER_GCT_IMBAL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_SEL_OVER_GCT_IMBAL]
},
-#define POWER5p_PME_PM_FPU_FSQRT 73
[ POWER5p_PME_PM_FPU_FSQRT ] = {
.pme_name = "PM_FPU_FSQRT",
+ .pme_code = 0x200090,
.pme_short_desc = "FPU executed FSQRT instruction",
.pme_long_desc = "The floating point unit has executed a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.",
- .pme_event_ids = { -1, 86, 86, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000040000ULL,
- 0x0000000000410000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_FSQRT],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_FSQRT]
},
-#define POWER5p_PME_PM_PMC1_OVERFLOW 74
[ POWER5p_PME_PM_PMC1_OVERFLOW ] = {
.pme_name = "PM_PMC1_OVERFLOW",
+ .pme_code = 0x20000a,
.pme_short_desc = "PMC1 Overflow",
.pme_long_desc = "Overflows from PMC1 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
- .pme_event_ids = { -1, 301, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PMC1_OVERFLOW],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PMC1_OVERFLOW]
},
-#define POWER5p_PME_PM_MRK_LSU0_FLUSH_LRQ 75
[ POWER5p_PME_PM_MRK_LSU0_FLUSH_LRQ ] = {
.pme_name = "PM_MRK_LSU0_FLUSH_LRQ",
+ .pme_code = 0x810c2,
.pme_short_desc = "LSU0 marked LRQ flushes",
.pme_long_desc = "A marked load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { 288, 288, 282, 285, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0010000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU0_FLUSH_LRQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU0_FLUSH_LRQ]
},
-#define POWER5p_PME_PM_L3SC_SNOOP_RETRY 76
[ POWER5p_PME_PM_L3SC_SNOOP_RETRY ] = {
.pme_name = "PM_L3SC_SNOOP_RETRY",
+ .pme_code = 0x731e5,
.pme_short_desc = "L3 slice C snoop retries",
.pme_long_desc = "Number of times an L3 retried a snoop because it got two in at the same time (one on snp_a, one on snp_b)",
- .pme_event_ids = { 197, 194, 193, 192, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000010000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SC_SNOOP_RETRY],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SC_SNOOP_RETRY]
},
-#define POWER5p_PME_PM_DATA_TABLEWALK_CYC 77
[ POWER5p_PME_PM_DATA_TABLEWALK_CYC ] = {
.pme_name = "PM_DATA_TABLEWALK_CYC",
+ .pme_code = 0x800c7,
.pme_short_desc = "Cycles doing data tablewalks",
.pme_long_desc = "Cycles a translation tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.",
- .pme_event_ids = { 25, 24, 24, 25, -1, -1 },
- .pme_group_vector = {
- 0x0000100000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_TABLEWALK_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_TABLEWALK_CYC]
},
-#define POWER5p_PME_PM_THRD_PRIO_6_CYC 78
[ POWER5p_PME_PM_THRD_PRIO_6_CYC ] = {
.pme_name = "PM_THRD_PRIO_6_CYC",
+ .pme_code = 0x420e5,
.pme_short_desc = "Cycles thread running at priority level 6",
.pme_long_desc = "Cycles this thread was running at priority level 6.",
- .pme_event_ids = { 339, 334, 332, 328, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000200000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_6_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_6_CYC]
},
-#define POWER5p_PME_PM_FPU_FEST 79
[ POWER5p_PME_PM_FPU_FEST ] = {
.pme_name = "PM_FPU_FEST",
+ .pme_code = 0x1010a8,
.pme_short_desc = "FPU executed FEST instruction",
.pme_long_desc = "The floating point unit has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. Combined Unit 0 + Unit 1.",
- .pme_event_ids = { 88, -1, -1, 87, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000020000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_FEST],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_FEST]
},
-#define POWER5p_PME_PM_FAB_M1toP1_SIDECAR_EMPTY 80
[ POWER5p_PME_PM_FAB_M1toP1_SIDECAR_EMPTY ] = {
.pme_name = "PM_FAB_M1toP1_SIDECAR_EMPTY",
+ .pme_code = 0x702c7,
.pme_short_desc = "M1 to P1 sidecar empty",
.pme_long_desc = "Fabric cycles when the Minus-1 hip/hop sidecars (sidecars for chip to chip data transfer) are empty. The signal is delivered at FBC speed and the count must be scaled accordingly.",
- .pme_event_ids = { 43, 42, 42, 44, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000080000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_M1toP1_SIDECAR_EMPTY],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_M1toP1_SIDECAR_EMPTY]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_RMEM 81
[ POWER5p_PME_PM_MRK_DATA_FROM_RMEM ] = {
.pme_name = "PM_MRK_DATA_FROM_RMEM",
+ .pme_code = 0x1c70a1,
.pme_short_desc = "Marked data loaded from remote memory",
.pme_long_desc = "The processor's Data Cache was reloaded due to a marked load from memory attached to a different module than this proccessor is located on.",
- .pme_event_ids = { 275, -1, -1, 271, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0400000000000000ULL,
- 0x0000800000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_RMEM],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_RMEM]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD_CYC 82
[ POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L35_MOD_CYC",
+ .pme_code = 0x4c70a6,
.pme_short_desc = "Marked load latency from L3.5 modified",
.pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
- .pme_event_ids = { -1, -1, -1, 267, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000008ULL,
- 0x0200000000000000ULL,
- 0x0000000400000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD_CYC]
},
-#define POWER5p_PME_PM_MEM_PWQ_DISP 83
[ POWER5p_PME_PM_MEM_PWQ_DISP ] = {
.pme_name = "PM_MEM_PWQ_DISP",
+ .pme_code = 0x704c6,
.pme_short_desc = "Memory partial-write queue dispatched",
.pme_long_desc = "Number of Partial Writes dispatched. The MC provides resources to gather partial cacheline writes (Partial line DMA writes & CI-stores) to up to four different cachelines at a time. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 256, 255, 251, 250, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0008000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_PWQ_DISP],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_PWQ_DISP]
},
-#define POWER5p_PME_PM_FAB_P1toM1_SIDECAR_EMPTY 84
[ POWER5p_PME_PM_FAB_P1toM1_SIDECAR_EMPTY ] = {
.pme_name = "PM_FAB_P1toM1_SIDECAR_EMPTY",
+ .pme_code = 0x701c7,
.pme_short_desc = "P1 to M1 sidecar empty",
.pme_long_desc = "Fabric cycles when the Plus-1 hip/hop sidecars (sidecars for chip to chip data transfer) are empty. The signal is delivered at FBC speed and the count must be scaled accordingly.",
- .pme_event_ids = { 45, 44, 44, 46, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000020000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_P1toM1_SIDECAR_EMPTY],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_P1toM1_SIDECAR_EMPTY]
},
-#define POWER5p_PME_PM_LD_MISS_L1_LSU0 85
[ POWER5p_PME_PM_LD_MISS_L1_LSU0 ] = {
.pme_name = "PM_LD_MISS_L1_LSU0",
+ .pme_code = 0xc10c2,
.pme_short_desc = "LSU0 L1 D cache load misses",
.pme_long_desc = "Load references that miss the Level 1 Data cache, by unit 0.",
- .pme_event_ids = { 199, 196, 196, 194, -1, -1 },
- .pme_group_vector = {
- 0x0000400000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LD_MISS_L1_LSU0],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LD_MISS_L1_LSU0]
},
-#define POWER5p_PME_PM_SNOOP_PARTIAL_RTRY_QFULL 86
[ POWER5p_PME_PM_SNOOP_PARTIAL_RTRY_QFULL ] = {
.pme_name = "PM_SNOOP_PARTIAL_RTRY_QFULL",
+ .pme_code = 0x730e6,
.pme_short_desc = "Snoop partial write retry due to partial-write queues full",
.pme_long_desc = "A snoop request for a partial write to memory was retried because the write queues that handle partial writes were full. When this happens the active writes are changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 314, 309, 307, 305, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000100000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_PARTIAL_RTRY_QFULL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_PARTIAL_RTRY_QFULL]
},
-#define POWER5p_PME_PM_FPU1_STALL3 87
[ POWER5p_PME_PM_FPU1_STALL3 ] = {
.pme_name = "PM_FPU1_STALL3",
+ .pme_code = 0x20e5,
.pme_short_desc = "FPU1 stalled in pipe3",
.pme_long_desc = "FPU1 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always).",
- .pme_event_ids = { 83, 82, 82, 84, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000001000000ULL,
- 0x0000000000000800ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_STALL3],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_STALL3]
},
-#define POWER5p_PME_PM_GCT_USAGE_80to99_CYC 88
[ POWER5p_PME_PM_GCT_USAGE_80to99_CYC ] = {
.pme_name = "PM_GCT_USAGE_80to99_CYC",
+ .pme_code = 0x30001f,
.pme_short_desc = "Cycles GCT 80-99% full",
.pme_long_desc = "Cycles when the Global Completion Table has between 80% and 99% of its slots used. The GCT has 20 entries shared between threads",
- .pme_event_ids = { -1, -1, 96, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000040ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GCT_USAGE_80to99_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GCT_USAGE_80to99_CYC]
},
-#define POWER5p_PME_PM_WORK_HELD 89
[ POWER5p_PME_PM_WORK_HELD ] = {
.pme_name = "PM_WORK_HELD",
+ .pme_code = 0x40000c,
.pme_short_desc = "Work held",
.pme_long_desc = "RAS Unit has signaled completion to stop and there are groups waiting to complete",
- .pme_event_ids = { -1, -1, -1, 345, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_WORK_HELD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_WORK_HELD]
},
-#define POWER5p_PME_PM_INST_CMPL 90
[ POWER5p_PME_PM_INST_CMPL ] = {
.pme_name = "PM_INST_CMPL",
+ .pme_code = 0x100009,
.pme_short_desc = "Instructions completed",
.pme_long_desc = "Number of PowerPC instructions that completed.",
- .pme_event_ids = { 303, 302, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000001ULL,
- 0x0000000000000000ULL,
- 0x0ffffffff9880000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_CMPL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_CMPL]
},
-#define POWER5p_PME_PM_LSU1_FLUSH_UST 91
[ POWER5p_PME_PM_LSU1_FLUSH_UST ] = {
.pme_name = "PM_LSU1_FLUSH_UST",
+ .pme_code = 0xc00c5,
.pme_short_desc = "LSU1 unaligned store flushes",
.pme_long_desc = "A store was flushed from unit 1 because it was unaligned (crossed a 4K boundary)",
- .pme_event_ids = { 223, 219, 219, 218, -1, -1 },
- .pme_group_vector = {
- 0x0000000008000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_FLUSH_UST],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_FLUSH_UST]
},
-#define POWER5p_PME_PM_FXU_IDLE 92
[ POWER5p_PME_PM_FXU_IDLE ] = {
.pme_name = "PM_FXU_IDLE",
+ .pme_code = 0x100012,
.pme_short_desc = "FXU idle",
.pme_long_desc = "FXU0 and FXU1 are both idle.",
- .pme_event_ids = { 96, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000020000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FXU_IDLE],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FXU_IDLE]
},
-#define POWER5p_PME_PM_LSU0_FLUSH_ULD 93
[ POWER5p_PME_PM_LSU0_FLUSH_ULD ] = {
.pme_name = "PM_LSU0_FLUSH_ULD",
+ .pme_code = 0xc00c0,
.pme_short_desc = "LSU0 unaligned load flushes",
.pme_long_desc = "A load was flushed from unit 0 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { 209, 205, 205, 204, -1, -1 },
- .pme_group_vector = {
- 0x0000000004000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_FLUSH_ULD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_FLUSH_ULD]
},
-#define POWER5p_PME_PM_LSU1_REJECT_LMQ_FULL 94
[ POWER5p_PME_PM_LSU1_REJECT_LMQ_FULL ] = {
.pme_name = "PM_LSU1_REJECT_LMQ_FULL",
+ .pme_code = 0xc40c5,
.pme_short_desc = "LSU1 reject due to LMQ full or missed data coming",
.pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected.",
- .pme_event_ids = { 227, 223, 223, 222, -1, -1 },
- .pme_group_vector = {
- 0x0000000000040000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_REJECT_LMQ_FULL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_REJECT_LMQ_FULL]
},
-#define POWER5p_PME_PM_GRP_DISP_REJECT 95
[ POWER5p_PME_PM_GRP_DISP_REJECT ] = {
.pme_name = "PM_GRP_DISP_REJECT",
+ .pme_code = 0x120e4,
.pme_short_desc = "Group dispatch rejected",
.pme_long_desc = "A group that previously attempted dispatch was rejected.",
- .pme_event_ids = { 104, 104, 102, 103, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000004ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_DISP_REJECT],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_DISP_REJECT]
},
-#define POWER5p_PME_PM_PTEG_FROM_L25_SHR 96
[ POWER5p_PME_PM_PTEG_FROM_L25_SHR ] = {
.pme_name = "PM_PTEG_FROM_L25_SHR",
+ .pme_code = 0x183097,
.pme_short_desc = "PTEG loaded from L2.5 shared",
.pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (T or SL) data from the L2 of a chip on the same module as this processor is located due to a demand load.",
- .pme_event_ids = { 305, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0800000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_L25_SHR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_L25_SHR]
},
-#define POWER5p_PME_PM_L2SA_MOD_INV 97
[ POWER5p_PME_PM_L2SA_MOD_INV ] = {
.pme_name = "PM_L2SA_MOD_INV",
+ .pme_code = 0x730e0,
.pme_short_desc = "L2 slice A transition from modified to invalid",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.",
- .pme_event_ids = { 128, 125, 124, 123, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000800ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_MOD_INV],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_MOD_INV]
},
-#define POWER5p_PME_PM_FAB_CMD_RETRIED 98
[ POWER5p_PME_PM_FAB_CMD_RETRIED ] = {
.pme_name = "PM_FAB_CMD_RETRIED",
+ .pme_code = 0x710c7,
.pme_short_desc = "Fabric command retried",
.pme_long_desc = "Incremented when a command issued by a chip on its SnoopA address bus is retried for any reason. The overwhelming majority of retries are due to running out of memory controller queues but retries can also be caused by trying to reference addresses that are in a transient cache state -- e.g. a line is transient after issuing a DCLAIM instruction to a shared line but before the associated store completes. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.",
- .pme_event_ids = { 38, 37, 37, 39, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000010000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_CMD_RETRIED],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_CMD_RETRIED]
},
-#define POWER5p_PME_PM_L3SA_SHR_INV 99
[ POWER5p_PME_PM_L3SA_SHR_INV ] = {
.pme_name = "PM_L3SA_SHR_INV",
+ .pme_code = 0x710c3,
.pme_short_desc = "L3 slice A transition from shared to invalid",
.pme_long_desc = "L3 snooper detects someone doing a store to a line that is Sx in this L3(i.e. invalidate hit SX and dispatched).",
- .pme_event_ids = { 182, 179, 178, 177, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000100ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SA_SHR_INV],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SA_SHR_INV]
},
-#define POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL 100
[ POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL ] = {
.pme_name = "PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL",
+ .pme_code = 0x713c1,
.pme_short_desc = "L2 slice B RC dispatch attempt failed due to all CO busy",
.pme_long_desc = "A Read/Claim dispatch was rejected because all Castout machines were busy.",
- .pme_event_ids = { 155, 152, 151, 150, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000010ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL]
},
-#define POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_ADDR 101
[ POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_ADDR ] = {
.pme_name = "PM_L2SA_RCST_DISP_FAIL_ADDR",
+ .pme_code = 0x712c0,
.pme_short_desc = "L2 slice A RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ",
.pme_long_desc = "A Read/Claim dispatch for a store failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.",
- .pme_event_ids = { 135, 132, 131, 130, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000001ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_ADDR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_ADDR]
},
-#define POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL 102
[ POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL ] = {
.pme_name = "PM_L2SA_RCLD_DISP_FAIL_RC_FULL",
+ .pme_code = 0x721e0,
.pme_short_desc = "L2 slice A RC load dispatch attempt failed due to all RC full",
.pme_long_desc = "A Read/Claim dispatch for a load failed because all RC machines are busy.",
- .pme_event_ids = { 133, 130, 129, 128, -1, -1 },
- .pme_group_vector = {
- 0x8000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL]
},
-#define POWER5p_PME_PM_PTEG_FROM_L375_MOD 103
[ POWER5p_PME_PM_PTEG_FROM_L375_MOD ] = {
.pme_name = "PM_PTEG_FROM_L375_MOD",
+ .pme_code = 0x1830a7,
.pme_short_desc = "PTEG loaded from L3.75 modified",
.pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L3 of a chip on a different module than this processor is located, due to a demand load.",
- .pme_event_ids = { 309, -1, -1, 301, -1, -1 },
- .pme_group_vector = {
- 0x1000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_L375_MOD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_L375_MOD]
},
-#define POWER5p_PME_PM_MRK_LSU1_FLUSH_UST 104
[ POWER5p_PME_PM_MRK_LSU1_FLUSH_UST ] = {
.pme_name = "PM_MRK_LSU1_FLUSH_UST",
+ .pme_code = 0x810c5,
.pme_short_desc = "LSU1 marked unaligned store flushes",
.pme_long_desc = "A marked store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)",
- .pme_event_ids = { 295, 295, 289, 292, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0004000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU1_FLUSH_UST],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU1_FLUSH_UST]
},
-#define POWER5p_PME_PM_BR_ISSUED 105
[ POWER5p_PME_PM_BR_ISSUED ] = {
.pme_name = "PM_BR_ISSUED",
+ .pme_code = 0x230e4,
.pme_short_desc = "Branches issued",
.pme_long_desc = "A branch instruction was issued to the branch unit. A branch that was incorrectly predicted may issue and execute multiple times.",
- .pme_event_ids = { 9, 8, 8, 9, -1, -1 },
- .pme_group_vector = {
- 0x0000000002040000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000400ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_BR_ISSUED],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_BR_ISSUED]
},
-#define POWER5p_PME_PM_MRK_GRP_BR_REDIR 106
[ POWER5p_PME_PM_MRK_GRP_BR_REDIR ] = {
.pme_name = "PM_MRK_GRP_BR_REDIR",
+ .pme_code = 0x212091,
.pme_short_desc = "Group experienced marked branch redirect",
.pme_long_desc = "A group containing a marked (sampled) instruction experienced a branch redirect.",
- .pme_event_ids = { -1, 283, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000040000000ULL,
- 0x0800000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_GRP_BR_REDIR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_GRP_BR_REDIR]
},
-#define POWER5p_PME_PM_EE_OFF 107
[ POWER5p_PME_PM_EE_OFF ] = {
.pme_name = "PM_EE_OFF",
+ .pme_code = 0x130e3,
.pme_short_desc = "Cycles MSR(EE) bit off",
.pme_long_desc = "Cycles MSR(EE) bit was off indicating that interrupts due to external exceptions were masked.",
- .pme_event_ids = { 35, 34, 34, 35, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000080000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_EE_OFF],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_EE_OFF]
},
-#define POWER5p_PME_PM_IERAT_XLATE_WR_LP 108
[ POWER5p_PME_PM_IERAT_XLATE_WR_LP ] = {
.pme_name = "PM_IERAT_XLATE_WR_LP",
+ .pme_code = 0x210c6,
.pme_short_desc = "Large page translation written to ierat",
.pme_long_desc = "An entry was written into the IERAT as a result of an IERAT miss. This event can be used to count IERAT misses. An ERAT miss that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed.",
- .pme_event_ids = { 114, 112, 111, 111, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_IERAT_XLATE_WR_LP],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_IERAT_XLATE_WR_LP]
},
-#define POWER5p_PME_PM_DTLB_REF_64K 109
[ POWER5p_PME_PM_DTLB_REF_64K ] = {
.pme_name = "PM_DTLB_REF_64K",
+ .pme_code = 0x2c2086,
.pme_short_desc = "Data TLB reference for 64K page",
.pme_long_desc = "Data TLB references for 64KB pages. Includes hits + misses.",
- .pme_event_ids = { -1, 33, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000800000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DTLB_REF_64K],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DTLB_REF_64K]
},
-#define POWER5p_PME_PM_MEM_RQ_DISP_Q4to7 110
[ POWER5p_PME_PM_MEM_RQ_DISP_Q4to7 ] = {
.pme_name = "PM_MEM_RQ_DISP_Q4to7",
+ .pme_code = 0x712c6,
.pme_short_desc = "Memory read queue dispatched to queues 4-7",
.pme_long_desc = "A memory operation was dispatched to read queue 4,5,6 or 7. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 262, 259, 258, 257, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0002000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_RQ_DISP_Q4to7],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_RQ_DISP_Q4to7]
},
-#define POWER5p_PME_PM_MEM_FAST_PATH_RD_DISP 111
[ POWER5p_PME_PM_MEM_FAST_PATH_RD_DISP ] = {
.pme_name = "PM_MEM_FAST_PATH_RD_DISP",
+ .pme_code = 0x731e6,
.pme_short_desc = "Fast path memory read dispatched",
.pme_long_desc = "Fast path memory read dispatched",
- .pme_event_ids = { 251, 354, 246, 245, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_FAST_PATH_RD_DISP],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_FAST_PATH_RD_DISP]
},
-#define POWER5p_PME_PM_INST_FROM_L3 112
[ POWER5p_PME_PM_INST_FROM_L3 ] = {
.pme_name = "PM_INST_FROM_L3",
+ .pme_code = 0x12208d,
.pme_short_desc = "Instruction fetched from L3",
.pme_long_desc = "An instruction fetch group was fetched from the local L3. Fetch groups can contain up to 8 instructions",
- .pme_event_ids = { 121, -1, 116, -1, -1, -1 },
- .pme_group_vector = {
- 0x0080000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L3],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L3]
},
-#define POWER5p_PME_PM_ITLB_MISS 113
[ POWER5p_PME_PM_ITLB_MISS ] = {
.pme_name = "PM_ITLB_MISS",
+ .pme_code = 0x800c0,
.pme_short_desc = "Instruction TLB misses",
.pme_long_desc = "A TLB miss for an Instruction Fetch has occurred",
- .pme_event_ids = { 124, 121, 120, 119, -1, -1 },
- .pme_group_vector = {
- 0x0000000000200000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000080ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_ITLB_MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_ITLB_MISS]
},
-#define POWER5p_PME_PM_FXU1_BUSY_FXU0_IDLE 114
[ POWER5p_PME_PM_FXU1_BUSY_FXU0_IDLE ] = {
.pme_name = "PM_FXU1_BUSY_FXU0_IDLE",
+ .pme_code = 0x400012,
.pme_short_desc = "FXU1 busy FXU0 idle",
.pme_long_desc = "FXU0 was idle while FXU1 was busy.",
- .pme_event_ids = { -1, -1, -1, 95, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000020000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FXU1_BUSY_FXU0_IDLE],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FXU1_BUSY_FXU0_IDLE]
},
-#define POWER5p_PME_PM_DTLB_REF_4K 115
[ POWER5p_PME_PM_DTLB_REF_4K ] = {
.pme_name = "PM_DTLB_REF_4K",
+ .pme_code = 0x1c2086,
.pme_short_desc = "Data TLB reference for 4K page",
.pme_long_desc = "Data TLB references for 4KB pages. Includes hits + misses.",
- .pme_event_ids = { 34, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000800000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DTLB_REF_4K],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DTLB_REF_4K]
},
-#define POWER5p_PME_PM_FXLS_FULL_CYC 116
[ POWER5p_PME_PM_FXLS_FULL_CYC ] = {
.pme_name = "PM_FXLS_FULL_CYC",
+ .pme_code = 0x1110a8,
.pme_short_desc = "Cycles FXLS queue is full",
.pme_long_desc = "Cycles when the issue queues for one or both FXU/LSU units is full. Use with caution since this is the sum of cycles when Unit 0 was full plus Unit 1 full. It does not indicate when both units were full.",
- .pme_event_ids = { 93, -1, -1, 93, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000040000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FXLS_FULL_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FXLS_FULL_CYC]
},
-#define POWER5p_PME_PM_GRP_DISP_VALID 117
[ POWER5p_PME_PM_GRP_DISP_VALID ] = {
.pme_name = "PM_GRP_DISP_VALID",
+ .pme_code = 0x120e3,
.pme_short_desc = "Group dispatch valid",
.pme_long_desc = "A group is available for dispatch. This does not mean it was successfully dispatched.",
- .pme_event_ids = { 105, 105, 104, 104, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000004ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_DISP_VALID],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_DISP_VALID]
},
-#define POWER5p_PME_PM_LSU_FLUSH_UST 118
[ POWER5p_PME_PM_LSU_FLUSH_UST ] = {
.pme_name = "PM_LSU_FLUSH_UST",
+ .pme_code = 0x2c0088,
.pme_short_desc = "SRQ unaligned store flushes",
.pme_long_desc = "A store was flushed because it was unaligned (crossed a 4K boundary). Combined Unit 0 + 1.",
- .pme_event_ids = { -1, 233, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000002100000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_FLUSH_UST],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_FLUSH_UST]
},
-#define POWER5p_PME_PM_FXU1_FIN 119
[ POWER5p_PME_PM_FXU1_FIN ] = {
.pme_name = "PM_FXU1_FIN",
+ .pme_code = 0x130e6,
.pme_short_desc = "FXU1 produced a result",
.pme_long_desc = "The Fixed Point unit 1 finished an instruction and produced a result. Instructions that finish may not necessary complete.",
- .pme_event_ids = { 95, 92, 92, 96, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000080000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FXU1_FIN],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FXU1_FIN]
},
-#define POWER5p_PME_PM_THRD_PRIO_4_CYC 120
[ POWER5p_PME_PM_THRD_PRIO_4_CYC ] = {
.pme_name = "PM_THRD_PRIO_4_CYC",
+ .pme_code = 0x420e3,
.pme_short_desc = "Cycles thread running at priority level 4",
.pme_long_desc = "Cycles this thread was running at priority level 4.",
- .pme_event_ids = { 337, 332, 330, 326, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000100000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_4_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_4_CYC]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD 121
[ POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD ] = {
.pme_name = "PM_MRK_DATA_FROM_L35_MOD",
+ .pme_code = 0x2c709e,
.pme_short_desc = "Marked data loaded from L3.5 modified",
.pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on the same module as this processor is located due to a marked load.",
- .pme_event_ids = { -1, 273, 268, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0200000000000000ULL,
- 0x0000000400000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD]
},
-#define POWER5p_PME_PM_4INST_CLB_CYC 122
[ POWER5p_PME_PM_4INST_CLB_CYC ] = {
.pme_name = "PM_4INST_CLB_CYC",
+ .pme_code = 0x400c4,
.pme_short_desc = "Cycles 4 instructions in CLB",
.pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.",
- .pme_event_ids = { 5, 4, 4, 5, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000080000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_4INST_CLB_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_4INST_CLB_CYC]
},
-#define POWER5p_PME_PM_MRK_DTLB_REF_16M 123
[ POWER5p_PME_PM_MRK_DTLB_REF_16M ] = {
.pme_name = "PM_MRK_DTLB_REF_16M",
+ .pme_code = 0x3c6086,
.pme_short_desc = "Marked Data TLB reference for 16M page",
.pme_long_desc = "Data TLB references by a marked instruction for 16MB pages.",
- .pme_event_ids = { -1, -1, 275, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x4000000000000000ULL,
- 0x0000050000000002ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DTLB_REF_16M],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DTLB_REF_16M]
},
-#define POWER5p_PME_PM_INST_FROM_L375_MOD 124
[ POWER5p_PME_PM_INST_FROM_L375_MOD ] = {
.pme_name = "PM_INST_FROM_L375_MOD",
+ .pme_code = 0x42209d,
.pme_short_desc = "Instruction fetched from L3.75 modified",
.pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L3 of a chip on a different module than this processor is located. Fetch groups can contain up to 8 instructions",
- .pme_event_ids = { -1, -1, -1, 116, -1, -1 },
- .pme_group_vector = {
- 0x0400000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L375_MOD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L375_MOD]
},
-#define POWER5p_PME_PM_GRP_CMPL 125
[ POWER5p_PME_PM_GRP_CMPL ] = {
.pme_name = "PM_GRP_CMPL",
+ .pme_code = 0x300013,
.pme_short_desc = "Group completed",
.pme_long_desc = "A group completed. Microcoded instructions that span multiple groups will generate this event once per group.",
- .pme_event_ids = { -1, -1, 100, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000002ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_CMPL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_CMPL]
},
-#define POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_ADDR 126
[ POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_ADDR ] = {
.pme_name = "PM_L2SC_RCST_DISP_FAIL_ADDR",
+ .pme_code = 0x712c2,
.pme_short_desc = "L2 slice C RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ",
.pme_long_desc = "A Read/Claim dispatch for a store failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.",
- .pme_event_ids = { 167, 164, 163, 162, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000040ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_ADDR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_ADDR]
},
-#define POWER5p_PME_PM_FPU1_1FLOP 127
[ POWER5p_PME_PM_FPU1_1FLOP ] = {
.pme_name = "PM_FPU1_1FLOP",
+ .pme_code = 0xc7,
.pme_short_desc = "FPU1 executed add",
.pme_long_desc = " mult",
- .pme_event_ids = { 72, 71, 71, 73, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000008000000ULL,
- 0x0000000000002000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_1FLOP],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_1FLOP]
},
-#define POWER5p_PME_PM_FPU_FRSP_FCONV 128
[ POWER5p_PME_PM_FPU_FRSP_FCONV ] = {
.pme_name = "PM_FPU_FRSP_FCONV",
+ .pme_code = 0x2010a8,
.pme_short_desc = "FPU executed FRSP or FCONV instructions",
.pme_long_desc = "The floating point unit has executed a frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.",
- .pme_event_ids = { -1, 85, 85, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000040000ULL,
- 0x0000000000010000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_FRSP_FCONV],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_FRSP_FCONV]
},
-#define POWER5p_PME_PM_L3SC_REF 129
[ POWER5p_PME_PM_L3SC_REF ] = {
.pme_name = "PM_L3SC_REF",
+ .pme_code = 0x701c5,
.pme_short_desc = "L3 slice C references",
.pme_long_desc = "Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice.",
- .pme_event_ids = { 195, 192, 191, 190, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000010000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SC_REF],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SC_REF]
},
-#define POWER5p_PME_PM_5INST_CLB_CYC 130
[ POWER5p_PME_PM_5INST_CLB_CYC ] = {
.pme_name = "PM_5INST_CLB_CYC",
+ .pme_code = 0x400c5,
.pme_short_desc = "Cycles 5 instructions in CLB",
.pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.",
- .pme_event_ids = { 6, 5, 5, 6, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000010ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_5INST_CLB_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_5INST_CLB_CYC]
},
-#define POWER5p_PME_PM_THRD_L2MISS_BOTH_CYC 131
[ POWER5p_PME_PM_THRD_L2MISS_BOTH_CYC ] = {
.pme_name = "PM_THRD_L2MISS_BOTH_CYC",
+ .pme_code = 0x410c7,
.pme_short_desc = "Cycles both threads in L2 misses",
.pme_long_desc = "Cycles that both threads have L2 miss pending. If only one thread has a L2 miss pending the other thread is given priority at decode. If both threads have L2 miss pending decode priority is determined by the number of GCT entries used.",
- .pme_event_ids = { 332, 328, 326, 322, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000001000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_L2MISS_BOTH_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_L2MISS_BOTH_CYC]
},
-#define POWER5p_PME_PM_MEM_PW_GATH 132
[ POWER5p_PME_PM_MEM_PW_GATH ] = {
.pme_name = "PM_MEM_PW_GATH",
+ .pme_code = 0x714c6,
.pme_short_desc = "Memory partial-write gathered",
.pme_long_desc = "Two or more partial-writes have been merged into a single memory write. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 259, 258, 254, 253, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0008000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_PW_GATH],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_PW_GATH]
},
-#define POWER5p_PME_PM_DTLB_REF_16G 133
[ POWER5p_PME_PM_DTLB_REF_16G ] = {
.pme_name = "PM_DTLB_REF_16G",
+ .pme_code = 0x4c2086,
.pme_short_desc = "Data TLB reference for 16G page",
.pme_long_desc = "Data TLB references for 16GB pages. Includes hits + misses.",
- .pme_event_ids = { -1, -1, -1, 34, -1, -1 },
- .pme_group_vector = {
- 0x0000800000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DTLB_REF_16G],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DTLB_REF_16G]
},
-#define POWER5p_PME_PM_FAB_DCLAIM_ISSUED 134
[ POWER5p_PME_PM_FAB_DCLAIM_ISSUED ] = {
.pme_name = "PM_FAB_DCLAIM_ISSUED",
+ .pme_code = 0x720e7,
.pme_short_desc = "dclaim issued",
.pme_long_desc = "A DCLAIM command was issued. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.",
- .pme_event_ids = { 39, 38, 38, 40, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000010000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_DCLAIM_ISSUED],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_DCLAIM_ISSUED]
},
-#define POWER5p_PME_PM_FAB_PNtoNN_SIDECAR 135
[ POWER5p_PME_PM_FAB_PNtoNN_SIDECAR ] = {
.pme_name = "PM_FAB_PNtoNN_SIDECAR",
+ .pme_code = 0x713c7,
.pme_short_desc = "PN to NN beat went to sidecar first",
.pme_long_desc = "Fabric Data beats that the base chip takes the inbound PN data and forwards it on to the outbound NN data bus after going into a sidecar first. The signal is delivered at FBC speed and the count must be scaled.",
- .pme_event_ids = { 48, 47, 47, 49, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000040000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_PNtoNN_SIDECAR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_PNtoNN_SIDECAR]
},
-#define POWER5p_PME_PM_GRP_IC_MISS 136
[ POWER5p_PME_PM_GRP_IC_MISS ] = {
.pme_name = "PM_GRP_IC_MISS",
+ .pme_code = 0x120e7,
.pme_short_desc = "Group experienced I cache miss",
.pme_long_desc = "Number of groups, counted at dispatch, that have encountered an icache miss redirect. Every group constructed from a fetch group that missed the instruction cache will count.",
- .pme_event_ids = { 106, 106, 105, 105, -1, -1 },
- .pme_group_vector = {
- 0x0000010000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_IC_MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_IC_MISS]
},
-#define POWER5p_PME_PM_INST_FROM_L35_SHR 137
[ POWER5p_PME_PM_INST_FROM_L35_SHR ] = {
.pme_name = "PM_INST_FROM_L35_SHR",
+ .pme_code = 0x12209d,
.pme_short_desc = "Instruction fetched from L3.5 shared",
.pme_long_desc = "An instruction fetch group was fetched with shared (S) data from the L3 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions",
- .pme_event_ids = { 122, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0400000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L35_SHR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L35_SHR]
},
-#define POWER5p_PME_PM_LSU_LMQ_FULL_CYC 138
[ POWER5p_PME_PM_LSU_LMQ_FULL_CYC ] = {
.pme_name = "PM_LSU_LMQ_FULL_CYC",
+ .pme_code = 0xc30e7,
.pme_short_desc = "Cycles LMQ full",
.pme_long_desc = "The Load Miss Queue was full.",
- .pme_event_ids = { 237, 234, 232, 231, -1, -1 },
- .pme_group_vector = {
- 0x0000000200000400ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_LMQ_FULL_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_LMQ_FULL_CYC]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_L2_CYC 139
[ POWER5p_PME_PM_MRK_DATA_FROM_L2_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L2_CYC",
+ .pme_code = 0x2c70a0,
.pme_short_desc = "Marked load latency from L2",
.pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
- .pme_event_ids = { -1, 272, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0080000000000000ULL,
- 0x0008000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L2_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L2_CYC]
},
-#define POWER5p_PME_PM_LSU_SRQ_SYNC_CYC 140
[ POWER5p_PME_PM_LSU_SRQ_SYNC_CYC ] = {
.pme_name = "PM_LSU_SRQ_SYNC_CYC",
+ .pme_code = 0x830e5,
.pme_short_desc = "SRQ sync duration",
.pme_long_desc = "Cycles that a sync instruction is active in the Store Request Queue.",
- .pme_event_ids = { 249, 248, 244, 243, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000100ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_SRQ_SYNC_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_SRQ_SYNC_CYC]
},
-#define POWER5p_PME_PM_LSU0_BUSY_REJECT 141
[ POWER5p_PME_PM_LSU0_BUSY_REJECT ] = {
.pme_name = "PM_LSU0_BUSY_REJECT",
+ .pme_code = 0xc20e1,
.pme_short_desc = "LSU0 busy due to reject",
.pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions.",
- .pme_event_ids = { 205, 201, 201, 200, -1, -1 },
- .pme_group_vector = {
- 0x0000004000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_BUSY_REJECT],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_BUSY_REJECT]
},
-#define POWER5p_PME_PM_LSU_REJECT_ERAT_MISS 142
[ POWER5p_PME_PM_LSU_REJECT_ERAT_MISS ] = {
.pme_name = "PM_LSU_REJECT_ERAT_MISS",
+ .pme_code = 0x1c4090,
.pme_short_desc = "LSU reject due to ERAT miss",
.pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions due to an ERAT miss. Combined unit 0 + 1. Requests that miss the Derat are rejected and retried until the request hits in the Erat.",
- .pme_event_ids = { 244, -1, -1, 238, -1, -1 },
- .pme_group_vector = {
- 0x0000000000008000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_REJECT_ERAT_MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_REJECT_ERAT_MISS]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_RMEM_CYC 143
[ POWER5p_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_RMEM_CYC",
+ .pme_code = 0x4c70a1,
.pme_short_desc = "Marked load latency from remote memory",
.pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
- .pme_event_ids = { -1, -1, -1, 272, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0400000000000000ULL,
- 0x0000000800000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_RMEM_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_RMEM_CYC]
},
-#define POWER5p_PME_PM_DATA_FROM_L375_SHR 144
[ POWER5p_PME_PM_DATA_FROM_L375_SHR ] = {
.pme_name = "PM_DATA_FROM_L375_SHR",
+ .pme_code = 0x3c309e,
.pme_short_desc = "Data loaded from L3.75 shared",
.pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on a different module than this processor is located due to a demand load.",
- .pme_event_ids = { -1, -1, 22, -1, -1, -1 },
- .pme_group_vector = {
- 0x0040000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_L375_SHR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_L375_SHR]
},
-#define POWER5p_PME_PM_PTEG_FROM_L25_MOD 145
[ POWER5p_PME_PM_PTEG_FROM_L25_MOD ] = {
.pme_name = "PM_PTEG_FROM_L25_MOD",
+ .pme_code = 0x283097,
.pme_short_desc = "PTEG loaded from L2.5 modified",
.pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L2 of a chip on the same module as this processor is located due to a demand load.",
- .pme_event_ids = { -1, 303, 298, -1, -1, -1 },
- .pme_group_vector = {
- 0x0800000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_L25_MOD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_L25_MOD]
},
-#define POWER5p_PME_PM_FPU0_FMOV_FEST 146
[ POWER5p_PME_PM_FPU0_FMOV_FEST ] = {
.pme_name = "PM_FPU0_FMOV_FEST",
+ .pme_code = 0x10c0,
.pme_short_desc = "FPU0 executed FMOV or FEST instructions",
.pme_long_desc = "FPU0 has executed a move kind of instruction or one of the estimate instructions. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ.",
- .pme_event_ids = { 64, 63, 63, 65, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000400000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_FMOV_FEST],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_FMOV_FEST]
},
-#define POWER5p_PME_PM_THRD_PRIO_7_CYC 147
[ POWER5p_PME_PM_THRD_PRIO_7_CYC ] = {
.pme_name = "PM_THRD_PRIO_7_CYC",
+ .pme_code = 0x420e6,
.pme_short_desc = "Cycles thread running at priority level 7",
.pme_long_desc = "Cycles this thread was running at priority level 7.",
- .pme_event_ids = { 340, 335, 333, 329, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000100000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_7_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_7_CYC]
},
-#define POWER5p_PME_PM_LSU1_FLUSH_SRQ 148
[ POWER5p_PME_PM_LSU1_FLUSH_SRQ ] = {
.pme_name = "PM_LSU1_FLUSH_SRQ",
+ .pme_code = 0xc00c7,
.pme_short_desc = "LSU1 SRQ lhs flushes",
.pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { 221, 217, 217, 216, -1, -1 },
- .pme_group_vector = {
- 0x0000000001000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_FLUSH_SRQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_FLUSH_SRQ]
},
-#define POWER5p_PME_PM_LD_REF_L1_LSU0 149
[ POWER5p_PME_PM_LD_REF_L1_LSU0 ] = {
.pme_name = "PM_LD_REF_L1_LSU0",
+ .pme_code = 0xc10c0,
.pme_short_desc = "LSU0 L1 D cache load references",
.pme_long_desc = "Load references to Level 1 Data Cache, by unit 0.",
- .pme_event_ids = { 202, 198, 198, 197, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LD_REF_L1_LSU0],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LD_REF_L1_LSU0]
},
-#define POWER5p_PME_PM_L2SC_RCST_DISP 150
[ POWER5p_PME_PM_L2SC_RCST_DISP ] = {
.pme_name = "PM_L2SC_RCST_DISP",
+ .pme_code = 0x702c2,
.pme_short_desc = "L2 slice C RC store dispatch attempt",
.pme_long_desc = "A Read/Claim dispatch for a Store was attempted.",
- .pme_event_ids = { 166, 163, 162, 161, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000040ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_RCST_DISP],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_RCST_DISP]
},
-#define POWER5p_PME_PM_CMPLU_STALL_DIV 151
[ POWER5p_PME_PM_CMPLU_STALL_DIV ] = {
.pme_name = "PM_CMPLU_STALL_DIV",
+ .pme_code = 0x411099,
.pme_short_desc = "Completion stall caused by DIV instruction",
.pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point divide instruction. This is a subset of PM_CMPLU_STALL_FXU.",
- .pme_event_ids = { -1, -1, -1, 15, -1, -1 },
- .pme_group_vector = {
- 0x0000000080000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CMPLU_STALL_DIV],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CMPLU_STALL_DIV]
},
-#define POWER5p_PME_PM_MEM_RQ_DISP_Q12to15 152
[ POWER5p_PME_PM_MEM_RQ_DISP_Q12to15 ] = {
.pme_name = "PM_MEM_RQ_DISP_Q12to15",
+ .pme_code = 0x732e6,
.pme_short_desc = "Memory read queue dispatched to queues 12-15",
.pme_long_desc = "A memory operation was dispatched to read queue 12,13,14 or 15. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 359, 262, 255, 248, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_RQ_DISP_Q12to15],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_RQ_DISP_Q12to15]
},
-#define POWER5p_PME_PM_INST_FROM_L375_SHR 153
[ POWER5p_PME_PM_INST_FROM_L375_SHR ] = {
.pme_name = "PM_INST_FROM_L375_SHR",
+ .pme_code = 0x32209d,
.pme_short_desc = "Instruction fetched from L3.75 shared",
.pme_long_desc = "An instruction fetch group was fetched with shared (S) data from the L3 of a chip on a different module than this processor is located. Fetch groups can contain up to 8 instructions",
- .pme_event_ids = { -1, -1, 117, -1, -1, -1 },
- .pme_group_vector = {
- 0x0400000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L375_SHR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L375_SHR]
},
-#define POWER5p_PME_PM_ST_REF_L1 154
[ POWER5p_PME_PM_ST_REF_L1 ] = {
.pme_name = "PM_ST_REF_L1",
+ .pme_code = 0x2c10a8,
.pme_short_desc = "L1 D cache store references",
.pme_long_desc = "Store references to the Data Cache. Combined Unit 0 + 1.",
- .pme_event_ids = { -1, 323, 322, -1, -1, -1 },
- .pme_group_vector = {
- 0x0004200000000000ULL,
- 0x0000000000000000ULL,
- 0x00000000092040e0ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_ST_REF_L1],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_ST_REF_L1]
},
-#define POWER5p_PME_PM_L3SB_ALL_BUSY 155
[ POWER5p_PME_PM_L3SB_ALL_BUSY ] = {
.pme_name = "PM_L3SB_ALL_BUSY",
+ .pme_code = 0x721e4,
.pme_short_desc = "L3 slice B active for every cycle all CI/CO machines busy",
.pme_long_desc = "Cycles All Castin/Castout machines are busy.",
- .pme_event_ids = { 184, 181, 180, 179, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000004000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SB_ALL_BUSY],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SB_ALL_BUSY]
},
-#define POWER5p_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY 156
[ POWER5p_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY ] = {
.pme_name = "PM_FAB_P1toVNorNN_SIDECAR_EMPTY",
+ .pme_code = 0x711c7,
.pme_short_desc = "P1 to VN/NN sidecar empty",
.pme_long_desc = "Fabric cycles when the Plus-1 jump sidecar (sidecars for mcm to mcm data transfer) is empty. The signal is delivered at FBC speed and the count must be scaled accordingly.",
- .pme_event_ids = { 46, 45, 45, 47, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000020000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR_CYC 157
[ POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L275_SHR_CYC",
+ .pme_code = 0x2c70a3,
.pme_short_desc = "Marked load latency from L2.75 shared",
.pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
- .pme_event_ids = { -1, 271, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x1400000000000000ULL,
- 0x0000002800000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR_CYC]
},
-#define POWER5p_PME_PM_FAB_HOLDtoNN_EMPTY 158
[ POWER5p_PME_PM_FAB_HOLDtoNN_EMPTY ] = {
.pme_name = "PM_FAB_HOLDtoNN_EMPTY",
+ .pme_code = 0x722e7,
.pme_short_desc = "Hold buffer to NN empty",
.pme_long_desc = "Fabric cyles when the Next Node out hold-buffers are emtpy. The signal is delivered at FBC speed and the count must be scaled accordingly.",
- .pme_event_ids = { 41, 40, 40, 42, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000080000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_HOLDtoNN_EMPTY],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_HOLDtoNN_EMPTY]
},
-#define POWER5p_PME_PM_DATA_FROM_LMEM 159
[ POWER5p_PME_PM_DATA_FROM_LMEM ] = {
.pme_name = "PM_DATA_FROM_LMEM",
+ .pme_code = 0x2c3087,
.pme_short_desc = "Data loaded from local memory",
.pme_long_desc = "The processor's Data Cache was reloaded from memory attached to the same module this proccessor is located on.",
- .pme_event_ids = { -1, 23, 23, -1, -1, -1 },
- .pme_group_vector = {
- 0x0018000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000010000140ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_LMEM],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_LMEM]
},
-#define POWER5p_PME_PM_RUN_CYC 160
[ POWER5p_PME_PM_RUN_CYC ] = {
.pme_name = "PM_RUN_CYC",
+ .pme_code = 0x100005,
.pme_short_desc = "Run cycles",
.pme_long_desc = "Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.",
- .pme_event_ids = { 312, -1, -1, -1, -1, 0 },
- .pme_group_vector = {
- 0xffffffffffffffffULL,
- 0xffffffffffffffffULL,
- 0x0fffffffffffffffULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_RUN_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_RUN_CYC]
},
-#define POWER5p_PME_PM_PTEG_FROM_RMEM 161
[ POWER5p_PME_PM_PTEG_FROM_RMEM ] = {
.pme_name = "PM_PTEG_FROM_RMEM",
+ .pme_code = 0x1830a1,
.pme_short_desc = "PTEG loaded from remote memory",
.pme_long_desc = "A Page Table Entry was loaded into the TLB from memory attached to a different module than this proccessor is located on.",
- .pme_event_ids = { 310, -1, -1, 302, -1, -1 },
- .pme_group_vector = {
- 0x2000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_RMEM],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_RMEM]
},
-#define POWER5p_PME_PM_L2SC_RCLD_DISP 162
[ POWER5p_PME_PM_L2SC_RCLD_DISP ] = {
.pme_name = "PM_L2SC_RCLD_DISP",
+ .pme_code = 0x701c2,
.pme_short_desc = "L2 slice C RC load dispatch attempt",
.pme_long_desc = "A Read/Claim dispatch for a Load was attempted",
- .pme_event_ids = { 162, 159, 158, 157, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000020ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_RCLD_DISP],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_RCLD_DISP]
},
-#define POWER5p_PME_PM_LSU_LRQ_S0_VALID 163
[ POWER5p_PME_PM_LSU_LRQ_S0_VALID ] = {
.pme_name = "PM_LSU_LRQ_S0_VALID",
+ .pme_code = 0xc60e6,
.pme_short_desc = "LRQ slot 0 valid",
.pme_long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each).",
- .pme_event_ids = { 243, 241, 239, 237, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000080ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_LRQ_S0_VALID],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_LRQ_S0_VALID]
},
-#define POWER5p_PME_PM_LSU0_LDF 164
[ POWER5p_PME_PM_LSU0_LDF ] = {
.pme_name = "PM_LSU0_LDF",
+ .pme_code = 0xc50c0,
.pme_short_desc = "LSU0 executed Floating Point load instruction",
.pme_long_desc = "A floating point load was executed by LSU0",
- .pme_event_ids = { 211, 207, 207, 206, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000012000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_LDF],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_LDF]
},
-#define POWER5p_PME_PM_PMC3_OVERFLOW 165
[ POWER5p_PME_PM_PMC3_OVERFLOW ] = {
.pme_name = "PM_PMC3_OVERFLOW",
+ .pme_code = 0x40000a,
.pme_short_desc = "PMC3 Overflow",
.pme_long_desc = "Overflows from PMC3 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
- .pme_event_ids = { -1, -1, -1, 299, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PMC3_OVERFLOW],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PMC3_OVERFLOW]
},
-#define POWER5p_PME_PM_MRK_IMR_RELOAD 166
[ POWER5p_PME_PM_MRK_IMR_RELOAD ] = {
.pme_name = "PM_MRK_IMR_RELOAD",
+ .pme_code = 0x820e2,
.pme_short_desc = "Marked IMR reloaded",
.pme_long_desc = "A DL1 reload occurred due to marked load",
- .pme_event_ids = { 283, 284, 277, 281, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0010000000000000ULL,
- 0x0000400200000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_IMR_RELOAD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_IMR_RELOAD]
},
-#define POWER5p_PME_PM_MRK_GRP_TIMEO 167
[ POWER5p_PME_PM_MRK_GRP_TIMEO ] = {
.pme_name = "PM_MRK_GRP_TIMEO",
+ .pme_code = 0x40000b,
.pme_short_desc = "Marked group completion timeout",
.pme_long_desc = "The sampling timeout expired indicating that the previously sampled instruction is no longer in the processor",
- .pme_event_ids = { -1, -1, -1, 280, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000200000000010ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_GRP_TIMEO],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_GRP_TIMEO]
},
-#define POWER5p_PME_PM_ST_MISS_L1 168
[ POWER5p_PME_PM_ST_MISS_L1 ] = {
.pme_name = "PM_ST_MISS_L1",
+ .pme_code = 0xc10c3,
.pme_short_desc = "L1 D cache store misses",
.pme_long_desc = "A store missed the dcache. Combined Unit 0 + 1.",
- .pme_event_ids = { 327, 322, 321, 318, -1, -1 },
- .pme_group_vector = {
- 0x0004200000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000008100100ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_ST_MISS_L1],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_ST_MISS_L1]
},
-#define POWER5p_PME_PM_STOP_COMPLETION 169
[ POWER5p_PME_PM_STOP_COMPLETION ] = {
.pme_name = "PM_STOP_COMPLETION",
+ .pme_code = 0x300018,
.pme_short_desc = "Completion stopped",
.pme_long_desc = "RAS Unit has signaled completion to stop",
- .pme_event_ids = { -1, -1, 320, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_STOP_COMPLETION],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_STOP_COMPLETION]
},
-#define POWER5p_PME_PM_LSU_BUSY_REJECT 170
[ POWER5p_PME_PM_LSU_BUSY_REJECT ] = {
.pme_name = "PM_LSU_BUSY_REJECT",
+ .pme_code = 0x2c2088,
.pme_short_desc = "LSU busy due to reject",
.pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions. Combined unit 0 + 1.",
- .pme_event_ids = { -1, 227, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000002000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_BUSY_REJECT],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_BUSY_REJECT]
},
-#define POWER5p_PME_PM_ISLB_MISS 171
[ POWER5p_PME_PM_ISLB_MISS ] = {
.pme_name = "PM_ISLB_MISS",
+ .pme_code = 0x800c1,
.pme_short_desc = "Instruction SLB misses",
.pme_long_desc = "A SLB miss for an instruction fetch as occurred",
- .pme_event_ids = { 123, 120, 119, 118, -1, -1 },
- .pme_group_vector = {
- 0x0000400000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_ISLB_MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_ISLB_MISS]
},
-#define POWER5p_PME_PM_CYC 172
[ POWER5p_PME_PM_CYC ] = {
.pme_name = "PM_CYC",
+ .pme_code = 0xf,
.pme_short_desc = "Processor cycles",
.pme_long_desc = "Processor cycles",
- .pme_event_ids = { 17, 20, 16, 21, -1, -1 },
- .pme_group_vector = {
- 0x0002000040000003ULL,
- 0x0000008000000000ULL,
- 0x000000001eb40201ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CYC]
},
-#define POWER5p_PME_PM_THRD_ONE_RUN_CYC 173
[ POWER5p_PME_PM_THRD_ONE_RUN_CYC ] = {
.pme_name = "PM_THRD_ONE_RUN_CYC",
+ .pme_code = 0x10000b,
.pme_short_desc = "One of the threads in run cycles",
.pme_long_desc = "At least one thread has set its run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. This event does not respect FCWAIT.",
- .pme_event_ids = { 333, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000001000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_ONE_RUN_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_ONE_RUN_CYC]
},
-#define POWER5p_PME_PM_GRP_BR_REDIR_NONSPEC 174
[ POWER5p_PME_PM_GRP_BR_REDIR_NONSPEC ] = {
.pme_name = "PM_GRP_BR_REDIR_NONSPEC",
+ .pme_code = 0x112091,
.pme_short_desc = "Group experienced non-speculative branch redirect",
.pme_long_desc = "Number of groups, counted at completion, that have encountered a branch redirect.",
- .pme_event_ids = { 102, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000080000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_BR_REDIR_NONSPEC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_BR_REDIR_NONSPEC]
},
-#define POWER5p_PME_PM_LSU1_SRQ_STFWD 175
[ POWER5p_PME_PM_LSU1_SRQ_STFWD ] = {
.pme_name = "PM_LSU1_SRQ_STFWD",
+ .pme_code = 0xc60e5,
.pme_short_desc = "LSU1 SRQ store forwarded",
.pme_long_desc = "Data from a store instruction was forwarded to a load on unit 1. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.",
- .pme_event_ids = { 230, 226, 226, 225, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_SRQ_STFWD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_SRQ_STFWD]
},
-#define POWER5p_PME_PM_L3SC_MOD_INV 176
[ POWER5p_PME_PM_L3SC_MOD_INV ] = {
.pme_name = "PM_L3SC_MOD_INV",
+ .pme_code = 0x730e5,
.pme_short_desc = "L3 slice C transition from modified to invalid",
.pme_long_desc = "L3 snooper detects someone doing a store to a line that is truly M in this L3 (i.e. L3 going M=>I) Mu|Me are not included since they are formed due to a previous read op Tx is not included since it is considered shared at this point.",
- .pme_event_ids = { 193, 190, 189, 188, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000400ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SC_MOD_INV],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SC_MOD_INV]
},
-#define POWER5p_PME_PM_L2_PREF 177
[ POWER5p_PME_PM_L2_PREF ] = {
.pme_name = "PM_L2_PREF",
+ .pme_code = 0xc50c3,
.pme_short_desc = "L2 cache prefetches",
.pme_long_desc = "A request to prefetch data into L2 was made",
- .pme_event_ids = { 176, 173, 172, 171, -1, -1 },
- .pme_group_vector = {
- 0x0000000000006000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000200ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2_PREF],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2_PREF]
},
-#define POWER5p_PME_PM_GCT_NOSLOT_BR_MPRED 178
[ POWER5p_PME_PM_GCT_NOSLOT_BR_MPRED ] = {
.pme_name = "PM_GCT_NOSLOT_BR_MPRED",
+ .pme_code = 0x41009c,
.pme_short_desc = "No slot in GCT caused by branch mispredict",
.pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because of a branch misprediction.",
- .pme_event_ids = { -1, -1, -1, 98, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000020ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GCT_NOSLOT_BR_MPRED],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GCT_NOSLOT_BR_MPRED]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD 179
[ POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD ] = {
.pme_name = "PM_MRK_DATA_FROM_L25_MOD",
+ .pme_code = 0x2c7097,
.pme_short_desc = "Marked data loaded from L2.5 modified",
.pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 of a chip on the same module as this processor is located due to a marked load.",
- .pme_event_ids = { -1, 269, 264, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0080000000000000ULL,
- 0x0080000100000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD]
},
-#define POWER5p_PME_PM_L2SB_ST_REQ 180
[ POWER5p_PME_PM_L2SB_ST_REQ ] = {
.pme_name = "PM_L2SB_ST_REQ",
+ .pme_code = 0x723e1,
.pme_short_desc = "L2 slice B store requests",
.pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A, B, and C.",
- .pme_event_ids = { 159, 156, 155, 154, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000010ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_ST_REQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_ST_REQ]
},
-#define POWER5p_PME_PM_L2SB_MOD_INV 181
[ POWER5p_PME_PM_L2SB_MOD_INV ] = {
.pme_name = "PM_L2SB_MOD_INV",
+ .pme_code = 0x730e1,
.pme_short_desc = "L2 slice B transition from modified to invalid",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.",
- .pme_event_ids = { 144, 141, 140, 139, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000001000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_MOD_INV],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_MOD_INV]
},
-#define POWER5p_PME_PM_MRK_L1_RELOAD_VALID 182
[ POWER5p_PME_PM_MRK_L1_RELOAD_VALID ] = {
.pme_name = "PM_MRK_L1_RELOAD_VALID",
+ .pme_code = 0xc70e4,
.pme_short_desc = "Marked L1 reload data source valid",
.pme_long_desc = "The source information is valid and is for a marked load",
- .pme_event_ids = { 284, 285, 279, 282, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0040000000000000ULL,
- 0x0000000080000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_L1_RELOAD_VALID],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_L1_RELOAD_VALID]
},
-#define POWER5p_PME_PM_L3SB_HIT 183
[ POWER5p_PME_PM_L3SB_HIT ] = {
.pme_name = "PM_L3SB_HIT",
+ .pme_code = 0x711c4,
.pme_short_desc = "L3 slice B hits",
.pme_long_desc = "Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 slice",
- .pme_event_ids = { 185, 182, 181, 180, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000008000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SB_HIT],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SB_HIT]
},
-#define POWER5p_PME_PM_L2SB_SHR_MOD 184
[ POWER5p_PME_PM_L2SB_SHR_MOD ] = {
.pme_name = "PM_L2SB_SHR_MOD",
+ .pme_code = 0x700c1,
.pme_short_desc = "L2 slice B transition from shared to modified",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A, B, and C.",
- .pme_event_ids = { 157, 154, 153, 152, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000001000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_SHR_MOD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_SHR_MOD]
},
-#define POWER5p_PME_PM_EE_OFF_EXT_INT 185
[ POWER5p_PME_PM_EE_OFF_EXT_INT ] = {
.pme_name = "PM_EE_OFF_EXT_INT",
+ .pme_code = 0x130e7,
.pme_short_desc = "Cycles MSR(EE) bit off and external interrupt pending",
.pme_long_desc = "Cycles when an interrupt due to an external exception is pending but external exceptions were masked.",
- .pme_event_ids = { 36, 35, 35, 36, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0001000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_EE_OFF_EXT_INT],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_EE_OFF_EXT_INT]
},
-#define POWER5p_PME_PM_1PLUS_PPC_CMPL 186
[ POWER5p_PME_PM_1PLUS_PPC_CMPL ] = {
.pme_name = "PM_1PLUS_PPC_CMPL",
+ .pme_code = 0x100013,
.pme_short_desc = "One or more PPC instruction completed",
.pme_long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.",
- .pme_event_ids = { 2, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000002ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_1PLUS_PPC_CMPL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_1PLUS_PPC_CMPL]
},
-#define POWER5p_PME_PM_L2SC_SHR_MOD 187
[ POWER5p_PME_PM_L2SC_SHR_MOD ] = {
.pme_name = "PM_L2SC_SHR_MOD",
+ .pme_code = 0x700c2,
.pme_short_desc = "L2 slice C transition from shared to modified",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A, B, and C.",
- .pme_event_ids = { 173, 170, 169, 168, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000002000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_SHR_MOD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_SHR_MOD]
},
-#define POWER5p_PME_PM_PMC6_OVERFLOW 188
[ POWER5p_PME_PM_PMC6_OVERFLOW ] = {
.pme_name = "PM_PMC6_OVERFLOW",
+ .pme_code = 0x30001a,
.pme_short_desc = "PMC6 Overflow",
.pme_long_desc = "Overflows from PMC6 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
- .pme_event_ids = { -1, -1, 297, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PMC6_OVERFLOW],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PMC6_OVERFLOW]
},
-#define POWER5p_PME_PM_IC_PREF_INSTALL 189
[ POWER5p_PME_PM_IC_PREF_INSTALL ] = {
.pme_name = "PM_IC_PREF_INSTALL",
+ .pme_code = 0x210c7,
.pme_short_desc = "Instruction prefetched installed in prefetch buffer",
.pme_long_desc = "A prefetch buffer entry (line) is allocated but the request is not a demand fetch.",
- .pme_event_ids = { 252, 251, 108, 108, -1, -1 },
- .pme_group_vector = {
- 0x0000008000001000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_IC_PREF_INSTALL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_IC_PREF_INSTALL]
},
-#define POWER5p_PME_PM_LSU_LRQ_FULL_CYC 190
[ POWER5p_PME_PM_LSU_LRQ_FULL_CYC ] = {
.pme_name = "PM_LSU_LRQ_FULL_CYC",
+ .pme_code = 0x110c2,
.pme_short_desc = "Cycles LRQ full",
.pme_long_desc = "Cycles when the LRQ is full.",
- .pme_event_ids = { 241, 239, 237, 235, -1, -1 },
- .pme_group_vector = {
- 0x0000000200000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_LRQ_FULL_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_LRQ_FULL_CYC]
},
-#define POWER5p_PME_PM_TLB_MISS 191
[ POWER5p_PME_PM_TLB_MISS ] = {
.pme_name = "PM_TLB_MISS",
+ .pme_code = 0x180088,
.pme_short_desc = "TLB misses",
.pme_long_desc = "Total of Data TLB mises + Instruction TLB misses",
- .pme_event_ids = { 356, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000020000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000200000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_TLB_MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_TLB_MISS]
},
-#define POWER5p_PME_PM_GCT_FULL_CYC 192
[ POWER5p_PME_PM_GCT_FULL_CYC ] = {
.pme_name = "PM_GCT_FULL_CYC",
+ .pme_code = 0x100c0,
.pme_short_desc = "Cycles GCT full",
.pme_long_desc = "The Global Completion Table is completely full.",
- .pme_event_ids = { 97, 96, 94, 97, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000040ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GCT_FULL_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GCT_FULL_CYC]
},
-#define POWER5p_PME_PM_FXU_BUSY 193
[ POWER5p_PME_PM_FXU_BUSY ] = {
.pme_name = "PM_FXU_BUSY",
+ .pme_code = 0x200012,
.pme_short_desc = "FXU busy",
.pme_long_desc = "Cycles when both FXU0 and FXU1 are busy.",
- .pme_event_ids = { -1, 93, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000020000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FXU_BUSY],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FXU_BUSY]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_L3_CYC 194
[ POWER5p_PME_PM_MRK_DATA_FROM_L3_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L3_CYC",
+ .pme_code = 0x2c70a4,
.pme_short_desc = "Marked load latency from L3",
.pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
- .pme_event_ids = { -1, 276, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0200000000000000ULL,
- 0x0000000400000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L3_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L3_CYC]
},
-#define POWER5p_PME_PM_LSU_REJECT_LMQ_FULL 195
[ POWER5p_PME_PM_LSU_REJECT_LMQ_FULL ] = {
.pme_name = "PM_LSU_REJECT_LMQ_FULL",
+ .pme_code = 0x2c4088,
.pme_short_desc = "LSU reject due to LMQ full or missed data coming",
.pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all the eight entries are full, subsequent load instructions are rejected. Combined unit 0 + 1.",
- .pme_event_ids = { -1, 242, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000008000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_REJECT_LMQ_FULL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_REJECT_LMQ_FULL]
},
-#define POWER5p_PME_PM_LSU_SRQ_S0_ALLOC 196
[ POWER5p_PME_PM_LSU_SRQ_S0_ALLOC ] = {
.pme_name = "PM_LSU_SRQ_S0_ALLOC",
+ .pme_code = 0xc20e7,
.pme_short_desc = "SRQ slot 0 allocated",
.pme_long_desc = "SRQ Slot zero was allocated",
- .pme_event_ids = { 247, 245, 242, 241, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000100ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_SRQ_S0_ALLOC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_SRQ_S0_ALLOC]
},
-#define POWER5p_PME_PM_GRP_MRK 197
[ POWER5p_PME_PM_GRP_MRK ] = {
.pme_name = "PM_GRP_MRK",
+ .pme_code = 0x100014,
.pme_short_desc = "Group marked in IDU",
.pme_long_desc = "A group was sampled (marked). The group is called a marked group. One instruction within the group is tagged for detailed monitoring. The sampled instruction is called a marked instructions. Events associated with the marked instruction are annotated with the marked term.",
- .pme_event_ids = { 109, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000020000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_MRK],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_MRK]
},
-#define POWER5p_PME_PM_INST_FROM_L25_SHR 198
[ POWER5p_PME_PM_INST_FROM_L25_SHR ] = {
.pme_name = "PM_INST_FROM_L25_SHR",
+ .pme_code = 0x122096,
.pme_short_desc = "Instruction fetched from L2.5 shared",
.pme_long_desc = "An instruction fetch group was fetched with shared (T or SL) data from the L2 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions.",
- .pme_event_ids = { 119, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0200000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L25_SHR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L25_SHR]
},
-#define POWER5p_PME_PM_DC_PREF_STREAM_ALLOC 199
[ POWER5p_PME_PM_DC_PREF_STREAM_ALLOC ] = {
.pme_name = "PM_DC_PREF_STREAM_ALLOC",
+ .pme_code = 0x830e7,
.pme_short_desc = "D cache new prefetch stream allocated",
.pme_long_desc = "A new Prefetch Stream was allocated.",
- .pme_event_ids = { 29, 28, 28, 29, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000800ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DC_PREF_STREAM_ALLOC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DC_PREF_STREAM_ALLOC]
},
-#define POWER5p_PME_PM_FPU1_FIN 200
[ POWER5p_PME_PM_FPU1_FIN ] = {
.pme_name = "PM_FPU1_FIN",
+ .pme_code = 0x10c7,
.pme_short_desc = "FPU1 produced a result",
.pme_long_desc = "FPU1 finished, produced a result. This only indicates finish, not completion. Floating Point Stores are included in this count but not Floating Point Loads., ,",
- .pme_event_ids = { 76, 75, 75, 77, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000080000ULL,
- 0x000000000000a000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_FIN],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_FIN]
},
-#define POWER5p_PME_PM_BR_MPRED_TA 201
[ POWER5p_PME_PM_BR_MPRED_TA ] = {
.pme_name = "PM_BR_MPRED_TA",
+ .pme_code = 0x230e6,
.pme_short_desc = "Branch mispredictions due to target address",
.pme_long_desc = "A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.",
- .pme_event_ids = { 11, 10, 10, 11, -1, -1 },
- .pme_group_vector = {
- 0x0000020000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_BR_MPRED_TA],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_BR_MPRED_TA]
},
-#define POWER5p_PME_PM_MRK_DTLB_REF_64K 202
[ POWER5p_PME_PM_MRK_DTLB_REF_64K ] = {
.pme_name = "PM_MRK_DTLB_REF_64K",
+ .pme_code = 0x2c6086,
.pme_short_desc = "Marked Data TLB reference for 64K page",
.pme_long_desc = "Data TLB references by a marked instruction for 64KB pages.",
- .pme_event_ids = { -1, 282, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x4000000000000000ULL,
- 0x0000010000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DTLB_REF_64K],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DTLB_REF_64K]
},
-#define POWER5p_PME_PM_RUN_INST_CMPL 203
[ POWER5p_PME_PM_RUN_INST_CMPL ] = {
.pme_name = "PM_RUN_INST_CMPL",
+ .pme_code = 0x500009,
.pme_short_desc = "Run instructions completed",
.pme_long_desc = "Number of run instructions completed.",
- .pme_event_ids = { -1, -1, -1, -1, 0, -1 },
- .pme_group_vector = {
- 0xffffffffffffffffULL,
- 0xffffffffffffffffULL,
- 0x0fffffffffffffffULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_RUN_INST_CMPL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_RUN_INST_CMPL]
},
-#define POWER5p_PME_PM_CRQ_FULL_CYC 204
[ POWER5p_PME_PM_CRQ_FULL_CYC ] = {
.pme_name = "PM_CRQ_FULL_CYC",
+ .pme_code = 0x110c1,
.pme_short_desc = "Cycles CR issue queue full",
.pme_long_desc = "The issue queue that feeds the Conditional Register unit is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.",
- .pme_event_ids = { 15, 18, 14, 19, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CRQ_FULL_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CRQ_FULL_CYC]
},
-#define POWER5p_PME_PM_L2SA_RCLD_DISP 205
[ POWER5p_PME_PM_L2SA_RCLD_DISP ] = {
.pme_name = "PM_L2SA_RCLD_DISP",
+ .pme_code = 0x701c0,
.pme_short_desc = "L2 slice A RC load dispatch attempt",
.pme_long_desc = "A Read/Claim dispatch for a Load was attempted",
- .pme_event_ids = { 130, 127, 126, 125, -1, -1 },
- .pme_group_vector = {
- 0x8000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_RCLD_DISP],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_RCLD_DISP]
},
-#define POWER5p_PME_PM_SNOOP_WR_RETRY_QFULL 206
[ POWER5p_PME_PM_SNOOP_WR_RETRY_QFULL ] = {
.pme_name = "PM_SNOOP_WR_RETRY_QFULL",
+ .pme_code = 0x710c6,
.pme_short_desc = "Snoop read retry due to read queue full",
.pme_long_desc = "A snoop request for a write to memory was retried because the write queues were full. When this happens the snoop request is retried and the writes in the write reorder queue are changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 322, 317, 315, 313, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000100000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_WR_RETRY_QFULL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_WR_RETRY_QFULL]
},
-#define POWER5p_PME_PM_MRK_DTLB_REF_4K 207
[ POWER5p_PME_PM_MRK_DTLB_REF_4K ] = {
.pme_name = "PM_MRK_DTLB_REF_4K",
+ .pme_code = 0x1c6086,
.pme_short_desc = "Marked Data TLB reference for 4K page",
.pme_long_desc = "Data TLB references by a marked instruction for 4KB pages.",
- .pme_event_ids = { 280, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x4000000000000000ULL,
- 0x0002040000000002ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DTLB_REF_4K],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DTLB_REF_4K]
},
-#define POWER5p_PME_PM_LSU_SRQ_S0_VALID 208
[ POWER5p_PME_PM_LSU_SRQ_S0_VALID ] = {
.pme_name = "PM_LSU_SRQ_S0_VALID",
+ .pme_code = 0xc20e6,
.pme_short_desc = "SRQ slot 0 valid",
.pme_long_desc = "This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the SRQ is split between the two threads (16 entries each).",
- .pme_event_ids = { 248, 246, 243, 242, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000100ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_SRQ_S0_VALID],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_SRQ_S0_VALID]
},
-#define POWER5p_PME_PM_LSU0_FLUSH_LRQ 209
[ POWER5p_PME_PM_LSU0_FLUSH_LRQ ] = {
.pme_name = "PM_LSU0_FLUSH_LRQ",
+ .pme_code = 0xc00c2,
.pme_short_desc = "LSU0 LRQ flushes",
.pme_long_desc = "A load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { 207, 203, 203, 202, -1, -1 },
- .pme_group_vector = {
- 0x0000000000800000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_FLUSH_LRQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_FLUSH_LRQ]
},
-#define POWER5p_PME_PM_INST_FROM_L275_MOD 210
[ POWER5p_PME_PM_INST_FROM_L275_MOD ] = {
.pme_name = "PM_INST_FROM_L275_MOD",
+ .pme_code = 0x422096,
.pme_short_desc = "Instruction fetched from L2.75 modified",
.pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L2 on a different module than this processor is located. Fetch groups can contain up to 8 instructions",
- .pme_event_ids = { -1, -1, -1, 115, -1, -1 },
- .pme_group_vector = {
- 0x0200000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L275_MOD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L275_MOD]
},
-#define POWER5p_PME_PM_GCT_EMPTY_CYC 211
[ POWER5p_PME_PM_GCT_EMPTY_CYC ] = {
.pme_name = "PM_GCT_EMPTY_CYC",
+ .pme_code = 0x200004,
.pme_short_desc = "Cycles GCT empty",
.pme_long_desc = "The Global Completion Table is completely empty",
- .pme_event_ids = { -1, 95, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000002ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GCT_EMPTY_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GCT_EMPTY_CYC]
},
-#define POWER5p_PME_PM_LARX_LSU0 212
[ POWER5p_PME_PM_LARX_LSU0 ] = {
.pme_name = "PM_LARX_LSU0",
+ .pme_code = 0x820e7,
.pme_short_desc = "Larx executed on LSU0",
.pme_long_desc = "A larx (lwarx or ldarx) was executed on side 0 (there is no corresponding unit 1 event since larx instructions can only execute on unit 0)",
- .pme_event_ids = { 198, 195, 194, 193, -1, -1 },
- .pme_group_vector = {
- 0x0000000200000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LARX_LSU0],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LARX_LSU0]
},
-#define POWER5p_PME_PM_THRD_PRIO_DIFF_5or6_CYC 213
[ POWER5p_PME_PM_THRD_PRIO_DIFF_5or6_CYC ] = {
.pme_name = "PM_THRD_PRIO_DIFF_5or6_CYC",
+ .pme_code = 0x430e6,
.pme_short_desc = "Cycles thread priority difference is 5 or 6",
.pme_long_desc = "Cycles when this thread's priority is higher than the other thread's priority by 5 or 6.",
- .pme_event_ids = { 344, 339, 337, 333, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000200000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_DIFF_5or6_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_DIFF_5or6_CYC]
},
-#define POWER5p_PME_PM_SNOOP_RETRY_1AHEAD 214
[ POWER5p_PME_PM_SNOOP_RETRY_1AHEAD ] = {
.pme_name = "PM_SNOOP_RETRY_1AHEAD",
+ .pme_code = 0x725e6,
.pme_short_desc = "Snoop retry due to one ahead collision",
.pme_long_desc = "Snoop retry due to one ahead collision",
- .pme_event_ids = { 320, 315, 313, 311, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000200000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_RETRY_1AHEAD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_RETRY_1AHEAD]
},
-#define POWER5p_PME_PM_FPU1_FSQRT 215
[ POWER5p_PME_PM_FPU1_FSQRT ] = {
.pme_name = "PM_FPU1_FSQRT",
+ .pme_code = 0xc6,
.pme_short_desc = "FPU1 executed FSQRT instruction",
.pme_long_desc = "FPU1 has executed a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 80, 79, 79, 81, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000200000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_FSQRT],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_FSQRT]
},
-#define POWER5p_PME_PM_MRK_LD_MISS_L1_LSU1 216
[ POWER5p_PME_PM_MRK_LD_MISS_L1_LSU1 ] = {
.pme_name = "PM_MRK_LD_MISS_L1_LSU1",
+ .pme_code = 0x820e4,
.pme_short_desc = "LSU1 marked L1 D cache load misses",
.pme_long_desc = "Load references that miss the Level 1 Data cache, by LSU1.",
- .pme_event_ids = { 287, 287, 281, 284, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0040000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LD_MISS_L1_LSU1],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LD_MISS_L1_LSU1]
},
-#define POWER5p_PME_PM_MRK_FPU_FIN 217
[ POWER5p_PME_PM_MRK_FPU_FIN ] = {
.pme_name = "PM_MRK_FPU_FIN",
+ .pme_code = 0x300014,
.pme_short_desc = "Marked instruction FPU processing finished",
.pme_long_desc = "One of the Floating Point Units finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, -1, 276, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0400200000000010ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_FPU_FIN],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_FPU_FIN]
},
-#define POWER5p_PME_PM_THRD_PRIO_5_CYC 218
[ POWER5p_PME_PM_THRD_PRIO_5_CYC ] = {
.pme_name = "PM_THRD_PRIO_5_CYC",
+ .pme_code = 0x420e4,
.pme_short_desc = "Cycles thread running at priority level 5",
.pme_long_desc = "Cycles this thread was running at priority level 5.",
- .pme_event_ids = { 338, 333, 331, 327, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000400000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_5_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_5_CYC]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_LMEM 219
[ POWER5p_PME_PM_MRK_DATA_FROM_LMEM ] = {
.pme_name = "PM_MRK_DATA_FROM_LMEM",
+ .pme_code = 0x2c7087,
.pme_short_desc = "Marked data loaded from local memory",
.pme_long_desc = "The processor's Data Cache was reloaded due to a marked load from memory attached to the same module this proccessor is located on.",
- .pme_event_ids = { -1, 277, 270, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0800000000000000ULL,
- 0x0000001000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_LMEM],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_LMEM]
},
-#define POWER5p_PME_PM_SNOOP_TLBIE 220
[ POWER5p_PME_PM_SNOOP_TLBIE ] = {
.pme_name = "PM_SNOOP_TLBIE",
+ .pme_code = 0x800c3,
.pme_short_desc = "Snoop TLBIE",
.pme_long_desc = "A tlbie was snooped from another processor.",
- .pme_event_ids = { 321, 316, 314, 312, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000002000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_TLBIE],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_TLBIE]
},
-#define POWER5p_PME_PM_FPU1_FRSP_FCONV 221
[ POWER5p_PME_PM_FPU1_FRSP_FCONV ] = {
.pme_name = "PM_FPU1_FRSP_FCONV",
+ .pme_code = 0x10c5,
.pme_short_desc = "FPU1 executed FRSP or FCONV instructions",
.pme_long_desc = "FPU1 has executed a frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 79, 78, 78, 80, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000004800000ULL,
- 0x0000000000001000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_FRSP_FCONV],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_FRSP_FCONV]
},
-#define POWER5p_PME_PM_DTLB_MISS_16G 222
[ POWER5p_PME_PM_DTLB_MISS_16G ] = {
.pme_name = "PM_DTLB_MISS_16G",
+ .pme_code = 0x4c208d,
.pme_short_desc = "Data TLB miss for 16G page",
.pme_long_desc = "Data TLB references to 16GB pages that missed the TLB. Page size is determined at TLB reload time.",
- .pme_event_ids = { -1, -1, -1, 32, -1, -1 },
- .pme_group_vector = {
- 0x0001000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DTLB_MISS_16G],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DTLB_MISS_16G]
},
-#define POWER5p_PME_PM_L3SB_SNOOP_RETRY 223
[ POWER5p_PME_PM_L3SB_SNOOP_RETRY ] = {
.pme_name = "PM_L3SB_SNOOP_RETRY",
+ .pme_code = 0x731e4,
.pme_short_desc = "L3 slice B snoop retries",
.pme_long_desc = "Number of times an L3 retried a snoop because it got two in at the same time (one on snp_a, one on snp_b)",
- .pme_event_ids = { 190, 187, 186, 185, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000004000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SB_SNOOP_RETRY],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SB_SNOOP_RETRY]
},
-#define POWER5p_PME_PM_FAB_VBYPASS_EMPTY 224
[ POWER5p_PME_PM_FAB_VBYPASS_EMPTY ] = {
.pme_name = "PM_FAB_VBYPASS_EMPTY",
+ .pme_code = 0x731e7,
.pme_short_desc = "Vertical bypass buffer empty",
.pme_long_desc = "Fabric cycles when the Middle Bypass sidecar is empty. The signal is delivered at FBC speed and the count must be scaled accordingly.",
- .pme_event_ids = { 51, 50, 50, 52, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000020000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_VBYPASS_EMPTY],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_VBYPASS_EMPTY]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD 225
[ POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD ] = {
.pme_name = "PM_MRK_DATA_FROM_L275_MOD",
+ .pme_code = 0x1c70a3,
.pme_short_desc = "Marked data loaded from L2.75 modified",
.pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 on a different module than this processor is located due to a marked load.",
- .pme_event_ids = { 271, -1, -1, 265, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x1000000000000000ULL,
- 0x0001000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD]
},
-#define POWER5p_PME_PM_L2SB_RCST_DISP 226
[ POWER5p_PME_PM_L2SB_RCST_DISP ] = {
.pme_name = "PM_L2SB_RCST_DISP",
+ .pme_code = 0x702c1,
.pme_short_desc = "L2 slice B RC store dispatch attempt",
.pme_long_desc = "A Read/Claim dispatch for a Store was attempted.",
- .pme_event_ids = { 150, 147, 146, 145, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000008ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_RCST_DISP],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_RCST_DISP]
},
-#define POWER5p_PME_PM_6INST_CLB_CYC 227
[ POWER5p_PME_PM_6INST_CLB_CYC ] = {
.pme_name = "PM_6INST_CLB_CYC",
+ .pme_code = 0x400c6,
.pme_short_desc = "Cycles 6 instructions in CLB",
.pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.",
- .pme_event_ids = { 7, 6, 6, 7, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000010ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_6INST_CLB_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_6INST_CLB_CYC]
},
-#define POWER5p_PME_PM_FLUSH 228
[ POWER5p_PME_PM_FLUSH ] = {
.pme_name = "PM_FLUSH",
+ .pme_code = 0x110c7,
.pme_short_desc = "Flushes",
.pme_long_desc = "Flushes occurred including LSU and Branch flushes.",
- .pme_event_ids = { 52, 51, 51, 53, -1, -1 },
- .pme_group_vector = {
- 0x0008000000080000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FLUSH],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FLUSH]
},
-#define POWER5p_PME_PM_L2SC_MOD_INV 229
[ POWER5p_PME_PM_L2SC_MOD_INV ] = {
.pme_name = "PM_L2SC_MOD_INV",
+ .pme_code = 0x730e2,
.pme_short_desc = "L2 slice C transition from modified to invalid",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.",
- .pme_event_ids = { 160, 157, 156, 155, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000002000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_MOD_INV],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_MOD_INV]
},
-#define POWER5p_PME_PM_FPU_DENORM 230
[ POWER5p_PME_PM_FPU_DENORM ] = {
.pme_name = "PM_FPU_DENORM",
+ .pme_code = 0x102088,
.pme_short_desc = "FPU received denormalized data",
.pme_long_desc = "The floating point unit has encountered a denormalized operand. Combined Unit 0 + Unit 1.",
- .pme_event_ids = { 86, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000080000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_DENORM],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_DENORM]
},
-#define POWER5p_PME_PM_L3SC_HIT 231
[ POWER5p_PME_PM_L3SC_HIT ] = {
.pme_name = "PM_L3SC_HIT",
+ .pme_code = 0x711c5,
.pme_short_desc = "L3 slice C hits",
.pme_long_desc = "Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 Slice",
- .pme_event_ids = { 192, 189, 188, 187, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000010000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SC_HIT],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SC_HIT]
},
-#define POWER5p_PME_PM_SNOOP_WR_RETRY_RQ 232
[ POWER5p_PME_PM_SNOOP_WR_RETRY_RQ ] = {
.pme_name = "PM_SNOOP_WR_RETRY_RQ",
+ .pme_code = 0x706c6,
.pme_short_desc = "Snoop write/dclaim retry due to collision with active read queue",
.pme_long_desc = "A snoop request for a write or dclaim to memory was retried because it matched the cacheline of an active read. This event is sent from the Memory Controller clock domain and must be scaled accordingly",
- .pme_event_ids = { 323, 318, 316, 314, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000400000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_WR_RETRY_RQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_WR_RETRY_RQ]
},
-#define POWER5p_PME_PM_LSU1_REJECT_SRQ 233
[ POWER5p_PME_PM_LSU1_REJECT_SRQ ] = {
.pme_name = "PM_LSU1_REJECT_SRQ",
+ .pme_code = 0xc40c4,
.pme_short_desc = "LSU1 SRQ lhs rejects",
.pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because of Load Hit Store conditions. Loads are rejected when data is needed from a previous store instruction but store forwarding is not possible because the data is not fully contained in the Store Data Queue or is not yet available in the Store Data Queue.",
- .pme_event_ids = { 229, 225, 225, 224, -1, -1 },
- .pme_group_vector = {
- 0x0000000000004000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_REJECT_SRQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_REJECT_SRQ]
},
-#define POWER5p_PME_PM_L3SC_ALL_BUSY 234
[ POWER5p_PME_PM_L3SC_ALL_BUSY ] = {
.pme_name = "PM_L3SC_ALL_BUSY",
+ .pme_code = 0x721e5,
.pme_short_desc = "L3 slice C active for every cycle all CI/CO machines busy",
.pme_long_desc = "Cycles All Castin/Castout machines are busy.",
- .pme_event_ids = { 191, 188, 187, 186, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000010000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SC_ALL_BUSY],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SC_ALL_BUSY]
},
-#define POWER5p_PME_PM_IC_PREF_REQ 235
[ POWER5p_PME_PM_IC_PREF_REQ ] = {
.pme_name = "PM_IC_PREF_REQ",
+ .pme_code = 0x220e6,
.pme_short_desc = "Instruction prefetch requests",
.pme_long_desc = "An instruction prefetch request has been made.",
- .pme_event_ids = { 112, 110, 109, 109, -1, -1 },
- .pme_group_vector = {
- 0x0000008000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000200ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_IC_PREF_REQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_IC_PREF_REQ]
},
-#define POWER5p_PME_PM_MRK_GRP_IC_MISS 236
[ POWER5p_PME_PM_MRK_GRP_IC_MISS ] = {
.pme_name = "PM_MRK_GRP_IC_MISS",
+ .pme_code = 0x412091,
.pme_short_desc = "Group experienced marked I cache miss",
.pme_long_desc = "A group containing a marked (sampled) instruction experienced an instruction cache miss.",
- .pme_event_ids = { -1, -1, -1, 279, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0040000000000000ULL,
- 0x0000000080000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_GRP_IC_MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_GRP_IC_MISS]
},
-#define POWER5p_PME_PM_GCT_NOSLOT_IC_MISS 237
[ POWER5p_PME_PM_GCT_NOSLOT_IC_MISS ] = {
.pme_name = "PM_GCT_NOSLOT_IC_MISS",
+ .pme_code = 0x21009c,
.pme_short_desc = "No slot in GCT caused by I cache miss",
.pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because of an Instruction Cache miss.",
- .pme_event_ids = { -1, 97, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000020ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GCT_NOSLOT_IC_MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GCT_NOSLOT_IC_MISS]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_L3 238
[ POWER5p_PME_PM_MRK_DATA_FROM_L3 ] = {
.pme_name = "PM_MRK_DATA_FROM_L3",
+ .pme_code = 0x1c708e,
.pme_short_desc = "Marked data loaded from L3",
.pme_long_desc = "The processor's Data Cache was reloaded from the local L3 due to a marked load.",
- .pme_event_ids = { 272, -1, 267, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0200000000000000ULL,
- 0x0000400000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L3],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L3]
},
-#define POWER5p_PME_PM_GCT_NOSLOT_SRQ_FULL 239
[ POWER5p_PME_PM_GCT_NOSLOT_SRQ_FULL ] = {
.pme_name = "PM_GCT_NOSLOT_SRQ_FULL",
+ .pme_code = 0x310084,
.pme_short_desc = "No slot in GCT caused by SRQ full",
.pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because the Store Request Queue (SRQ) is full. This happens when the storage subsystem can not process the stores in the SRQ. Groups can not be dispatched until a SRQ entry is available.",
- .pme_event_ids = { -1, -1, 95, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000020ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GCT_NOSLOT_SRQ_FULL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GCT_NOSLOT_SRQ_FULL]
},
-#define POWER5p_PME_PM_CMPLU_STALL_DCACHE_MISS 240
[ POWER5p_PME_PM_CMPLU_STALL_DCACHE_MISS ] = {
.pme_name = "PM_CMPLU_STALL_DCACHE_MISS",
+ .pme_code = 0x21109a,
.pme_short_desc = "Completion stall caused by D cache miss",
.pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a Data Cache Miss. Data Cache Miss has higher priority than any other Load/Store delay, so if an instruction encounters multiple delays only the Data Cache Miss will be reported and the entire delay period will be charged to Data Cache Miss. This is a subset of PM_CMPLU_STALL_LSU.",
- .pme_event_ids = { -1, 14, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000040000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CMPLU_STALL_DCACHE_MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CMPLU_STALL_DCACHE_MISS]
},
-#define POWER5p_PME_PM_THRD_SEL_OVER_ISU_HOLD 241
[ POWER5p_PME_PM_THRD_SEL_OVER_ISU_HOLD ] = {
.pme_name = "PM_THRD_SEL_OVER_ISU_HOLD",
+ .pme_code = 0x410c5,
.pme_short_desc = "Thread selection overrides caused by ISU holds",
.pme_long_desc = "Thread selection was overridden because of an ISU hold.",
- .pme_event_ids = { 350, 345, 343, 339, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000008000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_SEL_OVER_ISU_HOLD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_SEL_OVER_ISU_HOLD]
},
-#define POWER5p_PME_PM_LSU_FLUSH_LRQ 242
[ POWER5p_PME_PM_LSU_FLUSH_LRQ ] = {
.pme_name = "PM_LSU_FLUSH_LRQ",
+ .pme_code = 0x2c0090,
.pme_short_desc = "LRQ flushes",
.pme_long_desc = "A load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. Combined Units 0 and 1.",
- .pme_event_ids = { -1, 230, 229, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000400000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_FLUSH_LRQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_FLUSH_LRQ]
},
-#define POWER5p_PME_PM_THRD_PRIO_2_CYC 243
[ POWER5p_PME_PM_THRD_PRIO_2_CYC ] = {
.pme_name = "PM_THRD_PRIO_2_CYC",
+ .pme_code = 0x420e1,
.pme_short_desc = "Cycles thread running at priority level 2",
.pme_long_desc = "Cycles this thread was running at priority level 2.",
- .pme_event_ids = { 335, 330, 328, 324, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000400000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_2_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_2_CYC]
},
-#define POWER5p_PME_PM_L3SA_MOD_INV 244
[ POWER5p_PME_PM_L3SA_MOD_INV ] = {
.pme_name = "PM_L3SA_MOD_INV",
+ .pme_code = 0x730e3,
.pme_short_desc = "L3 slice A transition from modified to invalid",
.pme_long_desc = "L3 snooper detects someone doing a store to a line that is truly M in this L3 (i.e. L3 going M=>I) Mu|Me are not included since they are formed due to a prev read op. Tx is not included since it is considered shared at this point.",
- .pme_event_ids = { 179, 176, 175, 174, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000100ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SA_MOD_INV],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SA_MOD_INV]
},
-#define POWER5p_PME_PM_LSU_FLUSH_SRQ 245
[ POWER5p_PME_PM_LSU_FLUSH_SRQ ] = {
.pme_name = "PM_LSU_FLUSH_SRQ",
+ .pme_code = 0x1c0090,
.pme_short_desc = "SRQ flushes",
.pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. Combined Unit 0 + 1.",
- .pme_event_ids = { 233, -1, -1, 228, -1, -1 },
- .pme_group_vector = {
- 0x0000000000400000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_FLUSH_SRQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_FLUSH_SRQ]
},
-#define POWER5p_PME_PM_MRK_LSU_SRQ_INST_VALID 246
[ POWER5p_PME_PM_MRK_LSU_SRQ_INST_VALID ] = {
.pme_name = "PM_MRK_LSU_SRQ_INST_VALID",
+ .pme_code = 0xc70e6,
.pme_short_desc = "Marked instruction valid in SRQ",
.pme_long_desc = "This signal is asserted every cycle when a marked request is resident in the Store Request Queue",
- .pme_event_ids = { 297, 297, 292, 296, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000010ULL,
- 0x0000000000000000ULL,
- 0x0200000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU_SRQ_INST_VALID],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU_SRQ_INST_VALID]
},
-#define POWER5p_PME_PM_L3SA_REF 247
[ POWER5p_PME_PM_L3SA_REF ] = {
.pme_name = "PM_L3SA_REF",
+ .pme_code = 0x701c3,
.pme_short_desc = "L3 slice A references",
.pme_long_desc = "Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice",
- .pme_event_ids = { 181, 178, 177, 176, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000008000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SA_REF],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SA_REF]
},
-#define POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL 248
[ POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL ] = {
.pme_name = "PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL",
+ .pme_code = 0x713c2,
.pme_short_desc = "L2 slice C RC dispatch attempt failed due to all CO busy",
.pme_long_desc = "A Read/Claim dispatch was rejected because all Castout machines were busy.",
- .pme_event_ids = { 171, 168, 167, 166, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000080ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL]
},
-#define POWER5p_PME_PM_FPU0_STALL3 249
[ POWER5p_PME_PM_FPU0_STALL3 ] = {
.pme_name = "PM_FPU0_STALL3",
+ .pme_code = 0x20e1,
.pme_short_desc = "FPU0 stalled in pipe3",
.pme_long_desc = "FPU0 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always).",
- .pme_event_ids = { 70, 69, 69, 71, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000001000000ULL,
- 0x0000000000000800ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_STALL3],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_STALL3]
},
-#define POWER5p_PME_PM_TB_BIT_TRANS 250
[ POWER5p_PME_PM_TB_BIT_TRANS ] = {
.pme_name = "PM_TB_BIT_TRANS",
+ .pme_code = 0x100018,
.pme_short_desc = "Time Base bit transition",
.pme_long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1",
- .pme_event_ids = { 331, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_TB_BIT_TRANS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_TB_BIT_TRANS]
},
-#define POWER5p_PME_PM_GPR_MAP_FULL_CYC 251
[ POWER5p_PME_PM_GPR_MAP_FULL_CYC ] = {
.pme_name = "PM_GPR_MAP_FULL_CYC",
+ .pme_code = 0x130e5,
.pme_short_desc = "Cycles GPR mapper full",
.pme_long_desc = "The General Purpose Register mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.",
- .pme_event_ids = { 100, 99, 97, 99, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GPR_MAP_FULL_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GPR_MAP_FULL_CYC]
},
-#define POWER5p_PME_PM_MRK_LSU_FLUSH_LRQ 252
[ POWER5p_PME_PM_MRK_LSU_FLUSH_LRQ ] = {
.pme_name = "PM_MRK_LSU_FLUSH_LRQ",
+ .pme_code = 0x381088,
.pme_short_desc = "Marked LRQ flushes",
.pme_long_desc = "A marked load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { -1, -1, 290, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000010000000ULL,
- 0x0000000000000000ULL,
- 0x0100000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU_FLUSH_LRQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU_FLUSH_LRQ]
},
-#define POWER5p_PME_PM_FPU0_STF 253
[ POWER5p_PME_PM_FPU0_STF ] = {
.pme_name = "PM_FPU0_STF",
+ .pme_code = 0x20e2,
.pme_short_desc = "FPU0 executed store instruction",
.pme_long_desc = "FPU0 has executed a Floating Point Store instruction.",
- .pme_event_ids = { 71, 70, 70, 72, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000010000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_STF],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_STF]
},
-#define POWER5p_PME_PM_MRK_DTLB_MISS 254
[ POWER5p_PME_PM_MRK_DTLB_MISS ] = {
.pme_name = "PM_MRK_DTLB_MISS",
+ .pme_code = 0xc50c6,
.pme_short_desc = "Marked Data TLB misses",
.pme_long_desc = "Data TLB references by a marked instruction that missed the TLB (all page sizes).",
- .pme_event_ids = { 277, 279, 272, 274, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000800000000001ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DTLB_MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DTLB_MISS]
},
-#define POWER5p_PME_PM_FPU1_FMA 255
[ POWER5p_PME_PM_FPU1_FMA ] = {
.pme_name = "PM_FPU1_FMA",
+ .pme_code = 0xc5,
.pme_short_desc = "FPU1 executed multiply-add instruction",
.pme_long_desc = "The floating point unit has executed a multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 77, 76, 76, 78, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000004000000ULL,
- 0x0000000000001000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_FMA],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_FMA]
},
-#define POWER5p_PME_PM_L2SA_MOD_TAG 256
[ POWER5p_PME_PM_L2SA_MOD_TAG ] = {
.pme_name = "PM_L2SA_MOD_TAG",
+ .pme_code = 0x720e0,
.pme_short_desc = "L2 slice A transition from modified to tagged",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.",
- .pme_event_ids = { 129, 126, 125, 124, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000800ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_MOD_TAG],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_MOD_TAG]
},
-#define POWER5p_PME_PM_LSU1_FLUSH_ULD 257
[ POWER5p_PME_PM_LSU1_FLUSH_ULD ] = {
.pme_name = "PM_LSU1_FLUSH_ULD",
+ .pme_code = 0xc00c4,
.pme_short_desc = "LSU1 unaligned load flushes",
.pme_long_desc = "A load was flushed from unit 1 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1).",
- .pme_event_ids = { 222, 218, 218, 217, -1, -1 },
- .pme_group_vector = {
- 0x0000000004000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_FLUSH_ULD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_FLUSH_ULD]
},
-#define POWER5p_PME_PM_MRK_INST_FIN 258
[ POWER5p_PME_PM_MRK_INST_FIN ] = {
.pme_name = "PM_MRK_INST_FIN",
+ .pme_code = 0x300005,
.pme_short_desc = "Marked instruction finished",
.pme_long_desc = "One of the execution units finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, -1, 278, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0020000000000000ULL,
- 0x0800000040000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_INST_FIN],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_INST_FIN]
},
-#define POWER5p_PME_PM_MRK_LSU0_FLUSH_UST 259
[ POWER5p_PME_PM_MRK_LSU0_FLUSH_UST ] = {
.pme_name = "PM_MRK_LSU0_FLUSH_UST",
+ .pme_code = 0x810c0,
.pme_short_desc = "LSU0 marked unaligned store flushes",
.pme_long_desc = "A marked store was flushed from unit 0 because it was unaligned",
- .pme_event_ids = { 291, 291, 285, 288, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0008000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU0_FLUSH_UST],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU0_FLUSH_UST]
},
-#define POWER5p_PME_PM_FPU0_FULL_CYC 260
[ POWER5p_PME_PM_FPU0_FULL_CYC ] = {
.pme_name = "PM_FPU0_FULL_CYC",
+ .pme_code = 0x100c3,
.pme_short_desc = "Cycles FPU0 issue queue full",
.pme_long_desc = "The issue queue for FPU0 cannot accept any more instruction. Dispatch to this issue queue is stopped.",
- .pme_event_ids = { 68, 67, 67, 69, -1, -1 },
- .pme_group_vector = {
- 0x0000000400000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_FULL_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_FULL_CYC]
},
-#define POWER5p_PME_PM_LSU_LRQ_S0_ALLOC 261
[ POWER5p_PME_PM_LSU_LRQ_S0_ALLOC ] = {
.pme_name = "PM_LSU_LRQ_S0_ALLOC",
+ .pme_code = 0xc60e7,
.pme_short_desc = "LRQ slot 0 allocated",
.pme_long_desc = "LRQ slot zero was allocated",
- .pme_event_ids = { 242, 240, 238, 236, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000080ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_LRQ_S0_ALLOC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_LRQ_S0_ALLOC]
},
-#define POWER5p_PME_PM_MRK_LSU1_FLUSH_ULD 262
[ POWER5p_PME_PM_MRK_LSU1_FLUSH_ULD ] = {
.pme_name = "PM_MRK_LSU1_FLUSH_ULD",
+ .pme_code = 0x810c4,
.pme_short_desc = "LSU1 marked unaligned load flushes",
.pme_long_desc = "A marked load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { 294, 294, 288, 291, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0004000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU1_FLUSH_ULD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU1_FLUSH_ULD]
},
-#define POWER5p_PME_PM_MRK_DTLB_REF 263
[ POWER5p_PME_PM_MRK_DTLB_REF ] = {
.pme_name = "PM_MRK_DTLB_REF",
+ .pme_code = 0xc60e4,
.pme_short_desc = "Marked Data TLB reference",
.pme_long_desc = "Total number of Data TLB references by a marked instruction for all page sizes. Page size is determined at TLB reload time.",
- .pme_event_ids = { 279, 281, 274, 276, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0001000000000001ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DTLB_REF],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DTLB_REF]
},
-#define POWER5p_PME_PM_BR_UNCOND 264
[ POWER5p_PME_PM_BR_UNCOND ] = {
.pme_name = "PM_BR_UNCOND",
+ .pme_code = 0x123087,
.pme_short_desc = "Unconditional branch",
.pme_long_desc = "An unconditional branch was executed.",
- .pme_event_ids = { 12, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000040000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000400ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_BR_UNCOND],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_BR_UNCOND]
},
-#define POWER5p_PME_PM_THRD_SEL_OVER_L2MISS 265
[ POWER5p_PME_PM_THRD_SEL_OVER_L2MISS ] = {
.pme_name = "PM_THRD_SEL_OVER_L2MISS",
+ .pme_code = 0x410c3,
.pme_short_desc = "Thread selection overrides caused by L2 misses",
.pme_long_desc = "Thread selection was overridden because one thread was had a L2 miss pending.",
- .pme_event_ids = { 351, 346, 344, 340, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000008000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_SEL_OVER_L2MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_SEL_OVER_L2MISS]
},
-#define POWER5p_PME_PM_L2SB_SHR_INV 266
[ POWER5p_PME_PM_L2SB_SHR_INV ] = {
.pme_name = "PM_L2SB_SHR_INV",
+ .pme_code = 0x710c1,
.pme_short_desc = "L2 slice B transition from shared to invalid",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A, B, and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.",
- .pme_event_ids = { 156, 153, 152, 151, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000001000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_SHR_INV],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_SHR_INV]
},
-#define POWER5p_PME_PM_MEM_LO_PRIO_WR_CMPL 267
[ POWER5p_PME_PM_MEM_LO_PRIO_WR_CMPL ] = {
.pme_name = "PM_MEM_LO_PRIO_WR_CMPL",
+ .pme_code = 0x736e6,
.pme_short_desc = "Low priority write completed",
.pme_long_desc = "A memory write, which was not upgraded to high priority, completed. This event is sent from the Memory Controller clock domain and must be scaled accordingly",
- .pme_event_ids = { 255, 254, 250, 249, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000400000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_LO_PRIO_WR_CMPL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_LO_PRIO_WR_CMPL]
},
-#define POWER5p_PME_PM_MRK_DTLB_MISS_64K 268
[ POWER5p_PME_PM_MRK_DTLB_MISS_64K ] = {
.pme_name = "PM_MRK_DTLB_MISS_64K",
+ .pme_code = 0x2c608d,
.pme_short_desc = "Marked Data TLB misses for 64K page",
.pme_long_desc = "Data TLB references to 64KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.",
- .pme_event_ids = { -1, 280, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x8000000000000000ULL,
- 0x0000028000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DTLB_MISS_64K],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DTLB_MISS_64K]
},
-#define POWER5p_PME_PM_MRK_ST_MISS_L1 269
[ POWER5p_PME_PM_MRK_ST_MISS_L1 ] = {
.pme_name = "PM_MRK_ST_MISS_L1",
+ .pme_code = 0x820e3,
.pme_short_desc = "Marked L1 D cache store misses",
.pme_long_desc = "A marked store missed the dcache",
- .pme_event_ids = { 300, 300, 295, 298, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0020000000000000ULL,
- 0x0040000000000008ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_ST_MISS_L1],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_ST_MISS_L1]
},
-#define POWER5p_PME_PM_L3SC_MOD_TAG 270
[ POWER5p_PME_PM_L3SC_MOD_TAG ] = {
.pme_name = "PM_L3SC_MOD_TAG",
+ .pme_code = 0x720e5,
.pme_short_desc = "L3 slice C transition from modified to TAG",
.pme_long_desc = "L3 snooper detects someone doing a read to a line that is truly M in this L3(i.e. L3 going M->T or M->I(go_Mu case); Mu|Me are not included since they are formed due to a prev read op). Tx is not included since it is considered shared at this point.",
- .pme_event_ids = { 194, 191, 190, 189, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000400ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SC_MOD_TAG],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SC_MOD_TAG]
},
-#define POWER5p_PME_PM_GRP_DISP_SUCCESS 271
[ POWER5p_PME_PM_GRP_DISP_SUCCESS ] = {
.pme_name = "PM_GRP_DISP_SUCCESS",
+ .pme_code = 0x300002,
.pme_short_desc = "Group dispatch success",
.pme_long_desc = "Number of groups sucessfully dispatched (not rejected)",
- .pme_event_ids = { -1, -1, 103, -1, -1, -1 },
- .pme_group_vector = {
- 0x4000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_DISP_SUCCESS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_DISP_SUCCESS]
},
-#define POWER5p_PME_PM_THRD_PRIO_DIFF_1or2_CYC 272
[ POWER5p_PME_PM_THRD_PRIO_DIFF_1or2_CYC ] = {
.pme_name = "PM_THRD_PRIO_DIFF_1or2_CYC",
+ .pme_code = 0x430e4,
.pme_short_desc = "Cycles thread priority difference is 1 or 2",
.pme_long_desc = "Cycles when this thread's priority is higher than the other thread's priority by 1 or 2.",
- .pme_event_ids = { 342, 337, 335, 331, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000100000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_DIFF_1or2_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_DIFF_1or2_CYC]
},
-#define POWER5p_PME_PM_IC_DEMAND_L2_BHT_REDIRECT 273
[ POWER5p_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = {
.pme_name = "PM_IC_DEMAND_L2_BHT_REDIRECT",
+ .pme_code = 0x230e0,
.pme_short_desc = "L2 I cache demand request due to BHT redirect",
.pme_long_desc = "A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict).",
- .pme_event_ids = { 110, 108, 106, 106, -1, -1 },
- .pme_group_vector = {
- 0x0000004000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_IC_DEMAND_L2_BHT_REDIRECT],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_IC_DEMAND_L2_BHT_REDIRECT]
},
-#define POWER5p_PME_PM_LSU_DERAT_MISS 274
[ POWER5p_PME_PM_LSU_DERAT_MISS ] = {
.pme_name = "PM_LSU_DERAT_MISS",
+ .pme_code = 0x280090,
.pme_short_desc = "DERAT misses",
.pme_long_desc = "Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1.",
- .pme_event_ids = { -1, 228, 227, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000200000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_DERAT_MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_DERAT_MISS]
},
-#define POWER5p_PME_PM_MEM_WQ_DISP_Q8to15 275
[ POWER5p_PME_PM_MEM_WQ_DISP_Q8to15 ] = {
.pme_name = "PM_MEM_WQ_DISP_Q8to15",
+ .pme_code = 0x733e6,
.pme_short_desc = "Memory write queue dispatched to queues 8-15",
.pme_long_desc = "A memory operation was dispatched to a write queue in the range between 8 and 15. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 266, 265, 261, 260, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0004000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_WQ_DISP_Q8to15],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_WQ_DISP_Q8to15]
},
-#define POWER5p_PME_PM_FPU0_SINGLE 276
[ POWER5p_PME_PM_FPU0_SINGLE ] = {
.pme_name = "PM_FPU0_SINGLE",
+ .pme_code = 0x20e3,
.pme_short_desc = "FPU0 executed single precision instruction",
.pme_long_desc = "FPU0 has executed a single precision instruction.",
- .pme_event_ids = { 69, 68, 68, 70, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000002000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_SINGLE],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_SINGLE]
},
-#define POWER5p_PME_PM_THRD_PRIO_1_CYC 277
[ POWER5p_PME_PM_THRD_PRIO_1_CYC ] = {
.pme_name = "PM_THRD_PRIO_1_CYC",
+ .pme_code = 0x420e0,
.pme_short_desc = "Cycles thread running at priority level 1",
.pme_long_desc = "Cycles this thread was running at priority level 1. Priority level 1 is the lowest and indicates the thread is sleeping.",
- .pme_event_ids = { 334, 329, 327, 323, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000800000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_1_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_1_CYC]
},
-#define POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_OTHER 278
[ POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_OTHER ] = {
.pme_name = "PM_L2SC_RCST_DISP_FAIL_OTHER",
+ .pme_code = 0x732e2,
.pme_short_desc = "L2 slice C RC store dispatch attempt failed due to other reasons",
.pme_long_desc = "A Read/Claim dispatch for a store failed for some reason other than Full or Collision conditions. Rejected dispatches do not count because they have not yet been attempted.",
- .pme_event_ids = { 168, 165, 164, 163, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000040ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_OTHER],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_OTHER]
},
-#define POWER5p_PME_PM_SNOOP_RD_RETRY_RQ 279
[ POWER5p_PME_PM_SNOOP_RD_RETRY_RQ ] = {
.pme_name = "PM_SNOOP_RD_RETRY_RQ",
+ .pme_code = 0x705c6,
.pme_short_desc = "Snoop read retry due to collision with active read queue",
.pme_long_desc = "A snoop request for a read from memory was retried because it matched the cache line of an active read. The snoop request is retried because the L2 may be able to source data via intervention for the 2nd read faster than the MC. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 318, 313, 311, 309, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000200000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_RD_RETRY_RQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_RD_RETRY_RQ]
},
-#define POWER5p_PME_PM_FAB_HOLDtoVN_EMPTY 280
[ POWER5p_PME_PM_FAB_HOLDtoVN_EMPTY ] = {
.pme_name = "PM_FAB_HOLDtoVN_EMPTY",
+ .pme_code = 0x721e7,
.pme_short_desc = "Hold buffer to VN empty",
.pme_long_desc = "Fabric cycles when the Vertical Node out hold-buffers are emtpy. The signal is delivered at FBC speed and the count must be scaled accordingly.",
- .pme_event_ids = { 42, 41, 41, 43, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000020000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_HOLDtoVN_EMPTY],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_HOLDtoVN_EMPTY]
},
-#define POWER5p_PME_PM_FPU1_FEST 281
[ POWER5p_PME_PM_FPU1_FEST ] = {
.pme_name = "PM_FPU1_FEST",
+ .pme_code = 0x10c6,
.pme_short_desc = "FPU1 executed FEST instruction",
.pme_long_desc = "FPU1 has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ.",
- .pme_event_ids = { 75, 74, 74, 76, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000200000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_FEST],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_FEST]
},
-#define POWER5p_PME_PM_SNOOP_DCLAIM_RETRY_QFULL 282
[ POWER5p_PME_PM_SNOOP_DCLAIM_RETRY_QFULL ] = {
.pme_name = "PM_SNOOP_DCLAIM_RETRY_QFULL",
+ .pme_code = 0x720e6,
.pme_short_desc = "Snoop dclaim/flush retry due to write/dclaim queues full",
.pme_long_desc = "The memory controller A memory write was dispatched to a write queue. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 313, 308, 306, 304, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000100000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_DCLAIM_RETRY_QFULL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_DCLAIM_RETRY_QFULL]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR_CYC 283
[ POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L25_SHR_CYC",
+ .pme_code = 0x2c70a2,
.pme_short_desc = "Marked load latency from L2.5 shared",
.pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
- .pme_event_ids = { -1, 270, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0100000000000000ULL,
- 0x0000400000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR_CYC]
},
-#define POWER5p_PME_PM_MRK_ST_CMPL_INT 284
[ POWER5p_PME_PM_MRK_ST_CMPL_INT ] = {
.pme_name = "PM_MRK_ST_CMPL_INT",
+ .pme_code = 0x300003,
.pme_short_desc = "Marked store completed with intervention",
.pme_long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention",
- .pme_event_ids = { -1, -1, 294, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000080000000004ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_ST_CMPL_INT],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_ST_CMPL_INT]
},
-#define POWER5p_PME_PM_FLUSH_BR_MPRED 285
[ POWER5p_PME_PM_FLUSH_BR_MPRED ] = {
.pme_name = "PM_FLUSH_BR_MPRED",
+ .pme_code = 0x110c6,
.pme_short_desc = "Flush caused by branch mispredict",
.pme_long_desc = "A flush was caused by a branch mispredict.",
- .pme_event_ids = { 53, 52, 52, 54, -1, -1 },
- .pme_group_vector = {
- 0x0000080000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FLUSH_BR_MPRED],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FLUSH_BR_MPRED]
},
-#define POWER5p_PME_PM_MRK_DTLB_MISS_16G 286
[ POWER5p_PME_PM_MRK_DTLB_MISS_16G ] = {
.pme_name = "PM_MRK_DTLB_MISS_16G",
+ .pme_code = 0x4c608d,
.pme_short_desc = "Marked Data TLB misses for 16G page",
.pme_long_desc = "Data TLB references to 16GB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.",
- .pme_event_ids = { -1, -1, -1, 275, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x8000000000000000ULL,
- 0x0000028000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DTLB_MISS_16G],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DTLB_MISS_16G]
},
-#define POWER5p_PME_PM_FPU_STF 287
[ POWER5p_PME_PM_FPU_STF ] = {
.pme_name = "PM_FPU_STF",
+ .pme_code = 0x202090,
.pme_short_desc = "FPU executed store instruction",
.pme_long_desc = "FPU has executed a store instruction. Combined Unit 0 + Unit 1.",
- .pme_event_ids = { -1, 88, 87, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000100000ULL,
- 0x00000000020a8000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_STF],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_STF]
},
-#define POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR 288
[ POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR ] = {
.pme_name = "PM_L2SB_RCLD_DISP_FAIL_ADDR",
+ .pme_code = 0x711c1,
.pme_short_desc = "L2 slice B RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ",
.pme_long_desc = "A Read/Claim dispatch for a load failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.",
- .pme_event_ids = { 147, 144, 143, 142, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000004ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR]
},
-#define POWER5p_PME_PM_CMPLU_STALL_FPU 289
[ POWER5p_PME_PM_CMPLU_STALL_FPU ] = {
.pme_name = "PM_CMPLU_STALL_FPU",
+ .pme_code = 0x411098,
.pme_short_desc = "Completion stall caused by FPU instruction",
.pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a floating point instruction.",
- .pme_event_ids = { -1, -1, -1, 17, -1, -1 },
- .pme_group_vector = {
- 0x0000000100000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CMPLU_STALL_FPU],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CMPLU_STALL_FPU]
},
-#define POWER5p_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC 290
[ POWER5p_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC ] = {
.pme_name = "PM_THRD_PRIO_DIFF_minus1or2_CYC",
+ .pme_code = 0x430e2,
.pme_short_desc = "Cycles thread priority difference is -1 or -2",
.pme_long_desc = "Cycles when this thread's priority is lower than the other thread's priority by 1 or 2.",
- .pme_event_ids = { 345, 340, 338, 334, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000400000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC]
},
-#define POWER5p_PME_PM_GCT_NOSLOT_CYC 291
[ POWER5p_PME_PM_GCT_NOSLOT_CYC ] = {
.pme_name = "PM_GCT_NOSLOT_CYC",
+ .pme_code = 0x100004,
.pme_short_desc = "Cycles no GCT slot allocated",
.pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread.",
- .pme_event_ids = { 98, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000020ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GCT_NOSLOT_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GCT_NOSLOT_CYC]
},
-#define POWER5p_PME_PM_FXU0_BUSY_FXU1_IDLE 292
[ POWER5p_PME_PM_FXU0_BUSY_FXU1_IDLE ] = {
.pme_name = "PM_FXU0_BUSY_FXU1_IDLE",
+ .pme_code = 0x300012,
.pme_short_desc = "FXU0 busy FXU1 idle",
.pme_long_desc = "FXU0 is busy while FXU1 was idle",
- .pme_event_ids = { -1, -1, 90, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000020000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FXU0_BUSY_FXU1_IDLE],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FXU0_BUSY_FXU1_IDLE]
},
-#define POWER5p_PME_PM_PTEG_FROM_L35_SHR 293
[ POWER5p_PME_PM_PTEG_FROM_L35_SHR ] = {
.pme_name = "PM_PTEG_FROM_L35_SHR",
+ .pme_code = 0x18309e,
.pme_short_desc = "PTEG loaded from L3.5 shared",
.pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (S) data from the L3 of a chip on the same module as this processor is located, due to a demand load.",
- .pme_event_ids = { 308, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x1000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_L35_SHR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_L35_SHR]
},
-#define POWER5p_PME_PM_MRK_DTLB_REF_16G 294
[ POWER5p_PME_PM_MRK_DTLB_REF_16G ] = {
.pme_name = "PM_MRK_DTLB_REF_16G",
+ .pme_code = 0x4c6086,
.pme_short_desc = "Marked Data TLB reference for 16G page",
.pme_long_desc = "Data TLB references by a marked instruction for 16GB pages.",
- .pme_event_ids = { -1, -1, -1, 277, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x4000000000000000ULL,
- 0x0000010000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DTLB_REF_16G],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DTLB_REF_16G]
},
-#define POWER5p_PME_PM_MRK_LSU_FLUSH_UST 295
[ POWER5p_PME_PM_MRK_LSU_FLUSH_UST ] = {
.pme_name = "PM_MRK_LSU_FLUSH_UST",
+ .pme_code = 0x2810a8,
.pme_short_desc = "Marked unaligned store flushes",
.pme_long_desc = "A marked store was flushed because it was unaligned",
- .pme_event_ids = { -1, 296, 291, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0100100000000008ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU_FLUSH_UST],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU_FLUSH_UST]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR 296
[ POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR ] = {
.pme_name = "PM_MRK_DATA_FROM_L25_SHR",
+ .pme_code = 0x1c7097,
.pme_short_desc = "Marked data loaded from L2.5 shared",
.pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from the L2 of a chip on the same module as this processor is located due to a marked load.",
- .pme_event_ids = { 270, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0100000000000000ULL,
- 0x0000000200000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR]
},
-#define POWER5p_PME_PM_L3SA_HIT 297
[ POWER5p_PME_PM_L3SA_HIT ] = {
.pme_name = "PM_L3SA_HIT",
+ .pme_code = 0x711c3,
.pme_short_desc = "L3 slice A hits",
.pme_long_desc = "Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 slice",
- .pme_event_ids = { 178, 175, 174, 173, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000008000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SA_HIT],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SA_HIT]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR 298
[ POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR ] = {
.pme_name = "PM_MRK_DATA_FROM_L35_SHR",
+ .pme_code = 0x1c709e,
.pme_short_desc = "Marked data loaded from L3.5 shared",
.pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on the same module as this processor is located due to a marked load.",
- .pme_event_ids = { 273, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0800000000000000ULL,
- 0x0000001000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR]
},
-#define POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_ADDR 299
[ POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_ADDR ] = {
.pme_name = "PM_L2SB_RCST_DISP_FAIL_ADDR",
+ .pme_code = 0x712c1,
.pme_short_desc = "L2 slice B RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ",
.pme_long_desc = "A Read/Claim dispatch for a store failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.",
- .pme_event_ids = { 151, 148, 147, 146, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000008ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_ADDR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_ADDR]
},
-#define POWER5p_PME_PM_IERAT_XLATE_WR 300
[ POWER5p_PME_PM_IERAT_XLATE_WR ] = {
.pme_name = "PM_IERAT_XLATE_WR",
+ .pme_code = 0x220e7,
.pme_short_desc = "Translation written to ierat",
.pme_long_desc = "An entry was written into the IERAT as a result of an IERAT miss. This event can be used to count IERAT misses. An ERAT miss that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed.",
- .pme_event_ids = { 113, 111, 110, 110, -1, -1 },
- .pme_group_vector = {
- 0x0000008000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_IERAT_XLATE_WR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_IERAT_XLATE_WR]
},
-#define POWER5p_PME_PM_L2SA_ST_REQ 301
[ POWER5p_PME_PM_L2SA_ST_REQ ] = {
.pme_name = "PM_L2SA_ST_REQ",
+ .pme_code = 0x723e0,
.pme_short_desc = "L2 slice A store requests",
.pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A, B, and C.",
- .pme_event_ids = { 143, 140, 139, 138, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000002ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_ST_REQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_ST_REQ]
},
-#define POWER5p_PME_PM_INST_FROM_LMEM 302
[ POWER5p_PME_PM_INST_FROM_LMEM ] = {
.pme_name = "PM_INST_FROM_LMEM",
+ .pme_code = 0x222086,
.pme_short_desc = "Instruction fetched from local memory",
.pme_long_desc = "An instruction fetch group was fetched from memory attached to the same module this proccessor is located on. Fetch groups can contain up to 8 instructions",
- .pme_event_ids = { -1, 119, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0100000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_LMEM],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_LMEM]
},
-#define POWER5p_PME_PM_THRD_SEL_T1 303
[ POWER5p_PME_PM_THRD_SEL_T1 ] = {
.pme_name = "PM_THRD_SEL_T1",
+ .pme_code = 0x410c1,
.pme_short_desc = "Decode selected thread 1",
.pme_long_desc = "Thread selection picked thread 1 for decode.",
- .pme_event_ids = { 353, 348, 346, 342, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000002000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_SEL_T1],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_SEL_T1]
},
-#define POWER5p_PME_PM_IC_DEMAND_L2_BR_REDIRECT 304
[ POWER5p_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = {
.pme_name = "PM_IC_DEMAND_L2_BR_REDIRECT",
+ .pme_code = 0x230e1,
.pme_short_desc = "L2 I cache demand request due to branch redirect",
.pme_long_desc = "A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target).",
- .pme_event_ids = { 111, 109, 107, 107, -1, -1 },
- .pme_group_vector = {
- 0x0000004000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_IC_DEMAND_L2_BR_REDIRECT],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_IC_DEMAND_L2_BR_REDIRECT]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR_CYC 305
[ POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L35_SHR_CYC",
+ .pme_code = 0x2c70a6,
.pme_short_desc = "Marked load latency from L3.5 shared",
.pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
- .pme_event_ids = { -1, 274, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0800000000000000ULL,
- 0x0000800000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR_CYC]
},
-#define POWER5p_PME_PM_FPU0_1FLOP 306
[ POWER5p_PME_PM_FPU0_1FLOP ] = {
.pme_name = "PM_FPU0_1FLOP",
+ .pme_code = 0xc3,
.pme_short_desc = "FPU0 executed add",
.pme_long_desc = " mult",
- .pme_event_ids = { 58, 57, 57, 59, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000008000000ULL,
- 0x0000000000002000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_1FLOP],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_1FLOP]
},
-#define POWER5p_PME_PM_PTEG_FROM_L2 307
[ POWER5p_PME_PM_PTEG_FROM_L2 ] = {
.pme_name = "PM_PTEG_FROM_L2",
+ .pme_code = 0x183087,
.pme_short_desc = "PTEG loaded from L2",
.pme_long_desc = "A Page Table Entry was loaded into the TLB from the local L2 due to a demand load",
- .pme_event_ids = { 304, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x2000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_L2],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_L2]
},
-#define POWER5p_PME_PM_MEM_PW_CMPL 308
[ POWER5p_PME_PM_MEM_PW_CMPL ] = {
.pme_name = "PM_MEM_PW_CMPL",
+ .pme_code = 0x724e6,
.pme_short_desc = "Memory partial-write completed",
.pme_long_desc = "Number of Partial Writes completed. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 258, 257, 253, 252, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0008000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_PW_CMPL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_PW_CMPL]
},
-#define POWER5p_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC 309
[ POWER5p_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC ] = {
.pme_name = "PM_THRD_PRIO_DIFF_minus5or6_CYC",
+ .pme_code = 0x430e0,
.pme_short_desc = "Cycles thread priority difference is -5 or -6",
.pme_long_desc = "Cycles when this thread's priority is lower than the other thread's priority by 5 or 6.",
- .pme_event_ids = { 347, 342, 340, 336, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000800000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC]
},
-#define POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER 310
[ POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER ] = {
.pme_name = "PM_L2SB_RCLD_DISP_FAIL_OTHER",
+ .pme_code = 0x731e1,
.pme_short_desc = "L2 slice B RC load dispatch attempt failed due to other reasons",
.pme_long_desc = "A Read/Claim dispatch for a load failed for some reason other than Full or Collision conditions.",
- .pme_event_ids = { 148, 145, 144, 143, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000004ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER]
},
-#define POWER5p_PME_PM_MRK_DTLB_MISS_4K 311
[ POWER5p_PME_PM_MRK_DTLB_MISS_4K ] = {
.pme_name = "PM_MRK_DTLB_MISS_4K",
+ .pme_code = 0x1c608d,
.pme_short_desc = "Marked Data TLB misses for 4K page",
.pme_long_desc = "Data TLB references to 4KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.",
- .pme_event_ids = { 278, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x8000000000000000ULL,
- 0x0005000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DTLB_MISS_4K],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DTLB_MISS_4K]
},
-#define POWER5p_PME_PM_FPU0_FIN 312
[ POWER5p_PME_PM_FPU0_FIN ] = {
.pme_name = "PM_FPU0_FIN",
+ .pme_code = 0x10c3,
.pme_short_desc = "FPU0 produced a result",
.pme_long_desc = "FPU0 finished, produced a result. This only indicates finish, not completion. Floating Point Stores are included in this count but not Floating Point Loads.",
- .pme_event_ids = { 62, 61, 61, 63, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000008080000ULL,
- 0x000000000000a800ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_FIN],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_FIN]
},
-#define POWER5p_PME_PM_L3SC_SHR_INV 313
[ POWER5p_PME_PM_L3SC_SHR_INV ] = {
.pme_name = "PM_L3SC_SHR_INV",
+ .pme_code = 0x710c5,
.pme_short_desc = "L3 slice C transition from shared to invalid",
.pme_long_desc = "L3 snooper detects someone doing a store to a line that is Sx in this L3(i.e. invalidate hit SX and dispatched).",
- .pme_event_ids = { 196, 193, 192, 191, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000400ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SC_SHR_INV],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SC_SHR_INV]
},
-#define POWER5p_PME_PM_GRP_BR_REDIR 314
[ POWER5p_PME_PM_GRP_BR_REDIR ] = {
.pme_name = "PM_GRP_BR_REDIR",
+ .pme_code = 0x120e6,
.pme_short_desc = "Group experienced branch redirect",
.pme_long_desc = "Number of groups, counted at dispatch, that have encountered a branch redirect. Every group constructed from a fetch group that has been redirected will count.",
- .pme_event_ids = { 101, 100, 98, 100, -1, -1 },
- .pme_group_vector = {
- 0x0000080000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_BR_REDIR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_BR_REDIR]
},
-#define POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL 315
[ POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL ] = {
.pme_name = "PM_L2SC_RCLD_DISP_FAIL_RC_FULL",
+ .pme_code = 0x721e2,
.pme_short_desc = "L2 slice C RC load dispatch attempt failed due to all RC full",
.pme_long_desc = "A Read/Claim dispatch for a load failed because all RC machines are busy.",
- .pme_event_ids = { 165, 162, 161, 160, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000020ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL]
},
-#define POWER5p_PME_PM_MRK_LSU_FLUSH_SRQ 316
[ POWER5p_PME_PM_MRK_LSU_FLUSH_SRQ ] = {
.pme_name = "PM_MRK_LSU_FLUSH_SRQ",
+ .pme_code = 0x481088,
.pme_short_desc = "Marked SRQ lhs flushes",
.pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { -1, -1, -1, 294, -1, -1 },
- .pme_group_vector = {
- 0x0000000000008000ULL,
- 0x0000000000000000ULL,
- 0x0100000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU_FLUSH_SRQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU_FLUSH_SRQ]
},
-#define POWER5p_PME_PM_PTEG_FROM_L275_SHR 317
[ POWER5p_PME_PM_PTEG_FROM_L275_SHR ] = {
.pme_name = "PM_PTEG_FROM_L275_SHR",
+ .pme_code = 0x383097,
.pme_short_desc = "PTEG loaded from L2.75 shared",
.pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (T) data from the L2 on a different module than this processor is located due to a demand load.",
- .pme_event_ids = { -1, -1, 299, -1, -1, -1 },
- .pme_group_vector = {
- 0x0800000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_L275_SHR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_L275_SHR]
},
-#define POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL 318
[ POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL ] = {
.pme_name = "PM_L2SB_RCLD_DISP_FAIL_RC_FULL",
+ .pme_code = 0x721e1,
.pme_short_desc = "L2 slice B RC load dispatch attempt failed due to all RC full",
.pme_long_desc = "A Read/Claim dispatch for a load failed because all RC machines are busy.",
- .pme_event_ids = { 149, 146, 145, 144, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000004ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL]
},
-#define POWER5p_PME_PM_SNOOP_RD_RETRY_WQ 319
[ POWER5p_PME_PM_SNOOP_RD_RETRY_WQ ] = {
.pme_name = "PM_SNOOP_RD_RETRY_WQ",
+ .pme_code = 0x715c6,
.pme_short_desc = "Snoop read retry due to collision with active write queue",
.pme_long_desc = "A snoop request for a read from memory was retried because it matched the cache line of an active write. The snoop request is retried and the active write is changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 319, 314, 312, 310, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000200000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_RD_RETRY_WQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_RD_RETRY_WQ]
},
-#define POWER5p_PME_PM_FAB_DCLAIM_RETRIED 320
[ POWER5p_PME_PM_FAB_DCLAIM_RETRIED ] = {
.pme_name = "PM_FAB_DCLAIM_RETRIED",
+ .pme_code = 0x730e7,
.pme_short_desc = "dclaim retried",
.pme_long_desc = "A DCLAIM command was retried. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.",
- .pme_event_ids = { 40, 39, 39, 41, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000010000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_DCLAIM_RETRIED],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_DCLAIM_RETRIED]
},
-#define POWER5p_PME_PM_LSU0_NCLD 321
[ POWER5p_PME_PM_LSU0_NCLD ] = {
.pme_name = "PM_LSU0_NCLD",
+ .pme_code = 0xc50c1,
.pme_short_desc = "LSU0 non-cacheable loads",
.pme_long_desc = "A non-cacheable load was executed by unit 0.",
- .pme_event_ids = { 212, 208, 208, 207, -1, -1 },
- .pme_group_vector = {
- 0x0000002000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_NCLD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_NCLD]
},
-#define POWER5p_PME_PM_LSU1_BUSY_REJECT 322
[ POWER5p_PME_PM_LSU1_BUSY_REJECT ] = {
.pme_name = "PM_LSU1_BUSY_REJECT",
+ .pme_code = 0xc20e5,
.pme_short_desc = "LSU1 busy due to reject",
.pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions.",
- .pme_event_ids = { 218, 214, 214, 213, -1, -1 },
- .pme_group_vector = {
- 0x0000004000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_BUSY_REJECT],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_BUSY_REJECT]
},
-#define POWER5p_PME_PM_FXLS0_FULL_CYC 323
[ POWER5p_PME_PM_FXLS0_FULL_CYC ] = {
.pme_name = "PM_FXLS0_FULL_CYC",
+ .pme_code = 0x110c0,
.pme_short_desc = "Cycles FXU0/LS0 queue full",
.pme_long_desc = "The issue queue that feeds the Fixed Point unit 0 / Load Store Unit 0 is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.",
- .pme_event_ids = { 91, 89, 88, 91, -1, -1 },
- .pme_group_vector = {
- 0x0000000400000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FXLS0_FULL_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FXLS0_FULL_CYC]
},
-#define POWER5p_PME_PM_DTLB_REF_16M 324
[ POWER5p_PME_PM_DTLB_REF_16M ] = {
.pme_name = "PM_DTLB_REF_16M",
+ .pme_code = 0x3c2086,
.pme_short_desc = "Data TLB reference for 16M page",
.pme_long_desc = "Data TLB references for 16MB pages. Includes hits + misses.",
- .pme_event_ids = { -1, -1, 33, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000800000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DTLB_REF_16M],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DTLB_REF_16M]
},
-#define POWER5p_PME_PM_FPU0_FEST 325
[ POWER5p_PME_PM_FPU0_FEST ] = {
.pme_name = "PM_FPU0_FEST",
+ .pme_code = 0x10c2,
.pme_short_desc = "FPU0 executed FEST instruction",
.pme_long_desc = "FPU0 has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ.",
- .pme_event_ids = { 61, 60, 60, 62, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000200000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_FEST],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_FEST]
},
-#define POWER5p_PME_PM_GCT_USAGE_60to79_CYC 326
[ POWER5p_PME_PM_GCT_USAGE_60to79_CYC ] = {
.pme_name = "PM_GCT_USAGE_60to79_CYC",
+ .pme_code = 0x20001f,
.pme_short_desc = "Cycles GCT 60-79% full",
.pme_long_desc = "Cycles when the Global Completion Table has between 60% and 70% of its slots used. The GCT has 20 entries shared between threads.",
- .pme_event_ids = { -1, 98, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000040ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GCT_USAGE_60to79_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GCT_USAGE_60to79_CYC]
},
-#define POWER5p_PME_PM_DATA_FROM_L25_MOD 327
[ POWER5p_PME_PM_DATA_FROM_L25_MOD ] = {
.pme_name = "PM_DATA_FROM_L25_MOD",
+ .pme_code = 0x2c3097,
.pme_short_desc = "Data loaded from L2.5 modified",
.pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 of a chip on the same module as this processor is located due to a demand load.",
- .pme_event_ids = { -1, 21, 17, -1, -1, -1 },
- .pme_group_vector = {
- 0x0020000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_L25_MOD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_L25_MOD]
},
-#define POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR 328
[ POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR ] = {
.pme_name = "PM_L2SC_RCLD_DISP_FAIL_ADDR",
+ .pme_code = 0x711c2,
.pme_short_desc = "L2 slice C RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ",
.pme_long_desc = "A Read/Claim dispatch for a load failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.",
- .pme_event_ids = { 163, 160, 159, 158, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000020ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR]
},
-#define POWER5p_PME_PM_LSU0_REJECT_ERAT_MISS 329
[ POWER5p_PME_PM_LSU0_REJECT_ERAT_MISS ] = {
.pme_name = "PM_LSU0_REJECT_ERAT_MISS",
+ .pme_code = 0xc40c3,
.pme_short_desc = "LSU0 reject due to ERAT miss",
.pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions due to an ERAT miss. Requests that miss the Derat are rejected and retried until the request hits in the Erat.",
- .pme_event_ids = { 213, 209, 209, 208, -1, -1 },
- .pme_group_vector = {
- 0x0000000000020000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_REJECT_ERAT_MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_REJECT_ERAT_MISS]
},
-#define POWER5p_PME_PM_DATA_FROM_L375_MOD 330
[ POWER5p_PME_PM_DATA_FROM_L375_MOD ] = {
.pme_name = "PM_DATA_FROM_L375_MOD",
+ .pme_code = 0x1c30a7,
.pme_short_desc = "Data loaded from L3.75 modified",
.pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on the same module as this processor is located due to a demand load.",
- .pme_event_ids = { 23, -1, -1, 23, -1, -1 },
- .pme_group_vector = {
- 0x0040000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_L375_MOD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_L375_MOD]
},
-#define POWER5p_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 331
[ POWER5p_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = {
.pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC",
+ .pme_code = 0x200015,
.pme_short_desc = "Cycles LMQ and SRQ empty",
.pme_long_desc = "Cycles when both the LMQ and SRQ are empty (LSU is idle)",
- .pme_event_ids = { -1, 238, 236, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000600ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC]
},
-#define POWER5p_PME_PM_DTLB_MISS_64K 332
[ POWER5p_PME_PM_DTLB_MISS_64K ] = {
.pme_name = "PM_DTLB_MISS_64K",
+ .pme_code = 0x2c208d,
.pme_short_desc = "Data TLB miss for 64K page",
.pme_long_desc = "Data TLB references to 64KB pages that missed the TLB. Page size is determined at TLB reload time.",
- .pme_event_ids = { -1, 31, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0001000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DTLB_MISS_64K],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DTLB_MISS_64K]
},
-#define POWER5p_PME_PM_LSU0_REJECT_RELOAD_CDF 333
[ POWER5p_PME_PM_LSU0_REJECT_RELOAD_CDF ] = {
.pme_name = "PM_LSU0_REJECT_RELOAD_CDF",
+ .pme_code = 0xc40c2,
.pme_short_desc = "LSU0 reject due to reload CDF or tag update collision",
.pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because of Critical Data Forward. When critical data arrives from the storage system it is formatted and immediately forwarded, bypassing the data cache, to the destination register using the result bus. Any instruction the requires the result bus in the same cycle is rejected. Tag update rejects are caused when an instruction requires access to the Dcache directory or ERAT in the same system when they are being updated.",
- .pme_event_ids = { 215, 211, 211, 210, -1, -1 },
- .pme_group_vector = {
- 0x0000000000010000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_REJECT_RELOAD_CDF],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_REJECT_RELOAD_CDF]
},
-#define POWER5p_PME_PM_0INST_FETCH 334
[ POWER5p_PME_PM_0INST_FETCH ] = {
.pme_name = "PM_0INST_FETCH",
+ .pme_code = 0x42208d,
.pme_short_desc = "No instructions fetched",
.pme_long_desc = "No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)",
- .pme_event_ids = { -1, -1, -1, 1, -1, -1 },
- .pme_group_vector = {
- 0x0100008000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_0INST_FETCH],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_0INST_FETCH]
},
-#define POWER5p_PME_PM_LSU1_REJECT_RELOAD_CDF 335
[ POWER5p_PME_PM_LSU1_REJECT_RELOAD_CDF ] = {
.pme_name = "PM_LSU1_REJECT_RELOAD_CDF",
+ .pme_code = 0xc40c6,
.pme_short_desc = "LSU1 reject due to reload CDF or tag update collision",
.pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because of Critical Data Forward. When critical data arrives from the storage system it is formatted and immediately forwarded, bypassing the data cache, to the destination register using the result bus. Any instruction the requires the result bus in the same cycle is rejected. Tag update rejects are caused when an instruction requires access to the Dcache directory or ERAT in the same system when they are being updated.",
- .pme_event_ids = { 228, 224, 224, 223, -1, -1 },
- .pme_group_vector = {
- 0x0000000000010000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_REJECT_RELOAD_CDF],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_REJECT_RELOAD_CDF]
},
-#define POWER5p_PME_PM_MEM_WQ_DISP_Q0to7 336
[ POWER5p_PME_PM_MEM_WQ_DISP_Q0to7 ] = {
.pme_name = "PM_MEM_WQ_DISP_Q0to7",
+ .pme_code = 0x723e6,
.pme_short_desc = "Memory write queue dispatched to queues 0-7",
.pme_long_desc = "A memory operation was dispatched to a write queue in the range between 0 and 7. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 265, 264, 260, 259, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0004000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_WQ_DISP_Q0to7],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_WQ_DISP_Q0to7]
},
-#define POWER5p_PME_PM_L1_PREF 337
[ POWER5p_PME_PM_L1_PREF ] = {
.pme_name = "PM_L1_PREF",
+ .pme_code = 0xc70e7,
.pme_short_desc = "L1 cache data prefetches",
.pme_long_desc = "A request to prefetch data into the L1 was made",
- .pme_event_ids = { 126, 123, 122, 121, -1, -1 },
- .pme_group_vector = {
- 0x0000000000001000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000200ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L1_PREF],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L1_PREF]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_LMEM_CYC 338
[ POWER5p_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_LMEM_CYC",
+ .pme_code = 0x4c70a0,
.pme_short_desc = "Marked load latency from local memory",
.pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
- .pme_event_ids = { -1, -1, -1, 270, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0800000000000000ULL,
- 0x0000001000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_LMEM_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_LMEM_CYC]
},
-#define POWER5p_PME_PM_BRQ_FULL_CYC 339
[ POWER5p_PME_PM_BRQ_FULL_CYC ] = {
.pme_name = "PM_BRQ_FULL_CYC",
+ .pme_code = 0x100c5,
.pme_short_desc = "Cycles branch queue full",
.pme_long_desc = "Cycles when the issue queue that feeds the branch unit is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.",
- .pme_event_ids = { 8, 7, 7, 8, -1, -1 },
- .pme_group_vector = {
- 0x0000000200000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_BRQ_FULL_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_BRQ_FULL_CYC]
},
-#define POWER5p_PME_PM_GRP_IC_MISS_NONSPEC 340
[ POWER5p_PME_PM_GRP_IC_MISS_NONSPEC ] = {
.pme_name = "PM_GRP_IC_MISS_NONSPEC",
+ .pme_code = 0x112099,
.pme_short_desc = "Group experienced non-speculative I cache miss",
.pme_long_desc = "Number of groups, counted at completion, that have encountered an instruction cache miss.",
- .pme_event_ids = { 108, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000010000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_IC_MISS_NONSPEC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_IC_MISS_NONSPEC]
},
-#define POWER5p_PME_PM_PTEG_FROM_L275_MOD 341
[ POWER5p_PME_PM_PTEG_FROM_L275_MOD ] = {
.pme_name = "PM_PTEG_FROM_L275_MOD",
+ .pme_code = 0x1830a3,
.pme_short_desc = "PTEG loaded from L2.75 modified",
.pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L2 on a different module than this processor is located due to a demand load.",
- .pme_event_ids = { 306, -1, -1, 300, -1, -1 },
- .pme_group_vector = {
- 0x0800000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_L275_MOD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_L275_MOD]
},
-#define POWER5p_PME_PM_MRK_LD_MISS_L1_LSU0 342
[ POWER5p_PME_PM_MRK_LD_MISS_L1_LSU0 ] = {
.pme_name = "PM_MRK_LD_MISS_L1_LSU0",
+ .pme_code = 0x820e0,
.pme_short_desc = "LSU0 marked L1 D cache load misses",
.pme_long_desc = "Load references that miss the Level 1 Data cache, by LSU0.",
- .pme_event_ids = { 286, 286, 280, 283, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0040000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LD_MISS_L1_LSU0],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LD_MISS_L1_LSU0]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR_CYC 343
[ POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L375_SHR_CYC",
+ .pme_code = 0x2c70a7,
.pme_short_desc = "Marked load latency from L3.75 shared",
.pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
- .pme_event_ids = { -1, 275, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x2000000000000000ULL,
- 0x0000004000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR_CYC]
},
-#define POWER5p_PME_PM_DATA_FROM_L3 344
[ POWER5p_PME_PM_DATA_FROM_L3 ] = {
.pme_name = "PM_DATA_FROM_L3",
+ .pme_code = 0x1c308e,
.pme_short_desc = "Data loaded from L3",
.pme_long_desc = "The processor's Data Cache was reloaded from the local L3 due to a demand load.",
- .pme_event_ids = { 21, -1, 20, -1, -1, -1 },
- .pme_group_vector = {
- 0x0018000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000140ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_L3],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_L3]
},
-#define POWER5p_PME_PM_INST_FROM_L2 345
[ POWER5p_PME_PM_INST_FROM_L2 ] = {
.pme_name = "PM_INST_FROM_L2",
+ .pme_code = 0x122086,
.pme_short_desc = "Instruction fetched from L2",
.pme_long_desc = "An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions",
- .pme_event_ids = { 118, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0100000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L2],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L2]
},
-#define POWER5p_PME_PM_LSU_FLUSH 346
[ POWER5p_PME_PM_LSU_FLUSH ] = {
.pme_name = "PM_LSU_FLUSH",
+ .pme_code = 0x110c5,
.pme_short_desc = "Flush initiated by LSU",
.pme_long_desc = "A flush was initiated by the Load Store Unit",
- .pme_event_ids = { 231, 229, 228, 226, -1, -1 },
- .pme_group_vector = {
- 0x000000000dc80000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_FLUSH],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_FLUSH]
},
-#define POWER5p_PME_PM_PMC2_OVERFLOW 347
[ POWER5p_PME_PM_PMC2_OVERFLOW ] = {
.pme_name = "PM_PMC2_OVERFLOW",
+ .pme_code = 0x30000a,
.pme_short_desc = "PMC2 Overflow",
.pme_long_desc = "Overflows from PMC2 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
- .pme_event_ids = { -1, -1, 296, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PMC2_OVERFLOW],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PMC2_OVERFLOW]
},
-#define POWER5p_PME_PM_FPU0_DENORM 348
[ POWER5p_PME_PM_FPU0_DENORM ] = {
.pme_name = "PM_FPU0_DENORM",
+ .pme_code = 0x20e0,
.pme_short_desc = "FPU0 received denormalized data",
.pme_long_desc = "FPU0 has encountered a denormalized operand.",
- .pme_event_ids = { 59, 58, 58, 60, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000400000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_DENORM],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_DENORM]
},
-#define POWER5p_PME_PM_FPU1_FMOV_FEST 349
[ POWER5p_PME_PM_FPU1_FMOV_FEST ] = {
.pme_name = "PM_FPU1_FMOV_FEST",
+ .pme_code = 0x10c4,
.pme_short_desc = "FPU1 executed FMOV or FEST instructions",
.pme_long_desc = "FPU1 has executed a move kind of instruction or one of the estimate instructions. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ.",
- .pme_event_ids = { 78, 77, 77, 79, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000400000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_FMOV_FEST],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_FMOV_FEST]
},
-#define POWER5p_PME_PM_INST_FETCH_CYC 350
[ POWER5p_PME_PM_INST_FETCH_CYC ] = {
.pme_name = "PM_INST_FETCH_CYC",
+ .pme_code = 0x220e4,
.pme_short_desc = "Cycles at least 1 instruction fetched",
.pme_long_desc = "Cycles when at least one instruction was sent from the fetch unit to the decode unit.",
- .pme_event_ids = { 117, 115, 114, 114, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000800ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FETCH_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FETCH_CYC]
},
-#define POWER5p_PME_PM_INST_DISP 351
[ POWER5p_PME_PM_INST_DISP ] = {
.pme_name = "PM_INST_DISP",
+ .pme_code = 0x300009,
.pme_short_desc = "Instructions dispatched",
.pme_long_desc = "Number of PowerPC instructions successfully dispatched.",
- .pme_event_ids = { -1, -1, 113, 113, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000005ULL,
- 0x0000000000000000ULL,
- 0x0000000001080000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_DISP],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_DISP]
},
-#define POWER5p_PME_PM_LSU_LDF 352
[ POWER5p_PME_PM_LSU_LDF ] = {
.pme_name = "PM_LSU_LDF",
+ .pme_code = 0x1c50a8,
.pme_short_desc = "LSU executed Floating Point load instruction",
.pme_long_desc = "LSU executed Floating Point load instruction. Combined Unit 0 + 1.",
- .pme_event_ids = { 236, -1, -1, 230, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000100000ULL,
- 0x0000000000080000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_LDF],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_LDF]
},
-#define POWER5p_PME_PM_DATA_FROM_L25_SHR 353
[ POWER5p_PME_PM_DATA_FROM_L25_SHR ] = {
.pme_name = "PM_DATA_FROM_L25_SHR",
+ .pme_code = 0x1c3097,
.pme_short_desc = "Data loaded from L2.5 shared",
.pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from the L2 of a chip on the same module as this processor is located due to a demand load.",
- .pme_event_ids = { 19, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0020000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_L25_SHR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_L25_SHR]
},
-#define POWER5p_PME_PM_L1_DCACHE_RELOAD_VALID 354
[ POWER5p_PME_PM_L1_DCACHE_RELOAD_VALID ] = {
.pme_name = "PM_L1_DCACHE_RELOAD_VALID",
+ .pme_code = 0xc30e4,
.pme_short_desc = "L1 reload data source valid",
.pme_long_desc = "The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads.",
- .pme_event_ids = { 125, 122, 121, 120, -1, -1 },
- .pme_group_vector = {
- 0x0000010000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L1_DCACHE_RELOAD_VALID],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L1_DCACHE_RELOAD_VALID]
},
-#define POWER5p_PME_PM_MEM_WQ_DISP_DCLAIM 355
[ POWER5p_PME_PM_MEM_WQ_DISP_DCLAIM ] = {
.pme_name = "PM_MEM_WQ_DISP_DCLAIM",
+ .pme_code = 0x713c6,
.pme_short_desc = "Memory write queue dispatched due to dclaim/flush",
.pme_long_desc = "A memory dclaim or flush operation was dispatched to a write queue. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 267, 266, 262, 261, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0004000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_WQ_DISP_DCLAIM],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_WQ_DISP_DCLAIM]
},
-#define POWER5p_PME_PM_MRK_GRP_ISSUED 356
[ POWER5p_PME_PM_MRK_GRP_ISSUED ] = {
.pme_name = "PM_MRK_GRP_ISSUED",
+ .pme_code = 0x100015,
.pme_short_desc = "Marked group issued",
.pme_long_desc = "A sampled instruction was issued.",
- .pme_event_ids = { 282, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0040000000000000ULL,
- 0x0000000080000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_GRP_ISSUED],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_GRP_ISSUED]
},
-#define POWER5p_PME_PM_FPU_FULL_CYC 357
[ POWER5p_PME_PM_FPU_FULL_CYC ] = {
.pme_name = "PM_FPU_FULL_CYC",
+ .pme_code = 0x110090,
.pme_short_desc = "Cycles FPU issue queue full",
.pme_long_desc = "Cycles when one or both FPU issue queues are full. Combined Unit 0 + 1. Use with caution since this is the sum of cycles when Unit 0 was full plus Unit 1 full. It does not indicate when both units were full.",
- .pme_event_ids = { 89, -1, -1, 89, -1, -1 },
- .pme_group_vector = {
- 0x0000000100000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_FULL_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_FULL_CYC]
},
-#define POWER5p_PME_PM_INST_FROM_L35_MOD 358
[ POWER5p_PME_PM_INST_FROM_L35_MOD ] = {
.pme_name = "PM_INST_FROM_L35_MOD",
+ .pme_code = 0x22209d,
.pme_short_desc = "Instruction fetched from L3.5 modified",
.pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L3 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions",
- .pme_event_ids = { -1, 118, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0400000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L35_MOD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L35_MOD]
},
-#define POWER5p_PME_PM_FPU_FMA 359
[ POWER5p_PME_PM_FPU_FMA ] = {
.pme_name = "PM_FPU_FMA",
+ .pme_code = 0x200088,
.pme_short_desc = "FPU executed multiply-add instruction",
.pme_long_desc = "This signal is active for one cycle when FPU is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.",
- .pme_event_ids = { -1, 84, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000020000ULL,
- 0x0000000002424000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_FMA],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_FMA]
},
-#define POWER5p_PME_PM_THRD_PRIO_3_CYC 360
[ POWER5p_PME_PM_THRD_PRIO_3_CYC ] = {
.pme_name = "PM_THRD_PRIO_3_CYC",
+ .pme_code = 0x420e2,
.pme_short_desc = "Cycles thread running at priority level 3",
.pme_long_desc = "Cycles this thread was running at priority level 3.",
- .pme_event_ids = { 336, 331, 329, 325, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000200000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_3_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_3_CYC]
},
-#define POWER5p_PME_PM_MRK_CRU_FIN 361
[ POWER5p_PME_PM_MRK_CRU_FIN ] = {
.pme_name = "PM_MRK_CRU_FIN",
+ .pme_code = 0x400005,
.pme_short_desc = "Marked instruction CRU processing finished",
.pme_long_desc = "The Condition Register Unit finished a marked instruction. Instructions that finish may not necessary complete.",
- .pme_event_ids = { -1, -1, -1, 263, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000080000000004ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_CRU_FIN],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_CRU_FIN]
},
-#define POWER5p_PME_PM_SNOOP_WR_RETRY_WQ 362
[ POWER5p_PME_PM_SNOOP_WR_RETRY_WQ ] = {
.pme_name = "PM_SNOOP_WR_RETRY_WQ",
+ .pme_code = 0x716c6,
.pme_short_desc = "Snoop write/dclaim retry due to collision with active write queue",
.pme_long_desc = "A snoop request for a write or dclaim to memory was retried because it matched the cache line of an active write. The snoop request is retried and the active write is changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 324, 319, 317, 315, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000400000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_WR_RETRY_WQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_WR_RETRY_WQ]
},
-#define POWER5p_PME_PM_CMPLU_STALL_REJECT 363
[ POWER5p_PME_PM_CMPLU_STALL_REJECT ] = {
.pme_name = "PM_CMPLU_STALL_REJECT",
+ .pme_code = 0x41109a,
.pme_short_desc = "Completion stall caused by reject",
.pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a load/store reject. This is a subset of PM_CMPLU_STALL_LSU.",
- .pme_event_ids = { -1, -1, -1, 18, -1, -1 },
- .pme_group_vector = {
- 0x0000000020000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CMPLU_STALL_REJECT],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CMPLU_STALL_REJECT]
},
-#define POWER5p_PME_PM_MRK_FXU_FIN 364
[ POWER5p_PME_PM_MRK_FXU_FIN ] = {
.pme_name = "PM_MRK_FXU_FIN",
+ .pme_code = 0x200014,
.pme_short_desc = "Marked instruction FXU processing finished",
.pme_long_desc = "One of the Fixed Point Units finished a marked instruction. Instructions that finish may not necessary complete.",
- .pme_event_ids = { -1, 94, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0400000000040000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_FXU_FIN],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_FXU_FIN]
},
-#define POWER5p_PME_PM_LSU1_REJECT_ERAT_MISS 365
[ POWER5p_PME_PM_LSU1_REJECT_ERAT_MISS ] = {
.pme_name = "PM_LSU1_REJECT_ERAT_MISS",
+ .pme_code = 0xc40c7,
.pme_short_desc = "LSU1 reject due to ERAT miss",
.pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions due to an ERAT miss. Requests that miss the Derat are rejected and retried until the request hits in the Erat.",
- .pme_event_ids = { 226, 222, 222, 221, -1, -1 },
- .pme_group_vector = {
- 0x0000000000020000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_REJECT_ERAT_MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_REJECT_ERAT_MISS]
},
-#define POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_OTHER 366
[ POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_OTHER ] = {
.pme_name = "PM_L2SB_RCST_DISP_FAIL_OTHER",
+ .pme_code = 0x732e1,
.pme_short_desc = "L2 slice B RC store dispatch attempt failed due to other reasons",
.pme_long_desc = "A Read/Claim dispatch for a store failed for some reason other than Full or Collision conditions. Rejected dispatches do not count because they have not yet been attempted.",
- .pme_event_ids = { 152, 149, 148, 147, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000008ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_OTHER],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_OTHER]
},
-#define POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY 367
[ POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY ] = {
.pme_name = "PM_L2SC_RC_DISP_FAIL_CO_BUSY",
+ .pme_code = 0x703c2,
.pme_short_desc = "L2 slice C RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy",
.pme_long_desc = "A Read/Claim Dispatch was rejected at dispatch because the Castout Machine was busy. In the case of an RC starting up on a miss and the victim is valid, the CO machine must be available for the RC to process the access. If the CO is still busy working on an old castout, then the RC must not-ack the access if it is a miss(re-issued by the CIU). If it is a miss and the CO is available to process the castout, the RC will accept the access. Once the RC has finished, it can restart and process new accesses that result in a hit (or miss that doesn't need a CO) even though the CO is still processing a castout from a previous access.",
- .pme_event_ids = { 170, 167, 166, 165, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000080ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY]
},
-#define POWER5p_PME_PM_PMC4_OVERFLOW 368
[ POWER5p_PME_PM_PMC4_OVERFLOW ] = {
.pme_name = "PM_PMC4_OVERFLOW",
+ .pme_code = 0x10000a,
.pme_short_desc = "PMC4 Overflow",
.pme_long_desc = "Overflows from PMC4 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
- .pme_event_ids = { 301, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PMC4_OVERFLOW],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PMC4_OVERFLOW]
},
-#define POWER5p_PME_PM_L3SA_SNOOP_RETRY 369
[ POWER5p_PME_PM_L3SA_SNOOP_RETRY ] = {
.pme_name = "PM_L3SA_SNOOP_RETRY",
+ .pme_code = 0x731e3,
.pme_short_desc = "L3 slice A snoop retries",
.pme_long_desc = "Number of times an L3 retried a snoop because it got two in at the same time (one on snp_a, one on snp_b)",
- .pme_event_ids = { 183, 180, 179, 178, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000004000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SA_SNOOP_RETRY],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SA_SNOOP_RETRY]
},
-#define POWER5p_PME_PM_PTEG_FROM_L35_MOD 370
[ POWER5p_PME_PM_PTEG_FROM_L35_MOD ] = {
.pme_name = "PM_PTEG_FROM_L35_MOD",
+ .pme_code = 0x28309e,
.pme_short_desc = "PTEG loaded from L3.5 modified",
.pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L3 of a chip on the same module as this processor is located, due to a demand load.",
- .pme_event_ids = { -1, 304, 302, -1, -1, -1 },
- .pme_group_vector = {
- 0x1000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_L35_MOD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_L35_MOD]
},
-#define POWER5p_PME_PM_INST_FROM_L25_MOD 371
[ POWER5p_PME_PM_INST_FROM_L25_MOD ] = {
.pme_name = "PM_INST_FROM_L25_MOD",
+ .pme_code = 0x222096,
.pme_short_desc = "Instruction fetched from L2.5 modified",
.pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L2 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions.",
- .pme_event_ids = { -1, 117, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0200000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L25_MOD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L25_MOD]
},
-#define POWER5p_PME_PM_THRD_SMT_HANG 372
[ POWER5p_PME_PM_THRD_SMT_HANG ] = {
.pme_name = "PM_THRD_SMT_HANG",
+ .pme_code = 0x330e7,
.pme_short_desc = "SMT hang detected",
.pme_long_desc = "A hung thread was detected",
- .pme_event_ids = { 354, 349, 347, 343, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_SMT_HANG],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_SMT_HANG]
},
-#define POWER5p_PME_PM_CMPLU_STALL_ERAT_MISS 373
[ POWER5p_PME_PM_CMPLU_STALL_ERAT_MISS ] = {
.pme_name = "PM_CMPLU_STALL_ERAT_MISS",
+ .pme_code = 0x41109b,
.pme_short_desc = "Completion stall caused by ERAT miss",
.pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered an ERAT miss. This is a subset of PM_CMPLU_STALL_REJECT.",
- .pme_event_ids = { -1, -1, -1, 16, -1, -1 },
- .pme_group_vector = {
- 0x0000000040000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CMPLU_STALL_ERAT_MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CMPLU_STALL_ERAT_MISS]
},
-#define POWER5p_PME_PM_L3SA_MOD_TAG 374
[ POWER5p_PME_PM_L3SA_MOD_TAG ] = {
.pme_name = "PM_L3SA_MOD_TAG",
+ .pme_code = 0x720e3,
.pme_short_desc = "L3 slice A transition from modified to TAG",
.pme_long_desc = "L3 snooper detects someone doing a read to a line that is truly M in this L3(i.e. L3 going M->T or M->I(go_Mu case) Mu|Me are not included since they are formed due to a prev read op). Tx is not included since it is considered shared at this point.",
- .pme_event_ids = { 180, 177, 176, 175, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000100ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SA_MOD_TAG],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SA_MOD_TAG]
},
-#define POWER5p_PME_PM_INST_FROM_L2MISS 375
[ POWER5p_PME_PM_INST_FROM_L2MISS ] = {
.pme_name = "PM_INST_FROM_L2MISS",
+ .pme_code = 0x12209b,
.pme_short_desc = "Instruction fetched missed L2",
.pme_long_desc = "An instruction fetch group was fetched from beyond the local L2.",
- .pme_event_ids = { 120, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000800ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L2MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L2MISS]
},
-#define POWER5p_PME_PM_FLUSH_SYNC 376
[ POWER5p_PME_PM_FLUSH_SYNC ] = {
.pme_name = "PM_FLUSH_SYNC",
+ .pme_code = 0x330e1,
.pme_short_desc = "Flush caused by sync",
.pme_long_desc = "This thread has been flushed at dispatch due to a sync, lwsync, ptesync, or tlbsync instruction. This allows the other thread to have more machine resources for it to make progress until the sync finishes.",
- .pme_event_ids = { 56, 55, 55, 57, -1, -1 },
- .pme_group_vector = {
- 0x0000000000200000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FLUSH_SYNC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FLUSH_SYNC]
},
-#define POWER5p_PME_PM_MRK_GRP_DISP 377
[ POWER5p_PME_PM_MRK_GRP_DISP ] = {
.pme_name = "PM_MRK_GRP_DISP",
+ .pme_code = 0x100002,
.pme_short_desc = "Marked group dispatched",
.pme_long_desc = "A group containing a sampled instruction was dispatched",
- .pme_event_ids = { 281, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0030000040000000ULL,
- 0x0000000060000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_GRP_DISP],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_GRP_DISP]
},
-#define POWER5p_PME_PM_MEM_RQ_DISP_Q8to11 378
[ POWER5p_PME_PM_MEM_RQ_DISP_Q8to11 ] = {
.pme_name = "PM_MEM_RQ_DISP_Q8to11",
+ .pme_code = 0x722e6,
.pme_short_desc = "Memory read queue dispatched to queues 8-11",
.pme_long_desc = "A memory operation was dispatched to read queue 8,9,10 or 11. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 263, 261, 247, 349, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0002000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_RQ_DISP_Q8to11],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_RQ_DISP_Q8to11]
},
-#define POWER5p_PME_PM_L2SC_ST_HIT 379
[ POWER5p_PME_PM_L2SC_ST_HIT ] = {
.pme_name = "PM_L2SC_ST_HIT",
+ .pme_code = 0x733e2,
.pme_short_desc = "L2 slice C store hits",
.pme_long_desc = "A store request made from the core hit in the L2 directory. The event is provided on each of the three slices A, B, and C.",
- .pme_event_ids = { 174, 171, 170, 169, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000080ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_ST_HIT],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_ST_HIT]
},
-#define POWER5p_PME_PM_L2SB_MOD_TAG 380
[ POWER5p_PME_PM_L2SB_MOD_TAG ] = {
.pme_name = "PM_L2SB_MOD_TAG",
+ .pme_code = 0x720e1,
.pme_short_desc = "L2 slice B transition from modified to tagged",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.",
- .pme_event_ids = { 145, 142, 141, 140, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000001000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_MOD_TAG],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_MOD_TAG]
},
-#define POWER5p_PME_PM_CLB_EMPTY_CYC 381
[ POWER5p_PME_PM_CLB_EMPTY_CYC ] = {
.pme_name = "PM_CLB_EMPTY_CYC",
+ .pme_code = 0x410c6,
.pme_short_desc = "Cycles CLB empty",
.pme_long_desc = "Cycles when both thread's CLB is completely empty.",
- .pme_event_ids = { 13, 12, 12, 13, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000008ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CLB_EMPTY_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CLB_EMPTY_CYC]
},
-#define POWER5p_PME_PM_L2SB_ST_HIT 382
[ POWER5p_PME_PM_L2SB_ST_HIT ] = {
.pme_name = "PM_L2SB_ST_HIT",
+ .pme_code = 0x733e1,
.pme_short_desc = "L2 slice B store hits",
.pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A, B and C.",
- .pme_event_ids = { 158, 155, 154, 153, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000010ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_ST_HIT],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_ST_HIT]
},
-#define POWER5p_PME_PM_MEM_NONSPEC_RD_CANCEL 383
[ POWER5p_PME_PM_MEM_NONSPEC_RD_CANCEL ] = {
.pme_name = "PM_MEM_NONSPEC_RD_CANCEL",
+ .pme_code = 0x711c6,
.pme_short_desc = "Non speculative memory read cancelled",
.pme_long_desc = "A non-speculative read was cancelled because the combined response indicated it was sourced from aother L2 or L3. This event is sent from the Memory Controller clock domain and must be scaled accordingly",
- .pme_event_ids = { 254, 253, 249, 351, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0001000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_NONSPEC_RD_CANCEL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_NONSPEC_RD_CANCEL]
},
-#define POWER5p_PME_PM_BR_PRED_CR_TA 384
[ POWER5p_PME_PM_BR_PRED_CR_TA ] = {
.pme_name = "PM_BR_PRED_CR_TA",
+ .pme_code = 0x423087,
.pme_short_desc = "A conditional branch was predicted",
.pme_long_desc = " CR and target prediction",
- .pme_event_ids = { -1, -1, -1, 12, -1, -1 },
- .pme_group_vector = {
- 0x0000040000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_BR_PRED_CR_TA],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_BR_PRED_CR_TA]
},
-#define POWER5p_PME_PM_MRK_LSU0_FLUSH_SRQ 385
[ POWER5p_PME_PM_MRK_LSU0_FLUSH_SRQ ] = {
.pme_name = "PM_MRK_LSU0_FLUSH_SRQ",
+ .pme_code = 0x810c3,
.pme_short_desc = "LSU0 marked SRQ lhs flushes",
.pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { 289, 289, 283, 286, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0012000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU0_FLUSH_SRQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU0_FLUSH_SRQ]
},
-#define POWER5p_PME_PM_MRK_LSU_FLUSH_ULD 386
[ POWER5p_PME_PM_MRK_LSU_FLUSH_ULD ] = {
.pme_name = "PM_MRK_LSU_FLUSH_ULD",
+ .pme_code = 0x1810a8,
.pme_short_desc = "Marked unaligned load flushes",
.pme_long_desc = "A marked load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { 296, -1, -1, 295, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000100000000008ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU_FLUSH_ULD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU_FLUSH_ULD]
},
-#define POWER5p_PME_PM_INST_DISP_ATTEMPT 387
[ POWER5p_PME_PM_INST_DISP_ATTEMPT ] = {
.pme_name = "PM_INST_DISP_ATTEMPT",
+ .pme_code = 0x120e1,
.pme_short_desc = "Instructions dispatch attempted",
.pme_long_desc = "Number of PowerPC Instructions dispatched (attempted, not filtered by success.",
- .pme_event_ids = { 116, 114, 354, 254, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000100000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_DISP_ATTEMPT],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_DISP_ATTEMPT]
},
-#define POWER5p_PME_PM_INST_FROM_RMEM 388
[ POWER5p_PME_PM_INST_FROM_RMEM ] = {
.pme_name = "PM_INST_FROM_RMEM",
+ .pme_code = 0x422086,
.pme_short_desc = "Instruction fetched from remote memory",
.pme_long_desc = "An instruction fetch group was fetched from memory attached to a different module than this proccessor is located on. Fetch groups can contain up to 8 instructions",
- .pme_event_ids = { -1, -1, -1, 117, -1, -1 },
- .pme_group_vector = {
- 0x0080000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_RMEM],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_RMEM]
},
-#define POWER5p_PME_PM_ST_REF_L1_LSU0 389
[ POWER5p_PME_PM_ST_REF_L1_LSU0 ] = {
.pme_name = "PM_ST_REF_L1_LSU0",
+ .pme_code = 0xc10c1,
.pme_short_desc = "LSU0 L1 D cache store references",
.pme_long_desc = "Store references to the Data Cache by LSU0.",
- .pme_event_ids = { 328, 324, 323, 319, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_ST_REF_L1_LSU0],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_ST_REF_L1_LSU0]
},
-#define POWER5p_PME_PM_LSU0_DERAT_MISS 390
[ POWER5p_PME_PM_LSU0_DERAT_MISS ] = {
.pme_name = "PM_LSU0_DERAT_MISS",
+ .pme_code = 0x800c2,
.pme_short_desc = "LSU0 DERAT misses",
.pme_long_desc = "Total D-ERAT Misses by LSU0. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.",
- .pme_event_ids = { 206, 202, 202, 201, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_DERAT_MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_DERAT_MISS]
},
-#define POWER5p_PME_PM_FPU_STALL3 391
[ POWER5p_PME_PM_FPU_STALL3 ] = {
.pme_name = "PM_FPU_STALL3",
+ .pme_code = 0x202088,
.pme_short_desc = "FPU stalled in pipe3",
.pme_long_desc = "FPU has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. Combined Unit 0 + Unit 1.",
- .pme_event_ids = { -1, 87, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000080000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_STALL3],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_STALL3]
},
-#define POWER5p_PME_PM_L2SB_RCLD_DISP 392
[ POWER5p_PME_PM_L2SB_RCLD_DISP ] = {
.pme_name = "PM_L2SB_RCLD_DISP",
+ .pme_code = 0x701c1,
.pme_short_desc = "L2 slice B RC load dispatch attempt",
.pme_long_desc = "A Read/Claim dispatch for a Load was attempted",
- .pme_event_ids = { 146, 143, 142, 141, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000004ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_RCLD_DISP],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_RCLD_DISP]
},
-#define POWER5p_PME_PM_BR_PRED_CR 393
[ POWER5p_PME_PM_BR_PRED_CR ] = {
.pme_name = "PM_BR_PRED_CR",
+ .pme_code = 0x230e2,
.pme_short_desc = "A conditional branch was predicted",
.pme_long_desc = " CR prediction",
- .pme_event_ids = { 358, 352, 11, 347, -1, -1 },
- .pme_group_vector = {
- 0x0000040000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000400ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_BR_PRED_CR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_BR_PRED_CR]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_L2 394
[ POWER5p_PME_PM_MRK_DATA_FROM_L2 ] = {
.pme_name = "PM_MRK_DATA_FROM_L2",
+ .pme_code = 0x1c7087,
.pme_short_desc = "Marked data loaded from L2",
.pme_long_desc = "The processor's Data Cache was reloaded from the local L2 due to a marked load.",
- .pme_event_ids = { 269, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0080000000000000ULL,
- 0x0200000100000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L2],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L2]
},
-#define POWER5p_PME_PM_LSU0_FLUSH_SRQ 395
[ POWER5p_PME_PM_LSU0_FLUSH_SRQ ] = {
.pme_name = "PM_LSU0_FLUSH_SRQ",
+ .pme_code = 0xc00c3,
.pme_short_desc = "LSU0 SRQ lhs flushes",
.pme_long_desc = "A store was flushed by unit 0 because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { 208, 204, 204, 203, -1, -1 },
- .pme_group_vector = {
- 0x0000000001000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_FLUSH_SRQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_FLUSH_SRQ]
},
-#define POWER5p_PME_PM_FAB_PNtoNN_DIRECT 396
[ POWER5p_PME_PM_FAB_PNtoNN_DIRECT ] = {
.pme_name = "PM_FAB_PNtoNN_DIRECT",
+ .pme_code = 0x703c7,
.pme_short_desc = "PN to NN beat went straight to its destination",
.pme_long_desc = "Fabric Data beats that the base chip takes the inbound PN data and passes it through to the outbound NN bus without going into a sidecar. The signal is delivered at FBC speed and the count must be scaled.",
- .pme_event_ids = { 47, 46, 46, 48, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000040000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_PNtoNN_DIRECT],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_PNtoNN_DIRECT]
},
-#define POWER5p_PME_PM_IOPS_CMPL 397
[ POWER5p_PME_PM_IOPS_CMPL ] = {
.pme_name = "PM_IOPS_CMPL",
+ .pme_code = 0x1,
.pme_short_desc = "Internal operations completed",
.pme_long_desc = "Number of internal operations that completed.",
- .pme_event_ids = { 115, 113, 112, 112, -1, -1 },
- .pme_group_vector = {
- 0x01080911fff53010ULL,
- 0x110020f81d100700ULL,
- 0x0002002000000006ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_IOPS_CMPL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_IOPS_CMPL]
},
-#define POWER5p_PME_PM_L2SA_RCST_DISP 398
[ POWER5p_PME_PM_L2SA_RCST_DISP ] = {
.pme_name = "PM_L2SA_RCST_DISP",
+ .pme_code = 0x702c0,
.pme_short_desc = "L2 slice A RC store dispatch attempt",
.pme_long_desc = "A Read/Claim dispatch for a Store was attempted.",
- .pme_event_ids = { 134, 131, 130, 129, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000001ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_RCST_DISP],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_RCST_DISP]
},
-#define POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_OTHER 399
[ POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_OTHER ] = {
.pme_name = "PM_L2SA_RCST_DISP_FAIL_OTHER",
+ .pme_code = 0x732e0,
.pme_short_desc = "L2 slice A RC store dispatch attempt failed due to other reasons",
.pme_long_desc = "A Read/Claim dispatch for a store failed for some reason other than Full or Collision conditions. Rejected dispatches do not count because they have not yet been attempted.",
- .pme_event_ids = { 136, 133, 132, 131, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000001ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_OTHER],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_OTHER]
},
-#define POWER5p_PME_PM_L2SC_SHR_INV 400
[ POWER5p_PME_PM_L2SC_SHR_INV ] = {
.pme_name = "PM_L2SC_SHR_INV",
+ .pme_code = 0x710c2,
.pme_short_desc = "L2 slice C transition from shared to invalid",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A, B, and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.",
- .pme_event_ids = { 172, 169, 168, 167, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000002000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_SHR_INV],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_SHR_INV]
},
-#define POWER5p_PME_PM_SNOOP_RETRY_AB_COLLISION 401
[ POWER5p_PME_PM_SNOOP_RETRY_AB_COLLISION ] = {
.pme_name = "PM_SNOOP_RETRY_AB_COLLISION",
+ .pme_code = 0x735e6,
.pme_short_desc = "Snoop retry due to a b collision",
.pme_long_desc = "Snoop retry due to a b collision",
- .pme_event_ids = { 361, 355, 353, 350, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_RETRY_AB_COLLISION],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_RETRY_AB_COLLISION]
},
-#define POWER5p_PME_PM_FAB_PNtoVN_SIDECAR 402
[ POWER5p_PME_PM_FAB_PNtoVN_SIDECAR ] = {
.pme_name = "PM_FAB_PNtoVN_SIDECAR",
+ .pme_code = 0x733e7,
.pme_short_desc = "PN to VN beat went to sidecar first",
.pme_long_desc = "Fabric data beats that the base chip takes the inbound PN data and forwards it on to the outbound VN data bus after going into a sidecar first. The signal is delivered at FBC speed and the count must be scaled accordingly.",
- .pme_event_ids = { 50, 49, 49, 51, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000040000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_PNtoVN_SIDECAR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_PNtoVN_SIDECAR]
},
-#define POWER5p_PME_PM_LSU0_REJECT_LMQ_FULL 403
[ POWER5p_PME_PM_LSU0_REJECT_LMQ_FULL ] = {
.pme_name = "PM_LSU0_REJECT_LMQ_FULL",
+ .pme_code = 0xc40c1,
.pme_short_desc = "LSU0 reject due to LMQ full or missed data coming",
.pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected.",
- .pme_event_ids = { 214, 210, 210, 209, -1, -1 },
- .pme_group_vector = {
- 0x0000000000040000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_REJECT_LMQ_FULL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_REJECT_LMQ_FULL]
},
-#define POWER5p_PME_PM_LSU_LMQ_S0_ALLOC 404
[ POWER5p_PME_PM_LSU_LMQ_S0_ALLOC ] = {
.pme_name = "PM_LSU_LMQ_S0_ALLOC",
+ .pme_code = 0xc30e6,
.pme_short_desc = "LMQ slot 0 allocated",
.pme_long_desc = "The first entry in the LMQ was allocated.",
- .pme_event_ids = { 239, 236, 234, 233, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000080ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_LMQ_S0_ALLOC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_LMQ_S0_ALLOC]
},
-#define POWER5p_PME_PM_SNOOP_PW_RETRY_RQ 405
[ POWER5p_PME_PM_SNOOP_PW_RETRY_RQ ] = {
.pme_name = "PM_SNOOP_PW_RETRY_RQ",
+ .pme_code = 0x707c6,
.pme_short_desc = "Snoop partial-write retry due to collision with active read queue",
.pme_long_desc = "A snoop request for a partial write to memory was retried because it matched the cache line of an active read. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 315, 310, 308, 306, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000800000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_PW_RETRY_RQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_PW_RETRY_RQ]
},
-#define POWER5p_PME_PM_DTLB_REF 406
[ POWER5p_PME_PM_DTLB_REF ] = {
.pme_name = "PM_DTLB_REF",
+ .pme_code = 0xc20e4,
.pme_short_desc = "Data TLB references",
.pme_long_desc = "Total number of Data TLB references for all page sizes. Page size is determined at TLB reload time.",
- .pme_event_ids = { 33, 32, 32, 33, -1, -1 },
- .pme_group_vector = {
- 0x0002000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DTLB_REF],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DTLB_REF]
},
-#define POWER5p_PME_PM_PTEG_FROM_L3 407
[ POWER5p_PME_PM_PTEG_FROM_L3 ] = {
.pme_name = "PM_PTEG_FROM_L3",
+ .pme_code = 0x18308e,
.pme_short_desc = "PTEG loaded from L3",
.pme_long_desc = "A Page Table Entry was loaded into the TLB from the local L3 due to a demand load.",
- .pme_event_ids = { 307, -1, 301, -1, -1, -1 },
- .pme_group_vector = {
- 0x4000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_L3],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_L3]
},
-#define POWER5p_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY 408
[ POWER5p_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY ] = {
.pme_name = "PM_FAB_M1toVNorNN_SIDECAR_EMPTY",
+ .pme_code = 0x712c7,
.pme_short_desc = "M1 to VN/NN sidecar empty",
.pme_long_desc = "Fabric cycles when the Minus-1 jump sidecar (sidecars for mcm to mcm data transfer) is empty. The signal is delivered at FBC speed and the count must be scaled accordingly.",
- .pme_event_ids = { 44, 43, 43, 45, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000080000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY]
},
-#define POWER5p_PME_PM_LSU_SRQ_EMPTY_CYC 409
[ POWER5p_PME_PM_LSU_SRQ_EMPTY_CYC ] = {
.pme_name = "PM_LSU_SRQ_EMPTY_CYC",
+ .pme_code = 0x400015,
.pme_short_desc = "Cycles SRQ empty",
.pme_long_desc = "Cycles the Store Request Queue is empty",
- .pme_event_ids = { -1, -1, -1, 239, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000600ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_SRQ_EMPTY_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_SRQ_EMPTY_CYC]
},
-#define POWER5p_PME_PM_FPU1_STF 410
[ POWER5p_PME_PM_FPU1_STF ] = {
.pme_name = "PM_FPU1_STF",
+ .pme_code = 0x20e6,
.pme_short_desc = "FPU1 executed store instruction",
.pme_long_desc = "FPU1 has executed a Floating Point Store instruction.",
- .pme_event_ids = { 84, 83, 83, 85, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000010000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_STF],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_STF]
},
-#define POWER5p_PME_PM_LSU_LMQ_S0_VALID 411
[ POWER5p_PME_PM_LSU_LMQ_S0_VALID ] = {
.pme_name = "PM_LSU_LMQ_S0_VALID",
+ .pme_code = 0xc30e5,
.pme_short_desc = "LMQ slot 0 valid",
.pme_long_desc = "This signal is asserted every cycle when the first entry in the LMQ is valid. The LMQ had eight entries that are allocated FIFO",
- .pme_event_ids = { 240, 237, 235, 234, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000080ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_LMQ_S0_VALID],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_LMQ_S0_VALID]
},
-#define POWER5p_PME_PM_GCT_USAGE_00to59_CYC 412
[ POWER5p_PME_PM_GCT_USAGE_00to59_CYC ] = {
.pme_name = "PM_GCT_USAGE_00to59_CYC",
+ .pme_code = 0x10001f,
.pme_short_desc = "Cycles GCT less than 60% full",
.pme_long_desc = "Cycles when the Global Completion Table has fewer than 60% of its slots used. The GCT has 20 entries shared between threads.",
- .pme_event_ids = { 99, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000040ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GCT_USAGE_00to59_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GCT_USAGE_00to59_CYC]
},
-#define POWER5p_PME_PM_FPU_FMOV_FEST 413
[ POWER5p_PME_PM_FPU_FMOV_FEST ] = {
.pme_name = "PM_FPU_FMOV_FEST",
+ .pme_code = 0x301088,
.pme_short_desc = "FPU executed FMOV or FEST instructions",
.pme_long_desc = "The floating point unit has executed a move kind of instruction or one of the estimate instructions. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ.. Combined Unit 0 + Unit 1.",
- .pme_event_ids = { -1, -1, 84, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000020000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_FMOV_FEST],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_FMOV_FEST]
},
-#define POWER5p_PME_PM_DATA_FROM_L2MISS 414
[ POWER5p_PME_PM_DATA_FROM_L2MISS ] = {
.pme_name = "PM_DATA_FROM_L2MISS",
+ .pme_code = 0x3c309b,
.pme_short_desc = "Data loaded missed L2",
.pme_long_desc = "The processor's Data Cache was reloaded but not from the local L2.",
- .pme_event_ids = { -1, -1, 19, -1, -1, -1 },
- .pme_group_vector = {
- 0x0010000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_L2MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_L2MISS]
},
-#define POWER5p_PME_PM_XER_MAP_FULL_CYC 415
[ POWER5p_PME_PM_XER_MAP_FULL_CYC ] = {
.pme_name = "PM_XER_MAP_FULL_CYC",
+ .pme_code = 0x100c2,
.pme_short_desc = "Cycles XER mapper full",
.pme_long_desc = "The XER mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.",
- .pme_event_ids = { 357, 351, 350, 346, -1, -1 },
- .pme_group_vector = {
- 0x0000001000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_XER_MAP_FULL_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_XER_MAP_FULL_CYC]
},
-#define POWER5p_PME_PM_GRP_DISP_BLK_SB_CYC 416
[ POWER5p_PME_PM_GRP_DISP_BLK_SB_CYC ] = {
.pme_name = "PM_GRP_DISP_BLK_SB_CYC",
+ .pme_code = 0x130e1,
.pme_short_desc = "Cycles group dispatch blocked by scoreboard",
.pme_long_desc = "A scoreboard operation on a non-renamed resource has blocked dispatch.",
- .pme_event_ids = { 103, 103, 101, 102, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000004ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_DISP_BLK_SB_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_DISP_BLK_SB_CYC]
},
-#define POWER5p_PME_PM_FLUSH_SB 417
[ POWER5p_PME_PM_FLUSH_SB ] = {
.pme_name = "PM_FLUSH_SB",
+ .pme_code = 0x330e2,
.pme_short_desc = "Flush caused by scoreboard operation",
.pme_long_desc = "This thread has been flushed at dispatch because its scoreboard bit is set indicating that a non-renamed resource is being updated. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.",
- .pme_event_ids = { 55, 54, 54, 56, -1, -1 },
- .pme_group_vector = {
- 0x0000000000200000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FLUSH_SB],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FLUSH_SB]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR 418
[ POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR ] = {
.pme_name = "PM_MRK_DATA_FROM_L375_SHR",
+ .pme_code = 0x3c709e,
.pme_short_desc = "Marked data loaded from L3.75 shared",
.pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on a different module than this processor is located due to a marked load.",
- .pme_event_ids = { -1, -1, 269, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x2000000000000000ULL,
- 0x0000004000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR]
},
-#define POWER5p_PME_PM_MRK_GRP_CMPL 419
[ POWER5p_PME_PM_MRK_GRP_CMPL ] = {
.pme_name = "PM_MRK_GRP_CMPL",
+ .pme_code = 0x400013,
.pme_short_desc = "Marked group completed",
.pme_long_desc = "A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group.",
- .pme_event_ids = { -1, -1, -1, 278, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0020000000000000ULL,
- 0x0800000040000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_GRP_CMPL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_GRP_CMPL]
},
-#define POWER5p_PME_PM_SUSPENDED 420
[ POWER5p_PME_PM_SUSPENDED ] = {
.pme_name = "PM_SUSPENDED",
+ .pme_code = 0x0,
.pme_short_desc = "Suspended",
.pme_long_desc = "The counter is suspended (does not count).",
- .pme_event_ids = { 330, 326, 325, 321, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SUSPENDED],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SUSPENDED]
},
-#define POWER5p_PME_PM_SNOOP_RD_RETRY_QFULL 421
[ POWER5p_PME_PM_SNOOP_RD_RETRY_QFULL ] = {
.pme_name = "PM_SNOOP_RD_RETRY_QFULL",
+ .pme_code = 0x700c6,
.pme_short_desc = "Snoop read retry due to read queue full",
.pme_long_desc = "A snoop request for a read from memory was retried because the read queues were full. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 317, 312, 310, 308, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000100000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_RD_RETRY_QFULL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_RD_RETRY_QFULL]
},
-#define POWER5p_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC 422
[ POWER5p_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC ] = {
.pme_name = "PM_GRP_IC_MISS_BR_REDIR_NONSPEC",
+ .pme_code = 0x120e5,
.pme_short_desc = "Group experienced non-speculative I cache miss or branch redirect",
.pme_long_desc = "Group experienced non-speculative I cache miss or branch redirect",
- .pme_event_ids = { 107, 101, 99, 101, -1, -1 },
- .pme_group_vector = {
- 0x0000000080000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC]
},
-#define POWER5p_PME_PM_DATA_FROM_L35_SHR 423
[ POWER5p_PME_PM_DATA_FROM_L35_SHR ] = {
.pme_name = "PM_DATA_FROM_L35_SHR",
+ .pme_code = 0x1c309e,
.pme_short_desc = "Data loaded from L3.5 shared",
.pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on the same module as this processor is located due to a demand load.",
- .pme_event_ids = { 22, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0040000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_L35_SHR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_L35_SHR]
},
-#define POWER5p_PME_PM_L3SB_MOD_INV 424
[ POWER5p_PME_PM_L3SB_MOD_INV ] = {
.pme_name = "PM_L3SB_MOD_INV",
+ .pme_code = 0x730e4,
.pme_short_desc = "L3 slice B transition from modified to invalid",
.pme_long_desc = "L3 snooper detects someone doing a store to a line that is truly M in this L3 (i.e. L3 going M=>I). Mu|Me are not included since they are formed due to a prev read op. Tx is not included since it is considered shared at this point.",
- .pme_event_ids = { 186, 183, 182, 181, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000200ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SB_MOD_INV],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SB_MOD_INV]
},
-#define POWER5p_PME_PM_STCX_FAIL 425
[ POWER5p_PME_PM_STCX_FAIL ] = {
.pme_name = "PM_STCX_FAIL",
+ .pme_code = 0x820e1,
.pme_short_desc = "STCX failed",
.pme_long_desc = "A stcx (stwcx or stdcx) failed",
- .pme_event_ids = { 325, 320, 318, 316, -1, -1 },
- .pme_group_vector = {
- 0x0000002000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_STCX_FAIL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_STCX_FAIL]
},
-#define POWER5p_PME_PM_LD_MISS_L1_LSU1 426
[ POWER5p_PME_PM_LD_MISS_L1_LSU1 ] = {
.pme_name = "PM_LD_MISS_L1_LSU1",
+ .pme_code = 0xc10c5,
.pme_short_desc = "LSU1 L1 D cache load misses",
.pme_long_desc = "Load references that miss the Level 1 Data cache, by unit 1.",
- .pme_event_ids = { 200, 199, 199, 198, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LD_MISS_L1_LSU1],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LD_MISS_L1_LSU1]
},
-#define POWER5p_PME_PM_GRP_DISP 427
[ POWER5p_PME_PM_GRP_DISP ] = {
.pme_name = "PM_GRP_DISP",
+ .pme_code = 0x200002,
.pme_short_desc = "Group dispatches",
.pme_long_desc = "A group was dispatched",
- .pme_event_ids = { -1, 102, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x4000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_DISP],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_DISP]
},
-#define POWER5p_PME_PM_DC_PREF_DST 428
[ POWER5p_PME_PM_DC_PREF_DST ] = {
.pme_name = "PM_DC_PREF_DST",
+ .pme_code = 0x830e6,
.pme_short_desc = "DST (Data Stream Touch) stream start",
.pme_long_desc = "A prefetch stream was started using the DST instruction.",
- .pme_event_ids = { 28, 27, 27, 28, -1, -1 },
- .pme_group_vector = {
- 0x0000000000004000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DC_PREF_DST],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DC_PREF_DST]
},
-#define POWER5p_PME_PM_FPU1_DENORM 429
[ POWER5p_PME_PM_FPU1_DENORM ] = {
.pme_name = "PM_FPU1_DENORM",
+ .pme_code = 0x20e4,
.pme_short_desc = "FPU1 received denormalized data",
.pme_long_desc = "FPU1 has encountered a denormalized operand.",
- .pme_event_ids = { 73, 72, 72, 74, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000400000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_DENORM],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_DENORM]
},
-#define POWER5p_PME_PM_FPU0_FPSCR 430
[ POWER5p_PME_PM_FPU0_FPSCR ] = {
.pme_name = "PM_FPU0_FPSCR",
+ .pme_code = 0x30e0,
.pme_short_desc = "FPU0 executed FPSCR instruction",
.pme_long_desc = "FPU0 has executed FPSCR move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*, mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 65, 64, 64, 66, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000001000000ULL,
- 0x0000000000000800ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_FPSCR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_FPSCR]
},
-#define POWER5p_PME_PM_DATA_FROM_L2 431
[ POWER5p_PME_PM_DATA_FROM_L2 ] = {
.pme_name = "PM_DATA_FROM_L2",
+ .pme_code = 0x1c3087,
.pme_short_desc = "Data loaded from L2",
.pme_long_desc = "The processor's Data Cache was reloaded from the local L2 due to a demand load.",
- .pme_event_ids = { 18, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000200000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000020ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_L2],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_L2]
},
-#define POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR 432
[ POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR ] = {
.pme_name = "PM_L2SA_RCLD_DISP_FAIL_ADDR",
+ .pme_code = 0x711c0,
.pme_short_desc = "L2 slice A RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ",
.pme_long_desc = "A Read/Claim dispatch for a load failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.",
- .pme_event_ids = { 131, 128, 127, 126, -1, -1 },
- .pme_group_vector = {
- 0x8000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR]
},
-#define POWER5p_PME_PM_FPU_1FLOP 433
[ POWER5p_PME_PM_FPU_1FLOP ] = {
.pme_name = "PM_FPU_1FLOP",
+ .pme_code = 0x100090,
.pme_short_desc = "FPU executed one flop instruction",
.pme_long_desc = "The floating point unit has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations.",
- .pme_event_ids = { 85, -1, -1, 86, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000040000ULL,
- 0x0000000000424000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_1FLOP],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_1FLOP]
},
-#define POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER 434
[ POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER ] = {
.pme_name = "PM_L2SC_RCLD_DISP_FAIL_OTHER",
+ .pme_code = 0x731e2,
.pme_short_desc = "L2 slice C RC load dispatch attempt failed due to other reasons",
.pme_long_desc = "A Read/Claim dispatch for a load failed for some reason other than Full or Collision conditions.",
- .pme_event_ids = { 164, 161, 160, 159, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000020ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER]
},
-#define POWER5p_PME_PM_FPU0_FSQRT 435
[ POWER5p_PME_PM_FPU0_FSQRT ] = {
.pme_name = "PM_FPU0_FSQRT",
+ .pme_code = 0xc2,
.pme_short_desc = "FPU0 executed FSQRT instruction",
.pme_long_desc = "FPU0 has executed a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 67, 66, 66, 68, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000200000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_FSQRT],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_FSQRT]
},
-#define POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL 436
[ POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL ] = {
.pme_name = "PM_L2SC_RCST_DISP_FAIL_RC_FULL",
+ .pme_code = 0x722e1,
.pme_short_desc = "L2 slice C RC store dispatch attempt failed due to all RC full",
.pme_long_desc = "A Read/Claim dispatch for a store failed because all RC machines are busy.",
- .pme_event_ids = { 169, 166, 165, 164, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000040ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL]
},
-#define POWER5p_PME_PM_LD_REF_L1 437
[ POWER5p_PME_PM_LD_REF_L1 ] = {
.pme_name = "PM_LD_REF_L1",
+ .pme_code = 0x1c10a8,
.pme_short_desc = "L1 D cache load references",
.pme_long_desc = "Load references to the Level 1 Data Cache. Combined unit 0 + 1.",
- .pme_event_ids = { 201, -1, -1, 196, -1, -1 },
- .pme_group_vector = {
- 0x0004100000000000ULL,
- 0x0000000000000000ULL,
- 0x00000000052040e0ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LD_REF_L1],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LD_REF_L1]
},
-#define POWER5p_PME_PM_INST_FROM_L1 438
[ POWER5p_PME_PM_INST_FROM_L1 ] = {
.pme_name = "PM_INST_FROM_L1",
+ .pme_code = 0x22208d,
.pme_short_desc = "Instruction fetched from L1",
.pme_long_desc = "An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions",
- .pme_event_ids = { -1, 116, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0080000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000020ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L1],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L1]
},
-#define POWER5p_PME_PM_TLBIE_HELD 439
[ POWER5p_PME_PM_TLBIE_HELD ] = {
.pme_name = "PM_TLBIE_HELD",
+ .pme_code = 0x130e4,
.pme_short_desc = "TLBIE held at dispatch",
.pme_long_desc = "Cycles a TLBIE instruction was held at dispatch.",
- .pme_event_ids = { 355, 350, 349, 344, -1, -1 },
- .pme_group_vector = {
- 0x0000000000020000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_TLBIE_HELD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_TLBIE_HELD]
},
-#define POWER5p_PME_PM_DC_PREF_OUT_OF_STREAMS 440
[ POWER5p_PME_PM_DC_PREF_OUT_OF_STREAMS ] = {
.pme_name = "PM_DC_PREF_OUT_OF_STREAMS",
+ .pme_code = 0xc50c2,
.pme_short_desc = "D cache out of prefetch streams",
.pme_long_desc = "A new prefetch stream was detected but no more stream entries were available.",
- .pme_event_ids = { 27, 26, 26, 27, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000800ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DC_PREF_OUT_OF_STREAMS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DC_PREF_OUT_OF_STREAMS]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD_CYC 441
[ POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L25_MOD_CYC",
+ .pme_code = 0x4c70a2,
.pme_short_desc = "Marked load latency from L2.5 modified",
.pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
- .pme_event_ids = { -1, -1, -1, 264, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0080000000000000ULL,
- 0x0000000100000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD_CYC]
},
-#define POWER5p_PME_PM_MRK_LSU1_FLUSH_SRQ 442
[ POWER5p_PME_PM_MRK_LSU1_FLUSH_SRQ ] = {
.pme_name = "PM_MRK_LSU1_FLUSH_SRQ",
+ .pme_code = 0x810c7,
.pme_short_desc = "LSU1 marked SRQ lhs flushes",
.pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { 293, 293, 287, 290, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0020000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU1_FLUSH_SRQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU1_FLUSH_SRQ]
},
-#define POWER5p_PME_PM_MEM_RQ_DISP_Q0to3 443
[ POWER5p_PME_PM_MEM_RQ_DISP_Q0to3 ] = {
.pme_name = "PM_MEM_RQ_DISP_Q0to3",
+ .pme_code = 0x702c6,
.pme_short_desc = "Memory read queue dispatched to queues 0-3",
.pme_long_desc = "A memory operation was dispatched to read queue 0,1,2, or 3. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
- .pme_event_ids = { 260, 256, 257, 256, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0002000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_RQ_DISP_Q0to3],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_RQ_DISP_Q0to3]
},
-#define POWER5p_PME_PM_ST_REF_L1_LSU1 444
[ POWER5p_PME_PM_ST_REF_L1_LSU1 ] = {
.pme_name = "PM_ST_REF_L1_LSU1",
+ .pme_code = 0xc10c4,
.pme_short_desc = "LSU1 L1 D cache store references",
.pme_long_desc = "Store references to the Data Cache by LSU1.",
- .pme_event_ids = { 329, 325, 324, 320, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_ST_REF_L1_LSU1],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_ST_REF_L1_LSU1]
},
-#define POWER5p_PME_PM_MRK_LD_MISS_L1 445
[ POWER5p_PME_PM_MRK_LD_MISS_L1 ] = {
.pme_name = "PM_MRK_LD_MISS_L1",
+ .pme_code = 0x182088,
.pme_short_desc = "Marked L1 D cache load misses",
.pme_long_desc = "Marked L1 D cache load misses",
- .pme_event_ids = { 285, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000080000000004ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LD_MISS_L1],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LD_MISS_L1]
},
-#define POWER5p_PME_PM_L1_WRITE_CYC 446
[ POWER5p_PME_PM_L1_WRITE_CYC ] = {
.pme_name = "PM_L1_WRITE_CYC",
+ .pme_code = 0x230e7,
.pme_short_desc = "Cycles writing to instruction L1",
.pme_long_desc = "Cycles that a cache line was written to the instruction cache.",
- .pme_event_ids = { 127, 124, 123, 122, -1, -1 },
- .pme_group_vector = {
- 0x0000000000010000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L1_WRITE_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L1_WRITE_CYC]
},
-#define POWER5p_PME_PM_L2SC_ST_REQ 447
[ POWER5p_PME_PM_L2SC_ST_REQ ] = {
.pme_name = "PM_L2SC_ST_REQ",
+ .pme_code = 0x723e2,
.pme_short_desc = "L2 slice C store requests",
.pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A, B, and C.",
- .pme_event_ids = { 175, 172, 171, 170, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000080ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_ST_REQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_ST_REQ]
},
-#define POWER5p_PME_PM_CMPLU_STALL_FDIV 448
[ POWER5p_PME_PM_CMPLU_STALL_FDIV ] = {
.pme_name = "PM_CMPLU_STALL_FDIV",
+ .pme_code = 0x21109b,
.pme_short_desc = "Completion stall caused by FDIV or FQRT instruction",
.pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a floating point divide or square root instruction. This is a subset of PM_CMPLU_STALL_FPU.",
- .pme_event_ids = { -1, 15, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000100000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CMPLU_STALL_FDIV],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CMPLU_STALL_FDIV]
},
-#define POWER5p_PME_PM_THRD_SEL_OVER_CLB_EMPTY 449
[ POWER5p_PME_PM_THRD_SEL_OVER_CLB_EMPTY ] = {
.pme_name = "PM_THRD_SEL_OVER_CLB_EMPTY",
+ .pme_code = 0x410c2,
.pme_short_desc = "Thread selection overrides caused by CLB empty",
.pme_long_desc = "Thread selection was overridden because one thread's CLB was empty.",
- .pme_event_ids = { 348, 343, 341, 337, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000004000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_SEL_OVER_CLB_EMPTY],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_SEL_OVER_CLB_EMPTY]
},
-#define POWER5p_PME_PM_BR_MPRED_CR 450
[ POWER5p_PME_PM_BR_MPRED_CR ] = {
.pme_name = "PM_BR_MPRED_CR",
+ .pme_code = 0x230e5,
.pme_short_desc = "Branch mispredictions due to CR bit setting",
.pme_long_desc = "A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.",
- .pme_event_ids = { 10, 9, 9, 10, -1, -1 },
- .pme_group_vector = {
- 0x0000020000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_BR_MPRED_CR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_BR_MPRED_CR]
},
-#define POWER5p_PME_PM_L3SB_MOD_TAG 451
[ POWER5p_PME_PM_L3SB_MOD_TAG ] = {
.pme_name = "PM_L3SB_MOD_TAG",
+ .pme_code = 0x720e4,
.pme_short_desc = "L3 slice B transition from modified to TAG",
.pme_long_desc = "L3 snooper detects someone doing a read to a line that is truly M in this L3(i.e. L3 going M->T or M->I(go_Mu case); Mu|Me are not included since they are formed due to a prev read op). Tx is not included since it is considered shared at this point.",
- .pme_event_ids = { 187, 184, 183, 182, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000200ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SB_MOD_TAG],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SB_MOD_TAG]
},
-#define POWER5p_PME_PM_MRK_DATA_FROM_L2MISS 452
[ POWER5p_PME_PM_MRK_DATA_FROM_L2MISS ] = {
.pme_name = "PM_MRK_DATA_FROM_L2MISS",
+ .pme_code = 0x3c709b,
.pme_short_desc = "Marked data loaded missed L2",
.pme_long_desc = "DL1 was reloaded from beyond L2 due to a marked demand load.",
- .pme_event_ids = { -1, -1, 266, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000001000000000ULL,
- 0x0000000000000000ULL,
- 0x0200000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L2MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L2MISS]
},
-#define POWER5p_PME_PM_LSU_REJECT_SRQ 453
[ POWER5p_PME_PM_LSU_REJECT_SRQ ] = {
.pme_name = "PM_LSU_REJECT_SRQ",
+ .pme_code = 0x1c4088,
.pme_short_desc = "LSU SRQ lhs rejects",
.pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions because of Load Hit Store conditions. Loads are rejected when data is needed from a previous store instruction but store forwarding is not possible because the data is not fully contained in the Store Data Queue or is not yet available in the Store Data Queue. Combined Unit 0 + 1.",
- .pme_event_ids = { 245, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000080000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_REJECT_SRQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_REJECT_SRQ]
},
-#define POWER5p_PME_PM_LD_MISS_L1 454
[ POWER5p_PME_PM_LD_MISS_L1 ] = {
.pme_name = "PM_LD_MISS_L1",
+ .pme_code = 0x3c1088,
.pme_short_desc = "L1 D cache load misses",
.pme_long_desc = "Load references that miss the Level 1 Data cache. Combined unit 0 + 1.",
- .pme_event_ids = { -1, -1, 195, -1, -1, -1 },
- .pme_group_vector = {
- 0x0004100000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000004900100ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LD_MISS_L1],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LD_MISS_L1]
},
-#define POWER5p_PME_PM_INST_FROM_PREF 455
[ POWER5p_PME_PM_INST_FROM_PREF ] = {
.pme_name = "PM_INST_FROM_PREF",
+ .pme_code = 0x32208d,
.pme_short_desc = "Instruction fetched from prefetch",
.pme_long_desc = "An instruction fetch group was fetched from the prefetch buffer. Fetch groups can contain up to 8 instructions",
- .pme_event_ids = { -1, -1, 118, -1, -1, -1 },
- .pme_group_vector = {
- 0x0080000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_PREF],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_PREF]
},
-#define POWER5p_PME_PM_STCX_PASS 456
[ POWER5p_PME_PM_STCX_PASS ] = {
.pme_name = "PM_STCX_PASS",
+ .pme_code = 0x820e5,
.pme_short_desc = "Stcx passes",
.pme_long_desc = "A stcx (stwcx or stdcx) instruction was successful",
- .pme_event_ids = { 326, 321, 319, 317, -1, -1 },
- .pme_group_vector = {
- 0x0000002000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_STCX_PASS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_STCX_PASS]
},
-#define POWER5p_PME_PM_DC_INV_L2 457
[ POWER5p_PME_PM_DC_INV_L2 ] = {
.pme_name = "PM_DC_INV_L2",
+ .pme_code = 0xc10c7,
.pme_short_desc = "L1 D cache entries invalidated from L2",
.pme_long_desc = "A dcache invalidated was received from the L2 because a line in L2 was castout.",
- .pme_event_ids = { 26, 25, 25, 26, -1, -1 },
- .pme_group_vector = {
- 0x4000000000100000ULL,
- 0x0000000000000000ULL,
- 0x0000000000800000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DC_INV_L2],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DC_INV_L2]
},
-#define POWER5p_PME_PM_LSU_SRQ_FULL_CYC 458
[ POWER5p_PME_PM_LSU_SRQ_FULL_CYC ] = {
.pme_name = "PM_LSU_SRQ_FULL_CYC",
+ .pme_code = 0x110c3,
.pme_short_desc = "Cycles SRQ full",
.pme_long_desc = "Cycles the Store Request Queue is full.",
- .pme_event_ids = { 246, 244, 241, 240, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000500ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_SRQ_FULL_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_SRQ_FULL_CYC]
},
-#define POWER5p_PME_PM_FPU_FIN 459
[ POWER5p_PME_PM_FPU_FIN ] = {
.pme_name = "PM_FPU_FIN",
+ .pme_code = 0x401088,
.pme_short_desc = "FPU produced a result",
.pme_long_desc = "FPU finished, produced a result. This only indicates finish, not completion. Combined Unit 0 + Unit 1. Floating Point Stores are included in this count but not Floating Point Loads., , , XYZs",
- .pme_event_ids = { -1, -1, -1, 88, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0100000000040000ULL,
- 0x0000000202070000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_FIN],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_FIN]
},
-#define POWER5p_PME_PM_LSU_SRQ_STFWD 460
[ POWER5p_PME_PM_LSU_SRQ_STFWD ] = {
.pme_name = "PM_LSU_SRQ_STFWD",
+ .pme_code = 0x2c6088,
.pme_short_desc = "SRQ store forwarded",
.pme_long_desc = "Data from a store instruction was forwarded to a load. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. Combined Unit 0 + 1.",
- .pme_event_ids = { -1, 247, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000200ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_SRQ_STFWD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_SRQ_STFWD]
},
-#define POWER5p_PME_PM_L2SA_SHR_MOD 461
[ POWER5p_PME_PM_L2SA_SHR_MOD ] = {
.pme_name = "PM_L2SA_SHR_MOD",
+ .pme_code = 0x700c0,
.pme_short_desc = "L2 slice A transition from shared to modified",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A, B, and C.",
- .pme_event_ids = { 141, 138, 137, 136, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000800ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_SHR_MOD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_SHR_MOD]
},
-#define POWER5p_PME_PM_0INST_CLB_CYC 462
[ POWER5p_PME_PM_0INST_CLB_CYC ] = {
.pme_name = "PM_0INST_CLB_CYC",
+ .pme_code = 0x400c0,
.pme_short_desc = "Cycles no instructions in CLB",
.pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.",
- .pme_event_ids = { 0, 0, 0, 0, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000008ULL,
- 0x0000004000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_0INST_CLB_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_0INST_CLB_CYC]
},
-#define POWER5p_PME_PM_FXU0_FIN 463
[ POWER5p_PME_PM_FXU0_FIN ] = {
.pme_name = "PM_FXU0_FIN",
+ .pme_code = 0x130e2,
.pme_short_desc = "FXU0 produced a result",
.pme_long_desc = "The Fixed Point unit 0 finished an instruction and produced a result. Instructions that finish may not necessary complete.",
- .pme_event_ids = { 94, 91, 91, 94, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000080000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FXU0_FIN],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FXU0_FIN]
},
-#define POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL 464
[ POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL ] = {
.pme_name = "PM_L2SB_RCST_DISP_FAIL_RC_FULL",
+ .pme_code = 0x722e2,
.pme_short_desc = "L2 slice B RC store dispatch attempt failed due to all RC full",
.pme_long_desc = "A Read/Claim dispatch for a store failed because all RC machines are busy.",
- .pme_event_ids = { 153, 150, 149, 148, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000008ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL]
},
-#define POWER5p_PME_PM_THRD_GRP_CMPL_BOTH_CYC 465
[ POWER5p_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = {
.pme_name = "PM_THRD_GRP_CMPL_BOTH_CYC",
+ .pme_code = 0x200013,
.pme_short_desc = "Cycles group completed by both threads",
.pme_long_desc = "Cycles that both threads completed.",
- .pme_event_ids = { -1, 327, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000001000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_GRP_CMPL_BOTH_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_GRP_CMPL_BOTH_CYC]
},
-#define POWER5p_PME_PM_PMC5_OVERFLOW 466
[ POWER5p_PME_PM_PMC5_OVERFLOW ] = {
.pme_name = "PM_PMC5_OVERFLOW",
+ .pme_code = 0x10001a,
.pme_short_desc = "PMC5 Overflow",
.pme_long_desc = "Overflows from PMC5 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
- .pme_event_ids = { 302, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PMC5_OVERFLOW],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PMC5_OVERFLOW]
},
-#define POWER5p_PME_PM_FPU0_FDIV 467
[ POWER5p_PME_PM_FPU0_FDIV ] = {
.pme_name = "PM_FPU0_FDIV",
+ .pme_code = 0xc0,
.pme_short_desc = "FPU0 executed FDIV instruction",
.pme_long_desc = "FPU0 has executed a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.",
- .pme_event_ids = { 60, 59, 59, 61, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000800000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_FDIV],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_FDIV]
},
-#define POWER5p_PME_PM_PTEG_FROM_L375_SHR 468
[ POWER5p_PME_PM_PTEG_FROM_L375_SHR ] = {
.pme_name = "PM_PTEG_FROM_L375_SHR",
+ .pme_code = 0x38309e,
.pme_short_desc = "PTEG loaded from L3.75 shared",
.pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (S) data from the L3 of a chip on a different module than this processor is located, due to a demand load.",
- .pme_event_ids = { -1, -1, 303, -1, -1, -1 },
- .pme_group_vector = {
- 0x1000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_L375_SHR],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_L375_SHR]
},
-#define POWER5p_PME_PM_HV_CYC 469
[ POWER5p_PME_PM_HV_CYC ] = {
.pme_name = "PM_HV_CYC",
+ .pme_code = 0x20000b,
.pme_short_desc = "Hypervisor Cycles",
.pme_long_desc = "Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)",
- .pme_event_ids = { -1, 107, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000800000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_HV_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_HV_CYC]
},
-#define POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY 470
[ POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY ] = {
.pme_name = "PM_L2SA_RC_DISP_FAIL_CO_BUSY",
+ .pme_code = 0x703c0,
.pme_short_desc = "L2 slice A RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy",
.pme_long_desc = "A Read/Claim Dispatch was rejected at dispatch because the Castout Machine was busy. In the case of an RC starting up on a miss and the victim is valid, the CO machine must be available for the RC to process the access. If the CO is still busy working on an old castout, then the RC must not-ack the access if it is a miss(re-issued by the CIU). If it is a miss and the CO is available to process the castout, the RC will accept the access. Once the RC has finished, it can restart and process new accesses that result in a hit (or miss that doesn't need a CO) even though the CO is still processing a castout from a previous access.",
- .pme_event_ids = { 138, 135, 134, 133, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000002ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY]
},
-#define POWER5p_PME_PM_THRD_PRIO_DIFF_0_CYC 471
[ POWER5p_PME_PM_THRD_PRIO_DIFF_0_CYC ] = {
.pme_name = "PM_THRD_PRIO_DIFF_0_CYC",
+ .pme_code = 0x430e3,
.pme_short_desc = "Cycles no thread priority difference",
.pme_long_desc = "Cycles when this thread's priority is equal to the other thread's priority.",
- .pme_event_ids = { 341, 336, 334, 330, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000100000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_DIFF_0_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_DIFF_0_CYC]
},
-#define POWER5p_PME_PM_LR_CTR_MAP_FULL_CYC 472
[ POWER5p_PME_PM_LR_CTR_MAP_FULL_CYC ] = {
.pme_name = "PM_LR_CTR_MAP_FULL_CYC",
+ .pme_code = 0x100c6,
.pme_short_desc = "Cycles LR/CTR mapper full",
.pme_long_desc = "The LR/CTR mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.",
- .pme_event_ids = { 204, 200, 200, 199, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LR_CTR_MAP_FULL_CYC],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LR_CTR_MAP_FULL_CYC]
},
-#define POWER5p_PME_PM_L3SB_SHR_INV 473
[ POWER5p_PME_PM_L3SB_SHR_INV ] = {
.pme_name = "PM_L3SB_SHR_INV",
+ .pme_code = 0x710c4,
.pme_short_desc = "L3 slice B transition from shared to invalid",
.pme_long_desc = "L3 snooper detects someone doing a store to a line that is Sx in this L3(i.e. invalidate hit SX and dispatched).",
- .pme_event_ids = { 189, 186, 185, 184, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000200ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SB_SHR_INV],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SB_SHR_INV]
},
-#define POWER5p_PME_PM_DATA_FROM_RMEM 474
[ POWER5p_PME_PM_DATA_FROM_RMEM ] = {
.pme_name = "PM_DATA_FROM_RMEM",
+ .pme_code = 0x1c30a1,
.pme_short_desc = "Data loaded from remote memory",
.pme_long_desc = "The processor's Data Cache was reloaded from memory attached to a different module than this proccessor is located on.",
- .pme_event_ids = { 24, -1, -1, 24, -1, -1 },
- .pme_group_vector = {
- 0x0010000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000010000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_RMEM],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_RMEM]
},
-#define POWER5p_PME_PM_DATA_FROM_L275_MOD 475
[ POWER5p_PME_PM_DATA_FROM_L275_MOD ] = {
.pme_name = "PM_DATA_FROM_L275_MOD",
+ .pme_code = 0x1c30a3,
.pme_short_desc = "Data loaded from L2.75 modified",
.pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 on a different module than this processor is located due to a demand load.",
- .pme_event_ids = { 20, -1, -1, 22, -1, -1 },
- .pme_group_vector = {
- 0x0020000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_L275_MOD],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_L275_MOD]
},
-#define POWER5p_PME_PM_LSU0_REJECT_SRQ 476
[ POWER5p_PME_PM_LSU0_REJECT_SRQ ] = {
.pme_name = "PM_LSU0_REJECT_SRQ",
+ .pme_code = 0xc40c0,
.pme_short_desc = "LSU0 SRQ lhs rejects",
.pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because of Load Hit Store conditions. Loads are rejected when data is needed from a previous store instruction but store forwarding is not possible because the data is not fully contained in the Store Data Queue or is not yet available in the Store Data Queue.",
- .pme_event_ids = { 216, 212, 212, 211, -1, -1 },
- .pme_group_vector = {
- 0x0000000000004000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_REJECT_SRQ],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_REJECT_SRQ]
},
-#define POWER5p_PME_PM_LSU1_DERAT_MISS 477
[ POWER5p_PME_PM_LSU1_DERAT_MISS ] = {
.pme_name = "PM_LSU1_DERAT_MISS",
+ .pme_code = 0x800c6,
.pme_short_desc = "LSU1 DERAT misses",
.pme_long_desc = "A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.",
- .pme_event_ids = { 219, 215, 215, 214, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_DERAT_MISS],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_DERAT_MISS]
},
-#define POWER5p_PME_PM_MRK_LSU_FIN 478
[ POWER5p_PME_PM_MRK_LSU_FIN ] = {
.pme_name = "PM_MRK_LSU_FIN",
+ .pme_code = 0x400014,
.pme_short_desc = "Marked instruction LSU processing finished",
.pme_long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, -1, -1, 293, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0010000000000000ULL,
- 0x0400000020000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU_FIN],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU_FIN]
},
-#define POWER5p_PME_PM_DTLB_MISS_16M 479
[ POWER5p_PME_PM_DTLB_MISS_16M ] = {
.pme_name = "PM_DTLB_MISS_16M",
+ .pme_code = 0x3c208d,
.pme_short_desc = "Data TLB miss for 16M page",
.pme_long_desc = "Data TLB references to 16MB pages that missed the TLB. Page size is determined at TLB reload time.",
- .pme_event_ids = { -1, -1, 31, -1, -1, -1 },
- .pme_group_vector = {
- 0x0001000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DTLB_MISS_16M],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DTLB_MISS_16M]
},
-#define POWER5p_PME_PM_LSU0_FLUSH_UST 480
[ POWER5p_PME_PM_LSU0_FLUSH_UST ] = {
.pme_name = "PM_LSU0_FLUSH_UST",
+ .pme_code = 0xc00c1,
.pme_short_desc = "LSU0 unaligned store flushes",
.pme_long_desc = "A store was flushed from unit 0 because it was unaligned (crossed a 4K boundary).",
- .pme_event_ids = { 210, 206, 206, 205, -1, -1 },
- .pme_group_vector = {
- 0x0000000008000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_FLUSH_UST],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_FLUSH_UST]
},
-#define POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY 481
[ POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY ] = {
.pme_name = "PM_L2SB_RC_DISP_FAIL_CO_BUSY",
+ .pme_code = 0x703c1,
.pme_short_desc = "L2 slice B RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy",
.pme_long_desc = "A Read/Claim Dispatch was rejected at dispatch because the Castout Machine was busy. In the case of an RC starting up on a miss and the victim is valid, the CO machine must be available for the RC to process the access. If the CO is still busy working on an old castout, then the RC must not-ack the access if it is a miss(re-issued by the CIU). If it is a miss and the CO is available to process the castout, the RC will accept the access. Once the RC has finished, it can restart and process new accesses that result in a hit (or miss that doesn't need a CO) even though the CO is still processing a castout from a previous access.",
- .pme_event_ids = { 154, 151, 150, 149, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000010ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY]
},
-#define POWER5p_PME_PM_L2SC_MOD_TAG 482
[ POWER5p_PME_PM_L2SC_MOD_TAG ] = {
.pme_name = "PM_L2SC_MOD_TAG",
+ .pme_code = 0x720e2,
.pme_short_desc = "L2 slice C transition from modified to tagged",
.pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.",
- .pme_event_ids = { 161, 158, 157, 156, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000002000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_MOD_TAG],
+ .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_MOD_TAG]
}
};
#define POWER5p_PME_EVENT_COUNT 483
-static pmg_power5p_group_t power5p_groups[] = {
+static const int power5p_group_event_ids[][POWER5p_NUM_EVENT_COUNTERS] = {
+ [ 0 ] = { 312, 302, 113, 21, 0, 0 },
+ [ 1 ] = { 2, 95, 100, 21, 0, 0 },
+ [ 2 ] = { 105, 104, 101, 113, 0, 0 },
+ [ 3 ] = { 0, 2, 12, 267, 0, 0 },
+ [ 4 ] = { 6, 6, 292, 112, 0, 0 },
+ [ 5 ] = { 98, 97, 95, 98, 0, 0 },
+ [ 6 ] = { 99, 98, 96, 97, 0, 0 },
+ [ 7 ] = { 242, 241, 234, 234, 0, 0 },
+ [ 8 ] = { 247, 246, 244, 240, 0, 0 },
+ [ 9 ] = { 238, 247, 236, 239, 0, 0 },
+ [ 10 ] = { 237, 244, 236, 239, 0, 0 },
+ [ 11 ] = { 120, 115, 26, 29, 0, 0 },
+ [ 12 ] = { 115, 13, 122, 108, 0, 0 },
+ [ 13 ] = { 1, 227, 172, 112, 0, 0 },
+ [ 14 ] = { 216, 225, 27, 171, 0, 0 },
+ [ 15 ] = { 244, 242, 53, 294, 0, 0 },
+ [ 16 ] = { 215, 224, 112, 122, 0, 0 },
+ [ 17 ] = { 213, 222, 245, 344, 0, 0 },
+ [ 18 ] = { 214, 223, 112, 9, 0, 0 },
+ [ 19 ] = { 245, 243, 228, 53, 0, 0 },
+ [ 20 ] = { 115, 233, 53, 26, 0, 0 },
+ [ 21 ] = { 124, 113, 54, 57, 0, 0 },
+ [ 22 ] = { 233, 230, 112, 226, 0, 0 },
+ [ 23 ] = { 207, 216, 228, 112, 0, 0 },
+ [ 24 ] = { 208, 217, 112, 226, 0, 0 },
+ [ 25 ] = { 235, 233, 8, 112, 0, 0 },
+ [ 26 ] = { 209, 218, 228, 112, 0, 0 },
+ [ 27 ] = { 210, 219, 112, 226, 0, 0 },
+ [ 28 ] = { 232, 113, 290, 229, 0, 0 },
+ [ 29 ] = { 109, 17, 112, 18, 0, 0 },
+ [ 30 ] = { 115, 14, 16, 16, 0, 0 },
+ [ 31 ] = { 107, 16, 112, 15, 0, 0 },
+ [ 32 ] = { 89, 15, 112, 17, 0, 0 },
+ [ 33 ] = { 198, 7, 237, 231, 0, 0 },
+ [ 34 ] = { 68, 80, 88, 92, 0, 0 },
+ [ 35 ] = { 16, 200, 97, 19, 0, 0 },
+ [ 36 ] = { 57, 351, 266, 112, 0, 0 },
+ [ 37 ] = { 325, 321, 208, 220, 0, 0 },
+ [ 38 ] = { 205, 214, 106, 107, 0, 0 },
+ [ 39 ] = { 113, 110, 108, 1, 0, 0 },
+ [ 40 ] = { 108, 106, 121, 112, 0, 0 },
+ [ 41 ] = { 356, 307, 9, 11, 0, 0 },
+ [ 42 ] = { 12, 11, 11, 12, 0, 0 },
+ [ 43 ] = { 102, 100, 52, 112, 0, 0 },
+ [ 44 ] = { 25, 30, 195, 196, 0, 0 },
+ [ 45 ] = { 18, 228, 322, 318, 0, 0 },
+ [ 46 ] = { 30, 120, 196, 195, 0, 0 },
+ [ 47 ] = { 34, 33, 33, 34, 0, 0 },
+ [ 48 ] = { 32, 31, 31, 32, 0, 0 },
+ [ 49 ] = { 33, 30, 16, 21, 0, 0 },
+ [ 50 ] = { 201, 323, 195, 318, 0, 0 },
+ [ 51 ] = { 21, 23, 51, 112, 0, 0 },
+ [ 52 ] = { 21, 23, 19, 24, 0, 0 },
+ [ 53 ] = { 19, 21, 18, 22, 0, 0 },
+ [ 54 ] = { 22, 22, 22, 23, 0, 0 },
+ [ 55 ] = { 121, 116, 118, 117, 0, 0 },
+ [ 56 ] = { 118, 119, 112, 1, 0, 0 },
+ [ 57 ] = { 119, 117, 115, 115, 0, 0 },
+ [ 58 ] = { 122, 118, 117, 116, 0, 0 },
+ [ 59 ] = { 305, 303, 299, 300, 0, 0 },
+ [ 60 ] = { 308, 304, 303, 301, 0, 0 },
+ [ 61 ] = { 304, 305, 300, 302, 0, 0 },
+ [ 62 ] = { 307, 102, 103, 26, 0, 0 },
+ [ 63 ] = { 130, 130, 127, 127, 0, 0 },
+ [ 64 ] = { 134, 134, 131, 131, 0, 0 },
+ [ 65 ] = { 138, 140, 135, 137, 0, 0 },
+ [ 66 ] = { 146, 146, 143, 143, 0, 0 },
+ [ 67 ] = { 150, 150, 147, 147, 0, 0 },
+ [ 68 ] = { 154, 156, 151, 153, 0, 0 },
+ [ 69 ] = { 162, 162, 159, 159, 0, 0 },
+ [ 70 ] = { 166, 166, 163, 163, 0, 0 },
+ [ 71 ] = { 170, 172, 167, 169, 0, 0 },
+ [ 72 ] = { 180, 113, 175, 177, 0, 0 },
+ [ 73 ] = { 115, 184, 182, 184, 0, 0 },
+ [ 74 ] = { 115, 191, 189, 191, 0, 0 },
+ [ 75 ] = { 129, 138, 124, 135, 0, 0 },
+ [ 76 ] = { 145, 154, 140, 151, 0, 0 },
+ [ 77 ] = { 161, 170, 156, 167, 0, 0 },
+ [ 78 ] = { 177, 181, 179, 185, 0, 0 },
+ [ 79 ] = { 181, 185, 174, 180, 0, 0 },
+ [ 80 ] = { 191, 192, 193, 187, 0, 0 },
+ [ 81 ] = { 87, 84, 84, 87, 0, 0 },
+ [ 82 ] = { 85, 86, 85, 88, 0, 0 },
+ [ 83 ] = { 86, 87, 61, 77, 0, 0 },
+ [ 84 ] = { 90, 88, 112, 230, 0, 0 },
+ [ 85 ] = { 67, 79, 60, 76, 0, 0 },
+ [ 86 ] = { 59, 72, 63, 79, 0, 0 },
+ [ 87 ] = { 60, 73, 65, 80, 0, 0 },
+ [ 88 ] = { 70, 82, 112, 66, 0, 0 },
+ [ 89 ] = { 69, 81, 207, 219, 0, 0 },
+ [ 90 ] = { 63, 76, 112, 80, 0, 0 },
+ [ 91 ] = { 58, 71, 61, 112, 0, 0 },
+ [ 92 ] = { 71, 83, 207, 112, 0, 0 },
+ [ 93 ] = { 96, 93, 90, 95, 0, 0 },
+ [ 94 ] = { 281, 283, 93, 93, 0, 0 },
+ [ 95 ] = { 4, 4, 91, 96, 0, 0 },
+ [ 96 ] = { 337, 335, 334, 331, 0, 0 },
+ [ 97 ] = { 336, 334, 336, 333, 0, 0 },
+ [ 98 ] = { 335, 333, 338, 335, 0, 0 },
+ [ 99 ] = { 334, 107, 340, 112, 0, 0 },
+ [ 100 ] = { 333, 327, 112, 322, 0, 0 },
+ [ 101 ] = { 321, 113, 345, 342, 0, 0 },
+ [ 102 ] = { 115, 0, 341, 338, 0, 0 },
+ [ 103 ] = { 115, 20, 343, 340, 0, 0 },
+ [ 104 ] = { 37, 38, 37, 41, 0, 0 },
+ [ 105 ] = { 45, 41, 45, 52, 0, 0 },
+ [ 106 ] = { 47, 48, 47, 51, 0, 0 },
+ [ 107 ] = { 43, 40, 34, 45, 0, 0 },
+ [ 108 ] = { 317, 308, 315, 305, 0, 0 },
+ [ 109 ] = { 318, 315, 312, 112, 0, 0 },
+ [ 110 ] = { 323, 252, 317, 249, 0, 0 },
+ [ 111 ] = { 315, 353, 309, 306, 0, 0 },
+ [ 112 ] = { 261, 263, 249, 36, 0, 0 },
+ [ 113 ] = { 260, 261, 258, 37, 0, 0 },
+ [ 114 ] = { 268, 264, 262, 260, 0, 0 },
+ [ 115 ] = { 256, 257, 254, 251, 0, 0 },
+ [ 116 ] = { 281, 284, 348, 293, 0, 0 },
+ [ 117 ] = { 281, 300, 278, 278, 0, 0 },
+ [ 118 ] = { 282, 268, 279, 279, 0, 0 },
+ [ 119 ] = { 269, 272, 264, 264, 0, 0 },
+ [ 120 ] = { 270, 270, 112, 88, 0, 0 },
+ [ 121 ] = { 272, 276, 268, 267, 0, 0 },
+ [ 122 ] = { 275, 271, 265, 272, 0, 0 },
+ [ 123 ] = { 273, 274, 270, 270, 0, 0 },
+ [ 124 ] = { 271, 271, 112, 266, 0, 0 },
+ [ 125 ] = { 274, 275, 269, 269, 0, 0 },
+ [ 126 ] = { 280, 282, 275, 277, 0, 0 },
+ [ 127 ] = { 278, 280, 273, 275, 0, 0 },
+ [ 128 ] = { 279, 279, 271, 21, 0, 0 },
+ [ 129 ] = { 280, 113, 275, 273, 0, 0 },
+ [ 130 ] = { 285, 113, 294, 263, 0, 0 },
+ [ 131 ] = { 299, 300, 291, 295, 0, 0 },
+ [ 132 ] = { 298, 299, 276, 280, 0, 0 },
+ [ 133 ] = { 18, 116, 322, 196, 0, 0 },
+ [ 134 ] = { 21, 23, 322, 196, 0, 0 },
+ [ 135 ] = { 124, 30, 322, 196, 0, 0 },
+ [ 136 ] = { 21, 23, 195, 318, 0, 0 },
+ [ 137 ] = { 17, 110, 122, 171, 0, 0 },
+ [ 138 ] = { 12, 11, 11, 9, 0, 0 },
+ [ 139 ] = { 70, 82, 61, 66, 0, 0 },
+ [ 140 ] = { 63, 76, 65, 80, 0, 0 },
+ [ 141 ] = { 58, 71, 61, 77, 0, 0 },
+ [ 142 ] = { 85, 84, 322, 196, 0, 0 },
+ [ 143 ] = { 90, 88, 61, 77, 0, 0 },
+ [ 144 ] = { 87, 86, 85, 88, 0, 0 },
+ [ 145 ] = { 85, 84, 87, 88, 0, 0 },
+ [ 146 ] = { 17, 94, 16, 88, 0, 0 },
+ [ 147 ] = { 303, 88, 113, 230, 0, 0 },
+ [ 148 ] = { 17, 114, 195, 318, 0, 0 },
+ [ 149 ] = { 356, 20, 322, 196, 0, 0 },
+ [ 150 ] = { 87, 84, 86, 86, 0, 0 },
+ [ 151 ] = { 303, 20, 195, 26, 0, 0 },
+ [ 152 ] = { 303, 323, 113, 196, 0, 0 },
+ [ 153 ] = { 17, 84, 87, 88, 0, 0 },
+ [ 154 ] = { 17, 30, 195, 196, 0, 0 },
+ [ 155 ] = { 17, 302, 322, 318, 0, 0 },
+ [ 156 ] = { 303, 23, 16, 24, 0, 0 },
+ [ 157 ] = { 281, 302, 348, 293, 0, 0 },
+ [ 158 ] = { 281, 302, 278, 278, 0, 0 },
+ [ 159 ] = { 282, 302, 279, 279, 0, 0 },
+ [ 160 ] = { 269, 302, 264, 264, 0, 0 },
+ [ 161 ] = { 270, 302, 277, 88, 0, 0 },
+ [ 162 ] = { 303, 276, 268, 267, 0, 0 },
+ [ 163 ] = { 303, 271, 265, 272, 0, 0 },
+ [ 164 ] = { 273, 302, 270, 270, 0, 0 },
+ [ 165 ] = { 303, 271, 112, 266, 0, 0 },
+ [ 166 ] = { 303, 275, 269, 269, 0, 0 },
+ [ 167 ] = { 303, 280, 273, 275, 0, 0 },
+ [ 168 ] = { 303, 282, 275, 277, 0, 0 },
+ [ 169 ] = { 303, 280, 273, 275, 0, 0 },
+ [ 170 ] = { 280, 302, 275, 273, 0, 0 },
+ [ 171 ] = { 285, 302, 294, 263, 0, 0 },
+ [ 172 ] = { 299, 302, 291, 295, 0, 0 },
+ [ 173 ] = { 303, 299, 276, 280, 0, 0 },
+ [ 174 ] = { 303, 270, 267, 281, 0, 0 },
+ [ 175 ] = { 303, 274, 272, 271, 0, 0 },
+ [ 176 ] = { 278, 302, 274, 265, 0, 0 },
+ [ 177 ] = { 280, 302, 112, 286, 0, 0 },
+ [ 178 ] = { 278, 302, 288, 292, 0, 0 },
+ [ 179 ] = { 303, 272, 284, 288, 0, 0 },
+ [ 180 ] = { 303, 268, 282, 286, 0, 0 },
+ [ 181 ] = { 303, 292, 287, 297, 0, 0 },
+ [ 182 ] = { 303, 286, 281, 298, 0, 0 },
+ [ 183 ] = { 303, 268, 264, 268, 0, 0 },
+ [ 184 ] = { 303, 296, 290, 294, 0, 0 },
+ [ 185 ] = { 269, 302, 266, 296, 0, 0 },
+ [ 186 ] = { 303, 94, 276, 293, 0, 0 },
+ [ 187 ] = { 303, 283, 278, 278, 0, 0 }
+};
+
+static const pmg_power_group_t power5p_groups[] = {
[ 0 ] = {
.pmg_name = "pm_utilization",
.pmg_desc = "CPI and utilization data",
- .pmg_event_ids = { 312, 302, 113, 21, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[0],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000000a12121eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5349,7 +7480,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 1 ] = {
.pmg_name = "pm_completion",
.pmg_desc = "Completion and cycle counts",
- .pmg_event_ids = { 2, 95, 100, 21, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[1],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000002608261eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5357,7 +7488,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 2 ] = {
.pmg_name = "pm_group_dispatch",
.pmg_desc = "Group dispatch events",
- .pmg_event_ids = { 105, 104, 101, 113, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[2],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4000000ec6c8c212ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5365,7 +7496,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 3 ] = {
.pmg_name = "pm_clb1",
.pmg_desc = "CLB fullness",
- .pmg_event_ids = { 0, 2, 12, 267, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[3],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x015b000180848c4cULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5373,7 +7504,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 4 ] = {
.pmg_name = "pm_clb2",
.pmg_desc = "CLB fullness",
- .pmg_event_ids = { 6, 6, 292, 112, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[4],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x014300028a8ccc02ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5381,7 +7512,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 5 ] = {
.pmg_name = "pm_gct_empty",
.pmg_desc = "GCT empty reasons",
- .pmg_event_ids = { 98, 97, 95, 98, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[5],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4000000008380838ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5389,7 +7520,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 6 ] = {
.pmg_name = "pm_gct_usage",
.pmg_desc = "GCT Usage",
- .pmg_event_ids = { 99, 98, 96, 97, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[6],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000003e3e3e3eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5397,7 +7528,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 7 ] = {
.pmg_name = "pm_lsu1",
.pmg_desc = "LSU LRQ and LMQ events",
- .pmg_event_ids = { 242, 241, 234, 234, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[7],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x020f000fcecccccaULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5405,7 +7536,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 8 ] = {
.pmg_name = "pm_lsu2",
.pmg_desc = "LSU SRQ events",
- .pmg_event_ids = { 247, 246, 244, 240, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[8],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x400e000ececcca86ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5413,7 +7544,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 9 ] = {
.pmg_name = "pm_lsu3",
.pmg_desc = "LSU SRQ and LMQ events",
- .pmg_event_ids = { 238, 247, 236, 239, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[9],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x030f0004ea102a2aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5421,7 +7552,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 10 ] = {
.pmg_name = "pm_lsu4",
.pmg_desc = "LSU SRQ and LMQ events",
- .pmg_event_ids = { 237, 244, 236, 239, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[10],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x40030000eea62a2aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5429,7 +7560,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 11 ] = {
.pmg_name = "pm_prefetch1",
.pmg_desc = "Prefetch stream allocation",
- .pmg_event_ids = { 120, 115, 26, 29, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[11],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x8432000d36c884ceULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5437,7 +7568,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 12 ] = {
.pmg_name = "pm_prefetch2",
.pmg_desc = "Prefetch events",
- .pmg_event_ids = { 115, 13, 122, 108, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[12],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x8103000602cace8eULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5445,7 +7576,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 13 ] = {
.pmg_name = "pm_prefetch3",
.pmg_desc = "L2 prefetch and misc events",
- .pmg_event_ids = { 1, 227, 172, 112, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[13],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x047c000482108602ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5453,7 +7584,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 14 ] = {
.pmg_name = "pm_prefetch4",
.pmg_desc = "Misc prefetch and reject events",
- .pmg_event_ids = { 216, 225, 27, 171, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[14],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0cf200028088cc86ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5461,7 +7592,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 15 ] = {
.pmg_name = "pm_lsu_reject1",
.pmg_desc = "LSU reject events",
- .pmg_event_ids = { 244, 242, 53, 294, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[15],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xc8e000022010c610ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5469,7 +7600,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 16 ] = {
.pmg_name = "pm_lsu_reject2",
.pmg_desc = "LSU rejects due to reload CDF or tag update collision",
- .pmg_event_ids = { 215, 224, 112, 122, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[16],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x88c00001848c02ceULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5477,7 +7608,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 17 ] = {
.pmg_name = "LSU rejects due to ERAT",
.pmg_desc = " held instuctions",
- .pmg_event_ids = { 213, 222, 245, 344, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[17],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x48c00003868ec0c8ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5485,7 +7616,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 18 ] = {
.pmg_name = "pm_lsu_reject4",
.pmg_desc = "LSU0/1 reject LMQ full",
- .pmg_event_ids = { 214, 223, 112, 9, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[18],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x88c00001828a02c8ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5493,7 +7624,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 19 ] = {
.pmg_name = "pm_lsu_reject5",
.pmg_desc = "LSU misc reject and flush events",
- .pmg_event_ids = { 245, 243, 228, 53, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[19],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x48c0000010208a8eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5501,7 +7632,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 20 ] = {
.pmg_name = "pm_flush1",
.pmg_desc = "Misc flush events",
- .pmg_event_ids = { 115, 233, 53, 26, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[20],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xc0f000020210c68eULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5509,7 +7640,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 21 ] = {
.pmg_name = "pm_flush2",
.pmg_desc = "Flushes due to scoreboard and sync",
- .pmg_event_ids = { 124, 113, 54, 57, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[21],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xc08000038002c4c2ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5517,7 +7648,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 22 ] = {
.pmg_name = "pm_lsu_flush_srq_lrq",
.pmg_desc = "LSU flush by SRQ and LRQ events",
- .pmg_event_ids = { 233, 230, 112, 226, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[22],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x40c000002020028aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5525,7 +7656,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 23 ] = {
.pmg_name = "pm_lsu_flush_lrq",
.pmg_desc = "LSU0/1 flush due to LRQ",
- .pmg_event_ids = { 207, 216, 228, 112, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[23],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x40c00000848c8a02ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5533,7 +7664,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 24 ] = {
.pmg_name = "pm_lsu_flush_srq",
.pmg_desc = "LSU0/1 flush due to SRQ",
- .pmg_event_ids = { 208, 217, 112, 226, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[24],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x40c00000868e028aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5541,7 +7672,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 25 ] = {
.pmg_name = "pm_lsu_flush_unaligned",
.pmg_desc = "LSU flush due to unaligned data",
- .pmg_event_ids = { 235, 233, 8, 112, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[25],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x80c000021010c802ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5549,7 +7680,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 26 ] = {
.pmg_name = "pm_lsu_flush_uld",
.pmg_desc = "LSU0/1 flush due to unaligned load",
- .pmg_event_ids = { 209, 218, 228, 112, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[26],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x40c0000080888a02ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5557,7 +7688,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 27 ] = {
.pmg_name = "pm_lsu_flush_ust",
.pmg_desc = "LSU0/1 flush due to unaligned store",
- .pmg_event_ids = { 210, 219, 112, 226, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[27],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x40c00000828a028aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5565,7 +7696,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 28 ] = {
.pmg_name = "pm_lsu_flush_full",
.pmg_desc = "LSU flush due to LRQ/SRQ full",
- .pmg_event_ids = { 232, 113, 290, 229, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[28],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xc0200009ce0210c0ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5573,7 +7704,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 29 ] = {
.pmg_name = "pm_lsu_stall1",
.pmg_desc = "LSU Stalls",
- .pmg_event_ids = { 109, 17, 112, 18, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[29],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4000000028300234ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5581,7 +7712,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 30 ] = {
.pmg_name = "pm_lsu_stall2",
.pmg_desc = "LSU Stalls",
- .pmg_event_ids = { 115, 14, 16, 16, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[30],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4000000002341e36ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5589,7 +7720,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 31 ] = {
.pmg_name = "pm_fxu_stall",
.pmg_desc = "FXU Stalls",
- .pmg_event_ids = { 107, 16, 112, 15, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[31],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x40000008ca320232ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5597,7 +7728,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 32 ] = {
.pmg_name = "pm_fpu_stall",
.pmg_desc = "FPU Stalls",
- .pmg_event_ids = { 89, 15, 112, 17, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[32],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4000000020360230ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5605,7 +7736,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 33 ] = {
.pmg_name = "pm_queue_full",
.pmg_desc = "BRQ LRQ LMQ queue full",
- .pmg_event_ids = { 198, 7, 237, 231, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[33],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x400b0009ce8a84ceULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5613,7 +7744,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 34 ] = {
.pmg_name = "pm_issueq_full",
.pmg_desc = "FPU FX full",
- .pmg_event_ids = { 68, 80, 88, 92, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[34],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x40000000868e8088ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5621,7 +7752,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 35 ] = {
.pmg_name = "pm_mapper_full1",
.pmg_desc = "CR CTR GPR mapper full",
- .pmg_event_ids = { 16, 200, 97, 19, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[35],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x40000002888cca82ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5629,7 +7760,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 36 ] = {
.pmg_name = "pm_mapper_full2",
.pmg_desc = "FPR XER mapper full",
- .pmg_event_ids = { 57, 351, 266, 112, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[36],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4103000282843602ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5637,7 +7768,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 37 ] = {
.pmg_name = "pm_misc_load",
.pmg_desc = "Non-cachable loads and stcx events",
- .pmg_event_ids = { 325, 321, 208, 220, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[37],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0438000cc2ca828aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5645,7 +7776,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 38 ] = {
.pmg_name = "pm_ic_demand",
.pmg_desc = "ICache demand from BR redirect",
- .pmg_event_ids = { 205, 214, 106, 107, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[38],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x800c000fc2cac0c2ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5653,7 +7784,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 39 ] = {
.pmg_name = "pm_ic_pref",
.pmg_desc = "ICache prefetch",
- .pmg_event_ids = { 113, 110, 108, 1, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[39],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x8000000dcecc8e1aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5661,7 +7792,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 40 ] = {
.pmg_name = "pm_ic_miss",
.pmg_desc = "ICache misses",
- .pmg_event_ids = { 108, 106, 121, 112, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[40],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4003000e32cec802ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5669,7 +7800,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 41 ] = {
.pmg_name = "Branch mispredict",
.pmg_desc = " TLB and SLB misses",
- .pmg_event_ids = { 356, 307, 9, 11, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[41],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x808000031010caccULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5677,7 +7808,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 42 ] = {
.pmg_name = "pm_branch1",
.pmg_desc = "Branch operations",
- .pmg_event_ids = { 12, 11, 11, 12, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[42],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x8000000f0e0e0e0eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5685,7 +7816,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 43 ] = {
.pmg_name = "pm_branch2",
.pmg_desc = "Branch operations",
- .pmg_event_ids = { 102, 100, 52, 112, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[43],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4000000c22cc8c02ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5693,7 +7824,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 44 ] = {
.pmg_name = "pm_L1_tlbmiss",
.pmg_desc = "L1 load and TLB misses",
- .pmg_event_ids = { 25, 30, 195, 196, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[44],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00b000008e881020ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5701,7 +7832,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 45 ] = {
.pmg_name = "pm_L1_DERAT_miss",
.pmg_desc = "L1 store and DERAT misses",
- .pmg_event_ids = { 18, 228, 322, 318, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[45],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00b300080e202086ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5709,7 +7840,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 46 ] = {
.pmg_name = "pm_L1_slbmiss",
.pmg_desc = "L1 load and SLB misses",
- .pmg_event_ids = { 30, 120, 196, 195, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[46],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00b000008a82848cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5717,7 +7848,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 47 ] = {
.pmg_name = "pm_dtlbref",
.pmg_desc = "Data TLB references",
- .pmg_event_ids = { 34, 33, 33, 34, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[47],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000c000f0c0c0c0cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5725,7 +7856,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 48 ] = {
.pmg_name = "pm_dtlbmiss",
.pmg_desc = "Data TLB misses",
- .pmg_event_ids = { 32, 31, 31, 32, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[48],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000c000f1a1a1a1aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5733,7 +7864,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 49 ] = {
.pmg_name = "pm_dtlb",
.pmg_desc = "Data TLB references and misses",
- .pmg_event_ids = { 33, 30, 16, 21, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[49],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x008c0008c8881e1eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5741,7 +7872,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 50 ] = {
.pmg_name = "pm_L1_refmiss",
.pmg_desc = "L1 load references and misses and store references and misses",
- .pmg_event_ids = { 201, 323, 195, 318, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[50],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0030000050501086ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5749,7 +7880,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 51 ] = {
.pmg_name = "pm_dsource1",
.pmg_desc = "L3 cache and memory data access",
- .pmg_event_ids = { 21, 23, 51, 112, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[51],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4003000c1c0e8e02ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5757,7 +7888,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 52 ] = {
.pmg_name = "pm_dsource2",
.pmg_desc = "L3 cache and memory data access",
- .pmg_event_ids = { 21, 23, 19, 24, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[52],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0003000f1c0e360eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5765,7 +7896,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 53 ] = {
.pmg_name = "pm_dsource_L2",
.pmg_desc = "L2 cache data access",
- .pmg_event_ids = { 19, 21, 18, 22, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[53],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0003000f2e2e2e2eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5773,7 +7904,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 54 ] = {
.pmg_name = "pm_dsource_L3",
.pmg_desc = "L3 cache data access",
- .pmg_event_ids = { 22, 22, 22, 23, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[54],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0003000f3c3c3c3cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5781,7 +7912,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 55 ] = {
.pmg_name = "pm_isource1",
.pmg_desc = "Instruction source information",
- .pmg_event_ids = { 121, 116, 118, 117, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[55],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x8000000f1a1a1a0cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5789,7 +7920,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 56 ] = {
.pmg_name = "pm_isource2",
.pmg_desc = "Instruction source information",
- .pmg_event_ids = { 118, 119, 112, 1, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[56],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x8000000d0c0c021aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5797,7 +7928,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 57 ] = {
.pmg_name = "pm_isource_L2",
.pmg_desc = "L2 instruction source information",
- .pmg_event_ids = { 119, 117, 115, 115, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[57],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x8000000f2c2c2c2cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5805,7 +7936,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 58 ] = {
.pmg_name = "pm_isource_L3",
.pmg_desc = "L3 instruction source information",
- .pmg_event_ids = { 122, 118, 117, 116, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[58],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x8000000f3a3a3a3aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5813,7 +7944,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 59 ] = {
.pmg_name = "pm_pteg_source1",
.pmg_desc = "PTEG source information",
- .pmg_event_ids = { 305, 303, 299, 300, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[59],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0002000f2e2e2e2eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5821,7 +7952,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 60 ] = {
.pmg_name = "pm_pteg_source2",
.pmg_desc = "PTEG source information",
- .pmg_event_ids = { 308, 304, 303, 301, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[60],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0002000f3c3c3c3cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5829,7 +7960,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 61 ] = {
.pmg_name = "pm_pteg_source3",
.pmg_desc = "PTEG source information",
- .pmg_event_ids = { 304, 305, 300, 302, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[61],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0002000f0e0e360eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5837,7 +7968,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 62 ] = {
.pmg_name = "pm_pteg_source4",
.pmg_desc = "L3 PTEG and group disptach events",
- .pmg_event_ids = { 307, 102, 103, 26, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[62],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x003200081c04048eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5845,7 +7976,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 63 ] = {
.pmg_name = "pm_L2SA_ld",
.pmg_desc = "L2 slice A load events",
- .pmg_event_ids = { 130, 130, 127, 127, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[63],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055400580c080c0ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5853,7 +7984,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 64 ] = {
.pmg_name = "pm_L2SA_st",
.pmg_desc = "L2 slice A store events",
- .pmg_event_ids = { 134, 134, 131, 131, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[64],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055800580c080c0ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5861,7 +7992,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 65 ] = {
.pmg_name = "pm_L2SA_st2",
.pmg_desc = "L2 slice A store events",
- .pmg_event_ids = { 138, 140, 135, 137, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[65],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055c00580c080c0ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5869,7 +8000,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 66 ] = {
.pmg_name = "pm_L2SB_ld",
.pmg_desc = "L2 slice B load events",
- .pmg_event_ids = { 146, 146, 143, 143, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[66],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055400582c282c2ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5877,7 +8008,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 67 ] = {
.pmg_name = "pm_L2SB_st",
.pmg_desc = "L2 slice B store events",
- .pmg_event_ids = { 150, 150, 147, 147, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[67],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055800582c482c2ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5885,7 +8016,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 68 ] = {
.pmg_name = "pm_L2SB_st2",
.pmg_desc = "L2 slice B store events",
- .pmg_event_ids = { 154, 156, 151, 153, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[68],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055c00582c282c2ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5893,7 +8024,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 69 ] = {
.pmg_name = "pm_L2SC_ld",
.pmg_desc = "L2 slice C load events",
- .pmg_event_ids = { 162, 162, 159, 159, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[69],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055400584c484c4ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5901,7 +8032,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 70 ] = {
.pmg_name = "pm_L2SC_st",
.pmg_desc = "L2 slice C store events",
- .pmg_event_ids = { 166, 166, 163, 163, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[70],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055800584c284c4ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5909,7 +8040,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 71 ] = {
.pmg_name = "pm_L2SC_st2",
.pmg_desc = "L2 slice C store events",
- .pmg_event_ids = { 170, 172, 167, 169, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[71],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055c00584c484c4ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5917,7 +8048,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 72 ] = {
.pmg_name = "pm_L3SA_trans",
.pmg_desc = "L3 slice A state transistions",
- .pmg_event_ids = { 180, 113, 175, 177, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[72],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3015000ac602c686ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5925,7 +8056,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 73 ] = {
.pmg_name = "pm_L3SB_trans",
.pmg_desc = "L3 slice B state transistions",
- .pmg_event_ids = { 115, 184, 182, 184, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[73],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3015000602c8c888ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5933,7 +8064,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 74 ] = {
.pmg_name = "pm_L3SC_trans",
.pmg_desc = "L3 slice C state transistions",
- .pmg_event_ids = { 115, 191, 189, 191, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[74],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3015000602caca8aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5941,7 +8072,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 75 ] = {
.pmg_name = "pm_L2SA_trans",
.pmg_desc = "L2 slice A state transistions",
- .pmg_event_ids = { 129, 138, 124, 135, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[75],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055000ac080c080ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5949,7 +8080,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 76 ] = {
.pmg_name = "pm_L2SB_trans",
.pmg_desc = "L2 slice B state transistions",
- .pmg_event_ids = { 145, 154, 140, 151, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[76],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055000ac282c282ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5957,7 +8088,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 77 ] = {
.pmg_name = "pm_L2SC_trans",
.pmg_desc = "L2 slice C state transistions",
- .pmg_event_ids = { 161, 170, 156, 167, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[77],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055000ac484c484ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5965,7 +8096,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 78 ] = {
.pmg_name = "pm_L3SAB_retry",
.pmg_desc = "L3 slice A/B snoop retry and all CI/CO busy",
- .pmg_event_ids = { 177, 181, 179, 185, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[78],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3005100fc6c8c6c8ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5973,7 +8104,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 79 ] = {
.pmg_name = "pm_L3SAB_hit",
.pmg_desc = "L3 slice A/B hit and reference",
- .pmg_event_ids = { 181, 185, 174, 180, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[79],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3050100086888688ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5981,7 +8112,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 80 ] = {
.pmg_name = "pm_L3SC_retry_hit",
.pmg_desc = "L3 slice C hit & snoop retry",
- .pmg_event_ids = { 191, 192, 193, 187, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[80],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055100aca8aca8aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5989,7 +8120,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 81 ] = {
.pmg_name = "pm_fpu1",
.pmg_desc = "Floating Point events",
- .pmg_event_ids = { 87, 84, 84, 87, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[81],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000010101020ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5997,7 +8128,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 82 ] = {
.pmg_name = "pm_fpu2",
.pmg_desc = "Floating Point events",
- .pmg_event_ids = { 85, 86, 85, 88, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[82],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000020202010ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6005,7 +8136,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 83 ] = {
.pmg_name = "pm_fpu3",
.pmg_desc = "Floating point events",
- .pmg_event_ids = { 86, 87, 61, 77, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[83],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000c1010868eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6013,7 +8144,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 84 ] = {
.pmg_name = "pm_fpu4",
.pmg_desc = "Floating point events",
- .pmg_event_ids = { 90, 88, 112, 230, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[84],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0430000c20200220ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6021,7 +8152,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 85 ] = {
.pmg_name = "pm_fpu5",
.pmg_desc = "Floating point events by unit",
- .pmg_event_ids = { 67, 79, 60, 76, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[85],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00000000848c848cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6029,7 +8160,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 86 ] = {
.pmg_name = "pm_fpu6",
.pmg_desc = "Floating point events by unit",
- .pmg_event_ids = { 59, 72, 63, 79, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[86],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000cc0c88088ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6037,7 +8168,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 87 ] = {
.pmg_name = "pm_fpu7",
.pmg_desc = "Floating point events by unit",
- .pmg_event_ids = { 60, 73, 65, 80, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[87],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000008088828aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6045,7 +8176,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 88 ] = {
.pmg_name = "pm_fpu8",
.pmg_desc = "Floating point events by unit",
- .pmg_event_ids = { 70, 82, 112, 66, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[88],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000dc2ca02c0ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6053,7 +8184,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 89 ] = {
.pmg_name = "pm_fpu9",
.pmg_desc = "Floating point events by unit",
- .pmg_event_ids = { 69, 81, 207, 219, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[89],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0430000cc6ce8088ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6061,7 +8192,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 90 ] = {
.pmg_name = "pm_fpu10",
.pmg_desc = "Floating point events by unit",
- .pmg_event_ids = { 63, 76, 112, 80, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[90],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00000000828a028aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6069,7 +8200,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 91 ] = {
.pmg_name = "pm_fpu11",
.pmg_desc = "Floating point events by unit",
- .pmg_event_ids = { 58, 71, 61, 112, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[91],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00000000868e8602ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6077,7 +8208,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 92 ] = {
.pmg_name = "pm_fpu12",
.pmg_desc = "Floating point events by unit",
- .pmg_event_ids = { 71, 83, 207, 112, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[92],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0430000cc4cc8002ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6085,7 +8216,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 93 ] = {
.pmg_name = "pm_fxu1",
.pmg_desc = "Fixed Point events",
- .pmg_event_ids = { 96, 93, 90, 95, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[93],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000024242424ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6093,7 +8224,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 94 ] = {
.pmg_name = "pm_fxu2",
.pmg_desc = "Fixed Point events",
- .pmg_event_ids = { 281, 283, 93, 93, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[94],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4000000604221020ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6101,7 +8232,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 95 ] = {
.pmg_name = "pm_fxu3",
.pmg_desc = "Fixed Point events",
- .pmg_event_ids = { 4, 4, 91, 96, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[95],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x404000038688c4ccULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6109,7 +8240,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 96 ] = {
.pmg_name = "pm_smt_priorities1",
.pmg_desc = "Thread priority events",
- .pmg_event_ids = { 337, 335, 334, 331, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[96],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0005000fc6ccc6c8ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6117,7 +8248,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 97 ] = {
.pmg_name = "pm_smt_priorities2",
.pmg_desc = "Thread priority events",
- .pmg_event_ids = { 336, 334, 336, 333, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[97],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0005000fc4cacaccULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6125,7 +8256,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 98 ] = {
.pmg_name = "pm_smt_priorities3",
.pmg_desc = "Thread priority events",
- .pmg_event_ids = { 335, 333, 338, 335, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[98],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0005000fc2c8c4c2ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6133,7 +8264,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 99 ] = {
.pmg_name = "pm_smt_priorities4",
.pmg_desc = "Thread priority events",
- .pmg_event_ids = { 334, 107, 340, 112, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[99],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0005000ac016c002ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6141,7 +8272,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 100 ] = {
.pmg_name = "pm_smt_both",
.pmg_desc = "Thread common events",
- .pmg_event_ids = { 333, 327, 112, 322, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[100],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0010000016260208ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6149,7 +8280,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 101 ] = {
.pmg_name = "pm_smt_selection",
.pmg_desc = "Thread selection",
- .pmg_event_ids = { 321, 113, 345, 342, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[101],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0090000086028082ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6157,7 +8288,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 102 ] = {
.pmg_name = "pm_smt_selectover1",
.pmg_desc = "Thread selection overide",
- .pmg_event_ids = { 115, 0, 341, 338, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[102],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0050000002808488ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6165,7 +8296,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 103 ] = {
.pmg_name = "pm_smt_selectover2",
.pmg_desc = "Thread selection overide",
- .pmg_event_ids = { 115, 20, 343, 340, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[103],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00100000021e8a86ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6173,7 +8304,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 104 ] = {
.pmg_name = "pm_fabric1",
.pmg_desc = "Fabric events",
- .pmg_event_ids = { 37, 38, 37, 41, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[104],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x305500058ece8eceULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6181,7 +8312,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 105 ] = {
.pmg_name = "pm_fabric2",
.pmg_desc = "Fabric data movement",
- .pmg_event_ids = { 45, 41, 45, 52, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[105],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x305500858ece8eceULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6189,7 +8320,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 106 ] = {
.pmg_name = "pm_fabric3",
.pmg_desc = "Fabric data movement",
- .pmg_event_ids = { 47, 48, 47, 51, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[106],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x305501858ece8eceULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6197,7 +8328,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 107 ] = {
.pmg_name = "pm_fabric4",
.pmg_desc = "Fabric data movement",
- .pmg_event_ids = { 43, 40, 34, 45, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[107],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x705401068ecec68eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6205,7 +8336,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 108 ] = {
.pmg_name = "pm_snoop1",
.pmg_desc = "Snoop retry",
- .pmg_event_ids = { 317, 308, 315, 305, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[108],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x305500058ccc8cccULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6213,7 +8344,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 109 ] = {
.pmg_name = "pm_snoop2",
.pmg_desc = "Snoop read retry",
- .pmg_event_ids = { 318, 315, 312, 112, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[109],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x30540a048ccc8c02ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6221,7 +8352,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 110 ] = {
.pmg_name = "pm_snoop3",
.pmg_desc = "Snoop write retry",
- .pmg_event_ids = { 323, 252, 317, 249, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[110],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x30550c058ccc8cccULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6229,7 +8360,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 111 ] = {
.pmg_name = "pm_snoop4",
.pmg_desc = "Snoop partial write retry",
- .pmg_event_ids = { 315, 353, 309, 306, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[111],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x30540e048ccc8cacULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6237,7 +8368,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 112 ] = {
.pmg_name = "pm_mem_rq",
.pmg_desc = "Memory read queue dispatch",
- .pmg_event_ids = { 261, 263, 249, 36, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[112],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x705402058ccc8cceULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6245,7 +8376,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 113 ] = {
.pmg_name = "pm_mem_read",
.pmg_desc = "Memory read complete and cancel",
- .pmg_event_ids = { 260, 261, 258, 37, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[113],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x305404048ccc8c06ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6253,7 +8384,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 114 ] = {
.pmg_name = "pm_mem_wq",
.pmg_desc = "Memory write queue dispatch",
- .pmg_event_ids = { 268, 264, 262, 260, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[114],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x305506058ccc8cccULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6261,7 +8392,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 115 ] = {
.pmg_name = "pm_mem_pwq",
.pmg_desc = "Memory partial write queue",
- .pmg_event_ids = { 256, 257, 254, 251, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[115],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x305508058ccc8cccULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6269,7 +8400,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 116 ] = {
.pmg_name = "pm_threshold",
.pmg_desc = "Thresholding",
- .pmg_event_ids = { 281, 284, 348, 293, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[116],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0008000404c41628ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6277,7 +8408,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 117 ] = {
.pmg_name = "pm_mrk_grp1",
.pmg_desc = "Marked group events",
- .pmg_event_ids = { 281, 300, 278, 278, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[117],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0008000404c60a26ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6285,7 +8416,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 118 ] = {
.pmg_name = "pm_mrk_grp2",
.pmg_desc = "Marked group events",
- .pmg_event_ids = { 282, 268, 279, 279, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[118],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x410300032a0ac822ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6293,7 +8424,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 119 ] = {
.pmg_name = "pm_mrk_dsource1",
.pmg_desc = "Marked data from",
- .pmg_event_ids = { 269, 272, 264, 264, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[119],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010b000f0e404444ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6301,7 +8432,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 120 ] = {
.pmg_name = "pm_mrk_dsource2",
.pmg_desc = "Marked data from",
- .pmg_event_ids = { 270, 270, 112, 88, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[120],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010b000c2e440210ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6309,7 +8440,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 121 ] = {
.pmg_name = "pm_mrk_dsource3",
.pmg_desc = "Marked data from",
- .pmg_event_ids = { 272, 276, 268, 267, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[121],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010b000f1c484c4cULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6317,7 +8448,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 122 ] = {
.pmg_name = "pm_mrk_dsource4",
.pmg_desc = "Marked data from",
- .pmg_event_ids = { 275, 271, 265, 272, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[122],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010b000f42462e42ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6325,7 +8456,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 123 ] = {
.pmg_name = "pm_mrk_dsource5",
.pmg_desc = "Marked data from",
- .pmg_event_ids = { 273, 274, 270, 270, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[123],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010b000f3c4c4040ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6333,7 +8464,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 124 ] = {
.pmg_name = "pm_mrk_dsource6",
.pmg_desc = "Marked data from",
- .pmg_event_ids = { 271, 271, 112, 266, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[124],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010b000d46460246ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6341,7 +8472,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 125 ] = {
.pmg_name = "pm_mrk_dsource7",
.pmg_desc = "Marked data from",
- .pmg_event_ids = { 274, 275, 269, 269, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[125],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010b000f4e4e3c4eULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6349,7 +8480,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 126 ] = {
.pmg_name = "pm_mrk_dtlbref",
.pmg_desc = "Marked data TLB references",
- .pmg_event_ids = { 280, 282, 275, 277, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[126],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x020c000f0c0c0c0cULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6357,7 +8488,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 127 ] = {
.pmg_name = "pm_mrk_dtlbmiss",
.pmg_desc = "Marked data TLB misses",
- .pmg_event_ids = { 278, 280, 273, 275, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[127],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x020c000f1a1a1a1aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6365,7 +8496,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 128 ] = {
.pmg_name = "pm_mrk_dtlb_dslb",
.pmg_desc = "Marked data TLB references and misses and marked data SLB misses",
- .pmg_event_ids = { 279, 279, 271, 21, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[128],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x063c0008c8ac8e1eULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6373,7 +8504,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 129 ] = {
.pmg_name = "pm_mrk_lbref",
.pmg_desc = "Marked TLB and SLB references",
- .pmg_event_ids = { 280, 113, 275, 273, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[129],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x063c000a0c020c8eULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6381,7 +8512,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 130 ] = {
.pmg_name = "pm_mrk_lsmiss",
.pmg_desc = "Marked load and store miss",
- .pmg_event_ids = { 285, 113, 294, 263, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[130],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000800081002060aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6389,7 +8520,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 131 ] = {
.pmg_name = "pm_mrk_ulsflush",
.pmg_desc = "Mark unaligned load and store flushes",
- .pmg_event_ids = { 299, 300, 291, 295, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[131],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0028000406c62020ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6397,7 +8528,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 132 ] = {
.pmg_name = "pm_mrk_misc",
.pmg_desc = "Misc marked instructions",
- .pmg_event_ids = { 298, 299, 276, 280, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[132],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00080008cc062816ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6405,7 +8536,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 133 ] = {
.pmg_name = "pm_lsref_L1",
.pmg_desc = "Load/Store operations and L1 activity",
- .pmg_event_ids = { 18, 116, 322, 196, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[133],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x8033000c0e1a2020ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6413,7 +8544,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 134 ] = {
.pmg_name = "Load/Store operations and L2",
.pmg_desc = " L3 activity",
- .pmg_event_ids = { 21, 23, 322, 196, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[134],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0033000c1c0e2020ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6421,7 +8552,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 135 ] = {
.pmg_name = "pm_lsref_tlbmiss",
.pmg_desc = "Load/Store operations and TLB misses",
- .pmg_event_ids = { 124, 30, 322, 196, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[135],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00b0000080882020ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6429,7 +8560,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 136 ] = {
.pmg_name = "pm_Dmiss",
.pmg_desc = "Data cache misses",
- .pmg_event_ids = { 21, 23, 195, 318, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[136],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0033000c1c0e1086ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6437,7 +8568,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 137 ] = {
.pmg_name = "pm_prefetchX",
.pmg_desc = "Prefetch events",
- .pmg_event_ids = { 17, 110, 122, 171, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[137],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x853300061eccce86ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6445,7 +8576,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 138 ] = {
.pmg_name = "pm_branchX",
.pmg_desc = "Branch operations",
- .pmg_event_ids = { 12, 11, 11, 9, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[138],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x8000000f0e0e0ec8ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6453,7 +8584,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 139 ] = {
.pmg_name = "pm_fpuX1",
.pmg_desc = "Floating point events by unit",
- .pmg_event_ids = { 70, 82, 61, 66, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[139],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000dc2ca86c0ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6461,7 +8592,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 140 ] = {
.pmg_name = "pm_fpuX2",
.pmg_desc = "Floating point events by unit",
- .pmg_event_ids = { 63, 76, 65, 80, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[140],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00000000828a828aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6469,7 +8600,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 141 ] = {
.pmg_name = "pm_fpuX3",
.pmg_desc = "Floating point events by unit",
- .pmg_event_ids = { 58, 71, 61, 77, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[141],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00000000868e868eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6477,7 +8608,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 142 ] = {
.pmg_name = "pm_fpuX4",
.pmg_desc = "Floating point and L1 events",
- .pmg_event_ids = { 85, 84, 322, 196, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[142],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0030000020102020ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6485,7 +8616,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 143 ] = {
.pmg_name = "pm_fpuX5",
.pmg_desc = "Floating point events",
- .pmg_event_ids = { 90, 88, 61, 77, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[143],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000c2020868eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6493,7 +8624,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 144 ] = {
.pmg_name = "pm_fpuX6",
.pmg_desc = "Floating point events",
- .pmg_event_ids = { 87, 86, 85, 88, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[144],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000010202010ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6501,7 +8632,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 145 ] = {
.pmg_name = "pm_fpuX7",
.pmg_desc = "Floating point events",
- .pmg_event_ids = { 85, 84, 87, 88, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[145],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000220105010ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6509,7 +8640,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 146 ] = {
.pmg_name = "pm_hpmcount8",
.pmg_desc = "HPM group for set 9",
- .pmg_event_ids = { 17, 94, 16, 88, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[146],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000001e281e10ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6517,7 +8648,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 147 ] = {
.pmg_name = "pm_hpmcount2",
.pmg_desc = "HPM group for set 2",
- .pmg_event_ids = { 303, 88, 113, 230, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[147],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0430000412201220ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6525,7 +8656,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 148 ] = {
.pmg_name = "pm_hpmcount3",
.pmg_desc = "HPM group for set 3",
- .pmg_event_ids = { 17, 114, 195, 318, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[148],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x403000041ec21086ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6533,7 +8664,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 149 ] = {
.pmg_name = "pm_hpmcount4",
.pmg_desc = "HPM group for set 7",
- .pmg_event_ids = { 356, 20, 322, 196, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[149],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00b00000101e2020ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6541,7 +8672,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 150 ] = {
.pmg_name = "pm_flop",
.pmg_desc = "Floating point operations",
- .pmg_event_ids = { 87, 84, 86, 86, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[150],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000010105050ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6549,7 +8680,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 151 ] = {
.pmg_name = "pm_eprof1",
.pmg_desc = "Group for use with eprof",
- .pmg_event_ids = { 303, 20, 195, 26, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[151],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00300000121e108eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6557,7 +8688,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 152 ] = {
.pmg_name = "pm_eprof2",
.pmg_desc = "Group for use with eprof",
- .pmg_event_ids = { 303, 323, 113, 196, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[152],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0030000012501220ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6565,7 +8696,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 153 ] = {
.pmg_name = "pm_flip",
.pmg_desc = "Group for flips",
- .pmg_event_ids = { 17, 84, 87, 88, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[153],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000021e105010ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6573,7 +8704,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 154 ] = {
.pmg_name = "pm_hpmcount5",
.pmg_desc = "HPM group for set 5",
- .pmg_event_ids = { 17, 30, 195, 196, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[154],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00b000001e881020ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6581,7 +8712,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 155 ] = {
.pmg_name = "pm_hpmcount6",
.pmg_desc = "HPM group for set 6",
- .pmg_event_ids = { 17, 302, 322, 318, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[155],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x003000001e122086ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6589,7 +8720,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 156 ] = {
.pmg_name = "pm_hpmcount7",
.pmg_desc = "HPM group for set 8",
- .pmg_event_ids = { 303, 23, 16, 24, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[156],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00030005120e1e0eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6597,7 +8728,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 157 ] = {
.pmg_name = "pm_ep_threshold",
.pmg_desc = "Thresholding",
- .pmg_event_ids = { 281, 302, 348, 293, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[157],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000004121628ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6605,7 +8736,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 158 ] = {
.pmg_name = "pm_ep_mrk_grp1",
.pmg_desc = "Marked group events",
- .pmg_event_ids = { 281, 302, 278, 278, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[158],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000004120a26ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6613,7 +8744,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 159 ] = {
.pmg_name = "pm_ep_mrk_grp2",
.pmg_desc = "Marked group events",
- .pmg_event_ids = { 282, 302, 279, 279, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[159],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x410300032a12c822ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6621,7 +8752,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 160 ] = {
.pmg_name = "pm_ep_mrk_dsource1",
.pmg_desc = "Marked data from",
- .pmg_event_ids = { 269, 302, 264, 264, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[160],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010b000b0e124444ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6629,7 +8760,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 161 ] = {
.pmg_name = "pm_ep_mrk_dsource2",
.pmg_desc = "Marked data from",
- .pmg_event_ids = { 270, 302, 277, 88, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[161],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010b00082e12e410ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6637,7 +8768,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 162 ] = {
.pmg_name = "pm_ep_mrk_dsource3",
.pmg_desc = "Marked data from",
- .pmg_event_ids = { 303, 276, 268, 267, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[162],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010b000712484c4cULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6645,7 +8776,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 163 ] = {
.pmg_name = "pm_ep_mrk_dsource4",
.pmg_desc = "Marked data from",
- .pmg_event_ids = { 303, 271, 265, 272, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[163],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010b000712462e42ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6653,7 +8784,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 164 ] = {
.pmg_name = "pm_ep_mrk_dsource5",
.pmg_desc = "Marked data from",
- .pmg_event_ids = { 273, 302, 270, 270, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[164],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010b000b3c124040ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6661,7 +8792,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 165 ] = {
.pmg_name = "pm_ep_mrk_dsource6",
.pmg_desc = "Marked data from",
- .pmg_event_ids = { 303, 271, 112, 266, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[165],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010b000512460246ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6669,7 +8800,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 166 ] = {
.pmg_name = "pm_ep_mrk_dsource7",
.pmg_desc = "Marked data from",
- .pmg_event_ids = { 303, 275, 269, 269, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[166],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010b0007124e3c4eULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6677,7 +8808,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 167 ] = {
.pmg_name = "pm_ep_mrk_lbmiss",
.pmg_desc = "Marked TLB and SLB misses",
- .pmg_event_ids = { 303, 280, 273, 275, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[167],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x020c0007121a1a1aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6685,7 +8816,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 168 ] = {
.pmg_name = "pm_ep_mrk_dtlbref",
.pmg_desc = "Marked data TLB references",
- .pmg_event_ids = { 303, 282, 275, 277, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[168],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x020c0007120c0c0cULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6693,7 +8824,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 169 ] = {
.pmg_name = "pm_ep_mrk_dtlbmiss",
.pmg_desc = "Marked data TLB misses",
- .pmg_event_ids = { 303, 280, 273, 275, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[169],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x020c0007121a1a1aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6701,7 +8832,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 170 ] = {
.pmg_name = "pm_ep_mrk_lbref",
.pmg_desc = "Marked TLB and SLB references",
- .pmg_event_ids = { 280, 302, 275, 273, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[170],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x063c000a0c120c8eULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6709,7 +8840,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 171 ] = {
.pmg_name = "pm_ep_mrk_lsmiss",
.pmg_desc = "Marked load and store miss",
- .pmg_event_ids = { 285, 302, 294, 263, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[171],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000800081012060aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6717,7 +8848,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 172 ] = {
.pmg_name = "pm_ep_mrk_ulsflush",
.pmg_desc = "Mark unaligned load and store flushes",
- .pmg_event_ids = { 299, 302, 291, 295, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[172],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0020000006122020ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6725,7 +8856,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 173 ] = {
.pmg_name = "pm_ep_mrk_misc1",
.pmg_desc = "Misc marked instructions",
- .pmg_event_ids = { 303, 299, 276, 280, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[173],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000012062816ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6733,7 +8864,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 174 ] = {
.pmg_name = "pm_ep_mrk_misc2",
.pmg_desc = "Misc marked instructions",
- .pmg_event_ids = { 303, 270, 267, 281, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[174],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010b000612445ee4ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6741,7 +8872,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 175 ] = {
.pmg_name = "pm_ep_mrk_misc3",
.pmg_desc = "Misc marked instructions",
- .pmg_event_ids = { 303, 274, 272, 271, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[175],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x053b0005124c8c0eULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6749,7 +8880,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 176 ] = {
.pmg_name = "pm_ep_mrk_misc4",
.pmg_desc = "Misc marked instructions",
- .pmg_event_ids = { 278, 302, 274, 265, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[176],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x030f00091a12e82eULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6757,7 +8888,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 177 ] = {
.pmg_name = "pm_ep_mrk_misc5",
.pmg_desc = "Misc marked instructions",
- .pmg_event_ids = { 280, 302, 112, 286, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[177],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x022c00080c120286ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6765,7 +8896,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 178 ] = {
.pmg_name = "pm_ep_mrk_misc6",
.pmg_desc = "Misc marked instructions",
- .pmg_event_ids = { 278, 302, 288, 292, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[178],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x022c00081a12888aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6773,7 +8904,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 179 ] = {
.pmg_name = "pm_ep_mrk_misc7",
.pmg_desc = "Misc marked instructions",
- .pmg_event_ids = { 303, 272, 284, 288, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[179],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x012b000412408280ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6781,7 +8912,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 180 ] = {
.pmg_name = "pm_ep_mrk_misc8",
.pmg_desc = "Misc marked instructions",
- .pmg_event_ids = { 303, 268, 282, 286, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[180],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00200000120a8486ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6789,7 +8920,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 181 ] = {
.pmg_name = "pm_ep_mrk_misc9",
.pmg_desc = "Misc marked instructions",
- .pmg_event_ids = { 303, 292, 287, 297, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[181],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0028000012ac8eecULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6797,7 +8928,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 182 ] = {
.pmg_name = "pm_ep_mrk_misc10",
.pmg_desc = "Misc marked instructions",
- .pmg_event_ids = { 303, 286, 281, 298, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[182],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0008000412c0e8e6ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6805,7 +8936,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 183 ] = {
.pmg_name = "pm_ep_mrk_misc11",
.pmg_desc = "Misc marked instructions",
- .pmg_event_ids = { 303, 268, 264, 268, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[183],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x01030003120a443cULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6813,7 +8944,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 184 ] = {
.pmg_name = "pm_ep_mrk_misc12",
.pmg_desc = "Misc marked instructions",
- .pmg_event_ids = { 303, 296, 290, 294, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[184],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0020000012501010ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6821,7 +8952,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 185 ] = {
.pmg_name = "pm_ep_mrk_misc13",
.pmg_desc = "Misc marked instructions",
- .pmg_event_ids = { 269, 302, 266, 296, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[185],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0103000b0e1236ccULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6829,7 +8960,7 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 186 ] = {
.pmg_name = "pm_ep_mrk_misc14",
.pmg_desc = "Misc marked instructions",
- .pmg_event_ids = { 303, 94, 276, 293, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[186],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000012282828ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6837,11 +8968,12 @@ static pmg_power5p_group_t power5p_groups[] = {
[ 187 ] = {
.pmg_name = "pm_ep_mrk_misc15",
.pmg_desc = "Misc marked instructions",
- .pmg_event_ids = { 303, 283, 278, 278, 0, 0 },
+ .pmg_event_ids = power5p_group_event_ids[187],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4000000412220a26ULL,
.pmg_mmcra = 0x0000000000000001ULL
}
};
+
#endif
diff --git a/src/libpfm-3.y/lib/power5_events.h b/src/libpfm-3.y/lib/power5_events.h
index 8102d8d35f12204018e7e72df3acec1722bffdd8..b6903321d64b3b31a122ab65cb7d86e2086e1882 100644
--- a/src/libpfm-3.y/lib/power5_events.h
+++ b/src/libpfm-3.y/lib/power5_events.h
@@ -20,5141 +20,7281 @@
* hand.
*
*/
-static pme_power5_entry_t power5_pe[] = {
#define POWER5_PME_PM_LSU_REJECT_RELOAD_CDF 0
+#define POWER5_PME_PM_FPU1_SINGLE 1
+#define POWER5_PME_PM_L3SB_REF 2
+#define POWER5_PME_PM_THRD_PRIO_DIFF_3or4_CYC 3
+#define POWER5_PME_PM_INST_FROM_L275_SHR 4
+#define POWER5_PME_PM_MRK_DATA_FROM_L375_MOD 5
+#define POWER5_PME_PM_DTLB_MISS_4K 6
+#define POWER5_PME_PM_CLB_FULL_CYC 7
+#define POWER5_PME_PM_MRK_ST_CMPL 8
+#define POWER5_PME_PM_LSU_FLUSH_LRQ_FULL 9
+#define POWER5_PME_PM_MRK_DATA_FROM_L275_SHR 10
+#define POWER5_PME_PM_1INST_CLB_CYC 11
+#define POWER5_PME_PM_MEM_SPEC_RD_CANCEL 12
+#define POWER5_PME_PM_MRK_DTLB_MISS_16M 13
+#define POWER5_PME_PM_FPU_FDIV 14
+#define POWER5_PME_PM_FPU_SINGLE 15
+#define POWER5_PME_PM_FPU0_FMA 16
+#define POWER5_PME_PM_SLB_MISS 17
+#define POWER5_PME_PM_LSU1_FLUSH_LRQ 18
+#define POWER5_PME_PM_L2SA_ST_HIT 19
+#define POWER5_PME_PM_DTLB_MISS 20
+#define POWER5_PME_PM_BR_PRED_TA 21
+#define POWER5_PME_PM_MRK_DATA_FROM_L375_MOD_CYC 22
+#define POWER5_PME_PM_CMPLU_STALL_FXU 23
+#define POWER5_PME_PM_EXT_INT 24
+#define POWER5_PME_PM_MRK_LSU1_FLUSH_LRQ 25
+#define POWER5_PME_PM_LSU1_LDF 26
+#define POWER5_PME_PM_MRK_ST_GPS 27
+#define POWER5_PME_PM_FAB_CMD_ISSUED 28
+#define POWER5_PME_PM_LSU0_SRQ_STFWD 29
+#define POWER5_PME_PM_CR_MAP_FULL_CYC 30
+#define POWER5_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL 31
+#define POWER5_PME_PM_MRK_LSU0_FLUSH_ULD 32
+#define POWER5_PME_PM_LSU_FLUSH_SRQ_FULL 33
+#define POWER5_PME_PM_FLUSH_IMBAL 34
+#define POWER5_PME_PM_MEM_RQ_DISP_Q16to19 35
+#define POWER5_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC 36
+#define POWER5_PME_PM_DATA_FROM_L35_MOD 37
+#define POWER5_PME_PM_MEM_HI_PRIO_WR_CMPL 38
+#define POWER5_PME_PM_FPU1_FDIV 39
+#define POWER5_PME_PM_FPU0_FRSP_FCONV 40
+#define POWER5_PME_PM_MEM_RQ_DISP 41
+#define POWER5_PME_PM_LWSYNC_HELD 42
+#define POWER5_PME_PM_FXU_FIN 43
+#define POWER5_PME_PM_DSLB_MISS 44
+#define POWER5_PME_PM_FXLS1_FULL_CYC 45
+#define POWER5_PME_PM_DATA_FROM_L275_SHR 46
+#define POWER5_PME_PM_THRD_SEL_T0 47
+#define POWER5_PME_PM_PTEG_RELOAD_VALID 48
+#define POWER5_PME_PM_LSU_LMQ_LHR_MERGE 49
+#define POWER5_PME_PM_MRK_STCX_FAIL 50
+#define POWER5_PME_PM_2INST_CLB_CYC 51
+#define POWER5_PME_PM_FAB_PNtoVN_DIRECT 52
+#define POWER5_PME_PM_PTEG_FROM_L2MISS 53
+#define POWER5_PME_PM_CMPLU_STALL_LSU 54
+#define POWER5_PME_PM_MRK_DSLB_MISS 55
+#define POWER5_PME_PM_LSU_FLUSH_ULD 56
+#define POWER5_PME_PM_PTEG_FROM_LMEM 57
+#define POWER5_PME_PM_MRK_BRU_FIN 58
+#define POWER5_PME_PM_MEM_WQ_DISP_WRITE 59
+#define POWER5_PME_PM_MRK_DATA_FROM_L275_MOD_CYC 60
+#define POWER5_PME_PM_LSU1_NCLD 61
+#define POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER 62
+#define POWER5_PME_PM_SNOOP_PW_RETRY_WQ_PWQ 63
+#define POWER5_PME_PM_FPR_MAP_FULL_CYC 64
+#define POWER5_PME_PM_FPU1_FULL_CYC 65
+#define POWER5_PME_PM_L3SA_ALL_BUSY 66
+#define POWER5_PME_PM_3INST_CLB_CYC 67
+#define POWER5_PME_PM_MEM_PWQ_DISP_Q2or3 68
+#define POWER5_PME_PM_L2SA_SHR_INV 69
+#define POWER5_PME_PM_THRESH_TIMEO 70
+#define POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL 71
+#define POWER5_PME_PM_THRD_SEL_OVER_GCT_IMBAL 72
+#define POWER5_PME_PM_FPU_FSQRT 73
+#define POWER5_PME_PM_MRK_LSU0_FLUSH_LRQ 74
+#define POWER5_PME_PM_PMC1_OVERFLOW 75
+#define POWER5_PME_PM_L3SC_SNOOP_RETRY 76
+#define POWER5_PME_PM_DATA_TABLEWALK_CYC 77
+#define POWER5_PME_PM_THRD_PRIO_6_CYC 78
+#define POWER5_PME_PM_FPU_FEST 79
+#define POWER5_PME_PM_FAB_M1toP1_SIDECAR_EMPTY 80
+#define POWER5_PME_PM_MRK_DATA_FROM_RMEM 81
+#define POWER5_PME_PM_MRK_DATA_FROM_L35_MOD_CYC 82
+#define POWER5_PME_PM_MEM_PWQ_DISP 83
+#define POWER5_PME_PM_FAB_P1toM1_SIDECAR_EMPTY 84
+#define POWER5_PME_PM_LD_MISS_L1_LSU0 85
+#define POWER5_PME_PM_SNOOP_PARTIAL_RTRY_QFULL 86
+#define POWER5_PME_PM_FPU1_STALL3 87
+#define POWER5_PME_PM_GCT_USAGE_80to99_CYC 88
+#define POWER5_PME_PM_WORK_HELD 89
+#define POWER5_PME_PM_INST_CMPL 90
+#define POWER5_PME_PM_LSU1_FLUSH_UST 91
+#define POWER5_PME_PM_FXU_IDLE 92
+#define POWER5_PME_PM_LSU0_FLUSH_ULD 93
+#define POWER5_PME_PM_LSU1_REJECT_LMQ_FULL 94
+#define POWER5_PME_PM_GRP_DISP_REJECT 95
+#define POWER5_PME_PM_L2SA_MOD_INV 96
+#define POWER5_PME_PM_PTEG_FROM_L25_SHR 97
+#define POWER5_PME_PM_FAB_CMD_RETRIED 98
+#define POWER5_PME_PM_L3SA_SHR_INV 99
+#define POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL 100
+#define POWER5_PME_PM_L2SA_RCST_DISP_FAIL_ADDR 101
+#define POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL 102
+#define POWER5_PME_PM_PTEG_FROM_L375_MOD 103
+#define POWER5_PME_PM_MRK_LSU1_FLUSH_UST 104
+#define POWER5_PME_PM_BR_ISSUED 105
+#define POWER5_PME_PM_MRK_GRP_BR_REDIR 106
+#define POWER5_PME_PM_EE_OFF 107
+#define POWER5_PME_PM_MEM_RQ_DISP_Q4to7 108
+#define POWER5_PME_PM_MEM_FAST_PATH_RD_DISP 109
+#define POWER5_PME_PM_INST_FROM_L3 110
+#define POWER5_PME_PM_ITLB_MISS 111
+#define POWER5_PME_PM_FXU1_BUSY_FXU0_IDLE 112
+#define POWER5_PME_PM_FXLS_FULL_CYC 113
+#define POWER5_PME_PM_DTLB_REF_4K 114
+#define POWER5_PME_PM_GRP_DISP_VALID 115
+#define POWER5_PME_PM_LSU_FLUSH_UST 116
+#define POWER5_PME_PM_FXU1_FIN 117
+#define POWER5_PME_PM_THRD_PRIO_4_CYC 118
+#define POWER5_PME_PM_MRK_DATA_FROM_L35_MOD 119
+#define POWER5_PME_PM_4INST_CLB_CYC 120
+#define POWER5_PME_PM_MRK_DTLB_REF_16M 121
+#define POWER5_PME_PM_INST_FROM_L375_MOD 122
+#define POWER5_PME_PM_L2SC_RCST_DISP_FAIL_ADDR 123
+#define POWER5_PME_PM_GRP_CMPL 124
+#define POWER5_PME_PM_FPU1_1FLOP 125
+#define POWER5_PME_PM_FPU_FRSP_FCONV 126
+#define POWER5_PME_PM_5INST_CLB_CYC 127
+#define POWER5_PME_PM_L3SC_REF 128
+#define POWER5_PME_PM_THRD_L2MISS_BOTH_CYC 129
+#define POWER5_PME_PM_MEM_PW_GATH 130
+#define POWER5_PME_PM_FAB_PNtoNN_SIDECAR 131
+#define POWER5_PME_PM_FAB_DCLAIM_ISSUED 132
+#define POWER5_PME_PM_GRP_IC_MISS 133
+#define POWER5_PME_PM_INST_FROM_L35_SHR 134
+#define POWER5_PME_PM_LSU_LMQ_FULL_CYC 135
+#define POWER5_PME_PM_MRK_DATA_FROM_L2_CYC 136
+#define POWER5_PME_PM_LSU_SRQ_SYNC_CYC 137
+#define POWER5_PME_PM_LSU0_BUSY_REJECT 138
+#define POWER5_PME_PM_LSU_REJECT_ERAT_MISS 139
+#define POWER5_PME_PM_MRK_DATA_FROM_RMEM_CYC 140
+#define POWER5_PME_PM_DATA_FROM_L375_SHR 141
+#define POWER5_PME_PM_FPU0_FMOV_FEST 142
+#define POWER5_PME_PM_PTEG_FROM_L25_MOD 143
+#define POWER5_PME_PM_LD_REF_L1_LSU0 144
+#define POWER5_PME_PM_THRD_PRIO_7_CYC 145
+#define POWER5_PME_PM_LSU1_FLUSH_SRQ 146
+#define POWER5_PME_PM_L2SC_RCST_DISP 147
+#define POWER5_PME_PM_CMPLU_STALL_DIV 148
+#define POWER5_PME_PM_MEM_RQ_DISP_Q12to15 149
+#define POWER5_PME_PM_INST_FROM_L375_SHR 150
+#define POWER5_PME_PM_ST_REF_L1 151
+#define POWER5_PME_PM_L3SB_ALL_BUSY 152
+#define POWER5_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY 153
+#define POWER5_PME_PM_MRK_DATA_FROM_L275_SHR_CYC 154
+#define POWER5_PME_PM_FAB_HOLDtoNN_EMPTY 155
+#define POWER5_PME_PM_DATA_FROM_LMEM 156
+#define POWER5_PME_PM_RUN_CYC 157
+#define POWER5_PME_PM_PTEG_FROM_RMEM 158
+#define POWER5_PME_PM_L2SC_RCLD_DISP 159
+#define POWER5_PME_PM_LSU0_LDF 160
+#define POWER5_PME_PM_LSU_LRQ_S0_VALID 161
+#define POWER5_PME_PM_PMC3_OVERFLOW 162
+#define POWER5_PME_PM_MRK_IMR_RELOAD 163
+#define POWER5_PME_PM_MRK_GRP_TIMEO 164
+#define POWER5_PME_PM_ST_MISS_L1 165
+#define POWER5_PME_PM_STOP_COMPLETION 166
+#define POWER5_PME_PM_LSU_BUSY_REJECT 167
+#define POWER5_PME_PM_ISLB_MISS 168
+#define POWER5_PME_PM_CYC 169
+#define POWER5_PME_PM_THRD_ONE_RUN_CYC 170
+#define POWER5_PME_PM_GRP_BR_REDIR_NONSPEC 171
+#define POWER5_PME_PM_LSU1_SRQ_STFWD 172
+#define POWER5_PME_PM_L3SC_MOD_INV 173
+#define POWER5_PME_PM_L2_PREF 174
+#define POWER5_PME_PM_GCT_NOSLOT_BR_MPRED 175
+#define POWER5_PME_PM_MRK_DATA_FROM_L25_MOD 176
+#define POWER5_PME_PM_L2SB_MOD_INV 177
+#define POWER5_PME_PM_L2SB_ST_REQ 178
+#define POWER5_PME_PM_MRK_L1_RELOAD_VALID 179
+#define POWER5_PME_PM_L3SB_HIT 180
+#define POWER5_PME_PM_L2SB_SHR_MOD 181
+#define POWER5_PME_PM_EE_OFF_EXT_INT 182
+#define POWER5_PME_PM_1PLUS_PPC_CMPL 183
+#define POWER5_PME_PM_L2SC_SHR_MOD 184
+#define POWER5_PME_PM_PMC6_OVERFLOW 185
+#define POWER5_PME_PM_LSU_LRQ_FULL_CYC 186
+#define POWER5_PME_PM_IC_PREF_INSTALL 187
+#define POWER5_PME_PM_TLB_MISS 188
+#define POWER5_PME_PM_GCT_FULL_CYC 189
+#define POWER5_PME_PM_FXU_BUSY 190
+#define POWER5_PME_PM_MRK_DATA_FROM_L3_CYC 191
+#define POWER5_PME_PM_LSU_REJECT_LMQ_FULL 192
+#define POWER5_PME_PM_LSU_SRQ_S0_ALLOC 193
+#define POWER5_PME_PM_GRP_MRK 194
+#define POWER5_PME_PM_INST_FROM_L25_SHR 195
+#define POWER5_PME_PM_FPU1_FIN 196
+#define POWER5_PME_PM_DC_PREF_STREAM_ALLOC 197
+#define POWER5_PME_PM_BR_MPRED_TA 198
+#define POWER5_PME_PM_CRQ_FULL_CYC 199
+#define POWER5_PME_PM_L2SA_RCLD_DISP 200
+#define POWER5_PME_PM_SNOOP_WR_RETRY_QFULL 201
+#define POWER5_PME_PM_MRK_DTLB_REF_4K 202
+#define POWER5_PME_PM_LSU_SRQ_S0_VALID 203
+#define POWER5_PME_PM_LSU0_FLUSH_LRQ 204
+#define POWER5_PME_PM_INST_FROM_L275_MOD 205
+#define POWER5_PME_PM_GCT_EMPTY_CYC 206
+#define POWER5_PME_PM_LARX_LSU0 207
+#define POWER5_PME_PM_THRD_PRIO_DIFF_5or6_CYC 208
+#define POWER5_PME_PM_SNOOP_RETRY_1AHEAD 209
+#define POWER5_PME_PM_FPU1_FSQRT 210
+#define POWER5_PME_PM_MRK_LD_MISS_L1_LSU1 211
+#define POWER5_PME_PM_MRK_FPU_FIN 212
+#define POWER5_PME_PM_THRD_PRIO_5_CYC 213
+#define POWER5_PME_PM_MRK_DATA_FROM_LMEM 214
+#define POWER5_PME_PM_FPU1_FRSP_FCONV 215
+#define POWER5_PME_PM_SNOOP_TLBIE 216
+#define POWER5_PME_PM_L3SB_SNOOP_RETRY 217
+#define POWER5_PME_PM_FAB_VBYPASS_EMPTY 218
+#define POWER5_PME_PM_MRK_DATA_FROM_L275_MOD 219
+#define POWER5_PME_PM_6INST_CLB_CYC 220
+#define POWER5_PME_PM_L2SB_RCST_DISP 221
+#define POWER5_PME_PM_FLUSH 222
+#define POWER5_PME_PM_L2SC_MOD_INV 223
+#define POWER5_PME_PM_FPU_DENORM 224
+#define POWER5_PME_PM_L3SC_HIT 225
+#define POWER5_PME_PM_SNOOP_WR_RETRY_RQ 226
+#define POWER5_PME_PM_LSU1_REJECT_SRQ 227
+#define POWER5_PME_PM_IC_PREF_REQ 228
+#define POWER5_PME_PM_L3SC_ALL_BUSY 229
+#define POWER5_PME_PM_MRK_GRP_IC_MISS 230
+#define POWER5_PME_PM_GCT_NOSLOT_IC_MISS 231
+#define POWER5_PME_PM_MRK_DATA_FROM_L3 232
+#define POWER5_PME_PM_GCT_NOSLOT_SRQ_FULL 233
+#define POWER5_PME_PM_THRD_SEL_OVER_ISU_HOLD 234
+#define POWER5_PME_PM_CMPLU_STALL_DCACHE_MISS 235
+#define POWER5_PME_PM_L3SA_MOD_INV 236
+#define POWER5_PME_PM_LSU_FLUSH_LRQ 237
+#define POWER5_PME_PM_THRD_PRIO_2_CYC 238
+#define POWER5_PME_PM_LSU_FLUSH_SRQ 239
+#define POWER5_PME_PM_MRK_LSU_SRQ_INST_VALID 240
+#define POWER5_PME_PM_L3SA_REF 241
+#define POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL 242
+#define POWER5_PME_PM_FPU0_STALL3 243
+#define POWER5_PME_PM_GPR_MAP_FULL_CYC 244
+#define POWER5_PME_PM_TB_BIT_TRANS 245
+#define POWER5_PME_PM_MRK_LSU_FLUSH_LRQ 246
+#define POWER5_PME_PM_FPU0_STF 247
+#define POWER5_PME_PM_MRK_DTLB_MISS 248
+#define POWER5_PME_PM_FPU1_FMA 249
+#define POWER5_PME_PM_L2SA_MOD_TAG 250
+#define POWER5_PME_PM_LSU1_FLUSH_ULD 251
+#define POWER5_PME_PM_MRK_LSU0_FLUSH_UST 252
+#define POWER5_PME_PM_MRK_INST_FIN 253
+#define POWER5_PME_PM_FPU0_FULL_CYC 254
+#define POWER5_PME_PM_LSU_LRQ_S0_ALLOC 255
+#define POWER5_PME_PM_MRK_LSU1_FLUSH_ULD 256
+#define POWER5_PME_PM_MRK_DTLB_REF 257
+#define POWER5_PME_PM_BR_UNCOND 258
+#define POWER5_PME_PM_THRD_SEL_OVER_L2MISS 259
+#define POWER5_PME_PM_L2SB_SHR_INV 260
+#define POWER5_PME_PM_MEM_LO_PRIO_WR_CMPL 261
+#define POWER5_PME_PM_L3SC_MOD_TAG 262
+#define POWER5_PME_PM_MRK_ST_MISS_L1 263
+#define POWER5_PME_PM_GRP_DISP_SUCCESS 264
+#define POWER5_PME_PM_THRD_PRIO_DIFF_1or2_CYC 265
+#define POWER5_PME_PM_IC_DEMAND_L2_BHT_REDIRECT 266
+#define POWER5_PME_PM_MEM_WQ_DISP_Q8to15 267
+#define POWER5_PME_PM_FPU0_SINGLE 268
+#define POWER5_PME_PM_LSU_DERAT_MISS 269
+#define POWER5_PME_PM_THRD_PRIO_1_CYC 270
+#define POWER5_PME_PM_L2SC_RCST_DISP_FAIL_OTHER 271
+#define POWER5_PME_PM_FPU1_FEST 272
+#define POWER5_PME_PM_FAB_HOLDtoVN_EMPTY 273
+#define POWER5_PME_PM_SNOOP_RD_RETRY_RQ 274
+#define POWER5_PME_PM_SNOOP_DCLAIM_RETRY_QFULL 275
+#define POWER5_PME_PM_MRK_DATA_FROM_L25_SHR_CYC 276
+#define POWER5_PME_PM_MRK_ST_CMPL_INT 277
+#define POWER5_PME_PM_FLUSH_BR_MPRED 278
+#define POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR 279
+#define POWER5_PME_PM_FPU_STF 280
+#define POWER5_PME_PM_CMPLU_STALL_FPU 281
+#define POWER5_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC 282
+#define POWER5_PME_PM_GCT_NOSLOT_CYC 283
+#define POWER5_PME_PM_FXU0_BUSY_FXU1_IDLE 284
+#define POWER5_PME_PM_PTEG_FROM_L35_SHR 285
+#define POWER5_PME_PM_MRK_LSU_FLUSH_UST 286
+#define POWER5_PME_PM_L3SA_HIT 287
+#define POWER5_PME_PM_MRK_DATA_FROM_L25_SHR 288
+#define POWER5_PME_PM_L2SB_RCST_DISP_FAIL_ADDR 289
+#define POWER5_PME_PM_MRK_DATA_FROM_L35_SHR 290
+#define POWER5_PME_PM_IERAT_XLATE_WR 291
+#define POWER5_PME_PM_L2SA_ST_REQ 292
+#define POWER5_PME_PM_THRD_SEL_T1 293
+#define POWER5_PME_PM_IC_DEMAND_L2_BR_REDIRECT 294
+#define POWER5_PME_PM_INST_FROM_LMEM 295
+#define POWER5_PME_PM_FPU0_1FLOP 296
+#define POWER5_PME_PM_MRK_DATA_FROM_L35_SHR_CYC 297
+#define POWER5_PME_PM_PTEG_FROM_L2 298
+#define POWER5_PME_PM_MEM_PW_CMPL 299
+#define POWER5_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC 300
+#define POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER 301
+#define POWER5_PME_PM_FPU0_FIN 302
+#define POWER5_PME_PM_MRK_DTLB_MISS_4K 303
+#define POWER5_PME_PM_L3SC_SHR_INV 304
+#define POWER5_PME_PM_GRP_BR_REDIR 305
+#define POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL 306
+#define POWER5_PME_PM_MRK_LSU_FLUSH_SRQ 307
+#define POWER5_PME_PM_PTEG_FROM_L275_SHR 308
+#define POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL 309
+#define POWER5_PME_PM_SNOOP_RD_RETRY_WQ 310
+#define POWER5_PME_PM_LSU0_NCLD 311
+#define POWER5_PME_PM_FAB_DCLAIM_RETRIED 312
+#define POWER5_PME_PM_LSU1_BUSY_REJECT 313
+#define POWER5_PME_PM_FXLS0_FULL_CYC 314
+#define POWER5_PME_PM_FPU0_FEST 315
+#define POWER5_PME_PM_DTLB_REF_16M 316
+#define POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR 317
+#define POWER5_PME_PM_LSU0_REJECT_ERAT_MISS 318
+#define POWER5_PME_PM_DATA_FROM_L25_MOD 319
+#define POWER5_PME_PM_GCT_USAGE_60to79_CYC 320
+#define POWER5_PME_PM_DATA_FROM_L375_MOD 321
+#define POWER5_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 322
+#define POWER5_PME_PM_LSU0_REJECT_RELOAD_CDF 323
+#define POWER5_PME_PM_0INST_FETCH 324
+#define POWER5_PME_PM_LSU1_REJECT_RELOAD_CDF 325
+#define POWER5_PME_PM_L1_PREF 326
+#define POWER5_PME_PM_MEM_WQ_DISP_Q0to7 327
+#define POWER5_PME_PM_MRK_DATA_FROM_LMEM_CYC 328
+#define POWER5_PME_PM_BRQ_FULL_CYC 329
+#define POWER5_PME_PM_GRP_IC_MISS_NONSPEC 330
+#define POWER5_PME_PM_PTEG_FROM_L275_MOD 331
+#define POWER5_PME_PM_MRK_LD_MISS_L1_LSU0 332
+#define POWER5_PME_PM_MRK_DATA_FROM_L375_SHR_CYC 333
+#define POWER5_PME_PM_LSU_FLUSH 334
+#define POWER5_PME_PM_DATA_FROM_L3 335
+#define POWER5_PME_PM_INST_FROM_L2 336
+#define POWER5_PME_PM_PMC2_OVERFLOW 337
+#define POWER5_PME_PM_FPU0_DENORM 338
+#define POWER5_PME_PM_FPU1_FMOV_FEST 339
+#define POWER5_PME_PM_INST_FETCH_CYC 340
+#define POWER5_PME_PM_LSU_LDF 341
+#define POWER5_PME_PM_INST_DISP 342
+#define POWER5_PME_PM_DATA_FROM_L25_SHR 343
+#define POWER5_PME_PM_L1_DCACHE_RELOAD_VALID 344
+#define POWER5_PME_PM_MEM_WQ_DISP_DCLAIM 345
+#define POWER5_PME_PM_FPU_FULL_CYC 346
+#define POWER5_PME_PM_MRK_GRP_ISSUED 347
+#define POWER5_PME_PM_THRD_PRIO_3_CYC 348
+#define POWER5_PME_PM_FPU_FMA 349
+#define POWER5_PME_PM_INST_FROM_L35_MOD 350
+#define POWER5_PME_PM_MRK_CRU_FIN 351
+#define POWER5_PME_PM_SNOOP_WR_RETRY_WQ 352
+#define POWER5_PME_PM_CMPLU_STALL_REJECT 353
+#define POWER5_PME_PM_LSU1_REJECT_ERAT_MISS 354
+#define POWER5_PME_PM_MRK_FXU_FIN 355
+#define POWER5_PME_PM_L2SB_RCST_DISP_FAIL_OTHER 356
+#define POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY 357
+#define POWER5_PME_PM_PMC4_OVERFLOW 358
+#define POWER5_PME_PM_L3SA_SNOOP_RETRY 359
+#define POWER5_PME_PM_PTEG_FROM_L35_MOD 360
+#define POWER5_PME_PM_INST_FROM_L25_MOD 361
+#define POWER5_PME_PM_THRD_SMT_HANG 362
+#define POWER5_PME_PM_CMPLU_STALL_ERAT_MISS 363
+#define POWER5_PME_PM_L3SA_MOD_TAG 364
+#define POWER5_PME_PM_FLUSH_SYNC 365
+#define POWER5_PME_PM_INST_FROM_L2MISS 366
+#define POWER5_PME_PM_L2SC_ST_HIT 367
+#define POWER5_PME_PM_MEM_RQ_DISP_Q8to11 368
+#define POWER5_PME_PM_MRK_GRP_DISP 369
+#define POWER5_PME_PM_L2SB_MOD_TAG 370
+#define POWER5_PME_PM_CLB_EMPTY_CYC 371
+#define POWER5_PME_PM_L2SB_ST_HIT 372
+#define POWER5_PME_PM_MEM_NONSPEC_RD_CANCEL 373
+#define POWER5_PME_PM_BR_PRED_CR_TA 374
+#define POWER5_PME_PM_MRK_LSU0_FLUSH_SRQ 375
+#define POWER5_PME_PM_MRK_LSU_FLUSH_ULD 376
+#define POWER5_PME_PM_INST_DISP_ATTEMPT 377
+#define POWER5_PME_PM_INST_FROM_RMEM 378
+#define POWER5_PME_PM_ST_REF_L1_LSU0 379
+#define POWER5_PME_PM_LSU0_DERAT_MISS 380
+#define POWER5_PME_PM_L2SB_RCLD_DISP 381
+#define POWER5_PME_PM_FPU_STALL3 382
+#define POWER5_PME_PM_BR_PRED_CR 383
+#define POWER5_PME_PM_MRK_DATA_FROM_L2 384
+#define POWER5_PME_PM_LSU0_FLUSH_SRQ 385
+#define POWER5_PME_PM_FAB_PNtoNN_DIRECT 386
+#define POWER5_PME_PM_IOPS_CMPL 387
+#define POWER5_PME_PM_L2SC_SHR_INV 388
+#define POWER5_PME_PM_L2SA_RCST_DISP_FAIL_OTHER 389
+#define POWER5_PME_PM_L2SA_RCST_DISP 390
+#define POWER5_PME_PM_SNOOP_RETRY_AB_COLLISION 391
+#define POWER5_PME_PM_FAB_PNtoVN_SIDECAR 392
+#define POWER5_PME_PM_LSU_LMQ_S0_ALLOC 393
+#define POWER5_PME_PM_LSU0_REJECT_LMQ_FULL 394
+#define POWER5_PME_PM_SNOOP_PW_RETRY_RQ 395
+#define POWER5_PME_PM_DTLB_REF 396
+#define POWER5_PME_PM_PTEG_FROM_L3 397
+#define POWER5_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY 398
+#define POWER5_PME_PM_LSU_SRQ_EMPTY_CYC 399
+#define POWER5_PME_PM_FPU1_STF 400
+#define POWER5_PME_PM_LSU_LMQ_S0_VALID 401
+#define POWER5_PME_PM_GCT_USAGE_00to59_CYC 402
+#define POWER5_PME_PM_DATA_FROM_L2MISS 403
+#define POWER5_PME_PM_GRP_DISP_BLK_SB_CYC 404
+#define POWER5_PME_PM_FPU_FMOV_FEST 405
+#define POWER5_PME_PM_XER_MAP_FULL_CYC 406
+#define POWER5_PME_PM_FLUSH_SB 407
+#define POWER5_PME_PM_MRK_DATA_FROM_L375_SHR 408
+#define POWER5_PME_PM_MRK_GRP_CMPL 409
+#define POWER5_PME_PM_SUSPENDED 410
+#define POWER5_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC 411
+#define POWER5_PME_PM_SNOOP_RD_RETRY_QFULL 412
+#define POWER5_PME_PM_L3SB_MOD_INV 413
+#define POWER5_PME_PM_DATA_FROM_L35_SHR 414
+#define POWER5_PME_PM_LD_MISS_L1_LSU1 415
+#define POWER5_PME_PM_STCX_FAIL 416
+#define POWER5_PME_PM_DC_PREF_DST 417
+#define POWER5_PME_PM_GRP_DISP 418
+#define POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR 419
+#define POWER5_PME_PM_FPU0_FPSCR 420
+#define POWER5_PME_PM_DATA_FROM_L2 421
+#define POWER5_PME_PM_FPU1_DENORM 422
+#define POWER5_PME_PM_FPU_1FLOP 423
+#define POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER 424
+#define POWER5_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL 425
+#define POWER5_PME_PM_FPU0_FSQRT 426
+#define POWER5_PME_PM_LD_REF_L1 427
+#define POWER5_PME_PM_INST_FROM_L1 428
+#define POWER5_PME_PM_TLBIE_HELD 429
+#define POWER5_PME_PM_DC_PREF_OUT_OF_STREAMS 430
+#define POWER5_PME_PM_MRK_DATA_FROM_L25_MOD_CYC 431
+#define POWER5_PME_PM_MRK_LSU1_FLUSH_SRQ 432
+#define POWER5_PME_PM_MEM_RQ_DISP_Q0to3 433
+#define POWER5_PME_PM_ST_REF_L1_LSU1 434
+#define POWER5_PME_PM_MRK_LD_MISS_L1 435
+#define POWER5_PME_PM_L1_WRITE_CYC 436
+#define POWER5_PME_PM_L2SC_ST_REQ 437
+#define POWER5_PME_PM_CMPLU_STALL_FDIV 438
+#define POWER5_PME_PM_THRD_SEL_OVER_CLB_EMPTY 439
+#define POWER5_PME_PM_BR_MPRED_CR 440
+#define POWER5_PME_PM_L3SB_MOD_TAG 441
+#define POWER5_PME_PM_MRK_DATA_FROM_L2MISS 442
+#define POWER5_PME_PM_LSU_REJECT_SRQ 443
+#define POWER5_PME_PM_LD_MISS_L1 444
+#define POWER5_PME_PM_INST_FROM_PREF 445
+#define POWER5_PME_PM_DC_INV_L2 446
+#define POWER5_PME_PM_STCX_PASS 447
+#define POWER5_PME_PM_LSU_SRQ_FULL_CYC 448
+#define POWER5_PME_PM_FPU_FIN 449
+#define POWER5_PME_PM_L2SA_SHR_MOD 450
+#define POWER5_PME_PM_LSU_SRQ_STFWD 451
+#define POWER5_PME_PM_0INST_CLB_CYC 452
+#define POWER5_PME_PM_FXU0_FIN 453
+#define POWER5_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL 454
+#define POWER5_PME_PM_THRD_GRP_CMPL_BOTH_CYC 455
+#define POWER5_PME_PM_PMC5_OVERFLOW 456
+#define POWER5_PME_PM_FPU0_FDIV 457
+#define POWER5_PME_PM_PTEG_FROM_L375_SHR 458
+#define POWER5_PME_PM_LD_REF_L1_LSU1 459
+#define POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY 460
+#define POWER5_PME_PM_HV_CYC 461
+#define POWER5_PME_PM_THRD_PRIO_DIFF_0_CYC 462
+#define POWER5_PME_PM_LR_CTR_MAP_FULL_CYC 463
+#define POWER5_PME_PM_L3SB_SHR_INV 464
+#define POWER5_PME_PM_DATA_FROM_RMEM 465
+#define POWER5_PME_PM_DATA_FROM_L275_MOD 466
+#define POWER5_PME_PM_LSU0_REJECT_SRQ 467
+#define POWER5_PME_PM_LSU1_DERAT_MISS 468
+#define POWER5_PME_PM_MRK_LSU_FIN 469
+#define POWER5_PME_PM_DTLB_MISS_16M 470
+#define POWER5_PME_PM_LSU0_FLUSH_UST 471
+#define POWER5_PME_PM_L2SC_MOD_TAG 472
+#define POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY 473
+
+
+static const int power5_event_ids[][POWER5_NUM_EVENT_COUNTERS] = {
+ [ POWER5_PME_PM_LSU_REJECT_RELOAD_CDF ] = { -1, 145, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU1_SINGLE ] = { 51, 50, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L3SB_REF ] = { 111, 109, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_THRD_PRIO_DIFF_3or4_CYC ] = { -1, -1, 173, 179, -1, -1 },
+ [ POWER5_PME_PM_INST_FROM_L275_SHR ] = { -1, -1, 57, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L375_MOD ] = { 165, -1, -1, 139, -1, -1 },
+ [ POWER5_PME_PM_DTLB_MISS_4K ] = { 24, 23, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_CLB_FULL_CYC ] = { 10, 9, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_ST_CMPL ] = { 179, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU_FLUSH_LRQ_FULL ] = { 140, 139, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L275_SHR ] = { -1, -1, 130, -1, -1, -1 },
+ [ POWER5_PME_PM_1INST_CLB_CYC ] = { 1, 1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MEM_SPEC_RD_CANCEL ] = { 157, 155, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_DTLB_MISS_16M ] = { 167, 168, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU_FDIV ] = { 55, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU_SINGLE ] = { 58, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU0_FMA ] = { 39, 38, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_SLB_MISS ] = { -1, 184, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU1_FLUSH_LRQ ] = { 130, 128, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SA_ST_HIT ] = { -1, -1, 70, 74, -1, -1 },
+ [ POWER5_PME_PM_DTLB_MISS ] = { 22, 21, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_BR_PRED_TA ] = { -1, 8, 4, 6, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L375_MOD_CYC ] = { -1, -1, -1, 140, -1, -1 },
+ [ POWER5_PME_PM_CMPLU_STALL_FXU ] = { -1, 12, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_EXT_INT ] = { -1, -1, -1, 21, -1, -1 },
+ [ POWER5_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { -1, -1, 143, 154, -1, -1 },
+ [ POWER5_PME_PM_LSU1_LDF ] = { -1, -1, 107, 111, -1, -1 },
+ [ POWER5_PME_PM_MRK_ST_GPS ] = { -1, 178, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FAB_CMD_ISSUED ] = { 27, 26, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU0_SRQ_STFWD ] = { 127, 125, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_CR_MAP_FULL_CYC ] = { 11, 14, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL ] = { 86, 84, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_LSU0_FLUSH_ULD ] = { -1, -1, 142, 153, -1, -1 },
+ [ POWER5_PME_PM_LSU_FLUSH_SRQ_FULL ] = { -1, -1, 110, 114, -1, -1 },
+ [ POWER5_PME_PM_FLUSH_IMBAL ] = { -1, -1, 25, 30, -1, -1 },
+ [ POWER5_PME_PM_MEM_RQ_DISP_Q16to19 ] = { 151, 149, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC ] = { -1, -1, 176, 182, -1, -1 },
+ [ POWER5_PME_PM_DATA_FROM_L35_MOD ] = { -1, 17, 9, -1, -1, -1 },
+ [ POWER5_PME_PM_MEM_HI_PRIO_WR_CMPL ] = { 152, 150, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU1_FDIV ] = { 47, 46, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU0_FRSP_FCONV ] = { -1, -1, 33, 38, -1, -1 },
+ [ POWER5_PME_PM_MEM_RQ_DISP ] = { 156, 154, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LWSYNC_HELD ] = { -1, -1, 120, 125, -1, -1 },
+ [ POWER5_PME_PM_FXU_FIN ] = { -1, -1, 45, -1, -1, -1 },
+ [ POWER5_PME_PM_DSLB_MISS ] = { 21, 20, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FXLS1_FULL_CYC ] = { -1, -1, 41, 46, -1, -1 },
+ [ POWER5_PME_PM_DATA_FROM_L275_SHR ] = { -1, -1, 8, -1, -1, -1 },
+ [ POWER5_PME_PM_THRD_SEL_T0 ] = { -1, -1, 182, 188, -1, -1 },
+ [ POWER5_PME_PM_PTEG_RELOAD_VALID ] = { -1, -1, 191, 195, -1, -1 },
+ [ POWER5_PME_PM_LSU_LMQ_LHR_MERGE ] = { -1, -1, 112, 117, -1, -1 },
+ [ POWER5_PME_PM_MRK_STCX_FAIL ] = { 178, 177, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_2INST_CLB_CYC ] = { 3, 2, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FAB_PNtoVN_DIRECT ] = { 34, 33, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_PTEG_FROM_L2MISS ] = { -1, -1, 189, -1, -1, -1 },
+ [ POWER5_PME_PM_CMPLU_STALL_LSU ] = { -1, 13, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_DSLB_MISS ] = { -1, -1, 134, 144, -1, -1 },
+ [ POWER5_PME_PM_LSU_FLUSH_ULD ] = { 142, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_PTEG_FROM_LMEM ] = { -1, 183, 157, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_BRU_FIN ] = { -1, 158, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MEM_WQ_DISP_WRITE ] = { 159, 157, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L275_MOD_CYC ] = { -1, -1, -1, 137, -1, -1 },
+ [ POWER5_PME_PM_LSU1_NCLD ] = { -1, -1, 108, 112, -1, -1 },
+ [ POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER ] = { -1, -1, 65, 69, -1, -1 },
+ [ POWER5_PME_PM_SNOOP_PW_RETRY_WQ_PWQ ] = { -1, -1, 159, 167, -1, -1 },
+ [ POWER5_PME_PM_FPR_MAP_FULL_CYC ] = { 35, 34, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU1_FULL_CYC ] = { 50, 49, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L3SA_ALL_BUSY ] = { 106, 104, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_3INST_CLB_CYC ] = { 4, 3, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MEM_PWQ_DISP_Q2or3 ] = { -1, -1, 123, 128, -1, -1 },
+ [ POWER5_PME_PM_L2SA_SHR_INV ] = { -1, -1, 69, 73, -1, -1 },
+ [ POWER5_PME_PM_THRESH_TIMEO ] = { -1, -1, 185, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL ] = { -1, -1, 68, 72, -1, -1 },
+ [ POWER5_PME_PM_THRD_SEL_OVER_GCT_IMBAL ] = { -1, -1, 179, 185, -1, -1 },
+ [ POWER5_PME_PM_FPU_FSQRT ] = { -1, 53, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { -1, -1, 139, 150, -1, -1 },
+ [ POWER5_PME_PM_PMC1_OVERFLOW ] = { -1, 180, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L3SC_SNOOP_RETRY ] = { -1, -1, 99, 103, -1, -1 },
+ [ POWER5_PME_PM_DATA_TABLEWALK_CYC ] = { 20, 19, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_THRD_PRIO_6_CYC ] = { 208, 202, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU_FEST ] = { -1, -1, -1, 43, -1, -1 },
+ [ POWER5_PME_PM_FAB_M1toP1_SIDECAR_EMPTY ] = { 31, 30, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_RMEM ] = { 166, -1, -1, 142, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L35_MOD_CYC ] = { -1, -1, -1, 138, -1, -1 },
+ [ POWER5_PME_PM_MEM_PWQ_DISP ] = { 153, 151, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FAB_P1toM1_SIDECAR_EMPTY ] = { 32, 31, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LD_MISS_L1_LSU0 ] = { -1, -1, 101, 104, -1, -1 },
+ [ POWER5_PME_PM_SNOOP_PARTIAL_RTRY_QFULL ] = { -1, -1, 158, 166, -1, -1 },
+ [ POWER5_PME_PM_FPU1_STALL3 ] = { 52, 51, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_GCT_USAGE_80to99_CYC ] = { -1, -1, 47, -1, -1, -1 },
+ [ POWER5_PME_PM_WORK_HELD ] = { -1, -1, -1, 192, -1, -1 },
+ [ POWER5_PME_PM_INST_CMPL ] = { 174, 174, -1, -1, 0, -1 },
+ [ POWER5_PME_PM_LSU1_FLUSH_UST ] = { 133, 131, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FXU_IDLE ] = { 59, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU0_FLUSH_ULD ] = { 121, 119, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU1_REJECT_LMQ_FULL ] = { 135, 133, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_GRP_DISP_REJECT ] = { 65, 65, -1, 55, -1, -1 },
+ [ POWER5_PME_PM_L2SA_MOD_INV ] = { -1, -1, 63, 67, -1, -1 },
+ [ POWER5_PME_PM_PTEG_FROM_L25_SHR ] = { 184, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FAB_CMD_RETRIED ] = { -1, -1, 17, 22, -1, -1 },
+ [ POWER5_PME_PM_L3SA_SHR_INV ] = { -1, -1, 90, 94, -1, -1 },
+ [ POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL ] = { -1, -1, 76, 80, -1, -1 },
+ [ POWER5_PME_PM_L2SA_RCST_DISP_FAIL_ADDR ] = { -1, -1, 66, 70, -1, -1 },
+ [ POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL ] = { 84, 82, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_PTEG_FROM_L375_MOD ] = { 188, -1, -1, 164, -1, -1 },
+ [ POWER5_PME_PM_MRK_LSU1_FLUSH_UST ] = { -1, -1, 146, 157, -1, -1 },
+ [ POWER5_PME_PM_BR_ISSUED ] = { -1, -1, 0, 1, -1, -1 },
+ [ POWER5_PME_PM_MRK_GRP_BR_REDIR ] = { -1, 172, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_EE_OFF ] = { -1, -1, 15, 19, -1, -1 },
+ [ POWER5_PME_PM_MEM_RQ_DISP_Q4to7 ] = { -1, -1, 126, 131, -1, -1 },
+ [ POWER5_PME_PM_MEM_FAST_PATH_RD_DISP ] = { -1, -1, 190, 193, -1, -1 },
+ [ POWER5_PME_PM_INST_FROM_L3 ] = { 78, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_ITLB_MISS ] = { 81, 79, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { -1, -1, -1, 49, -1, -1 },
+ [ POWER5_PME_PM_FXLS_FULL_CYC ] = { -1, -1, -1, 47, -1, -1 },
+ [ POWER5_PME_PM_DTLB_REF_4K ] = { 26, 25, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_GRP_DISP_VALID ] = { 66, 66, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU_FLUSH_UST ] = { -1, 140, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FXU1_FIN ] = { -1, -1, 44, 50, -1, -1 },
+ [ POWER5_PME_PM_THRD_PRIO_4_CYC ] = { 206, 200, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L35_MOD ] = { -1, 163, 131, -1, -1, -1 },
+ [ POWER5_PME_PM_4INST_CLB_CYC ] = { 5, 4, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_DTLB_REF_16M ] = { 169, 170, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_INST_FROM_L375_MOD ] = { -1, -1, -1, 62, -1, -1 },
+ [ POWER5_PME_PM_L2SC_RCST_DISP_FAIL_ADDR ] = { -1, -1, 82, 86, -1, -1 },
+ [ POWER5_PME_PM_GRP_CMPL ] = { -1, -1, 49, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU1_1FLOP ] = { 45, 44, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU_FRSP_FCONV ] = { -1, -1, 39, -1, -1, -1 },
+ [ POWER5_PME_PM_5INST_CLB_CYC ] = { 6, 5, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L3SC_REF ] = { 114, 112, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_THRD_L2MISS_BOTH_CYC ] = { -1, -1, 170, 176, -1, -1 },
+ [ POWER5_PME_PM_MEM_PW_GATH ] = { -1, -1, 124, 129, -1, -1 },
+ [ POWER5_PME_PM_FAB_PNtoNN_SIDECAR ] = { -1, -1, 21, 26, -1, -1 },
+ [ POWER5_PME_PM_FAB_DCLAIM_ISSUED ] = { 28, 27, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_GRP_IC_MISS ] = { 67, 67, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_INST_FROM_L35_SHR ] = { 79, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU_LMQ_FULL_CYC ] = { -1, -1, 111, 116, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L2_CYC ] = { -1, 162, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU_SRQ_SYNC_CYC ] = { -1, -1, 119, 124, -1, -1 },
+ [ POWER5_PME_PM_LSU0_BUSY_REJECT ] = { 117, 115, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU_REJECT_ERAT_MISS ] = { 145, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = { -1, -1, -1, 143, -1, -1 },
+ [ POWER5_PME_PM_DATA_FROM_L375_SHR ] = { -1, -1, 10, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU0_FMOV_FEST ] = { -1, -1, 31, 36, -1, -1 },
+ [ POWER5_PME_PM_PTEG_FROM_L25_MOD ] = { -1, 181, 153, -1, -1, -1 },
+ [ POWER5_PME_PM_LD_REF_L1_LSU0 ] = { -1, -1, 103, 107, -1, -1 },
+ [ POWER5_PME_PM_THRD_PRIO_7_CYC ] = { 209, 203, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU1_FLUSH_SRQ ] = { 131, 129, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SC_RCST_DISP ] = { 101, 99, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_CMPLU_STALL_DIV ] = { -1, -1, -1, 7, -1, -1 },
+ [ POWER5_PME_PM_MEM_RQ_DISP_Q12to15 ] = { -1, -1, 121, 126, -1, -1 },
+ [ POWER5_PME_PM_INST_FROM_L375_SHR ] = { -1, -1, 58, -1, -1, -1 },
+ [ POWER5_PME_PM_ST_REF_L1 ] = { -1, -1, 165, -1, -1, -1 },
+ [ POWER5_PME_PM_L3SB_ALL_BUSY ] = { 109, 107, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY ] = { -1, -1, 20, 25, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L275_SHR_CYC ] = { -1, 161, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FAB_HOLDtoNN_EMPTY ] = { 29, 28, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_DATA_FROM_LMEM ] = { -1, 18, 11, -1, -1, -1 },
+ [ POWER5_PME_PM_RUN_CYC ] = { 190, -1, -1, -1, -1, 0 },
+ [ POWER5_PME_PM_PTEG_FROM_RMEM ] = { 189, -1, -1, 165, -1, -1 },
+ [ POWER5_PME_PM_L2SC_RCLD_DISP ] = { 99, 97, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU0_LDF ] = { -1, -1, 105, 109, -1, -1 },
+ [ POWER5_PME_PM_LSU_LRQ_S0_VALID ] = { 144, 143, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_PMC3_OVERFLOW ] = { -1, -1, -1, 162, -1, -1 },
+ [ POWER5_PME_PM_MRK_IMR_RELOAD ] = { 173, 173, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_GRP_TIMEO ] = { -1, -1, -1, 148, -1, -1 },
+ [ POWER5_PME_PM_ST_MISS_L1 ] = { -1, -1, 164, 171, -1, -1 },
+ [ POWER5_PME_PM_STOP_COMPLETION ] = { -1, -1, 163, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU_BUSY_REJECT ] = { 139, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_ISLB_MISS ] = { 80, 78, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_CYC ] = { 12, 15, 6, 12, -1, -1 },
+ [ POWER5_PME_PM_THRD_ONE_RUN_CYC ] = { 202, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_GRP_BR_REDIR_NONSPEC ] = { 64, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU1_SRQ_STFWD ] = { 138, 136, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L3SC_MOD_INV ] = { -1, -1, 97, 101, -1, -1 },
+ [ POWER5_PME_PM_L2_PREF ] = { -1, -1, 87, 91, -1, -1 },
+ [ POWER5_PME_PM_GCT_NOSLOT_BR_MPRED ] = { -1, -1, -1, 51, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L25_MOD ] = { -1, 159, 129, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SB_MOD_INV ] = { -1, -1, 71, 75, -1, -1 },
+ [ POWER5_PME_PM_L2SB_ST_REQ ] = { 97, 95, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_L1_RELOAD_VALID ] = { -1, -1, 138, 149, -1, -1 },
+ [ POWER5_PME_PM_L3SB_HIT ] = { -1, -1, 92, 96, -1, -1 },
+ [ POWER5_PME_PM_L2SB_SHR_MOD ] = { 96, 94, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_EE_OFF_EXT_INT ] = { -1, -1, 16, 20, -1, -1 },
+ [ POWER5_PME_PM_1PLUS_PPC_CMPL ] = { 2, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SC_SHR_MOD ] = { 104, 102, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_PMC6_OVERFLOW ] = { -1, -1, 152, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU_LRQ_FULL_CYC ] = { -1, -1, 116, 120, -1, -1 },
+ [ POWER5_PME_PM_IC_PREF_INSTALL ] = { -1, -1, 54, 58, -1, -1 },
+ [ POWER5_PME_PM_TLB_MISS ] = { 210, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_GCT_FULL_CYC ] = { 61, 60, -1, 52, -1, -1 },
+ [ POWER5_PME_PM_FXU_BUSY ] = { -1, 57, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L3_CYC ] = { -1, 166, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU_REJECT_LMQ_FULL ] = { -1, 144, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU_SRQ_S0_ALLOC ] = { 147, 146, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_GRP_MRK ] = { 70, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_INST_FROM_L25_SHR ] = { 77, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU1_FIN ] = { -1, -1, 35, 40, -1, -1 },
+ [ POWER5_PME_PM_DC_PREF_STREAM_ALLOC ] = { -1, -1, 14, 18, -1, -1 },
+ [ POWER5_PME_PM_BR_MPRED_TA ] = { -1, -1, 2, 3, -1, -1 },
+ [ POWER5_PME_PM_CRQ_FULL_CYC ] = { -1, -1, 5, 11, -1, -1 },
+ [ POWER5_PME_PM_L2SA_RCLD_DISP ] = { 83, 81, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_SNOOP_WR_RETRY_QFULL ] = { -1, -1, 161, 169, -1, -1 },
+ [ POWER5_PME_PM_MRK_DTLB_REF_4K ] = { 170, 171, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU_SRQ_S0_VALID ] = { 148, 147, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU0_FLUSH_LRQ ] = { 119, 117, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_INST_FROM_L275_MOD ] = { -1, -1, -1, 61, -1, -1 },
+ [ POWER5_PME_PM_GCT_EMPTY_CYC ] = { -1, 195, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LARX_LSU0 ] = { 115, 113, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_THRD_PRIO_DIFF_5or6_CYC ] = { -1, -1, 174, 180, -1, -1 },
+ [ POWER5_PME_PM_SNOOP_RETRY_1AHEAD ] = { 195, 189, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU1_FSQRT ] = { 49, 48, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { 177, 176, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_FPU_FIN ] = { -1, -1, 136, -1, -1, -1 },
+ [ POWER5_PME_PM_THRD_PRIO_5_CYC ] = { 207, 201, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_LMEM ] = { -1, 167, 133, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU1_FRSP_FCONV ] = { -1, -1, 37, 42, -1, -1 },
+ [ POWER5_PME_PM_SNOOP_TLBIE ] = { 196, 190, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L3SB_SNOOP_RETRY ] = { -1, -1, 95, 99, -1, -1 },
+ [ POWER5_PME_PM_FAB_VBYPASS_EMPTY ] = { -1, -1, 23, 28, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L275_MOD ] = { 162, -1, -1, 136, -1, -1 },
+ [ POWER5_PME_PM_6INST_CLB_CYC ] = { 7, 6, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SB_RCST_DISP ] = { 93, 91, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FLUSH ] = { -1, -1, 26, 31, -1, -1 },
+ [ POWER5_PME_PM_L2SC_MOD_INV ] = { -1, -1, 79, 83, -1, -1 },
+ [ POWER5_PME_PM_FPU_DENORM ] = { 54, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L3SC_HIT ] = { -1, -1, 96, 100, -1, -1 },
+ [ POWER5_PME_PM_SNOOP_WR_RETRY_RQ ] = { 197, 191, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU1_REJECT_SRQ ] = { 137, 135, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_IC_PREF_REQ ] = { 71, 69, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L3SC_ALL_BUSY ] = { 112, 110, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_GRP_IC_MISS ] = { -1, -1, -1, 147, -1, -1 },
+ [ POWER5_PME_PM_GCT_NOSLOT_IC_MISS ] = { -1, 59, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L3 ] = { 163, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_GCT_NOSLOT_SRQ_FULL ] = { -1, -1, 46, -1, -1, -1 },
+ [ POWER5_PME_PM_THRD_SEL_OVER_ISU_HOLD ] = { -1, -1, 180, 186, -1, -1 },
+ [ POWER5_PME_PM_CMPLU_STALL_DCACHE_MISS ] = { -1, 10, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L3SA_MOD_INV ] = { -1, -1, 89, 93, -1, -1 },
+ [ POWER5_PME_PM_LSU_FLUSH_LRQ ] = { -1, 138, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_THRD_PRIO_2_CYC ] = { 204, 198, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU_FLUSH_SRQ ] = { 141, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { -1, -1, 149, 161, -1, -1 },
+ [ POWER5_PME_PM_L3SA_REF ] = { 108, 106, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL ] = { -1, -1, 84, 88, -1, -1 },
+ [ POWER5_PME_PM_FPU0_STALL3 ] = { 43, 42, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_GPR_MAP_FULL_CYC ] = { -1, -1, 48, 53, -1, -1 },
+ [ POWER5_PME_PM_TB_BIT_TRANS ] = { 201, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_LSU_FLUSH_LRQ ] = { -1, -1, 147, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU0_STF ] = { 44, 43, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_DTLB_MISS ] = { -1, -1, 135, 145, -1, -1 },
+ [ POWER5_PME_PM_FPU1_FMA ] = { 48, 47, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SA_MOD_TAG ] = { 82, 80, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU1_FLUSH_ULD ] = { 132, 130, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_LSU0_FLUSH_UST ] = { -1, -1, 141, 152, -1, -1 },
+ [ POWER5_PME_PM_MRK_INST_FIN ] = { -1, -1, 137, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU0_FULL_CYC ] = { 41, 40, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU_LRQ_S0_ALLOC ] = { 143, 142, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_LSU1_FLUSH_ULD ] = { -1, -1, 145, 156, -1, -1 },
+ [ POWER5_PME_PM_MRK_DTLB_REF ] = { 213, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_BR_UNCOND ] = { 9, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_THRD_SEL_OVER_L2MISS ] = { -1, -1, 181, 187, -1, -1 },
+ [ POWER5_PME_PM_L2SB_SHR_INV ] = { -1, -1, 77, 81, -1, -1 },
+ [ POWER5_PME_PM_MEM_LO_PRIO_WR_CMPL ] = { -1, -1, 122, 127, -1, -1 },
+ [ POWER5_PME_PM_L3SC_MOD_TAG ] = { 113, 111, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_ST_MISS_L1 ] = { 180, 179, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_GRP_DISP_SUCCESS ] = { -1, -1, 51, -1, -1, -1 },
+ [ POWER5_PME_PM_THRD_PRIO_DIFF_1or2_CYC ] = { -1, -1, 172, 178, -1, -1 },
+ [ POWER5_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { -1, -1, 52, 56, -1, -1 },
+ [ POWER5_PME_PM_MEM_WQ_DISP_Q8to15 ] = { -1, -1, 127, 132, -1, -1 },
+ [ POWER5_PME_PM_FPU0_SINGLE ] = { 42, 41, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU_DERAT_MISS ] = { -1, 137, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_THRD_PRIO_1_CYC ] = { 203, 197, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SC_RCST_DISP_FAIL_OTHER ] = { -1, -1, 83, 87, -1, -1 },
+ [ POWER5_PME_PM_FPU1_FEST ] = { -1, -1, 34, 39, -1, -1 },
+ [ POWER5_PME_PM_FAB_HOLDtoVN_EMPTY ] = { 30, 29, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_SNOOP_RD_RETRY_RQ ] = { 194, 188, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_SNOOP_DCLAIM_RETRY_QFULL ] = { 191, 185, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L25_SHR_CYC ] = { -1, 160, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_ST_CMPL_INT ] = { -1, -1, 150, -1, -1, -1 },
+ [ POWER5_PME_PM_FLUSH_BR_MPRED ] = { -1, -1, 24, 29, -1, -1 },
+ [ POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR ] = { -1, -1, 72, 76, -1, -1 },
+ [ POWER5_PME_PM_FPU_STF ] = { -1, 56, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_CMPLU_STALL_FPU ] = { -1, -1, -1, 9, -1, -1 },
+ [ POWER5_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC ] = { -1, -1, 175, 181, -1, -1 },
+ [ POWER5_PME_PM_GCT_NOSLOT_CYC ] = { 60, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { -1, -1, 42, -1, -1, -1 },
+ [ POWER5_PME_PM_PTEG_FROM_L35_SHR ] = { 187, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_LSU_FLUSH_UST ] = { -1, -1, 148, -1, -1, -1 },
+ [ POWER5_PME_PM_L3SA_HIT ] = { -1, -1, 88, 92, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L25_SHR ] = { 161, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SB_RCST_DISP_FAIL_ADDR ] = { -1, -1, 74, 78, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L35_SHR ] = { 164, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_IERAT_XLATE_WR ] = { 72, 70, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SA_ST_REQ ] = { 89, 87, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_THRD_SEL_T1 ] = { -1, -1, 183, 189, -1, -1 },
+ [ POWER5_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { -1, -1, 53, 57, -1, -1 },
+ [ POWER5_PME_PM_INST_FROM_LMEM ] = { -1, 77, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU0_1FLOP ] = { 36, 35, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L35_SHR_CYC ] = { -1, 164, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_PTEG_FROM_L2 ] = { 183, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MEM_PW_CMPL ] = { 154, 152, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC ] = { -1, -1, 177, 183, -1, -1 },
+ [ POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER ] = { -1, -1, 73, 77, -1, -1 },
+ [ POWER5_PME_PM_FPU0_FIN ] = { -1, -1, 30, 35, -1, -1 },
+ [ POWER5_PME_PM_MRK_DTLB_MISS_4K ] = { 168, 169, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L3SC_SHR_INV ] = { -1, -1, 98, 102, -1, -1 },
+ [ POWER5_PME_PM_GRP_BR_REDIR ] = { 63, 62, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL ] = { 100, 98, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_LSU_FLUSH_SRQ ] = { -1, -1, -1, 159, -1, -1 },
+ [ POWER5_PME_PM_PTEG_FROM_L275_SHR ] = { -1, -1, 154, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL ] = { 92, 90, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_SNOOP_RD_RETRY_WQ ] = { -1, -1, 160, 168, -1, -1 },
+ [ POWER5_PME_PM_LSU0_NCLD ] = { -1, -1, 106, 110, -1, -1 },
+ [ POWER5_PME_PM_FAB_DCLAIM_RETRIED ] = { -1, -1, 18, 23, -1, -1 },
+ [ POWER5_PME_PM_LSU1_BUSY_REJECT ] = { 128, 126, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FXLS0_FULL_CYC ] = { -1, -1, 40, 45, -1, -1 },
+ [ POWER5_PME_PM_FPU0_FEST ] = { -1, -1, 29, 34, -1, -1 },
+ [ POWER5_PME_PM_DTLB_REF_16M ] = { 25, 24, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR ] = { -1, -1, 80, 84, -1, -1 },
+ [ POWER5_PME_PM_LSU0_REJECT_ERAT_MISS ] = { 123, 121, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_DATA_FROM_L25_MOD ] = { -1, 16, 7, -1, -1, -1 },
+ [ POWER5_PME_PM_GCT_USAGE_60to79_CYC ] = { -1, 61, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_DATA_FROM_L375_MOD ] = { 18, -1, -1, 14, -1, -1 },
+ [ POWER5_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { -1, 141, 115, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU0_REJECT_RELOAD_CDF ] = { 125, 123, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_0INST_FETCH ] = { -1, -1, -1, 0, -1, -1 },
+ [ POWER5_PME_PM_LSU1_REJECT_RELOAD_CDF ] = { 136, 134, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L1_PREF ] = { -1, -1, 61, 65, -1, -1 },
+ [ POWER5_PME_PM_MEM_WQ_DISP_Q0to7 ] = { 158, 156, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = { -1, -1, -1, 141, -1, -1 },
+ [ POWER5_PME_PM_BRQ_FULL_CYC ] = { 8, 7, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_GRP_IC_MISS_NONSPEC ] = { 69, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_PTEG_FROM_L275_MOD ] = { 185, -1, -1, 163, -1, -1 },
+ [ POWER5_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { 176, 175, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L375_SHR_CYC ] = { -1, 165, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU_FLUSH ] = { -1, -1, 109, 113, -1, -1 },
+ [ POWER5_PME_PM_DATA_FROM_L3 ] = { 16, -1, 192, -1, -1, -1 },
+ [ POWER5_PME_PM_INST_FROM_L2 ] = { 76, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_PMC2_OVERFLOW ] = { -1, -1, 151, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU0_DENORM ] = { 37, 36, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU1_FMOV_FEST ] = { -1, -1, 36, 41, -1, -1 },
+ [ POWER5_PME_PM_INST_FETCH_CYC ] = { 75, 73, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU_LDF ] = { -1, -1, -1, 115, -1, -1 },
+ [ POWER5_PME_PM_INST_DISP ] = { -1, -1, 56, 60, -1, -1 },
+ [ POWER5_PME_PM_DATA_FROM_L25_SHR ] = { 14, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L1_DCACHE_RELOAD_VALID ] = { -1, -1, 60, 64, -1, -1 },
+ [ POWER5_PME_PM_MEM_WQ_DISP_DCLAIM ] = { -1, -1, 128, 133, -1, -1 },
+ [ POWER5_PME_PM_FPU_FULL_CYC ] = { 57, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_GRP_ISSUED ] = { 172, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_THRD_PRIO_3_CYC ] = { 205, 199, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU_FMA ] = { -1, 54, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_INST_FROM_L35_MOD ] = { -1, 76, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_CRU_FIN ] = { -1, -1, -1, 134, -1, -1 },
+ [ POWER5_PME_PM_SNOOP_WR_RETRY_WQ ] = { -1, -1, 162, 170, -1, -1 },
+ [ POWER5_PME_PM_CMPLU_STALL_REJECT ] = { -1, -1, -1, 10, -1, -1 },
+ [ POWER5_PME_PM_LSU1_REJECT_ERAT_MISS ] = { 134, 132, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_FXU_FIN ] = { -1, 58, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SB_RCST_DISP_FAIL_OTHER ] = { -1, -1, 75, 79, -1, -1 },
+ [ POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY ] = { 103, 101, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_PMC4_OVERFLOW ] = { 181, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L3SA_SNOOP_RETRY ] = { -1, -1, 91, 95, -1, -1 },
+ [ POWER5_PME_PM_PTEG_FROM_L35_MOD ] = { -1, 182, 155, -1, -1, -1 },
+ [ POWER5_PME_PM_INST_FROM_L25_MOD ] = { -1, 75, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_THRD_SMT_HANG ] = { -1, -1, 184, 190, -1, -1 },
+ [ POWER5_PME_PM_CMPLU_STALL_ERAT_MISS ] = { -1, -1, -1, 8, -1, -1 },
+ [ POWER5_PME_PM_L3SA_MOD_TAG ] = { 107, 105, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FLUSH_SYNC ] = { -1, -1, 28, 33, -1, -1 },
+ [ POWER5_PME_PM_INST_FROM_L2MISS ] = { 212, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SC_ST_HIT ] = { -1, -1, 86, 90, -1, -1 },
+ [ POWER5_PME_PM_MEM_RQ_DISP_Q8to11 ] = { 150, 148, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_GRP_DISP ] = { 171, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SB_MOD_TAG ] = { 90, 88, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_CLB_EMPTY_CYC ] = { -1, -1, 169, 175, -1, -1 },
+ [ POWER5_PME_PM_L2SB_ST_HIT ] = { -1, -1, 78, 82, -1, -1 },
+ [ POWER5_PME_PM_MEM_NONSPEC_RD_CANCEL ] = { -1, -1, 125, 130, -1, -1 },
+ [ POWER5_PME_PM_BR_PRED_CR_TA ] = { -1, -1, -1, 5, -1, -1 },
+ [ POWER5_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { -1, -1, 140, 151, -1, -1 },
+ [ POWER5_PME_PM_MRK_LSU_FLUSH_ULD ] = { -1, -1, -1, 160, -1, -1 },
+ [ POWER5_PME_PM_INST_DISP_ATTEMPT ] = { 74, 72, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_INST_FROM_RMEM ] = { -1, -1, -1, 63, -1, -1 },
+ [ POWER5_PME_PM_ST_REF_L1_LSU0 ] = { -1, -1, 166, 172, -1, -1 },
+ [ POWER5_PME_PM_LSU0_DERAT_MISS ] = { 118, 116, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SB_RCLD_DISP ] = { 91, 89, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU_STALL3 ] = { -1, 55, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_BR_PRED_CR ] = { -1, -1, 3, 4, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L2 ] = { 160, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU0_FLUSH_SRQ ] = { 120, 118, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FAB_PNtoNN_DIRECT ] = { 33, 32, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_IOPS_CMPL ] = { 73, 71, 55, 59, -1, -1 },
+ [ POWER5_PME_PM_L2SC_SHR_INV ] = { -1, -1, 85, 89, -1, -1 },
+ [ POWER5_PME_PM_L2SA_RCST_DISP_FAIL_OTHER ] = { -1, -1, 67, 71, -1, -1 },
+ [ POWER5_PME_PM_L2SA_RCST_DISP ] = { 85, 83, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_SNOOP_RETRY_AB_COLLISION ] = { -1, -1, -1, 194, -1, -1 },
+ [ POWER5_PME_PM_FAB_PNtoVN_SIDECAR ] = { -1, -1, 22, 27, -1, -1 },
+ [ POWER5_PME_PM_LSU_LMQ_S0_ALLOC ] = { -1, -1, 113, 118, -1, -1 },
+ [ POWER5_PME_PM_LSU0_REJECT_LMQ_FULL ] = { 124, 122, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_SNOOP_PW_RETRY_RQ ] = { 192, 186, -1, 196, -1, -1 },
+ [ POWER5_PME_PM_DTLB_REF ] = { -1, 63, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_PTEG_FROM_L3 ] = { 186, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY ] = { -1, -1, 19, 24, -1, -1 },
+ [ POWER5_PME_PM_LSU_SRQ_EMPTY_CYC ] = { -1, -1, -1, 122, -1, -1 },
+ [ POWER5_PME_PM_FPU1_STF ] = { 53, 52, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU_LMQ_S0_VALID ] = { -1, -1, 114, 119, -1, -1 },
+ [ POWER5_PME_PM_GCT_USAGE_00to59_CYC ] = { 62, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_DATA_FROM_L2MISS ] = { -1, -1, 187, -1, -1, -1 },
+ [ POWER5_PME_PM_GRP_DISP_BLK_SB_CYC ] = { -1, -1, 50, 54, -1, -1 },
+ [ POWER5_PME_PM_FPU_FMOV_FEST ] = { -1, -1, 38, -1, -1, -1 },
+ [ POWER5_PME_PM_XER_MAP_FULL_CYC ] = { 211, 204, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FLUSH_SB ] = { -1, -1, 27, 32, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L375_SHR ] = { -1, -1, 132, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_GRP_CMPL ] = { -1, -1, -1, 146, -1, -1 },
+ [ POWER5_PME_PM_SUSPENDED ] = { 200, 194, 168, 174, -1, -1 },
+ [ POWER5_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC ] = { 68, 205, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_SNOOP_RD_RETRY_QFULL ] = { 193, 187, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L3SB_MOD_INV ] = { -1, -1, 93, 97, -1, -1 },
+ [ POWER5_PME_PM_DATA_FROM_L35_SHR ] = { 17, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LD_MISS_L1_LSU1 ] = { -1, -1, 102, 105, -1, -1 },
+ [ POWER5_PME_PM_STCX_FAIL ] = { 198, 192, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_DC_PREF_DST ] = { -1, -1, 13, 17, -1, -1 },
+ [ POWER5_PME_PM_GRP_DISP ] = { -1, 64, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR ] = { -1, -1, 64, 68, -1, -1 },
+ [ POWER5_PME_PM_FPU0_FPSCR ] = { -1, -1, 32, 37, -1, -1 },
+ [ POWER5_PME_PM_DATA_FROM_L2 ] = { 13, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU1_DENORM ] = { 46, 45, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU_1FLOP ] = { 56, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER ] = { -1, -1, 81, 85, -1, -1 },
+ [ POWER5_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL ] = { 102, 100, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU0_FSQRT ] = { 40, 39, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LD_REF_L1 ] = { -1, -1, -1, 106, -1, -1 },
+ [ POWER5_PME_PM_INST_FROM_L1 ] = { -1, 74, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_TLBIE_HELD ] = { -1, -1, 186, 191, -1, -1 },
+ [ POWER5_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { -1, -1, 117, 121, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L25_MOD_CYC ] = { -1, -1, -1, 135, -1, -1 },
+ [ POWER5_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { -1, -1, 144, 155, -1, -1 },
+ [ POWER5_PME_PM_MEM_RQ_DISP_Q0to3 ] = { 155, 153, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_ST_REF_L1_LSU1 ] = { -1, -1, 167, 173, -1, -1 },
+ [ POWER5_PME_PM_MRK_LD_MISS_L1 ] = { 175, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L1_WRITE_CYC ] = { -1, -1, 62, 66, -1, -1 },
+ [ POWER5_PME_PM_L2SC_ST_REQ ] = { 105, 103, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_CMPLU_STALL_FDIV ] = { -1, 11, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_THRD_SEL_OVER_CLB_EMPTY ] = { -1, -1, 178, 184, -1, -1 },
+ [ POWER5_PME_PM_BR_MPRED_CR ] = { -1, -1, 1, 2, -1, -1 },
+ [ POWER5_PME_PM_L3SB_MOD_TAG ] = { 110, 108, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L2MISS ] = { -1, -1, 188, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU_REJECT_SRQ ] = { 146, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LD_MISS_L1 ] = { -1, -1, 100, -1, -1, -1 },
+ [ POWER5_PME_PM_INST_FROM_PREF ] = { -1, -1, 59, -1, -1, -1 },
+ [ POWER5_PME_PM_DC_INV_L2 ] = { -1, -1, 12, 16, -1, -1 },
+ [ POWER5_PME_PM_STCX_PASS ] = { 199, 193, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU_SRQ_FULL_CYC ] = { -1, -1, 118, 123, -1, -1 },
+ [ POWER5_PME_PM_FPU_FIN ] = { -1, -1, -1, 44, -1, -1 },
+ [ POWER5_PME_PM_L2SA_SHR_MOD ] = { 88, 86, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU_SRQ_STFWD ] = { 149, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_0INST_CLB_CYC ] = { 0, 0, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FXU0_FIN ] = { -1, -1, 43, 48, -1, -1 },
+ [ POWER5_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL ] = { 94, 92, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = { -1, 196, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_PMC5_OVERFLOW ] = { 182, -1, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_FPU0_FDIV ] = { 38, 37, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_PTEG_FROM_L375_SHR ] = { -1, -1, 156, -1, -1, -1 },
+ [ POWER5_PME_PM_LD_REF_L1_LSU1 ] = { -1, -1, 104, 108, -1, -1 },
+ [ POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY ] = { 87, 85, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_HV_CYC ] = { -1, 68, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_THRD_PRIO_DIFF_0_CYC ] = { -1, -1, 171, 177, -1, -1 },
+ [ POWER5_PME_PM_LR_CTR_MAP_FULL_CYC ] = { 116, 114, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L3SB_SHR_INV ] = { -1, -1, 94, 98, -1, -1 },
+ [ POWER5_PME_PM_DATA_FROM_RMEM ] = { 19, -1, -1, 15, -1, -1 },
+ [ POWER5_PME_PM_DATA_FROM_L275_MOD ] = { 15, -1, -1, 13, -1, -1 },
+ [ POWER5_PME_PM_LSU0_REJECT_SRQ ] = { 126, 124, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU1_DERAT_MISS ] = { 129, 127, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_MRK_LSU_FIN ] = { -1, -1, -1, 158, -1, -1 },
+ [ POWER5_PME_PM_DTLB_MISS_16M ] = { 23, 22, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_LSU0_FLUSH_UST ] = { 122, 120, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SC_MOD_TAG ] = { 98, 96, -1, -1, -1, -1 },
+ [ POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY ] = { 95, 93, -1, -1, -1, -1 }
+};
+
+static const unsigned long long power5_group_vecs[][POWER5_NUM_GROUP_VEC] = {
+ [ POWER5_PME_PM_LSU_REJECT_RELOAD_CDF ] = {
+ 0x0000000000040000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU1_SINGLE ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000400000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L3SB_REF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000001000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRD_PRIO_DIFF_3or4_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000040000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_INST_FROM_L275_SHR ] = {
+ 0x0040000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L375_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0400000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_DTLB_MISS_4K ] = {
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_CLB_FULL_CYC ] = {
+ 0x0000000000000800ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_ST_CMPL ] = {
+ 0x0000000000000000ULL,
+ 0x4000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_FLUSH_LRQ_FULL ] = {
+ 0x0000000008000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L275_SHR ] = {
+ 0x0000000000000000ULL,
+ 0x0080000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_1INST_CLB_CYC ] = {
+ 0x0000000000001000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MEM_SPEC_RD_CANCEL ] = {
+ 0x0000000000000000ULL,
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DTLB_MISS_16M ] = {
+ 0x0000000000000000ULL,
+ 0x0800000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU_FDIV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000004000ULL,
+ 0x0000000000000800ULL
+ },
+ [ POWER5_PME_PM_FPU_SINGLE ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000020000ULL,
+ 0x0000000000000400ULL
+ },
+ [ POWER5_PME_PM_FPU0_FMA ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000800000ULL,
+ 0x0000000000000080ULL
+ },
+ [ POWER5_PME_PM_SLB_MISS ] = {
+ 0x0000010000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU1_FLUSH_LRQ ] = {
+ 0x0000000000400000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SA_ST_HIT ] = {
+ 0x4000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_DTLB_MISS ] = {
+ 0x0000080000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000004ULL
+ },
+ [ POWER5_PME_PM_BR_PRED_TA ] = {
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000020ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L375_MOD_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0400000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_CMPLU_STALL_FXU ] = {
+ 0x0000000040000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_EXT_INT ] = {
+ 0x0000000000000000ULL,
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_LSU1_FLUSH_LRQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU1_LDF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000400000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_ST_GPS ] = {
+ 0x0000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FAB_CMD_ISSUED ] = {
+ 0x0000000000000000ULL,
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU0_SRQ_STFWD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_CR_MAP_FULL_CYC ] = {
+ 0x0000000400000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL ] = {
+ 0x2000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_LSU0_FLUSH_ULD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_FLUSH_SRQ_FULL ] = {
+ 0x0000000008000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FLUSH_IMBAL ] = {
+ 0x0000000000084000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MEM_RQ_DISP_Q16to19 ] = {
+ 0x0000000000000000ULL,
+ 0x0000100000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_DATA_FROM_L35_MOD ] = {
+ 0x0008000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MEM_HI_PRIO_WR_CMPL ] = {
+ 0x0000000000000000ULL,
+ 0x0000080000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU1_FDIV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000100000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU0_FRSP_FCONV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000100000ULL,
+ 0x0000000000000080ULL
+ },
+ [ POWER5_PME_PM_MEM_RQ_DISP ] = {
+ 0x0000000000000000ULL,
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LWSYNC_HELD ] = {
+ 0x0000000000010000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FXU_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000008000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_DSLB_MISS ] = {
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FXLS1_FULL_CYC ] = {
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_DATA_FROM_L275_SHR ] = {
+ 0x0004000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRD_SEL_T0 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000400000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_PTEG_RELOAD_VALID ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_LMQ_LHR_MERGE ] = {
+ 0x0000000000000200ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_STCX_FAIL ] = {
+ 0x0000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_2INST_CLB_CYC ] = {
+ 0x0000000000000008ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FAB_PNtoVN_DIRECT ] = {
+ 0x0000000000000000ULL,
+ 0x0000008000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_PTEG_FROM_L2MISS ] = {
+ 0x0400000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_CMPLU_STALL_LSU ] = {
+ 0x0000000010000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DSLB_MISS ] = {
+ 0x0000000000000000ULL,
+ 0x1800000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_FLUSH_ULD ] = {
+ 0x0000000001000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_PTEG_FROM_LMEM ] = {
+ 0x0400000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_BRU_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0008000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MEM_WQ_DISP_WRITE ] = {
+ 0x0000000000000000ULL,
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L275_MOD_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0200000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU1_NCLD ] = {
+ 0x0000001000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER ] = {
+ 0x1000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_SNOOP_PW_RETRY_WQ_PWQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000100000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPR_MAP_FULL_CYC ] = {
+ 0x0000000800000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU1_FULL_CYC ] = {
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L3SA_ALL_BUSY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000800ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_3INST_CLB_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000010000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MEM_PWQ_DISP_Q2or3 ] = {
+ 0x0000000000000000ULL,
+ 0x0001000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SA_SHR_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000100ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRESH_TIMEO ] = {
+ 0x0000000000000000ULL,
+ 0x0002000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL ] = {
+ 0x4000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRD_SEL_OVER_GCT_IMBAL ] = {
+ 0x0000000000000000ULL,
+ 0x0000000800000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU_FSQRT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000008000ULL,
+ 0x0000000000000800ULL
+ },
+ [ POWER5_PME_PM_MRK_LSU0_FLUSH_LRQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_PMC1_OVERFLOW ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L3SC_SNOOP_RETRY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000002000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_DATA_TABLEWALK_CYC ] = {
+ 0x0000080000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRD_PRIO_6_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000040000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU_FEST ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000004000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FAB_M1toP1_SIDECAR_EMPTY ] = {
+ 0x0000000000000000ULL,
+ 0x0000010000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_RMEM ] = {
+ 0x0000000000000000ULL,
+ 0x0080000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L35_MOD_CYC ] = {
+ 0x0000000000000008ULL,
+ 0x0040000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MEM_PWQ_DISP ] = {
+ 0x0000000000000000ULL,
+ 0x0001000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FAB_P1toM1_SIDECAR_EMPTY ] = {
+ 0x0000000000000000ULL,
+ 0x0000004000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LD_MISS_L1_LSU0 ] = {
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_SNOOP_PARTIAL_RTRY_QFULL ] = {
+ 0x0000000000000000ULL,
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU1_STALL3 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000200000ULL,
+ 0x0000000000000040ULL
+ },
+ [ POWER5_PME_PM_GCT_USAGE_80to99_CYC ] = {
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_WORK_HELD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_INST_CMPL ] = {
+ 0xffffffffffffffffULL,
+ 0xffffffffffffffffULL,
+ 0x000000000001ffffULL
+ },
+ [ POWER5_PME_PM_LSU1_FLUSH_UST ] = {
+ 0x0000000004000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FXU_IDLE ] = {
+ 0x0000000000000000ULL,
+ 0x0000000004000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU0_FLUSH_ULD ] = {
+ 0x0000000002000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU1_REJECT_LMQ_FULL ] = {
+ 0x0000000000020000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_GRP_DISP_REJECT ] = {
+ 0x0000000000000004ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SA_MOD_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000100ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_PTEG_FROM_L25_SHR ] = {
+ 0x0100000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FAB_CMD_RETRIED ] = {
+ 0x0000000000000000ULL,
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L3SA_SHR_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000020ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000002ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SA_RCST_DISP_FAIL_ADDR ] = {
+ 0x2000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL ] = {
+ 0x1000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_PTEG_FROM_L375_MOD ] = {
+ 0x0200000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_LSU1_FLUSH_UST ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_BR_ISSUED ] = {
+ 0x0000000001020000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000020ULL
+ },
+ [ POWER5_PME_PM_MRK_GRP_BR_REDIR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000008000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_EE_OFF ] = {
+ 0x0000000000000000ULL,
+ 0x0000010000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MEM_RQ_DISP_Q4to7 ] = {
+ 0x0000000000000000ULL,
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MEM_FAST_PATH_RD_DISP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_INST_FROM_L3 ] = {
+ 0x0010000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_ITLB_MISS ] = {
+ 0x0000000000100000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000004ULL
+ },
+ [ POWER5_PME_PM_FXU1_BUSY_FXU0_IDLE ] = {
+ 0x0000000000000000ULL,
+ 0x0000000004000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FXLS_FULL_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000008000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_DTLB_REF_4K ] = {
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_GRP_DISP_VALID ] = {
+ 0x0000000000000004ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_FLUSH_UST ] = {
+ 0x0000000001080000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FXU1_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000010000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRD_PRIO_4_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000020000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L35_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0040000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_4INST_CLB_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000010000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DTLB_REF_16M ] = {
+ 0x0000000000000000ULL,
+ 0x1000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_INST_FROM_L375_MOD ] = {
+ 0x0080000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SC_RCST_DISP_FAIL_ADDR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000008ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_GRP_CMPL ] = {
+ 0x0000000000000002ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU1_1FLOP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000001000000ULL,
+ 0x0000000000000100ULL
+ },
+ [ POWER5_PME_PM_FPU_FRSP_FCONV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000008000ULL,
+ 0x0000000000000800ULL
+ },
+ [ POWER5_PME_PM_5INST_CLB_CYC ] = {
+ 0x0000000000000010ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L3SC_REF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000002000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRD_L2MISS_BOTH_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MEM_PW_GATH ] = {
+ 0x0000000000000000ULL,
+ 0x0001000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FAB_PNtoNN_SIDECAR ] = {
+ 0x0000000000000000ULL,
+ 0x0000008000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FAB_DCLAIM_ISSUED ] = {
+ 0x0000000000000000ULL,
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_GRP_IC_MISS ] = {
+ 0x0000008000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_INST_FROM_L35_SHR ] = {
+ 0x0080000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_LMQ_FULL_CYC ] = {
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L2_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0010000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_SRQ_SYNC_CYC ] = {
+ 0x0000000000000100ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU0_BUSY_REJECT ] = {
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_REJECT_ERAT_MISS ] = {
+ 0x0000000000004000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0080000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_DATA_FROM_L375_SHR ] = {
+ 0x0008000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU0_FMOV_FEST ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000080000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_PTEG_FROM_L25_MOD ] = {
+ 0x0100000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LD_REF_L1_LSU0 ] = {
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRD_PRIO_7_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000020000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU1_FLUSH_SRQ ] = {
+ 0x0000000000800000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SC_RCST_DISP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000008ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_CMPLU_STALL_DIV ] = {
+ 0x0000000040000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MEM_RQ_DISP_Q12to15 ] = {
+ 0x0000000000000000ULL,
+ 0x0000100000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_INST_FROM_L375_SHR ] = {
+ 0x0080000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_ST_REF_L1 ] = {
+ 0x0000100000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000008207ULL
+ },
+ [ POWER5_PME_PM_L3SB_ALL_BUSY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000800ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY ] = {
+ 0x0000000000000000ULL,
+ 0x0000004000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L275_SHR_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0280000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FAB_HOLDtoNN_EMPTY ] = {
+ 0x0000000000000000ULL,
+ 0x0000010000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_DATA_FROM_LMEM ] = {
+ 0x0003000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x000000000000000aULL
+ },
+ [ POWER5_PME_PM_RUN_CYC ] = {
+ 0xffffffffffffffffULL,
+ 0xffffffffffffffffULL,
+ 0x000000000001ffffULL
+ },
+ [ POWER5_PME_PM_PTEG_FROM_RMEM ] = {
+ 0x0400000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SC_RCLD_DISP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000004ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU0_LDF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000002400000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_LRQ_S0_VALID ] = {
+ 0x0000000000000080ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_PMC3_OVERFLOW ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_IMR_RELOAD ] = {
+ 0x0000000000000000ULL,
+ 0x0002000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_GRP_TIMEO ] = {
+ 0x0000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_ST_MISS_L1 ] = {
+ 0x0000100000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000004008ULL
+ },
+ [ POWER5_PME_PM_STOP_COMPLETION ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_BUSY_REJECT ] = {
+ 0x0000000000001000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_ISLB_MISS ] = {
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_CYC ] = {
+ 0x0000000020000003ULL,
+ 0x0000001000000000ULL,
+ 0x000000000001f010ULL
+ },
+ [ POWER5_PME_PM_THRD_ONE_RUN_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_GRP_BR_REDIR_NONSPEC ] = {
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU1_SRQ_STFWD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L3SC_MOD_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000080ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2_PREF ] = {
+ 0x0000000000003000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000010ULL
+ },
+ [ POWER5_PME_PM_GCT_NOSLOT_BR_MPRED ] = {
+ 0x0000000000000020ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L25_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0010000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SB_MOD_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000200ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SB_ST_REQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000002ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_L1_RELOAD_VALID ] = {
+ 0x0000000000000000ULL,
+ 0x0008000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L3SB_HIT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000001000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SB_SHR_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000200ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_EE_OFF_EXT_INT ] = {
+ 0x0000000000000000ULL,
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_1PLUS_PPC_CMPL ] = {
+ 0x0000000000000002ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SC_SHR_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000400ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_PMC6_OVERFLOW ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_LRQ_FULL_CYC ] = {
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_IC_PREF_INSTALL ] = {
+ 0x0000004000000800ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_TLB_MISS ] = {
+ 0x0000010000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000008000ULL
+ },
+ [ POWER5_PME_PM_GCT_FULL_CYC ] = {
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FXU_BUSY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000004000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L3_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0040000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_REJECT_LMQ_FULL ] = {
+ 0x0000000000004000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_SRQ_S0_ALLOC ] = {
+ 0x0000000000000100ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_GRP_MRK ] = {
+ 0x0000000010000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_INST_FROM_L25_SHR ] = {
+ 0x0040000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU1_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000010000ULL,
+ 0x0000000000000500ULL
+ },
+ [ POWER5_PME_PM_DC_PREF_STREAM_ALLOC ] = {
+ 0x0000000000000400ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_BR_MPRED_TA ] = {
+ 0x0000010000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_CRQ_FULL_CYC ] = {
+ 0x0000000400000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SA_RCLD_DISP ] = {
+ 0x1000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_SNOOP_WR_RETRY_QFULL ] = {
+ 0x0000000000000000ULL,
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DTLB_REF_4K ] = {
+ 0x0000000000000000ULL,
+ 0x1000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_SRQ_S0_VALID ] = {
+ 0x0000000000000100ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU0_FLUSH_LRQ ] = {
+ 0x0000000000400000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_INST_FROM_L275_MOD ] = {
+ 0x0040000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_GCT_EMPTY_CYC ] = {
+ 0x0000000000000002ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LARX_LSU0 ] = {
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRD_PRIO_DIFF_5or6_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000040000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_SNOOP_RETRY_1AHEAD ] = {
+ 0x0000000000000000ULL,
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU1_FSQRT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000040000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_LD_MISS_L1_LSU1 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_FPU_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRD_PRIO_5_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_LMEM ] = {
+ 0x0000000000000000ULL,
+ 0x0100000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU1_FRSP_FCONV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000900000ULL,
+ 0x0000000000000080ULL
+ },
+ [ POWER5_PME_PM_SNOOP_TLBIE ] = {
+ 0x0000000000000000ULL,
+ 0x0000000400000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L3SB_SNOOP_RETRY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000800ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FAB_VBYPASS_EMPTY ] = {
+ 0x0000000000000000ULL,
+ 0x0000004000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L275_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0200000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_6INST_CLB_CYC ] = {
+ 0x0000000000000010ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SB_RCST_DISP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000001ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FLUSH ] = {
+ 0x0001000000040000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SC_MOD_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000400ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU_DENORM ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000010000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L3SC_HIT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000002000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_SNOOP_WR_RETRY_RQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000080000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU1_REJECT_SRQ ] = {
+ 0x0000000000002000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_IC_PREF_REQ ] = {
+ 0x0000004000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000010ULL
+ },
+ [ POWER5_PME_PM_L3SC_ALL_BUSY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000002000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_GRP_IC_MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0008000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_GCT_NOSLOT_IC_MISS ] = {
+ 0x0000000000000020ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L3 ] = {
+ 0x0000000000000000ULL,
+ 0x0040000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_GCT_NOSLOT_SRQ_FULL ] = {
+ 0x0000000000000020ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRD_SEL_OVER_ISU_HOLD ] = {
+ 0x0000000000000000ULL,
+ 0x0000001000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_CMPLU_STALL_DCACHE_MISS ] = {
+ 0x0000000020000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L3SA_MOD_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000020ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_FLUSH_LRQ ] = {
+ 0x0000000000200000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRD_PRIO_2_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_FLUSH_SRQ ] = {
+ 0x0000000000200000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_LSU_SRQ_INST_VALID ] = {
+ 0x0000000000000010ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L3SA_REF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000001000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000010ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU0_STALL3 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000200000ULL,
+ 0x0000000000000040ULL
+ },
+ [ POWER5_PME_PM_GPR_MAP_FULL_CYC ] = {
+ 0x0000000400000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_TB_BIT_TRANS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_LSU_FLUSH_LRQ ] = {
+ 0x0000000008000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU0_STF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000002000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DTLB_MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0800000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU1_FMA ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000800000ULL,
+ 0x0000000000000080ULL
+ },
+ [ POWER5_PME_PM_L2SA_MOD_TAG ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000100ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU1_FLUSH_ULD ] = {
+ 0x0000000002000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_LSU0_FLUSH_UST ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_INST_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0004000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU0_FULL_CYC ] = {
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_LRQ_S0_ALLOC ] = {
+ 0x0000000000000080ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_LSU1_FLUSH_ULD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DTLB_REF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_BR_UNCOND ] = {
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000020ULL
+ },
+ [ POWER5_PME_PM_THRD_SEL_OVER_L2MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0000001000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SB_SHR_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000200ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MEM_LO_PRIO_WR_CMPL ] = {
+ 0x0000000000000000ULL,
+ 0x0000080000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L3SC_MOD_TAG ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000080ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_ST_MISS_L1 ] = {
+ 0x0000000000000000ULL,
+ 0x4004000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_GRP_DISP_SUCCESS ] = {
+ 0x0800000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRD_PRIO_DIFF_1or2_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000020000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = {
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MEM_WQ_DISP_Q8to15 ] = {
+ 0x0000000000000000ULL,
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU0_SINGLE ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000400000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_DERAT_MISS ] = {
+ 0x0000100000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRD_PRIO_1_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SC_RCST_DISP_FAIL_OTHER ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000008ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU1_FEST ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000040000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FAB_HOLDtoVN_EMPTY ] = {
+ 0x0000000000000000ULL,
+ 0x0000004000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_SNOOP_RD_RETRY_RQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_SNOOP_DCLAIM_RETRY_QFULL ] = {
+ 0x0000000000000000ULL,
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L25_SHR_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0020000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_ST_CMPL_INT ] = {
+ 0x0000000000000000ULL,
+ 0x2000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FLUSH_BR_MPRED ] = {
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR ] = {
+ 0x8000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU_STF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000020000ULL,
+ 0x0000000000002400ULL
+ },
+ [ POWER5_PME_PM_CMPLU_STALL_FPU ] = {
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_GCT_NOSLOT_CYC ] = {
+ 0x0000000000000020ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FXU0_BUSY_FXU1_IDLE ] = {
+ 0x0000000000000000ULL,
+ 0x0000000004000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_PTEG_FROM_L35_SHR ] = {
+ 0x0200000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_LSU_FLUSH_UST ] = {
+ 0x0000000000000000ULL,
+ 0x4000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L3SA_HIT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000001000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L25_SHR ] = {
+ 0x0000000000000000ULL,
+ 0x0020000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SB_RCST_DISP_FAIL_ADDR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000001ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L35_SHR ] = {
+ 0x0000000000000000ULL,
+ 0x0100000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_IERAT_XLATE_WR ] = {
+ 0x0000004000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SA_ST_REQ ] = {
+ 0x4000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRD_SEL_T1 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000400000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = {
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_INST_FROM_LMEM ] = {
+ 0x0020000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU0_1FLOP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000001000000ULL,
+ 0x0000000000000100ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L35_SHR_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0100000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_PTEG_FROM_L2 ] = {
+ 0x0400000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MEM_PW_CMPL ] = {
+ 0x0000000000000000ULL,
+ 0x0001000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER ] = {
+ 0x8000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU0_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000001010000ULL,
+ 0x0000000000000540ULL
+ },
+ [ POWER5_PME_PM_MRK_DTLB_MISS_4K ] = {
+ 0x0000000000000000ULL,
+ 0x0800000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L3SC_SHR_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000080ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_GRP_BR_REDIR ] = {
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000004ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_LSU_FLUSH_SRQ ] = {
+ 0x0000000000004000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_PTEG_FROM_L275_SHR ] = {
+ 0x0100000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL ] = {
+ 0x8000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_SNOOP_RD_RETRY_WQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU0_NCLD ] = {
+ 0x0000001000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FAB_DCLAIM_RETRIED ] = {
+ 0x0000000000000000ULL,
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU1_BUSY_REJECT ] = {
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FXLS0_FULL_CYC ] = {
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU0_FEST ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000040000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_DTLB_REF_16M ] = {
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000004ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU0_REJECT_ERAT_MISS ] = {
+ 0x0000000000010000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_DATA_FROM_L25_MOD ] = {
+ 0x0004000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_GCT_USAGE_60to79_CYC ] = {
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_DATA_FROM_L375_MOD ] = {
+ 0x0008000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = {
+ 0x0000000000000200ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU0_REJECT_RELOAD_CDF ] = {
+ 0x0000000000008000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_0INST_FETCH ] = {
+ 0x0020004000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU1_REJECT_RELOAD_CDF ] = {
+ 0x0000000000008000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L1_PREF ] = {
+ 0x0000000000000800ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000010ULL
+ },
+ [ POWER5_PME_PM_MEM_WQ_DISP_Q0to7 ] = {
+ 0x0000000000000000ULL,
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0100000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_BRQ_FULL_CYC ] = {
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_GRP_IC_MISS_NONSPEC ] = {
+ 0x0000008000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_PTEG_FROM_L275_MOD ] = {
+ 0x0100000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_LD_MISS_L1_LSU0 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L375_SHR_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0400000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_FLUSH ] = {
+ 0x0000000006e40000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_DATA_FROM_L3 ] = {
+ 0x0003000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x000000000000000aULL
+ },
+ [ POWER5_PME_PM_INST_FROM_L2 ] = {
+ 0x0020000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_PMC2_OVERFLOW ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU0_DENORM ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000080000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU1_FMOV_FEST ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000080000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_INST_FETCH_CYC ] = {
+ 0x0000000000000400ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_LDF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000020000ULL,
+ 0x0000000000002000ULL
+ },
+ [ POWER5_PME_PM_INST_DISP ] = {
+ 0x0000000000000005ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000002000ULL
+ },
+ [ POWER5_PME_PM_DATA_FROM_L25_SHR ] = {
+ 0x0004000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L1_DCACHE_RELOAD_VALID ] = {
+ 0x0000008000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MEM_WQ_DISP_DCLAIM ] = {
+ 0x0000000000000000ULL,
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU_FULL_CYC ] = {
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_GRP_ISSUED ] = {
+ 0x0000000000000000ULL,
+ 0x0008000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRD_PRIO_3_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000040000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU_FMA ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000004000ULL,
+ 0x0000000000010200ULL
+ },
+ [ POWER5_PME_PM_INST_FROM_L35_MOD ] = {
+ 0x0080000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_CRU_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x2000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_SNOOP_WR_RETRY_WQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000080000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_CMPLU_STALL_REJECT ] = {
+ 0x0000000010000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU1_REJECT_ERAT_MISS ] = {
+ 0x0000000000010000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_FXU_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000001000ULL
+ },
+ [ POWER5_PME_PM_L2SB_RCST_DISP_FAIL_OTHER ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000001ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000010ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_PMC4_OVERFLOW ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L3SA_SNOOP_RETRY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000800ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_PTEG_FROM_L35_MOD ] = {
+ 0x0200000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_INST_FROM_L25_MOD ] = {
+ 0x0040000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRD_SMT_HANG ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_CMPLU_STALL_ERAT_MISS ] = {
+ 0x0000000020000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L3SA_MOD_TAG ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000020ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FLUSH_SYNC ] = {
+ 0x0000000000100000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_INST_FROM_L2MISS ] = {
+ 0x0000000000000400ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SC_ST_HIT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000010ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MEM_RQ_DISP_Q8to11 ] = {
+ 0x0000000000000000ULL,
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_GRP_DISP ] = {
+ 0x0000000000000000ULL,
+ 0x0006000008000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SB_MOD_TAG ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000200ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_CLB_EMPTY_CYC ] = {
+ 0x0000000000000008ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SB_ST_HIT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000002ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MEM_NONSPEC_RD_CANCEL ] = {
+ 0x0000000000000000ULL,
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_BR_PRED_CR_TA ] = {
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_LSU0_FLUSH_SRQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_LSU_FLUSH_ULD ] = {
+ 0x0000000000000000ULL,
+ 0x4000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_INST_DISP_ATTEMPT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000004000ULL
+ },
+ [ POWER5_PME_PM_INST_FROM_RMEM ] = {
+ 0x0010000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_ST_REF_L1_LSU0 ] = {
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU0_DERAT_MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SB_RCLD_DISP ] = {
+ 0x8000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU_STALL3 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000010000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_BR_PRED_CR ] = {
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000020ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L2 ] = {
+ 0x0000000000000000ULL,
+ 0x0010000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU0_FLUSH_SRQ ] = {
+ 0x0000000000800000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FAB_PNtoNN_DIRECT ] = {
+ 0x0000000000000000ULL,
+ 0x0000008000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_IOPS_CMPL ] = {
+ 0x00210488fffa9811ULL,
+ 0x3220041f03a200e0ULL,
+ 0x0000000000010000ULL
+ },
+ [ POWER5_PME_PM_L2SC_SHR_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000400ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SA_RCST_DISP_FAIL_OTHER ] = {
+ 0x2000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SA_RCST_DISP ] = {
+ 0x2000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_SNOOP_RETRY_AB_COLLISION ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FAB_PNtoVN_SIDECAR ] = {
+ 0x0000000000000000ULL,
+ 0x0000008000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_LMQ_S0_ALLOC ] = {
+ 0x0000000000000080ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU0_REJECT_LMQ_FULL ] = {
+ 0x0000000000020000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_SNOOP_PW_RETRY_RQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000100000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_DTLB_REF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_PTEG_FROM_L3 ] = {
+ 0x0800000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY ] = {
+ 0x0000000000000000ULL,
+ 0x0000010000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_SRQ_EMPTY_CYC ] = {
+ 0x0000000000000200ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU1_STF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000002000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_LMQ_S0_VALID ] = {
+ 0x0000000000000080ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_GCT_USAGE_00to59_CYC ] = {
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_DATA_FROM_L2MISS ] = {
+ 0x0002000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_GRP_DISP_BLK_SB_CYC ] = {
+ 0x0000000000000004ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU_FMOV_FEST ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000004000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_XER_MAP_FULL_CYC ] = {
+ 0x0000000800000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FLUSH_SB ] = {
+ 0x0000000000100000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L375_SHR ] = {
+ 0x0000000000000000ULL,
+ 0x0400000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_GRP_CMPL ] = {
+ 0x0000000000000000ULL,
+ 0x0004000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_SUSPENDED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC ] = {
+ 0x0000000040000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_SNOOP_RD_RETRY_QFULL ] = {
+ 0x0000000000000000ULL,
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L3SB_MOD_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_DATA_FROM_L35_SHR ] = {
+ 0x0008000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LD_MISS_L1_LSU1 ] = {
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_STCX_FAIL ] = {
+ 0x0000001000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_DC_PREF_DST ] = {
+ 0x0000000000002000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_GRP_DISP ] = {
+ 0x0800000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR ] = {
+ 0x1000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU0_FPSCR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000200000ULL,
+ 0x0000000000000040ULL
+ },
+ [ POWER5_PME_PM_DATA_FROM_L2 ] = {
+ 0x0000100000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000001ULL
+ },
+ [ POWER5_PME_PM_FPU1_DENORM ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000080000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU_1FLOP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000008000ULL,
+ 0x0000000000010200ULL
+ },
+ [ POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000004ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000008ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU0_FSQRT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000040000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LD_REF_L1 ] = {
+ 0x0000080000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000008207ULL
+ },
+ [ POWER5_PME_PM_INST_FROM_L1 ] = {
+ 0x0010000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000001ULL
+ },
+ [ POWER5_PME_PM_TLBIE_HELD ] = {
+ 0x0000000000010000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_DC_PREF_OUT_OF_STREAMS ] = {
+ 0x0000000000000400ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L25_MOD_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0010000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_LSU1_FLUSH_SRQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MEM_RQ_DISP_Q0to3 ] = {
+ 0x0000000000000000ULL,
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_ST_REF_L1_LSU1 ] = {
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_LD_MISS_L1 ] = {
+ 0x0000000000000000ULL,
+ 0x2000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L1_WRITE_CYC ] = {
+ 0x0000000000008000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SC_ST_REQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000010ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_CMPLU_STALL_FDIV ] = {
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRD_SEL_OVER_CLB_EMPTY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000800000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_BR_MPRED_CR ] = {
+ 0x0000010000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L3SB_MOD_TAG ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_DATA_FROM_L2MISS ] = {
+ 0x0000000800000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_REJECT_SRQ ] = {
+ 0x0000000000040000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LD_MISS_L1 ] = {
+ 0x0000080000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000004008ULL
+ },
+ [ POWER5_PME_PM_INST_FROM_PREF ] = {
+ 0x0010000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_DC_INV_L2 ] = {
+ 0x0800000000080000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_STCX_PASS ] = {
+ 0x0000001000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_SRQ_FULL_CYC ] = {
+ 0x0000000000000100ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0020000000008000ULL,
+ 0x0000000000001800ULL
+ },
+ [ POWER5_PME_PM_L2SA_SHR_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000100ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU_SRQ_STFWD ] = {
+ 0x0000000000000200ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_0INST_CLB_CYC ] = {
+ 0x0000000000000008ULL,
+ 0x0000000800000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FXU0_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000010000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000001ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_PMC5_OVERFLOW ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_FPU0_FDIV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000100000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_PTEG_FROM_L375_SHR ] = {
+ 0x0200000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LD_REF_L1_LSU1 ] = {
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY ] = {
+ 0x4000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_HV_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_THRD_PRIO_DIFF_0_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000020000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LR_CTR_MAP_FULL_CYC ] = {
+ 0x0000000400000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L3SB_SHR_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_DATA_FROM_RMEM ] = {
+ 0x0002000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_DATA_FROM_L275_MOD ] = {
+ 0x0004000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU0_REJECT_SRQ ] = {
+ 0x0000000000002000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU1_DERAT_MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_MRK_LSU_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0002000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_DTLB_MISS_16M ] = {
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_LSU0_FLUSH_UST ] = {
+ 0x0000000004000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SC_MOD_TAG ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000400ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000002ULL,
+ 0x0000000000000000ULL
+ }
+};
+
+static const pme_power_entry_t power5_pe[] = {
[ POWER5_PME_PM_LSU_REJECT_RELOAD_CDF ] = {
.pme_name = "PM_LSU_REJECT_RELOAD_CDF",
+ .pme_code = 0x2c6090,
.pme_short_desc = "LSU reject due to reload CDF or tag update collision",
- .pme_long_desc = "LSU reject due to reload CDF or tag update collision",
- .pme_event_ids = { -1, 145, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000040000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions because of Critical Data Forward. When critical data arrives from the storage system it is formatted and immediately forwarded, bypassing the data cache, to the destination register using the result bus. Any instruction the requires the result bus in the same cycle is rejected. Tag update rejects are caused when an instruction requires access to the Dcache directory or ERAT in the same system when they are being updated. Combined Unit 0 + 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_REJECT_RELOAD_CDF],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_REJECT_RELOAD_CDF]
},
-#define POWER5_PME_PM_FPU1_SINGLE 1
[ POWER5_PME_PM_FPU1_SINGLE ] = {
.pme_name = "PM_FPU1_SINGLE",
+ .pme_code = 0x20e7,
.pme_short_desc = "FPU1 executed single precision instruction",
- .pme_long_desc = "This signal is active for one cycle when fp1 is executing single precision instruction.",
- .pme_event_ids = { 51, 50, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000400000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "FPU1 has executed a single precision instruction.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_SINGLE],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_SINGLE]
},
-#define POWER5_PME_PM_L3SB_REF 2
[ POWER5_PME_PM_L3SB_REF ] = {
.pme_name = "PM_L3SB_REF",
+ .pme_code = 0x701c4,
.pme_short_desc = "L3 slice B references",
- .pme_long_desc = "L3 slice B references",
- .pme_event_ids = { 111, 109, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000001000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice ",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SB_REF],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SB_REF]
},
-#define POWER5_PME_PM_THRD_PRIO_DIFF_3or4_CYC 3
[ POWER5_PME_PM_THRD_PRIO_DIFF_3or4_CYC ] = {
.pme_name = "PM_THRD_PRIO_DIFF_3or4_CYC",
+ .pme_code = 0x430e5,
.pme_short_desc = "Cycles thread priority difference is 3 or 4",
- .pme_long_desc = "Cycles thread priority difference is 3 or 4",
- .pme_event_ids = { -1, -1, 173, 179, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000040000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "Cycles when this thread's priority is higher than the other thread's priority by 3 or 4.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_DIFF_3or4_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_DIFF_3or4_CYC]
},
-#define POWER5_PME_PM_INST_FROM_L275_SHR 4
[ POWER5_PME_PM_INST_FROM_L275_SHR ] = {
.pme_name = "PM_INST_FROM_L275_SHR",
+ .pme_code = 0x322096,
.pme_short_desc = "Instruction fetched from L2.75 shared",
- .pme_long_desc = "Instruction fetched from L2.75 shared",
- .pme_event_ids = { -1, -1, 57, -1, -1, -1 },
- .pme_group_vector = {
- 0x0040000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "An instruction fetch group was fetched with shared (T) data from the L2 on a different module than this processor is located. Fetch groups can contain up to 8 instructions",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L275_SHR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L275_SHR]
},
-#define POWER5_PME_PM_MRK_DATA_FROM_L375_MOD 5
[ POWER5_PME_PM_MRK_DATA_FROM_L375_MOD ] = {
.pme_name = "PM_MRK_DATA_FROM_L375_MOD",
+ .pme_code = 0x1c70a7,
.pme_short_desc = "Marked data loaded from L3.75 modified",
- .pme_long_desc = "Marked data loaded from L3.75 modified",
- .pme_event_ids = { 165, -1, -1, 139, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0400000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on a different module than this processor is located due to a marked load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L375_MOD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L375_MOD]
},
-#define POWER5_PME_PM_DTLB_MISS_4K 6
[ POWER5_PME_PM_DTLB_MISS_4K ] = {
.pme_name = "PM_DTLB_MISS_4K",
+ .pme_code = 0xc40c0,
.pme_short_desc = "Data TLB miss for 4K page",
- .pme_long_desc = "Data TLB miss for 4K page",
- .pme_event_ids = { 24, 23, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000400000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "Data TLB references to 4KB pages that missed the TLB. Page size is determined at TLB reload time.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DTLB_MISS_4K],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DTLB_MISS_4K]
},
-#define POWER5_PME_PM_CLB_FULL_CYC 7
[ POWER5_PME_PM_CLB_FULL_CYC ] = {
.pme_name = "PM_CLB_FULL_CYC",
+ .pme_code = 0x220e5,
.pme_short_desc = "Cycles CLB full",
- .pme_long_desc = "Cycles CLB full",
- .pme_event_ids = { 10, 9, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000800ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "Cycles when both thread's CLB is full.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_CLB_FULL_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CLB_FULL_CYC]
},
-#define POWER5_PME_PM_MRK_ST_CMPL 8
[ POWER5_PME_PM_MRK_ST_CMPL ] = {
.pme_name = "PM_MRK_ST_CMPL",
+ .pme_code = 0x100003,
.pme_short_desc = "Marked store instruction completed",
.pme_long_desc = "A sampled store has completed (data home)",
- .pme_event_ids = { 179, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x4000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_ST_CMPL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_ST_CMPL]
},
-#define POWER5_PME_PM_LSU_FLUSH_LRQ_FULL 9
[ POWER5_PME_PM_LSU_FLUSH_LRQ_FULL ] = {
.pme_name = "PM_LSU_FLUSH_LRQ_FULL",
+ .pme_code = 0x320e7,
.pme_short_desc = "Flush caused by LRQ full",
- .pme_long_desc = "Flush caused by LRQ full",
- .pme_event_ids = { 140, 139, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000008000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "This thread was flushed at dispatch because its Load Request Queue was full. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_FLUSH_LRQ_FULL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_FLUSH_LRQ_FULL]
},
-#define POWER5_PME_PM_MRK_DATA_FROM_L275_SHR 10
[ POWER5_PME_PM_MRK_DATA_FROM_L275_SHR ] = {
.pme_name = "PM_MRK_DATA_FROM_L275_SHR",
+ .pme_code = 0x3c7097,
.pme_short_desc = "Marked data loaded from L2.75 shared",
- .pme_long_desc = "DL1 was reloaded with shared (T) data from the L2 of another MCM due to a marked demand load",
- .pme_event_ids = { -1, -1, 130, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0080000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "The processor's Data Cache was reloaded with shared (T) data from the L2 on a different module than this processor is located due to a marked load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L275_SHR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L275_SHR]
},
-#define POWER5_PME_PM_1INST_CLB_CYC 11
[ POWER5_PME_PM_1INST_CLB_CYC ] = {
.pme_name = "PM_1INST_CLB_CYC",
+ .pme_code = 0x400c1,
.pme_short_desc = "Cycles 1 instruction in CLB",
- .pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.",
- .pme_event_ids = { 1, 1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000001000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_1INST_CLB_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_1INST_CLB_CYC]
},
-#define POWER5_PME_PM_MEM_SPEC_RD_CANCEL 12
[ POWER5_PME_PM_MEM_SPEC_RD_CANCEL ] = {
.pme_name = "PM_MEM_SPEC_RD_CANCEL",
- .pme_short_desc = "Speculative memory read canceled",
- .pme_long_desc = "Speculative memory read canceled",
- .pme_event_ids = { -1, -1, 126, 131, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000400000000000ULL,
- 0x0000000000000000ULL }
+ .pme_code = 0x721e6,
+ .pme_short_desc = "Speculative memory read cancelled",
+ .pme_long_desc = "Speculative memory read cancelled (i.e. cresp = sourced by L2/L3)",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_SPEC_RD_CANCEL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_SPEC_RD_CANCEL]
},
-#define POWER5_PME_PM_MRK_DTLB_MISS_16M 13
[ POWER5_PME_PM_MRK_DTLB_MISS_16M ] = {
.pme_name = "PM_MRK_DTLB_MISS_16M",
+ .pme_code = 0xc40c5,
.pme_short_desc = "Marked Data TLB misses for 16M page",
.pme_long_desc = "Marked Data TLB misses for 16M page",
- .pme_event_ids = { 167, 168, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0800000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DTLB_MISS_16M],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DTLB_MISS_16M]
},
-#define POWER5_PME_PM_FPU_FDIV 14
[ POWER5_PME_PM_FPU_FDIV ] = {
.pme_name = "PM_FPU_FDIV",
+ .pme_code = 0x100088,
.pme_short_desc = "FPU executed FDIV instruction",
- .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when FPU is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs. Combined Unit 0 + Unit 1",
- .pme_event_ids = { 55, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000004000ULL,
- 0x0000000000000800ULL }
+ .pme_long_desc = "The floating point unit has executed a divide instruction. This could be fdiv, fdivs, fdiv., fdivs.. Combined Unit 0 + Unit 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_FDIV],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_FDIV]
},
-#define POWER5_PME_PM_FPU_SINGLE 15
[ POWER5_PME_PM_FPU_SINGLE ] = {
.pme_name = "PM_FPU_SINGLE",
+ .pme_code = 0x102090,
.pme_short_desc = "FPU executed single precision instruction",
- .pme_long_desc = "FPU is executing single precision instruction. Combined Unit 0 + Unit 1",
- .pme_event_ids = { 58, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000020000ULL,
- 0x0000000000000400ULL }
+ .pme_long_desc = "FPU is executing single precision instruction. Combined Unit 0 + Unit 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_SINGLE],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_SINGLE]
},
-#define POWER5_PME_PM_FPU0_FMA 16
[ POWER5_PME_PM_FPU0_FMA ] = {
.pme_name = "PM_FPU0_FMA",
+ .pme_code = 0xc1,
.pme_short_desc = "FPU0 executed multiply-add instruction",
- .pme_long_desc = "This signal is active for one cycle when fp0 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 39, 38, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000800000ULL,
- 0x0000000000000080ULL }
+ .pme_long_desc = "The floating point unit has executed a multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_FMA],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_FMA]
},
-#define POWER5_PME_PM_SLB_MISS 17
[ POWER5_PME_PM_SLB_MISS ] = {
.pme_name = "PM_SLB_MISS",
+ .pme_code = 0x280088,
.pme_short_desc = "SLB misses",
- .pme_long_desc = "SLB misses",
- .pme_event_ids = { -1, 184, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000010000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "Total of all Segment Lookaside Buffer (SLB) misses, Instructions + Data.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_SLB_MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SLB_MISS]
},
-#define POWER5_PME_PM_LSU1_FLUSH_LRQ 18
[ POWER5_PME_PM_LSU1_FLUSH_LRQ ] = {
.pme_name = "PM_LSU1_FLUSH_LRQ",
+ .pme_code = 0xc00c6,
.pme_short_desc = "LSU1 LRQ flushes",
.pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { 130, 128, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000400000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_FLUSH_LRQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_FLUSH_LRQ]
},
-#define POWER5_PME_PM_L2SA_ST_HIT 19
[ POWER5_PME_PM_L2SA_ST_HIT ] = {
.pme_name = "PM_L2SA_ST_HIT",
+ .pme_code = 0x733e0,
.pme_short_desc = "L2 slice A store hits",
- .pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A,B, and C.",
- .pme_event_ids = { -1, -1, 70, 74, -1, -1 },
- .pme_group_vector = {
- 0x4000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A, B, and C.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_ST_HIT],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_ST_HIT]
},
-#define POWER5_PME_PM_DTLB_MISS 20
[ POWER5_PME_PM_DTLB_MISS ] = {
.pme_name = "PM_DTLB_MISS",
+ .pme_code = 0x800c4,
.pme_short_desc = "Data TLB misses",
- .pme_long_desc = "A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.",
- .pme_event_ids = { 22, 21, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000080000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000004ULL }
+ .pme_long_desc = "Data TLB misses, all page sizes.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DTLB_MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DTLB_MISS]
},
-#define POWER5_PME_PM_BR_PRED_TA 21
[ POWER5_PME_PM_BR_PRED_TA ] = {
.pme_name = "PM_BR_PRED_TA",
+ .pme_code = 0x230e3,
.pme_short_desc = "A conditional branch was predicted",
.pme_long_desc = " target prediction",
- .pme_event_ids = { -1, 8, 4, 6, -1, -1 },
- .pme_group_vector = {
- 0x0000020000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000020ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_BR_PRED_TA],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_BR_PRED_TA]
},
-#define POWER5_PME_PM_MRK_DATA_FROM_L375_MOD_CYC 22
[ POWER5_PME_PM_MRK_DATA_FROM_L375_MOD_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L375_MOD_CYC",
+ .pme_code = 0x4c70a7,
.pme_short_desc = "Marked load latency from L3.75 modified",
- .pme_long_desc = "Marked load latency from L3.75 modified",
- .pme_event_ids = { -1, -1, -1, 140, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0400000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L375_MOD_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L375_MOD_CYC]
},
-#define POWER5_PME_PM_CMPLU_STALL_FXU 23
[ POWER5_PME_PM_CMPLU_STALL_FXU ] = {
.pme_name = "PM_CMPLU_STALL_FXU",
+ .pme_code = 0x211099,
.pme_short_desc = "Completion stall caused by FXU instruction",
- .pme_long_desc = "Completion stall caused by FXU instruction",
- .pme_event_ids = { -1, 12, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000040000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point instruction.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_CMPLU_STALL_FXU],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CMPLU_STALL_FXU]
},
-#define POWER5_PME_PM_EXT_INT 24
[ POWER5_PME_PM_EXT_INT ] = {
.pme_name = "PM_EXT_INT",
+ .pme_code = 0x400003,
.pme_short_desc = "External interrupts",
- .pme_long_desc = "An external interrupt occurred",
- .pme_event_ids = { -1, -1, -1, 21, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000400000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "An interrupt due to an external exception occurred",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_EXT_INT],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_EXT_INT]
},
-#define POWER5_PME_PM_MRK_LSU1_FLUSH_LRQ 25
[ POWER5_PME_PM_MRK_LSU1_FLUSH_LRQ ] = {
.pme_name = "PM_MRK_LSU1_FLUSH_LRQ",
+ .pme_code = 0x810c6,
.pme_short_desc = "LSU1 marked LRQ flushes",
.pme_long_desc = "A marked load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { -1, -1, 143, 154, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU1_FLUSH_LRQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU1_FLUSH_LRQ]
},
-#define POWER5_PME_PM_LSU1_LDF 26
[ POWER5_PME_PM_LSU1_LDF ] = {
.pme_name = "PM_LSU1_LDF",
+ .pme_code = 0xc50c4,
.pme_short_desc = "LSU1 executed Floating Point load instruction",
- .pme_long_desc = "A floating point load was executed from LSU unit 1",
- .pme_event_ids = { -1, -1, 107, 111, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000400000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "A floating point load was executed by LSU1",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_LDF],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_LDF]
},
-#define POWER5_PME_PM_MRK_ST_GPS 27
[ POWER5_PME_PM_MRK_ST_GPS ] = {
.pme_name = "PM_MRK_ST_GPS",
+ .pme_code = 0x200003,
.pme_short_desc = "Marked store sent to GPS",
.pme_long_desc = "A sampled store has been sent to the memory subsystem",
- .pme_event_ids = { -1, 178, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x8000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_ST_GPS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_ST_GPS]
},
-#define POWER5_PME_PM_FAB_CMD_ISSUED 28
[ POWER5_PME_PM_FAB_CMD_ISSUED ] = {
.pme_name = "PM_FAB_CMD_ISSUED",
+ .pme_code = 0x700c7,
.pme_short_desc = "Fabric command issued",
- .pme_long_desc = "Fabric command issued",
- .pme_event_ids = { 27, 26, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000002000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "Incremented when a chip issues a command on its SnoopA address bus. Each of the two address busses (SnoopA and SnoopB) is capable of one transaction per fabric cycle (one fabric cycle = 2 cpu cycles in normal 2:1 mode), but each chip can only drive the SnoopA bus, and can only drive one transaction every two fabric cycles (i.e., every four cpu cycles). In MCM-based systems, two chips interleave their accesses to each of the two fabric busses (SnoopA, SnoopB) to reach a peak capability of one transaction per cpu clock cycle. The two chips that drive SnoopB are wired so that the chips refer to the bus as SnoopA but it is connected to the other two chips as SnoopB. Note that this event will only be recorded by the FBC on the chip that sourced the operation. The signal is delivered at FBC speed and the count must be scaled.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_CMD_ISSUED],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_CMD_ISSUED]
},
-#define POWER5_PME_PM_LSU0_SRQ_STFWD 29
[ POWER5_PME_PM_LSU0_SRQ_STFWD ] = {
.pme_name = "PM_LSU0_SRQ_STFWD",
+ .pme_code = 0xc20e0,
.pme_short_desc = "LSU0 SRQ store forwarded",
- .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 0",
- .pme_event_ids = { 127, 125, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 0. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_SRQ_STFWD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_SRQ_STFWD]
},
-#define POWER5_PME_PM_CR_MAP_FULL_CYC 30
[ POWER5_PME_PM_CR_MAP_FULL_CYC ] = {
.pme_name = "PM_CR_MAP_FULL_CYC",
+ .pme_code = 0x100c4,
.pme_short_desc = "Cycles CR logical operation mapper full",
- .pme_long_desc = "The ISU sends a signal indicating that the cr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.",
- .pme_event_ids = { 11, 14, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000400000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "The Conditional Register mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_CR_MAP_FULL_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CR_MAP_FULL_CYC]
},
-#define POWER5_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL 31
[ POWER5_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL ] = {
.pme_name = "PM_L2SA_RCST_DISP_FAIL_RC_FULL",
- .pme_short_desc = "L2 Slice A RC store dispatch attempt failed due to all RC full",
- .pme_long_desc = "L2 Slice A RC store dispatch attempt failed due to all RC full",
- .pme_event_ids = { 86, 84, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x2000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_code = 0x722e0,
+ .pme_short_desc = "L2 slice A RC store dispatch attempt failed due to all RC full",
+ .pme_long_desc = "A Read/Claim dispatch for a store failed because all RC machines are busy.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL]
},
-#define POWER5_PME_PM_MRK_LSU0_FLUSH_ULD 32
[ POWER5_PME_PM_MRK_LSU0_FLUSH_ULD ] = {
.pme_name = "PM_MRK_LSU0_FLUSH_ULD",
+ .pme_code = 0x810c0,
.pme_short_desc = "LSU0 marked unaligned load flushes",
.pme_long_desc = "A marked load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { -1, -1, 142, 153, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU0_FLUSH_ULD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU0_FLUSH_ULD]
},
-#define POWER5_PME_PM_LSU_FLUSH_SRQ_FULL 33
[ POWER5_PME_PM_LSU_FLUSH_SRQ_FULL ] = {
.pme_name = "PM_LSU_FLUSH_SRQ_FULL",
+ .pme_code = 0x330e0,
.pme_short_desc = "Flush caused by SRQ full",
- .pme_long_desc = "Flush caused by SRQ full",
- .pme_event_ids = { -1, -1, 110, 114, -1, -1 },
- .pme_group_vector = {
- 0x0000000008000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "This thread was flushed at dispatch because its Store Request Queue was full. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_FLUSH_SRQ_FULL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_FLUSH_SRQ_FULL]
},
-#define POWER5_PME_PM_FLUSH_IMBAL 34
[ POWER5_PME_PM_FLUSH_IMBAL ] = {
.pme_name = "PM_FLUSH_IMBAL",
+ .pme_code = 0x330e3,
.pme_short_desc = "Flush caused by thread GCT imbalance",
- .pme_long_desc = "Flush caused by thread GCT imbalance",
- .pme_event_ids = { -1, -1, 25, 30, -1, -1 },
- .pme_group_vector = {
- 0x0000000000084000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC 35
+ .pme_long_desc = "This thread has been flushed at dispatch because it is stalled and a GCT imbalance exists. GCT thresholds are set in the TSCR register. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FLUSH_IMBAL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FLUSH_IMBAL]
+ },
+ [ POWER5_PME_PM_MEM_RQ_DISP_Q16to19 ] = {
+ .pme_name = "PM_MEM_RQ_DISP_Q16to19",
+ .pme_code = 0x727e6,
+ .pme_short_desc = "Memory read queue dispatched to queues 16-19",
+ .pme_long_desc = "A memory operation was dispatched to read queue 16,17,18 or 19. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_RQ_DISP_Q16to19],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_RQ_DISP_Q16to19]
+ },
[ POWER5_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC ] = {
.pme_name = "PM_THRD_PRIO_DIFF_minus3or4_CYC",
+ .pme_code = 0x430e1,
.pme_short_desc = "Cycles thread priority difference is -3 or -4",
- .pme_long_desc = "Cycles thread priority difference is -3 or -4",
- .pme_event_ids = { -1, -1, 176, 182, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000080000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_DATA_FROM_L35_MOD 36
+ .pme_long_desc = "Cycles when this thread's priority is lower than the other thread's priority by 3 or 4.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC]
+ },
[ POWER5_PME_PM_DATA_FROM_L35_MOD ] = {
.pme_name = "PM_DATA_FROM_L35_MOD",
+ .pme_code = 0x2c309e,
.pme_short_desc = "Data loaded from L3.5 modified",
- .pme_long_desc = "Data loaded from L3.5 modified",
- .pme_event_ids = { -1, 17, 9, -1, -1, -1 },
- .pme_group_vector = {
- 0x0008000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MEM_HI_PRIO_WR_CMPL 37
+ .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on the same module as this processor is located due to a demand load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_L35_MOD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_L35_MOD]
+ },
[ POWER5_PME_PM_MEM_HI_PRIO_WR_CMPL ] = {
.pme_name = "PM_MEM_HI_PRIO_WR_CMPL",
+ .pme_code = 0x726e6,
.pme_short_desc = "High priority write completed",
- .pme_long_desc = "High priority write completed",
- .pme_event_ids = { 152, 150, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000080000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU1_FDIV 38
+ .pme_long_desc = "A memory write, which was upgraded to high priority, completed. Writes can be upgraded to high priority to ensure that read traffic does not lock out writes. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_HI_PRIO_WR_CMPL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_HI_PRIO_WR_CMPL]
+ },
[ POWER5_PME_PM_FPU1_FDIV ] = {
.pme_name = "PM_FPU1_FDIV",
+ .pme_code = 0xc4,
.pme_short_desc = "FPU1 executed FDIV instruction",
- .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp1 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.",
- .pme_event_ids = { 47, 46, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000100000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MEM_FAST_PATH_RD_CMPL 39
- [ POWER5_PME_PM_MEM_FAST_PATH_RD_CMPL ] = {
- .pme_name = "PM_MEM_FAST_PATH_RD_CMPL",
- .pme_short_desc = "Fast path memory read completed",
- .pme_long_desc = "Fast path memory read completed",
- .pme_event_ids = { 150, 148, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000400000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "FPU1 has executed a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_FDIV],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_FDIV]
},
-#define POWER5_PME_PM_FPU0_FRSP_FCONV 40
[ POWER5_PME_PM_FPU0_FRSP_FCONV ] = {
.pme_name = "PM_FPU0_FRSP_FCONV",
+ .pme_code = 0x10c1,
.pme_short_desc = "FPU0 executed FRSP or FCONV instructions",
- .pme_long_desc = "This signal is active for one cycle when fp0 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { -1, -1, 33, 38, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000100000ULL,
- 0x0000000000000080ULL }
- },
-#define POWER5_PME_PM_MEM_WQ_DISP_BUSY1to7 41
- [ POWER5_PME_PM_MEM_WQ_DISP_BUSY1to7 ] = {
- .pme_name = "PM_MEM_WQ_DISP_BUSY1to7",
- .pme_short_desc = "Memory write queue dispatched with 1-7 queues busy",
- .pme_long_desc = "Memory write queue dispatched with 1-7 queues busy",
- .pme_event_ids = { 158, 156, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000800000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MEM_RQ_DISP 42
+ .pme_long_desc = "FPU0 has executed a frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_FRSP_FCONV],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_FRSP_FCONV]
+ },
[ POWER5_PME_PM_MEM_RQ_DISP ] = {
.pme_name = "PM_MEM_RQ_DISP",
+ .pme_code = 0x701c6,
.pme_short_desc = "Memory read queue dispatched",
- .pme_long_desc = "Memory read queue dispatched",
- .pme_event_ids = { 156, 154, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000200000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LWSYNC_HELD 43
+ .pme_long_desc = "A memory read was dispatched. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_RQ_DISP],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_RQ_DISP]
+ },
[ POWER5_PME_PM_LWSYNC_HELD ] = {
.pme_name = "PM_LWSYNC_HELD",
+ .pme_code = 0x130e0,
.pme_short_desc = "LWSYNC held at dispatch",
- .pme_long_desc = "LWSYNC held at dispatch",
- .pme_event_ids = { -1, -1, 120, 125, -1, -1 },
- .pme_group_vector = {
- 0x0000000000010000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FXU_FIN 44
+ .pme_long_desc = "Cycles a LWSYNC instruction was held at dispatch. LWSYNC instructions are held at dispatch until all previous loads are done and all previous stores have issued. LWSYNC enters the Store Request Queue and is sent to the storage subsystem but does not wait for a response.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LWSYNC_HELD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LWSYNC_HELD]
+ },
[ POWER5_PME_PM_FXU_FIN ] = {
.pme_name = "PM_FXU_FIN",
+ .pme_code = 0x313088,
.pme_short_desc = "FXU produced a result",
- .pme_long_desc = "The fixed point unit (Unit 0 + Unit 1) finished a marked instruction. Instructions that finish may not necessary complete.",
- .pme_event_ids = { -1, 58, 45, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000008000000ULL,
- 0x0000000000001000ULL }
- },
-#define POWER5_PME_PM_DSLB_MISS 45
+ .pme_long_desc = "The fixed point unit (Unit 0 + Unit 1) finished an instruction. Instructions that finish may not necessary complete.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FXU_FIN],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FXU_FIN]
+ },
[ POWER5_PME_PM_DSLB_MISS ] = {
.pme_name = "PM_DSLB_MISS",
+ .pme_code = 0x800c5,
.pme_short_desc = "Data SLB misses",
- .pme_long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve",
- .pme_event_ids = { 21, 20, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000200000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FXLS1_FULL_CYC 46
+ .pme_long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DSLB_MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DSLB_MISS]
+ },
[ POWER5_PME_PM_FXLS1_FULL_CYC ] = {
.pme_name = "PM_FXLS1_FULL_CYC",
+ .pme_code = 0x110c4,
.pme_short_desc = "Cycles FXU1/LS1 queue full",
- .pme_long_desc = "The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped",
- .pme_event_ids = { -1, -1, 41, 46, -1, -1 },
- .pme_group_vector = {
- 0x0000000200000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_DATA_FROM_L275_SHR 47
+ .pme_long_desc = "The issue queue that feeds the Fixed Point unit 1 / Load Store Unit 1 is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FXLS1_FULL_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FXLS1_FULL_CYC]
+ },
[ POWER5_PME_PM_DATA_FROM_L275_SHR ] = {
.pme_name = "PM_DATA_FROM_L275_SHR",
+ .pme_code = 0x3c3097,
.pme_short_desc = "Data loaded from L2.75 shared",
- .pme_long_desc = "DL1 was reloaded with shared (T) data from the L2 of another MCM due to a demand load",
- .pme_event_ids = { -1, -1, 8, -1, -1, -1 },
- .pme_group_vector = {
- 0x0004000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_THRD_SEL_T0 48
+ .pme_long_desc = "The processor's Data Cache was reloaded with shared (T) data from the L2 on a different module than this processor is located due to a demand load. ",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_L275_SHR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_L275_SHR]
+ },
[ POWER5_PME_PM_THRD_SEL_T0 ] = {
.pme_name = "PM_THRD_SEL_T0",
+ .pme_code = 0x410c0,
.pme_short_desc = "Decode selected thread 0",
- .pme_long_desc = "Decode selected thread 0",
- .pme_event_ids = { -1, -1, 182, 188, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000400000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "Thread selection picked thread 0 for decode.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_SEL_T0],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_SEL_T0]
+ },
+ [ POWER5_PME_PM_PTEG_RELOAD_VALID ] = {
+ .pme_name = "PM_PTEG_RELOAD_VALID",
+ .pme_code = 0x830e4,
+ .pme_short_desc = "PTEG reload valid",
+ .pme_long_desc = "A Page Table Entry was loaded into the TLB.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_RELOAD_VALID],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_RELOAD_VALID]
},
-#define POWER5_PME_PM_LSU_LMQ_LHR_MERGE 49
[ POWER5_PME_PM_LSU_LMQ_LHR_MERGE ] = {
.pme_name = "PM_LSU_LMQ_LHR_MERGE",
+ .pme_code = 0xc70e5,
.pme_short_desc = "LMQ LHR merges",
- .pme_long_desc = "A dcache miss occured for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.",
- .pme_event_ids = { -1, -1, 112, 117, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000200ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "A data cache miss occurred for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_LMQ_LHR_MERGE],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_LMQ_LHR_MERGE]
},
-#define POWER5_PME_PM_MRK_STCX_FAIL 50
[ POWER5_PME_PM_MRK_STCX_FAIL ] = {
.pme_name = "PM_MRK_STCX_FAIL",
+ .pme_code = 0x820e6,
.pme_short_desc = "Marked STCX failed",
.pme_long_desc = "A marked stcx (stwcx or stdcx) failed",
- .pme_event_ids = { 178, 177, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x8000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_STCX_FAIL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_STCX_FAIL]
},
-#define POWER5_PME_PM_2INST_CLB_CYC 51
[ POWER5_PME_PM_2INST_CLB_CYC ] = {
.pme_name = "PM_2INST_CLB_CYC",
+ .pme_code = 0x400c2,
.pme_short_desc = "Cycles 2 instructions in CLB",
- .pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.",
- .pme_event_ids = { 3, 2, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000008ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_2INST_CLB_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_2INST_CLB_CYC]
},
-#define POWER5_PME_PM_FAB_PNtoVN_DIRECT 52
[ POWER5_PME_PM_FAB_PNtoVN_DIRECT ] = {
.pme_name = "PM_FAB_PNtoVN_DIRECT",
+ .pme_code = 0x723e7,
.pme_short_desc = "PN to VN beat went straight to its destination",
- .pme_long_desc = "PN to VN beat went straight to its destination",
- .pme_event_ids = { 34, 33, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000008000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "Fabric Data beats that the base chip takes the inbound PN data and passes it through to the outbound VN bus without going into a sidecar. The signal is delivered at FBC speed and the count must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_PNtoVN_DIRECT],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_PNtoVN_DIRECT]
},
-#define POWER5_PME_PM_PTEG_FROM_L2MISS 53
[ POWER5_PME_PM_PTEG_FROM_L2MISS ] = {
.pme_name = "PM_PTEG_FROM_L2MISS",
+ .pme_code = 0x38309b,
.pme_short_desc = "PTEG loaded from L2 miss",
- .pme_long_desc = "PTEG loaded from L2 miss",
- .pme_event_ids = { -1, -1, 189, -1, -1, -1 },
- .pme_group_vector = {
- 0x0400000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "A Page Table Entry was loaded into the TLB but not from the local L2.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_L2MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_L2MISS]
},
-#define POWER5_PME_PM_CMPLU_STALL_LSU 54
[ POWER5_PME_PM_CMPLU_STALL_LSU ] = {
.pme_name = "PM_CMPLU_STALL_LSU",
+ .pme_code = 0x211098,
.pme_short_desc = "Completion stall caused by LSU instruction",
- .pme_long_desc = "Completion stall caused by LSU instruction",
- .pme_event_ids = { -1, 13, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000010000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a load/store instruction.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_CMPLU_STALL_LSU],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CMPLU_STALL_LSU]
},
-#define POWER5_PME_PM_MRK_DSLB_MISS 55
[ POWER5_PME_PM_MRK_DSLB_MISS ] = {
.pme_name = "PM_MRK_DSLB_MISS",
+ .pme_code = 0xc50c7,
.pme_short_desc = "Marked Data SLB misses",
- .pme_long_desc = "Marked Data SLB misses",
- .pme_event_ids = { -1, -1, 134, 144, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x1800000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "A Data SLB miss was caused by a marked instruction.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DSLB_MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DSLB_MISS]
},
-#define POWER5_PME_PM_LSU_FLUSH_ULD 56
[ POWER5_PME_PM_LSU_FLUSH_ULD ] = {
.pme_name = "PM_LSU_FLUSH_ULD",
+ .pme_code = 0x1c0088,
.pme_short_desc = "LRQ unaligned load flushes",
- .pme_long_desc = "A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { 142, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000001000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1). Combined Unit 0 + 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_FLUSH_ULD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_FLUSH_ULD]
},
-#define POWER5_PME_PM_PTEG_FROM_LMEM 57
[ POWER5_PME_PM_PTEG_FROM_LMEM ] = {
.pme_name = "PM_PTEG_FROM_LMEM",
+ .pme_code = 0x283087,
.pme_short_desc = "PTEG loaded from local memory",
- .pme_long_desc = "PTEG loaded from local memory",
- .pme_event_ids = { -1, 183, 157, -1, -1, -1 },
- .pme_group_vector = {
- 0x0400000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "A Page Table Entry was loaded into the TLB from memory attached to the same module this proccessor is located on.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_LMEM],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_LMEM]
},
-#define POWER5_PME_PM_MRK_BRU_FIN 58
[ POWER5_PME_PM_MRK_BRU_FIN ] = {
.pme_name = "PM_MRK_BRU_FIN",
+ .pme_code = 0x200005,
.pme_short_desc = "Marked instruction BRU processing finished",
- .pme_long_desc = "The branch unit finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, 158, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0008000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "The branch unit finished a marked instruction. Instructions that finish may not necessary complete.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_BRU_FIN],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_BRU_FIN]
},
-#define POWER5_PME_PM_MEM_WQ_DISP_WRITE 59
[ POWER5_PME_PM_MEM_WQ_DISP_WRITE ] = {
.pme_name = "PM_MEM_WQ_DISP_WRITE",
+ .pme_code = 0x703c6,
.pme_short_desc = "Memory write queue dispatched due to write",
- .pme_long_desc = "Memory write queue dispatched due to write",
- .pme_event_ids = { 159, 157, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000800000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "A memory write was dispatched to a write queue. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_WQ_DISP_WRITE],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_WQ_DISP_WRITE]
},
-#define POWER5_PME_PM_MRK_DATA_FROM_L275_MOD_CYC 60
[ POWER5_PME_PM_MRK_DATA_FROM_L275_MOD_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L275_MOD_CYC",
+ .pme_code = 0x4c70a3,
.pme_short_desc = "Marked load latency from L2.75 modified",
- .pme_long_desc = "Marked load latency from L2.75 modified",
- .pme_event_ids = { -1, -1, -1, 137, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0200000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L275_MOD_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L275_MOD_CYC]
},
-#define POWER5_PME_PM_LSU1_NCLD 61
[ POWER5_PME_PM_LSU1_NCLD ] = {
.pme_name = "PM_LSU1_NCLD",
+ .pme_code = 0xc50c5,
.pme_short_desc = "LSU1 non-cacheable loads",
- .pme_long_desc = "LSU1 non-cacheable loads",
- .pme_event_ids = { -1, -1, 108, 112, -1, -1 },
- .pme_group_vector = {
- 0x0000001000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "A non-cacheable load was executed by Unit 0.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_NCLD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_NCLD]
},
-#define POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER 62
[ POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER ] = {
.pme_name = "PM_L2SA_RCLD_DISP_FAIL_OTHER",
- .pme_short_desc = "L2 Slice A RC load dispatch attempt failed due to other reasons",
- .pme_long_desc = "L2 Slice A RC load dispatch attempt failed due to other reasons",
- .pme_event_ids = { -1, -1, 65, 69, -1, -1 },
- .pme_group_vector = {
- 0x1000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_code = 0x731e0,
+ .pme_short_desc = "L2 slice A RC load dispatch attempt failed due to other reasons",
+ .pme_long_desc = "A Read/Claim dispatch for a load failed for some reason other than Full or Collision conditions.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER]
},
-#define POWER5_PME_PM_SNOOP_PW_RETRY_WQ_PWQ 63
[ POWER5_PME_PM_SNOOP_PW_RETRY_WQ_PWQ ] = {
.pme_name = "PM_SNOOP_PW_RETRY_WQ_PWQ",
+ .pme_code = 0x717c6,
.pme_short_desc = "Snoop partial-write retry due to collision with active write or partial-write queue",
- .pme_long_desc = "Snoop partial-write retry due to collision with active write or partial-write queue",
- .pme_event_ids = { -1, -1, 159, 167, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000100000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "A snoop request for a partial write to memory was retried because it matched the cache line of an active write or partial write. When this happens the snoop request is retried and the active write is changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_PW_RETRY_WQ_PWQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_PW_RETRY_WQ_PWQ]
},
-#define POWER5_PME_PM_FPR_MAP_FULL_CYC 64
[ POWER5_PME_PM_FPR_MAP_FULL_CYC ] = {
.pme_name = "PM_FPR_MAP_FULL_CYC",
+ .pme_code = 0x100c1,
.pme_short_desc = "Cycles FPR mapper full",
- .pme_long_desc = "The ISU sends a signal indicating that the FPR mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.",
- .pme_event_ids = { 35, 34, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "The floating point unit has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations. ",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPR_MAP_FULL_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPR_MAP_FULL_CYC]
},
-#define POWER5_PME_PM_FPU1_FULL_CYC 65
[ POWER5_PME_PM_FPU1_FULL_CYC ] = {
.pme_name = "PM_FPU1_FULL_CYC",
+ .pme_code = 0x100c7,
.pme_short_desc = "Cycles FPU1 issue queue full",
- .pme_long_desc = "The issue queue for FPU unit 1 cannot accept any more instructions. Issue is stopped",
- .pme_event_ids = { 50, 49, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000200000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "The issue queue for FPU1 cannot accept any more instructions. Dispatch to this issue queue is stopped",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_FULL_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_FULL_CYC]
},
-#define POWER5_PME_PM_L3SA_ALL_BUSY 66
[ POWER5_PME_PM_L3SA_ALL_BUSY ] = {
.pme_name = "PM_L3SA_ALL_BUSY",
+ .pme_code = 0x721e3,
.pme_short_desc = "L3 slice A active for every cycle all CI/CO machines busy",
- .pme_long_desc = "L3 slice A active for every cycle all CI/CO machines busy",
- .pme_event_ids = { 106, 104, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000800ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "Cycles All Castin/Castout machines are busy.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SA_ALL_BUSY],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SA_ALL_BUSY]
},
-#define POWER5_PME_PM_3INST_CLB_CYC 67
[ POWER5_PME_PM_3INST_CLB_CYC ] = {
.pme_name = "PM_3INST_CLB_CYC",
+ .pme_code = 0x400c3,
.pme_short_desc = "Cycles 3 instructions in CLB",
- .pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.",
- .pme_event_ids = { 4, 3, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000010000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SA_SHR_INV 68
+ .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_3INST_CLB_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_3INST_CLB_CYC]
+ },
+ [ POWER5_PME_PM_MEM_PWQ_DISP_Q2or3 ] = {
+ .pme_name = "PM_MEM_PWQ_DISP_Q2or3",
+ .pme_code = 0x734e6,
+ .pme_short_desc = "Memory partial-write queue dispatched to Write Queue 2 or 3",
+ .pme_long_desc = "Memory partial-write queue dispatched to Write Queue 2 or 3. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_PWQ_DISP_Q2or3],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_PWQ_DISP_Q2or3]
+ },
[ POWER5_PME_PM_L2SA_SHR_INV ] = {
.pme_name = "PM_L2SA_SHR_INV",
+ .pme_code = 0x710c0,
.pme_short_desc = "L2 slice A transition from shared to invalid",
- .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.",
- .pme_event_ids = { -1, -1, 69, 73, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000100ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_THRESH_TIMEO 69
+ .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A, B, and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_SHR_INV],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_SHR_INV]
+ },
[ POWER5_PME_PM_THRESH_TIMEO ] = {
.pme_name = "PM_THRESH_TIMEO",
+ .pme_code = 0x30000b,
.pme_short_desc = "Threshold timeout",
.pme_long_desc = "The threshold timer expired",
- .pme_event_ids = { -1, -1, 185, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0002000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRESH_TIMEO],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRESH_TIMEO]
},
-#define POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL 70
[ POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL ] = {
.pme_name = "PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL",
- .pme_short_desc = "L2 Slice A RC dispatch attempt failed due to all CO busy",
- .pme_long_desc = "L2 Slice A RC dispatch attempt failed due to all CO busy",
- .pme_event_ids = { -1, -1, 68, 72, -1, -1 },
- .pme_group_vector = {
- 0x4000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_THRD_SEL_OVER_GCT_IMBAL 71
+ .pme_code = 0x713c0,
+ .pme_short_desc = "L2 slice A RC dispatch attempt failed due to all CO busy",
+ .pme_long_desc = "A Read/Claim dispatch was rejected because all Castout machines were busy.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL]
+ },
[ POWER5_PME_PM_THRD_SEL_OVER_GCT_IMBAL ] = {
.pme_name = "PM_THRD_SEL_OVER_GCT_IMBAL",
- .pme_short_desc = "Thread selection overides caused by GCT imbalance",
- .pme_long_desc = "Thread selection overides caused by GCT imbalance",
- .pme_event_ids = { -1, -1, 179, 185, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000800000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU_FSQRT 72
+ .pme_code = 0x410c4,
+ .pme_short_desc = "Thread selection overrides caused by GCT imbalance",
+ .pme_long_desc = "Thread selection was overridden because of a GCT imbalance.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_SEL_OVER_GCT_IMBAL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_SEL_OVER_GCT_IMBAL]
+ },
[ POWER5_PME_PM_FPU_FSQRT ] = {
.pme_name = "PM_FPU_FSQRT",
+ .pme_code = 0x200090,
.pme_short_desc = "FPU executed FSQRT instruction",
- .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when FPU is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, 53, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000008000ULL,
- 0x0000000000000800ULL }
- },
-#define POWER5_PME_PM_MRK_LSU0_FLUSH_LRQ 73
+ .pme_long_desc = "The floating point unit has executed a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_FSQRT],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_FSQRT]
+ },
[ POWER5_PME_PM_MRK_LSU0_FLUSH_LRQ ] = {
.pme_name = "PM_MRK_LSU0_FLUSH_LRQ",
+ .pme_code = 0x810c2,
.pme_short_desc = "LSU0 marked LRQ flushes",
.pme_long_desc = "A marked load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { -1, -1, 139, 150, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU0_FLUSH_LRQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU0_FLUSH_LRQ]
},
-#define POWER5_PME_PM_PMC1_OVERFLOW 74
[ POWER5_PME_PM_PMC1_OVERFLOW ] = {
.pme_name = "PM_PMC1_OVERFLOW",
+ .pme_code = 0x20000a,
.pme_short_desc = "PMC1 Overflow",
- .pme_long_desc = "PMC1 Overflow",
- .pme_event_ids = { -1, 180, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L3SC_SNOOP_RETRY 75
+ .pme_long_desc = "Overflows from PMC1 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_PMC1_OVERFLOW],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PMC1_OVERFLOW]
+ },
[ POWER5_PME_PM_L3SC_SNOOP_RETRY ] = {
.pme_name = "PM_L3SC_SNOOP_RETRY",
+ .pme_code = 0x731e5,
.pme_short_desc = "L3 slice C snoop retries",
- .pme_long_desc = "L3 slice C snoop retries",
- .pme_event_ids = { -1, -1, 99, 103, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000002000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_DATA_TABLEWALK_CYC 76
+ .pme_long_desc = "Number of times an L3 retried a snoop because it got two in at the same time (one on snp_a, one on snp_b)",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SC_SNOOP_RETRY],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SC_SNOOP_RETRY]
+ },
[ POWER5_PME_PM_DATA_TABLEWALK_CYC ] = {
.pme_name = "PM_DATA_TABLEWALK_CYC",
+ .pme_code = 0x800c7,
.pme_short_desc = "Cycles doing data tablewalks",
- .pme_long_desc = "This signal is asserted every cycle when a tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.",
- .pme_event_ids = { 20, 19, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000080000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_THRD_PRIO_6_CYC 77
+ .pme_long_desc = "Cycles a translation tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_TABLEWALK_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_TABLEWALK_CYC]
+ },
[ POWER5_PME_PM_THRD_PRIO_6_CYC ] = {
.pme_name = "PM_THRD_PRIO_6_CYC",
+ .pme_code = 0x420e5,
.pme_short_desc = "Cycles thread running at priority level 6",
- .pme_long_desc = "Cycles thread running at priority level 6",
- .pme_event_ids = { 208, 202, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000040000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU_FEST 78
+ .pme_long_desc = "Cycles this thread was running at priority level 6.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_6_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_6_CYC]
+ },
[ POWER5_PME_PM_FPU_FEST ] = {
.pme_name = "PM_FPU_FEST",
+ .pme_code = 0x401090,
.pme_short_desc = "FPU executed FEST instruction",
- .pme_long_desc = "This signal is active for one cycle when executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. Combined Unit 0 + Unit 1.",
- .pme_event_ids = { -1, -1, -1, 43, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000004000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FAB_M1toP1_SIDECAR_EMPTY 79
+ .pme_long_desc = "The floating point unit has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. Combined Unit 0 + Unit 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_FEST],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_FEST]
+ },
[ POWER5_PME_PM_FAB_M1toP1_SIDECAR_EMPTY ] = {
.pme_name = "PM_FAB_M1toP1_SIDECAR_EMPTY",
+ .pme_code = 0x702c7,
.pme_short_desc = "M1 to P1 sidecar empty",
- .pme_long_desc = "M1 to P1 sidecar empty",
- .pme_event_ids = { 31, 30, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000010000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_DATA_FROM_RMEM 80
+ .pme_long_desc = "Fabric cycles when the Minus-1 hip/hop sidecars (sidecars for chip to chip data transfer) are empty. The signal is delivered at FBC speed and the count must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_M1toP1_SIDECAR_EMPTY],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_M1toP1_SIDECAR_EMPTY]
+ },
[ POWER5_PME_PM_MRK_DATA_FROM_RMEM ] = {
.pme_name = "PM_MRK_DATA_FROM_RMEM",
+ .pme_code = 0x1c70a1,
.pme_short_desc = "Marked data loaded from remote memory",
- .pme_long_desc = "Marked data loaded from remote memory",
- .pme_event_ids = { 166, -1, -1, 142, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0080000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_DATA_FROM_L35_MOD_CYC 81
+ .pme_long_desc = "The processor's Data Cache was reloaded due to a marked load from memory attached to a different module than this proccessor is located on.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_RMEM],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_RMEM]
+ },
[ POWER5_PME_PM_MRK_DATA_FROM_L35_MOD_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L35_MOD_CYC",
+ .pme_code = 0x4c70a6,
.pme_short_desc = "Marked load latency from L3.5 modified",
- .pme_long_desc = "Marked load latency from L3.5 modified",
- .pme_event_ids = { -1, -1, -1, 138, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000008ULL,
- 0x0040000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MEM_PWQ_DISP 82
+ .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L35_MOD_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L35_MOD_CYC]
+ },
[ POWER5_PME_PM_MEM_PWQ_DISP ] = {
.pme_name = "PM_MEM_PWQ_DISP",
+ .pme_code = 0x704c6,
.pme_short_desc = "Memory partial-write queue dispatched",
- .pme_long_desc = "Memory partial-write queue dispatched",
- .pme_event_ids = { 153, 151, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0001000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FAB_P1toM1_SIDECAR_EMPTY 83
+ .pme_long_desc = "Number of Partial Writes dispatched. The MC provides resources to gather partial cacheline writes (Partial line DMA writes & CI-stores) to up to four different cachelines at a time. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_PWQ_DISP],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_PWQ_DISP]
+ },
[ POWER5_PME_PM_FAB_P1toM1_SIDECAR_EMPTY ] = {
.pme_name = "PM_FAB_P1toM1_SIDECAR_EMPTY",
+ .pme_code = 0x701c7,
.pme_short_desc = "P1 to M1 sidecar empty",
- .pme_long_desc = "P1 to M1 sidecar empty",
- .pme_event_ids = { 32, 31, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000004000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LD_MISS_L1_LSU0 84
+ .pme_long_desc = "Fabric cycles when the Plus-1 hip/hop sidecars (sidecars for chip to chip data transfer) are empty. The signal is delivered at FBC speed and the count must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_P1toM1_SIDECAR_EMPTY],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_P1toM1_SIDECAR_EMPTY]
+ },
[ POWER5_PME_PM_LD_MISS_L1_LSU0 ] = {
.pme_name = "PM_LD_MISS_L1_LSU0",
+ .pme_code = 0xc10c2,
.pme_short_desc = "LSU0 L1 D cache load misses",
- .pme_long_desc = "A load, executing on unit 0, missed the dcache",
- .pme_event_ids = { -1, -1, 101, 104, -1, -1 },
- .pme_group_vector = {
- 0x0000200000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_SNOOP_PARTIAL_RTRY_QFULL 85
+ .pme_long_desc = "Load references that miss the Level 1 Data cache, by unit 0.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LD_MISS_L1_LSU0],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LD_MISS_L1_LSU0]
+ },
[ POWER5_PME_PM_SNOOP_PARTIAL_RTRY_QFULL ] = {
.pme_name = "PM_SNOOP_PARTIAL_RTRY_QFULL",
+ .pme_code = 0x730e6,
.pme_short_desc = "Snoop partial write retry due to partial-write queues full",
- .pme_long_desc = "Snoop partial write retry due to partial-write queues full",
- .pme_event_ids = { -1, -1, 158, 166, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000020000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU1_STALL3 86
+ .pme_long_desc = "A snoop request for a partial write to memory was retried because the write queues that handle partial writes were full. When this happens the active writes are changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_PARTIAL_RTRY_QFULL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_PARTIAL_RTRY_QFULL]
+ },
[ POWER5_PME_PM_FPU1_STALL3 ] = {
.pme_name = "PM_FPU1_STALL3",
+ .pme_code = 0x20e5,
.pme_short_desc = "FPU1 stalled in pipe3",
- .pme_long_desc = "This signal indicates that fp1 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. ",
- .pme_event_ids = { 52, 51, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000200000ULL,
- 0x0000000000000040ULL }
- },
-#define POWER5_PME_PM_GCT_USAGE_80to99_CYC 87
+ .pme_long_desc = "FPU1 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always).",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_STALL3],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_STALL3]
+ },
[ POWER5_PME_PM_GCT_USAGE_80to99_CYC ] = {
.pme_name = "PM_GCT_USAGE_80to99_CYC",
+ .pme_code = 0x30001f,
.pme_short_desc = "Cycles GCT 80-99% full",
- .pme_long_desc = "Cycles GCT 80-99% full",
- .pme_event_ids = { -1, -1, 47, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000040ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_WORK_HELD 88
+ .pme_long_desc = "Cycles when the Global Completion Table has between 80% and 99% of its slots used. The GCT has 20 entries shared between threads",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_GCT_USAGE_80to99_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GCT_USAGE_80to99_CYC]
+ },
[ POWER5_PME_PM_WORK_HELD ] = {
.pme_name = "PM_WORK_HELD",
+ .pme_code = 0x40000c,
.pme_short_desc = "Work held",
.pme_long_desc = "RAS Unit has signaled completion to stop and there are groups waiting to complete",
- .pme_event_ids = { -1, -1, -1, 192, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_WORK_HELD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_WORK_HELD]
+ },
+ [ POWER5_PME_PM_INST_CMPL ] = {
+ .pme_name = "PM_INST_CMPL",
+ .pme_code = 0x100009,
+ .pme_short_desc = "Instructions completed",
+ .pme_long_desc = "Number of PowerPC instructions that completed. ",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_CMPL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_CMPL]
},
-#define POWER5_PME_PM_LSU1_FLUSH_UST 89
[ POWER5_PME_PM_LSU1_FLUSH_UST ] = {
.pme_name = "PM_LSU1_FLUSH_UST",
+ .pme_code = 0xc00c5,
.pme_short_desc = "LSU1 unaligned store flushes",
- .pme_long_desc = "A store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)",
- .pme_event_ids = { 133, 131, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000004000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "A store was flushed from unit 1 because it was unaligned (crossed a 4K boundary)",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_FLUSH_UST],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_FLUSH_UST]
},
-#define POWER5_PME_PM_INST_CMPL 90
- [ POWER5_PME_PM_INST_CMPL ] = {
- .pme_name = "PM_INST_CMPL",
- .pme_short_desc = "Instructions completed",
- .pme_long_desc = "Number of PPC instructions completed. ",
- .pme_event_ids = { 174, 174, 55, 59, 0, -1 },
- .pme_group_vector = {
- 0xffffffffffffffffULL,
- 0xffffffffffffffffULL,
- 0x000000000001ffffULL }
- },
-#define POWER5_PME_PM_FXU_IDLE 91
[ POWER5_PME_PM_FXU_IDLE ] = {
.pme_name = "PM_FXU_IDLE",
+ .pme_code = 0x100012,
.pme_short_desc = "FXU idle",
- .pme_long_desc = "FXU0 and FXU1 are both idle",
- .pme_event_ids = { 59, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000004000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU0_FLUSH_ULD 92
+ .pme_long_desc = "FXU0 and FXU1 are both idle.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FXU_IDLE],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FXU_IDLE]
+ },
[ POWER5_PME_PM_LSU0_FLUSH_ULD ] = {
.pme_name = "PM_LSU0_FLUSH_ULD",
+ .pme_code = 0xc00c0,
.pme_short_desc = "LSU0 unaligned load flushes",
- .pme_long_desc = "A load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { 121, 119, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000002000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU1_REJECT_LMQ_FULL 93
+ .pme_long_desc = "A load was flushed from unit 0 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1)",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_FLUSH_ULD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_FLUSH_ULD]
+ },
[ POWER5_PME_PM_LSU1_REJECT_LMQ_FULL ] = {
.pme_name = "PM_LSU1_REJECT_LMQ_FULL",
+ .pme_code = 0xc60e5,
.pme_short_desc = "LSU1 reject due to LMQ full or missed data coming",
- .pme_long_desc = "LSU1 reject due to LMQ full or missed data coming",
- .pme_event_ids = { 135, 133, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000020000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_GRP_DISP_REJECT 94
+ .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_REJECT_LMQ_FULL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_REJECT_LMQ_FULL]
+ },
[ POWER5_PME_PM_GRP_DISP_REJECT ] = {
.pme_name = "PM_GRP_DISP_REJECT",
+ .pme_code = 0x120e4,
.pme_short_desc = "Group dispatch rejected",
.pme_long_desc = "A group that previously attempted dispatch was rejected.",
- .pme_event_ids = { 65, 65, -1, 55, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000004ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_DISP_REJECT],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_DISP_REJECT]
},
-#define POWER5_PME_PM_L2SA_MOD_INV 95
[ POWER5_PME_PM_L2SA_MOD_INV ] = {
.pme_name = "PM_L2SA_MOD_INV",
+ .pme_code = 0x730e0,
.pme_short_desc = "L2 slice A transition from modified to invalid",
- .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.",
- .pme_event_ids = { -1, -1, 63, 67, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000100ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_PTEG_FROM_L25_SHR 96
+ .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_MOD_INV],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_MOD_INV]
+ },
[ POWER5_PME_PM_PTEG_FROM_L25_SHR ] = {
.pme_name = "PM_PTEG_FROM_L25_SHR",
+ .pme_code = 0x183097,
.pme_short_desc = "PTEG loaded from L2.5 shared",
- .pme_long_desc = "PTEG loaded from L2.5 shared",
- .pme_event_ids = { 184, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0100000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FAB_CMD_RETRIED 97
+ .pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (T or SL) data from the L2 of a chip on the same module as this processor is located due to a demand load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_L25_SHR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_L25_SHR]
+ },
[ POWER5_PME_PM_FAB_CMD_RETRIED ] = {
.pme_name = "PM_FAB_CMD_RETRIED",
+ .pme_code = 0x710c7,
.pme_short_desc = "Fabric command retried",
- .pme_long_desc = "Fabric command retried",
- .pme_event_ids = { -1, -1, 17, 22, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000002000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L3SA_SHR_INV 98
+ .pme_long_desc = "Incremented when a command issued by a chip on its SnoopA address bus is retried for any reason. The overwhelming majority of retries are due to running out of memory controller queues but retries can also be caused by trying to reference addresses that are in a transient cache state -- e.g. a line is transient after issuing a DCLAIM instruction to a shared line but before the associated store completes. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_CMD_RETRIED],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_CMD_RETRIED]
+ },
[ POWER5_PME_PM_L3SA_SHR_INV ] = {
.pme_name = "PM_L3SA_SHR_INV",
+ .pme_code = 0x710c3,
.pme_short_desc = "L3 slice A transition from shared to invalid",
- .pme_long_desc = "L3 slice A transition from shared to invalid",
- .pme_event_ids = { -1, -1, 90, 94, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000020ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL 99
+ .pme_long_desc = "L3 snooper detects someone doing a store to a line that is Sx in this L3(i.e. invalidate hit SX and dispatched).",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SA_SHR_INV],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SA_SHR_INV]
+ },
[ POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL ] = {
.pme_name = "PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL",
- .pme_short_desc = "L2 Slice B RC dispatch attempt failed due to all CO busy",
- .pme_long_desc = "L2 Slice B RC dispatch attempt failed due to all CO busy",
- .pme_event_ids = { -1, -1, 76, 80, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000002ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SA_RCST_DISP_FAIL_ADDR 100
+ .pme_code = 0x713c1,
+ .pme_short_desc = "L2 slice B RC dispatch attempt failed due to all CO busy",
+ .pme_long_desc = "A Read/Claim dispatch was rejected because all Castout machines were busy.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL]
+ },
[ POWER5_PME_PM_L2SA_RCST_DISP_FAIL_ADDR ] = {
.pme_name = "PM_L2SA_RCST_DISP_FAIL_ADDR",
- .pme_short_desc = "L2 Slice A RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ",
- .pme_long_desc = "L2 Slice A RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ",
- .pme_event_ids = { -1, -1, 66, 70, -1, -1 },
- .pme_group_vector = {
- 0x2000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL 101
+ .pme_code = 0x712c0,
+ .pme_short_desc = "L2 slice A RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ",
+ .pme_long_desc = "A Read/Claim dispatch for a store failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_RCST_DISP_FAIL_ADDR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_RCST_DISP_FAIL_ADDR]
+ },
[ POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL ] = {
.pme_name = "PM_L2SA_RCLD_DISP_FAIL_RC_FULL",
- .pme_short_desc = "L2 Slice A RC load dispatch attempt failed due to all RC full",
- .pme_long_desc = "L2 Slice A RC load dispatch attempt failed due to all RC full",
- .pme_event_ids = { 84, 82, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x1000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_PTEG_FROM_L375_MOD 102
+ .pme_code = 0x721e0,
+ .pme_short_desc = "L2 slice A RC load dispatch attempt failed due to all RC full",
+ .pme_long_desc = "A Read/Claim dispatch for a load failed because all RC machines are busy.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL]
+ },
[ POWER5_PME_PM_PTEG_FROM_L375_MOD ] = {
.pme_name = "PM_PTEG_FROM_L375_MOD",
+ .pme_code = 0x1830a7,
.pme_short_desc = "PTEG loaded from L3.75 modified",
- .pme_long_desc = "PTEG loaded from L3.75 modified",
- .pme_event_ids = { 188, -1, -1, 164, -1, -1 },
- .pme_group_vector = {
- 0x0200000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_LSU1_FLUSH_UST 103
+ .pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L3 of a chip on a different module than this processor is located, due to a demand load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_L375_MOD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_L375_MOD]
+ },
[ POWER5_PME_PM_MRK_LSU1_FLUSH_UST ] = {
.pme_name = "PM_MRK_LSU1_FLUSH_UST",
+ .pme_code = 0x810c5,
.pme_short_desc = "LSU1 marked unaligned store flushes",
.pme_long_desc = "A marked store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)",
- .pme_event_ids = { -1, -1, 146, 157, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU1_FLUSH_UST],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU1_FLUSH_UST]
},
-#define POWER5_PME_PM_BR_ISSUED 104
[ POWER5_PME_PM_BR_ISSUED ] = {
.pme_name = "PM_BR_ISSUED",
+ .pme_code = 0x230e4,
.pme_short_desc = "Branches issued",
- .pme_long_desc = "This signal will be asserted each time the ISU issues a branch instruction. This signal will be asserted each time the ISU selects a branch instruction to issue.",
- .pme_event_ids = { -1, -1, 0, 1, -1, -1 },
- .pme_group_vector = {
- 0x0000000001020000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000020ULL }
- },
-#define POWER5_PME_PM_MRK_GRP_BR_REDIR 105
+ .pme_long_desc = "A branch instruction was issued to the branch unit. A branch that was incorrectly predicted may issue and execute multiple times.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_BR_ISSUED],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_BR_ISSUED]
+ },
[ POWER5_PME_PM_MRK_GRP_BR_REDIR ] = {
.pme_name = "PM_MRK_GRP_BR_REDIR",
+ .pme_code = 0x212091,
.pme_short_desc = "Group experienced marked branch redirect",
- .pme_long_desc = "Group experienced marked branch redirect",
- .pme_event_ids = { -1, 172, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000008000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_EE_OFF 106
+ .pme_long_desc = "A group containing a marked (sampled) instruction experienced a branch redirect.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_GRP_BR_REDIR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_GRP_BR_REDIR]
+ },
[ POWER5_PME_PM_EE_OFF ] = {
.pme_name = "PM_EE_OFF",
+ .pme_code = 0x130e3,
.pme_short_desc = "Cycles MSR(EE) bit off",
- .pme_long_desc = "The number of Cycles MSR(EE) bit was off.",
- .pme_event_ids = { -1, -1, 15, 19, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000010000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MEM_LO_PRIO_PW_CMPL 107
- [ POWER5_PME_PM_MEM_LO_PRIO_PW_CMPL ] = {
- .pme_name = "PM_MEM_LO_PRIO_PW_CMPL",
- .pme_short_desc = "Low priority partial-write completed",
- .pme_long_desc = "Low priority partial-write completed",
- .pme_event_ids = { -1, -1, 121, 126, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000100000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_INST_FROM_L3 108
+ .pme_long_desc = "Cycles MSR(EE) bit was off indicating that interrupts due to external exceptions were masked.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_EE_OFF],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_EE_OFF]
+ },
+ [ POWER5_PME_PM_MEM_RQ_DISP_Q4to7 ] = {
+ .pme_name = "PM_MEM_RQ_DISP_Q4to7",
+ .pme_code = 0x712c6,
+ .pme_short_desc = "Memory read queue dispatched to queues 4-7",
+ .pme_long_desc = "A memory operation was dispatched to read queue 4,5,6 or 7. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_RQ_DISP_Q4to7],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_RQ_DISP_Q4to7]
+ },
+ [ POWER5_PME_PM_MEM_FAST_PATH_RD_DISP ] = {
+ .pme_name = "PM_MEM_FAST_PATH_RD_DISP",
+ .pme_code = 0x713e6,
+ .pme_short_desc = "Fast path memory read dispatched",
+ .pme_long_desc = "Fast path memory read dispatched",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_FAST_PATH_RD_DISP],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_FAST_PATH_RD_DISP]
+ },
[ POWER5_PME_PM_INST_FROM_L3 ] = {
.pme_name = "PM_INST_FROM_L3",
+ .pme_code = 0x12208d,
.pme_short_desc = "Instruction fetched from L3",
- .pme_long_desc = "An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions",
- .pme_event_ids = { 78, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0010000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_ITLB_MISS 109
+ .pme_long_desc = "An instruction fetch group was fetched from the local L3. Fetch groups can contain up to 8 instructions",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L3],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L3]
+ },
[ POWER5_PME_PM_ITLB_MISS ] = {
.pme_name = "PM_ITLB_MISS",
+ .pme_code = 0x800c0,
.pme_short_desc = "Instruction TLB misses",
.pme_long_desc = "A TLB miss for an Instruction Fetch has occurred",
- .pme_event_ids = { 81, 79, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000100000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000004ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_ITLB_MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_ITLB_MISS]
},
-#define POWER5_PME_PM_FXU1_BUSY_FXU0_IDLE 110
[ POWER5_PME_PM_FXU1_BUSY_FXU0_IDLE ] = {
.pme_name = "PM_FXU1_BUSY_FXU0_IDLE",
+ .pme_code = 0x400012,
.pme_short_desc = "FXU1 busy FXU0 idle",
- .pme_long_desc = "FXU0 was idle while FXU1 was busy",
- .pme_event_ids = { -1, -1, -1, 49, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000004000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FXLS_FULL_CYC 111
+ .pme_long_desc = "FXU0 was idle while FXU1 was busy.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FXU1_BUSY_FXU0_IDLE],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FXU1_BUSY_FXU0_IDLE]
+ },
[ POWER5_PME_PM_FXLS_FULL_CYC ] = {
.pme_name = "PM_FXLS_FULL_CYC",
+ .pme_code = 0x411090,
.pme_short_desc = "Cycles FXLS queue is full",
- .pme_long_desc = "Cycles when one or both FXU/LSU issue queue are full",
- .pme_event_ids = { -1, -1, -1, 47, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000008000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_DTLB_REF_4K 112
+ .pme_long_desc = "Cycles when the issue queues for one or both FXU/LSU units is full. Use with caution since this is the sum of cycles when Unit 0 was full plus Unit 1 full. It does not indicate when both units were full.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FXLS_FULL_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FXLS_FULL_CYC]
+ },
[ POWER5_PME_PM_DTLB_REF_4K ] = {
.pme_name = "PM_DTLB_REF_4K",
+ .pme_code = 0xc40c2,
.pme_short_desc = "Data TLB reference for 4K page",
- .pme_long_desc = "Data TLB reference for 4K page",
- .pme_event_ids = { 26, 25, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000400000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_GRP_DISP_VALID 113
+ .pme_long_desc = "Data TLB references for 4KB pages. Includes hits + misses.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DTLB_REF_4K],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DTLB_REF_4K]
+ },
[ POWER5_PME_PM_GRP_DISP_VALID ] = {
.pme_name = "PM_GRP_DISP_VALID",
+ .pme_code = 0x120e3,
.pme_short_desc = "Group dispatch valid",
- .pme_long_desc = "Dispatch has been attempted for a valid group. Some groups may be rejected. The total number of successful dispatches is the number of dispatch valid minus dispatch reject.",
- .pme_event_ids = { 66, 66, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000004ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU_FLUSH_UST 114
+ .pme_long_desc = "A group is available for dispatch. This does not mean it was successfully dispatched.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_DISP_VALID],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_DISP_VALID]
+ },
[ POWER5_PME_PM_LSU_FLUSH_UST ] = {
.pme_name = "PM_LSU_FLUSH_UST",
+ .pme_code = 0x2c0088,
.pme_short_desc = "SRQ unaligned store flushes",
- .pme_long_desc = "A store was flushed because it was unaligned",
- .pme_event_ids = { -1, 140, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000001080000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FXU1_FIN 115
+ .pme_long_desc = "A store was flushed because it was unaligned (crossed a 4K boundary). Combined Unit 0 + 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_FLUSH_UST],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_FLUSH_UST]
+ },
[ POWER5_PME_PM_FXU1_FIN ] = {
.pme_name = "PM_FXU1_FIN",
+ .pme_code = 0x130e6,
.pme_short_desc = "FXU1 produced a result",
- .pme_long_desc = "The Fixed Point unit 1 finished an instruction and produced a result",
- .pme_event_ids = { -1, -1, 44, 50, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000010000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_THRD_PRIO_4_CYC 116
+ .pme_long_desc = "The Fixed Point unit 1 finished an instruction and produced a result. Instructions that finish may not necessary complete.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FXU1_FIN],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FXU1_FIN]
+ },
[ POWER5_PME_PM_THRD_PRIO_4_CYC ] = {
.pme_name = "PM_THRD_PRIO_4_CYC",
+ .pme_code = 0x420e3,
.pme_short_desc = "Cycles thread running at priority level 4",
- .pme_long_desc = "Cycles thread running at priority level 4",
- .pme_event_ids = { 206, 200, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000020000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_DATA_FROM_L35_MOD 117
+ .pme_long_desc = "Cycles this thread was running at priority level 4.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_4_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_4_CYC]
+ },
[ POWER5_PME_PM_MRK_DATA_FROM_L35_MOD ] = {
.pme_name = "PM_MRK_DATA_FROM_L35_MOD",
+ .pme_code = 0x2c709e,
.pme_short_desc = "Marked data loaded from L3.5 modified",
- .pme_long_desc = "Marked data loaded from L3.5 modified",
- .pme_event_ids = { -1, 163, 131, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0040000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_4INST_CLB_CYC 118
+ .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on the same module as this processor is located due to a marked load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L35_MOD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L35_MOD]
+ },
[ POWER5_PME_PM_4INST_CLB_CYC ] = {
.pme_name = "PM_4INST_CLB_CYC",
+ .pme_code = 0x400c4,
.pme_short_desc = "Cycles 4 instructions in CLB",
- .pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.",
- .pme_event_ids = { 5, 4, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000010000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_DTLB_REF_16M 119
+ .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_4INST_CLB_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_4INST_CLB_CYC]
+ },
[ POWER5_PME_PM_MRK_DTLB_REF_16M ] = {
.pme_name = "PM_MRK_DTLB_REF_16M",
+ .pme_code = 0xc40c7,
.pme_short_desc = "Marked Data TLB reference for 16M page",
- .pme_long_desc = "Marked Data TLB reference for 16M page",
- .pme_event_ids = { 169, 170, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x1000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_INST_FROM_L375_MOD 120
+ .pme_long_desc = "Data TLB references by a marked instruction for 16MB pages.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DTLB_REF_16M],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DTLB_REF_16M]
+ },
[ POWER5_PME_PM_INST_FROM_L375_MOD ] = {
.pme_name = "PM_INST_FROM_L375_MOD",
+ .pme_code = 0x42209d,
.pme_short_desc = "Instruction fetched from L3.75 modified",
- .pme_long_desc = "Instruction fetched from L3.75 modified",
- .pme_event_ids = { -1, -1, -1, 62, -1, -1 },
- .pme_group_vector = {
- 0x0080000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SC_RCST_DISP_FAIL_ADDR 121
+ .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L3 of a chip on a different module than this processor is located. Fetch groups can contain up to 8 instructions",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L375_MOD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L375_MOD]
+ },
[ POWER5_PME_PM_L2SC_RCST_DISP_FAIL_ADDR ] = {
.pme_name = "PM_L2SC_RCST_DISP_FAIL_ADDR",
- .pme_short_desc = "L2 Slice C RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ",
- .pme_long_desc = "L2 Slice C RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ",
- .pme_event_ids = { -1, -1, 82, 86, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000008ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_GRP_CMPL 122
+ .pme_code = 0x712c2,
+ .pme_short_desc = "L2 slice C RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ",
+ .pme_long_desc = "A Read/Claim dispatch for a store failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_RCST_DISP_FAIL_ADDR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_RCST_DISP_FAIL_ADDR]
+ },
[ POWER5_PME_PM_GRP_CMPL ] = {
.pme_name = "PM_GRP_CMPL",
+ .pme_code = 0x300013,
.pme_short_desc = "Group completed",
.pme_long_desc = "A group completed. Microcoded instructions that span multiple groups will generate this event once per group.",
- .pme_event_ids = { -1, -1, 49, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000002ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MEM_RQ_DISP_BUSY8to15 123
- [ POWER5_PME_PM_MEM_RQ_DISP_BUSY8to15 ] = {
- .pme_name = "PM_MEM_RQ_DISP_BUSY8to15",
- .pme_short_desc = "Memory read queue dispatched with 8-15 queues busy",
- .pme_long_desc = "Memory read queue dispatched with 8-15 queues busy",
- .pme_event_ids = { 157, 155, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000200000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU1_1FLOP 124
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_CMPL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_CMPL]
+ },
[ POWER5_PME_PM_FPU1_1FLOP ] = {
.pme_name = "PM_FPU1_1FLOP",
+ .pme_code = 0xc7,
.pme_short_desc = "FPU1 executed add",
.pme_long_desc = " mult",
- .pme_event_ids = { 45, 44, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000001000000ULL,
- 0x0000000000000100ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_1FLOP],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_1FLOP]
},
-#define POWER5_PME_PM_FPU_FRSP_FCONV 125
[ POWER5_PME_PM_FPU_FRSP_FCONV ] = {
.pme_name = "PM_FPU_FRSP_FCONV",
+ .pme_code = 0x301090,
.pme_short_desc = "FPU executed FRSP or FCONV instructions",
- .pme_long_desc = "This signal is active for one cycle when executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, 39, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000008000ULL,
- 0x0000000000000800ULL }
- },
-#define POWER5_PME_PM_5INST_CLB_CYC 126
+ .pme_long_desc = "The floating point unit has executed a frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_FRSP_FCONV],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_FRSP_FCONV]
+ },
[ POWER5_PME_PM_5INST_CLB_CYC ] = {
.pme_name = "PM_5INST_CLB_CYC",
+ .pme_code = 0x400c5,
.pme_short_desc = "Cycles 5 instructions in CLB",
- .pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.",
- .pme_event_ids = { 6, 5, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000010ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L3SC_REF 127
+ .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_5INST_CLB_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_5INST_CLB_CYC]
+ },
[ POWER5_PME_PM_L3SC_REF ] = {
.pme_name = "PM_L3SC_REF",
+ .pme_code = 0x701c5,
.pme_short_desc = "L3 slice C references",
- .pme_long_desc = "L3 slice C references",
- .pme_event_ids = { 114, 112, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000002000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_THRD_L2MISS_BOTH_CYC 128
+ .pme_long_desc = "Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SC_REF],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SC_REF]
+ },
[ POWER5_PME_PM_THRD_L2MISS_BOTH_CYC ] = {
.pme_name = "PM_THRD_L2MISS_BOTH_CYC",
+ .pme_code = 0x410c7,
.pme_short_desc = "Cycles both threads in L2 misses",
- .pme_long_desc = "Cycles both threads in L2 misses",
- .pme_event_ids = { -1, -1, 170, 176, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000200000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MEM_PW_GATH 129
+ .pme_long_desc = "Cycles that both threads have L2 miss pending. If only one thread has a L2 miss pending the other thread is given priority at decode. If both threads have L2 miss pending decode priority is determined by the number of GCT entries used.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_L2MISS_BOTH_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_L2MISS_BOTH_CYC]
+ },
[ POWER5_PME_PM_MEM_PW_GATH ] = {
.pme_name = "PM_MEM_PW_GATH",
+ .pme_code = 0x714c6,
.pme_short_desc = "Memory partial-write gathered",
- .pme_long_desc = "Memory partial-write gathered",
- .pme_event_ids = { -1, -1, 124, 129, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0001000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FAB_PNtoNN_SIDECAR 130
+ .pme_long_desc = "Two or more partial-writes have been merged into a single memory write. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_PW_GATH],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_PW_GATH]
+ },
[ POWER5_PME_PM_FAB_PNtoNN_SIDECAR ] = {
.pme_name = "PM_FAB_PNtoNN_SIDECAR",
+ .pme_code = 0x713c7,
.pme_short_desc = "PN to NN beat went to sidecar first",
- .pme_long_desc = "PN to NN beat went to sidecar first",
- .pme_event_ids = { -1, -1, 21, 26, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000008000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FAB_DCLAIM_ISSUED 131
+ .pme_long_desc = "Fabric Data beats that the base chip takes the inbound PN data and forwards it on to the outbound NN data bus after going into a sidecar first. The signal is delivered at FBC speed and the count must be scaled.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_PNtoNN_SIDECAR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_PNtoNN_SIDECAR]
+ },
[ POWER5_PME_PM_FAB_DCLAIM_ISSUED ] = {
.pme_name = "PM_FAB_DCLAIM_ISSUED",
+ .pme_code = 0x720e7,
.pme_short_desc = "dclaim issued",
- .pme_long_desc = "dclaim issued",
- .pme_event_ids = { 28, 27, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000002000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_GRP_IC_MISS 132
+ .pme_long_desc = "A DCLAIM command was issued. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly. ",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_DCLAIM_ISSUED],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_DCLAIM_ISSUED]
+ },
[ POWER5_PME_PM_GRP_IC_MISS ] = {
.pme_name = "PM_GRP_IC_MISS",
+ .pme_code = 0x120e7,
.pme_short_desc = "Group experienced I cache miss",
- .pme_long_desc = "Group experienced I cache miss",
- .pme_event_ids = { 67, 67, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000008000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_INST_FROM_L35_SHR 133
+ .pme_long_desc = "Number of groups, counted at dispatch, that have encountered an icache miss redirect. Every group constructed from a fetch group that missed the instruction cache will count.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_IC_MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_IC_MISS]
+ },
[ POWER5_PME_PM_INST_FROM_L35_SHR ] = {
.pme_name = "PM_INST_FROM_L35_SHR",
+ .pme_code = 0x12209d,
.pme_short_desc = "Instruction fetched from L3.5 shared",
- .pme_long_desc = "Instruction fetched from L3.5 shared",
- .pme_event_ids = { 79, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0080000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU_LMQ_FULL_CYC 134
+ .pme_long_desc = "An instruction fetch group was fetched with shared (S) data from the L3 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L35_SHR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L35_SHR]
+ },
[ POWER5_PME_PM_LSU_LMQ_FULL_CYC ] = {
.pme_name = "PM_LSU_LMQ_FULL_CYC",
+ .pme_code = 0xc30e7,
.pme_short_desc = "Cycles LMQ full",
- .pme_long_desc = "The LMQ was full",
- .pme_event_ids = { -1, -1, 111, 116, -1, -1 },
- .pme_group_vector = {
- 0x0000000100000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_DATA_FROM_L2_CYC 135
+ .pme_long_desc = "The Load Miss Queue was full.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_LMQ_FULL_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_LMQ_FULL_CYC]
+ },
[ POWER5_PME_PM_MRK_DATA_FROM_L2_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L2_CYC",
+ .pme_code = 0x2c70a0,
.pme_short_desc = "Marked load latency from L2",
- .pme_long_desc = "Marked load latency from L2",
- .pme_event_ids = { -1, 162, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0010000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU_SRQ_SYNC_CYC 136
+ .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L2_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L2_CYC]
+ },
[ POWER5_PME_PM_LSU_SRQ_SYNC_CYC ] = {
.pme_name = "PM_LSU_SRQ_SYNC_CYC",
+ .pme_code = 0x830e5,
.pme_short_desc = "SRQ sync duration",
- .pme_long_desc = "This signal is asserted every cycle when a sync is in the SRQ.",
- .pme_event_ids = { -1, -1, 119, 124, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000100ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU0_BUSY_REJECT 137
+ .pme_long_desc = "Cycles that a sync instruction is active in the Store Request Queue.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_SRQ_SYNC_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_SRQ_SYNC_CYC]
+ },
[ POWER5_PME_PM_LSU0_BUSY_REJECT ] = {
.pme_name = "PM_LSU0_BUSY_REJECT",
+ .pme_code = 0xc20e3,
.pme_short_desc = "LSU0 busy due to reject",
- .pme_long_desc = "LSU unit 0 busy due to reject",
- .pme_event_ids = { 117, 115, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000002000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU_REJECT_ERAT_MISS 138
+ .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions. ",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_BUSY_REJECT],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_BUSY_REJECT]
+ },
[ POWER5_PME_PM_LSU_REJECT_ERAT_MISS ] = {
.pme_name = "PM_LSU_REJECT_ERAT_MISS",
+ .pme_code = 0x1c6090,
.pme_short_desc = "LSU reject due to ERAT miss",
- .pme_long_desc = "LSU reject due to ERAT miss",
- .pme_event_ids = { 145, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000004000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_DATA_FROM_RMEM_CYC 139
+ .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions due to an ERAT miss. Combined unit 0 + 1. Requests that miss the Derat are rejected and retried until the request hits in the Erat.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_REJECT_ERAT_MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_REJECT_ERAT_MISS]
+ },
[ POWER5_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_RMEM_CYC",
+ .pme_code = 0x4c70a1,
.pme_short_desc = "Marked load latency from remote memory",
- .pme_long_desc = "Marked load latency from remote memory",
- .pme_event_ids = { -1, -1, -1, 143, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0080000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_DATA_FROM_L375_SHR 140
+ .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_RMEM_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_RMEM_CYC]
+ },
[ POWER5_PME_PM_DATA_FROM_L375_SHR ] = {
.pme_name = "PM_DATA_FROM_L375_SHR",
+ .pme_code = 0x3c309e,
.pme_short_desc = "Data loaded from L3.75 shared",
- .pme_long_desc = "Data loaded from L3.75 shared",
- .pme_event_ids = { -1, -1, 10, -1, -1, -1 },
- .pme_group_vector = {
- 0x0008000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU0_FMOV_FEST 141
+ .pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on a different module than this processor is located due to a demand load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_L375_SHR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_L375_SHR]
+ },
[ POWER5_PME_PM_FPU0_FMOV_FEST ] = {
.pme_name = "PM_FPU0_FMOV_FEST",
+ .pme_code = 0x10c0,
.pme_short_desc = "FPU0 executed FMOV or FEST instructions",
- .pme_long_desc = "This signal is active for one cycle when fp0 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ",
- .pme_event_ids = { -1, -1, 31, 36, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000080000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_PTEG_FROM_L25_MOD 142
+ .pme_long_desc = "FPU0 has executed a move kind of instruction or one of the estimate instructions. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_FMOV_FEST],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_FMOV_FEST]
+ },
[ POWER5_PME_PM_PTEG_FROM_L25_MOD ] = {
.pme_name = "PM_PTEG_FROM_L25_MOD",
+ .pme_code = 0x283097,
.pme_short_desc = "PTEG loaded from L2.5 modified",
- .pme_long_desc = "PTEG loaded from L2.5 modified",
- .pme_event_ids = { -1, 181, 153, -1, -1, -1 },
- .pme_group_vector = {
- 0x0100000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LD_REF_L1_LSU0 143
+ .pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L2 of a chip on the same module as this processor is located due to a demand load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_L25_MOD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_L25_MOD]
+ },
[ POWER5_PME_PM_LD_REF_L1_LSU0 ] = {
.pme_name = "PM_LD_REF_L1_LSU0",
+ .pme_code = 0xc10c0,
.pme_short_desc = "LSU0 L1 D cache load references",
- .pme_long_desc = "A load executed on unit 0",
- .pme_event_ids = { -1, -1, 103, 107, -1, -1 },
- .pme_group_vector = {
- 0x0000400000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_THRD_PRIO_7_CYC 144
+ .pme_long_desc = "Load references to Level 1 Data Cache, by unit 0.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LD_REF_L1_LSU0],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LD_REF_L1_LSU0]
+ },
[ POWER5_PME_PM_THRD_PRIO_7_CYC ] = {
.pme_name = "PM_THRD_PRIO_7_CYC",
+ .pme_code = 0x420e6,
.pme_short_desc = "Cycles thread running at priority level 7",
- .pme_long_desc = "Cycles thread running at priority level 7",
- .pme_event_ids = { 209, 203, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000020000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU1_FLUSH_SRQ 145
+ .pme_long_desc = "Cycles this thread was running at priority level 7.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_7_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_7_CYC]
+ },
[ POWER5_PME_PM_LSU1_FLUSH_SRQ ] = {
.pme_name = "PM_LSU1_FLUSH_SRQ",
- .pme_short_desc = "LSU1 SRQ flushes",
+ .pme_code = 0xc00c7,
+ .pme_short_desc = "LSU1 SRQ lhs flushes",
.pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. ",
- .pme_event_ids = { 131, 129, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000800000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_FLUSH_SRQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_FLUSH_SRQ]
},
-#define POWER5_PME_PM_L2SC_RCST_DISP 146
[ POWER5_PME_PM_L2SC_RCST_DISP ] = {
.pme_name = "PM_L2SC_RCST_DISP",
- .pme_short_desc = "L2 Slice C RC store dispatch attempt",
- .pme_long_desc = "L2 Slice C RC store dispatch attempt",
- .pme_event_ids = { 101, 99, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000008ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_CMPLU_STALL_DIV 147
+ .pme_code = 0x702c2,
+ .pme_short_desc = "L2 slice C RC store dispatch attempt",
+ .pme_long_desc = "A Read/Claim dispatch for a Store was attempted.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_RCST_DISP],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_RCST_DISP]
+ },
[ POWER5_PME_PM_CMPLU_STALL_DIV ] = {
.pme_name = "PM_CMPLU_STALL_DIV",
+ .pme_code = 0x411099,
.pme_short_desc = "Completion stall caused by DIV instruction",
- .pme_long_desc = "Completion stall caused by DIV instruction",
- .pme_event_ids = { -1, -1, -1, 7, -1, -1 },
- .pme_group_vector = {
- 0x0000000040000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_INST_FROM_L375_SHR 148
+ .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point divide instruction. This is a subset of PM_CMPLU_STALL_FXU.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_CMPLU_STALL_DIV],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CMPLU_STALL_DIV]
+ },
+ [ POWER5_PME_PM_MEM_RQ_DISP_Q12to15 ] = {
+ .pme_name = "PM_MEM_RQ_DISP_Q12to15",
+ .pme_code = 0x732e6,
+ .pme_short_desc = "Memory read queue dispatched to queues 12-15",
+ .pme_long_desc = "A memory operation was dispatched to read queue 12,13,14 or 15. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_RQ_DISP_Q12to15],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_RQ_DISP_Q12to15]
+ },
[ POWER5_PME_PM_INST_FROM_L375_SHR ] = {
.pme_name = "PM_INST_FROM_L375_SHR",
+ .pme_code = 0x32209d,
.pme_short_desc = "Instruction fetched from L3.75 shared",
- .pme_long_desc = "Instruction fetched from L3.75 shared",
- .pme_event_ids = { -1, -1, 58, -1, -1, -1 },
- .pme_group_vector = {
- 0x0080000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_ST_REF_L1 149
+ .pme_long_desc = "An instruction fetch group was fetched with shared (S) data from the L3 of a chip on a different module than this processor is located. Fetch groups can contain up to 8 instructions",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L375_SHR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L375_SHR]
+ },
[ POWER5_PME_PM_ST_REF_L1 ] = {
.pme_name = "PM_ST_REF_L1",
+ .pme_code = 0x3c1090,
.pme_short_desc = "L1 D cache store references",
- .pme_long_desc = "Total DL1 Store references",
- .pme_event_ids = { -1, -1, 165, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000100000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000008207ULL }
- },
-#define POWER5_PME_PM_L3SB_ALL_BUSY 150
+ .pme_long_desc = "Store references to the Data Cache. Combined Unit 0 + 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_ST_REF_L1],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_ST_REF_L1]
+ },
[ POWER5_PME_PM_L3SB_ALL_BUSY ] = {
.pme_name = "PM_L3SB_ALL_BUSY",
+ .pme_code = 0x721e4,
.pme_short_desc = "L3 slice B active for every cycle all CI/CO machines busy",
- .pme_long_desc = "L3 slice B active for every cycle all CI/CO machines busy",
- .pme_event_ids = { 109, 107, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000800ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY 151
+ .pme_long_desc = "Cycles All Castin/Castout machines are busy.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SB_ALL_BUSY],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SB_ALL_BUSY]
+ },
[ POWER5_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY ] = {
.pme_name = "PM_FAB_P1toVNorNN_SIDECAR_EMPTY",
+ .pme_code = 0x711c7,
.pme_short_desc = "P1 to VN/NN sidecar empty",
- .pme_long_desc = "P1 to VN/NN sidecar empty",
- .pme_event_ids = { -1, -1, 20, 25, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000004000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_DATA_FROM_L275_SHR_CYC 152
+ .pme_long_desc = "Fabric cycles when the Plus-1 jump sidecar (sidecars for mcm to mcm data transfer) is empty. The signal is delivered at FBC speed and the count must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY]
+ },
[ POWER5_PME_PM_MRK_DATA_FROM_L275_SHR_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L275_SHR_CYC",
+ .pme_code = 0x2c70a3,
.pme_short_desc = "Marked load latency from L2.75 shared",
- .pme_long_desc = "Marked load latency from L2.75 shared",
- .pme_event_ids = { -1, 161, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0280000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FAB_HOLDtoNN_EMPTY 153
+ .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L275_SHR_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L275_SHR_CYC]
+ },
[ POWER5_PME_PM_FAB_HOLDtoNN_EMPTY ] = {
.pme_name = "PM_FAB_HOLDtoNN_EMPTY",
+ .pme_code = 0x722e7,
.pme_short_desc = "Hold buffer to NN empty",
- .pme_long_desc = "Hold buffer to NN empty",
- .pme_event_ids = { 29, 28, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000010000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_DATA_FROM_LMEM 154
+ .pme_long_desc = "Fabric cyles when the Next Node out hold-buffers are emtpy. The signal is delivered at FBC speed and the count must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_HOLDtoNN_EMPTY],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_HOLDtoNN_EMPTY]
+ },
[ POWER5_PME_PM_DATA_FROM_LMEM ] = {
.pme_name = "PM_DATA_FROM_LMEM",
+ .pme_code = 0x2c3087,
.pme_short_desc = "Data loaded from local memory",
- .pme_long_desc = "Data loaded from local memory",
- .pme_event_ids = { -1, 18, 11, -1, -1, -1 },
- .pme_group_vector = {
- 0x0003000000000000ULL,
- 0x0000000000000000ULL,
- 0x000000000000000aULL }
- },
-#define POWER5_PME_PM_RUN_CYC 155
+ .pme_long_desc = "The processor's Data Cache was reloaded from memory attached to the same module this proccessor is located on.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_LMEM],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_LMEM]
+ },
[ POWER5_PME_PM_RUN_CYC ] = {
.pme_name = "PM_RUN_CYC",
+ .pme_code = 0x100005,
.pme_short_desc = "Run cycles",
- .pme_long_desc = "Processor Cycles gated by the run latch",
- .pme_event_ids = { 190, -1, -1, -1, -1, 0 },
- .pme_group_vector = {
- 0xffffffffffffffffULL,
- 0xffffffffffffffffULL,
- 0x000000000001ffffULL }
- },
-#define POWER5_PME_PM_PTEG_FROM_RMEM 156
+ .pme_long_desc = "Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_RUN_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_RUN_CYC]
+ },
[ POWER5_PME_PM_PTEG_FROM_RMEM ] = {
.pme_name = "PM_PTEG_FROM_RMEM",
+ .pme_code = 0x1830a1,
.pme_short_desc = "PTEG loaded from remote memory",
- .pme_long_desc = "PTEG loaded from remote memory",
- .pme_event_ids = { 189, -1, -1, 165, -1, -1 },
- .pme_group_vector = {
- 0x0400000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SC_RCLD_DISP 157
+ .pme_long_desc = "A Page Table Entry was loaded into the TLB from memory attached to a different module than this proccessor is located on.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_RMEM],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_RMEM]
+ },
[ POWER5_PME_PM_L2SC_RCLD_DISP ] = {
.pme_name = "PM_L2SC_RCLD_DISP",
- .pme_short_desc = "L2 Slice C RC load dispatch attempt",
- .pme_long_desc = "L2 Slice C RC load dispatch attempt",
- .pme_event_ids = { 99, 97, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000004ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU0_LDF 158
+ .pme_code = 0x701c2,
+ .pme_short_desc = "L2 slice C RC load dispatch attempt",
+ .pme_long_desc = "A Read/Claim dispatch for a Load was attempted",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_RCLD_DISP],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_RCLD_DISP]
+ },
[ POWER5_PME_PM_LSU0_LDF ] = {
.pme_name = "PM_LSU0_LDF",
+ .pme_code = 0xc50c0,
.pme_short_desc = "LSU0 executed Floating Point load instruction",
- .pme_long_desc = "A floating point load was executed from LSU unit 0",
- .pme_event_ids = { -1, -1, 105, 109, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000002400000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU_LRQ_S0_VALID 159
+ .pme_long_desc = "A floating point load was executed by LSU0",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_LDF],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_LDF]
+ },
[ POWER5_PME_PM_LSU_LRQ_S0_VALID ] = {
.pme_name = "PM_LSU_LRQ_S0_VALID",
+ .pme_code = 0xc20e2,
.pme_short_desc = "LRQ slot 0 valid",
- .pme_long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.",
- .pme_event_ids = { 144, 143, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000080ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_PMC3_OVERFLOW 160
+ .pme_long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each).",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_LRQ_S0_VALID],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_LRQ_S0_VALID]
+ },
[ POWER5_PME_PM_PMC3_OVERFLOW ] = {
.pme_name = "PM_PMC3_OVERFLOW",
+ .pme_code = 0x40000a,
.pme_short_desc = "PMC3 Overflow",
- .pme_long_desc = "PMC3 Overflow",
- .pme_event_ids = { -1, -1, -1, 162, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_IMR_RELOAD 161
+ .pme_long_desc = "Overflows from PMC3 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_PMC3_OVERFLOW],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PMC3_OVERFLOW]
+ },
[ POWER5_PME_PM_MRK_IMR_RELOAD ] = {
.pme_name = "PM_MRK_IMR_RELOAD",
+ .pme_code = 0x820e2,
.pme_short_desc = "Marked IMR reloaded",
- .pme_long_desc = "A DL1 reload occured due to marked load",
- .pme_event_ids = { 173, 173, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0002000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_GRP_TIMEO 162
+ .pme_long_desc = "A DL1 reload occurred due to marked load",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_IMR_RELOAD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_IMR_RELOAD]
+ },
[ POWER5_PME_PM_MRK_GRP_TIMEO ] = {
.pme_name = "PM_MRK_GRP_TIMEO",
+ .pme_code = 0x40000b,
.pme_short_desc = "Marked group completion timeout",
.pme_long_desc = "The sampling timeout expired indicating that the previously sampled instruction is no longer in the processor",
- .pme_event_ids = { -1, -1, -1, 148, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x8000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_GRP_TIMEO],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_GRP_TIMEO]
},
-#define POWER5_PME_PM_ST_MISS_L1 163
[ POWER5_PME_PM_ST_MISS_L1 ] = {
.pme_name = "PM_ST_MISS_L1",
+ .pme_code = 0xc10c3,
.pme_short_desc = "L1 D cache store misses",
- .pme_long_desc = "A store missed the dcache",
- .pme_event_ids = { -1, -1, 164, 171, -1, -1 },
- .pme_group_vector = {
- 0x0000100000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000004008ULL }
- },
-#define POWER5_PME_PM_STOP_COMPLETION 164
+ .pme_long_desc = "A store missed the dcache. Combined Unit 0 + 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_ST_MISS_L1],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_ST_MISS_L1]
+ },
[ POWER5_PME_PM_STOP_COMPLETION ] = {
.pme_name = "PM_STOP_COMPLETION",
+ .pme_code = 0x300018,
.pme_short_desc = "Completion stopped",
.pme_long_desc = "RAS Unit has signaled completion to stop",
- .pme_event_ids = { -1, -1, 163, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_STOP_COMPLETION],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_STOP_COMPLETION]
},
-#define POWER5_PME_PM_LSU_BUSY_REJECT 165
[ POWER5_PME_PM_LSU_BUSY_REJECT ] = {
.pme_name = "PM_LSU_BUSY_REJECT",
+ .pme_code = 0x1c2090,
.pme_short_desc = "LSU busy due to reject",
- .pme_long_desc = "LSU (unit 0 + unit 1) is busy due to reject",
- .pme_event_ids = { 139, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000001000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_ISLB_MISS 166
+ .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions. Combined unit 0 + 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_BUSY_REJECT],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_BUSY_REJECT]
+ },
[ POWER5_PME_PM_ISLB_MISS ] = {
.pme_name = "PM_ISLB_MISS",
+ .pme_code = 0x800c1,
.pme_short_desc = "Instruction SLB misses",
.pme_long_desc = "A SLB miss for an instruction fetch as occurred",
- .pme_event_ids = { 80, 78, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000200000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_ISLB_MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_ISLB_MISS]
},
-#define POWER5_PME_PM_CYC 167
[ POWER5_PME_PM_CYC ] = {
.pme_name = "PM_CYC",
+ .pme_code = 0xf,
.pme_short_desc = "Processor cycles",
.pme_long_desc = "Processor cycles",
- .pme_event_ids = { 12, 15, 6, 12, -1, -1 },
- .pme_group_vector = {
- 0x0000000020000003ULL,
- 0x0000001000000000ULL,
- 0x000000000001f010ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CYC]
},
-#define POWER5_PME_PM_THRD_ONE_RUN_CYC 168
[ POWER5_PME_PM_THRD_ONE_RUN_CYC ] = {
.pme_name = "PM_THRD_ONE_RUN_CYC",
+ .pme_code = 0x10000b,
.pme_short_desc = "One of the threads in run cycles",
- .pme_long_desc = "One of the threads in run cycles",
- .pme_event_ids = { 202, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000200000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_GRP_BR_REDIR_NONSPEC 169
+ .pme_long_desc = "At least one thread has set its run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. This event does not respect FCWAIT.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_ONE_RUN_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_ONE_RUN_CYC]
+ },
[ POWER5_PME_PM_GRP_BR_REDIR_NONSPEC ] = {
.pme_name = "PM_GRP_BR_REDIR_NONSPEC",
+ .pme_code = 0x112091,
.pme_short_desc = "Group experienced non-speculative branch redirect",
- .pme_long_desc = "Group experienced non-speculative branch redirect",
- .pme_event_ids = { 64, 63, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000040000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU1_SRQ_STFWD 170
+ .pme_long_desc = "Number of groups, counted at completion, that have encountered a branch redirect.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_BR_REDIR_NONSPEC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_BR_REDIR_NONSPEC]
+ },
[ POWER5_PME_PM_LSU1_SRQ_STFWD ] = {
.pme_name = "PM_LSU1_SRQ_STFWD",
+ .pme_code = 0xc20e4,
.pme_short_desc = "LSU1 SRQ store forwarded",
- .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 1",
- .pme_event_ids = { 138, 136, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L3SC_MOD_INV 171
+ .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 1. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_SRQ_STFWD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_SRQ_STFWD]
+ },
[ POWER5_PME_PM_L3SC_MOD_INV ] = {
.pme_name = "PM_L3SC_MOD_INV",
+ .pme_code = 0x730e5,
.pme_short_desc = "L3 slice C transition from modified to invalid",
- .pme_long_desc = "L3 slice C transition from modified to invalid",
- .pme_event_ids = { -1, -1, 97, 101, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000080ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2_PREF 172
+ .pme_long_desc = "L3 snooper detects someone doing a store to a line that is truly M in this L3 (i.e. L3 going M=>I) Mu|Me are not included since they are formed due to a previous read op Tx is not included since it is considered shared at this point.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SC_MOD_INV],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SC_MOD_INV]
+ },
[ POWER5_PME_PM_L2_PREF ] = {
.pme_name = "PM_L2_PREF",
+ .pme_code = 0xc50c3,
.pme_short_desc = "L2 cache prefetches",
.pme_long_desc = "A request to prefetch data into L2 was made",
- .pme_event_ids = { -1, -1, 87, 91, -1, -1 },
- .pme_group_vector = {
- 0x0000000000003000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000010ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2_PREF],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2_PREF]
},
-#define POWER5_PME_PM_GCT_NOSLOT_BR_MPRED 173
[ POWER5_PME_PM_GCT_NOSLOT_BR_MPRED ] = {
.pme_name = "PM_GCT_NOSLOT_BR_MPRED",
+ .pme_code = 0x41009c,
.pme_short_desc = "No slot in GCT caused by branch mispredict",
- .pme_long_desc = "This thread has no slot in the GCT because of branch mispredict",
- .pme_event_ids = { -1, -1, -1, 51, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000020ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_DATA_FROM_L25_MOD 174
+ .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because of a branch misprediction.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_GCT_NOSLOT_BR_MPRED],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GCT_NOSLOT_BR_MPRED]
+ },
[ POWER5_PME_PM_MRK_DATA_FROM_L25_MOD ] = {
.pme_name = "PM_MRK_DATA_FROM_L25_MOD",
+ .pme_code = 0x2c7097,
.pme_short_desc = "Marked data loaded from L2.5 modified",
- .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a marked demand load",
- .pme_event_ids = { -1, 159, 129, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0010000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SB_MOD_INV 175
+ .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 of a chip on the same module as this processor is located due to a marked load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L25_MOD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L25_MOD]
+ },
[ POWER5_PME_PM_L2SB_MOD_INV ] = {
.pme_name = "PM_L2SB_MOD_INV",
+ .pme_code = 0x730e1,
.pme_short_desc = "L2 slice B transition from modified to invalid",
- .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.",
- .pme_event_ids = { -1, -1, 71, 75, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000200ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SB_ST_REQ 176
+ .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_MOD_INV],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_MOD_INV]
+ },
[ POWER5_PME_PM_L2SB_ST_REQ ] = {
.pme_name = "PM_L2SB_ST_REQ",
+ .pme_code = 0x723e1,
.pme_short_desc = "L2 slice B store requests",
- .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C.",
- .pme_event_ids = { 97, 95, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000002ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_L1_RELOAD_VALID 177
+ .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A, B, and C.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_ST_REQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_ST_REQ]
+ },
[ POWER5_PME_PM_MRK_L1_RELOAD_VALID ] = {
.pme_name = "PM_MRK_L1_RELOAD_VALID",
+ .pme_code = 0xc70e4,
.pme_short_desc = "Marked L1 reload data source valid",
.pme_long_desc = "The source information is valid and is for a marked load",
- .pme_event_ids = { -1, -1, 138, 149, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0008000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_L1_RELOAD_VALID],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_L1_RELOAD_VALID]
},
-#define POWER5_PME_PM_L3SB_HIT 178
[ POWER5_PME_PM_L3SB_HIT ] = {
.pme_name = "PM_L3SB_HIT",
+ .pme_code = 0x711c4,
.pme_short_desc = "L3 slice B hits",
- .pme_long_desc = "L3 slice B hits",
- .pme_event_ids = { -1, -1, 92, 96, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000001000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SB_SHR_MOD 179
+ .pme_long_desc = "Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 slice",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SB_HIT],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SB_HIT]
+ },
[ POWER5_PME_PM_L2SB_SHR_MOD ] = {
.pme_name = "PM_L2SB_SHR_MOD",
+ .pme_code = 0x700c1,
.pme_short_desc = "L2 slice B transition from shared to modified",
- .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. ",
- .pme_event_ids = { 96, 94, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000200ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_EE_OFF_EXT_INT 180
+ .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A, B, and C. ",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_SHR_MOD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_SHR_MOD]
+ },
[ POWER5_PME_PM_EE_OFF_EXT_INT ] = {
.pme_name = "PM_EE_OFF_EXT_INT",
+ .pme_code = 0x130e7,
.pme_short_desc = "Cycles MSR(EE) bit off and external interrupt pending",
- .pme_long_desc = "Cycles MSR(EE) bit off and external interrupt pending",
- .pme_event_ids = { -1, -1, 16, 20, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000200000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_1PLUS_PPC_CMPL 181
+ .pme_long_desc = "Cycles when an interrupt due to an external exception is pending but external exceptions were masked.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_EE_OFF_EXT_INT],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_EE_OFF_EXT_INT]
+ },
[ POWER5_PME_PM_1PLUS_PPC_CMPL ] = {
.pme_name = "PM_1PLUS_PPC_CMPL",
+ .pme_code = 0x100013,
.pme_short_desc = "One or more PPC instruction completed",
.pme_long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.",
- .pme_event_ids = { 2, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000002ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_1PLUS_PPC_CMPL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_1PLUS_PPC_CMPL]
},
-#define POWER5_PME_PM_L2SC_SHR_MOD 182
[ POWER5_PME_PM_L2SC_SHR_MOD ] = {
.pme_name = "PM_L2SC_SHR_MOD",
+ .pme_code = 0x700c2,
.pme_short_desc = "L2 slice C transition from shared to modified",
- .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. ",
- .pme_event_ids = { 104, 102, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000400ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_PMC6_OVERFLOW 183
+ .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A, B, and C. ",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_SHR_MOD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_SHR_MOD]
+ },
[ POWER5_PME_PM_PMC6_OVERFLOW ] = {
.pme_name = "PM_PMC6_OVERFLOW",
+ .pme_code = 0x30001a,
.pme_short_desc = "PMC6 Overflow",
- .pme_long_desc = "PMC6 Overflow",
- .pme_event_ids = { -1, -1, 152, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU_LRQ_FULL_CYC 184
+ .pme_long_desc = "Overflows from PMC6 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_PMC6_OVERFLOW],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PMC6_OVERFLOW]
+ },
[ POWER5_PME_PM_LSU_LRQ_FULL_CYC ] = {
.pme_name = "PM_LSU_LRQ_FULL_CYC",
+ .pme_code = 0x110c2,
.pme_short_desc = "Cycles LRQ full",
- .pme_long_desc = "The ISU sends this signal when the LRQ is full.",
- .pme_event_ids = { -1, -1, 116, 120, -1, -1 },
- .pme_group_vector = {
- 0x0000000100000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_IC_PREF_INSTALL 185
+ .pme_long_desc = "Cycles when the LRQ is full.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_LRQ_FULL_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_LRQ_FULL_CYC]
+ },
[ POWER5_PME_PM_IC_PREF_INSTALL ] = {
.pme_name = "PM_IC_PREF_INSTALL",
- .pme_short_desc = "Instruction prefetched installed in prefetch",
- .pme_long_desc = "New line coming into the prefetch buffer",
- .pme_event_ids = { -1, -1, 54, 58, -1, -1 },
- .pme_group_vector = {
- 0x0000004000000800ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_TLB_MISS 186
+ .pme_code = 0x210c7,
+ .pme_short_desc = "Instruction prefetched installed in prefetch buffer",
+ .pme_long_desc = "A prefetch buffer entry (line) is allocated but the request is not a demand fetch.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_IC_PREF_INSTALL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_IC_PREF_INSTALL]
+ },
[ POWER5_PME_PM_TLB_MISS ] = {
.pme_name = "PM_TLB_MISS",
+ .pme_code = 0x180088,
.pme_short_desc = "TLB misses",
- .pme_long_desc = "TLB misses",
- .pme_event_ids = { 210, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000010000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000008000ULL }
- },
-#define POWER5_PME_PM_GCT_FULL_CYC 187
+ .pme_long_desc = "Total of Data TLB mises + Instruction TLB misses",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_TLB_MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_TLB_MISS]
+ },
[ POWER5_PME_PM_GCT_FULL_CYC ] = {
.pme_name = "PM_GCT_FULL_CYC",
+ .pme_code = 0x100c0,
.pme_short_desc = "Cycles GCT full",
- .pme_long_desc = "The ISU sends a signal indicating the gct is full. ",
- .pme_event_ids = { 61, 60, -1, 52, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000040ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FXU_BUSY 188
+ .pme_long_desc = "The Global Completion Table is completely full.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_GCT_FULL_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GCT_FULL_CYC]
+ },
[ POWER5_PME_PM_FXU_BUSY ] = {
.pme_name = "PM_FXU_BUSY",
+ .pme_code = 0x200012,
.pme_short_desc = "FXU busy",
- .pme_long_desc = "FXU0 and FXU1 are both busy",
- .pme_event_ids = { -1, 57, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000004000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_DATA_FROM_L3_CYC 189
+ .pme_long_desc = "Cycles when both FXU0 and FXU1 are busy.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FXU_BUSY],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FXU_BUSY]
+ },
[ POWER5_PME_PM_MRK_DATA_FROM_L3_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L3_CYC",
+ .pme_code = 0x2c70a4,
.pme_short_desc = "Marked load latency from L3",
- .pme_long_desc = "Marked load latency from L3",
- .pme_event_ids = { -1, 166, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0040000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU_REJECT_LMQ_FULL 190
+ .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L3_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L3_CYC]
+ },
[ POWER5_PME_PM_LSU_REJECT_LMQ_FULL ] = {
.pme_name = "PM_LSU_REJECT_LMQ_FULL",
+ .pme_code = 0x2c6088,
.pme_short_desc = "LSU reject due to LMQ full or missed data coming",
- .pme_long_desc = "LSU reject due to LMQ full or missed data coming",
- .pme_event_ids = { -1, 144, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000004000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU_SRQ_S0_ALLOC 191
+ .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all the eight entries are full, subsequent load instructions are rejected. Combined unit 0 + 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_REJECT_LMQ_FULL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_REJECT_LMQ_FULL]
+ },
[ POWER5_PME_PM_LSU_SRQ_S0_ALLOC ] = {
.pme_name = "PM_LSU_SRQ_S0_ALLOC",
+ .pme_code = 0xc20e5,
.pme_short_desc = "SRQ slot 0 allocated",
.pme_long_desc = "SRQ Slot zero was allocated",
- .pme_event_ids = { 147, 146, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000100ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_SRQ_S0_ALLOC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_SRQ_S0_ALLOC]
},
-#define POWER5_PME_PM_GRP_MRK 192
[ POWER5_PME_PM_GRP_MRK ] = {
.pme_name = "PM_GRP_MRK",
+ .pme_code = 0x100014,
.pme_short_desc = "Group marked in IDU",
- .pme_long_desc = "A group was sampled (marked)",
- .pme_event_ids = { 70, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000010000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_INST_FROM_L25_SHR 193
+ .pme_long_desc = "A group was sampled (marked). The group is called a marked group. One instruction within the group is tagged for detailed monitoring. The sampled instruction is called a marked instructions. Events associated with the marked instruction are annotated with the marked term.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_MRK],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_MRK]
+ },
[ POWER5_PME_PM_INST_FROM_L25_SHR ] = {
.pme_name = "PM_INST_FROM_L25_SHR",
+ .pme_code = 0x122096,
.pme_short_desc = "Instruction fetched from L2.5 shared",
- .pme_long_desc = "Instruction fetched from L2.5 shared",
- .pme_event_ids = { 77, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0040000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU1_FIN 194
+ .pme_long_desc = "An instruction fetch group was fetched with shared (T or SL) data from the L2 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L25_SHR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L25_SHR]
+ },
[ POWER5_PME_PM_FPU1_FIN ] = {
.pme_name = "PM_FPU1_FIN",
+ .pme_code = 0x10c7,
.pme_short_desc = "FPU1 produced a result",
- .pme_long_desc = "fp1 finished, produced a result. This only indicates finish, not completion. ",
- .pme_event_ids = { -1, -1, 35, 40, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000010000ULL,
- 0x0000000000000500ULL }
- },
-#define POWER5_PME_PM_DC_PREF_STREAM_ALLOC 195
+ .pme_long_desc = "FPU1 finished, produced a result. This only indicates finish, not completion. Floating Point Stores are included in this count but not Floating Point Loads., , ",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_FIN],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_FIN]
+ },
[ POWER5_PME_PM_DC_PREF_STREAM_ALLOC ] = {
.pme_name = "PM_DC_PREF_STREAM_ALLOC",
+ .pme_code = 0x830e7,
.pme_short_desc = "D cache new prefetch stream allocated",
- .pme_long_desc = "A new Prefetch Stream was allocated",
- .pme_event_ids = { -1, -1, 14, 18, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000400ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_BR_MPRED_TA 196
+ .pme_long_desc = "A new Prefetch Stream was allocated.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DC_PREF_STREAM_ALLOC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DC_PREF_STREAM_ALLOC]
+ },
[ POWER5_PME_PM_BR_MPRED_TA ] = {
.pme_name = "PM_BR_MPRED_TA",
+ .pme_code = 0x230e6,
.pme_short_desc = "Branch mispredictions due to target address",
- .pme_long_desc = "branch miss predict due to a target address prediction. This signal will be asserted each time the branch execution unit detects an incorrect target address prediction. This signal will be asserted after a valid branch execution unit issue and will cause a branch mispredict flush unless a flush is detected from an older instruction.",
- .pme_event_ids = { -1, -1, 2, 3, -1, -1 },
- .pme_group_vector = {
- 0x0000010000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_CRQ_FULL_CYC 197
+ .pme_long_desc = "A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_BR_MPRED_TA],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_BR_MPRED_TA]
+ },
[ POWER5_PME_PM_CRQ_FULL_CYC ] = {
.pme_name = "PM_CRQ_FULL_CYC",
+ .pme_code = 0x110c1,
.pme_short_desc = "Cycles CR issue queue full",
- .pme_long_desc = "The ISU sends a signal indicating that the issue queue that feeds the ifu cr unit cannot accept any more group (queue is full of groups).",
- .pme_event_ids = { -1, -1, 5, 11, -1, -1 },
- .pme_group_vector = {
- 0x0000000400000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SA_RCLD_DISP 198
+ .pme_long_desc = "The issue queue that feeds the Conditional Register unit is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_CRQ_FULL_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CRQ_FULL_CYC]
+ },
[ POWER5_PME_PM_L2SA_RCLD_DISP ] = {
.pme_name = "PM_L2SA_RCLD_DISP",
- .pme_short_desc = "L2 Slice A RC load dispatch attempt",
- .pme_long_desc = "L2 Slice A RC load dispatch attempt",
- .pme_event_ids = { 83, 81, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x1000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_SNOOP_WR_RETRY_QFULL 199
+ .pme_code = 0x701c0,
+ .pme_short_desc = "L2 slice A RC load dispatch attempt",
+ .pme_long_desc = "A Read/Claim dispatch for a Load was attempted",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_RCLD_DISP],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_RCLD_DISP]
+ },
[ POWER5_PME_PM_SNOOP_WR_RETRY_QFULL ] = {
.pme_name = "PM_SNOOP_WR_RETRY_QFULL",
+ .pme_code = 0x710c6,
.pme_short_desc = "Snoop read retry due to read queue full",
- .pme_long_desc = "Snoop read retry due to read queue full",
- .pme_event_ids = { -1, -1, 161, 169, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000020000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_DTLB_REF_4K 200
+ .pme_long_desc = "A snoop request for a write to memory was retried because the write queues were full. When this happens the snoop request is retried and the writes in the write reorder queue are changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_WR_RETRY_QFULL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_WR_RETRY_QFULL]
+ },
[ POWER5_PME_PM_MRK_DTLB_REF_4K ] = {
.pme_name = "PM_MRK_DTLB_REF_4K",
+ .pme_code = 0xc40c3,
.pme_short_desc = "Marked Data TLB reference for 4K page",
- .pme_long_desc = "Marked Data TLB reference for 4K page",
- .pme_event_ids = { 170, 171, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x1000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU_SRQ_S0_VALID 201
+ .pme_long_desc = "Data TLB references by a marked instruction for 4KB pages.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DTLB_REF_4K],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DTLB_REF_4K]
+ },
[ POWER5_PME_PM_LSU_SRQ_S0_VALID ] = {
.pme_name = "PM_LSU_SRQ_S0_VALID",
+ .pme_code = 0xc20e1,
.pme_short_desc = "SRQ slot 0 valid",
- .pme_long_desc = "This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.",
- .pme_event_ids = { 148, 147, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000100ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU0_FLUSH_LRQ 202
+ .pme_long_desc = "This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the SRQ is split between the two threads (16 entries each).",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_SRQ_S0_VALID],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_SRQ_S0_VALID]
+ },
[ POWER5_PME_PM_LSU0_FLUSH_LRQ ] = {
.pme_name = "PM_LSU0_FLUSH_LRQ",
+ .pme_code = 0xc00c2,
.pme_short_desc = "LSU0 LRQ flushes",
- .pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { 119, 117, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000400000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_long_desc = "A load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_FLUSH_LRQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_FLUSH_LRQ]
},
-#define POWER5_PME_PM_INST_FROM_L275_MOD 203
[ POWER5_PME_PM_INST_FROM_L275_MOD ] = {
.pme_name = "PM_INST_FROM_L275_MOD",
+ .pme_code = 0x422096,
.pme_short_desc = "Instruction fetched from L2.75 modified",
- .pme_long_desc = "Instruction fetched from L2.75 modified",
- .pme_event_ids = { -1, -1, -1, 61, -1, -1 },
- .pme_group_vector = {
- 0x0040000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_GCT_EMPTY_CYC 204
+ .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L2 on a different module than this processor is located. Fetch groups can contain up to 8 instructions ",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L275_MOD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L275_MOD]
+ },
[ POWER5_PME_PM_GCT_EMPTY_CYC ] = {
.pme_name = "PM_GCT_EMPTY_CYC",
+ .pme_code = 0x200004,
.pme_short_desc = "Cycles GCT empty",
.pme_long_desc = "The Global Completion Table is completely empty",
- .pme_event_ids = { -1, 195, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000002ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_GCT_EMPTY_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GCT_EMPTY_CYC]
},
-#define POWER5_PME_PM_LARX_LSU0 205
[ POWER5_PME_PM_LARX_LSU0 ] = {
.pme_name = "PM_LARX_LSU0",
+ .pme_code = 0x820e7,
.pme_short_desc = "Larx executed on LSU0",
- .pme_long_desc = "A larx (lwarx or ldarx) was executed on side 0 (there is no coresponding unit 1 event since larx instructions can only execute on unit 0)",
- .pme_event_ids = { 115, 113, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000100000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_THRD_PRIO_DIFF_5or6_CYC 206
+ .pme_long_desc = "A larx (lwarx or ldarx) was executed on side 0 (there is no corresponding unit 1 event since larx instructions can only execute on unit 0)",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LARX_LSU0],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LARX_LSU0]
+ },
[ POWER5_PME_PM_THRD_PRIO_DIFF_5or6_CYC ] = {
.pme_name = "PM_THRD_PRIO_DIFF_5or6_CYC",
+ .pme_code = 0x430e6,
.pme_short_desc = "Cycles thread priority difference is 5 or 6",
- .pme_long_desc = "Cycles thread priority difference is 5 or 6",
- .pme_event_ids = { -1, -1, 174, 180, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000040000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_SNOOP_RETRY_1AHEAD 207
+ .pme_long_desc = "Cycles when this thread's priority is higher than the other thread's priority by 5 or 6.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_DIFF_5or6_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_DIFF_5or6_CYC]
+ },
[ POWER5_PME_PM_SNOOP_RETRY_1AHEAD ] = {
.pme_name = "PM_SNOOP_RETRY_1AHEAD",
+ .pme_code = 0x725e6,
.pme_short_desc = "Snoop retry due to one ahead collision",
.pme_long_desc = "Snoop retry due to one ahead collision",
- .pme_event_ids = { 195, 189, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000040000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_RETRY_1AHEAD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_RETRY_1AHEAD]
},
-#define POWER5_PME_PM_FPU1_FSQRT 208
[ POWER5_PME_PM_FPU1_FSQRT ] = {
.pme_name = "PM_FPU1_FSQRT",
+ .pme_code = 0xc6,
.pme_short_desc = "FPU1 executed FSQRT instruction",
- .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp1 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 49, 48, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000040000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_LD_MISS_L1_LSU1 209
+ .pme_long_desc = "FPU1 has executed a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_FSQRT],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_FSQRT]
+ },
[ POWER5_PME_PM_MRK_LD_MISS_L1_LSU1 ] = {
.pme_name = "PM_MRK_LD_MISS_L1_LSU1",
- .pme_short_desc = "LSU1 L1 D cache load misses",
- .pme_long_desc = "A marked load, executing on unit 1, missed the dcache",
- .pme_event_ids = { 177, 176, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_FPU_FIN 210
+ .pme_code = 0x820e4,
+ .pme_short_desc = "LSU1 marked L1 D cache load misses",
+ .pme_long_desc = "Load references that miss the Level 1 Data cache, by LSU1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LD_MISS_L1_LSU1],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LD_MISS_L1_LSU1]
+ },
[ POWER5_PME_PM_MRK_FPU_FIN ] = {
.pme_name = "PM_MRK_FPU_FIN",
+ .pme_code = 0x300014,
.pme_short_desc = "Marked instruction FPU processing finished",
.pme_long_desc = "One of the Floating Point Units finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, -1, 136, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x8000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_FPU_FIN],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_FPU_FIN]
},
-#define POWER5_PME_PM_THRD_PRIO_5_CYC 211
[ POWER5_PME_PM_THRD_PRIO_5_CYC ] = {
.pme_name = "PM_THRD_PRIO_5_CYC",
+ .pme_code = 0x420e4,
.pme_short_desc = "Cycles thread running at priority level 5",
- .pme_long_desc = "Cycles thread running at priority level 5",
- .pme_event_ids = { 207, 201, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000080000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_DATA_FROM_LMEM 212
+ .pme_long_desc = "Cycles this thread was running at priority level 5.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_5_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_5_CYC]
+ },
[ POWER5_PME_PM_MRK_DATA_FROM_LMEM ] = {
.pme_name = "PM_MRK_DATA_FROM_LMEM",
+ .pme_code = 0x2c7087,
.pme_short_desc = "Marked data loaded from local memory",
- .pme_long_desc = "Marked data loaded from local memory",
- .pme_event_ids = { -1, 167, 133, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0100000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU1_FRSP_FCONV 213
+ .pme_long_desc = "The processor's Data Cache was reloaded due to a marked load from memory attached to the same module this proccessor is located on.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_LMEM],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_LMEM]
+ },
[ POWER5_PME_PM_FPU1_FRSP_FCONV ] = {
.pme_name = "PM_FPU1_FRSP_FCONV",
+ .pme_code = 0x10c5,
.pme_short_desc = "FPU1 executed FRSP or FCONV instructions",
- .pme_long_desc = "This signal is active for one cycle when fp1 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { -1, -1, 37, 42, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000900000ULL,
- 0x0000000000000080ULL }
- },
-#define POWER5_PME_PM_SNOOP_TLBIE 214
+ .pme_long_desc = "FPU1 has executed a frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_FRSP_FCONV],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_FRSP_FCONV]
+ },
[ POWER5_PME_PM_SNOOP_TLBIE ] = {
.pme_name = "PM_SNOOP_TLBIE",
+ .pme_code = 0x800c3,
.pme_short_desc = "Snoop TLBIE",
- .pme_long_desc = "A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.",
- .pme_event_ids = { 196, 190, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000400000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L3SB_SNOOP_RETRY 215
+ .pme_long_desc = "A tlbie was snooped from another processor.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_TLBIE],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_TLBIE]
+ },
[ POWER5_PME_PM_L3SB_SNOOP_RETRY ] = {
.pme_name = "PM_L3SB_SNOOP_RETRY",
+ .pme_code = 0x731e4,
.pme_short_desc = "L3 slice B snoop retries",
- .pme_long_desc = "L3 slice B snoop retries",
- .pme_event_ids = { -1, -1, 95, 99, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000800ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FAB_VBYPASS_EMPTY 216
+ .pme_long_desc = "Number of times an L3 retried a snoop because it got two in at the same time (one on snp_a, one on snp_b)",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SB_SNOOP_RETRY],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SB_SNOOP_RETRY]
+ },
[ POWER5_PME_PM_FAB_VBYPASS_EMPTY ] = {
.pme_name = "PM_FAB_VBYPASS_EMPTY",
+ .pme_code = 0x731e7,
.pme_short_desc = "Vertical bypass buffer empty",
- .pme_long_desc = "Vertical bypass buffer empty",
- .pme_event_ids = { -1, -1, 23, 28, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000004000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_DATA_FROM_L275_MOD 217
+ .pme_long_desc = "Fabric cycles when the Middle Bypass sidecar is empty. The signal is delivered at FBC speed and the count must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_VBYPASS_EMPTY],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_VBYPASS_EMPTY]
+ },
[ POWER5_PME_PM_MRK_DATA_FROM_L275_MOD ] = {
.pme_name = "PM_MRK_DATA_FROM_L275_MOD",
+ .pme_code = 0x1c70a3,
.pme_short_desc = "Marked data loaded from L2.75 modified",
- .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of another MCM due to a marked demand load. ",
- .pme_event_ids = { 162, -1, -1, 136, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0200000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_6INST_CLB_CYC 218
+ .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 on a different module than this processor is located due to a marked load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L275_MOD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L275_MOD]
+ },
[ POWER5_PME_PM_6INST_CLB_CYC ] = {
.pme_name = "PM_6INST_CLB_CYC",
+ .pme_code = 0x400c6,
.pme_short_desc = "Cycles 6 instructions in CLB",
- .pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.",
- .pme_event_ids = { 7, 6, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000010ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SB_RCST_DISP 219
+ .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_6INST_CLB_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_6INST_CLB_CYC]
+ },
[ POWER5_PME_PM_L2SB_RCST_DISP ] = {
.pme_name = "PM_L2SB_RCST_DISP",
- .pme_short_desc = "L2 Slice B RC store dispatch attempt",
- .pme_long_desc = "L2 Slice B RC store dispatch attempt",
- .pme_event_ids = { 93, 91, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000001ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FLUSH 220
+ .pme_code = 0x702c1,
+ .pme_short_desc = "L2 slice B RC store dispatch attempt",
+ .pme_long_desc = "A Read/Claim dispatch for a Store was attempted.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_RCST_DISP],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_RCST_DISP]
+ },
[ POWER5_PME_PM_FLUSH ] = {
.pme_name = "PM_FLUSH",
+ .pme_code = 0x110c7,
.pme_short_desc = "Flushes",
- .pme_long_desc = "Flushes",
- .pme_event_ids = { -1, -1, 26, 31, -1, -1 },
- .pme_group_vector = {
- 0x0001000000040000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SC_MOD_INV 221
+ .pme_long_desc = "Flushes occurred including LSU and Branch flushes.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FLUSH],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FLUSH]
+ },
[ POWER5_PME_PM_L2SC_MOD_INV ] = {
.pme_name = "PM_L2SC_MOD_INV",
+ .pme_code = 0x730e2,
.pme_short_desc = "L2 slice C transition from modified to invalid",
- .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.",
- .pme_event_ids = { -1, -1, 79, 83, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000400ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU_DENORM 222
+ .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_MOD_INV],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_MOD_INV]
+ },
[ POWER5_PME_PM_FPU_DENORM ] = {
.pme_name = "PM_FPU_DENORM",
+ .pme_code = 0x102088,
.pme_short_desc = "FPU received denormalized data",
- .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized. Combined Unit 0 + Unit 1",
- .pme_event_ids = { 54, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000010000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L3SC_HIT 223
+ .pme_long_desc = "The floating point unit has encountered a denormalized operand. Combined Unit 0 + Unit 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_DENORM],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_DENORM]
+ },
[ POWER5_PME_PM_L3SC_HIT ] = {
.pme_name = "PM_L3SC_HIT",
- .pme_short_desc = "L3 Slice C hits",
- .pme_long_desc = "L3 Slice C hits",
- .pme_event_ids = { -1, -1, 96, 100, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000002000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_SNOOP_WR_RETRY_RQ 224
+ .pme_code = 0x711c5,
+ .pme_short_desc = "L3 slice C hits",
+ .pme_long_desc = "Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 Slice",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SC_HIT],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SC_HIT]
+ },
[ POWER5_PME_PM_SNOOP_WR_RETRY_RQ ] = {
.pme_name = "PM_SNOOP_WR_RETRY_RQ",
+ .pme_code = 0x706c6,
.pme_short_desc = "Snoop write/dclaim retry due to collision with active read queue",
- .pme_long_desc = "Snoop write/dclaim retry due to collision with active read queue",
- .pme_event_ids = { 197, 191, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000080000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_IC_PREF_REQ 225
+ .pme_long_desc = "A snoop request for a write or dclaim to memory was retried because it matched the cacheline of an active read. This event is sent from the Memory Controller clock domain and must be scaled accordingly",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_WR_RETRY_RQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_WR_RETRY_RQ]
+ },
+ [ POWER5_PME_PM_LSU1_REJECT_SRQ ] = {
+ .pme_name = "PM_LSU1_REJECT_SRQ",
+ .pme_code = 0xc60e4,
+ .pme_short_desc = "LSU1 SRQ lhs rejects",
+ .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because of Load Hit Store conditions. Loads are rejected when data is needed from a previous store instruction but store forwarding is not possible because the data is not fully contained in the Store Data Queue or is not yet available in the Store Data Queue.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_REJECT_SRQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_REJECT_SRQ]
+ },
[ POWER5_PME_PM_IC_PREF_REQ ] = {
.pme_name = "PM_IC_PREF_REQ",
+ .pme_code = 0x220e6,
.pme_short_desc = "Instruction prefetch requests",
- .pme_long_desc = "Asserted when a non-canceled prefetch is made to the cache interface unit (CIU).",
- .pme_event_ids = { 71, 69, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000004000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000010ULL }
- },
-#define POWER5_PME_PM_L3SC_ALL_BUSY 226
+ .pme_long_desc = "An instruction prefetch request has been made.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_IC_PREF_REQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_IC_PREF_REQ]
+ },
[ POWER5_PME_PM_L3SC_ALL_BUSY ] = {
.pme_name = "PM_L3SC_ALL_BUSY",
+ .pme_code = 0x721e5,
.pme_short_desc = "L3 slice C active for every cycle all CI/CO machines busy",
- .pme_long_desc = "L3 slice C active for every cycle all CI/CO machines busy",
- .pme_event_ids = { 112, 110, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000002000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_GRP_IC_MISS 227
+ .pme_long_desc = "Cycles All Castin/Castout machines are busy.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SC_ALL_BUSY],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SC_ALL_BUSY]
+ },
[ POWER5_PME_PM_MRK_GRP_IC_MISS ] = {
.pme_name = "PM_MRK_GRP_IC_MISS",
+ .pme_code = 0x412091,
.pme_short_desc = "Group experienced marked I cache miss",
- .pme_long_desc = "Group experienced marked I cache miss",
- .pme_event_ids = { -1, -1, -1, 147, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0008000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_GCT_NOSLOT_IC_MISS 228
+ .pme_long_desc = "A group containing a marked (sampled) instruction experienced an instruction cache miss.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_GRP_IC_MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_GRP_IC_MISS]
+ },
[ POWER5_PME_PM_GCT_NOSLOT_IC_MISS ] = {
.pme_name = "PM_GCT_NOSLOT_IC_MISS",
+ .pme_code = 0x21009c,
.pme_short_desc = "No slot in GCT caused by I cache miss",
- .pme_long_desc = "This thread has no slot in the GCT because of an I cache miss",
- .pme_event_ids = { -1, 59, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000020ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_DATA_FROM_L3 229
+ .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because of an Instruction Cache miss.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_GCT_NOSLOT_IC_MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GCT_NOSLOT_IC_MISS]
+ },
[ POWER5_PME_PM_MRK_DATA_FROM_L3 ] = {
.pme_name = "PM_MRK_DATA_FROM_L3",
+ .pme_code = 0x1c708e,
.pme_short_desc = "Marked data loaded from L3",
- .pme_long_desc = "DL1 was reloaded from the local L3 due to a marked demand load",
- .pme_event_ids = { 163, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0040000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MEM_HI_PRIO_PW_CMPL 230
- [ POWER5_PME_PM_MEM_HI_PRIO_PW_CMPL ] = {
- .pme_name = "PM_MEM_HI_PRIO_PW_CMPL",
- .pme_short_desc = "High priority partial-write completed",
- .pme_long_desc = "High priority partial-write completed",
- .pme_event_ids = { 151, 149, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000100000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_GCT_NOSLOT_SRQ_FULL 231
+ .pme_long_desc = "The processor's Data Cache was reloaded from the local L3 due to a marked load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L3],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L3]
+ },
[ POWER5_PME_PM_GCT_NOSLOT_SRQ_FULL ] = {
.pme_name = "PM_GCT_NOSLOT_SRQ_FULL",
+ .pme_code = 0x310084,
.pme_short_desc = "No slot in GCT caused by SRQ full",
- .pme_long_desc = "This thread has no slot in the GCT because the SRQ is full",
- .pme_event_ids = { -1, -1, 46, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000020ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_THRD_SEL_OVER_ISU_HOLD 232
+ .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because the Store Request Queue (SRQ) is full. This happens when the storage subsystem can not process the stores in the SRQ. Groups can not be dispatched until a SRQ entry is available.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_GCT_NOSLOT_SRQ_FULL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GCT_NOSLOT_SRQ_FULL]
+ },
[ POWER5_PME_PM_THRD_SEL_OVER_ISU_HOLD ] = {
.pme_name = "PM_THRD_SEL_OVER_ISU_HOLD",
- .pme_short_desc = "Thread selection overides caused by ISU holds",
- .pme_long_desc = "Thread selection overides caused by ISU holds",
- .pme_event_ids = { -1, -1, 180, 186, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000001000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_CMPLU_STALL_DCACHE_MISS 233
+ .pme_code = 0x410c5,
+ .pme_short_desc = "Thread selection overrides caused by ISU holds",
+ .pme_long_desc = "Thread selection was overridden because of an ISU hold.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_SEL_OVER_ISU_HOLD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_SEL_OVER_ISU_HOLD]
+ },
[ POWER5_PME_PM_CMPLU_STALL_DCACHE_MISS ] = {
.pme_name = "PM_CMPLU_STALL_DCACHE_MISS",
+ .pme_code = 0x21109a,
.pme_short_desc = "Completion stall caused by D cache miss",
- .pme_long_desc = "Completion stall caused by D cache miss",
- .pme_event_ids = { -1, 10, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000020000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L3SA_MOD_INV 234
+ .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a Data Cache Miss. Data Cache Miss has higher priority than any other Load/Store delay, so if an instruction encounters multiple delays only the Data Cache Miss will be reported and the entire delay period will be charged to Data Cache Miss. This is a subset of PM_CMPLU_STALL_LSU.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_CMPLU_STALL_DCACHE_MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CMPLU_STALL_DCACHE_MISS]
+ },
[ POWER5_PME_PM_L3SA_MOD_INV ] = {
.pme_name = "PM_L3SA_MOD_INV",
+ .pme_code = 0x730e3,
.pme_short_desc = "L3 slice A transition from modified to invalid",
- .pme_long_desc = "L3 slice A transition from modified to invalid",
- .pme_event_ids = { -1, -1, 89, 93, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000020ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU_FLUSH_LRQ 235
+ .pme_long_desc = "L3 snooper detects someone doing a store to a line that is truly M in this L3 (i.e. L3 going M=>I) Mu|Me are not included since they are formed due to a prev read op. Tx is not included since it is considered shared at this point.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SA_MOD_INV],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SA_MOD_INV]
+ },
[ POWER5_PME_PM_LSU_FLUSH_LRQ ] = {
.pme_name = "PM_LSU_FLUSH_LRQ",
+ .pme_code = 0x2c0090,
.pme_short_desc = "LRQ flushes",
- .pme_long_desc = "A load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { -1, 138, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000200000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_THRD_PRIO_2_CYC 236
+ .pme_long_desc = "A load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. Combined Units 0 and 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_FLUSH_LRQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_FLUSH_LRQ]
+ },
[ POWER5_PME_PM_THRD_PRIO_2_CYC ] = {
.pme_name = "PM_THRD_PRIO_2_CYC",
+ .pme_code = 0x420e1,
.pme_short_desc = "Cycles thread running at priority level 2",
- .pme_long_desc = "Cycles thread running at priority level 2",
- .pme_event_ids = { 204, 198, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000080000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU_FLUSH_SRQ 237
+ .pme_long_desc = "Cycles this thread was running at priority level 2.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_2_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_2_CYC]
+ },
[ POWER5_PME_PM_LSU_FLUSH_SRQ ] = {
.pme_name = "PM_LSU_FLUSH_SRQ",
+ .pme_code = 0x1c0090,
.pme_short_desc = "SRQ flushes",
- .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { 141, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000200000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_LSU_SRQ_INST_VALID 238
+ .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. Combined Unit 0 + 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_FLUSH_SRQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_FLUSH_SRQ]
+ },
[ POWER5_PME_PM_MRK_LSU_SRQ_INST_VALID ] = {
.pme_name = "PM_MRK_LSU_SRQ_INST_VALID",
+ .pme_code = 0xc70e6,
.pme_short_desc = "Marked instruction valid in SRQ",
.pme_long_desc = "This signal is asserted every cycle when a marked request is resident in the Store Request Queue",
- .pme_event_ids = { -1, -1, 149, 161, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000010ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU_SRQ_INST_VALID],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU_SRQ_INST_VALID]
},
-#define POWER5_PME_PM_L3SA_REF 239
[ POWER5_PME_PM_L3SA_REF ] = {
.pme_name = "PM_L3SA_REF",
+ .pme_code = 0x701c3,
.pme_short_desc = "L3 slice A references",
- .pme_long_desc = "L3 slice A references",
- .pme_event_ids = { 108, 106, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000001000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL 240
+ .pme_long_desc = "Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice ",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SA_REF],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SA_REF]
+ },
[ POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL ] = {
.pme_name = "PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL",
- .pme_short_desc = "L2 Slice C RC dispatch attempt failed due to all CO busy",
- .pme_long_desc = "L2 Slice C RC dispatch attempt failed due to all CO busy",
- .pme_event_ids = { -1, -1, 84, 88, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000010ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU0_STALL3 241
+ .pme_code = 0x713c2,
+ .pme_short_desc = "L2 slice C RC dispatch attempt failed due to all CO busy",
+ .pme_long_desc = "A Read/Claim dispatch was rejected because all Castout machines were busy.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL]
+ },
[ POWER5_PME_PM_FPU0_STALL3 ] = {
.pme_name = "PM_FPU0_STALL3",
+ .pme_code = 0x20e1,
.pme_short_desc = "FPU0 stalled in pipe3",
- .pme_long_desc = "This signal indicates that fp0 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. ",
- .pme_event_ids = { 43, 42, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000200000ULL,
- 0x0000000000000040ULL }
- },
-#define POWER5_PME_PM_GPR_MAP_FULL_CYC 242
+ .pme_long_desc = "FPU0 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always).",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_STALL3],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_STALL3]
+ },
[ POWER5_PME_PM_GPR_MAP_FULL_CYC ] = {
.pme_name = "PM_GPR_MAP_FULL_CYC",
+ .pme_code = 0x130e5,
.pme_short_desc = "Cycles GPR mapper full",
- .pme_long_desc = "The ISU sends a signal indicating that the gpr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.",
- .pme_event_ids = { -1, -1, 48, 53, -1, -1 },
- .pme_group_vector = {
- 0x0000000400000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_TB_BIT_TRANS 243
+ .pme_long_desc = "The General Purpose Register mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_GPR_MAP_FULL_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GPR_MAP_FULL_CYC]
+ },
[ POWER5_PME_PM_TB_BIT_TRANS ] = {
.pme_name = "PM_TB_BIT_TRANS",
+ .pme_code = 0x100018,
.pme_short_desc = "Time Base bit transition",
.pme_long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 ",
- .pme_event_ids = { 201, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_TB_BIT_TRANS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_TB_BIT_TRANS]
},
-#define POWER5_PME_PM_MRK_LSU_FLUSH_LRQ 244
[ POWER5_PME_PM_MRK_LSU_FLUSH_LRQ ] = {
.pme_name = "PM_MRK_LSU_FLUSH_LRQ",
+ .pme_code = 0x381088,
.pme_short_desc = "Marked LRQ flushes",
.pme_long_desc = "A marked load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { -1, -1, 147, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000008000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU_FLUSH_LRQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU_FLUSH_LRQ]
},
-#define POWER5_PME_PM_FPU0_STF 245
[ POWER5_PME_PM_FPU0_STF ] = {
.pme_name = "PM_FPU0_STF",
+ .pme_code = 0x20e2,
.pme_short_desc = "FPU0 executed store instruction",
- .pme_long_desc = "This signal is active for one cycle when fp0 is executing a store instruction.",
- .pme_event_ids = { 44, 43, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000002000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_DTLB_MISS 246
+ .pme_long_desc = "FPU0 has executed a Floating Point Store instruction.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_STF],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_STF]
+ },
[ POWER5_PME_PM_MRK_DTLB_MISS ] = {
.pme_name = "PM_MRK_DTLB_MISS",
+ .pme_code = 0xc50c6,
.pme_short_desc = "Marked Data TLB misses",
- .pme_long_desc = "Marked Data TLB misses",
- .pme_event_ids = { -1, -1, 135, 145, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0800000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU1_FMA 247
+ .pme_long_desc = "Data TLB references by a marked instruction that missed the TLB (all page sizes).",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DTLB_MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DTLB_MISS]
+ },
[ POWER5_PME_PM_FPU1_FMA ] = {
.pme_name = "PM_FPU1_FMA",
+ .pme_code = 0xc5,
.pme_short_desc = "FPU1 executed multiply-add instruction",
- .pme_long_desc = "This signal is active for one cycle when fp1 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 48, 47, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000800000ULL,
- 0x0000000000000080ULL }
- },
-#define POWER5_PME_PM_L2SA_MOD_TAG 248
+ .pme_long_desc = "The floating point unit has executed a multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_FMA],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_FMA]
+ },
[ POWER5_PME_PM_L2SA_MOD_TAG ] = {
.pme_name = "PM_L2SA_MOD_TAG",
+ .pme_code = 0x720e0,
.pme_short_desc = "L2 slice A transition from modified to tagged",
- .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.",
- .pme_event_ids = { 82, 80, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000100ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU1_FLUSH_ULD 249
+ .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_MOD_TAG],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_MOD_TAG]
+ },
[ POWER5_PME_PM_LSU1_FLUSH_ULD ] = {
.pme_name = "PM_LSU1_FLUSH_ULD",
+ .pme_code = 0xc00c4,
.pme_short_desc = "LSU1 unaligned load flushes",
- .pme_long_desc = "A load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { 132, 130, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000002000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_LSU0_FLUSH_UST 250
+ .pme_long_desc = "A load was flushed from unit 1 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1).",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_FLUSH_ULD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_FLUSH_ULD]
+ },
[ POWER5_PME_PM_MRK_LSU0_FLUSH_UST ] = {
.pme_name = "PM_MRK_LSU0_FLUSH_UST",
+ .pme_code = 0x810c1,
.pme_short_desc = "LSU0 marked unaligned store flushes",
.pme_long_desc = "A marked store was flushed from unit 0 because it was unaligned",
- .pme_event_ids = { -1, -1, 141, 152, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU0_FLUSH_UST],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU0_FLUSH_UST]
},
-#define POWER5_PME_PM_MRK_INST_FIN 251
[ POWER5_PME_PM_MRK_INST_FIN ] = {
.pme_name = "PM_MRK_INST_FIN",
+ .pme_code = 0x300005,
.pme_short_desc = "Marked instruction finished",
- .pme_long_desc = "One of the execution units finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, -1, 137, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0004000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU0_FULL_CYC 252
+ .pme_long_desc = "One of the execution units finished a marked instruction. Instructions that finish may not necessary complete",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_INST_FIN],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_INST_FIN]
+ },
[ POWER5_PME_PM_FPU0_FULL_CYC ] = {
.pme_name = "PM_FPU0_FULL_CYC",
+ .pme_code = 0x100c3,
.pme_short_desc = "Cycles FPU0 issue queue full",
- .pme_long_desc = "The issue queue for FPU unit 0 cannot accept any more instructions. Issue is stopped",
- .pme_event_ids = { 41, 40, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000200000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU_LRQ_S0_ALLOC 253
+ .pme_long_desc = "The issue queue for FPU0 cannot accept any more instruction. Dispatch to this issue queue is stopped.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_FULL_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_FULL_CYC]
+ },
[ POWER5_PME_PM_LSU_LRQ_S0_ALLOC ] = {
.pme_name = "PM_LSU_LRQ_S0_ALLOC",
+ .pme_code = 0xc20e6,
.pme_short_desc = "LRQ slot 0 allocated",
.pme_long_desc = "LRQ slot zero was allocated",
- .pme_event_ids = { 143, 142, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000080ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_LRQ_S0_ALLOC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_LRQ_S0_ALLOC]
},
-#define POWER5_PME_PM_MRK_LSU1_FLUSH_ULD 254
[ POWER5_PME_PM_MRK_LSU1_FLUSH_ULD ] = {
.pme_name = "PM_MRK_LSU1_FLUSH_ULD",
+ .pme_code = 0x810c4,
.pme_short_desc = "LSU1 marked unaligned load flushes",
.pme_long_desc = "A marked load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { -1, -1, 145, 156, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU1_FLUSH_ULD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU1_FLUSH_ULD]
+ },
+ [ POWER5_PME_PM_MRK_DTLB_REF ] = {
+ .pme_name = "PM_MRK_DTLB_REF",
+ .pme_code = 0x1c4090,
+ .pme_short_desc = "Marked Data TLB reference",
+ .pme_long_desc = "Total number of Data TLB references by a marked instruction for all page sizes. Page size is determined at TLB reload time.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DTLB_REF],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DTLB_REF]
},
-#define POWER5_PME_PM_BR_UNCOND 255
[ POWER5_PME_PM_BR_UNCOND ] = {
.pme_name = "PM_BR_UNCOND",
+ .pme_code = 0x123087,
.pme_short_desc = "Unconditional branch",
- .pme_long_desc = "Unconditional branch",
- .pme_event_ids = { 9, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000020000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000020ULL }
- },
-#define POWER5_PME_PM_THRD_SEL_OVER_L2MISS 256
+ .pme_long_desc = "An unconditional branch was executed.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_BR_UNCOND],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_BR_UNCOND]
+ },
[ POWER5_PME_PM_THRD_SEL_OVER_L2MISS ] = {
.pme_name = "PM_THRD_SEL_OVER_L2MISS",
- .pme_short_desc = "Thread selection overides caused by L2 misses",
- .pme_long_desc = "Thread selection overides caused by L2 misses",
- .pme_event_ids = { -1, -1, 181, 187, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000001000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SB_SHR_INV 257
+ .pme_code = 0x410c3,
+ .pme_short_desc = "Thread selection overrides caused by L2 misses",
+ .pme_long_desc = "Thread selection was overridden because one thread was had a L2 miss pending.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_SEL_OVER_L2MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_SEL_OVER_L2MISS]
+ },
[ POWER5_PME_PM_L2SB_SHR_INV ] = {
.pme_name = "PM_L2SB_SHR_INV",
+ .pme_code = 0x710c1,
.pme_short_desc = "L2 slice B transition from shared to invalid",
- .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.",
- .pme_event_ids = { -1, -1, 77, 81, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000200ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MEM_LO_PRIO_WR_CMPL 258
+ .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A, B, and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_SHR_INV],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_SHR_INV]
+ },
[ POWER5_PME_PM_MEM_LO_PRIO_WR_CMPL ] = {
.pme_name = "PM_MEM_LO_PRIO_WR_CMPL",
+ .pme_code = 0x736e6,
.pme_short_desc = "Low priority write completed",
- .pme_long_desc = "Low priority write completed",
- .pme_event_ids = { -1, -1, 122, 127, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000080000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L3SC_MOD_TAG 259
+ .pme_long_desc = "A memory write, which was not upgraded to high priority, completed. This event is sent from the Memory Controller clock domain and must be scaled accordingly",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_LO_PRIO_WR_CMPL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_LO_PRIO_WR_CMPL]
+ },
[ POWER5_PME_PM_L3SC_MOD_TAG ] = {
.pme_name = "PM_L3SC_MOD_TAG",
+ .pme_code = 0x720e5,
.pme_short_desc = "L3 slice C transition from modified to TAG",
- .pme_long_desc = "L3 slice C transition from modified to TAG",
- .pme_event_ids = { 113, 111, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000080ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_ST_MISS_L1 260
+ .pme_long_desc = "L3 snooper detects someone doing a read to a line that is truly M in this L3(i.e. L3 going M->T or M->I(go_Mu case); Mu|Me are not included since they are formed due to a prev read op). Tx is not included since it is considered shared at this point.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SC_MOD_TAG],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SC_MOD_TAG]
+ },
[ POWER5_PME_PM_MRK_ST_MISS_L1 ] = {
.pme_name = "PM_MRK_ST_MISS_L1",
+ .pme_code = 0x820e3,
.pme_short_desc = "Marked L1 D cache store misses",
.pme_long_desc = "A marked store missed the dcache",
- .pme_event_ids = { 180, 179, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x4004000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_ST_MISS_L1],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_ST_MISS_L1]
},
-#define POWER5_PME_PM_GRP_DISP_SUCCESS 261
[ POWER5_PME_PM_GRP_DISP_SUCCESS ] = {
.pme_name = "PM_GRP_DISP_SUCCESS",
+ .pme_code = 0x300002,
.pme_short_desc = "Group dispatch success",
.pme_long_desc = "Number of groups sucessfully dispatched (not rejected)",
- .pme_event_ids = { -1, -1, 51, -1, -1, -1 },
- .pme_group_vector = {
- 0x0800000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_DISP_SUCCESS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_DISP_SUCCESS]
},
-#define POWER5_PME_PM_THRD_PRIO_DIFF_1or2_CYC 262
[ POWER5_PME_PM_THRD_PRIO_DIFF_1or2_CYC ] = {
.pme_name = "PM_THRD_PRIO_DIFF_1or2_CYC",
+ .pme_code = 0x430e4,
.pme_short_desc = "Cycles thread priority difference is 1 or 2",
- .pme_long_desc = "Cycles thread priority difference is 1 or 2",
- .pme_event_ids = { -1, -1, 172, 178, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000020000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_IC_DEMAND_L2_BHT_REDIRECT 263
+ .pme_long_desc = "Cycles when this thread's priority is higher than the other thread's priority by 1 or 2.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_DIFF_1or2_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_DIFF_1or2_CYC]
+ },
[ POWER5_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = {
.pme_name = "PM_IC_DEMAND_L2_BHT_REDIRECT",
+ .pme_code = 0x230e0,
.pme_short_desc = "L2 I cache demand request due to BHT redirect",
- .pme_long_desc = "L2 I cache demand request due to BHT redirect",
- .pme_event_ids = { -1, -1, 52, 56, -1, -1 },
- .pme_group_vector = {
- 0x0000002000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU0_SINGLE 264
+ .pme_long_desc = "A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict).",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_IC_DEMAND_L2_BHT_REDIRECT],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_IC_DEMAND_L2_BHT_REDIRECT]
+ },
+ [ POWER5_PME_PM_MEM_WQ_DISP_Q8to15 ] = {
+ .pme_name = "PM_MEM_WQ_DISP_Q8to15",
+ .pme_code = 0x733e6,
+ .pme_short_desc = "Memory write queue dispatched to queues 8-15",
+ .pme_long_desc = "A memory operation was dispatched to a write queue in the range between 8 and 15. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_WQ_DISP_Q8to15],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_WQ_DISP_Q8to15]
+ },
[ POWER5_PME_PM_FPU0_SINGLE ] = {
.pme_name = "PM_FPU0_SINGLE",
+ .pme_code = 0x20e3,
.pme_short_desc = "FPU0 executed single precision instruction",
- .pme_long_desc = "This signal is active for one cycle when fp0 is executing single precision instruction.",
- .pme_event_ids = { 42, 41, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000400000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU_DERAT_MISS 265
+ .pme_long_desc = "FPU0 has executed a single precision instruction.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_SINGLE],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_SINGLE]
+ },
[ POWER5_PME_PM_LSU_DERAT_MISS ] = {
.pme_name = "PM_LSU_DERAT_MISS",
+ .pme_code = 0x280090,
.pme_short_desc = "DERAT misses",
- .pme_long_desc = "Total D-ERAT Misses (Unit 0 + Unit 1). Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.",
- .pme_event_ids = { -1, 137, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000100000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_THRD_PRIO_1_CYC 266
+ .pme_long_desc = "Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_DERAT_MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_DERAT_MISS]
+ },
[ POWER5_PME_PM_THRD_PRIO_1_CYC ] = {
.pme_name = "PM_THRD_PRIO_1_CYC",
+ .pme_code = 0x420e0,
.pme_short_desc = "Cycles thread running at priority level 1",
- .pme_long_desc = "Cycles thread running at priority level 1",
- .pme_event_ids = { 203, 197, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000100000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SC_RCST_DISP_FAIL_OTHER 267
+ .pme_long_desc = "Cycles this thread was running at priority level 1. Priority level 1 is the lowest and indicates the thread is sleeping.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_1_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_1_CYC]
+ },
[ POWER5_PME_PM_L2SC_RCST_DISP_FAIL_OTHER ] = {
.pme_name = "PM_L2SC_RCST_DISP_FAIL_OTHER",
- .pme_short_desc = "L2 Slice C RC store dispatch attempt failed due to other reasons",
- .pme_long_desc = "L2 Slice C RC store dispatch attempt failed due to other reasons",
- .pme_event_ids = { -1, -1, 83, 87, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000008ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU1_FEST 268
+ .pme_code = 0x732e2,
+ .pme_short_desc = "L2 slice C RC store dispatch attempt failed due to other reasons",
+ .pme_long_desc = "A Read/Claim dispatch for a store failed for some reason other than Full or Collision conditions. Rejected dispatches do not count because they have not yet been attempted.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_RCST_DISP_FAIL_OTHER],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_RCST_DISP_FAIL_OTHER]
+ },
[ POWER5_PME_PM_FPU1_FEST ] = {
.pme_name = "PM_FPU1_FEST",
+ .pme_code = 0x10c6,
.pme_short_desc = "FPU1 executed FEST instruction",
- .pme_long_desc = "This signal is active for one cycle when fp1 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ",
- .pme_event_ids = { -1, -1, 34, 39, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000040000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FAB_HOLDtoVN_EMPTY 269
+ .pme_long_desc = "FPU1 has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_FEST],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_FEST]
+ },
[ POWER5_PME_PM_FAB_HOLDtoVN_EMPTY ] = {
.pme_name = "PM_FAB_HOLDtoVN_EMPTY",
+ .pme_code = 0x721e7,
.pme_short_desc = "Hold buffer to VN empty",
- .pme_long_desc = "Hold buffer to VN empty",
- .pme_event_ids = { 30, 29, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000004000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_SNOOP_RD_RETRY_RQ 270
+ .pme_long_desc = "Fabric cycles when the Vertical Node out hold-buffers are emtpy. The signal is delivered at FBC speed and the count must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_HOLDtoVN_EMPTY],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_HOLDtoVN_EMPTY]
+ },
[ POWER5_PME_PM_SNOOP_RD_RETRY_RQ ] = {
.pme_name = "PM_SNOOP_RD_RETRY_RQ",
+ .pme_code = 0x705c6,
.pme_short_desc = "Snoop read retry due to collision with active read queue",
- .pme_long_desc = "Snoop read retry due to collision with active read queue",
- .pme_event_ids = { 194, 188, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000040000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_SNOOP_DCLAIM_RETRY_QFULL 271
+ .pme_long_desc = "A snoop request for a read from memory was retried because it matched the cache line of an active read. The snoop request is retried because the L2 may be able to source data via intervention for the 2nd read faster than the MC. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_RD_RETRY_RQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_RD_RETRY_RQ]
+ },
[ POWER5_PME_PM_SNOOP_DCLAIM_RETRY_QFULL ] = {
.pme_name = "PM_SNOOP_DCLAIM_RETRY_QFULL",
+ .pme_code = 0x720e6,
.pme_short_desc = "Snoop dclaim/flush retry due to write/dclaim queues full",
- .pme_long_desc = "Snoop dclaim/flush retry due to write/dclaim queues full",
- .pme_event_ids = { 191, 185, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000020000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_DATA_FROM_L25_SHR_CYC 272
+ .pme_long_desc = "The memory controller A memory write was dispatched to a write queue. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_DCLAIM_RETRY_QFULL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_DCLAIM_RETRY_QFULL]
+ },
[ POWER5_PME_PM_MRK_DATA_FROM_L25_SHR_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L25_SHR_CYC",
+ .pme_code = 0x2c70a2,
.pme_short_desc = "Marked load latency from L2.5 shared",
- .pme_long_desc = "Marked load latency from L2.5 shared",
- .pme_event_ids = { -1, 160, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0020000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_ST_CMPL_INT 273
+ .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L25_SHR_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L25_SHR_CYC]
+ },
[ POWER5_PME_PM_MRK_ST_CMPL_INT ] = {
.pme_name = "PM_MRK_ST_CMPL_INT",
+ .pme_code = 0x300003,
.pme_short_desc = "Marked store completed with intervention",
.pme_long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention",
- .pme_event_ids = { -1, -1, 150, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x2000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_ST_CMPL_INT],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_ST_CMPL_INT]
},
-#define POWER5_PME_PM_FLUSH_BR_MPRED 274
[ POWER5_PME_PM_FLUSH_BR_MPRED ] = {
.pme_name = "PM_FLUSH_BR_MPRED",
+ .pme_code = 0x110c6,
.pme_short_desc = "Flush caused by branch mispredict",
- .pme_long_desc = "Flush caused by branch mispredict",
- .pme_event_ids = { -1, -1, 24, 29, -1, -1 },
- .pme_group_vector = {
- 0x0000040000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR 275
+ .pme_long_desc = "A flush was caused by a branch mispredict.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FLUSH_BR_MPRED],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FLUSH_BR_MPRED]
+ },
[ POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR ] = {
.pme_name = "PM_L2SB_RCLD_DISP_FAIL_ADDR",
- .pme_short_desc = "L2 Slice B RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ",
- .pme_long_desc = "L2 Slice B RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ",
- .pme_event_ids = { -1, -1, 72, 76, -1, -1 },
- .pme_group_vector = {
- 0x8000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU_STF 276
+ .pme_code = 0x711c1,
+ .pme_short_desc = "L2 slice B RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ",
+ .pme_long_desc = "A Read/Claim dispatch for a load failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR]
+ },
[ POWER5_PME_PM_FPU_STF ] = {
.pme_name = "PM_FPU_STF",
+ .pme_code = 0x202090,
.pme_short_desc = "FPU executed store instruction",
- .pme_long_desc = "FPU is executing a store instruction. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, 56, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000020000ULL,
- 0x0000000000002400ULL }
- },
-#define POWER5_PME_PM_CMPLU_STALL_FPU 277
+ .pme_long_desc = "FPU has executed a store instruction. Combined Unit 0 + Unit 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_STF],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_STF]
+ },
[ POWER5_PME_PM_CMPLU_STALL_FPU ] = {
.pme_name = "PM_CMPLU_STALL_FPU",
+ .pme_code = 0x411098,
.pme_short_desc = "Completion stall caused by FPU instruction",
- .pme_long_desc = "Completion stall caused by FPU instruction",
- .pme_event_ids = { -1, -1, -1, 9, -1, -1 },
- .pme_group_vector = {
- 0x0000000080000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU_REJECT_SRQ_LHS 278
- [ POWER5_PME_PM_LSU_REJECT_SRQ_LHS ] = {
- .pme_name = "PM_LSU_REJECT_SRQ_LHS",
- .pme_short_desc = "LSU SRQ rejects",
- .pme_long_desc = "LSU reject due to load hit store",
- .pme_event_ids = { 146, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000040000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC 279
+ .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a floating point instruction.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_CMPLU_STALL_FPU],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CMPLU_STALL_FPU]
+ },
[ POWER5_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC ] = {
.pme_name = "PM_THRD_PRIO_DIFF_minus1or2_CYC",
+ .pme_code = 0x430e2,
.pme_short_desc = "Cycles thread priority difference is -1 or -2",
- .pme_long_desc = "Cycles thread priority difference is -1 or -2",
- .pme_event_ids = { -1, -1, 175, 181, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000080000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_GCT_NOSLOT_CYC 280
+ .pme_long_desc = "Cycles when this thread's priority is lower than the other thread's priority by 1 or 2.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC]
+ },
[ POWER5_PME_PM_GCT_NOSLOT_CYC ] = {
.pme_name = "PM_GCT_NOSLOT_CYC",
+ .pme_code = 0x100004,
.pme_short_desc = "Cycles no GCT slot allocated",
- .pme_long_desc = "Cycles this thread does not have any slots allocated in the GCT.",
- .pme_event_ids = { 60, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000020ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FXU0_BUSY_FXU1_IDLE 281
+ .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_GCT_NOSLOT_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GCT_NOSLOT_CYC]
+ },
[ POWER5_PME_PM_FXU0_BUSY_FXU1_IDLE ] = {
.pme_name = "PM_FXU0_BUSY_FXU1_IDLE",
+ .pme_code = 0x300012,
.pme_short_desc = "FXU0 busy FXU1 idle",
.pme_long_desc = "FXU0 is busy while FXU1 was idle",
- .pme_event_ids = { -1, -1, 42, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000004000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FXU0_BUSY_FXU1_IDLE],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FXU0_BUSY_FXU1_IDLE]
},
-#define POWER5_PME_PM_PTEG_FROM_L35_SHR 282
[ POWER5_PME_PM_PTEG_FROM_L35_SHR ] = {
.pme_name = "PM_PTEG_FROM_L35_SHR",
+ .pme_code = 0x18309e,
.pme_short_desc = "PTEG loaded from L3.5 shared",
- .pme_long_desc = "PTEG loaded from L3.5 shared",
- .pme_event_ids = { 187, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0200000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MEM_PWQ_DISP_BUSY2or3 283
- [ POWER5_PME_PM_MEM_PWQ_DISP_BUSY2or3 ] = {
- .pme_name = "PM_MEM_PWQ_DISP_BUSY2or3",
- .pme_short_desc = "Memory partial-write queue dispatched with 2-3 queues busy",
- .pme_long_desc = "Memory partial-write queue dispatched with 2-3 queues busy",
- .pme_event_ids = { 154, 152, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0001000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_LSU_FLUSH_UST 284
+ .pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (S) data from the L3 of a chip on the same module as this processor is located, due to a demand load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_L35_SHR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_L35_SHR]
+ },
[ POWER5_PME_PM_MRK_LSU_FLUSH_UST ] = {
.pme_name = "PM_MRK_LSU_FLUSH_UST",
+ .pme_code = 0x381090,
.pme_short_desc = "Marked unaligned store flushes",
.pme_long_desc = "A marked store was flushed because it was unaligned",
- .pme_event_ids = { -1, -1, 148, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x4000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU_FLUSH_UST],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU_FLUSH_UST]
},
-#define POWER5_PME_PM_L3SA_HIT 285
[ POWER5_PME_PM_L3SA_HIT ] = {
.pme_name = "PM_L3SA_HIT",
+ .pme_code = 0x711c3,
.pme_short_desc = "L3 slice A hits",
- .pme_long_desc = "L3 slice A hits",
- .pme_event_ids = { -1, -1, 88, 92, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000001000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_DATA_FROM_L25_SHR 286
+ .pme_long_desc = "Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 slice",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SA_HIT],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SA_HIT]
+ },
[ POWER5_PME_PM_MRK_DATA_FROM_L25_SHR ] = {
.pme_name = "PM_MRK_DATA_FROM_L25_SHR",
+ .pme_code = 0x1c7097,
.pme_short_desc = "Marked data loaded from L2.5 shared",
- .pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a marked demand load",
- .pme_event_ids = { 161, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0020000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SB_RCST_DISP_FAIL_ADDR 287
+ .pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from the L2 of a chip on the same module as this processor is located due to a marked load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L25_SHR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L25_SHR]
+ },
[ POWER5_PME_PM_L2SB_RCST_DISP_FAIL_ADDR ] = {
.pme_name = "PM_L2SB_RCST_DISP_FAIL_ADDR",
- .pme_short_desc = "L2 Slice B RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ",
- .pme_long_desc = "L2 Slice B RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ",
- .pme_event_ids = { -1, -1, 74, 78, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000001ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_DATA_FROM_L35_SHR 288
+ .pme_code = 0x712c1,
+ .pme_short_desc = "L2 slice B RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ",
+ .pme_long_desc = "A Read/Claim dispatch for a store failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_RCST_DISP_FAIL_ADDR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_RCST_DISP_FAIL_ADDR]
+ },
[ POWER5_PME_PM_MRK_DATA_FROM_L35_SHR ] = {
.pme_name = "PM_MRK_DATA_FROM_L35_SHR",
+ .pme_code = 0x1c709e,
.pme_short_desc = "Marked data loaded from L3.5 shared",
- .pme_long_desc = "Marked data loaded from L3.5 shared",
- .pme_event_ids = { 164, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0100000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_IERAT_XLATE_WR 289
+ .pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on the same module as this processor is located due to a marked load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L35_SHR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L35_SHR]
+ },
[ POWER5_PME_PM_IERAT_XLATE_WR ] = {
.pme_name = "PM_IERAT_XLATE_WR",
+ .pme_code = 0x220e7,
.pme_short_desc = "Translation written to ierat",
- .pme_long_desc = "This signal will be asserted each time the I-ERAT is written. This indicates that an ERAT miss has been serviced. ERAT misses will initiate a sequence resulting in the ERAT being written. ERAT misses that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed, This should be a fairly accurate count of ERAT missed (best available).",
- .pme_event_ids = { 72, 70, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000004000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SA_ST_REQ 290
+ .pme_long_desc = "An entry was written into the IERAT as a result of an IERAT miss. This event can be used to count IERAT misses. An ERAT miss that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_IERAT_XLATE_WR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_IERAT_XLATE_WR]
+ },
[ POWER5_PME_PM_L2SA_ST_REQ ] = {
.pme_name = "PM_L2SA_ST_REQ",
+ .pme_code = 0x723e0,
.pme_short_desc = "L2 slice A store requests",
- .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C.",
- .pme_event_ids = { 89, 87, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x4000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_THRD_SEL_T1 291
+ .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A, B, and C.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_ST_REQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_ST_REQ]
+ },
[ POWER5_PME_PM_THRD_SEL_T1 ] = {
.pme_name = "PM_THRD_SEL_T1",
+ .pme_code = 0x410c1,
.pme_short_desc = "Decode selected thread 1",
- .pme_long_desc = "Decode selected thread 1",
- .pme_event_ids = { -1, -1, 183, 189, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000400000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_IC_DEMAND_L2_BR_REDIRECT 292
+ .pme_long_desc = "Thread selection picked thread 1 for decode.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_SEL_T1],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_SEL_T1]
+ },
[ POWER5_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = {
.pme_name = "PM_IC_DEMAND_L2_BR_REDIRECT",
+ .pme_code = 0x230e1,
.pme_short_desc = "L2 I cache demand request due to branch redirect",
- .pme_long_desc = "L2 I cache demand request due to branch redirect",
- .pme_event_ids = { -1, -1, 53, 57, -1, -1 },
- .pme_group_vector = {
- 0x0000002000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_INST_FROM_LMEM 293
+ .pme_long_desc = "A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target).",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_IC_DEMAND_L2_BR_REDIRECT],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_IC_DEMAND_L2_BR_REDIRECT]
+ },
[ POWER5_PME_PM_INST_FROM_LMEM ] = {
.pme_name = "PM_INST_FROM_LMEM",
+ .pme_code = 0x222086,
.pme_short_desc = "Instruction fetched from local memory",
- .pme_long_desc = "Instruction fetched from local memory",
- .pme_event_ids = { -1, 77, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0020000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_DC_PREF_STREAM_ALLOC_BLK 294
- [ POWER5_PME_PM_DC_PREF_STREAM_ALLOC_BLK ] = {
- .pme_name = "PM_DC_PREF_STREAM_ALLOC_BLK",
- .pme_short_desc = "D cache out of prefech streams",
- .pme_long_desc = "D cache out of prefech streams",
- .pme_event_ids = { -1, -1, 117, 121, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000400ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU0_1FLOP 295
+ .pme_long_desc = "An instruction fetch group was fetched from memory attached to the same module this proccessor is located on. Fetch groups can contain up to 8 instructions",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_LMEM],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_LMEM]
+ },
[ POWER5_PME_PM_FPU0_1FLOP ] = {
.pme_name = "PM_FPU0_1FLOP",
+ .pme_code = 0xc3,
.pme_short_desc = "FPU0 executed add",
.pme_long_desc = " mult",
- .pme_event_ids = { 36, 35, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000001000000ULL,
- 0x0000000000000100ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_1FLOP],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_1FLOP]
},
-#define POWER5_PME_PM_MRK_DATA_FROM_L35_SHR_CYC 296
[ POWER5_PME_PM_MRK_DATA_FROM_L35_SHR_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L35_SHR_CYC",
+ .pme_code = 0x2c70a6,
.pme_short_desc = "Marked load latency from L3.5 shared",
- .pme_long_desc = "Marked load latency from L3.5 shared",
- .pme_event_ids = { -1, 164, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0100000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_PTEG_FROM_L2 297
+ .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L35_SHR_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L35_SHR_CYC]
+ },
[ POWER5_PME_PM_PTEG_FROM_L2 ] = {
.pme_name = "PM_PTEG_FROM_L2",
+ .pme_code = 0x183087,
.pme_short_desc = "PTEG loaded from L2",
- .pme_long_desc = "PTEG loaded from L2",
- .pme_event_ids = { 183, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0400000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MEM_PW_CMPL 298
+ .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local L2 due to a demand load",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_L2],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_L2]
+ },
[ POWER5_PME_PM_MEM_PW_CMPL ] = {
.pme_name = "PM_MEM_PW_CMPL",
+ .pme_code = 0x724e6,
.pme_short_desc = "Memory partial-write completed",
- .pme_long_desc = "Memory partial-write completed",
- .pme_event_ids = { -1, -1, 123, 128, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0001000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC 299
+ .pme_long_desc = "Number of Partial Writes completed. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_PW_CMPL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_PW_CMPL]
+ },
[ POWER5_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC ] = {
.pme_name = "PM_THRD_PRIO_DIFF_minus5or6_CYC",
+ .pme_code = 0x430e0,
.pme_short_desc = "Cycles thread priority difference is -5 or -6",
- .pme_long_desc = "Cycles thread priority difference is -5 or -6",
- .pme_event_ids = { -1, -1, 177, 183, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000100000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER 300
+ .pme_long_desc = "Cycles when this thread's priority is lower than the other thread's priority by 5 or 6.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC]
+ },
[ POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER ] = {
.pme_name = "PM_L2SB_RCLD_DISP_FAIL_OTHER",
- .pme_short_desc = "L2 Slice B RC load dispatch attempt failed due to other reasons",
- .pme_long_desc = "L2 Slice B RC load dispatch attempt failed due to other reasons",
- .pme_event_ids = { -1, -1, 73, 77, -1, -1 },
- .pme_group_vector = {
- 0x8000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU0_FIN 301
+ .pme_code = 0x731e1,
+ .pme_short_desc = "L2 slice B RC load dispatch attempt failed due to other reasons",
+ .pme_long_desc = "A Read/Claim dispatch for a load failed for some reason other than Full or Collision conditions.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER]
+ },
[ POWER5_PME_PM_FPU0_FIN ] = {
.pme_name = "PM_FPU0_FIN",
+ .pme_code = 0x10c3,
.pme_short_desc = "FPU0 produced a result",
- .pme_long_desc = "fp0 finished, produced a result This only indicates finish, not completion. ",
- .pme_event_ids = { -1, -1, 30, 35, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000001010000ULL,
- 0x0000000000000540ULL }
- },
-#define POWER5_PME_PM_MRK_DTLB_MISS_4K 302
+ .pme_long_desc = "FPU0 finished, produced a result. This only indicates finish, not completion. Floating Point Stores are included in this count but not Floating Point Loads.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_FIN],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_FIN]
+ },
[ POWER5_PME_PM_MRK_DTLB_MISS_4K ] = {
.pme_name = "PM_MRK_DTLB_MISS_4K",
+ .pme_code = 0xc40c1,
.pme_short_desc = "Marked Data TLB misses for 4K page",
- .pme_long_desc = "Marked Data TLB misses for 4K page",
- .pme_event_ids = { 168, 169, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0800000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L3SC_SHR_INV 303
+ .pme_long_desc = "Data TLB references to 4KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DTLB_MISS_4K],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DTLB_MISS_4K]
+ },
[ POWER5_PME_PM_L3SC_SHR_INV ] = {
.pme_name = "PM_L3SC_SHR_INV",
+ .pme_code = 0x710c5,
.pme_short_desc = "L3 slice C transition from shared to invalid",
- .pme_long_desc = "L3 slice C transition from shared to invalid",
- .pme_event_ids = { -1, -1, 98, 102, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000080ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_GRP_BR_REDIR 304
+ .pme_long_desc = "L3 snooper detects someone doing a store to a line that is Sx in this L3(i.e. invalidate hit SX and dispatched).",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SC_SHR_INV],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SC_SHR_INV]
+ },
[ POWER5_PME_PM_GRP_BR_REDIR ] = {
.pme_name = "PM_GRP_BR_REDIR",
+ .pme_code = 0x120e6,
.pme_short_desc = "Group experienced branch redirect",
- .pme_long_desc = "Group experienced branch redirect",
- .pme_event_ids = { 63, 62, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000040000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL 305
+ .pme_long_desc = "Number of groups, counted at dispatch, that have encountered a branch redirect. Every group constructed from a fetch group that has been redirected will count.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_BR_REDIR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_BR_REDIR]
+ },
[ POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL ] = {
.pme_name = "PM_L2SC_RCLD_DISP_FAIL_RC_FULL",
- .pme_short_desc = "L2 Slice C RC load dispatch attempt failed due to all RC full",
- .pme_long_desc = "L2 Slice C RC load dispatch attempt failed due to all RC full",
- .pme_event_ids = { 100, 98, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000004ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_LSU_FLUSH_SRQ 306
+ .pme_code = 0x721e2,
+ .pme_short_desc = "L2 slice C RC load dispatch attempt failed due to all RC full",
+ .pme_long_desc = "A Read/Claim dispatch for a load failed because all RC machines are busy.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL]
+ },
[ POWER5_PME_PM_MRK_LSU_FLUSH_SRQ ] = {
.pme_name = "PM_MRK_LSU_FLUSH_SRQ",
- .pme_short_desc = "Marked SRQ flushes",
+ .pme_code = 0x481088,
+ .pme_short_desc = "Marked SRQ lhs flushes",
.pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { -1, -1, -1, 159, -1, -1 },
- .pme_group_vector = {
- 0x0000000000004000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU_FLUSH_SRQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU_FLUSH_SRQ]
},
-#define POWER5_PME_PM_PTEG_FROM_L275_SHR 307
[ POWER5_PME_PM_PTEG_FROM_L275_SHR ] = {
.pme_name = "PM_PTEG_FROM_L275_SHR",
+ .pme_code = 0x383097,
.pme_short_desc = "PTEG loaded from L2.75 shared",
- .pme_long_desc = "PTEG loaded from L2.75 shared",
- .pme_event_ids = { -1, -1, 154, -1, -1, -1 },
- .pme_group_vector = {
- 0x0100000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL 308
+ .pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (T) data from the L2 on a different module than this processor is located due to a demand load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_L275_SHR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_L275_SHR]
+ },
[ POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL ] = {
.pme_name = "PM_L2SB_RCLD_DISP_FAIL_RC_FULL",
- .pme_short_desc = "L2 Slice B RC load dispatch attempt failed due to all RC full",
- .pme_long_desc = "L2 Slice B RC load dispatch attempt failed due to all RC full",
- .pme_event_ids = { 92, 90, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x8000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_SNOOP_RD_RETRY_WQ 309
+ .pme_code = 0x721e1,
+ .pme_short_desc = "L2 slice B RC load dispatch attempt failed due to all RC full",
+ .pme_long_desc = "A Read/Claim dispatch for a load failed because all RC machines are busy.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL]
+ },
[ POWER5_PME_PM_SNOOP_RD_RETRY_WQ ] = {
.pme_name = "PM_SNOOP_RD_RETRY_WQ",
+ .pme_code = 0x715c6,
.pme_short_desc = "Snoop read retry due to collision with active write queue",
- .pme_long_desc = "Snoop read retry due to collision with active write queue",
- .pme_event_ids = { -1, -1, 160, 168, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000040000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU0_NCLD 310
+ .pme_long_desc = "A snoop request for a read from memory was retried because it matched the cache line of an active write. The snoop request is retried and the active write is changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_RD_RETRY_WQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_RD_RETRY_WQ]
+ },
[ POWER5_PME_PM_LSU0_NCLD ] = {
.pme_name = "PM_LSU0_NCLD",
+ .pme_code = 0xc50c1,
.pme_short_desc = "LSU0 non-cacheable loads",
- .pme_long_desc = "LSU0 non-cacheable loads",
- .pme_event_ids = { -1, -1, 106, 110, -1, -1 },
- .pme_group_vector = {
- 0x0000001000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FAB_DCLAIM_RETRIED 311
+ .pme_long_desc = "A non-cacheable load was executed by unit 0.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_NCLD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_NCLD]
+ },
[ POWER5_PME_PM_FAB_DCLAIM_RETRIED ] = {
.pme_name = "PM_FAB_DCLAIM_RETRIED",
+ .pme_code = 0x730e7,
.pme_short_desc = "dclaim retried",
- .pme_long_desc = "dclaim retried",
- .pme_event_ids = { -1, -1, 18, 23, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000002000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU1_BUSY_REJECT 312
+ .pme_long_desc = "A DCLAIM command was retried. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_DCLAIM_RETRIED],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_DCLAIM_RETRIED]
+ },
[ POWER5_PME_PM_LSU1_BUSY_REJECT ] = {
.pme_name = "PM_LSU1_BUSY_REJECT",
+ .pme_code = 0xc20e7,
.pme_short_desc = "LSU1 busy due to reject",
- .pme_long_desc = "LSU unit 1 is busy due to reject",
- .pme_event_ids = { 128, 126, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000002000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FXLS0_FULL_CYC 313
+ .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_BUSY_REJECT],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_BUSY_REJECT]
+ },
[ POWER5_PME_PM_FXLS0_FULL_CYC ] = {
.pme_name = "PM_FXLS0_FULL_CYC",
+ .pme_code = 0x110c0,
.pme_short_desc = "Cycles FXU0/LS0 queue full",
- .pme_long_desc = "The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped",
- .pme_event_ids = { -1, -1, 40, 45, -1, -1 },
- .pme_group_vector = {
- 0x0000000200000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU0_FEST 314
+ .pme_long_desc = "The issue queue that feeds the Fixed Point unit 0 / Load Store Unit 0 is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FXLS0_FULL_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FXLS0_FULL_CYC]
+ },
[ POWER5_PME_PM_FPU0_FEST ] = {
.pme_name = "PM_FPU0_FEST",
+ .pme_code = 0x10c2,
.pme_short_desc = "FPU0 executed FEST instruction",
- .pme_long_desc = "This signal is active for one cycle when fp0 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ",
- .pme_event_ids = { -1, -1, 29, 34, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000040000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_DTLB_REF_16M 315
+ .pme_long_desc = "FPU0 has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_FEST],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_FEST]
+ },
[ POWER5_PME_PM_DTLB_REF_16M ] = {
.pme_name = "PM_DTLB_REF_16M",
+ .pme_code = 0xc40c6,
.pme_short_desc = "Data TLB reference for 16M page",
- .pme_long_desc = "Data TLB reference for 16M page",
- .pme_event_ids = { 25, 24, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000800000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR 316
+ .pme_long_desc = "Data TLB references for 16MB pages. Includes hits + misses.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DTLB_REF_16M],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DTLB_REF_16M]
+ },
[ POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR ] = {
.pme_name = "PM_L2SC_RCLD_DISP_FAIL_ADDR",
- .pme_short_desc = "L2 Slice C RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ",
- .pme_long_desc = "L2 Slice C RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ",
- .pme_event_ids = { -1, -1, 80, 84, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000004ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU0_REJECT_ERAT_MISS 317
+ .pme_code = 0x711c2,
+ .pme_short_desc = "L2 slice C RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ",
+ .pme_long_desc = "A Read/Claim dispatch for a load failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR]
+ },
[ POWER5_PME_PM_LSU0_REJECT_ERAT_MISS ] = {
.pme_name = "PM_LSU0_REJECT_ERAT_MISS",
+ .pme_code = 0xc60e3,
.pme_short_desc = "LSU0 reject due to ERAT miss",
- .pme_long_desc = "LSU0 reject due to ERAT miss",
- .pme_event_ids = { 123, 121, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000010000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_DATA_FROM_L25_MOD 318
+ .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions due to an ERAT miss. Requests that miss the Derat are rejected and retried until the request hits in the Erat.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_REJECT_ERAT_MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_REJECT_ERAT_MISS]
+ },
[ POWER5_PME_PM_DATA_FROM_L25_MOD ] = {
.pme_name = "PM_DATA_FROM_L25_MOD",
+ .pme_code = 0x2c3097,
.pme_short_desc = "Data loaded from L2.5 modified",
- .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a demand load",
- .pme_event_ids = { -1, 16, 7, -1, -1, -1 },
- .pme_group_vector = {
- 0x0004000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_GCT_USAGE_60to79_CYC 319
+ .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 of a chip on the same module as this processor is located due to a demand load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_L25_MOD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_L25_MOD]
+ },
[ POWER5_PME_PM_GCT_USAGE_60to79_CYC ] = {
.pme_name = "PM_GCT_USAGE_60to79_CYC",
+ .pme_code = 0x20001f,
.pme_short_desc = "Cycles GCT 60-79% full",
- .pme_long_desc = "Cycles GCT 60-79% full",
- .pme_event_ids = { -1, 61, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000040ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_DATA_FROM_L375_MOD 320
+ .pme_long_desc = "Cycles when the Global Completion Table has between 60% and 70% of its slots used. The GCT has 20 entries shared between threads.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_GCT_USAGE_60to79_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GCT_USAGE_60to79_CYC]
+ },
[ POWER5_PME_PM_DATA_FROM_L375_MOD ] = {
.pme_name = "PM_DATA_FROM_L375_MOD",
+ .pme_code = 0x1c30a7,
.pme_short_desc = "Data loaded from L3.75 modified",
- .pme_long_desc = "Data loaded from L3.75 modified",
- .pme_event_ids = { 18, -1, -1, 14, -1, -1 },
- .pme_group_vector = {
- 0x0008000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 321
+ .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on the same module as this processor is located due to a demand load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_L375_MOD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_L375_MOD]
+ },
[ POWER5_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = {
.pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC",
+ .pme_code = 0x200015,
.pme_short_desc = "Cycles LMQ and SRQ empty",
.pme_long_desc = "Cycles when both the LMQ and SRQ are empty (LSU is idle)",
- .pme_event_ids = { -1, 141, 115, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000200ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC]
},
-#define POWER5_PME_PM_LSU0_REJECT_RELOAD_CDF 322
[ POWER5_PME_PM_LSU0_REJECT_RELOAD_CDF ] = {
.pme_name = "PM_LSU0_REJECT_RELOAD_CDF",
+ .pme_code = 0xc60e2,
.pme_short_desc = "LSU0 reject due to reload CDF or tag update collision",
- .pme_long_desc = "LSU0 reject due to reload CDF or tag update collision",
- .pme_event_ids = { 125, 123, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000008000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_0INST_FETCH 323
+ .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because of Critical Data Forward. When critical data arrives from the storage system it is formatted and immediately forwarded, bypassing the data cache, to the destination register using the result bus. Any instruction the requires the result bus in the same cycle is rejected. Tag update rejects are caused when an instruction requires access to the Dcache directory or ERAT in the same system when they are being updated.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_REJECT_RELOAD_CDF],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_REJECT_RELOAD_CDF]
+ },
[ POWER5_PME_PM_0INST_FETCH ] = {
.pme_name = "PM_0INST_FETCH",
+ .pme_code = 0x42208d,
.pme_short_desc = "No instructions fetched",
.pme_long_desc = "No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)",
- .pme_event_ids = { -1, -1, -1, 0, -1, -1 },
- .pme_group_vector = {
- 0x0020004000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_0INST_FETCH],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_0INST_FETCH]
},
-#define POWER5_PME_PM_LSU1_REJECT_RELOAD_CDF 324
[ POWER5_PME_PM_LSU1_REJECT_RELOAD_CDF ] = {
.pme_name = "PM_LSU1_REJECT_RELOAD_CDF",
+ .pme_code = 0xc60e6,
.pme_short_desc = "LSU1 reject due to reload CDF or tag update collision",
- .pme_long_desc = "LSU1 reject due to reload CDF or tag update collision",
- .pme_event_ids = { 136, 134, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000008000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L1_PREF 325
+ .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because of Critical Data Forward. When critical data arrives from the storage system it is formatted and immediately forwarded, bypassing the data cache, to the destination register using the result bus. Any instruction the requires the result bus in the same cycle is rejected. Tag update rejects are caused when an instruction requires access to the Dcache directory or ERAT in the same system when they are being updated.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_REJECT_RELOAD_CDF],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_REJECT_RELOAD_CDF]
+ },
[ POWER5_PME_PM_L1_PREF ] = {
.pme_name = "PM_L1_PREF",
+ .pme_code = 0xc70e7,
.pme_short_desc = "L1 cache data prefetches",
.pme_long_desc = "A request to prefetch data into the L1 was made",
- .pme_event_ids = { -1, -1, 61, 65, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000800ULL,
- 0x0000000000000000ULL,
- 0x0000000000000010ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L1_PREF],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L1_PREF]
+ },
+ [ POWER5_PME_PM_MEM_WQ_DISP_Q0to7 ] = {
+ .pme_name = "PM_MEM_WQ_DISP_Q0to7",
+ .pme_code = 0x723e6,
+ .pme_short_desc = "Memory write queue dispatched to queues 0-7",
+ .pme_long_desc = "A memory operation was dispatched to a write queue in the range between 0 and 7. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_WQ_DISP_Q0to7],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_WQ_DISP_Q0to7]
},
-#define POWER5_PME_PM_MRK_DATA_FROM_LMEM_CYC 326
[ POWER5_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_LMEM_CYC",
+ .pme_code = 0x4c70a0,
.pme_short_desc = "Marked load latency from local memory",
- .pme_long_desc = "Marked load latency from local memory",
- .pme_event_ids = { -1, -1, -1, 141, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0100000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_BRQ_FULL_CYC 327
+ .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_LMEM_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_LMEM_CYC]
+ },
[ POWER5_PME_PM_BRQ_FULL_CYC ] = {
.pme_name = "PM_BRQ_FULL_CYC",
+ .pme_code = 0x100c5,
.pme_short_desc = "Cycles branch queue full",
- .pme_long_desc = "The ISU sends a signal indicating that the issue queue that feeds the ifu br unit cannot accept any more group (queue is full of groups).",
- .pme_event_ids = { 8, 7, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000100000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_GRP_IC_MISS_NONSPEC 328
+ .pme_long_desc = "Cycles when the issue queue that feeds the branch unit is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_BRQ_FULL_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_BRQ_FULL_CYC]
+ },
[ POWER5_PME_PM_GRP_IC_MISS_NONSPEC ] = {
.pme_name = "PM_GRP_IC_MISS_NONSPEC",
+ .pme_code = 0x112099,
.pme_short_desc = "Group experienced non-speculative I cache miss",
- .pme_long_desc = "Group experienced non-speculative I cache miss",
- .pme_event_ids = { 69, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000008000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_PTEG_FROM_L275_MOD 329
+ .pme_long_desc = "Number of groups, counted at completion, that have encountered an instruction cache miss.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_IC_MISS_NONSPEC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_IC_MISS_NONSPEC]
+ },
[ POWER5_PME_PM_PTEG_FROM_L275_MOD ] = {
.pme_name = "PM_PTEG_FROM_L275_MOD",
+ .pme_code = 0x1830a3,
.pme_short_desc = "PTEG loaded from L2.75 modified",
- .pme_long_desc = "PTEG loaded from L2.75 modified",
- .pme_event_ids = { 185, -1, -1, 163, -1, -1 },
- .pme_group_vector = {
- 0x0100000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_LD_MISS_L1_LSU0 330
+ .pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L2 on a different module than this processor is located due to a demand load. ",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_L275_MOD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_L275_MOD]
+ },
[ POWER5_PME_PM_MRK_LD_MISS_L1_LSU0 ] = {
.pme_name = "PM_MRK_LD_MISS_L1_LSU0",
- .pme_short_desc = "LSU0 L1 D cache load misses",
- .pme_long_desc = "A marked load, executing on unit 0, missed the dcache",
- .pme_event_ids = { 176, 175, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_DATA_FROM_L375_SHR_CYC 331
+ .pme_code = 0x820e0,
+ .pme_short_desc = "LSU0 marked L1 D cache load misses",
+ .pme_long_desc = "Load references that miss the Level 1 Data cache, by LSU0.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LD_MISS_L1_LSU0],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LD_MISS_L1_LSU0]
+ },
[ POWER5_PME_PM_MRK_DATA_FROM_L375_SHR_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L375_SHR_CYC",
+ .pme_code = 0x2c70a7,
.pme_short_desc = "Marked load latency from L3.75 shared",
- .pme_long_desc = "Marked load latency from L3.75 shared",
- .pme_event_ids = { -1, 165, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0400000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU_FLUSH 332
+ .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L375_SHR_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L375_SHR_CYC]
+ },
[ POWER5_PME_PM_LSU_FLUSH ] = {
.pme_name = "PM_LSU_FLUSH",
+ .pme_code = 0x110c5,
.pme_short_desc = "Flush initiated by LSU",
- .pme_long_desc = "Flush initiated by LSU",
- .pme_event_ids = { -1, -1, 109, 113, -1, -1 },
- .pme_group_vector = {
- 0x0000000006e40000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_DATA_FROM_L3 333
+ .pme_long_desc = "A flush was initiated by the Load Store Unit",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_FLUSH],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_FLUSH]
+ },
[ POWER5_PME_PM_DATA_FROM_L3 ] = {
.pme_name = "PM_DATA_FROM_L3",
+ .pme_code = 0x1c308e,
.pme_short_desc = "Data loaded from L3",
- .pme_long_desc = "DL1 was reloaded from the local L3 due to a demand load",
- .pme_event_ids = { 16, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0003000000000000ULL,
- 0x0000000000000000ULL,
- 0x000000000000000aULL }
- },
-#define POWER5_PME_PM_INST_FROM_L2 334
+ .pme_long_desc = "The processor's Data Cache was reloaded from the local L3 due to a demand load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_L3],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_L3]
+ },
[ POWER5_PME_PM_INST_FROM_L2 ] = {
.pme_name = "PM_INST_FROM_L2",
- .pme_short_desc = "Instructions fetched from L2",
+ .pme_code = 0x122086,
+ .pme_short_desc = "Instruction fetched from L2",
.pme_long_desc = "An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions",
- .pme_event_ids = { 76, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0020000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L2],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L2]
},
-#define POWER5_PME_PM_PMC2_OVERFLOW 335
[ POWER5_PME_PM_PMC2_OVERFLOW ] = {
.pme_name = "PM_PMC2_OVERFLOW",
+ .pme_code = 0x30000a,
.pme_short_desc = "PMC2 Overflow",
- .pme_long_desc = "PMC2 Overflow",
- .pme_event_ids = { -1, -1, 151, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU0_DENORM 336
+ .pme_long_desc = "Overflows from PMC2 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_PMC2_OVERFLOW],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PMC2_OVERFLOW]
+ },
[ POWER5_PME_PM_FPU0_DENORM ] = {
.pme_name = "PM_FPU0_DENORM",
+ .pme_code = 0x20e0,
.pme_short_desc = "FPU0 received denormalized data",
- .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.",
- .pme_event_ids = { 37, 36, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000080000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU1_FMOV_FEST 337
+ .pme_long_desc = "FPU0 has encountered a denormalized operand. ",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_DENORM],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_DENORM]
+ },
[ POWER5_PME_PM_FPU1_FMOV_FEST ] = {
.pme_name = "PM_FPU1_FMOV_FEST",
- .pme_short_desc = "FPU1 executing FMOV or FEST instructions",
- .pme_long_desc = "This signal is active for one cycle when fp1 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ",
- .pme_event_ids = { -1, -1, 36, 41, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000080000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_INST_FETCH_CYC 338
+ .pme_code = 0x10c4,
+ .pme_short_desc = "FPU1 executed FMOV or FEST instructions",
+ .pme_long_desc = "FPU1 has executed a move kind of instruction or one of the estimate instructions. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_FMOV_FEST],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_FMOV_FEST]
+ },
[ POWER5_PME_PM_INST_FETCH_CYC ] = {
.pme_name = "PM_INST_FETCH_CYC",
+ .pme_code = 0x220e4,
.pme_short_desc = "Cycles at least 1 instruction fetched",
- .pme_long_desc = "Asserted each cycle when the IFU sends at least one instruction to the IDU. ",
- .pme_event_ids = { 75, 73, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000400ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU0_REJECT_SRQ_LHS 339
- [ POWER5_PME_PM_LSU0_REJECT_SRQ_LHS ] = {
- .pme_name = "PM_LSU0_REJECT_SRQ_LHS",
- .pme_short_desc = "LSU0 SRQ rejects",
- .pme_long_desc = "LSU0 reject due to load hit store",
- .pme_event_ids = { 126, 124, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000002000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU_LDF 340
+ .pme_long_desc = "Cycles when at least one instruction was sent from the fetch unit to the decode unit.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FETCH_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FETCH_CYC]
+ },
[ POWER5_PME_PM_LSU_LDF ] = {
.pme_name = "PM_LSU_LDF",
+ .pme_code = 0x4c5090,
.pme_short_desc = "LSU executed Floating Point load instruction",
- .pme_long_desc = "LSU executed Floating Point load instruction",
- .pme_event_ids = { -1, -1, -1, 115, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000020000ULL,
- 0x0000000000002000ULL }
- },
-#define POWER5_PME_PM_INST_DISP 341
+ .pme_long_desc = "LSU executed Floating Point load instruction. Combined Unit 0 + 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_LDF],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_LDF]
+ },
[ POWER5_PME_PM_INST_DISP ] = {
.pme_name = "PM_INST_DISP",
+ .pme_code = 0x300009,
.pme_short_desc = "Instructions dispatched",
- .pme_long_desc = "The ISU sends the number of instructions dispatched.",
- .pme_event_ids = { 74, 72, 56, 60, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000005ULL,
- 0x0000000000000000ULL,
- 0x0000000000006000ULL }
- },
-#define POWER5_PME_PM_DATA_FROM_L25_SHR 342
+ .pme_long_desc = "Number of PowerPC instructions successfully dispatched.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_DISP],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_DISP]
+ },
[ POWER5_PME_PM_DATA_FROM_L25_SHR ] = {
.pme_name = "PM_DATA_FROM_L25_SHR",
+ .pme_code = 0x1c3097,
.pme_short_desc = "Data loaded from L2.5 shared",
- .pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a demand load",
- .pme_event_ids = { 14, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0004000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L1_DCACHE_RELOAD_VALID 343
+ .pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from the L2 of a chip on the same module as this processor is located due to a demand load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_L25_SHR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_L25_SHR]
+ },
[ POWER5_PME_PM_L1_DCACHE_RELOAD_VALID ] = {
.pme_name = "PM_L1_DCACHE_RELOAD_VALID",
+ .pme_code = 0xc30e4,
.pme_short_desc = "L1 reload data source valid",
- .pme_long_desc = "The data source information is valid",
- .pme_event_ids = { -1, -1, 60, 64, -1, -1 },
- .pme_group_vector = {
- 0x0000008000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MEM_WQ_DISP_DCLAIM 344
+ .pme_long_desc = "The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L1_DCACHE_RELOAD_VALID],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L1_DCACHE_RELOAD_VALID]
+ },
[ POWER5_PME_PM_MEM_WQ_DISP_DCLAIM ] = {
.pme_name = "PM_MEM_WQ_DISP_DCLAIM",
+ .pme_code = 0x713c6,
.pme_short_desc = "Memory write queue dispatched due to dclaim/flush",
- .pme_long_desc = "Memory write queue dispatched due to dclaim/flush",
- .pme_event_ids = { -1, -1, 128, 133, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000800000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU_FULL_CYC 345
+ .pme_long_desc = "A memory dclaim or flush operation was dispatched to a write queue. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_WQ_DISP_DCLAIM],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_WQ_DISP_DCLAIM]
+ },
[ POWER5_PME_PM_FPU_FULL_CYC ] = {
.pme_name = "PM_FPU_FULL_CYC",
+ .pme_code = 0x110090,
.pme_short_desc = "Cycles FPU issue queue full",
- .pme_long_desc = "Cycles when one or both FPU issue queues are full",
- .pme_event_ids = { 57, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000080000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_GRP_ISSUED 346
+ .pme_long_desc = "Cycles when one or both FPU issue queues are full. Combined Unit 0 + 1. Use with caution since this is the sum of cycles when Unit 0 was full plus Unit 1 full. It does not indicate when both units were full.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_FULL_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_FULL_CYC]
+ },
[ POWER5_PME_PM_MRK_GRP_ISSUED ] = {
.pme_name = "PM_MRK_GRP_ISSUED",
+ .pme_code = 0x100015,
.pme_short_desc = "Marked group issued",
- .pme_long_desc = "A sampled instruction was issued",
- .pme_event_ids = { 172, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0008000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_THRD_PRIO_3_CYC 347
+ .pme_long_desc = "A sampled instruction was issued.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_GRP_ISSUED],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_GRP_ISSUED]
+ },
[ POWER5_PME_PM_THRD_PRIO_3_CYC ] = {
.pme_name = "PM_THRD_PRIO_3_CYC",
+ .pme_code = 0x420e2,
.pme_short_desc = "Cycles thread running at priority level 3",
- .pme_long_desc = "Cycles thread running at priority level 3",
- .pme_event_ids = { 205, 199, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000040000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU_FMA 348
+ .pme_long_desc = "Cycles this thread was running at priority level 3.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_3_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_3_CYC]
+ },
[ POWER5_PME_PM_FPU_FMA ] = {
.pme_name = "PM_FPU_FMA",
+ .pme_code = 0x200088,
.pme_short_desc = "FPU executed multiply-add instruction",
- .pme_long_desc = "This signal is active for one cycle when FPU is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, 54, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000004000ULL,
- 0x0000000000010200ULL }
- },
-#define POWER5_PME_PM_INST_FROM_L35_MOD 349
+ .pme_long_desc = "This signal is active for one cycle when FPU is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_FMA],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_FMA]
+ },
[ POWER5_PME_PM_INST_FROM_L35_MOD ] = {
.pme_name = "PM_INST_FROM_L35_MOD",
+ .pme_code = 0x22209d,
.pme_short_desc = "Instruction fetched from L3.5 modified",
- .pme_long_desc = "Instruction fetched from L3.5 modified",
- .pme_event_ids = { -1, 76, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0080000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_CRU_FIN 350
+ .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L3 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L35_MOD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L35_MOD]
+ },
[ POWER5_PME_PM_MRK_CRU_FIN ] = {
.pme_name = "PM_MRK_CRU_FIN",
+ .pme_code = 0x400005,
.pme_short_desc = "Marked instruction CRU processing finished",
- .pme_long_desc = "The Condition Register Unit finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, -1, -1, 134, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x2000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_SNOOP_WR_RETRY_WQ 351
+ .pme_long_desc = "The Condition Register Unit finished a marked instruction. Instructions that finish may not necessary complete.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_CRU_FIN],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_CRU_FIN]
+ },
[ POWER5_PME_PM_SNOOP_WR_RETRY_WQ ] = {
.pme_name = "PM_SNOOP_WR_RETRY_WQ",
+ .pme_code = 0x716c6,
.pme_short_desc = "Snoop write/dclaim retry due to collision with active write queue",
- .pme_long_desc = "Snoop write/dclaim retry due to collision with active write queue",
- .pme_event_ids = { -1, -1, 162, 170, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000080000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_CMPLU_STALL_REJECT 352
+ .pme_long_desc = "A snoop request for a write or dclaim to memory was retried because it matched the cache line of an active write. The snoop request is retried and the active write is changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_WR_RETRY_WQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_WR_RETRY_WQ]
+ },
[ POWER5_PME_PM_CMPLU_STALL_REJECT ] = {
.pme_name = "PM_CMPLU_STALL_REJECT",
+ .pme_code = 0x41109a,
.pme_short_desc = "Completion stall caused by reject",
- .pme_long_desc = "Completion stall caused by reject",
- .pme_event_ids = { -1, -1, -1, 10, -1, -1 },
- .pme_group_vector = {
- 0x0000000010000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU1_REJECT_ERAT_MISS 353
+ .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a load/store reject. This is a subset of PM_CMPLU_STALL_LSU.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_CMPLU_STALL_REJECT],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CMPLU_STALL_REJECT]
+ },
[ POWER5_PME_PM_LSU1_REJECT_ERAT_MISS ] = {
.pme_name = "PM_LSU1_REJECT_ERAT_MISS",
+ .pme_code = 0xc60e7,
.pme_short_desc = "LSU1 reject due to ERAT miss",
- .pme_long_desc = "LSU1 reject due to ERAT miss",
- .pme_event_ids = { 134, 132, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000010000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SB_RCST_DISP_FAIL_OTHER 354
+ .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions due to an ERAT miss. Requests that miss the Derat are rejected and retried until the request hits in the Erat.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_REJECT_ERAT_MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_REJECT_ERAT_MISS]
+ },
+ [ POWER5_PME_PM_MRK_FXU_FIN ] = {
+ .pme_name = "PM_MRK_FXU_FIN",
+ .pme_code = 0x200014,
+ .pme_short_desc = "Marked instruction FXU processing finished",
+ .pme_long_desc = "One of the Fixed Point Units finished a marked instruction. Instructions that finish may not necessary complete.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_FXU_FIN],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_FXU_FIN]
+ },
[ POWER5_PME_PM_L2SB_RCST_DISP_FAIL_OTHER ] = {
.pme_name = "PM_L2SB_RCST_DISP_FAIL_OTHER",
- .pme_short_desc = "L2 Slice B RC store dispatch attempt failed due to other reasons",
- .pme_long_desc = "L2 Slice B RC store dispatch attempt failed due to other reasons",
- .pme_event_ids = { -1, -1, 75, 79, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000001ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY 355
+ .pme_code = 0x732e1,
+ .pme_short_desc = "L2 slice B RC store dispatch attempt failed due to other reasons",
+ .pme_long_desc = "A Read/Claim dispatch for a store failed for some reason other than Full or Collision conditions. Rejected dispatches do not count because they have not yet been attempted.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_RCST_DISP_FAIL_OTHER],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_RCST_DISP_FAIL_OTHER]
+ },
[ POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY ] = {
.pme_name = "PM_L2SC_RC_DISP_FAIL_CO_BUSY",
- .pme_short_desc = "L2 Slice C RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy",
- .pme_long_desc = "L2 Slice C RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy",
- .pme_event_ids = { 103, 101, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000010ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_PMC4_OVERFLOW 356
+ .pme_code = 0x703c2,
+ .pme_short_desc = "L2 slice C RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy",
+ .pme_long_desc = "A Read/Claim Dispatch was rejected at dispatch because the Castout Machine was busy. In the case of an RC starting up on a miss and the victim is valid, the CO machine must be available for the RC to process the access. If the CO is still busy working on an old castout, then the RC must not-ack the access if it is a miss(re-issued by the CIU). If it is a miss and the CO is available to process the castout, the RC will accept the access. Once the RC has finished, it can restart and process new accesses that result in a hit (or miss that doesn't need a CO) even though the CO is still processing a castout from a previous access.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY]
+ },
[ POWER5_PME_PM_PMC4_OVERFLOW ] = {
.pme_name = "PM_PMC4_OVERFLOW",
+ .pme_code = 0x10000a,
.pme_short_desc = "PMC4 Overflow",
- .pme_long_desc = "PMC4 Overflow",
- .pme_event_ids = { 181, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L3SA_SNOOP_RETRY 357
+ .pme_long_desc = "Overflows from PMC4 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_PMC4_OVERFLOW],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PMC4_OVERFLOW]
+ },
[ POWER5_PME_PM_L3SA_SNOOP_RETRY ] = {
.pme_name = "PM_L3SA_SNOOP_RETRY",
+ .pme_code = 0x731e3,
.pme_short_desc = "L3 slice A snoop retries",
- .pme_long_desc = "L3 slice A snoop retries",
- .pme_event_ids = { -1, -1, 91, 95, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000800ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_INST_FROM_L25_MOD 358
- [ POWER5_PME_PM_INST_FROM_L25_MOD ] = {
- .pme_name = "PM_INST_FROM_L25_MOD",
- .pme_short_desc = "Instruction fetched from L2.5 modified",
- .pme_long_desc = "Instruction fetched from L2.5 modified",
- .pme_event_ids = { -1, 75, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0040000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_PTEG_FROM_L35_MOD 359
+ .pme_long_desc = "Number of times an L3 retried a snoop because it got two in at the same time (one on snp_a, one on snp_b)",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SA_SNOOP_RETRY],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SA_SNOOP_RETRY]
+ },
[ POWER5_PME_PM_PTEG_FROM_L35_MOD ] = {
.pme_name = "PM_PTEG_FROM_L35_MOD",
+ .pme_code = 0x28309e,
.pme_short_desc = "PTEG loaded from L3.5 modified",
- .pme_long_desc = "PTEG loaded from L3.5 modified",
- .pme_event_ids = { -1, 182, 155, -1, -1, -1 },
- .pme_group_vector = {
- 0x0200000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_THRD_SMT_HANG 360
+ .pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L3 of a chip on the same module as this processor is located, due to a demand load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_L35_MOD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_L35_MOD]
+ },
+ [ POWER5_PME_PM_INST_FROM_L25_MOD ] = {
+ .pme_name = "PM_INST_FROM_L25_MOD",
+ .pme_code = 0x222096,
+ .pme_short_desc = "Instruction fetched from L2.5 modified",
+ .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L2 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L25_MOD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L25_MOD]
+ },
[ POWER5_PME_PM_THRD_SMT_HANG ] = {
.pme_name = "PM_THRD_SMT_HANG",
+ .pme_code = 0x330e7,
.pme_short_desc = "SMT hang detected",
- .pme_long_desc = "SMT hang detected",
- .pme_event_ids = { -1, -1, 184, 190, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_CMPLU_STALL_ERAT_MISS 361
+ .pme_long_desc = "A hung thread was detected",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_SMT_HANG],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_SMT_HANG]
+ },
[ POWER5_PME_PM_CMPLU_STALL_ERAT_MISS ] = {
.pme_name = "PM_CMPLU_STALL_ERAT_MISS",
+ .pme_code = 0x41109b,
.pme_short_desc = "Completion stall caused by ERAT miss",
- .pme_long_desc = "Completion stall caused by ERAT miss",
- .pme_event_ids = { -1, -1, -1, 8, -1, -1 },
- .pme_group_vector = {
- 0x0000000020000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L3SA_MOD_TAG 362
+ .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered an ERAT miss. This is a subset of PM_CMPLU_STALL_REJECT.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_CMPLU_STALL_ERAT_MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CMPLU_STALL_ERAT_MISS]
+ },
[ POWER5_PME_PM_L3SA_MOD_TAG ] = {
.pme_name = "PM_L3SA_MOD_TAG",
+ .pme_code = 0x720e3,
.pme_short_desc = "L3 slice A transition from modified to TAG",
- .pme_long_desc = "L3 slice A transition from modified to TAG",
- .pme_event_ids = { 107, 105, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000020ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FLUSH_SYNC 363
+ .pme_long_desc = "L3 snooper detects someone doing a read to a line that is truly M in this L3(i.e. L3 going M->T or M->I(go_Mu case) Mu|Me are not included since they are formed due to a prev read op). Tx is not included since it is considered shared at this point.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SA_MOD_TAG],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SA_MOD_TAG]
+ },
[ POWER5_PME_PM_FLUSH_SYNC ] = {
.pme_name = "PM_FLUSH_SYNC",
+ .pme_code = 0x330e1,
.pme_short_desc = "Flush caused by sync",
- .pme_long_desc = "Flush caused by sync",
- .pme_event_ids = { -1, -1, 28, 33, -1, -1 },
- .pme_group_vector = {
- 0x0000000000100000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_INST_FROM_L2MISS 364
+ .pme_long_desc = "This thread has been flushed at dispatch due to a sync, lwsync, ptesync, or tlbsync instruction. This allows the other thread to have more machine resources for it to make progress until the sync finishes.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FLUSH_SYNC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FLUSH_SYNC]
+ },
[ POWER5_PME_PM_INST_FROM_L2MISS ] = {
.pme_name = "PM_INST_FROM_L2MISS",
- .pme_short_desc = "Instructions fetched missed L2",
- .pme_long_desc = "An instruction fetch group was fetched from beyond L2.",
- .pme_event_ids = { 212, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000400ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SC_ST_HIT 365
+ .pme_code = 0x12209b,
+ .pme_short_desc = "Instruction fetched missed L2",
+ .pme_long_desc = "An instruction fetch group was fetched from beyond the local L2.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L2MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L2MISS]
+ },
[ POWER5_PME_PM_L2SC_ST_HIT ] = {
.pme_name = "PM_L2SC_ST_HIT",
+ .pme_code = 0x733e2,
.pme_short_desc = "L2 slice C store hits",
- .pme_long_desc = "L2 slice C store hits",
- .pme_event_ids = { -1, -1, 86, 90, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000010ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_GRP_DISP 366
+ .pme_long_desc = "A store request made from the core hit in the L2 directory. The event is provided on each of the three slices A, B, and C.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_ST_HIT],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_ST_HIT]
+ },
+ [ POWER5_PME_PM_MEM_RQ_DISP_Q8to11 ] = {
+ .pme_name = "PM_MEM_RQ_DISP_Q8to11",
+ .pme_code = 0x722e6,
+ .pme_short_desc = "Memory read queue dispatched to queues 8-11",
+ .pme_long_desc = "A memory operation was dispatched to read queue 8,9,10 or 11. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_RQ_DISP_Q8to11],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_RQ_DISP_Q8to11]
+ },
[ POWER5_PME_PM_MRK_GRP_DISP ] = {
.pme_name = "PM_MRK_GRP_DISP",
+ .pme_code = 0x100002,
.pme_short_desc = "Marked group dispatched",
.pme_long_desc = "A group containing a sampled instruction was dispatched",
- .pme_event_ids = { 171, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0006000008000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_GRP_DISP],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_GRP_DISP]
},
-#define POWER5_PME_PM_L2SB_MOD_TAG 367
[ POWER5_PME_PM_L2SB_MOD_TAG ] = {
.pme_name = "PM_L2SB_MOD_TAG",
+ .pme_code = 0x720e1,
.pme_short_desc = "L2 slice B transition from modified to tagged",
- .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.",
- .pme_event_ids = { 90, 88, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000200ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_CLB_EMPTY_CYC 368
+ .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_MOD_TAG],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_MOD_TAG]
+ },
[ POWER5_PME_PM_CLB_EMPTY_CYC ] = {
.pme_name = "PM_CLB_EMPTY_CYC",
+ .pme_code = 0x410c6,
.pme_short_desc = "Cycles CLB empty",
- .pme_long_desc = "Cycles CLB completely empty",
- .pme_event_ids = { -1, -1, 169, 175, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000008ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SB_ST_HIT 369
+ .pme_long_desc = "Cycles when both thread's CLB is completely empty.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_CLB_EMPTY_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CLB_EMPTY_CYC]
+ },
[ POWER5_PME_PM_L2SB_ST_HIT ] = {
.pme_name = "PM_L2SB_ST_HIT",
+ .pme_code = 0x733e1,
.pme_short_desc = "L2 slice B store hits",
- .pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A,B, and C.",
- .pme_event_ids = { -1, -1, 78, 82, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000002ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU1_REJECT_SRQ_LHS 370
- [ POWER5_PME_PM_LSU1_REJECT_SRQ_LHS ] = {
- .pme_name = "PM_LSU1_REJECT_SRQ_LHS",
- .pme_short_desc = "LSU1 SRQ rejects",
- .pme_long_desc = "LSU1 reject due to load hit store",
- .pme_event_ids = { 137, 135, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000002000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_BR_PRED_CR_TA 371
+ .pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A, B and C.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_ST_HIT],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_ST_HIT]
+ },
+ [ POWER5_PME_PM_MEM_NONSPEC_RD_CANCEL ] = {
+ .pme_name = "PM_MEM_NONSPEC_RD_CANCEL",
+ .pme_code = 0x711c6,
+ .pme_short_desc = "Non speculative memory read cancelled",
+ .pme_long_desc = "A non-speculative read was cancelled because the combined response indicated it was sourced from aother L2 or L3. This event is sent from the Memory Controller clock domain and must be scaled accordingly",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_NONSPEC_RD_CANCEL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_NONSPEC_RD_CANCEL]
+ },
[ POWER5_PME_PM_BR_PRED_CR_TA ] = {
.pme_name = "PM_BR_PRED_CR_TA",
+ .pme_code = 0x423087,
.pme_short_desc = "A conditional branch was predicted",
.pme_long_desc = " CR and target prediction",
- .pme_event_ids = { -1, -1, -1, 5, -1, -1 },
- .pme_group_vector = {
- 0x0000020000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_BR_PRED_CR_TA],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_BR_PRED_CR_TA]
},
-#define POWER5_PME_PM_MRK_LSU0_FLUSH_SRQ 372
[ POWER5_PME_PM_MRK_LSU0_FLUSH_SRQ ] = {
.pme_name = "PM_MRK_LSU0_FLUSH_SRQ",
- .pme_short_desc = "LSU0 marked SRQ flushes",
+ .pme_code = 0x810c3,
+ .pme_short_desc = "LSU0 marked SRQ lhs flushes",
.pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { -1, -1, 140, 151, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU0_FLUSH_SRQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU0_FLUSH_SRQ]
},
-#define POWER5_PME_PM_MRK_LSU_FLUSH_ULD 373
[ POWER5_PME_PM_MRK_LSU_FLUSH_ULD ] = {
.pme_name = "PM_MRK_LSU_FLUSH_ULD",
+ .pme_code = 0x481090,
.pme_short_desc = "Marked unaligned load flushes",
.pme_long_desc = "A marked load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { -1, -1, -1, 160, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x4000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU_FLUSH_ULD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU_FLUSH_ULD]
+ },
+ [ POWER5_PME_PM_INST_DISP_ATTEMPT ] = {
+ .pme_name = "PM_INST_DISP_ATTEMPT",
+ .pme_code = 0x120e1,
+ .pme_short_desc = "Instructions dispatch attempted",
+ .pme_long_desc = "Number of PowerPC Instructions dispatched (attempted, not filtered by success.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_DISP_ATTEMPT],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_DISP_ATTEMPT]
},
-#define POWER5_PME_PM_INST_FROM_RMEM 374
[ POWER5_PME_PM_INST_FROM_RMEM ] = {
.pme_name = "PM_INST_FROM_RMEM",
+ .pme_code = 0x422086,
.pme_short_desc = "Instruction fetched from remote memory",
- .pme_long_desc = "Instruction fetched from remote memory",
- .pme_event_ids = { -1, -1, -1, 63, -1, -1 },
- .pme_group_vector = {
- 0x0010000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_ST_REF_L1_LSU0 375
+ .pme_long_desc = "An instruction fetch group was fetched from memory attached to a different module than this proccessor is located on. Fetch groups can contain up to 8 instructions",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_RMEM],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_RMEM]
+ },
[ POWER5_PME_PM_ST_REF_L1_LSU0 ] = {
.pme_name = "PM_ST_REF_L1_LSU0",
+ .pme_code = 0xc10c1,
.pme_short_desc = "LSU0 L1 D cache store references",
- .pme_long_desc = "A store executed on unit 0",
- .pme_event_ids = { -1, -1, 166, 172, -1, -1 },
- .pme_group_vector = {
- 0x0000800000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU0_DERAT_MISS 376
+ .pme_long_desc = "Store references to the Data Cache by LSU0.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_ST_REF_L1_LSU0],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_ST_REF_L1_LSU0]
+ },
[ POWER5_PME_PM_LSU0_DERAT_MISS ] = {
.pme_name = "PM_LSU0_DERAT_MISS",
+ .pme_code = 0x800c2,
.pme_short_desc = "LSU0 DERAT misses",
- .pme_long_desc = "A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.",
- .pme_event_ids = { 118, 116, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SB_RCLD_DISP 377
+ .pme_long_desc = "Total D-ERAT Misses by LSU0. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_DERAT_MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_DERAT_MISS]
+ },
[ POWER5_PME_PM_L2SB_RCLD_DISP ] = {
.pme_name = "PM_L2SB_RCLD_DISP",
- .pme_short_desc = "L2 Slice B RC load dispatch attempt",
- .pme_long_desc = "L2 Slice B RC load dispatch attempt",
- .pme_event_ids = { 91, 89, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x8000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU_STALL3 378
+ .pme_code = 0x701c1,
+ .pme_short_desc = "L2 slice B RC load dispatch attempt",
+ .pme_long_desc = "A Read/Claim dispatch for a Load was attempted",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_RCLD_DISP],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_RCLD_DISP]
+ },
[ POWER5_PME_PM_FPU_STALL3 ] = {
.pme_name = "PM_FPU_STALL3",
+ .pme_code = 0x202088,
.pme_short_desc = "FPU stalled in pipe3",
- .pme_long_desc = "FPU has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, 55, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000010000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_BR_PRED_CR 379
+ .pme_long_desc = "FPU has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. Combined Unit 0 + Unit 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_STALL3],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_STALL3]
+ },
[ POWER5_PME_PM_BR_PRED_CR ] = {
.pme_name = "PM_BR_PRED_CR",
+ .pme_code = 0x230e2,
.pme_short_desc = "A conditional branch was predicted",
.pme_long_desc = " CR prediction",
- .pme_event_ids = { -1, -1, 3, 4, -1, -1 },
- .pme_group_vector = {
- 0x0000020000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000020ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_BR_PRED_CR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_BR_PRED_CR]
},
-#define POWER5_PME_PM_MRK_DATA_FROM_L2 380
[ POWER5_PME_PM_MRK_DATA_FROM_L2 ] = {
.pme_name = "PM_MRK_DATA_FROM_L2",
+ .pme_code = 0x1c7087,
.pme_short_desc = "Marked data loaded from L2",
- .pme_long_desc = "DL1 was reloaded from the local L2 due to a marked demand load",
- .pme_event_ids = { 160, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0010000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU0_FLUSH_SRQ 381
+ .pme_long_desc = "The processor's Data Cache was reloaded from the local L2 due to a marked load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L2],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L2]
+ },
[ POWER5_PME_PM_LSU0_FLUSH_SRQ ] = {
.pme_name = "PM_LSU0_FLUSH_SRQ",
- .pme_short_desc = "LSU0 SRQ flushes",
- .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { 120, 118, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000800000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FAB_PNtoNN_DIRECT 382
+ .pme_code = 0xc00c3,
+ .pme_short_desc = "LSU0 SRQ lhs flushes",
+ .pme_long_desc = "A store was flushed by unit 0 because younger load hits and older store that is already in the SRQ or in the same group.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_FLUSH_SRQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_FLUSH_SRQ]
+ },
[ POWER5_PME_PM_FAB_PNtoNN_DIRECT ] = {
.pme_name = "PM_FAB_PNtoNN_DIRECT",
+ .pme_code = 0x703c7,
.pme_short_desc = "PN to NN beat went straight to its destination",
- .pme_long_desc = "PN to NN beat went straight to its destination",
- .pme_event_ids = { 33, 32, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000008000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SC_SHR_INV 383
+ .pme_long_desc = "Fabric Data beats that the base chip takes the inbound PN data and passes it through to the outbound NN bus without going into a sidecar. The signal is delivered at FBC speed and the count must be scaled.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_PNtoNN_DIRECT],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_PNtoNN_DIRECT]
+ },
+ [ POWER5_PME_PM_IOPS_CMPL ] = {
+ .pme_name = "PM_IOPS_CMPL",
+ .pme_code = 0x1,
+ .pme_short_desc = "Internal operations completed",
+ .pme_long_desc = "Number of internal operations that completed.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_IOPS_CMPL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_IOPS_CMPL]
+ },
[ POWER5_PME_PM_L2SC_SHR_INV ] = {
.pme_name = "PM_L2SC_SHR_INV",
+ .pme_code = 0x710c2,
.pme_short_desc = "L2 slice C transition from shared to invalid",
- .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.",
- .pme_event_ids = { -1, -1, 85, 89, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000400ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SA_RCST_DISP_FAIL_OTHER 384
+ .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A, B, and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_SHR_INV],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_SHR_INV]
+ },
[ POWER5_PME_PM_L2SA_RCST_DISP_FAIL_OTHER ] = {
.pme_name = "PM_L2SA_RCST_DISP_FAIL_OTHER",
- .pme_short_desc = "L2 Slice A RC store dispatch attempt failed due to other reasons",
- .pme_long_desc = "L2 Slice A RC store dispatch attempt failed due to other reasons",
- .pme_event_ids = { -1, -1, 67, 71, -1, -1 },
- .pme_group_vector = {
- 0x2000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SA_RCST_DISP 385
+ .pme_code = 0x732e0,
+ .pme_short_desc = "L2 slice A RC store dispatch attempt failed due to other reasons",
+ .pme_long_desc = "A Read/Claim dispatch for a store failed for some reason other than Full or Collision conditions. Rejected dispatches do not count because they have not yet been attempted.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_RCST_DISP_FAIL_OTHER],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_RCST_DISP_FAIL_OTHER]
+ },
[ POWER5_PME_PM_L2SA_RCST_DISP ] = {
.pme_name = "PM_L2SA_RCST_DISP",
- .pme_short_desc = "L2 Slice A RC store dispatch attempt",
- .pme_long_desc = "L2 Slice A RC store dispatch attempt",
- .pme_event_ids = { 85, 83, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x2000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FAB_PNtoVN_SIDECAR 386
+ .pme_code = 0x702c0,
+ .pme_short_desc = "L2 slice A RC store dispatch attempt",
+ .pme_long_desc = "A Read/Claim dispatch for a Store was attempted.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_RCST_DISP],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_RCST_DISP]
+ },
+ [ POWER5_PME_PM_SNOOP_RETRY_AB_COLLISION ] = {
+ .pme_name = "PM_SNOOP_RETRY_AB_COLLISION",
+ .pme_code = 0x735e6,
+ .pme_short_desc = "Snoop retry due to a b collision",
+ .pme_long_desc = "Snoop retry due to a b collision",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_RETRY_AB_COLLISION],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_RETRY_AB_COLLISION]
+ },
[ POWER5_PME_PM_FAB_PNtoVN_SIDECAR ] = {
.pme_name = "PM_FAB_PNtoVN_SIDECAR",
+ .pme_code = 0x733e7,
.pme_short_desc = "PN to VN beat went to sidecar first",
- .pme_long_desc = "PN to VN beat went to sidecar first",
- .pme_event_ids = { -1, -1, 22, 27, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000008000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU_LMQ_S0_ALLOC 387
+ .pme_long_desc = "Fabric data beats that the base chip takes the inbound PN data and forwards it on to the outbound VN data bus after going into a sidecar first. The signal is delivered at FBC speed and the count must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_PNtoVN_SIDECAR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_PNtoVN_SIDECAR]
+ },
[ POWER5_PME_PM_LSU_LMQ_S0_ALLOC ] = {
.pme_name = "PM_LSU_LMQ_S0_ALLOC",
+ .pme_code = 0xc30e6,
.pme_short_desc = "LMQ slot 0 allocated",
.pme_long_desc = "The first entry in the LMQ was allocated.",
- .pme_event_ids = { -1, -1, 113, 118, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000080ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_LMQ_S0_ALLOC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_LMQ_S0_ALLOC]
},
-#define POWER5_PME_PM_LSU0_REJECT_LMQ_FULL 388
[ POWER5_PME_PM_LSU0_REJECT_LMQ_FULL ] = {
.pme_name = "PM_LSU0_REJECT_LMQ_FULL",
+ .pme_code = 0xc60e1,
.pme_short_desc = "LSU0 reject due to LMQ full or missed data coming",
- .pme_long_desc = "LSU0 reject due to LMQ full or missed data coming",
- .pme_event_ids = { 124, 122, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000020000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_SNOOP_PW_RETRY_RQ 389
+ .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_REJECT_LMQ_FULL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_REJECT_LMQ_FULL]
+ },
[ POWER5_PME_PM_SNOOP_PW_RETRY_RQ ] = {
.pme_name = "PM_SNOOP_PW_RETRY_RQ",
+ .pme_code = 0x707c6,
.pme_short_desc = "Snoop partial-write retry due to collision with active read queue",
- .pme_long_desc = "Snoop partial-write retry due to collision with active read queue",
- .pme_event_ids = { 192, 186, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000100000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_PTEG_FROM_L3 390
+ .pme_long_desc = "A snoop request for a partial write to memory was retried because it matched the cache line of an active read. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_PW_RETRY_RQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_PW_RETRY_RQ]
+ },
+ [ POWER5_PME_PM_DTLB_REF ] = {
+ .pme_name = "PM_DTLB_REF",
+ .pme_code = 0x2c4090,
+ .pme_short_desc = "Data TLB references",
+ .pme_long_desc = "Total number of Data TLB references for all page sizes. Page size is determined at TLB reload time.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DTLB_REF],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DTLB_REF]
+ },
[ POWER5_PME_PM_PTEG_FROM_L3 ] = {
.pme_name = "PM_PTEG_FROM_L3",
+ .pme_code = 0x18308e,
.pme_short_desc = "PTEG loaded from L3",
- .pme_long_desc = "PTEG loaded from L3",
- .pme_event_ids = { 186, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0800000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY 391
+ .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local L3 due to a demand load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_L3],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_L3]
+ },
[ POWER5_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY ] = {
.pme_name = "PM_FAB_M1toVNorNN_SIDECAR_EMPTY",
+ .pme_code = 0x712c7,
.pme_short_desc = "M1 to VN/NN sidecar empty",
- .pme_long_desc = "M1 to VN/NN sidecar empty",
- .pme_event_ids = { -1, -1, 19, 24, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000010000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU_SRQ_EMPTY_CYC 392
+ .pme_long_desc = "Fabric cycles when the Minus-1 jump sidecar (sidecars for mcm to mcm data transfer) is empty. The signal is delivered at FBC speed and the count must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY]
+ },
[ POWER5_PME_PM_LSU_SRQ_EMPTY_CYC ] = {
.pme_name = "PM_LSU_SRQ_EMPTY_CYC",
+ .pme_code = 0x400015,
.pme_short_desc = "Cycles SRQ empty",
- .pme_long_desc = "The Store Request Queue is empty",
- .pme_event_ids = { -1, -1, -1, 122, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000200ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU1_STF 393
+ .pme_long_desc = "Cycles the Store Request Queue is empty",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_SRQ_EMPTY_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_SRQ_EMPTY_CYC]
+ },
[ POWER5_PME_PM_FPU1_STF ] = {
.pme_name = "PM_FPU1_STF",
+ .pme_code = 0x20e6,
.pme_short_desc = "FPU1 executed store instruction",
- .pme_long_desc = "This signal is active for one cycle when fp1 is executing a store instruction.",
- .pme_event_ids = { 53, 52, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000002000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU_LMQ_S0_VALID 394
+ .pme_long_desc = "FPU1 has executed a Floating Point Store instruction.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_STF],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_STF]
+ },
[ POWER5_PME_PM_LSU_LMQ_S0_VALID ] = {
.pme_name = "PM_LSU_LMQ_S0_VALID",
+ .pme_code = 0xc30e5,
.pme_short_desc = "LMQ slot 0 valid",
.pme_long_desc = "This signal is asserted every cycle when the first entry in the LMQ is valid. The LMQ had eight entries that are allocated FIFO",
- .pme_event_ids = { -1, -1, 114, 119, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000080ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_LMQ_S0_VALID],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_LMQ_S0_VALID]
},
-#define POWER5_PME_PM_GCT_USAGE_00to59_CYC 395
[ POWER5_PME_PM_GCT_USAGE_00to59_CYC ] = {
.pme_name = "PM_GCT_USAGE_00to59_CYC",
+ .pme_code = 0x10001f,
.pme_short_desc = "Cycles GCT less than 60% full",
- .pme_long_desc = "Cycles GCT less than 60% full",
- .pme_event_ids = { 62, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000040ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_DATA_FROM_L2MISS 396
+ .pme_long_desc = "Cycles when the Global Completion Table has fewer than 60% of its slots used. The GCT has 20 entries shared between threads.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_GCT_USAGE_00to59_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GCT_USAGE_00to59_CYC]
+ },
[ POWER5_PME_PM_DATA_FROM_L2MISS ] = {
.pme_name = "PM_DATA_FROM_L2MISS",
+ .pme_code = 0x3c309b,
.pme_short_desc = "Data loaded missed L2",
- .pme_long_desc = "DL1 was reloaded from beyond L2.",
- .pme_event_ids = { -1, -1, 187, -1, -1, -1 },
- .pme_group_vector = {
- 0x0002000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_GRP_DISP_BLK_SB_CYC 397
+ .pme_long_desc = "The processor's Data Cache was reloaded but not from the local L2.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_L2MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_L2MISS]
+ },
[ POWER5_PME_PM_GRP_DISP_BLK_SB_CYC ] = {
.pme_name = "PM_GRP_DISP_BLK_SB_CYC",
+ .pme_code = 0x130e1,
.pme_short_desc = "Cycles group dispatch blocked by scoreboard",
- .pme_long_desc = "The ISU sends a signal indicating that dispatch is blocked by scoreboard.",
- .pme_event_ids = { -1, -1, 50, 54, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000004ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU_FMOV_FEST 398
+ .pme_long_desc = "A scoreboard operation on a non-renamed resource has blocked dispatch.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_DISP_BLK_SB_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_DISP_BLK_SB_CYC]
+ },
[ POWER5_PME_PM_FPU_FMOV_FEST ] = {
.pme_name = "PM_FPU_FMOV_FEST",
- .pme_short_desc = "FPU executing FMOV or FEST instructions",
- .pme_long_desc = "This signal is active for one cycle when executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ . Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, 38, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000004000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_XER_MAP_FULL_CYC 399
+ .pme_code = 0x301088,
+ .pme_short_desc = "FPU executed FMOV or FEST instructions",
+ .pme_long_desc = "The floating point unit has executed a move kind of instruction or one of the estimate instructions. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ.. Combined Unit 0 + Unit 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_FMOV_FEST],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_FMOV_FEST]
+ },
[ POWER5_PME_PM_XER_MAP_FULL_CYC ] = {
.pme_name = "PM_XER_MAP_FULL_CYC",
+ .pme_code = 0x100c2,
.pme_short_desc = "Cycles XER mapper full",
- .pme_long_desc = "The ISU sends a signal indicating that the xer mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.",
- .pme_event_ids = { 211, 204, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FLUSH_SB 400
+ .pme_long_desc = "The XER mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_XER_MAP_FULL_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_XER_MAP_FULL_CYC]
+ },
[ POWER5_PME_PM_FLUSH_SB ] = {
.pme_name = "PM_FLUSH_SB",
+ .pme_code = 0x330e2,
.pme_short_desc = "Flush caused by scoreboard operation",
- .pme_long_desc = "Flush caused by scoreboard operation",
- .pme_event_ids = { -1, -1, 27, 32, -1, -1 },
- .pme_group_vector = {
- 0x0000000000100000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_DATA_FROM_L375_SHR 401
+ .pme_long_desc = "This thread has been flushed at dispatch because its scoreboard bit is set indicating that a non-renamed resource is being updated. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FLUSH_SB],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FLUSH_SB]
+ },
[ POWER5_PME_PM_MRK_DATA_FROM_L375_SHR ] = {
.pme_name = "PM_MRK_DATA_FROM_L375_SHR",
+ .pme_code = 0x3c709e,
.pme_short_desc = "Marked data loaded from L3.75 shared",
- .pme_long_desc = "Marked data loaded from L3.75 shared",
- .pme_event_ids = { -1, -1, 132, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0400000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_GRP_CMPL 402
+ .pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on a different module than this processor is located due to a marked load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L375_SHR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L375_SHR]
+ },
[ POWER5_PME_PM_MRK_GRP_CMPL ] = {
.pme_name = "PM_MRK_GRP_CMPL",
+ .pme_code = 0x400013,
.pme_short_desc = "Marked group completed",
- .pme_long_desc = "A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group.",
- .pme_event_ids = { -1, -1, -1, 146, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0004000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_SUSPENDED 403
+ .pme_long_desc = "A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_GRP_CMPL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_GRP_CMPL]
+ },
[ POWER5_PME_PM_SUSPENDED ] = {
.pme_name = "PM_SUSPENDED",
+ .pme_code = 0x0,
.pme_short_desc = "Suspended",
- .pme_long_desc = "Suspended",
- .pme_event_ids = { 200, 194, 168, 174, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC 404
+ .pme_long_desc = "The counter is suspended (does not count).",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_SUSPENDED],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SUSPENDED]
+ },
[ POWER5_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC ] = {
.pme_name = "PM_GRP_IC_MISS_BR_REDIR_NONSPEC",
+ .pme_code = 0x120e5,
.pme_short_desc = "Group experienced non-speculative I cache miss or branch redirect",
.pme_long_desc = "Group experienced non-speculative I cache miss or branch redirect",
- .pme_event_ids = { 68, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000040000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC]
},
-#define POWER5_PME_PM_SNOOP_RD_RETRY_QFULL 405
[ POWER5_PME_PM_SNOOP_RD_RETRY_QFULL ] = {
.pme_name = "PM_SNOOP_RD_RETRY_QFULL",
+ .pme_code = 0x700c6,
.pme_short_desc = "Snoop read retry due to read queue full",
- .pme_long_desc = "Snoop read retry due to read queue full",
- .pme_event_ids = { 193, 187, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000020000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L3SB_MOD_INV 406
+ .pme_long_desc = "A snoop request for a read from memory was retried because the read queues were full. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_RD_RETRY_QFULL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_RD_RETRY_QFULL]
+ },
[ POWER5_PME_PM_L3SB_MOD_INV ] = {
.pme_name = "PM_L3SB_MOD_INV",
+ .pme_code = 0x730e4,
.pme_short_desc = "L3 slice B transition from modified to invalid",
- .pme_long_desc = "L3 slice B transition from modified to invalid",
- .pme_event_ids = { -1, -1, 93, 97, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000040ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_DATA_FROM_L35_SHR 407
+ .pme_long_desc = "L3 snooper detects someone doing a store to a line that is truly M in this L3 (i.e. L3 going M=>I). Mu|Me are not included since they are formed due to a prev read op. Tx is not included since it is considered shared at this point.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SB_MOD_INV],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SB_MOD_INV]
+ },
[ POWER5_PME_PM_DATA_FROM_L35_SHR ] = {
.pme_name = "PM_DATA_FROM_L35_SHR",
+ .pme_code = 0x1c309e,
.pme_short_desc = "Data loaded from L3.5 shared",
- .pme_long_desc = "Data loaded from L3.5 shared",
- .pme_event_ids = { 17, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0008000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LD_MISS_L1_LSU1 408
+ .pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on the same module as this processor is located due to a demand load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_L35_SHR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_L35_SHR]
+ },
[ POWER5_PME_PM_LD_MISS_L1_LSU1 ] = {
.pme_name = "PM_LD_MISS_L1_LSU1",
+ .pme_code = 0xc10c6,
.pme_short_desc = "LSU1 L1 D cache load misses",
- .pme_long_desc = "A load, executing on unit 1, missed the dcache",
- .pme_event_ids = { -1, -1, 102, 105, -1, -1 },
- .pme_group_vector = {
- 0x0000200000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_STCX_FAIL 409
+ .pme_long_desc = "Load references that miss the Level 1 Data cache, by unit 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LD_MISS_L1_LSU1],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LD_MISS_L1_LSU1]
+ },
[ POWER5_PME_PM_STCX_FAIL ] = {
.pme_name = "PM_STCX_FAIL",
+ .pme_code = 0x820e1,
.pme_short_desc = "STCX failed",
.pme_long_desc = "A stcx (stwcx or stdcx) failed",
- .pme_event_ids = { 198, 192, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000001000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_STCX_FAIL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_STCX_FAIL]
},
-#define POWER5_PME_PM_DC_PREF_DST 410
[ POWER5_PME_PM_DC_PREF_DST ] = {
.pme_name = "PM_DC_PREF_DST",
+ .pme_code = 0x830e6,
.pme_short_desc = "DST (Data Stream Touch) stream start",
- .pme_long_desc = "DST (Data Stream Touch) stream start",
- .pme_event_ids = { -1, -1, 13, 17, -1, -1 },
- .pme_group_vector = {
- 0x0000000000002000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_GRP_DISP 411
+ .pme_long_desc = "A prefetch stream was started using the DST instruction.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DC_PREF_DST],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DC_PREF_DST]
+ },
[ POWER5_PME_PM_GRP_DISP ] = {
.pme_name = "PM_GRP_DISP",
+ .pme_code = 0x200002,
.pme_short_desc = "Group dispatches",
.pme_long_desc = "A group was dispatched",
- .pme_event_ids = { -1, 64, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0800000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MEM_WQ_DISP_BUSY8to15 412
- [ POWER5_PME_PM_MEM_WQ_DISP_BUSY8to15 ] = {
- .pme_name = "PM_MEM_WQ_DISP_BUSY8to15",
- .pme_short_desc = "Memory write queue dispatched with 8-15 queues busy",
- .pme_long_desc = "Memory write queue dispatched with 8-15 queues busy",
- .pme_event_ids = { -1, -1, 127, 132, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000800000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR 413
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_DISP],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_DISP]
+ },
[ POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR ] = {
.pme_name = "PM_L2SA_RCLD_DISP_FAIL_ADDR",
- .pme_short_desc = "L2 Slice A RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ",
- .pme_long_desc = "L2 Slice A RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ",
- .pme_event_ids = { -1, -1, 64, 68, -1, -1 },
- .pme_group_vector = {
- 0x1000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU0_FPSCR 414
+ .pme_code = 0x711c0,
+ .pme_short_desc = "L2 slice A RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ",
+ .pme_long_desc = "A Read/Claim dispatch for a load failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR]
+ },
[ POWER5_PME_PM_FPU0_FPSCR ] = {
.pme_name = "PM_FPU0_FPSCR",
+ .pme_code = 0x30e0,
.pme_short_desc = "FPU0 executed FPSCR instruction",
- .pme_long_desc = "This signal is active for one cycle when fp0 is executing fpscr move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*. mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs",
- .pme_event_ids = { -1, -1, 32, 37, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000200000ULL,
- 0x0000000000000040ULL }
- },
-#define POWER5_PME_PM_DATA_FROM_L2 415
+ .pme_long_desc = "FPU0 has executed FPSCR move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*, mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_FPSCR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_FPSCR]
+ },
[ POWER5_PME_PM_DATA_FROM_L2 ] = {
.pme_name = "PM_DATA_FROM_L2",
+ .pme_code = 0x1c3087,
.pme_short_desc = "Data loaded from L2",
- .pme_long_desc = "DL1 was reloaded from the local L2 due to a demand load",
- .pme_event_ids = { 13, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000100000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000001ULL }
- },
-#define POWER5_PME_PM_FPU1_DENORM 416
+ .pme_long_desc = "The processor's Data Cache was reloaded from the local L2 due to a demand load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_L2],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_L2]
+ },
[ POWER5_PME_PM_FPU1_DENORM ] = {
.pme_name = "PM_FPU1_DENORM",
+ .pme_code = 0x20e4,
.pme_short_desc = "FPU1 received denormalized data",
- .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.",
- .pme_event_ids = { 46, 45, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000080000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MEM_RQ_DISP_BUSY1to7 417
- [ POWER5_PME_PM_MEM_RQ_DISP_BUSY1to7 ] = {
- .pme_name = "PM_MEM_RQ_DISP_BUSY1to7",
- .pme_short_desc = "Memory read queue dispatched with 1-7 queues busy",
- .pme_long_desc = "Memory read queue dispatched with 1-7 queues busy",
- .pme_event_ids = { -1, -1, 125, 130, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000200000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU_1FLOP 418
+ .pme_long_desc = "FPU1 has encountered a denormalized operand.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_DENORM],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_DENORM]
+ },
[ POWER5_PME_PM_FPU_1FLOP ] = {
.pme_name = "PM_FPU_1FLOP",
- .pme_short_desc = "FPU executed one flop instruction ",
- .pme_long_desc = "This event counts the number of one flop instructions. These could be fadd*, fmul*, fsub*, fneg+, fabs+, fnabs+, fres+, frsqrte+, fcmp**, or fsel where XYZ* means XYZ, XYZs, XYZ., XYZs., XYZ+ means XYZ, XYZ., and XYZ** means XYZu, XYZo.",
- .pme_event_ids = { 56, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000008000ULL,
- 0x0000000000010200ULL }
- },
-#define POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER 419
+ .pme_code = 0x100090,
+ .pme_short_desc = "FPU executed one flop instruction",
+ .pme_long_desc = "The floating point unit has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_1FLOP],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_1FLOP]
+ },
[ POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER ] = {
.pme_name = "PM_L2SC_RCLD_DISP_FAIL_OTHER",
- .pme_short_desc = "L2 Slice C RC load dispatch attempt failed due to other reasons",
- .pme_long_desc = "L2 Slice C RC load dispatch attempt failed due to other reasons",
- .pme_event_ids = { -1, -1, 81, 85, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000004ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL 420
+ .pme_code = 0x731e2,
+ .pme_short_desc = "L2 slice C RC load dispatch attempt failed due to other reasons",
+ .pme_long_desc = "A Read/Claim dispatch for a load failed for some reason other than Full or Collision conditions.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER]
+ },
[ POWER5_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL ] = {
.pme_name = "PM_L2SC_RCST_DISP_FAIL_RC_FULL",
- .pme_short_desc = "L2 Slice C RC store dispatch attempt failed due to all RC full",
- .pme_long_desc = "L2 Slice C RC store dispatch attempt failed due to all RC full",
- .pme_event_ids = { 102, 100, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000008ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU0_FSQRT 421
+ .pme_code = 0x722e2,
+ .pme_short_desc = "L2 slice C RC store dispatch attempt failed due to all RC full",
+ .pme_long_desc = "A Read/Claim dispatch for a store failed because all RC machines are busy.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL]
+ },
[ POWER5_PME_PM_FPU0_FSQRT ] = {
.pme_name = "PM_FPU0_FSQRT",
+ .pme_code = 0xc2,
.pme_short_desc = "FPU0 executed FSQRT instruction",
- .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp0 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 40, 39, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000040000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LD_REF_L1 422
+ .pme_long_desc = "FPU0 has executed a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_FSQRT],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_FSQRT]
+ },
[ POWER5_PME_PM_LD_REF_L1 ] = {
.pme_name = "PM_LD_REF_L1",
+ .pme_code = 0x4c1090,
.pme_short_desc = "L1 D cache load references",
- .pme_long_desc = "Total DL1 Load references",
- .pme_event_ids = { -1, -1, -1, 106, -1, -1 },
- .pme_group_vector = {
- 0x0000080000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000008207ULL }
- },
-#define POWER5_PME_PM_INST_FROM_L1 423
+ .pme_long_desc = "Load references to the Level 1 Data Cache. Combined unit 0 + 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LD_REF_L1],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LD_REF_L1]
+ },
[ POWER5_PME_PM_INST_FROM_L1 ] = {
.pme_name = "PM_INST_FROM_L1",
+ .pme_code = 0x22208d,
.pme_short_desc = "Instruction fetched from L1",
.pme_long_desc = "An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions",
- .pme_event_ids = { -1, 74, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0010000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000001ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L1],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L1]
},
-#define POWER5_PME_PM_TLBIE_HELD 424
[ POWER5_PME_PM_TLBIE_HELD ] = {
.pme_name = "PM_TLBIE_HELD",
+ .pme_code = 0x130e4,
.pme_short_desc = "TLBIE held at dispatch",
- .pme_long_desc = "TLBIE held at dispatch",
- .pme_event_ids = { -1, -1, 186, 191, -1, -1 },
- .pme_group_vector = {
- 0x0000000000010000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_DATA_FROM_L25_MOD_CYC 425
+ .pme_long_desc = "Cycles a TLBIE instruction was held at dispatch.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_TLBIE_HELD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_TLBIE_HELD]
+ },
+ [ POWER5_PME_PM_DC_PREF_OUT_OF_STREAMS ] = {
+ .pme_name = "PM_DC_PREF_OUT_OF_STREAMS",
+ .pme_code = 0xc50c2,
+ .pme_short_desc = "D cache out of prefetch streams",
+ .pme_long_desc = "A new prefetch stream was detected but no more stream entries were available.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DC_PREF_OUT_OF_STREAMS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DC_PREF_OUT_OF_STREAMS]
+ },
[ POWER5_PME_PM_MRK_DATA_FROM_L25_MOD_CYC ] = {
.pme_name = "PM_MRK_DATA_FROM_L25_MOD_CYC",
+ .pme_code = 0x4c70a2,
.pme_short_desc = "Marked load latency from L2.5 modified",
- .pme_long_desc = "Marked load latency from L2.5 modified",
- .pme_event_ids = { -1, -1, -1, 135, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0010000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_LSU1_FLUSH_SRQ 426
+ .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L25_MOD_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L25_MOD_CYC]
+ },
[ POWER5_PME_PM_MRK_LSU1_FLUSH_SRQ ] = {
.pme_name = "PM_MRK_LSU1_FLUSH_SRQ",
- .pme_short_desc = "LSU1 marked SRQ flushes",
+ .pme_code = 0x810c7,
+ .pme_short_desc = "LSU1 marked SRQ lhs flushes",
.pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { -1, -1, 144, 155, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU1_FLUSH_SRQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU1_FLUSH_SRQ]
+ },
+ [ POWER5_PME_PM_MEM_RQ_DISP_Q0to3 ] = {
+ .pme_name = "PM_MEM_RQ_DISP_Q0to3",
+ .pme_code = 0x702c6,
+ .pme_short_desc = "Memory read queue dispatched to queues 0-3",
+ .pme_long_desc = "A memory operation was dispatched to read queue 0,1,2, or 3. This event is sent from the Memory Controller clock domain and must be scaled accordingly.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_RQ_DISP_Q0to3],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_RQ_DISP_Q0to3]
},
-#define POWER5_PME_PM_ST_REF_L1_LSU1 427
[ POWER5_PME_PM_ST_REF_L1_LSU1 ] = {
.pme_name = "PM_ST_REF_L1_LSU1",
+ .pme_code = 0xc10c5,
.pme_short_desc = "LSU1 L1 D cache store references",
- .pme_long_desc = "A store executed on unit 1",
- .pme_event_ids = { -1, -1, 167, 173, -1, -1 },
- .pme_group_vector = {
- 0x0000800000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_LD_MISS_L1 428
+ .pme_long_desc = "Store references to the Data Cache by LSU1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_ST_REF_L1_LSU1],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_ST_REF_L1_LSU1]
+ },
[ POWER5_PME_PM_MRK_LD_MISS_L1 ] = {
.pme_name = "PM_MRK_LD_MISS_L1",
+ .pme_code = 0x182088,
.pme_short_desc = "Marked L1 D cache load misses",
.pme_long_desc = "Marked L1 D cache load misses",
- .pme_event_ids = { 175, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x2000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LD_MISS_L1],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LD_MISS_L1]
},
-#define POWER5_PME_PM_L1_WRITE_CYC 429
[ POWER5_PME_PM_L1_WRITE_CYC ] = {
.pme_name = "PM_L1_WRITE_CYC",
+ .pme_code = 0x230e7,
.pme_short_desc = "Cycles writing to instruction L1",
- .pme_long_desc = "This signal is asserted each cycle a cache write is active.",
- .pme_event_ids = { -1, -1, 62, 66, -1, -1 },
- .pme_group_vector = {
- 0x0000000000008000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SC_ST_REQ 430
+ .pme_long_desc = "Cycles that a cache line was written to the instruction cache.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L1_WRITE_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L1_WRITE_CYC]
+ },
[ POWER5_PME_PM_L2SC_ST_REQ ] = {
.pme_name = "PM_L2SC_ST_REQ",
+ .pme_code = 0x723e2,
.pme_short_desc = "L2 slice C store requests",
- .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C.",
- .pme_event_ids = { 105, 103, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000010ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_CMPLU_STALL_FDIV 431
+ .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A, B, and C.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_ST_REQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_ST_REQ]
+ },
[ POWER5_PME_PM_CMPLU_STALL_FDIV ] = {
.pme_name = "PM_CMPLU_STALL_FDIV",
+ .pme_code = 0x21109b,
.pme_short_desc = "Completion stall caused by FDIV or FQRT instruction",
- .pme_long_desc = "Completion stall caused by FDIV or FQRT instruction",
- .pme_event_ids = { -1, 11, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000080000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_THRD_SEL_OVER_CLB_EMPTY 432
+ .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a floating point divide or square root instruction. This is a subset of PM_CMPLU_STALL_FPU.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_CMPLU_STALL_FDIV],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CMPLU_STALL_FDIV]
+ },
[ POWER5_PME_PM_THRD_SEL_OVER_CLB_EMPTY ] = {
.pme_name = "PM_THRD_SEL_OVER_CLB_EMPTY",
- .pme_short_desc = "Thread selection overides caused by CLB empty",
- .pme_long_desc = "Thread selection overides caused by CLB empty",
- .pme_event_ids = { -1, -1, 178, 184, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000800000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_BR_MPRED_CR 433
+ .pme_code = 0x410c2,
+ .pme_short_desc = "Thread selection overrides caused by CLB empty",
+ .pme_long_desc = "Thread selection was overridden because one thread's CLB was empty.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_SEL_OVER_CLB_EMPTY],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_SEL_OVER_CLB_EMPTY]
+ },
[ POWER5_PME_PM_BR_MPRED_CR ] = {
.pme_name = "PM_BR_MPRED_CR",
+ .pme_code = 0x230e5,
.pme_short_desc = "Branch mispredictions due to CR bit setting",
- .pme_long_desc = "This signal is asserted when the branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This signal is asserted after a branch issue event and will result in a branch redirect flush if not overridden by a flush of an older instruction.",
- .pme_event_ids = { -1, -1, 1, 2, -1, -1 },
- .pme_group_vector = {
- 0x0000010000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L3SB_MOD_TAG 434
+ .pme_long_desc = "A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_BR_MPRED_CR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_BR_MPRED_CR]
+ },
[ POWER5_PME_PM_L3SB_MOD_TAG ] = {
.pme_name = "PM_L3SB_MOD_TAG",
+ .pme_code = 0x720e4,
.pme_short_desc = "L3 slice B transition from modified to TAG",
- .pme_long_desc = "L3 slice B transition from modified to TAG",
- .pme_event_ids = { 110, 108, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000040ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MRK_DATA_FROM_L2MISS 435
+ .pme_long_desc = "L3 snooper detects someone doing a read to a line that is truly M in this L3(i.e. L3 going M->T or M->I(go_Mu case); Mu|Me are not included since they are formed due to a prev read op). Tx is not included since it is considered shared at this point.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SB_MOD_TAG],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SB_MOD_TAG]
+ },
[ POWER5_PME_PM_MRK_DATA_FROM_L2MISS ] = {
.pme_name = "PM_MRK_DATA_FROM_L2MISS",
+ .pme_code = 0x3c709b,
.pme_short_desc = "Marked data loaded missed L2",
.pme_long_desc = "DL1 was reloaded from beyond L2 due to a marked demand load.",
- .pme_event_ids = { -1, -1, 188, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L2MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L2MISS]
+ },
+ [ POWER5_PME_PM_LSU_REJECT_SRQ ] = {
+ .pme_name = "PM_LSU_REJECT_SRQ",
+ .pme_code = 0x1c6088,
+ .pme_short_desc = "LSU SRQ lhs rejects",
+ .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions because of Load Hit Store conditions. Loads are rejected when data is needed from a previous store instruction but store forwarding is not possible because the data is not fully contained in the Store Data Queue or is not yet available in the Store Data Queue. Combined Unit 0 + 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_REJECT_SRQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_REJECT_SRQ]
},
-#define POWER5_PME_PM_LD_MISS_L1 436
[ POWER5_PME_PM_LD_MISS_L1 ] = {
.pme_name = "PM_LD_MISS_L1",
+ .pme_code = 0x3c1088,
.pme_short_desc = "L1 D cache load misses",
- .pme_long_desc = "Total DL1 Load references that miss the DL1",
- .pme_event_ids = { -1, -1, 100, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000080000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000004008ULL }
- },
-#define POWER5_PME_PM_INST_FROM_PREF 437
+ .pme_long_desc = "Load references that miss the Level 1 Data cache. Combined unit 0 + 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LD_MISS_L1],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LD_MISS_L1]
+ },
[ POWER5_PME_PM_INST_FROM_PREF ] = {
.pme_name = "PM_INST_FROM_PREF",
- .pme_short_desc = "Instructions fetched from prefetch",
- .pme_long_desc = "An instruction fetch group was fetched from the prefetch buffer. Fetch Groups can contain up to 8 instructions",
- .pme_event_ids = { -1, -1, 59, -1, -1, -1 },
- .pme_group_vector = {
- 0x0010000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_DC_INV_L2 438
+ .pme_code = 0x32208d,
+ .pme_short_desc = "Instruction fetched from prefetch",
+ .pme_long_desc = "An instruction fetch group was fetched from the prefetch buffer. Fetch groups can contain up to 8 instructions",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_PREF],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_PREF]
+ },
[ POWER5_PME_PM_DC_INV_L2 ] = {
.pme_name = "PM_DC_INV_L2",
+ .pme_code = 0xc10c7,
.pme_short_desc = "L1 D cache entries invalidated from L2",
.pme_long_desc = "A dcache invalidated was received from the L2 because a line in L2 was castout.",
- .pme_event_ids = { -1, -1, 12, 16, -1, -1 },
- .pme_group_vector = {
- 0x0800000000080000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DC_INV_L2],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DC_INV_L2]
},
-#define POWER5_PME_PM_STCX_PASS 439
[ POWER5_PME_PM_STCX_PASS ] = {
.pme_name = "PM_STCX_PASS",
+ .pme_code = 0x820e5,
.pme_short_desc = "Stcx passes",
.pme_long_desc = "A stcx (stwcx or stdcx) instruction was successful",
- .pme_event_ids = { 199, 193, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000001000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_STCX_PASS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_STCX_PASS]
},
-#define POWER5_PME_PM_LSU_SRQ_FULL_CYC 440
[ POWER5_PME_PM_LSU_SRQ_FULL_CYC ] = {
.pme_name = "PM_LSU_SRQ_FULL_CYC",
+ .pme_code = 0x110c3,
.pme_short_desc = "Cycles SRQ full",
- .pme_long_desc = "The ISU sends this signal when the srq is full.",
- .pme_event_ids = { -1, -1, 118, 123, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000100ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_MEM_READ_CMPL 441
- [ POWER5_PME_PM_MEM_READ_CMPL ] = {
- .pme_name = "PM_MEM_READ_CMPL",
- .pme_short_desc = "Memory read completed or canceled",
- .pme_long_desc = "Memory read completed or canceled",
- .pme_event_ids = { 155, 153, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000400000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU_FIN 442
+ .pme_long_desc = "Cycles the Store Request Queue is full.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_SRQ_FULL_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_SRQ_FULL_CYC]
+ },
[ POWER5_PME_PM_FPU_FIN ] = {
.pme_name = "PM_FPU_FIN",
+ .pme_code = 0x401088,
.pme_short_desc = "FPU produced a result",
- .pme_long_desc = "FPU finished, produced a result This only indicates finish, not completion. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, -1, 44, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0020000000008000ULL,
- 0x0000000000001800ULL }
- },
-#define POWER5_PME_PM_L2SA_SHR_MOD 443
+ .pme_long_desc = "FPU finished, produced a result. This only indicates finish, not completion. Combined Unit 0 + Unit 1. Floating Point Stores are included in this count but not Floating Point Loads., , , XYZs",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_FIN],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_FIN]
+ },
[ POWER5_PME_PM_L2SA_SHR_MOD ] = {
.pme_name = "PM_L2SA_SHR_MOD",
+ .pme_code = 0x700c0,
.pme_short_desc = "L2 slice A transition from shared to modified",
- .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. ",
- .pme_event_ids = { 88, 86, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000100ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU_SRQ_STFWD 444
+ .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A, B, and C. ",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_SHR_MOD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_SHR_MOD]
+ },
[ POWER5_PME_PM_LSU_SRQ_STFWD ] = {
.pme_name = "PM_LSU_SRQ_STFWD",
+ .pme_code = 0x1c2088,
.pme_short_desc = "SRQ store forwarded",
- .pme_long_desc = "Data from a store instruction was forwarded to a load",
- .pme_event_ids = { 149, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000200ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_0INST_CLB_CYC 445
+ .pme_long_desc = "Data from a store instruction was forwarded to a load. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. Combined Unit 0 + 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_SRQ_STFWD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_SRQ_STFWD]
+ },
[ POWER5_PME_PM_0INST_CLB_CYC ] = {
.pme_name = "PM_0INST_CLB_CYC",
+ .pme_code = 0x400c0,
.pme_short_desc = "Cycles no instructions in CLB",
- .pme_long_desc = "Cycles no instructions in CLB",
- .pme_event_ids = { 0, 0, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000008ULL,
- 0x0000000800000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FXU0_FIN 446
+ .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_0INST_CLB_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_0INST_CLB_CYC]
+ },
[ POWER5_PME_PM_FXU0_FIN ] = {
.pme_name = "PM_FXU0_FIN",
+ .pme_code = 0x130e2,
.pme_short_desc = "FXU0 produced a result",
- .pme_long_desc = "The Fixed Point unit 0 finished an instruction and produced a result",
- .pme_event_ids = { -1, -1, 43, 48, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000010000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL 447
+ .pme_long_desc = "The Fixed Point unit 0 finished an instruction and produced a result. Instructions that finish may not necessary complete.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FXU0_FIN],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FXU0_FIN]
+ },
[ POWER5_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL ] = {
.pme_name = "PM_L2SB_RCST_DISP_FAIL_RC_FULL",
- .pme_short_desc = "L2 Slice B RC store dispatch attempt failed due to all RC full",
- .pme_long_desc = "L2 Slice B RC store dispatch attempt failed due to all RC full",
- .pme_event_ids = { 94, 92, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000001ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_THRD_GRP_CMPL_BOTH_CYC 448
+ .pme_code = 0x722e1,
+ .pme_short_desc = "L2 slice B RC store dispatch attempt failed due to all RC full",
+ .pme_long_desc = "A Read/Claim dispatch for a store failed because all RC machines are busy.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL]
+ },
[ POWER5_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = {
.pme_name = "PM_THRD_GRP_CMPL_BOTH_CYC",
+ .pme_code = 0x200013,
.pme_short_desc = "Cycles group completed by both threads",
- .pme_long_desc = "Cycles group completed by both threads",
- .pme_event_ids = { -1, 196, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000200000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_PMC5_OVERFLOW 449
+ .pme_long_desc = "Cycles that both threads completed.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_GRP_CMPL_BOTH_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_GRP_CMPL_BOTH_CYC]
+ },
[ POWER5_PME_PM_PMC5_OVERFLOW ] = {
.pme_name = "PM_PMC5_OVERFLOW",
+ .pme_code = 0x10001a,
.pme_short_desc = "PMC5 Overflow",
- .pme_long_desc = "PMC5 Overflow",
- .pme_event_ids = { 182, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_FPU0_FDIV 450
+ .pme_long_desc = "Overflows from PMC5 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_PMC5_OVERFLOW],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PMC5_OVERFLOW]
+ },
[ POWER5_PME_PM_FPU0_FDIV ] = {
.pme_name = "PM_FPU0_FDIV",
+ .pme_code = 0xc0,
.pme_short_desc = "FPU0 executed FDIV instruction",
- .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp0 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.",
- .pme_event_ids = { 38, 37, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000100000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_PTEG_FROM_L375_SHR 451
+ .pme_long_desc = "FPU0 has executed a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_FDIV],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_FDIV]
+ },
[ POWER5_PME_PM_PTEG_FROM_L375_SHR ] = {
.pme_name = "PM_PTEG_FROM_L375_SHR",
+ .pme_code = 0x38309e,
.pme_short_desc = "PTEG loaded from L3.75 shared",
- .pme_long_desc = "PTEG loaded from L3.75 shared",
- .pme_event_ids = { -1, -1, 156, -1, -1, -1 },
- .pme_group_vector = {
- 0x0200000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LD_REF_L1_LSU1 452
+ .pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (S) data from the L3 of a chip on a different module than this processor is located, due to a demand load.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_L375_SHR],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_L375_SHR]
+ },
[ POWER5_PME_PM_LD_REF_L1_LSU1 ] = {
.pme_name = "PM_LD_REF_L1_LSU1",
+ .pme_code = 0xc10c4,
.pme_short_desc = "LSU1 L1 D cache load references",
- .pme_long_desc = "A load executed on unit 1",
- .pme_event_ids = { -1, -1, 104, 108, -1, -1 },
- .pme_group_vector = {
- 0x0000400000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY 453
+ .pme_long_desc = "Load references to Level 1 Data Cache, by unit 1.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LD_REF_L1_LSU1],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LD_REF_L1_LSU1]
+ },
[ POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY ] = {
.pme_name = "PM_L2SA_RC_DISP_FAIL_CO_BUSY",
- .pme_short_desc = "L2 Slice A RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy",
- .pme_long_desc = "L2 Slice A RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy",
- .pme_event_ids = { 87, 85, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x4000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_HV_CYC 454
+ .pme_code = 0x703c0,
+ .pme_short_desc = "L2 slice A RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy",
+ .pme_long_desc = "A Read/Claim Dispatch was rejected at dispatch because the Castout Machine was busy. In the case of an RC starting up on a miss and the victim is valid, the CO machine must be available for the RC to process the access. If the CO is still busy working on an old castout, then the RC must not-ack the access if it is a miss(re-issued by the CIU). If it is a miss and the CO is available to process the castout, the RC will accept the access. Once the RC has finished, it can restart and process new accesses that result in a hit (or miss that doesn't need a CO) even though the CO is still processing a castout from a previous access.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY]
+ },
[ POWER5_PME_PM_HV_CYC ] = {
.pme_name = "PM_HV_CYC",
+ .pme_code = 0x20000b,
.pme_short_desc = "Hypervisor Cycles",
.pme_long_desc = "Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)",
- .pme_event_ids = { -1, 68, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000100000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_HV_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_HV_CYC]
},
-#define POWER5_PME_PM_THRD_PRIO_DIFF_0_CYC 455
[ POWER5_PME_PM_THRD_PRIO_DIFF_0_CYC ] = {
.pme_name = "PM_THRD_PRIO_DIFF_0_CYC",
+ .pme_code = 0x430e3,
.pme_short_desc = "Cycles no thread priority difference",
- .pme_long_desc = "Cycles no thread priority difference",
- .pme_event_ids = { -1, -1, 171, 177, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000020000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LR_CTR_MAP_FULL_CYC 456
+ .pme_long_desc = "Cycles when this thread's priority is equal to the other thread's priority.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_DIFF_0_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_DIFF_0_CYC]
+ },
[ POWER5_PME_PM_LR_CTR_MAP_FULL_CYC ] = {
.pme_name = "PM_LR_CTR_MAP_FULL_CYC",
+ .pme_code = 0x100c6,
.pme_short_desc = "Cycles LR/CTR mapper full",
- .pme_long_desc = "The ISU sends a signal indicating that the lr/ctr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.",
- .pme_event_ids = { 116, 114, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000400000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L3SB_SHR_INV 457
+ .pme_long_desc = "The LR/CTR mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LR_CTR_MAP_FULL_CYC],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LR_CTR_MAP_FULL_CYC]
+ },
[ POWER5_PME_PM_L3SB_SHR_INV ] = {
.pme_name = "PM_L3SB_SHR_INV",
+ .pme_code = 0x710c4,
.pme_short_desc = "L3 slice B transition from shared to invalid",
- .pme_long_desc = "L3 slice B transition from shared to invalid",
- .pme_event_ids = { -1, -1, 94, 98, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000040ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_DATA_FROM_RMEM 458
+ .pme_long_desc = "L3 snooper detects someone doing a store to a line that is Sx in this L3(i.e. invalidate hit SX and dispatched).",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SB_SHR_INV],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SB_SHR_INV]
+ },
[ POWER5_PME_PM_DATA_FROM_RMEM ] = {
.pme_name = "PM_DATA_FROM_RMEM",
+ .pme_code = 0x1c30a1,
.pme_short_desc = "Data loaded from remote memory",
- .pme_long_desc = "Data loaded from remote memory",
- .pme_event_ids = { 19, -1, -1, 15, -1, -1 },
- .pme_group_vector = {
- 0x0002000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_DATA_FROM_L275_MOD 459
+ .pme_long_desc = "The processor's Data Cache was reloaded from memory attached to a different module than this proccessor is located on.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_RMEM],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_RMEM]
+ },
[ POWER5_PME_PM_DATA_FROM_L275_MOD ] = {
.pme_name = "PM_DATA_FROM_L275_MOD",
+ .pme_code = 0x1c30a3,
.pme_short_desc = "Data loaded from L2.75 modified",
- .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of another MCM due to a demand load. ",
- .pme_event_ids = { 15, -1, -1, 13, -1, -1 },
- .pme_group_vector = {
- 0x0004000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU1_DERAT_MISS 460
+ .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 on a different module than this processor is located due to a demand load. ",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_L275_MOD],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_L275_MOD]
+ },
+ [ POWER5_PME_PM_LSU0_REJECT_SRQ ] = {
+ .pme_name = "PM_LSU0_REJECT_SRQ",
+ .pme_code = 0xc60e0,
+ .pme_short_desc = "LSU0 SRQ lhs rejects",
+ .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because of Load Hit Store conditions. Loads are rejected when data is needed from a previous store instruction but store forwarding is not possible because the data is not fully contained in the Store Data Queue or is not yet available in the Store Data Queue.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_REJECT_SRQ],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_REJECT_SRQ]
+ },
[ POWER5_PME_PM_LSU1_DERAT_MISS ] = {
.pme_name = "PM_LSU1_DERAT_MISS",
+ .pme_code = 0x800c6,
.pme_short_desc = "LSU1 DERAT misses",
.pme_long_desc = "A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.",
- .pme_event_ids = { 129, 127, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_DERAT_MISS],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_DERAT_MISS]
},
-#define POWER5_PME_PM_MRK_LSU_FIN 461
[ POWER5_PME_PM_MRK_LSU_FIN ] = {
.pme_name = "PM_MRK_LSU_FIN",
+ .pme_code = 0x400014,
.pme_short_desc = "Marked instruction LSU processing finished",
.pme_long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, -1, -1, 158, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0002000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU_FIN],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU_FIN]
},
-#define POWER5_PME_PM_DTLB_MISS_16M 462
[ POWER5_PME_PM_DTLB_MISS_16M ] = {
.pme_name = "PM_DTLB_MISS_16M",
+ .pme_code = 0xc40c4,
.pme_short_desc = "Data TLB miss for 16M page",
- .pme_long_desc = "Data TLB miss for 16M page",
- .pme_event_ids = { 23, 22, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000800000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_LSU0_FLUSH_UST 463
+ .pme_long_desc = "Data TLB references to 16MB pages that missed the TLB. Page size is determined at TLB reload time.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_DTLB_MISS_16M],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DTLB_MISS_16M]
+ },
[ POWER5_PME_PM_LSU0_FLUSH_UST ] = {
.pme_name = "PM_LSU0_FLUSH_UST",
+ .pme_code = 0xc00c1,
.pme_short_desc = "LSU0 unaligned store flushes",
- .pme_long_desc = "A store was flushed from unit 0 because it was unaligned (crossed a 4k boundary)",
- .pme_event_ids = { 122, 120, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000004000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SC_MOD_TAG 464
+ .pme_long_desc = "A store was flushed from unit 0 because it was unaligned (crossed a 4K boundary).",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_FLUSH_UST],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_FLUSH_UST]
+ },
[ POWER5_PME_PM_L2SC_MOD_TAG ] = {
.pme_name = "PM_L2SC_MOD_TAG",
+ .pme_code = 0x720e2,
.pme_short_desc = "L2 slice C transition from modified to tagged",
- .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.",
- .pme_event_ids = { 98, 96, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000400ULL,
- 0x0000000000000000ULL }
- },
-#define POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY 465
+ .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_MOD_TAG],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_MOD_TAG]
+ },
[ POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY ] = {
.pme_name = "PM_L2SB_RC_DISP_FAIL_CO_BUSY",
- .pme_short_desc = "L2 Slice B RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy",
- .pme_long_desc = "L2 Slice B RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy",
- .pme_event_ids = { 95, 93, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000002ULL,
- 0x0000000000000000ULL }
+ .pme_code = 0x703c1,
+ .pme_short_desc = "L2 slice B RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy",
+ .pme_long_desc = "A Read/Claim Dispatch was rejected at dispatch because the Castout Machine was busy. In the case of an RC starting up on a miss and the victim is valid, the CO machine must be available for the RC to process the access. If the CO is still busy working on an old castout, then the RC must not-ack the access if it is a miss(re-issued by the CIU). If it is a miss and the CO is available to process the castout, the RC will accept the access. Once the RC has finished, it can restart and process new accesses that result in a hit (or miss that doesn't need a CO) even though the CO is still processing a castout from a previous access.",
+ .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY],
+ .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY]
}
};
-#define POWER5_PME_EVENT_COUNT 466
+#define POWER5_PME_EVENT_COUNT 474
+
+static const int power5_group_event_ids[][POWER5_NUM_EVENT_COUNTERS] = {
+ [ 0 ] = { 190, 71, 56, 12, 0, 0 },
+ [ 1 ] = { 2, 195, 49, 12, 0, 0 },
+ [ 2 ] = { 66, 65, 50, 60, 0, 0 },
+ [ 3 ] = { 0, 2, 169, 138, 0, 0 },
+ [ 4 ] = { 6, 6, 149, 59, 0, 0 },
+ [ 5 ] = { 60, 59, 46, 51, 0, 0 },
+ [ 6 ] = { 62, 61, 47, 52, 0, 0 },
+ [ 7 ] = { 143, 143, 113, 119, 0, 0 },
+ [ 8 ] = { 147, 147, 119, 123, 0, 0 },
+ [ 9 ] = { 149, 141, 112, 122, 0, 0 },
+ [ 10 ] = { 212, 73, 117, 18, 0, 0 },
+ [ 11 ] = { 73, 9, 61, 58, 0, 0 },
+ [ 12 ] = { 139, 1, 87, 59, 0, 0 },
+ [ 13 ] = { 126, 135, 13, 91, 0, 0 },
+ [ 14 ] = { 145, 144, 25, 159, 0, 0 },
+ [ 15 ] = { 125, 134, 55, 66, 0, 0 },
+ [ 16 ] = { 123, 132, 120, 191, 0, 0 },
+ [ 17 ] = { 124, 133, 55, 1, 0, 0 },
+ [ 18 ] = { 146, 145, 109, 31, 0, 0 },
+ [ 19 ] = { 73, 140, 25, 16, 0, 0 },
+ [ 20 ] = { 81, 71, 27, 33, 0, 0 },
+ [ 21 ] = { 141, 138, 55, 113, 0, 0 },
+ [ 22 ] = { 119, 128, 109, 59, 0, 0 },
+ [ 23 ] = { 120, 129, 55, 113, 0, 0 },
+ [ 24 ] = { 142, 140, 0, 59, 0, 0 },
+ [ 25 ] = { 121, 130, 109, 59, 0, 0 },
+ [ 26 ] = { 122, 131, 55, 113, 0, 0 },
+ [ 27 ] = { 140, 71, 147, 114, 0, 0 },
+ [ 28 ] = { 70, 13, 55, 10, 0, 0 },
+ [ 29 ] = { 73, 10, 6, 8, 0, 0 },
+ [ 30 ] = { 68, 12, 55, 7, 0, 0 },
+ [ 31 ] = { 57, 11, 55, 9, 0, 0 },
+ [ 32 ] = { 115, 7, 116, 116, 0, 0 },
+ [ 33 ] = { 41, 49, 40, 46, 0, 0 },
+ [ 34 ] = { 11, 114, 48, 11, 0, 0 },
+ [ 35 ] = { 35, 204, 188, 59, 0, 0 },
+ [ 36 ] = { 198, 193, 106, 112, 0, 0 },
+ [ 37 ] = { 117, 126, 52, 57, 0, 0 },
+ [ 38 ] = { 72, 69, 54, 0, 0, 0 },
+ [ 39 ] = { 69, 67, 60, 59, 0, 0 },
+ [ 40 ] = { 210, 184, 1, 3, 0, 0 },
+ [ 41 ] = { 9, 8, 3, 5, 0, 0 },
+ [ 42 ] = { 64, 62, 24, 59, 0, 0 },
+ [ 43 ] = { 20, 21, 100, 106, 0, 0 },
+ [ 44 ] = { 13, 137, 165, 171, 0, 0 },
+ [ 45 ] = { 21, 78, 101, 105, 0, 0 },
+ [ 46 ] = { 26, 23, 103, 108, 0, 0 },
+ [ 47 ] = { 25, 22, 166, 173, 0, 0 },
+ [ 48 ] = { 16, 18, 26, 59, 0, 0 },
+ [ 49 ] = { 16, 18, 187, 15, 0, 0 },
+ [ 50 ] = { 14, 16, 8, 13, 0, 0 },
+ [ 51 ] = { 17, 17, 10, 14, 0, 0 },
+ [ 52 ] = { 78, 74, 59, 63, 0, 0 },
+ [ 53 ] = { 76, 77, 55, 0, 0, 0 },
+ [ 54 ] = { 77, 75, 57, 61, 0, 0 },
+ [ 55 ] = { 79, 76, 58, 62, 0, 0 },
+ [ 56 ] = { 184, 181, 154, 163, 0, 0 },
+ [ 57 ] = { 187, 182, 156, 164, 0, 0 },
+ [ 58 ] = { 183, 183, 189, 165, 0, 0 },
+ [ 59 ] = { 186, 64, 51, 16, 0, 0 },
+ [ 60 ] = { 83, 82, 64, 69, 0, 0 },
+ [ 61 ] = { 85, 84, 66, 71, 0, 0 },
+ [ 62 ] = { 87, 87, 68, 74, 0, 0 },
+ [ 63 ] = { 91, 90, 72, 77, 0, 0 },
+ [ 64 ] = { 93, 92, 74, 79, 0, 0 },
+ [ 65 ] = { 95, 95, 76, 82, 0, 0 },
+ [ 66 ] = { 99, 98, 80, 85, 0, 0 },
+ [ 67 ] = { 101, 100, 82, 87, 0, 0 },
+ [ 68 ] = { 103, 103, 84, 90, 0, 0 },
+ [ 69 ] = { 107, 71, 89, 94, 0, 0 },
+ [ 70 ] = { 73, 108, 93, 98, 0, 0 },
+ [ 71 ] = { 73, 111, 97, 102, 0, 0 },
+ [ 72 ] = { 82, 86, 63, 73, 0, 0 },
+ [ 73 ] = { 90, 94, 71, 81, 0, 0 },
+ [ 74 ] = { 98, 102, 79, 89, 0, 0 },
+ [ 75 ] = { 106, 107, 91, 99, 0, 0 },
+ [ 76 ] = { 108, 109, 88, 96, 0, 0 },
+ [ 77 ] = { 112, 112, 99, 100, 0, 0 },
+ [ 78 ] = { 55, 54, 38, 43, 0, 0 },
+ [ 79 ] = { 56, 53, 39, 44, 0, 0 },
+ [ 80 ] = { 54, 55, 30, 40, 0, 0 },
+ [ 81 ] = { 58, 56, 55, 115, 0, 0 },
+ [ 82 ] = { 40, 48, 29, 39, 0, 0 },
+ [ 83 ] = { 37, 45, 31, 41, 0, 0 },
+ [ 84 ] = { 38, 46, 33, 42, 0, 0 },
+ [ 85 ] = { 43, 51, 55, 37, 0, 0 },
+ [ 86 ] = { 42, 50, 105, 111, 0, 0 },
+ [ 87 ] = { 39, 47, 55, 42, 0, 0 },
+ [ 88 ] = { 36, 44, 30, 59, 0, 0 },
+ [ 89 ] = { 44, 52, 105, 59, 0, 0 },
+ [ 90 ] = { 59, 57, 42, 49, 0, 0 },
+ [ 91 ] = { 171, 172, 45, 47, 0, 0 },
+ [ 92 ] = { 4, 4, 43, 50, 0, 0 },
+ [ 93 ] = { 206, 203, 171, 178, 0, 0 },
+ [ 94 ] = { 205, 202, 173, 180, 0, 0 },
+ [ 95 ] = { 204, 201, 175, 182, 0, 0 },
+ [ 96 ] = { 203, 68, 177, 59, 0, 0 },
+ [ 97 ] = { 202, 196, 55, 176, 0, 0 },
+ [ 98 ] = { 196, 71, 182, 189, 0, 0 },
+ [ 99 ] = { 73, 0, 178, 185, 0, 0 },
+ [ 100 ] = { 73, 15, 180, 187, 0, 0 },
+ [ 101 ] = { 27, 27, 17, 23, 0, 0 },
+ [ 102 ] = { 32, 29, 20, 28, 0, 0 },
+ [ 103 ] = { 33, 33, 21, 27, 0, 0 },
+ [ 104 ] = { 31, 28, 15, 24, 0, 0 },
+ [ 105 ] = { 193, 185, 161, 166, 0, 0 },
+ [ 106 ] = { 194, 189, 160, 59, 0, 0 },
+ [ 107 ] = { 197, 150, 162, 127, 0, 0 },
+ [ 108 ] = { 192, 149, 159, 126, 0, 0 },
+ [ 109 ] = { 156, 155, 125, 20, 0, 0 },
+ [ 110 ] = { 155, 148, 126, 21, 0, 0 },
+ [ 111 ] = { 159, 156, 128, 132, 0, 0 },
+ [ 112 ] = { 153, 152, 124, 128, 0, 0 },
+ [ 113 ] = { 171, 173, 185, 158, 0, 0 },
+ [ 114 ] = { 171, 179, 137, 146, 0, 0 },
+ [ 115 ] = { 172, 158, 138, 147, 0, 0 },
+ [ 116 ] = { 160, 162, 129, 135, 0, 0 },
+ [ 117 ] = { 161, 160, 55, 44, 0, 0 },
+ [ 118 ] = { 163, 166, 131, 138, 0, 0 },
+ [ 119 ] = { 166, 161, 130, 143, 0, 0 },
+ [ 120 ] = { 164, 164, 133, 141, 0, 0 },
+ [ 121 ] = { 162, 161, 55, 137, 0, 0 },
+ [ 122 ] = { 165, 165, 132, 140, 0, 0 },
+ [ 123 ] = { 168, 168, 135, 144, 0, 0 },
+ [ 124 ] = { 170, 170, 55, 144, 0, 0 },
+ [ 125 ] = { 175, 71, 150, 134, 0, 0 },
+ [ 126 ] = { 179, 179, 148, 160, 0, 0 },
+ [ 127 ] = { 178, 178, 136, 148, 0, 0 },
+ [ 128 ] = { 13, 74, 165, 106, 0, 0 },
+ [ 129 ] = { 16, 18, 165, 106, 0, 0 },
+ [ 130 ] = { 81, 21, 165, 106, 0, 0 },
+ [ 131 ] = { 16, 18, 100, 171, 0, 0 },
+ [ 132 ] = { 12, 69, 61, 91, 0, 0 },
+ [ 133 ] = { 9, 8, 3, 1, 0, 0 },
+ [ 134 ] = { 43, 51, 30, 37, 0, 0 },
+ [ 135 ] = { 39, 47, 33, 42, 0, 0 },
+ [ 136 ] = { 36, 44, 30, 40, 0, 0 },
+ [ 137 ] = { 56, 54, 165, 106, 0, 0 },
+ [ 138 ] = { 58, 56, 30, 40, 0, 0 },
+ [ 139 ] = { 55, 53, 39, 44, 0, 0 },
+ [ 140 ] = { 12, 58, 6, 44, 0, 0 },
+ [ 141 ] = { 12, 56, 56, 115, 0, 0 },
+ [ 142 ] = { 12, 72, 100, 171, 0, 0 },
+ [ 143 ] = { 210, 15, 165, 106, 0, 0 },
+ [ 144 ] = { 56, 54, 6, 59, 0, 0 }
+};
-static pmg_power5_group_t power5_groups[] = {
+static const pmg_power_group_t power5_groups[] = {
[ 0 ] = {
.pmg_name = "pm_utilization",
.pmg_desc = "CPI and utilization data",
- .pmg_event_ids = { 190, 71, 56, 12, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[0],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000000a02121eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5162,7 +7302,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 1 ] = {
.pmg_name = "pm_completion",
.pmg_desc = "Completion and cycle counts",
- .pmg_event_ids = { 2, 195, 49, 12, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[1],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000002608261eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5170,7 +7310,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 2 ] = {
.pmg_name = "pm_group_dispatch",
.pmg_desc = "Group dispatch events",
- .pmg_event_ids = { 66, 65, 50, 60, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[2],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4000000ec6c8c212ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5178,7 +7318,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 3 ] = {
.pmg_name = "pm_clb1",
.pmg_desc = "CLB fullness",
- .pmg_event_ids = { 0, 2, 169, 138, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[3],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x015b000180848c4cULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5186,7 +7326,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 4 ] = {
.pmg_name = "pm_clb2",
.pmg_desc = "CLB fullness",
- .pmg_event_ids = { 6, 6, 149, 59, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[4],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x014300028a8ccc02ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5194,7 +7334,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 5 ] = {
.pmg_name = "pm_gct_empty",
.pmg_desc = "GCT empty reasons",
- .pmg_event_ids = { 60, 59, 46, 51, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[5],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4000000008380838ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5202,7 +7342,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 6 ] = {
.pmg_name = "pm_gct_usage",
.pmg_desc = "GCT Usage",
- .pmg_event_ids = { 62, 61, 47, 52, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[6],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000003e3e3e3eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5210,7 +7350,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 7 ] = {
.pmg_name = "pm_lsu1",
.pmg_desc = "LSU LRQ and LMQ events",
- .pmg_event_ids = { 143, 143, 113, 119, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[7],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000f000fccc4cccaULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5218,7 +7358,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 8 ] = {
.pmg_name = "pm_lsu2",
.pmg_desc = "LSU SRQ events",
- .pmg_event_ids = { 147, 147, 119, 123, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[8],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x400e000ecac2ca86ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5226,7 +7366,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 9 ] = {
.pmg_name = "pm_lsu3",
.pmg_desc = "LSU SRQ and LMQ events",
- .pmg_event_ids = { 149, 141, 112, 122, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[9],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010f000a102aca2aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5234,7 +7374,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 10 ] = {
.pmg_name = "pm_prefetch1",
.pmg_desc = "Prefetch stream allocation",
- .pmg_event_ids = { 212, 73, 117, 18, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[10],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x8432000d36c884ceULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5242,7 +7382,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 11 ] = {
.pmg_name = "pm_prefetch2",
.pmg_desc = "Prefetch events",
- .pmg_event_ids = { 73, 9, 61, 58, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[11],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x8103000602cace8eULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5250,7 +7390,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 12 ] = {
.pmg_name = "pm_prefetch3",
.pmg_desc = "L2 prefetch and misc events",
- .pmg_event_ids = { 139, 1, 87, 59, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[12],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x047c000820828602ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5258,7 +7398,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 13 ] = {
.pmg_name = "pm_prefetch4",
.pmg_desc = "Misc prefetch and reject events",
- .pmg_event_ids = { 126, 135, 13, 91, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[13],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x063e000ec0c8cc86ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5266,7 +7406,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 14 ] = {
.pmg_name = "pm_lsu_reject1",
.pmg_desc = "LSU reject events",
- .pmg_event_ids = { 145, 144, 25, 159, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[14],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xc22c000e2010c610ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5274,7 +7414,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 15 ] = {
.pmg_name = "pm_lsu_reject2",
.pmg_desc = "LSU rejects due to reload CDF or tag update collision",
- .pmg_event_ids = { 125, 134, 55, 66, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[15],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x820c000dc4cc02ceULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5282,7 +7422,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 16 ] = {
.pmg_name = "LSU rejects due to ERAT",
.pmg_desc = " held instuctions",
- .pmg_event_ids = { 123, 132, 120, 191, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[16],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x420c000fc6cec0c8ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5290,7 +7430,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 17 ] = {
.pmg_name = "pm_lsu_reject4",
.pmg_desc = "LSU0/1 reject LMQ full",
- .pmg_event_ids = { 124, 133, 55, 1, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[17],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x820c000dc2ca02c8ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5298,7 +7438,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 18 ] = {
.pmg_name = "pm_lsu_reject5",
.pmg_desc = "LSU misc reject and flush events",
- .pmg_event_ids = { 146, 145, 109, 31, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[18],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x420c000c10208a8eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5306,7 +7446,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 19 ] = {
.pmg_name = "pm_flush1",
.pmg_desc = "Misc flush events",
- .pmg_event_ids = { 73, 140, 25, 16, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[19],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xc0f000020210c68eULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5314,7 +7454,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 20 ] = {
.pmg_name = "pm_flush2",
.pmg_desc = "Flushes due to scoreboard and sync",
- .pmg_event_ids = { 81, 71, 27, 33, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[20],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xc08000038002c4c2ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5322,7 +7462,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 21 ] = {
.pmg_name = "pm_lsu_flush_srq_lrq",
.pmg_desc = "LSU flush by SRQ and LRQ events",
- .pmg_event_ids = { 141, 138, 55, 113, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[21],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x40c000002020028aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5330,7 +7470,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 22 ] = {
.pmg_name = "pm_lsu_flush_lrq",
.pmg_desc = "LSU0/1 flush due to LRQ",
- .pmg_event_ids = { 119, 128, 109, 59, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[22],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x40c00000848c8a02ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5338,7 +7478,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 23 ] = {
.pmg_name = "pm_lsu_flush_srq",
.pmg_desc = "LSU0/1 flush due to SRQ",
- .pmg_event_ids = { 120, 129, 55, 113, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[23],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x40c00000868e028aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5346,7 +7486,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 24 ] = {
.pmg_name = "pm_lsu_flush_unaligned",
.pmg_desc = "LSU flush due to unaligned data",
- .pmg_event_ids = { 142, 140, 0, 59, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[24],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x80c000021010c802ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5354,7 +7494,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 25 ] = {
.pmg_name = "pm_lsu_flush_uld",
.pmg_desc = "LSU0/1 flush due to unaligned load",
- .pmg_event_ids = { 121, 130, 109, 59, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[25],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x40c0000080888a02ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5362,7 +7502,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 26 ] = {
.pmg_name = "pm_lsu_flush_ust",
.pmg_desc = "LSU0/1 flush due to unaligned store",
- .pmg_event_ids = { 122, 131, 55, 113, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[26],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x40c00000828a028aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5370,7 +7510,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 27 ] = {
.pmg_name = "pm_lsu_flush_full",
.pmg_desc = "LSU flush due to LRQ/SRQ full",
- .pmg_event_ids = { 140, 71, 147, 114, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[27],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xc0200009ce0210c0ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5378,7 +7518,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 28 ] = {
.pmg_name = "pm_lsu_stall1",
.pmg_desc = "LSU Stalls",
- .pmg_event_ids = { 70, 13, 55, 10, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[28],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4000000028300234ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5386,7 +7526,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 29 ] = {
.pmg_name = "pm_lsu_stall2",
.pmg_desc = "LSU Stalls",
- .pmg_event_ids = { 73, 10, 6, 8, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[29],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4000000002341e36ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5394,7 +7534,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 30 ] = {
.pmg_name = "pm_fxu_stall",
.pmg_desc = "FXU Stalls",
- .pmg_event_ids = { 68, 12, 55, 7, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[30],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4000000822320232ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5402,7 +7542,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 31 ] = {
.pmg_name = "pm_fpu_stall",
.pmg_desc = "FPU Stalls",
- .pmg_event_ids = { 57, 11, 55, 9, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[31],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4000000020360230ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5410,7 +7550,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 32 ] = {
.pmg_name = "pm_queue_full",
.pmg_desc = "BRQ LRQ LMQ queue full",
- .pmg_event_ids = { 115, 7, 116, 116, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[32],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x400b0009ce8a84ceULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5418,7 +7558,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 33 ] = {
.pmg_name = "pm_issueq_full",
.pmg_desc = "FPU FX full",
- .pmg_event_ids = { 41, 49, 40, 46, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[33],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x40000000868e8088ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5426,7 +7566,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 34 ] = {
.pmg_name = "pm_mapper_full1",
.pmg_desc = "CR CTR GPR mapper full",
- .pmg_event_ids = { 11, 114, 48, 11, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[34],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x40000002888cca82ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5434,7 +7574,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 35 ] = {
.pmg_name = "pm_mapper_full2",
.pmg_desc = "FPR XER mapper full",
- .pmg_event_ids = { 35, 204, 188, 59, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[35],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4103000282843602ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5442,7 +7582,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 36 ] = {
.pmg_name = "pm_misc_load",
.pmg_desc = "Non-cachable loads and stcx events",
- .pmg_event_ids = { 198, 193, 106, 112, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[36],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0438000cc2ca828aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5450,7 +7590,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 37 ] = {
.pmg_name = "pm_ic_demand",
.pmg_desc = "ICache demand from BR redirect",
- .pmg_event_ids = { 117, 126, 52, 57, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[37],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x800c000fc6cec0c2ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5458,7 +7598,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 38 ] = {
.pmg_name = "pm_ic_pref",
.pmg_desc = "ICache prefetch",
- .pmg_event_ids = { 72, 69, 54, 0, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[38],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x8000000ccecc8e1aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5466,7 +7606,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 39 ] = {
.pmg_name = "pm_ic_miss",
.pmg_desc = "ICache misses",
- .pmg_event_ids = { 69, 67, 60, 59, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[39],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4003000e32cec802ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5474,7 +7614,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 40 ] = {
.pmg_name = "Branch mispredict",
.pmg_desc = " TLB and SLB misses",
- .pmg_event_ids = { 210, 184, 1, 3, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[40],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x808000031010caccULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5482,7 +7622,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 41 ] = {
.pmg_name = "pm_branch1",
.pmg_desc = "Branch operations",
- .pmg_event_ids = { 9, 8, 3, 5, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[41],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x800000030e0e0e0eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5490,7 +7630,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 42 ] = {
.pmg_name = "pm_branch2",
.pmg_desc = "Branch operations",
- .pmg_event_ids = { 64, 62, 24, 59, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[42],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4000000ccacc8c02ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5498,7 +7638,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 43 ] = {
.pmg_name = "pm_L1_tlbmiss",
.pmg_desc = "L1 load and TLB misses",
- .pmg_event_ids = { 20, 21, 100, 106, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[43],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00b000008e881020ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5506,7 +7646,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 44 ] = {
.pmg_name = "pm_L1_DERAT_miss",
.pmg_desc = "L1 store and DERAT misses",
- .pmg_event_ids = { 13, 137, 165, 171, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[44],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00b300000e202086ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5514,7 +7654,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 45 ] = {
.pmg_name = "pm_L1_slbmiss",
.pmg_desc = "L1 load and SLB misses",
- .pmg_event_ids = { 21, 78, 101, 105, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[45],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00b000008a82848cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5522,7 +7662,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 46 ] = {
.pmg_name = "pm_L1_dtlbmiss_4K",
.pmg_desc = "L1 load references and 4K Data TLB references and misses",
- .pmg_event_ids = { 26, 23, 103, 108, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[46],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x08f0000084808088ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5530,7 +7670,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 47 ] = {
.pmg_name = "pm_L1_dtlbmiss_16M",
.pmg_desc = "L1 store references and 16M Data TLB references and misses",
- .pmg_event_ids = { 25, 22, 166, 173, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[47],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x08f000008c88828aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5538,7 +7678,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 48 ] = {
.pmg_name = "pm_dsource1",
.pmg_desc = "L3 cache and memory data access",
- .pmg_event_ids = { 16, 18, 26, 59, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[48],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x400300001c0e8e02ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5546,7 +7686,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 49 ] = {
.pmg_name = "pm_dsource2",
.pmg_desc = "L3 cache and memory data access",
- .pmg_event_ids = { 16, 18, 187, 15, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[49],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000300031c0e360eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5554,7 +7694,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 50 ] = {
.pmg_name = "pm_dsource_L2",
.pmg_desc = "L2 cache data access",
- .pmg_event_ids = { 14, 16, 8, 13, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[50],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000300032e2e2e2eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5562,7 +7702,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 51 ] = {
.pmg_name = "pm_dsource_L3",
.pmg_desc = "L3 cache data access",
- .pmg_event_ids = { 17, 17, 10, 14, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[51],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000300033c3c3c3cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5570,7 +7710,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 52 ] = {
.pmg_name = "pm_isource1",
.pmg_desc = "Instruction source information",
- .pmg_event_ids = { 78, 74, 59, 63, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[52],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x8000000c1a1a1a0cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5578,7 +7718,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 53 ] = {
.pmg_name = "pm_isource2",
.pmg_desc = "Instruction source information",
- .pmg_event_ids = { 76, 77, 55, 0, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[53],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x8000000c0c0c021aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5586,7 +7726,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 54 ] = {
.pmg_name = "pm_isource_L2",
.pmg_desc = "L2 instruction source information",
- .pmg_event_ids = { 77, 75, 57, 61, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[54],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x8000000c2c2c2c2cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5594,7 +7734,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 55 ] = {
.pmg_name = "pm_isource_L3",
.pmg_desc = "L3 instruction source information",
- .pmg_event_ids = { 79, 76, 58, 62, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[55],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x8000000c3a3a3a3aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5602,7 +7742,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 56 ] = {
.pmg_name = "pm_pteg_source1",
.pmg_desc = "PTEG source information",
- .pmg_event_ids = { 184, 181, 154, 163, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[56],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000200032e2e2e2eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5610,7 +7750,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 57 ] = {
.pmg_name = "pm_pteg_source2",
.pmg_desc = "PTEG source information",
- .pmg_event_ids = { 187, 182, 156, 164, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[57],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000200033c3c3c3cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5618,7 +7758,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 58 ] = {
.pmg_name = "pm_pteg_source3",
.pmg_desc = "PTEG source information",
- .pmg_event_ids = { 183, 183, 189, 165, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[58],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000200030e0e360eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5626,7 +7766,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 59 ] = {
.pmg_name = "pm_pteg_source4",
.pmg_desc = "L3 PTEG and group disptach events",
- .pmg_event_ids = { 186, 64, 51, 16, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[59],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x003200001c04048eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5634,7 +7774,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 60 ] = {
.pmg_name = "pm_L2SA_ld",
.pmg_desc = "L2 slice A load events",
- .pmg_event_ids = { 83, 82, 64, 69, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[60],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055400580c080c0ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5642,7 +7782,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 61 ] = {
.pmg_name = "pm_L2SA_st",
.pmg_desc = "L2 slice A store events",
- .pmg_event_ids = { 85, 84, 66, 71, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[61],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055800580c080c0ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5650,7 +7790,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 62 ] = {
.pmg_name = "pm_L2SA_st2",
.pmg_desc = "L2 slice A store events",
- .pmg_event_ids = { 87, 87, 68, 74, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[62],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055c00580c080c0ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5658,7 +7798,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 63 ] = {
.pmg_name = "pm_L2SB_ld",
.pmg_desc = "L2 slice B load events",
- .pmg_event_ids = { 91, 90, 72, 77, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[63],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055400582c282c2ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5666,7 +7806,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 64 ] = {
.pmg_name = "pm_L2SB_st",
.pmg_desc = "L2 slice B store events",
- .pmg_event_ids = { 93, 92, 74, 79, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[64],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055800582c282c2ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5674,7 +7814,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 65 ] = {
.pmg_name = "pm_L2SB_st2",
.pmg_desc = "L2 slice B store events",
- .pmg_event_ids = { 95, 95, 76, 82, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[65],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055c00582c282c2ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5682,7 +7822,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 66 ] = {
.pmg_name = "pm_L2SB_ld",
.pmg_desc = "L2 slice C load events",
- .pmg_event_ids = { 99, 98, 80, 85, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[66],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055400584c484c4ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5690,7 +7830,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 67 ] = {
.pmg_name = "pm_L2SB_st",
.pmg_desc = "L2 slice C store events",
- .pmg_event_ids = { 101, 100, 82, 87, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[67],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055800584c484c4ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5698,7 +7838,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 68 ] = {
.pmg_name = "pm_L2SB_st2",
.pmg_desc = "L2 slice C store events",
- .pmg_event_ids = { 103, 103, 84, 90, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[68],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055c00584c484c4ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5706,7 +7846,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 69 ] = {
.pmg_name = "pm_L3SA_trans",
.pmg_desc = "L3 slice A state transistions",
- .pmg_event_ids = { 107, 71, 89, 94, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[69],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3015000ac602c686ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5714,7 +7854,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 70 ] = {
.pmg_name = "pm_L3SB_trans",
.pmg_desc = "L3 slice B state transistions",
- .pmg_event_ids = { 73, 108, 93, 98, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[70],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3015000602c8c888ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5722,7 +7862,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 71 ] = {
.pmg_name = "pm_L3SC_trans",
.pmg_desc = "L3 slice C state transistions",
- .pmg_event_ids = { 73, 111, 97, 102, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[71],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3015000602caca8aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5730,7 +7870,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 72 ] = {
.pmg_name = "pm_L2SA_trans",
.pmg_desc = "L2 slice A state transistions",
- .pmg_event_ids = { 82, 86, 63, 73, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[72],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055000ac080c080ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5738,7 +7878,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 73 ] = {
.pmg_name = "pm_L2SB_trans",
.pmg_desc = "L2 slice B state transistions",
- .pmg_event_ids = { 90, 94, 71, 81, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[73],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055000ac282c282ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5746,7 +7886,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 74 ] = {
.pmg_name = "pm_L2SC_trans",
.pmg_desc = "L2 slice C state transistions",
- .pmg_event_ids = { 98, 102, 79, 89, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[74],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055000ac484c484ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5754,7 +7894,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 75 ] = {
.pmg_name = "pm_L3SAB_retry",
.pmg_desc = "L3 slice A/B snoop retry and all CI/CO busy",
- .pmg_event_ids = { 106, 107, 91, 99, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[75],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3005100fc6c8c6c8ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5762,7 +7902,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 76 ] = {
.pmg_name = "pm_L3SAB_hit",
.pmg_desc = "L3 slice A/B hit and reference",
- .pmg_event_ids = { 108, 109, 88, 96, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[76],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3050100086888688ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5770,7 +7910,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 77 ] = {
.pmg_name = "pm_L3SC_retry_hit",
.pmg_desc = "L3 slice C hit & snoop retry",
- .pmg_event_ids = { 112, 112, 99, 100, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[77],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x3055100aca8aca8aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5778,7 +7918,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 78 ] = {
.pmg_name = "pm_fpu1",
.pmg_desc = "Floating Point events",
- .pmg_event_ids = { 55, 54, 38, 43, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[78],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000010101020ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5786,7 +7926,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 79 ] = {
.pmg_name = "pm_fpu2",
.pmg_desc = "Floating Point events",
- .pmg_event_ids = { 56, 53, 39, 44, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[79],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000020202010ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5794,7 +7934,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 80 ] = {
.pmg_name = "pm_fpu3",
.pmg_desc = "Floating point events",
- .pmg_event_ids = { 54, 55, 30, 40, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[80],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000c1010868eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5802,7 +7942,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 81 ] = {
.pmg_name = "pm_fpu4",
.pmg_desc = "Floating point events",
- .pmg_event_ids = { 58, 56, 55, 115, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[81],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0430000c20200220ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5810,7 +7950,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 82 ] = {
.pmg_name = "pm_fpu5",
.pmg_desc = "Floating point events by unit",
- .pmg_event_ids = { 40, 48, 29, 39, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[82],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00000000848c848cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5818,7 +7958,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 83 ] = {
.pmg_name = "pm_fpu6",
.pmg_desc = "Floating point events by unit",
- .pmg_event_ids = { 37, 45, 31, 41, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[83],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000cc0c88088ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5826,7 +7966,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 84 ] = {
.pmg_name = "pm_fpu7",
.pmg_desc = "Floating point events by unit",
- .pmg_event_ids = { 38, 46, 33, 42, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[84],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000008088828aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5834,7 +7974,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 85 ] = {
.pmg_name = "pm_fpu8",
.pmg_desc = "Floating point events by unit",
- .pmg_event_ids = { 43, 51, 55, 37, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[85],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000dc2ca02c0ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5842,7 +7982,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 86 ] = {
.pmg_name = "pm_fpu9",
.pmg_desc = "Floating point events by unit",
- .pmg_event_ids = { 42, 50, 105, 111, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[86],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0430000cc6ce8088ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5850,7 +7990,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 87 ] = {
.pmg_name = "pm_fpu10",
.pmg_desc = "Floating point events by unit",
- .pmg_event_ids = { 39, 47, 55, 42, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[87],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00000000828a028aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5858,7 +7998,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 88 ] = {
.pmg_name = "pm_fpu11",
.pmg_desc = "Floating point events by unit",
- .pmg_event_ids = { 36, 44, 30, 59, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[88],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00000000868e8602ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5866,7 +8006,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 89 ] = {
.pmg_name = "pm_fpu12",
.pmg_desc = "Floating point events by unit",
- .pmg_event_ids = { 44, 52, 105, 59, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[89],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0430000cc4cc8002ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5874,7 +8014,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 90 ] = {
.pmg_name = "pm_fxu1",
.pmg_desc = "Fixed Point events",
- .pmg_event_ids = { 59, 57, 42, 49, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[90],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000024242424ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5882,7 +8022,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 91 ] = {
.pmg_name = "pm_fxu2",
.pmg_desc = "Fixed Point events",
- .pmg_event_ids = { 171, 172, 45, 47, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[91],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4000000604221020ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5890,7 +8030,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 92 ] = {
.pmg_name = "pm_fxu3",
.pmg_desc = "Fixed Point events",
- .pmg_event_ids = { 4, 4, 43, 50, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[92],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x404000038688c4ccULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5898,7 +8038,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 93 ] = {
.pmg_name = "pm_smt_priorities1",
.pmg_desc = "Thread priority events",
- .pmg_event_ids = { 206, 203, 171, 178, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[93],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0005000fc6ccc6c8ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5906,7 +8046,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 94 ] = {
.pmg_name = "pm_smt_priorities2",
.pmg_desc = "Thread priority events",
- .pmg_event_ids = { 205, 202, 173, 180, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[94],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0005000fc4cacaccULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5914,7 +8054,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 95 ] = {
.pmg_name = "pm_smt_priorities3",
.pmg_desc = "Thread priority events",
- .pmg_event_ids = { 204, 201, 175, 182, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[95],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0005000fc2c8c4c2ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5922,7 +8062,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 96 ] = {
.pmg_name = "pm_smt_priorities4",
.pmg_desc = "Thread priority events",
- .pmg_event_ids = { 203, 68, 177, 59, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[96],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0005000ac016c002ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5930,7 +8070,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 97 ] = {
.pmg_name = "pm_smt_both",
.pmg_desc = "Thread common events",
- .pmg_event_ids = { 202, 196, 55, 176, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[97],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0010000016260208ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5938,7 +8078,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 98 ] = {
.pmg_name = "pm_smt_selection",
.pmg_desc = "Thread selection",
- .pmg_event_ids = { 196, 71, 182, 189, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[98],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0090000086028082ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5946,7 +8086,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 99 ] = {
.pmg_name = "pm_smt_selectover1",
.pmg_desc = "Thread selection overide",
- .pmg_event_ids = { 73, 0, 178, 185, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[99],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0050000002808488ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5954,7 +8094,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 100 ] = {
.pmg_name = "pm_smt_selectover2",
.pmg_desc = "Thread selection overide",
- .pmg_event_ids = { 73, 15, 180, 187, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[100],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00100000021e8a86ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -5962,7 +8102,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 101 ] = {
.pmg_name = "pm_fabric1",
.pmg_desc = "Fabric events",
- .pmg_event_ids = { 27, 27, 17, 23, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[101],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x305500058ece8eceULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5970,7 +8110,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 102 ] = {
.pmg_name = "pm_fabric2",
.pmg_desc = "Fabric data movement",
- .pmg_event_ids = { 32, 29, 20, 28, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[102],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x305500858ece8eceULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5978,7 +8118,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 103 ] = {
.pmg_name = "pm_fabric3",
.pmg_desc = "Fabric data movement",
- .pmg_event_ids = { 33, 33, 21, 27, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[103],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x305501858ece8eceULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5986,7 +8126,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 104 ] = {
.pmg_name = "pm_fabric4",
.pmg_desc = "Fabric data movement",
- .pmg_event_ids = { 31, 28, 15, 24, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[104],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x705401068ecec68eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -5994,7 +8134,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 105 ] = {
.pmg_name = "pm_snoop1",
.pmg_desc = "Snoop retry",
- .pmg_event_ids = { 193, 185, 161, 166, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[105],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x305500058ccc8cccULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6002,7 +8142,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 106 ] = {
.pmg_name = "pm_snoop2",
.pmg_desc = "Snoop read retry",
- .pmg_event_ids = { 194, 189, 160, 59, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[106],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x30540a048ccc8c02ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6010,7 +8150,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 107 ] = {
.pmg_name = "pm_snoop3",
.pmg_desc = "Snoop write retry",
- .pmg_event_ids = { 197, 150, 162, 127, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[107],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x30550c058ccc8cccULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6018,7 +8158,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 108 ] = {
.pmg_name = "pm_snoop4",
.pmg_desc = "Snoop partial write retry",
- .pmg_event_ids = { 192, 149, 159, 126, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[108],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x30550e058ccc8cccULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6026,7 +8166,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 109 ] = {
.pmg_name = "pm_mem_rq",
.pmg_desc = "Memory read queue dispatch",
- .pmg_event_ids = { 156, 155, 125, 20, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[109],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x705402058ccc8cceULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6034,7 +8174,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 110 ] = {
.pmg_name = "pm_mem_read",
.pmg_desc = "Memory read complete and cancel",
- .pmg_event_ids = { 155, 148, 126, 21, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[110],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x305404048ccc8c06ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6042,7 +8182,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 111 ] = {
.pmg_name = "pm_mem_wq",
.pmg_desc = "Memory write queue dispatch",
- .pmg_event_ids = { 159, 156, 128, 132, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[111],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x305506058ccc8cccULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6050,7 +8190,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 112 ] = {
.pmg_name = "pm_mem_pwq",
.pmg_desc = "Memory partial write queue",
- .pmg_event_ids = { 153, 152, 124, 128, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[112],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x305508058ccc8cccULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6058,7 +8198,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 113 ] = {
.pmg_name = "pm_threshold",
.pmg_desc = "Thresholding",
- .pmg_event_ids = { 171, 173, 185, 158, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[113],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0008000404c41628ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6066,7 +8206,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 114 ] = {
.pmg_name = "pm_mrk_grp1",
.pmg_desc = "Marked group events",
- .pmg_event_ids = { 171, 179, 137, 146, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[114],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0008000404c60a26ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6074,7 +8214,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 115 ] = {
.pmg_name = "pm_mrk_grp2",
.pmg_desc = "Marked group events",
- .pmg_event_ids = { 172, 158, 138, 147, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[115],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x410300022a0ac822ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6082,7 +8222,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 116 ] = {
.pmg_name = "pm_mrk_dsource1",
.pmg_desc = "Marked data from ",
- .pmg_event_ids = { 160, 162, 129, 135, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[116],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010b00030e404444ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6090,7 +8230,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 117 ] = {
.pmg_name = "pm_mrk_dsource2",
.pmg_desc = "Marked data from",
- .pmg_event_ids = { 161, 160, 55, 44, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[117],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010b00002e440210ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6098,7 +8238,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 118 ] = {
.pmg_name = "pm_mrk_dsource3",
.pmg_desc = "Marked data from",
- .pmg_event_ids = { 163, 166, 131, 138, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[118],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010b00031c484c4cULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6106,7 +8246,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 119 ] = {
.pmg_name = "pm_mrk_dsource4",
.pmg_desc = "Marked data from",
- .pmg_event_ids = { 166, 161, 130, 143, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[119],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010b000342462e42ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6114,7 +8254,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 120 ] = {
.pmg_name = "pm_mrk_dsource5",
.pmg_desc = "Marked data from",
- .pmg_event_ids = { 164, 164, 133, 141, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[120],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010b00033c4c4040ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6122,7 +8262,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 121 ] = {
.pmg_name = "pm_mrk_dsource6",
.pmg_desc = "Marked data from",
- .pmg_event_ids = { 162, 161, 55, 137, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[121],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010b000146460246ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6130,7 +8270,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 122 ] = {
.pmg_name = "pm_mrk_dsource7",
.pmg_desc = "Marked data from",
- .pmg_event_ids = { 165, 165, 132, 140, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[122],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x010b00034e4e3c4eULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6138,7 +8278,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 123 ] = {
.pmg_name = "pm_mrk_lbmiss",
.pmg_desc = "Marked TLB and SLB misses",
- .pmg_event_ids = { 168, 168, 135, 144, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[123],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0cf00000828a8c8eULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6146,7 +8286,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 124 ] = {
.pmg_name = "pm_mrk_lbref",
.pmg_desc = "Marked TLB and SLB references",
- .pmg_event_ids = { 170, 170, 55, 144, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[124],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0cf00000868e028eULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6154,7 +8294,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 125 ] = {
.pmg_name = "pm_mrk_lsmiss",
.pmg_desc = "Marked load and store miss",
- .pmg_event_ids = { 175, 71, 150, 134, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[125],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000800081002060aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6162,7 +8302,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 126 ] = {
.pmg_name = "pm_mrk_ulsflush",
.pmg_desc = "Mark unaligned load and store flushes",
- .pmg_event_ids = { 179, 179, 148, 160, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[126],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0028000406c62020ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6170,7 +8310,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 127 ] = {
.pmg_name = "pm_mrk_misc",
.pmg_desc = "Misc marked instructions",
- .pmg_event_ids = { 178, 178, 136, 148, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[127],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00080008cc062816ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -6178,7 +8318,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 128 ] = {
.pmg_name = "pm_lsref_L1",
.pmg_desc = "Load/Store operations and L1 activity",
- .pmg_event_ids = { 13, 74, 165, 106, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[128],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x803300040e1a2020ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6186,7 +8326,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 129 ] = {
.pmg_name = "Load/Store operations and L2",
.pmg_desc = "L3 activity",
- .pmg_event_ids = { 16, 18, 165, 106, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[129],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x003300001c0e2020ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6194,7 +8334,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 130 ] = {
.pmg_name = "pm_lsref_tlbmiss",
.pmg_desc = "Load/Store operations and TLB misses",
- .pmg_event_ids = { 81, 21, 165, 106, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[130],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00b0000080882020ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6202,7 +8342,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 131 ] = {
.pmg_name = "pm_Dmiss",
.pmg_desc = "Data cache misses",
- .pmg_event_ids = { 16, 18, 100, 171, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[131],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x003300001c0e1086ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6210,7 +8350,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 132 ] = {
.pmg_name = "pm_prefetchX",
.pmg_desc = "Prefetch events",
- .pmg_event_ids = { 12, 69, 61, 91, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[132],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x853300061eccce86ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6218,7 +8358,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 133 ] = {
.pmg_name = "pm_branchX",
.pmg_desc = "Branch operations",
- .pmg_event_ids = { 9, 8, 3, 1, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[133],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x800000030e0e0ec8ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6226,7 +8366,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 134 ] = {
.pmg_name = "pm_fpuX1",
.pmg_desc = "Floating point events by unit",
- .pmg_event_ids = { 43, 51, 30, 37, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[134],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000dc2ca86c0ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6234,7 +8374,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 135 ] = {
.pmg_name = "pm_fpuX2",
.pmg_desc = "Floating point events by unit",
- .pmg_event_ids = { 39, 47, 33, 42, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[135],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00000000828a828aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6242,7 +8382,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 136 ] = {
.pmg_name = "pm_fpuX3",
.pmg_desc = "Floating point events by unit",
- .pmg_event_ids = { 36, 44, 30, 40, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[136],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00000000868e868eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6250,7 +8390,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 137 ] = {
.pmg_name = "pm_fpuX4",
.pmg_desc = "Floating point and L1 events",
- .pmg_event_ids = { 56, 54, 165, 106, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[137],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0030000020102020ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6258,7 +8398,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 138 ] = {
.pmg_name = "pm_fpuX5",
.pmg_desc = "Floating point events",
- .pmg_event_ids = { 58, 56, 30, 40, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[138],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000c2020868eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6266,7 +8406,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 139 ] = {
.pmg_name = "pm_fpuX6",
.pmg_desc = "Floating point events",
- .pmg_event_ids = { 55, 53, 39, 44, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[139],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000010202010ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6274,7 +8414,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 140 ] = {
.pmg_name = "pm_hpmcount1",
.pmg_desc = "HPM group for set 1 ",
- .pmg_event_ids = { 12, 58, 6, 44, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[140],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000001e281e10ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6282,7 +8422,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 141 ] = {
.pmg_name = "pm_hpmcount2",
.pmg_desc = "HPM group for set 2",
- .pmg_event_ids = { 12, 56, 56, 115, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[141],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x043000041e201220ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6290,7 +8430,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 142 ] = {
.pmg_name = "pm_hpmcount3",
.pmg_desc = "HPM group for set 3 ",
- .pmg_event_ids = { 12, 72, 100, 171, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[142],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x403000041ec21086ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6298,7 +8438,7 @@ static pmg_power5_group_t power5_groups[] = {
[ 143 ] = {
.pmg_name = "pm_hpmcount4",
.pmg_desc = "HPM group for set 7",
- .pmg_event_ids = { 210, 15, 165, 106, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[143],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00b00000101e2020ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6306,11 +8446,12 @@ static pmg_power5_group_t power5_groups[] = {
[ 144 ] = {
.pmg_name = "pm_1flop_with_fma",
.pmg_desc = "One flop instructions plus FMA",
- .pmg_event_ids = { 56, 54, 6, 59, 0, 0 },
+ .pmg_event_ids = power5_group_event_ids[144],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000020101e02ULL,
.pmg_mmcra = 0x0000000000000000ULL
}
};
+
#endif
diff --git a/src/libpfm-3.y/lib/power6_events.h b/src/libpfm-3.y/lib/power6_events.h
index b0c80f2c5e3480018ed2dd7ddbd5b3f094b3658d..16e7762f6fdbfc0ff7ec3706c224b39aac1c2806 100644
--- a/src/libpfm-3.y/lib/power6_events.h
+++ b/src/libpfm-3.y/lib/power6_events.h
@@ -20,6651 +20,9072 @@
* hand.
*
*/
-static pme_power6_entry_t power6_pe[] = {
#define POWER6_PME_PM_LSU_REJECT_STQ_FULL 0
+#define POWER6_PME_PM_DPU_HELD_FXU_MULTI 1
+#define POWER6_PME_PM_VMX1_STALL 2
+#define POWER6_PME_PM_PMC2_SAVED 3
+#define POWER6_PME_PM_L2SB_IC_INV 4
+#define POWER6_PME_PM_IERAT_MISS_64K 5
+#define POWER6_PME_PM_THRD_PRIO_DIFF_3or4_CYC 6
+#define POWER6_PME_PM_LD_REF_L1_BOTH 7
+#define POWER6_PME_PM_FPU1_FCONV 8
+#define POWER6_PME_PM_IBUF_FULL_COUNT 9
+#define POWER6_PME_PM_MRK_LSU_DERAT_MISS 10
+#define POWER6_PME_PM_MRK_ST_CMPL 11
+#define POWER6_PME_PM_L2_CASTOUT_MOD 12
+#define POWER6_PME_PM_FPU1_ST_FOLDED 13
+#define POWER6_PME_PM_MRK_INST_TIMEO 14
+#define POWER6_PME_PM_DPU_WT 15
+#define POWER6_PME_PM_DPU_HELD_RESTART 16
+#define POWER6_PME_PM_IERAT_MISS 17
+#define POWER6_PME_PM_FPU_SINGLE 18
+#define POWER6_PME_PM_MRK_PTEG_FROM_LMEM 19
+#define POWER6_PME_PM_HV_COUNT 20
+#define POWER6_PME_PM_L2SA_ST_HIT 21
+#define POWER6_PME_PM_L2_LD_MISS_INST 22
+#define POWER6_PME_PM_EXT_INT 23
+#define POWER6_PME_PM_LSU1_LDF 24
+#define POWER6_PME_PM_FAB_CMD_ISSUED 25
+#define POWER6_PME_PM_PTEG_FROM_L21 26
+#define POWER6_PME_PM_L2SA_MISS 27
+#define POWER6_PME_PM_PTEG_FROM_RL2L3_MOD 28
+#define POWER6_PME_PM_DPU_WT_COUNT 29
+#define POWER6_PME_PM_MRK_PTEG_FROM_L25_MOD 30
+#define POWER6_PME_PM_LD_HIT_L2 31
+#define POWER6_PME_PM_PTEG_FROM_DL2L3_SHR 32
+#define POWER6_PME_PM_MEM_DP_RQ_GLOB_LOC 33
+#define POWER6_PME_PM_L3SA_MISS 34
+#define POWER6_PME_PM_NO_ITAG_COUNT 35
+#define POWER6_PME_PM_DSLB_MISS 36
+#define POWER6_PME_PM_LSU_FLUSH_ALIGN 37
+#define POWER6_PME_PM_DPU_HELD_FPU_CR 38
+#define POWER6_PME_PM_PTEG_FROM_L2MISS 39
+#define POWER6_PME_PM_MRK_DATA_FROM_DMEM 40
+#define POWER6_PME_PM_PTEG_FROM_LMEM 41
+#define POWER6_PME_PM_MRK_DERAT_REF_64K 42
+#define POWER6_PME_PM_L2SA_LD_REQ_INST 43
+#define POWER6_PME_PM_MRK_DERAT_MISS_16M 44
+#define POWER6_PME_PM_DATA_FROM_DL2L3_MOD 45
+#define POWER6_PME_PM_FPU0_FXMULT 46
+#define POWER6_PME_PM_L3SB_MISS 47
+#define POWER6_PME_PM_STCX_CANCEL 48
+#define POWER6_PME_PM_L2SA_LD_MISS_DATA 49
+#define POWER6_PME_PM_IC_INV_L2 50
+#define POWER6_PME_PM_DPU_HELD 51
+#define POWER6_PME_PM_PMC1_OVERFLOW 52
+#define POWER6_PME_PM_THRD_PRIO_6_CYC 53
+#define POWER6_PME_PM_MRK_PTEG_FROM_L3MISS 54
+#define POWER6_PME_PM_MRK_LSU0_REJECT_UST 55
+#define POWER6_PME_PM_MRK_INST_DISP 56
+#define POWER6_PME_PM_LARX 57
+#define POWER6_PME_PM_INST_CMPL 58
+#define POWER6_PME_PM_FXU_IDLE 59
+#define POWER6_PME_PM_MRK_DATA_FROM_DL2L3_MOD 60
+#define POWER6_PME_PM_L2_LD_REQ_DATA 61
+#define POWER6_PME_PM_LSU_DERAT_MISS_CYC 62
+#define POWER6_PME_PM_DPU_HELD_POWER_COUNT 63
+#define POWER6_PME_PM_INST_FROM_RL2L3_MOD 64
+#define POWER6_PME_PM_DATA_FROM_DMEM_CYC 65
+#define POWER6_PME_PM_DATA_FROM_DMEM 66
+#define POWER6_PME_PM_LSU_REJECT_PARTIAL_SECTOR 67
+#define POWER6_PME_PM_LSU_REJECT_DERAT_MPRED 68
+#define POWER6_PME_PM_LSU1_REJECT_ULD 69
+#define POWER6_PME_PM_DATA_FROM_L3_CYC 70
+#define POWER6_PME_PM_FXU1_BUSY_FXU0_IDLE 71
+#define POWER6_PME_PM_INST_FROM_MEM_DP 72
+#define POWER6_PME_PM_LSU_FLUSH_DSI 73
+#define POWER6_PME_PM_MRK_DERAT_REF_16G 74
+#define POWER6_PME_PM_LSU_LDF_BOTH 75
+#define POWER6_PME_PM_FPU1_1FLOP 76
+#define POWER6_PME_PM_DATA_FROM_RMEM_CYC 77
+#define POWER6_PME_PM_INST_PTEG_SECONDARY 78
+#define POWER6_PME_PM_L1_ICACHE_MISS 79
+#define POWER6_PME_PM_INST_DISP_LLA 80
+#define POWER6_PME_PM_THRD_BOTH_RUN_CYC 81
+#define POWER6_PME_PM_LSU_ST_CHAINED 82
+#define POWER6_PME_PM_FPU1_FXDIV 83
+#define POWER6_PME_PM_FREQ_UP 84
+#define POWER6_PME_PM_FAB_RETRY_SYS_PUMP 85
+#define POWER6_PME_PM_DATA_FROM_LMEM 86
+#define POWER6_PME_PM_PMC3_OVERFLOW 87
+#define POWER6_PME_PM_LSU0_REJECT_SET_MPRED 88
+#define POWER6_PME_PM_LSU0_REJECT_DERAT_MPRED 89
+#define POWER6_PME_PM_LSU1_REJECT_STQ_FULL 90
+#define POWER6_PME_PM_MRK_BR_MPRED 91
+#define POWER6_PME_PM_L2SA_ST_MISS 92
+#define POWER6_PME_PM_LSU0_REJECT_EXTERN 93
+#define POWER6_PME_PM_MRK_BR_TAKEN 94
+#define POWER6_PME_PM_ISLB_MISS 95
+#define POWER6_PME_PM_CYC 96
+#define POWER6_PME_PM_FPU_FXDIV 97
+#define POWER6_PME_PM_DPU_HELD_LLA_END 98
+#define POWER6_PME_PM_MEM0_DP_CL_WR_LOC 99
+#define POWER6_PME_PM_MRK_LSU_REJECT_ULD 100
+#define POWER6_PME_PM_1PLUS_PPC_CMPL 101
+#define POWER6_PME_PM_PTEG_FROM_DMEM 102
+#define POWER6_PME_PM_DPU_WT_BR_MPRED_COUNT 103
+#define POWER6_PME_PM_GCT_FULL_CYC 104
+#define POWER6_PME_PM_INST_FROM_L25_SHR 105
+#define POWER6_PME_PM_MRK_DERAT_MISS_4K 106
+#define POWER6_PME_PM_DC_PREF_STREAM_ALLOC 107
+#define POWER6_PME_PM_FPU1_FIN 108
+#define POWER6_PME_PM_BR_MPRED_TA 109
+#define POWER6_PME_PM_DPU_HELD_POWER 110
+#define POWER6_PME_PM_RUN_INST_CMPL 111
+#define POWER6_PME_PM_GCT_EMPTY_CYC 112
+#define POWER6_PME_PM_LLA_COUNT 113
+#define POWER6_PME_PM_LSU0_REJECT_NO_SCRATCH 114
+#define POWER6_PME_PM_DPU_WT_IC_MISS 115
+#define POWER6_PME_PM_DATA_FROM_L3MISS 116
+#define POWER6_PME_PM_FPU_FPSCR 117
+#define POWER6_PME_PM_VMX1_INST_ISSUED 118
+#define POWER6_PME_PM_FLUSH 119
+#define POWER6_PME_PM_ST_HIT_L2 120
+#define POWER6_PME_PM_SYNC_CYC 121
+#define POWER6_PME_PM_FAB_SYS_PUMP 122
+#define POWER6_PME_PM_IC_PREF_REQ 123
+#define POWER6_PME_PM_MEM0_DP_RQ_GLOB_LOC 124
+#define POWER6_PME_PM_FPU_ISSUE_0 125
+#define POWER6_PME_PM_THRD_PRIO_2_CYC 126
+#define POWER6_PME_PM_VMX_SIMPLE_ISSUED 127
+#define POWER6_PME_PM_MRK_FPU1_FIN 128
+#define POWER6_PME_PM_DPU_HELD_CW 129
+#define POWER6_PME_PM_L3SA_REF 130
+#define POWER6_PME_PM_STCX 131
+#define POWER6_PME_PM_L2SB_MISS 132
+#define POWER6_PME_PM_LSU0_REJECT 133
+#define POWER6_PME_PM_TB_BIT_TRANS 134
+#define POWER6_PME_PM_THERMAL_MAX 135
+#define POWER6_PME_PM_FPU0_STF 136
+#define POWER6_PME_PM_FPU1_FMA 137
+#define POWER6_PME_PM_LSU1_REJECT_LHS 138
+#define POWER6_PME_PM_DPU_HELD_INT 139
+#define POWER6_PME_PM_THRD_LLA_BOTH_CYC 140
+#define POWER6_PME_PM_DPU_HELD_THERMAL_COUNT 141
+#define POWER6_PME_PM_PMC4_REWIND 142
+#define POWER6_PME_PM_DERAT_REF_16M 143
+#define POWER6_PME_PM_FPU0_FCONV 144
+#define POWER6_PME_PM_L2SA_LD_REQ_DATA 145
+#define POWER6_PME_PM_DATA_FROM_MEM_DP 146
+#define POWER6_PME_PM_MRK_VMX_FLOAT_ISSUED 147
+#define POWER6_PME_PM_MRK_PTEG_FROM_L2MISS 148
+#define POWER6_PME_PM_THRD_PRIO_DIFF_1or2_CYC 149
+#define POWER6_PME_PM_VMX0_STALL 150
+#define POWER6_PME_PM_IC_DEMAND_L2_BHT_REDIRECT 151
+#define POWER6_PME_PM_LSU_DERAT_MISS 152
+#define POWER6_PME_PM_FPU0_SINGLE 153
+#define POWER6_PME_PM_FPU_ISSUE_STEERING 154
+#define POWER6_PME_PM_THRD_PRIO_1_CYC 155
+#define POWER6_PME_PM_VMX_COMPLEX_ISSUED 156
+#define POWER6_PME_PM_FPU_ISSUE_ST_FOLDED 157
+#define POWER6_PME_PM_DFU_FIN 158
+#define POWER6_PME_PM_BR_PRED_CCACHE 159
+#define POWER6_PME_PM_MRK_ST_CMPL_INT 160
+#define POWER6_PME_PM_FAB_MMIO 161
+#define POWER6_PME_PM_MRK_VMX_SIMPLE_ISSUED 162
+#define POWER6_PME_PM_FPU_STF 163
+#define POWER6_PME_PM_MEM1_DP_CL_WR_GLOB 164
+#define POWER6_PME_PM_MRK_DATA_FROM_L3MISS 165
+#define POWER6_PME_PM_GCT_NOSLOT_CYC 166
+#define POWER6_PME_PM_L2_ST_REQ_DATA 167
+#define POWER6_PME_PM_INST_TABLEWALK_COUNT 168
+#define POWER6_PME_PM_PTEG_FROM_L35_SHR 169
+#define POWER6_PME_PM_DPU_HELD_ISYNC 170
+#define POWER6_PME_PM_MRK_DATA_FROM_L25_SHR 171
+#define POWER6_PME_PM_L3SA_HIT 172
+#define POWER6_PME_PM_DERAT_MISS_16G 173
+#define POWER6_PME_PM_DATA_PTEG_2ND_HALF 174
+#define POWER6_PME_PM_L2SA_ST_REQ 175
+#define POWER6_PME_PM_INST_FROM_LMEM 176
+#define POWER6_PME_PM_IC_DEMAND_L2_BR_REDIRECT 177
+#define POWER6_PME_PM_PTEG_FROM_L2 178
+#define POWER6_PME_PM_DATA_PTEG_1ST_HALF 179
+#define POWER6_PME_PM_BR_MPRED_COUNT 180
+#define POWER6_PME_PM_IERAT_MISS_4K 181
+#define POWER6_PME_PM_THRD_BOTH_RUN_COUNT 182
+#define POWER6_PME_PM_LSU_REJECT_ULD 183
+#define POWER6_PME_PM_DATA_FROM_DL2L3_MOD_CYC 184
+#define POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_MOD 185
+#define POWER6_PME_PM_FPU0_FLOP 186
+#define POWER6_PME_PM_FPU0_FEST 187
+#define POWER6_PME_PM_MRK_LSU0_REJECT_LHS 188
+#define POWER6_PME_PM_VMX_RESULT_SAT_1 189
+#define POWER6_PME_PM_NO_ITAG_CYC 190
+#define POWER6_PME_PM_LSU1_REJECT_NO_SCRATCH 191
+#define POWER6_PME_PM_0INST_FETCH 192
+#define POWER6_PME_PM_DPU_WT_BR_MPRED 193
+#define POWER6_PME_PM_L1_PREF 194
+#define POWER6_PME_PM_VMX_FLOAT_MULTICYCLE 195
+#define POWER6_PME_PM_DATA_FROM_L25_SHR_CYC 196
+#define POWER6_PME_PM_DATA_FROM_L3 197
+#define POWER6_PME_PM_PMC2_OVERFLOW 198
+#define POWER6_PME_PM_VMX0_LD_WRBACK 199
+#define POWER6_PME_PM_FPU0_DENORM 200
+#define POWER6_PME_PM_INST_FETCH_CYC 201
+#define POWER6_PME_PM_LSU_LDF 202
+#define POWER6_PME_PM_LSU_REJECT_L2_CORR 203
+#define POWER6_PME_PM_DERAT_REF_64K 204
+#define POWER6_PME_PM_THRD_PRIO_3_CYC 205
+#define POWER6_PME_PM_FPU_FMA 206
+#define POWER6_PME_PM_INST_FROM_L35_MOD 207
+#define POWER6_PME_PM_DFU_CONV 208
+#define POWER6_PME_PM_INST_FROM_L25_MOD 209
+#define POWER6_PME_PM_PTEG_FROM_L35_MOD 210
+#define POWER6_PME_PM_MRK_VMX_ST_ISSUED 211
+#define POWER6_PME_PM_VMX_FLOAT_ISSUED 212
+#define POWER6_PME_PM_LSU0_REJECT_L2_CORR 213
+#define POWER6_PME_PM_THRD_L2MISS 214
+#define POWER6_PME_PM_FPU_FCONV 215
+#define POWER6_PME_PM_FPU_FXMULT 216
+#define POWER6_PME_PM_FPU1_FRSP 217
+#define POWER6_PME_PM_MRK_DERAT_REF_16M 218
+#define POWER6_PME_PM_L2SB_CASTOUT_SHR 219
+#define POWER6_PME_PM_THRD_ONE_RUN_COUNT 220
+#define POWER6_PME_PM_INST_FROM_RMEM 221
+#define POWER6_PME_PM_LSU_BOTH_BUS 222
+#define POWER6_PME_PM_FPU1_FSQRT_FDIV 223
+#define POWER6_PME_PM_L2_LD_REQ_INST 224
+#define POWER6_PME_PM_MRK_PTEG_FROM_L35_SHR 225
+#define POWER6_PME_PM_BR_PRED_CR 226
+#define POWER6_PME_PM_MRK_LSU0_REJECT_ULD 227
+#define POWER6_PME_PM_LSU_REJECT 228
+#define POWER6_PME_PM_LSU_REJECT_LHS_BOTH 229
+#define POWER6_PME_PM_GXO_ADDR_CYC_BUSY 230
+#define POWER6_PME_PM_LSU_SRQ_EMPTY_COUNT 231
+#define POWER6_PME_PM_PTEG_FROM_L3 232
+#define POWER6_PME_PM_VMX0_LD_ISSUED 233
+#define POWER6_PME_PM_FXU_PIPELINED_MULT_DIV 234
+#define POWER6_PME_PM_FPU1_STF 235
+#define POWER6_PME_PM_DFU_ADD 236
+#define POWER6_PME_PM_MEM_DP_CL_WR_GLOB 237
+#define POWER6_PME_PM_MRK_LSU1_REJECT_ULD 238
+#define POWER6_PME_PM_ITLB_REF 239
+#define POWER6_PME_PM_LSU0_REJECT_L2MISS 240
+#define POWER6_PME_PM_DATA_FROM_L35_SHR 241
+#define POWER6_PME_PM_MRK_DATA_FROM_RL2L3_MOD 242
+#define POWER6_PME_PM_FPU0_FPSCR 243
+#define POWER6_PME_PM_DATA_FROM_L2 244
+#define POWER6_PME_PM_DPU_HELD_XER 245
+#define POWER6_PME_PM_FAB_NODE_PUMP 246
+#define POWER6_PME_PM_VMX_RESULT_SAT_0_1 247
+#define POWER6_PME_PM_LD_REF_L1 248
+#define POWER6_PME_PM_TLB_REF 249
+#define POWER6_PME_PM_DC_PREF_OUT_OF_STREAMS 250
+#define POWER6_PME_PM_FLUSH_FPU 251
+#define POWER6_PME_PM_MEM1_DP_CL_WR_LOC 252
+#define POWER6_PME_PM_L2SB_LD_HIT 253
+#define POWER6_PME_PM_FAB_DCLAIM 254
+#define POWER6_PME_PM_MEM_DP_CL_WR_LOC 255
+#define POWER6_PME_PM_BR_MPRED_CR 256
+#define POWER6_PME_PM_LSU_REJECT_EXTERN 257
+#define POWER6_PME_PM_DATA_FROM_RL2L3_MOD 258
+#define POWER6_PME_PM_DPU_HELD_RU_WQ 259
+#define POWER6_PME_PM_LD_MISS_L1 260
+#define POWER6_PME_PM_DC_INV_L2 261
+#define POWER6_PME_PM_MRK_PTEG_FROM_RMEM 262
+#define POWER6_PME_PM_FPU_FIN 263
+#define POWER6_PME_PM_FXU0_FIN 264
+#define POWER6_PME_PM_DPU_HELD_FPQ 265
+#define POWER6_PME_PM_GX_DMA_READ 266
+#define POWER6_PME_PM_LSU1_REJECT_PARTIAL_SECTOR 267
+#define POWER6_PME_PM_0INST_FETCH_COUNT 268
+#define POWER6_PME_PM_PMC5_OVERFLOW 269
+#define POWER6_PME_PM_L2SB_LD_REQ 270
+#define POWER6_PME_PM_THRD_PRIO_DIFF_0_CYC 271
+#define POWER6_PME_PM_DATA_FROM_RMEM 272
+#define POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC 273
+#define POWER6_PME_PM_ST_REF_L1_BOTH 274
+#define POWER6_PME_PM_VMX_PERMUTE_ISSUED 275
+#define POWER6_PME_PM_BR_TAKEN 276
+#define POWER6_PME_PM_FAB_DMA 277
+#define POWER6_PME_PM_GCT_EMPTY_COUNT 278
+#define POWER6_PME_PM_FPU1_SINGLE 279
+#define POWER6_PME_PM_L2SA_CASTOUT_SHR 280
+#define POWER6_PME_PM_L3SB_REF 281
+#define POWER6_PME_PM_FPU0_FRSP 282
+#define POWER6_PME_PM_PMC4_SAVED 283
+#define POWER6_PME_PM_L2SA_DC_INV 284
+#define POWER6_PME_PM_GXI_ADDR_CYC_BUSY 285
+#define POWER6_PME_PM_FPU0_FMA 286
+#define POWER6_PME_PM_SLB_MISS 287
+#define POWER6_PME_PM_MRK_ST_GPS 288
+#define POWER6_PME_PM_DERAT_REF_4K 289
+#define POWER6_PME_PM_L2_CASTOUT_SHR 290
+#define POWER6_PME_PM_DPU_HELD_STCX_CR 291
+#define POWER6_PME_PM_FPU0_ST_FOLDED 292
+#define POWER6_PME_PM_MRK_DATA_FROM_L21 293
+#define POWER6_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC 294
+#define POWER6_PME_PM_DATA_FROM_L35_MOD 295
+#define POWER6_PME_PM_DATA_FROM_DL2L3_SHR 296
+#define POWER6_PME_PM_GXI_DATA_CYC_BUSY 297
+#define POWER6_PME_PM_LSU_REJECT_STEAL 298
+#define POWER6_PME_PM_ST_FIN 299
+#define POWER6_PME_PM_DPU_HELD_CR_LOGICAL 300
+#define POWER6_PME_PM_THRD_SEL_T0 301
+#define POWER6_PME_PM_PTEG_RELOAD_VALID 302
+#define POWER6_PME_PM_L2_PREF_ST 303
+#define POWER6_PME_PM_MRK_STCX_FAIL 304
+#define POWER6_PME_PM_LSU0_REJECT_LHS 305
+#define POWER6_PME_PM_DFU_EXP_EQ 306
+#define POWER6_PME_PM_DPU_HELD_FP_FX_MULT 307
+#define POWER6_PME_PM_L2_LD_MISS_DATA 308
+#define POWER6_PME_PM_DATA_FROM_L35_MOD_CYC 309
+#define POWER6_PME_PM_FLUSH_FXU 310
+#define POWER6_PME_PM_FPU_ISSUE_1 311
+#define POWER6_PME_PM_DATA_FROM_LMEM_CYC 312
+#define POWER6_PME_PM_DPU_HELD_LSU_SOPS 313
+#define POWER6_PME_PM_INST_PTEG_2ND_HALF 314
+#define POWER6_PME_PM_THRESH_TIMEO 315
+#define POWER6_PME_PM_LSU_REJECT_UST_BOTH 316
+#define POWER6_PME_PM_LSU_REJECT_FAST 317
+#define POWER6_PME_PM_DPU_HELD_THRD_PRIO 318
+#define POWER6_PME_PM_L2_PREF_LD 319
+#define POWER6_PME_PM_FPU_FEST 320
+#define POWER6_PME_PM_MRK_DATA_FROM_RMEM 321
+#define POWER6_PME_PM_LD_MISS_L1_CYC 322
+#define POWER6_PME_PM_DERAT_MISS_4K 323
+#define POWER6_PME_PM_DPU_HELD_COMPLETION 324
+#define POWER6_PME_PM_FPU_ISSUE_STALL_ST 325
+#define POWER6_PME_PM_L2SB_DC_INV 326
+#define POWER6_PME_PM_PTEG_FROM_L25_SHR 327
+#define POWER6_PME_PM_PTEG_FROM_DL2L3_MOD 328
+#define POWER6_PME_PM_FAB_CMD_RETRIED 329
+#define POWER6_PME_PM_BR_PRED_LSTACK 330
+#define POWER6_PME_PM_GXO_DATA_CYC_BUSY 331
+#define POWER6_PME_PM_DFU_SUBNORM 332
+#define POWER6_PME_PM_FPU_ISSUE_OOO 333
+#define POWER6_PME_PM_LSU_REJECT_ULD_BOTH 334
+#define POWER6_PME_PM_L2SB_ST_MISS 335
+#define POWER6_PME_PM_DATA_FROM_L25_MOD_CYC 336
+#define POWER6_PME_PM_INST_PTEG_1ST_HALF 337
+#define POWER6_PME_PM_DERAT_MISS_16M 338
+#define POWER6_PME_PM_GX_DMA_WRITE 339
+#define POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_MOD 340
+#define POWER6_PME_PM_MEM1_DP_RQ_GLOB_LOC 341
+#define POWER6_PME_PM_L2SB_LD_REQ_DATA 342
+#define POWER6_PME_PM_L2SA_LD_MISS_INST 343
+#define POWER6_PME_PM_MRK_LSU0_REJECT_L2MISS 344
+#define POWER6_PME_PM_MRK_IFU_FIN 345
+#define POWER6_PME_PM_INST_FROM_L3 346
+#define POWER6_PME_PM_FXU1_FIN 347
+#define POWER6_PME_PM_THRD_PRIO_4_CYC 348
+#define POWER6_PME_PM_MRK_DATA_FROM_L35_MOD 349
+#define POWER6_PME_PM_LSU_REJECT_SET_MPRED 350
+#define POWER6_PME_PM_MRK_DERAT_MISS_16G 351
+#define POWER6_PME_PM_FPU0_FXDIV 352
+#define POWER6_PME_PM_MRK_LSU1_REJECT_UST 353
+#define POWER6_PME_PM_FPU_ISSUE_DIV_SQRT_OVERLAP 354
+#define POWER6_PME_PM_INST_FROM_L35_SHR 355
+#define POWER6_PME_PM_MRK_LSU_REJECT_LHS 356
+#define POWER6_PME_PM_LSU_LMQ_FULL_CYC 357
+#define POWER6_PME_PM_SYNC_COUNT 358
+#define POWER6_PME_PM_MEM0_DP_RQ_LOC_GLOB 359
+#define POWER6_PME_PM_L2SA_CASTOUT_MOD 360
+#define POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT 361
+#define POWER6_PME_PM_PTEG_FROM_MEM_DP 362
+#define POWER6_PME_PM_LSU_REJECT_SLOW 363
+#define POWER6_PME_PM_PTEG_FROM_L25_MOD 364
+#define POWER6_PME_PM_THRD_PRIO_7_CYC 365
+#define POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_SHR 366
+#define POWER6_PME_PM_ST_REQ_L2 367
+#define POWER6_PME_PM_ST_REF_L1 368
+#define POWER6_PME_PM_FPU_ISSUE_STALL_THRD 369
+#define POWER6_PME_PM_RUN_COUNT 370
+#define POWER6_PME_PM_RUN_CYC 371
+#define POWER6_PME_PM_PTEG_FROM_RMEM 372
+#define POWER6_PME_PM_LSU0_LDF 373
+#define POWER6_PME_PM_ST_MISS_L1 374
+#define POWER6_PME_PM_INST_FROM_DL2L3_SHR 375
+#define POWER6_PME_PM_L2SA_IC_INV 376
+#define POWER6_PME_PM_THRD_ONE_RUN_CYC 377
+#define POWER6_PME_PM_L2SB_LD_REQ_INST 378
+#define POWER6_PME_PM_MRK_DATA_FROM_L25_MOD 379
+#define POWER6_PME_PM_DPU_HELD_XTHRD 380
+#define POWER6_PME_PM_L2SB_ST_REQ 381
+#define POWER6_PME_PM_INST_FROM_L21 382
+#define POWER6_PME_PM_INST_FROM_L3MISS 383
+#define POWER6_PME_PM_L3SB_HIT 384
+#define POWER6_PME_PM_EE_OFF_EXT_INT 385
+#define POWER6_PME_PM_INST_FROM_DL2L3_MOD 386
+#define POWER6_PME_PM_PMC6_OVERFLOW 387
+#define POWER6_PME_PM_FPU_FLOP 388
+#define POWER6_PME_PM_FXU_BUSY 389
+#define POWER6_PME_PM_FPU1_FLOP 390
+#define POWER6_PME_PM_IC_RELOAD_SHR 391
+#define POWER6_PME_PM_INST_TABLEWALK_CYC 392
+#define POWER6_PME_PM_DATA_FROM_RL2L3_MOD_CYC 393
+#define POWER6_PME_PM_THRD_PRIO_DIFF_5or6_CYC 394
+#define POWER6_PME_PM_IBUF_FULL_CYC 395
+#define POWER6_PME_PM_L2SA_LD_REQ 396
+#define POWER6_PME_PM_VMX1_LD_WRBACK 397
+#define POWER6_PME_PM_MRK_FPU_FIN 398
+#define POWER6_PME_PM_THRD_PRIO_5_CYC 399
+#define POWER6_PME_PM_DFU_BACK2BACK 400
+#define POWER6_PME_PM_MRK_DATA_FROM_LMEM 401
+#define POWER6_PME_PM_LSU_REJECT_LHS 402
+#define POWER6_PME_PM_DPU_HELD_SPR 403
+#define POWER6_PME_PM_FREQ_DOWN 404
+#define POWER6_PME_PM_DFU_ENC_BCD_DPD 405
+#define POWER6_PME_PM_DPU_HELD_GPR 406
+#define POWER6_PME_PM_LSU0_NCST 407
+#define POWER6_PME_PM_MRK_INST_ISSUED 408
+#define POWER6_PME_PM_INST_FROM_RL2L3_SHR 409
+#define POWER6_PME_PM_FPU_DENORM 410
+#define POWER6_PME_PM_PTEG_FROM_L3MISS 411
+#define POWER6_PME_PM_RUN_PURR 412
+#define POWER6_PME_PM_MRK_VMX0_LD_WRBACK 413
+#define POWER6_PME_PM_L2_MISS 414
+#define POWER6_PME_PM_MRK_DATA_FROM_L3 415
+#define POWER6_PME_PM_MRK_LSU1_REJECT_LHS 416
+#define POWER6_PME_PM_L2SB_LD_MISS_INST 417
+#define POWER6_PME_PM_PTEG_FROM_RL2L3_SHR 418
+#define POWER6_PME_PM_MRK_DERAT_MISS_64K 419
+#define POWER6_PME_PM_LWSYNC 420
+#define POWER6_PME_PM_FPU1_FXMULT 421
+#define POWER6_PME_PM_MEM0_DP_CL_WR_GLOB 422
+#define POWER6_PME_PM_LSU0_REJECT_PARTIAL_SECTOR 423
+#define POWER6_PME_PM_INST_IMC_MATCH_CMPL 424
+#define POWER6_PME_PM_DPU_HELD_THERMAL 425
+#define POWER6_PME_PM_FPU_FRSP 426
+#define POWER6_PME_PM_MRK_INST_FIN 427
+#define POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_SHR 428
+#define POWER6_PME_PM_MRK_DTLB_REF 429
+#define POWER6_PME_PM_MRK_PTEG_FROM_L25_SHR 430
+#define POWER6_PME_PM_DPU_HELD_LSU 431
+#define POWER6_PME_PM_FPU_FSQRT_FDIV 432
+#define POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_COUNT 433
+#define POWER6_PME_PM_DATA_PTEG_SECONDARY 434
+#define POWER6_PME_PM_FPU1_FEST 435
+#define POWER6_PME_PM_L2SA_LD_HIT 436
+#define POWER6_PME_PM_DATA_FROM_MEM_DP_CYC 437
+#define POWER6_PME_PM_BR_MPRED_CCACHE 438
+#define POWER6_PME_PM_DPU_HELD_COUNT 439
+#define POWER6_PME_PM_LSU1_REJECT_SET_MPRED 440
+#define POWER6_PME_PM_FPU_ISSUE_2 441
+#define POWER6_PME_PM_LSU1_REJECT_L2_CORR 442
+#define POWER6_PME_PM_MRK_PTEG_FROM_DMEM 443
+#define POWER6_PME_PM_MEM1_DP_RQ_LOC_GLOB 444
+#define POWER6_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC 445
+#define POWER6_PME_PM_THRD_PRIO_0_CYC 446
+#define POWER6_PME_PM_FXU0_BUSY_FXU1_IDLE 447
+#define POWER6_PME_PM_LSU1_REJECT_DERAT_MPRED 448
+#define POWER6_PME_PM_MRK_VMX1_LD_WRBACK 449
+#define POWER6_PME_PM_DATA_FROM_RL2L3_SHR_CYC 450
+#define POWER6_PME_PM_IERAT_MISS_16M 451
+#define POWER6_PME_PM_MRK_DATA_FROM_MEM_DP 452
+#define POWER6_PME_PM_LARX_L1HIT 453
+#define POWER6_PME_PM_L2_ST_MISS_DATA 454
+#define POWER6_PME_PM_FPU_ST_FOLDED 455
+#define POWER6_PME_PM_MRK_DATA_FROM_L35_SHR 456
+#define POWER6_PME_PM_DPU_HELD_MULT_GPR 457
+#define POWER6_PME_PM_FPU0_1FLOP 458
+#define POWER6_PME_PM_IERAT_MISS_16G 459
+#define POWER6_PME_PM_IC_PREF_WRITE 460
+#define POWER6_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC 461
+#define POWER6_PME_PM_FPU0_FIN 462
+#define POWER6_PME_PM_DATA_FROM_L2_CYC 463
+#define POWER6_PME_PM_DERAT_REF_16G 464
+#define POWER6_PME_PM_BR_PRED 465
+#define POWER6_PME_PM_VMX1_LD_ISSUED 466
+#define POWER6_PME_PM_L2SB_CASTOUT_MOD 467
+#define POWER6_PME_PM_INST_FROM_DMEM 468
+#define POWER6_PME_PM_DATA_FROM_L35_SHR_CYC 469
+#define POWER6_PME_PM_LSU0_NCLD 470
+#define POWER6_PME_PM_FAB_RETRY_NODE_PUMP 471
+#define POWER6_PME_PM_VMX0_INST_ISSUED 472
+#define POWER6_PME_PM_DATA_FROM_L25_MOD 473
+#define POWER6_PME_PM_DPU_HELD_ITLB_ISLB 474
+#define POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 475
+#define POWER6_PME_PM_THRD_CONC_RUN_INST 476
+#define POWER6_PME_PM_MRK_PTEG_FROM_L2 477
+#define POWER6_PME_PM_PURR 478
+#define POWER6_PME_PM_DERAT_MISS_64K 479
+#define POWER6_PME_PM_PMC2_REWIND 480
+#define POWER6_PME_PM_INST_FROM_L2 481
+#define POWER6_PME_PM_INST_DISP 482
+#define POWER6_PME_PM_DATA_FROM_L25_SHR 483
+#define POWER6_PME_PM_L1_DCACHE_RELOAD_VALID 484
+#define POWER6_PME_PM_LSU1_REJECT_UST 485
+#define POWER6_PME_PM_FAB_ADDR_COLLISION 486
+#define POWER6_PME_PM_MRK_FXU_FIN 487
+#define POWER6_PME_PM_LSU0_REJECT_UST 488
+#define POWER6_PME_PM_PMC4_OVERFLOW 489
+#define POWER6_PME_PM_MRK_PTEG_FROM_L3 490
+#define POWER6_PME_PM_INST_FROM_L2MISS 491
+#define POWER6_PME_PM_L2SB_ST_HIT 492
+#define POWER6_PME_PM_DPU_WT_IC_MISS_COUNT 493
+#define POWER6_PME_PM_MRK_DATA_FROM_DL2L3_SHR 494
+#define POWER6_PME_PM_MRK_PTEG_FROM_L35_MOD 495
+#define POWER6_PME_PM_FPU1_FPSCR 496
+#define POWER6_PME_PM_LSU_REJECT_UST 497
+#define POWER6_PME_PM_LSU0_DERAT_MISS 498
+#define POWER6_PME_PM_MRK_PTEG_FROM_MEM_DP 499
+#define POWER6_PME_PM_MRK_DATA_FROM_L2 500
+#define POWER6_PME_PM_FPU0_FSQRT_FDIV 501
+#define POWER6_PME_PM_DPU_HELD_FXU_SOPS 502
+#define POWER6_PME_PM_MRK_FPU0_FIN 503
+#define POWER6_PME_PM_L2SB_LD_MISS_DATA 504
+#define POWER6_PME_PM_LSU_SRQ_EMPTY_CYC 505
+#define POWER6_PME_PM_1PLUS_PPC_DISP 506
+#define POWER6_PME_PM_VMX_ST_ISSUED 507
+#define POWER6_PME_PM_DATA_FROM_L2MISS 508
+#define POWER6_PME_PM_LSU0_REJECT_ULD 509
+#define POWER6_PME_PM_SUSPENDED 510
+#define POWER6_PME_PM_DFU_ADD_SHIFTED_BOTH 511
+#define POWER6_PME_PM_LSU_REJECT_NO_SCRATCH 512
+#define POWER6_PME_PM_STCX_FAIL 513
+#define POWER6_PME_PM_FPU1_DENORM 514
+#define POWER6_PME_PM_GCT_NOSLOT_COUNT 515
+#define POWER6_PME_PM_DATA_FROM_DL2L3_SHR_CYC 516
+#define POWER6_PME_PM_DATA_FROM_L21 517
+#define POWER6_PME_PM_FPU_1FLOP 518
+#define POWER6_PME_PM_LSU1_REJECT 519
+#define POWER6_PME_PM_IC_REQ 520
+#define POWER6_PME_PM_MRK_DFU_FIN 521
+#define POWER6_PME_PM_NOT_LLA_CYC 522
+#define POWER6_PME_PM_INST_FROM_L1 523
+#define POWER6_PME_PM_MRK_VMX_COMPLEX_ISSUED 524
+#define POWER6_PME_PM_BRU_FIN 525
+#define POWER6_PME_PM_LSU1_REJECT_EXTERN 526
+#define POWER6_PME_PM_DATA_FROM_L21_CYC 527
+#define POWER6_PME_PM_GXI_CYC_BUSY 528
+#define POWER6_PME_PM_MRK_LD_MISS_L1 529
+#define POWER6_PME_PM_L1_WRITE_CYC 530
+#define POWER6_PME_PM_LLA_CYC 531
+#define POWER6_PME_PM_MRK_DATA_FROM_L2MISS 532
+#define POWER6_PME_PM_GCT_FULL_COUNT 533
+#define POWER6_PME_PM_MEM_DP_RQ_LOC_GLOB 534
+#define POWER6_PME_PM_DATA_FROM_RL2L3_SHR 535
+#define POWER6_PME_PM_MRK_LSU_REJECT_UST 536
+#define POWER6_PME_PM_MRK_VMX_PERMUTE_ISSUED 537
+#define POWER6_PME_PM_MRK_PTEG_FROM_L21 538
+#define POWER6_PME_PM_THRD_GRP_CMPL_BOTH_CYC 539
+#define POWER6_PME_PM_BR_MPRED 540
+#define POWER6_PME_PM_LD_REQ_L2 541
+#define POWER6_PME_PM_FLUSH_ASYNC 542
+#define POWER6_PME_PM_HV_CYC 543
+#define POWER6_PME_PM_LSU1_DERAT_MISS 544
+#define POWER6_PME_PM_DPU_HELD_SMT 545
+#define POWER6_PME_PM_MRK_LSU_FIN 546
+#define POWER6_PME_PM_MRK_DATA_FROM_RL2L3_SHR 547
+#define POWER6_PME_PM_LSU0_REJECT_STQ_FULL 548
+#define POWER6_PME_PM_MRK_DERAT_REF_4K 549
+#define POWER6_PME_PM_FPU_ISSUE_STALL_FPR 550
+#define POWER6_PME_PM_IFU_FIN 551
+#define POWER6_PME_PM_GXO_CYC_BUSY 552
+
+
+static const int power6_event_ids[][POWER6_NUM_EVENT_COUNTERS] = {
+ [ POWER6_PME_PM_LSU_REJECT_STQ_FULL ] = { 243, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_FXU_MULTI ] = { 37, 45, 36, 44, -1, -1 },
+ [ POWER6_PME_PM_VMX1_STALL ] = { 328, 335, 322, 320, -1, -1 },
+ [ POWER6_PME_PM_PMC2_SAVED ] = { 291, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_L2SB_IC_INV ] = { 174, 183, 174, 180, -1, -1 },
+ [ POWER6_PME_PM_IERAT_MISS_64K ] = { -1, -1, 344, -1, -1, -1 },
+ [ POWER6_PME_PM_THRD_PRIO_DIFF_3or4_CYC ] = { -1, -1, 310, -1, -1, -1 },
+ [ POWER6_PME_PM_LD_REF_L1_BOTH ] = { 202, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_FPU1_FCONV ] = { 88, 97, 86, 94, -1, -1 },
+ [ POWER6_PME_PM_IBUF_FULL_COUNT ] = { 338, 345, 332, 330, -1, -1 },
+ [ POWER6_PME_PM_MRK_LSU_DERAT_MISS ] = { -1, -1, -1, 271, -1, -1 },
+ [ POWER6_PME_PM_MRK_ST_CMPL ] = { 282, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_L2_CASTOUT_MOD ] = { 185, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_FPU1_ST_FOLDED ] = { 100, 109, 98, 106, -1, -1 },
+ [ POWER6_PME_PM_MRK_INST_TIMEO ] = { -1, -1, -1, 263, -1, -1 },
+ [ POWER6_PME_PM_DPU_WT ] = { -1, -1, 54, -1, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_RESTART ] = { 47, 56, 46, 54, -1, -1 },
+ [ POWER6_PME_PM_IERAT_MISS ] = { 137, 146, 136, 143, -1, -1 },
+ [ POWER6_PME_PM_FPU_SINGLE ] = { -1, -1, -1, 122, -1, -1 },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_LMEM ] = { -1, -1, -1, 278, -1, -1 },
+ [ POWER6_PME_PM_HV_COUNT ] = { -1, 351, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_L2SA_ST_HIT ] = { 168, 177, 168, 174, -1, -1 },
+ [ POWER6_PME_PM_L2_LD_MISS_INST ] = { -1, 196, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_EXT_INT ] = { -1, 67, 57, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU1_LDF ] = { 221, 230, 216, 221, -1, -1 },
+ [ POWER6_PME_PM_FAB_CMD_ISSUED ] = { 59, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_PTEG_FROM_L21 ] = { -1, 305, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_L2SA_MISS ] = { 167, 176, 167, 173, -1, -1 },
+ [ POWER6_PME_PM_PTEG_FROM_RL2L3_MOD ] = { 299, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DPU_WT_COUNT ] = { -1, -1, 340, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_L25_MOD ] = { -1, -1, 272, -1, -1, -1 },
+ [ POWER6_PME_PM_LD_HIT_L2 ] = { -1, 209, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_PTEG_FROM_DL2L3_SHR ] = { -1, -1, 290, -1, -1, -1 },
+ [ POWER6_PME_PM_MEM_DP_RQ_GLOB_LOC ] = { 257, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_L3SA_MISS ] = { 192, 202, 190, 195, -1, -1 },
+ [ POWER6_PME_PM_NO_ITAG_COUNT ] = { 340, 347, 334, 332, -1, -1 },
+ [ POWER6_PME_PM_DSLB_MISS ] = { 56, 65, 55, 63, -1, -1 },
+ [ POWER6_PME_PM_LSU_FLUSH_ALIGN ] = { 235, 244, 229, 235, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_FPU_CR ] = { 35, 43, 34, 42, -1, -1 },
+ [ POWER6_PME_PM_PTEG_FROM_L2MISS ] = { 296, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_DATA_FROM_DMEM ] = { -1, 269, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_PTEG_FROM_LMEM ] = { -1, -1, -1, 291, -1, -1 },
+ [ POWER6_PME_PM_MRK_DERAT_REF_64K ] = { 353, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_L2SA_LD_REQ_INST ] = { 166, 175, 166, 172, -1, -1 },
+ [ POWER6_PME_PM_MRK_DERAT_MISS_16M ] = { -1, -1, 346, -1, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_DL2L3_MOD ] = { -1, -1, -1, 13, -1, -1 },
+ [ POWER6_PME_PM_FPU0_FXMULT ] = { 82, 91, 80, 88, -1, -1 },
+ [ POWER6_PME_PM_L3SB_MISS ] = { 195, 205, 193, 198, -1, -1 },
+ [ POWER6_PME_PM_STCX_CANCEL ] = { 305, 311, 297, 296, -1, -1 },
+ [ POWER6_PME_PM_L2SA_LD_MISS_DATA ] = { 162, 171, 162, 168, -1, -1 },
+ [ POWER6_PME_PM_IC_INV_L2 ] = { -1, 141, 131, -1, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD ] = { -1, 38, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_PMC1_OVERFLOW ] = { -1, 303, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_THRD_PRIO_6_CYC ] = { -1, 323, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_L3MISS ] = { -1, -1, 274, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_LSU0_REJECT_UST ] = { 272, 284, 266, 267, -1, -1 },
+ [ POWER6_PME_PM_MRK_INST_DISP ] = { 267, 279, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_LARX ] = { 197, 207, 195, 200, -1, -1 },
+ [ POWER6_PME_PM_INST_CMPL ] = { 139, 148, 138, 145, -1, -1 },
+ [ POWER6_PME_PM_FXU_IDLE ] = { 117, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_DATA_FROM_DL2L3_MOD ] = { -1, -1, -1, 256, -1, -1 },
+ [ POWER6_PME_PM_L2_LD_REQ_DATA ] = { 186, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU_DERAT_MISS_CYC ] = { 234, -1, -1, 234, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_POWER_COUNT ] = { -1, 356, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_INST_FROM_RL2L3_MOD ] = { 146, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_DMEM_CYC ] = { -1, 14, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_DMEM ] = { -1, 13, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU_REJECT_PARTIAL_SECTOR ] = { 241, -1, -1, 242, -1, -1 },
+ [ POWER6_PME_PM_LSU_REJECT_DERAT_MPRED ] = { -1, 249, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU1_REJECT_ULD ] = { 231, 240, 226, 231, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_L3_CYC ] = { -1, 21, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { -1, -1, -1, 124, -1, -1 },
+ [ POWER6_PME_PM_INST_FROM_MEM_DP ] = { 145, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU_FLUSH_DSI ] = { 236, 245, 230, 236, -1, -1 },
+ [ POWER6_PME_PM_MRK_DERAT_REF_16G ] = { -1, -1, -1, 345, -1, -1 },
+ [ POWER6_PME_PM_LSU_LDF_BOTH ] = { 237, -1, 232, -1, -1, -1 },
+ [ POWER6_PME_PM_FPU1_1FLOP ] = { 86, 95, 84, 92, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_RMEM_CYC ] = { -1, -1, -1, 23, -1, -1 },
+ [ POWER6_PME_PM_INST_PTEG_SECONDARY ] = { 150, 159, 150, 156, -1, -1 },
+ [ POWER6_PME_PM_L1_ICACHE_MISS ] = { 154, 163, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_INST_DISP_LLA ] = { 140, 150, 140, 146, -1, -1 },
+ [ POWER6_PME_PM_THRD_BOTH_RUN_CYC ] = { -1, -1, -1, 304, -1, -1 },
+ [ POWER6_PME_PM_LSU_ST_CHAINED ] = { 246, 257, 240, 245, -1, -1 },
+ [ POWER6_PME_PM_FPU1_FXDIV ] = { 96, 105, 94, 102, -1, -1 },
+ [ POWER6_PME_PM_FREQ_UP ] = { -1, -1, -1, 123, -1, -1 },
+ [ POWER6_PME_PM_FAB_RETRY_SYS_PUMP ] = { 65, 75, 64, 71, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_LMEM ] = { -1, -1, -1, 20, -1, -1 },
+ [ POWER6_PME_PM_PMC3_OVERFLOW ] = { -1, -1, -1, 288, -1, -1 },
+ [ POWER6_PME_PM_LSU0_REJECT_SET_MPRED ] = { 216, 225, 211, 216, -1, -1 },
+ [ POWER6_PME_PM_LSU0_REJECT_DERAT_MPRED ] = { 209, 218, 204, 209, -1, -1 },
+ [ POWER6_PME_PM_LSU1_REJECT_STQ_FULL ] = { 230, 239, 225, 230, -1, -1 },
+ [ POWER6_PME_PM_MRK_BR_MPRED ] = { -1, -1, 251, -1, -1, -1 },
+ [ POWER6_PME_PM_L2SA_ST_MISS ] = { 169, 178, 169, 175, -1, -1 },
+ [ POWER6_PME_PM_LSU0_REJECT_EXTERN ] = { 210, 219, 205, 210, -1, -1 },
+ [ POWER6_PME_PM_MRK_BR_TAKEN ] = { 258, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_ISLB_MISS ] = { 152, 161, 152, 158, -1, -1 },
+ [ POWER6_PME_PM_CYC ] = { 12, 11, 10, 12, -1, -1 },
+ [ POWER6_PME_PM_FPU_FXDIV ] = { 105, -1, -1, 110, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_LLA_END ] = { 43, 51, 42, 50, -1, -1 },
+ [ POWER6_PME_PM_MEM0_DP_CL_WR_LOC ] = { 249, 260, 243, 248, -1, -1 },
+ [ POWER6_PME_PM_MRK_LSU_REJECT_ULD ] = { 276, -1, -1, 274, -1, -1 },
+ [ POWER6_PME_PM_1PLUS_PPC_CMPL ] = { 1, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_PTEG_FROM_DMEM ] = { -1, 304, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DPU_WT_BR_MPRED_COUNT ] = { -1, -1, -1, 340, -1, -1 },
+ [ POWER6_PME_PM_GCT_FULL_CYC ] = { 120, 128, 119, 127, -1, -1 },
+ [ POWER6_PME_PM_INST_FROM_L25_SHR ] = { -1, -1, -1, 150, -1, -1 },
+ [ POWER6_PME_PM_MRK_DERAT_MISS_4K ] = { -1, 364, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DC_PREF_STREAM_ALLOC ] = { 22, 29, 21, 29, -1, -1 },
+ [ POWER6_PME_PM_FPU1_FIN ] = { 90, 99, 88, 96, -1, -1 },
+ [ POWER6_PME_PM_BR_MPRED_TA ] = { 7, 5, 5, 7, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_POWER ] = { -1, 55, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_RUN_INST_CMPL ] = { -1, -1, -1, -1, 0, -1 },
+ [ POWER6_PME_PM_GCT_EMPTY_CYC ] = { 119, 127, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_LLA_COUNT ] = { 347, 354, 339, 339, -1, -1 },
+ [ POWER6_PME_PM_LSU0_REJECT_NO_SCRATCH ] = { 214, 223, 209, 214, -1, -1 },
+ [ POWER6_PME_PM_DPU_WT_IC_MISS ] = { -1, 64, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_L3MISS ] = { -1, -1, 15, 19, -1, -1 },
+ [ POWER6_PME_PM_FPU_FPSCR ] = { -1, 112, 100, -1, -1, -1 },
+ [ POWER6_PME_PM_VMX1_INST_ISSUED ] = { 325, 332, 319, 317, -1, -1 },
+ [ POWER6_PME_PM_FLUSH ] = { 67, -1, -1, 73, -1, -1 },
+ [ POWER6_PME_PM_ST_HIT_L2 ] = { 308, -1, -1, 298, -1, -1 },
+ [ POWER6_PME_PM_SYNC_CYC ] = { 312, 319, 303, 303, -1, -1 },
+ [ POWER6_PME_PM_FAB_SYS_PUMP ] = { 66, 76, 65, 72, -1, -1 },
+ [ POWER6_PME_PM_IC_PREF_REQ ] = { 133, 142, 132, 139, -1, -1 },
+ [ POWER6_PME_PM_MEM0_DP_RQ_GLOB_LOC ] = { 250, 261, 244, 249, -1, -1 },
+ [ POWER6_PME_PM_FPU_ISSUE_0 ] = { 107, 115, 103, 112, -1, -1 },
+ [ POWER6_PME_PM_THRD_PRIO_2_CYC ] = { -1, -1, 308, -1, -1, -1 },
+ [ POWER6_PME_PM_VMX_SIMPLE_ISSUED ] = { 335, 342, 329, 327, -1, -1 },
+ [ POWER6_PME_PM_MRK_FPU1_FIN ] = { 266, 275, 260, 261, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_CW ] = { 33, 41, 32, 40, -1, -1 },
+ [ POWER6_PME_PM_L3SA_REF ] = { 193, 203, 191, 196, -1, -1 },
+ [ POWER6_PME_PM_STCX ] = { 304, 310, 296, 295, -1, -1 },
+ [ POWER6_PME_PM_L2SB_MISS ] = { 181, 190, 181, 187, -1, -1 },
+ [ POWER6_PME_PM_LSU0_REJECT ] = { 208, 217, 203, 208, -1, -1 },
+ [ POWER6_PME_PM_TB_BIT_TRANS ] = { 313, -1, 304, -1, -1, -1 },
+ [ POWER6_PME_PM_THERMAL_MAX ] = { -1, -1, 305, -1, -1, -1 },
+ [ POWER6_PME_PM_FPU0_STF ] = { 84, 93, 82, 90, -1, -1 },
+ [ POWER6_PME_PM_FPU1_FMA ] = { 92, 101, 90, 98, -1, -1 },
+ [ POWER6_PME_PM_LSU1_REJECT_LHS ] = { 226, 235, 221, 226, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_INT ] = { 40, 48, 39, 47, -1, -1 },
+ [ POWER6_PME_PM_THRD_LLA_BOTH_CYC ] = { -1, -1, -1, 306, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_THERMAL_COUNT ] = { 348, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_PMC4_REWIND ] = { 293, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DERAT_REF_16M ] = { -1, -1, 342, -1, -1, -1 },
+ [ POWER6_PME_PM_FPU0_FCONV ] = { 73, 82, 71, 79, -1, -1 },
+ [ POWER6_PME_PM_L2SA_LD_REQ_DATA ] = { 165, 174, 165, 171, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_MEM_DP ] = { 15, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_VMX_FLOAT_ISSUED ] = { 286, 298, 281, 283, -1, -1 },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_L2MISS ] = { -1, -1, -1, 277, -1, -1 },
+ [ POWER6_PME_PM_THRD_PRIO_DIFF_1or2_CYC ] = { -1, 324, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_VMX0_STALL ] = { 324, 331, 318, 316, -1, -1 },
+ [ POWER6_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { 131, 139, 129, 137, -1, -1 },
+ [ POWER6_PME_PM_LSU_DERAT_MISS ] = { -1, 243, -1, 335, -1, -1 },
+ [ POWER6_PME_PM_FPU0_SINGLE ] = { 83, 92, 81, 89, -1, -1 },
+ [ POWER6_PME_PM_FPU_ISSUE_STEERING ] = { 115, 123, 111, 120, -1, -1 },
+ [ POWER6_PME_PM_THRD_PRIO_1_CYC ] = { -1, 322, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_VMX_COMPLEX_ISSUED ] = { 329, 336, 323, 321, -1, -1 },
+ [ POWER6_PME_PM_FPU_ISSUE_ST_FOLDED ] = { 116, 124, 112, 121, -1, -1 },
+ [ POWER6_PME_PM_DFU_FIN ] = { 29, 36, 28, 36, -1, -1 },
+ [ POWER6_PME_PM_BR_PRED_CCACHE ] = { 9, 7, 7, 9, -1, -1 },
+ [ POWER6_PME_PM_MRK_ST_CMPL_INT ] = { -1, -1, 277, -1, -1, -1 },
+ [ POWER6_PME_PM_FAB_MMIO ] = { 62, 72, 61, 68, -1, -1 },
+ [ POWER6_PME_PM_MRK_VMX_SIMPLE_ISSUED ] = { 288, 300, 283, 285, -1, -1 },
+ [ POWER6_PME_PM_FPU_STF ] = { -1, -1, 113, -1, -1, -1 },
+ [ POWER6_PME_PM_MEM1_DP_CL_WR_GLOB ] = { 252, 263, 246, 251, -1, -1 },
+ [ POWER6_PME_PM_MRK_DATA_FROM_L3MISS ] = { -1, -1, 255, -1, -1, -1 },
+ [ POWER6_PME_PM_GCT_NOSLOT_CYC ] = { 121, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_L2_ST_REQ_DATA ] = { -1, 200, 188, -1, -1, -1 },
+ [ POWER6_PME_PM_INST_TABLEWALK_COUNT ] = { 341, 348, 335, 333, -1, -1 },
+ [ POWER6_PME_PM_PTEG_FROM_L35_SHR ] = { -1, 306, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_ISYNC ] = { 41, 49, 40, 48, -1, -1 },
+ [ POWER6_PME_PM_MRK_DATA_FROM_L25_SHR ] = { -1, -1, -1, 257, -1, -1 },
+ [ POWER6_PME_PM_L3SA_HIT ] = { 191, 201, 189, 194, -1, -1 },
+ [ POWER6_PME_PM_DERAT_MISS_16G ] = { -1, -1, -1, 343, -1, -1 },
+ [ POWER6_PME_PM_DATA_PTEG_2ND_HALF ] = { 18, 26, 18, 25, -1, -1 },
+ [ POWER6_PME_PM_L2SA_ST_REQ ] = { 170, 179, 170, 176, -1, -1 },
+ [ POWER6_PME_PM_INST_FROM_LMEM ] = { -1, -1, -1, 152, -1, -1 },
+ [ POWER6_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { 132, 140, 130, 138, -1, -1 },
+ [ POWER6_PME_PM_PTEG_FROM_L2 ] = { 295, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DATA_PTEG_1ST_HALF ] = { 17, 25, 17, 24, -1, -1 },
+ [ POWER6_PME_PM_BR_MPRED_COUNT ] = { 5, 3, 3, 5, -1, -1 },
+ [ POWER6_PME_PM_IERAT_MISS_4K ] = { -1, -1, -1, 344, -1, -1 },
+ [ POWER6_PME_PM_THRD_BOTH_RUN_COUNT ] = { -1, -1, -1, 336, -1, -1 },
+ [ POWER6_PME_PM_LSU_REJECT_ULD ] = { 244, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_DL2L3_MOD_CYC ] = { -1, -1, -1, 14, -1, -1 },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_MOD ] = { 280, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_FPU0_FLOP ] = { 76, 85, 74, 82, -1, -1 },
+ [ POWER6_PME_PM_FPU0_FEST ] = { 74, 83, 72, 80, -1, -1 },
+ [ POWER6_PME_PM_MRK_LSU0_REJECT_LHS ] = { 270, 282, 264, 265, -1, -1 },
+ [ POWER6_PME_PM_VMX_RESULT_SAT_1 ] = { 334, 341, 328, 326, -1, -1 },
+ [ POWER6_PME_PM_NO_ITAG_CYC ] = { 290, 302, 285, 287, -1, -1 },
+ [ POWER6_PME_PM_LSU1_REJECT_NO_SCRATCH ] = { 227, 236, 222, 227, -1, -1 },
+ [ POWER6_PME_PM_0INST_FETCH ] = { 0, 0, 0, 0, -1, -1 },
+ [ POWER6_PME_PM_DPU_WT_BR_MPRED ] = { -1, -1, -1, 62, -1, -1 },
+ [ POWER6_PME_PM_L1_PREF ] = { 155, 164, 155, 161, -1, -1 },
+ [ POWER6_PME_PM_VMX_FLOAT_MULTICYCLE ] = { 331, 338, 325, 323, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_L25_SHR_CYC ] = { -1, 16, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_L3 ] = { -1, -1, 14, -1, -1, -1 },
+ [ POWER6_PME_PM_PMC2_OVERFLOW ] = { -1, -1, 286, -1, -1, -1 },
+ [ POWER6_PME_PM_VMX0_LD_WRBACK ] = { 323, 330, 317, 315, -1, -1 },
+ [ POWER6_PME_PM_FPU0_DENORM ] = { 72, 81, 70, 78, -1, -1 },
+ [ POWER6_PME_PM_INST_FETCH_CYC ] = { 141, 151, 141, 147, -1, -1 },
+ [ POWER6_PME_PM_LSU_LDF ] = { -1, 246, 231, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU_REJECT_L2_CORR ] = { 239, -1, -1, 239, -1, -1 },
+ [ POWER6_PME_PM_DERAT_REF_64K ] = { -1, 360, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_THRD_PRIO_3_CYC ] = { -1, -1, -1, 307, -1, -1 },
+ [ POWER6_PME_PM_FPU_FMA ] = { -1, 111, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_INST_FROM_L35_MOD ] = { 144, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DFU_CONV ] = { 26, 33, 25, 33, -1, -1 },
+ [ POWER6_PME_PM_INST_FROM_L25_MOD ] = { -1, -1, 144, -1, -1, -1 },
+ [ POWER6_PME_PM_PTEG_FROM_L35_MOD ] = { 297, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_VMX_ST_ISSUED ] = { 289, 301, 284, 286, -1, -1 },
+ [ POWER6_PME_PM_VMX_FLOAT_ISSUED ] = { 330, 337, 324, 322, -1, -1 },
+ [ POWER6_PME_PM_LSU0_REJECT_L2_CORR ] = { 212, 221, 207, 212, -1, -1 },
+ [ POWER6_PME_PM_THRD_L2MISS ] = { 314, 321, 307, 305, -1, -1 },
+ [ POWER6_PME_PM_FPU_FCONV ] = { 102, -1, -1, 107, -1, -1 },
+ [ POWER6_PME_PM_FPU_FXMULT ] = { 106, -1, -1, 111, -1, -1 },
+ [ POWER6_PME_PM_FPU1_FRSP ] = { 94, 103, 92, 100, -1, -1 },
+ [ POWER6_PME_PM_MRK_DERAT_REF_16M ] = { -1, -1, 345, -1, -1, -1 },
+ [ POWER6_PME_PM_L2SB_CASTOUT_SHR ] = { 172, 181, 172, 178, -1, -1 },
+ [ POWER6_PME_PM_THRD_ONE_RUN_COUNT ] = { 344, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_INST_FROM_RMEM ] = { -1, -1, 147, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU_BOTH_BUS ] = { 233, 242, 228, 233, -1, -1 },
+ [ POWER6_PME_PM_FPU1_FSQRT_FDIV ] = { 95, 104, 93, 101, -1, -1 },
+ [ POWER6_PME_PM_L2_LD_REQ_INST ] = { 187, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_L35_SHR ] = { -1, 291, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_BR_PRED_CR ] = { 10, 8, 8, 10, -1, -1 },
+ [ POWER6_PME_PM_MRK_LSU0_REJECT_ULD ] = { 271, 283, 265, 266, -1, -1 },
+ [ POWER6_PME_PM_LSU_REJECT ] = { -1, -1, -1, 238, -1, -1 },
+ [ POWER6_PME_PM_LSU_REJECT_LHS_BOTH ] = { -1, 250, -1, 241, -1, -1 },
+ [ POWER6_PME_PM_GXO_ADDR_CYC_BUSY ] = { 125, 132, 123, 131, -1, -1 },
+ [ POWER6_PME_PM_LSU_SRQ_EMPTY_COUNT ] = { -1, -1, -1, 341, -1, -1 },
+ [ POWER6_PME_PM_PTEG_FROM_L3 ] = { -1, -1, 292, -1, -1, -1 },
+ [ POWER6_PME_PM_VMX0_LD_ISSUED ] = { 322, 329, 316, 314, -1, -1 },
+ [ POWER6_PME_PM_FXU_PIPELINED_MULT_DIV ] = { 118, 126, 118, 126, -1, -1 },
+ [ POWER6_PME_PM_FPU1_STF ] = { 99, 108, 97, 105, -1, -1 },
+ [ POWER6_PME_PM_DFU_ADD ] = { 23, 30, 22, 30, -1, -1 },
+ [ POWER6_PME_PM_MEM_DP_CL_WR_GLOB ] = { -1, 267, 250, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_LSU1_REJECT_ULD ] = { 274, 286, 268, 269, -1, -1 },
+ [ POWER6_PME_PM_ITLB_REF ] = { 153, 162, 153, 159, -1, -1 },
+ [ POWER6_PME_PM_LSU0_REJECT_L2MISS ] = { 211, 220, 206, 211, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_L35_SHR ] = { -1, 19, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_DATA_FROM_RL2L3_MOD ] = { 263, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_FPU0_FPSCR ] = { 78, 87, 76, 84, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_L2 ] = { 13, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_XER ] = { 54, 62, 52, 60, -1, -1 },
+ [ POWER6_PME_PM_FAB_NODE_PUMP ] = { 63, 73, 62, 69, -1, -1 },
+ [ POWER6_PME_PM_VMX_RESULT_SAT_0_1 ] = { 333, 340, 327, 325, -1, -1 },
+ [ POWER6_PME_PM_LD_REF_L1 ] = { 201, 212, 198, 203, -1, -1 },
+ [ POWER6_PME_PM_TLB_REF ] = { 320, 327, 314, 312, -1, -1 },
+ [ POWER6_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { 21, 28, 20, 28, -1, -1 },
+ [ POWER6_PME_PM_FLUSH_FPU ] = { 69, 78, 67, 75, -1, -1 },
+ [ POWER6_PME_PM_MEM1_DP_CL_WR_LOC ] = { 253, 264, 247, 252, -1, -1 },
+ [ POWER6_PME_PM_L2SB_LD_HIT ] = { 175, 184, 175, 181, -1, -1 },
+ [ POWER6_PME_PM_FAB_DCLAIM ] = { 60, 70, 59, 66, -1, -1 },
+ [ POWER6_PME_PM_MEM_DP_CL_WR_LOC ] = { 256, -1, -1, 255, -1, -1 },
+ [ POWER6_PME_PM_BR_MPRED_CR ] = { 6, 4, 4, 6, -1, -1 },
+ [ POWER6_PME_PM_LSU_REJECT_EXTERN ] = { -1, -1, 235, -1, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_RL2L3_MOD ] = { 16, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_RU_WQ ] = { 48, 57, 47, 55, -1, -1 },
+ [ POWER6_PME_PM_LD_MISS_L1 ] = { 199, 210, 197, 202, -1, -1 },
+ [ POWER6_PME_PM_DC_INV_L2 ] = { 20, -1, -1, 27, -1, -1 },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_RMEM ] = { -1, -1, 275, -1, -1, -1 },
+ [ POWER6_PME_PM_FPU_FIN ] = { 103, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_FXU0_FIN ] = { -1, -1, 117, -1, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_FPQ ] = { 34, 42, 33, 41, -1, -1 },
+ [ POWER6_PME_PM_GX_DMA_READ ] = { 128, 135, 126, 134, -1, -1 },
+ [ POWER6_PME_PM_LSU1_REJECT_PARTIAL_SECTOR ] = { 228, 237, 223, 228, -1, -1 },
+ [ POWER6_PME_PM_0INST_FETCH_COUNT ] = { 337, 344, 331, 329, -1, -1 },
+ [ POWER6_PME_PM_PMC5_OVERFLOW ] = { 294, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_L2SB_LD_REQ ] = { 178, 187, 178, 184, -1, -1 },
+ [ POWER6_PME_PM_THRD_PRIO_DIFF_0_CYC ] = { 318, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_RMEM ] = { -1, -1, 16, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC ] = { -1, -1, 234, -1, -1, -1 },
+ [ POWER6_PME_PM_ST_REF_L1_BOTH ] = { -1, 316, -1, 301, -1, -1 },
+ [ POWER6_PME_PM_VMX_PERMUTE_ISSUED ] = { 332, 339, 326, 324, -1, -1 },
+ [ POWER6_PME_PM_BR_TAKEN ] = { -1, 10, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_FAB_DMA ] = { 61, 71, 60, 67, -1, -1 },
+ [ POWER6_PME_PM_GCT_EMPTY_COUNT ] = { -1, 358, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_FPU1_SINGLE ] = { 98, 107, 96, 104, -1, -1 },
+ [ POWER6_PME_PM_L2SA_CASTOUT_SHR ] = { 158, 167, 158, 164, -1, -1 },
+ [ POWER6_PME_PM_L3SB_REF ] = { 196, 206, 194, 199, -1, -1 },
+ [ POWER6_PME_PM_FPU0_FRSP ] = { 79, 88, 77, 85, -1, -1 },
+ [ POWER6_PME_PM_PMC4_SAVED ] = { -1, -1, 288, -1, -1, -1 },
+ [ POWER6_PME_PM_L2SA_DC_INV ] = { 159, 168, 159, 165, -1, -1 },
+ [ POWER6_PME_PM_GXI_ADDR_CYC_BUSY ] = { 122, 129, 120, 128, -1, -1 },
+ [ POWER6_PME_PM_FPU0_FMA ] = { 77, 86, 75, 83, -1, -1 },
+ [ POWER6_PME_PM_SLB_MISS ] = { 303, -1, -1, 294, -1, -1 },
+ [ POWER6_PME_PM_MRK_ST_GPS ] = { -1, 294, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DERAT_REF_4K ] = { 350, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_L2_CASTOUT_SHR ] = { -1, 194, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_STCX_CR ] = { 51, 60, 50, 58, -1, -1 },
+ [ POWER6_PME_PM_FPU0_ST_FOLDED ] = { 85, 94, 83, 91, -1, -1 },
+ [ POWER6_PME_PM_MRK_DATA_FROM_L21 ] = { -1, 270, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC ] = { -1, -1, 311, -1, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_L35_MOD ] = { 14, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_DL2L3_SHR ] = { -1, -1, 11, -1, -1, -1 },
+ [ POWER6_PME_PM_GXI_DATA_CYC_BUSY ] = { 124, 131, 122, 130, -1, -1 },
+ [ POWER6_PME_PM_LSU_REJECT_STEAL ] = { 242, 254, 239, 243, -1, -1 },
+ [ POWER6_PME_PM_ST_FIN ] = { 307, 313, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_CR_LOGICAL ] = { 32, 40, 31, 39, -1, -1 },
+ [ POWER6_PME_PM_THRD_SEL_T0 ] = { 319, 326, 312, 311, -1, -1 },
+ [ POWER6_PME_PM_PTEG_RELOAD_VALID ] = { 300, 308, 295, 292, -1, -1 },
+ [ POWER6_PME_PM_L2_PREF_ST ] = { 189, 199, 187, 192, -1, -1 },
+ [ POWER6_PME_PM_MRK_STCX_FAIL ] = { 281, 293, 276, 279, -1, -1 },
+ [ POWER6_PME_PM_LSU0_REJECT_LHS ] = { 213, 222, 208, 213, -1, -1 },
+ [ POWER6_PME_PM_DFU_EXP_EQ ] = { 28, 35, 27, 35, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_FP_FX_MULT ] = { 36, 44, 35, 43, -1, -1 },
+ [ POWER6_PME_PM_L2_LD_MISS_DATA ] = { -1, 195, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_L35_MOD_CYC ] = { -1, -1, -1, 18, -1, -1 },
+ [ POWER6_PME_PM_FLUSH_FXU ] = { 70, 79, 68, 76, -1, -1 },
+ [ POWER6_PME_PM_FPU_ISSUE_1 ] = { 108, 116, 104, 113, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_LMEM_CYC ] = { -1, 22, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_LSU_SOPS ] = { 45, 53, 44, 52, -1, -1 },
+ [ POWER6_PME_PM_INST_PTEG_2ND_HALF ] = { 149, 158, 149, 155, -1, -1 },
+ [ POWER6_PME_PM_THRESH_TIMEO ] = { -1, -1, 313, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU_REJECT_UST_BOTH ] = { 245, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU_REJECT_FAST ] = { -1, -1, 236, -1, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_THRD_PRIO ] = { 53, 61, 51, 59, -1, -1 },
+ [ POWER6_PME_PM_L2_PREF_LD ] = { 188, 198, 186, 191, -1, -1 },
+ [ POWER6_PME_PM_FPU_FEST ] = { -1, -1, -1, 108, -1, -1 },
+ [ POWER6_PME_PM_MRK_DATA_FROM_RMEM ] = { -1, -1, 256, -1, -1, -1 },
+ [ POWER6_PME_PM_LD_MISS_L1_CYC ] = { 200, 211, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DERAT_MISS_4K ] = { 351, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_COMPLETION ] = { 31, 39, 30, 38, -1, -1 },
+ [ POWER6_PME_PM_FPU_ISSUE_STALL_ST ] = { 113, 121, 109, 118, -1, -1 },
+ [ POWER6_PME_PM_L2SB_DC_INV ] = { 173, 182, 173, 179, -1, -1 },
+ [ POWER6_PME_PM_PTEG_FROM_L25_SHR ] = { -1, -1, -1, 290, -1, -1 },
+ [ POWER6_PME_PM_PTEG_FROM_DL2L3_MOD ] = { -1, -1, -1, 289, -1, -1 },
+ [ POWER6_PME_PM_FAB_CMD_RETRIED ] = { -1, 69, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_BR_PRED_LSTACK ] = { 11, 9, 9, 11, -1, -1 },
+ [ POWER6_PME_PM_GXO_DATA_CYC_BUSY ] = { 127, 134, 125, 133, -1, -1 },
+ [ POWER6_PME_PM_DFU_SUBNORM ] = { 30, 37, 29, 37, -1, -1 },
+ [ POWER6_PME_PM_FPU_ISSUE_OOO ] = { 111, 119, 107, 116, -1, -1 },
+ [ POWER6_PME_PM_LSU_REJECT_ULD_BOTH ] = { -1, 255, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_L2SB_ST_MISS ] = { 183, 192, 183, 189, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_L25_MOD_CYC ] = { -1, -1, -1, 17, -1, -1 },
+ [ POWER6_PME_PM_INST_PTEG_1ST_HALF ] = { 148, 157, 148, 154, -1, -1 },
+ [ POWER6_PME_PM_DERAT_MISS_16M ] = { -1, -1, 343, -1, -1, -1 },
+ [ POWER6_PME_PM_GX_DMA_WRITE ] = { 129, 136, 127, 135, -1, -1 },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_MOD ] = { -1, -1, -1, 275, -1, -1 },
+ [ POWER6_PME_PM_MEM1_DP_RQ_GLOB_LOC ] = { 254, 265, 248, 253, -1, -1 },
+ [ POWER6_PME_PM_L2SB_LD_REQ_DATA ] = { 179, 188, 179, 185, -1, -1 },
+ [ POWER6_PME_PM_L2SA_LD_MISS_INST ] = { 163, 172, 163, 169, -1, -1 },
+ [ POWER6_PME_PM_MRK_LSU0_REJECT_L2MISS ] = { 269, 281, 263, 264, -1, -1 },
+ [ POWER6_PME_PM_MRK_IFU_FIN ] = { -1, 278, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_INST_FROM_L3 ] = { -1, -1, 145, -1, -1, -1 },
+ [ POWER6_PME_PM_FXU1_FIN ] = { -1, -1, -1, 125, -1, -1 },
+ [ POWER6_PME_PM_THRD_PRIO_4_CYC ] = { -1, -1, -1, 308, -1, -1 },
+ [ POWER6_PME_PM_MRK_DATA_FROM_L35_MOD ] = { 261, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU_REJECT_SET_MPRED ] = { -1, 252, 238, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_DERAT_MISS_16G ] = { -1, -1, -1, 346, -1, -1 },
+ [ POWER6_PME_PM_FPU0_FXDIV ] = { 81, 90, 79, 87, -1, -1 },
+ [ POWER6_PME_PM_MRK_LSU1_REJECT_UST ] = { 275, 287, 269, 270, -1, -1 },
+ [ POWER6_PME_PM_FPU_ISSUE_DIV_SQRT_OVERLAP ] = { 110, 118, 106, 115, -1, -1 },
+ [ POWER6_PME_PM_INST_FROM_L35_SHR ] = { -1, 155, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_LSU_REJECT_LHS ] = { -1, -1, -1, 273, -1, -1 },
+ [ POWER6_PME_PM_LSU_LMQ_FULL_CYC ] = { 238, 247, 233, 237, -1, -1 },
+ [ POWER6_PME_PM_SYNC_COUNT ] = { 342, 349, 336, 334, -1, -1 },
+ [ POWER6_PME_PM_MEM0_DP_RQ_LOC_GLOB ] = { 251, 262, 245, 250, -1, -1 },
+ [ POWER6_PME_PM_L2SA_CASTOUT_MOD ] = { 157, 166, 157, 163, -1, -1 },
+ [ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT ] = { -1, -1, 341, -1, -1, -1 },
+ [ POWER6_PME_PM_PTEG_FROM_MEM_DP ] = { 298, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU_REJECT_SLOW ] = { -1, 253, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_PTEG_FROM_L25_MOD ] = { -1, -1, 291, -1, -1, -1 },
+ [ POWER6_PME_PM_THRD_PRIO_7_CYC ] = { 317, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_SHR ] = { -1, 292, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_ST_REQ_L2 ] = { -1, 317, 301, -1, -1, -1 },
+ [ POWER6_PME_PM_ST_REF_L1 ] = { 310, 315, 300, 300, -1, -1 },
+ [ POWER6_PME_PM_FPU_ISSUE_STALL_THRD ] = { 114, 122, 110, 119, -1, -1 },
+ [ POWER6_PME_PM_RUN_COUNT ] = { 343, 350, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_RUN_CYC ] = { 302, 309, -1, -1, -1, 0 },
+ [ POWER6_PME_PM_PTEG_FROM_RMEM ] = { -1, -1, 294, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU0_LDF ] = { 205, 214, 200, 205, -1, -1 },
+ [ POWER6_PME_PM_ST_MISS_L1 ] = { 309, 314, 299, 299, -1, -1 },
+ [ POWER6_PME_PM_INST_FROM_DL2L3_SHR ] = { -1, -1, 142, -1, -1, -1 },
+ [ POWER6_PME_PM_L2SA_IC_INV ] = { 160, 169, 160, 166, -1, -1 },
+ [ POWER6_PME_PM_THRD_ONE_RUN_CYC ] = { 315, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_L2SB_LD_REQ_INST ] = { 180, 189, 180, 186, -1, -1 },
+ [ POWER6_PME_PM_MRK_DATA_FROM_L25_MOD ] = { -1, -1, 253, -1, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_XTHRD ] = { 55, 63, 53, 61, -1, -1 },
+ [ POWER6_PME_PM_L2SB_ST_REQ ] = { 184, 193, 184, 190, -1, -1 },
+ [ POWER6_PME_PM_INST_FROM_L21 ] = { -1, 154, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_INST_FROM_L3MISS ] = { -1, -1, 146, -1, -1, -1 },
+ [ POWER6_PME_PM_L3SB_HIT ] = { 194, 204, 192, 197, -1, -1 },
+ [ POWER6_PME_PM_EE_OFF_EXT_INT ] = { 57, 66, 56, 64, -1, -1 },
+ [ POWER6_PME_PM_INST_FROM_DL2L3_MOD ] = { -1, -1, -1, 148, -1, -1 },
+ [ POWER6_PME_PM_PMC6_OVERFLOW ] = { -1, -1, 289, -1, -1, -1 },
+ [ POWER6_PME_PM_FPU_FLOP ] = { 104, -1, -1, 109, -1, -1 },
+ [ POWER6_PME_PM_FXU_BUSY ] = { -1, 125, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_FPU1_FLOP ] = { 91, 100, 89, 97, -1, -1 },
+ [ POWER6_PME_PM_IC_RELOAD_SHR ] = { 135, 144, 134, 141, -1, -1 },
+ [ POWER6_PME_PM_INST_TABLEWALK_CYC ] = { 151, 160, 151, 157, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_RL2L3_MOD_CYC ] = { -1, -1, -1, 22, -1, -1 },
+ [ POWER6_PME_PM_THRD_PRIO_DIFF_5or6_CYC ] = { -1, -1, -1, 309, -1, -1 },
+ [ POWER6_PME_PM_IBUF_FULL_CYC ] = { 130, 138, 128, 136, -1, -1 },
+ [ POWER6_PME_PM_L2SA_LD_REQ ] = { 164, 173, 164, 170, -1, -1 },
+ [ POWER6_PME_PM_VMX1_LD_WRBACK ] = { 327, 334, 321, 319, -1, -1 },
+ [ POWER6_PME_PM_MRK_FPU_FIN ] = { -1, 276, 261, -1, -1, -1 },
+ [ POWER6_PME_PM_THRD_PRIO_5_CYC ] = { -1, -1, 309, -1, -1, -1 },
+ [ POWER6_PME_PM_DFU_BACK2BACK ] = { 25, 32, 24, 32, -1, -1 },
+ [ POWER6_PME_PM_MRK_DATA_FROM_LMEM ] = { -1, -1, -1, 258, -1, -1 },
+ [ POWER6_PME_PM_LSU_REJECT_LHS ] = { 240, -1, -1, 240, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_SPR ] = { 50, 59, 49, 57, -1, -1 },
+ [ POWER6_PME_PM_FREQ_DOWN ] = { -1, -1, 115, -1, -1, -1 },
+ [ POWER6_PME_PM_DFU_ENC_BCD_DPD ] = { 27, 34, 26, 34, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_GPR ] = { 39, 47, 38, 46, -1, -1 },
+ [ POWER6_PME_PM_LSU0_NCST ] = { 207, 216, 202, 207, -1, -1 },
+ [ POWER6_PME_PM_MRK_INST_ISSUED ] = { 268, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_INST_FROM_RL2L3_SHR ] = { -1, 156, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_FPU_DENORM ] = { -1, 110, 99, -1, -1, -1 },
+ [ POWER6_PME_PM_PTEG_FROM_L3MISS ] = { -1, -1, 293, -1, -1, -1 },
+ [ POWER6_PME_PM_RUN_PURR ] = { -1, -1, -1, 347, -1, -1 },
+ [ POWER6_PME_PM_MRK_VMX0_LD_WRBACK ] = { 283, 295, 278, 280, -1, -1 },
+ [ POWER6_PME_PM_L2_MISS ] = { -1, 197, 185, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_DATA_FROM_L3 ] = { -1, -1, 254, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_LSU1_REJECT_LHS ] = { 273, 285, 267, 268, -1, -1 },
+ [ POWER6_PME_PM_L2SB_LD_MISS_INST ] = { 177, 186, 177, 183, -1, -1 },
+ [ POWER6_PME_PM_PTEG_FROM_RL2L3_SHR ] = { -1, 307, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_DERAT_MISS_64K ] = { 354, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_LWSYNC ] = { 247, 258, 241, 246, -1, -1 },
+ [ POWER6_PME_PM_FPU1_FXMULT ] = { 97, 106, 95, 103, -1, -1 },
+ [ POWER6_PME_PM_MEM0_DP_CL_WR_GLOB ] = { 248, 259, 242, 247, -1, -1 },
+ [ POWER6_PME_PM_LSU0_REJECT_PARTIAL_SECTOR ] = { 215, 224, 210, 215, -1, -1 },
+ [ POWER6_PME_PM_INST_IMC_MATCH_CMPL ] = { 147, -1, -1, 153, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_THERMAL ] = { 52, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_FPU_FRSP ] = { -1, 113, 101, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_INST_FIN ] = { -1, -1, 262, 262, -1, -1 },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_SHR ] = { -1, -1, 271, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_DTLB_REF ] = { 264, 273, 258, 259, -1, -1 },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_L25_SHR ] = { -1, -1, -1, 276, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_LSU ] = { 44, 52, 43, 51, -1, -1 },
+ [ POWER6_PME_PM_FPU_FSQRT_FDIV ] = { -1, 114, 102, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_COUNT ] = { -1, 359, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DATA_PTEG_SECONDARY ] = { 19, 27, 19, 26, -1, -1 },
+ [ POWER6_PME_PM_FPU1_FEST ] = { 89, 98, 87, 95, -1, -1 },
+ [ POWER6_PME_PM_L2SA_LD_HIT ] = { 161, 170, 161, 167, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_MEM_DP_CYC ] = { -1, -1, -1, 21, -1, -1 },
+ [ POWER6_PME_PM_BR_MPRED_CCACHE ] = { 4, 2, 2, 4, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_COUNT ] = { -1, 355, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU1_REJECT_SET_MPRED ] = { 229, 238, 224, 229, -1, -1 },
+ [ POWER6_PME_PM_FPU_ISSUE_2 ] = { 109, 117, 105, 114, -1, -1 },
+ [ POWER6_PME_PM_LSU1_REJECT_L2_CORR ] = { 225, 234, 220, 225, -1, -1 },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_DMEM ] = { -1, 289, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_MEM1_DP_RQ_LOC_GLOB ] = { 255, 266, 249, 254, -1, -1 },
+ [ POWER6_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC ] = { -1, 325, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_THRD_PRIO_0_CYC ] = { 316, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { -1, -1, 116, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU1_REJECT_DERAT_MPRED ] = { 223, 232, 218, 223, -1, -1 },
+ [ POWER6_PME_PM_MRK_VMX1_LD_WRBACK ] = { 284, 296, 279, 281, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_RL2L3_SHR_CYC ] = { -1, 24, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_IERAT_MISS_16M ] = { -1, 362, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_DATA_FROM_MEM_DP ] = { 262, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_LARX_L1HIT ] = { 198, 208, 196, 201, -1, -1 },
+ [ POWER6_PME_PM_L2_ST_MISS_DATA ] = { 190, -1, -1, 193, -1, -1 },
+ [ POWER6_PME_PM_FPU_ST_FOLDED ] = { -1, -1, 114, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_DATA_FROM_L35_SHR ] = { -1, 271, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_MULT_GPR ] = { 46, 54, 45, 53, -1, -1 },
+ [ POWER6_PME_PM_FPU0_1FLOP ] = { 71, 80, 69, 77, -1, -1 },
+ [ POWER6_PME_PM_IERAT_MISS_16G ] = { 352, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_IC_PREF_WRITE ] = { 134, 143, 133, 140, -1, -1 },
+ [ POWER6_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC ] = { -1, -1, -1, 310, -1, -1 },
+ [ POWER6_PME_PM_FPU0_FIN ] = { 75, 84, 73, 81, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_L2_CYC ] = { -1, 18, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DERAT_REF_16G ] = { -1, -1, -1, 342, -1, -1 },
+ [ POWER6_PME_PM_BR_PRED ] = { 8, 6, 6, 8, -1, -1 },
+ [ POWER6_PME_PM_VMX1_LD_ISSUED ] = { 326, 333, 320, 318, -1, -1 },
+ [ POWER6_PME_PM_L2SB_CASTOUT_MOD ] = { 171, 180, 171, 177, -1, -1 },
+ [ POWER6_PME_PM_INST_FROM_DMEM ] = { -1, 152, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_L35_SHR_CYC ] = { -1, 20, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU0_NCLD ] = { 206, 215, 201, 206, -1, -1 },
+ [ POWER6_PME_PM_FAB_RETRY_NODE_PUMP ] = { 64, 74, 63, 70, -1, -1 },
+ [ POWER6_PME_PM_VMX0_INST_ISSUED ] = { 321, 328, 315, 313, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_L25_MOD ] = { -1, -1, 12, -1, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_ITLB_ISLB ] = { 42, 50, 41, 49, -1, -1 },
+ [ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { -1, 248, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_THRD_CONC_RUN_INST ] = { -1, -1, 306, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_L2 ] = { 277, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_PURR ] = { 301, -1, -1, 293, -1, -1 },
+ [ POWER6_PME_PM_DERAT_MISS_64K ] = { -1, 361, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_PMC2_REWIND ] = { -1, -1, 287, -1, -1, -1 },
+ [ POWER6_PME_PM_INST_FROM_L2 ] = { 143, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_INST_DISP ] = { -1, 149, 139, -1, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_L25_SHR ] = { -1, -1, -1, 16, -1, -1 },
+ [ POWER6_PME_PM_L1_DCACHE_RELOAD_VALID ] = { -1, -1, 154, 160, -1, -1 },
+ [ POWER6_PME_PM_LSU1_REJECT_UST ] = { 232, 241, 227, 232, -1, -1 },
+ [ POWER6_PME_PM_FAB_ADDR_COLLISION ] = { 58, 68, 58, 65, -1, -1 },
+ [ POWER6_PME_PM_MRK_FXU_FIN ] = { -1, 277, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU0_REJECT_UST ] = { 219, 228, 214, 219, -1, -1 },
+ [ POWER6_PME_PM_PMC4_OVERFLOW ] = { 292, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_L3 ] = { -1, -1, 273, -1, -1, -1 },
+ [ POWER6_PME_PM_INST_FROM_L2MISS ] = { -1, -1, -1, 151, -1, -1 },
+ [ POWER6_PME_PM_L2SB_ST_HIT ] = { 182, 191, 182, 188, -1, -1 },
+ [ POWER6_PME_PM_DPU_WT_IC_MISS_COUNT ] = { -1, 357, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_DATA_FROM_DL2L3_SHR ] = { -1, -1, 252, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_L35_MOD ] = { 278, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_FPU1_FPSCR ] = { 93, 102, 91, 99, -1, -1 },
+ [ POWER6_PME_PM_LSU_REJECT_UST ] = { -1, 256, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU0_DERAT_MISS ] = { 204, 213, 199, 204, -1, -1 },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_MEM_DP ] = { 279, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_DATA_FROM_L2 ] = { 259, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_FPU0_FSQRT_FDIV ] = { 80, 89, 78, 86, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_FXU_SOPS ] = { 38, 46, 37, 45, -1, -1 },
+ [ POWER6_PME_PM_MRK_FPU0_FIN ] = { 265, 274, 259, 260, -1, -1 },
+ [ POWER6_PME_PM_L2SB_LD_MISS_DATA ] = { 176, 185, 176, 182, -1, -1 },
+ [ POWER6_PME_PM_LSU_SRQ_EMPTY_CYC ] = { -1, -1, -1, 244, -1, -1 },
+ [ POWER6_PME_PM_1PLUS_PPC_DISP ] = { 2, -1, -1, 1, -1, -1 },
+ [ POWER6_PME_PM_VMX_ST_ISSUED ] = { 336, 343, 330, 328, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_L2MISS ] = { -1, 17, 13, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU0_REJECT_ULD ] = { 218, 227, 213, 218, -1, -1 },
+ [ POWER6_PME_PM_SUSPENDED ] = { 311, 318, 302, 302, -1, -1 },
+ [ POWER6_PME_PM_DFU_ADD_SHIFTED_BOTH ] = { 24, 31, 23, 31, -1, -1 },
+ [ POWER6_PME_PM_LSU_REJECT_NO_SCRATCH ] = { -1, 251, 237, -1, -1, -1 },
+ [ POWER6_PME_PM_STCX_FAIL ] = { 306, 312, 298, 297, -1, -1 },
+ [ POWER6_PME_PM_FPU1_DENORM ] = { 87, 96, 85, 93, -1, -1 },
+ [ POWER6_PME_PM_GCT_NOSLOT_COUNT ] = { 349, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_DL2L3_SHR_CYC ] = { -1, 12, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_L21 ] = { -1, 15, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_FPU_1FLOP ] = { 101, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU1_REJECT ] = { 222, 231, 217, 222, -1, -1 },
+ [ POWER6_PME_PM_IC_REQ ] = { 136, 145, 135, 142, -1, -1 },
+ [ POWER6_PME_PM_MRK_DFU_FIN ] = { -1, -1, 257, -1, -1, -1 },
+ [ POWER6_PME_PM_NOT_LLA_CYC ] = { 346, 353, 338, 338, -1, -1 },
+ [ POWER6_PME_PM_INST_FROM_L1 ] = { 142, 153, 143, 149, -1, -1 },
+ [ POWER6_PME_PM_MRK_VMX_COMPLEX_ISSUED ] = { 285, 297, 280, 282, -1, -1 },
+ [ POWER6_PME_PM_BRU_FIN ] = { 3, 1, 1, 2, -1, -1 },
+ [ POWER6_PME_PM_LSU1_REJECT_EXTERN ] = { 224, 233, 219, 224, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_L21_CYC ] = { -1, -1, -1, 15, -1, -1 },
+ [ POWER6_PME_PM_GXI_CYC_BUSY ] = { 123, 130, 121, 129, -1, -1 },
+ [ POWER6_PME_PM_MRK_LD_MISS_L1 ] = { -1, 280, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_L1_WRITE_CYC ] = { 156, 165, 156, 162, -1, -1 },
+ [ POWER6_PME_PM_LLA_CYC ] = { 345, 352, 337, 337, -1, -1 },
+ [ POWER6_PME_PM_MRK_DATA_FROM_L2MISS ] = { 260, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_GCT_FULL_COUNT ] = { 339, 346, 333, 331, -1, -1 },
+ [ POWER6_PME_PM_MEM_DP_RQ_LOC_GLOB ] = { -1, 268, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_DATA_FROM_RL2L3_SHR ] = { -1, 23, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_LSU_REJECT_UST ] = { -1, 288, 270, -1, -1, -1 },
+ [ POWER6_PME_PM_MRK_VMX_PERMUTE_ISSUED ] = { 287, 299, 282, 284, -1, -1 },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_L21 ] = { -1, 290, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = { -1, 320, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_BR_MPRED ] = { -1, -1, -1, 3, -1, -1 },
+ [ POWER6_PME_PM_LD_REQ_L2 ] = { 203, -1, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_FLUSH_ASYNC ] = { 68, 77, 66, 74, -1, -1 },
+ [ POWER6_PME_PM_HV_CYC ] = { -1, 137, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU1_DERAT_MISS ] = { 220, 229, 215, 220, -1, -1 },
+ [ POWER6_PME_PM_DPU_HELD_SMT ] = { 49, 58, 48, 56, -1, -1 },
+ [ POWER6_PME_PM_MRK_LSU_FIN ] = { -1, -1, -1, 272, -1, -1 },
+ [ POWER6_PME_PM_MRK_DATA_FROM_RL2L3_SHR ] = { -1, 272, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_LSU0_REJECT_STQ_FULL ] = { 217, 226, 212, 217, -1, -1 },
+ [ POWER6_PME_PM_MRK_DERAT_REF_4K ] = { -1, 363, -1, -1, -1, -1 },
+ [ POWER6_PME_PM_FPU_ISSUE_STALL_FPR ] = { 112, 120, 108, 117, -1, -1 },
+ [ POWER6_PME_PM_IFU_FIN ] = { 138, 147, 137, 144, -1, -1 },
+ [ POWER6_PME_PM_GXO_CYC_BUSY ] = { 126, 133, 124, 132, -1, -1 }
+};
+
+static const unsigned long long power6_group_vecs[][POWER6_NUM_GROUP_VEC] = {
+ [ POWER6_PME_PM_LSU_REJECT_STQ_FULL ] = {
+ 0x2000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_FXU_MULTI ] = {
+ 0x0000008000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_VMX1_STALL ] = {
+ 0x0000000000000000ULL,
+ 0x0000000001000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PMC2_SAVED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SB_IC_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_IERAT_MISS_64K ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000100ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_PRIO_DIFF_3or4_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000010000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LD_REF_L1_BOTH ] = {
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU1_FCONV ] = {
+ 0x0000000000000000ULL,
+ 0x4000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_IBUF_FULL_COUNT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000100000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_LSU_DERAT_MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000800000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_ST_CMPL ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000002000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2_CASTOUT_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0000008000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU1_ST_FOLDED ] = {
+ 0x0000000000000000ULL,
+ 0x4000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_INST_TIMEO ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000400000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_WT ] = {
+ 0x0000000800000000ULL,
+ 0x0000000000000000ULL,
+ 0x0004000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_RESTART ] = {
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_IERAT_MISS ] = {
+ 0x0400000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU_SINGLE ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000002ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_LMEM ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000040000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_HV_COUNT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SA_ST_HIT ] = {
+ 0x0000000000000000ULL,
+ 0x0001000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2_LD_MISS_INST ] = {
+ 0x0000000000000000ULL,
+ 0x0000004000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_EXT_INT ] = {
+ 0x0080000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU1_LDF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000100ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FAB_CMD_ISSUED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000028000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PTEG_FROM_L21 ] = {
+ 0x0000000018000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SA_MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0000100000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PTEG_FROM_RL2L3_MOD ] = {
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_WT_COUNT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0002040000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_L25_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000008000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LD_HIT_L2 ] = {
+ 0x0000000000000000ULL,
+ 0x0000010000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PTEG_FROM_DL2L3_SHR ] = {
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MEM_DP_RQ_GLOB_LOC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000040000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L3SA_MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0004000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_NO_ITAG_COUNT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DSLB_MISS ] = {
+ 0x0600000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_FLUSH_ALIGN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000800ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_FPU_CR ] = {
+ 0x0000188000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PTEG_FROM_L2MISS ] = {
+ 0x0000000010000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DATA_FROM_DMEM ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000400ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PTEG_FROM_LMEM ] = {
+ 0x0000000060000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DERAT_REF_64K ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000001000000000ULL,
+ 0x0000000000000010ULL
+ },
+ [ POWER6_PME_PM_L2SA_LD_REQ_INST ] = {
+ 0x0000000000000000ULL,
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DERAT_MISS_16M ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_DL2L3_MOD ] = {
+ 0x0000000000000400ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU0_FXMULT ] = {
+ 0x0000000000000000ULL,
+ 0x0200000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L3SB_MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0008000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_STCX_CANCEL ] = {
+ 0x0008000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SA_LD_MISS_DATA ] = {
+ 0x0000000000000000ULL,
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_IC_INV_L2 ] = {
+ 0x0000000000000000ULL,
+ 0x0000008000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD ] = {
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0004000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PMC1_OVERFLOW ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_PRIO_6_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000008000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_L3MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000040000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_LSU0_REJECT_UST ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000020000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_INST_DISP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000080000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LARX ] = {
+ 0x0018000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_CMPL ] = {
+ 0x0100000000006001ULL,
+ 0x0000000000000000ULL,
+ 0x3800003ffffffe18ULL,
+ 0x0000000000000038ULL
+ },
+ [ POWER6_PME_PM_FXU_IDLE ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000040000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DATA_FROM_DL2L3_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000400ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2_LD_REQ_DATA ] = {
+ 0x0000000000000000ULL,
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_DERAT_MISS_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000800ULL,
+ 0x0040000000000020ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_POWER_COUNT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0100020000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_FROM_RL2L3_MOD ] = {
+ 0x0000000001000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_DMEM_CYC ] = {
+ 0x0000000000004000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_DMEM ] = {
+ 0x0000000000000800ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_REJECT_PARTIAL_SECTOR ] = {
+ 0x2000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_REJECT_DERAT_MPRED ] = {
+ 0x0800000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU1_REJECT_ULD ] = {
+ 0x8000000000000000ULL,
+ 0x0000000000000002ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_L3_CYC ] = {
+ 0x0000000000010000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FXU1_BUSY_FXU0_IDLE ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000040000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_FROM_MEM_DP ] = {
+ 0x0000000002000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_FLUSH_DSI ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000800ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DERAT_REF_16G ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000010ULL
+ },
+ [ POWER6_PME_PM_LSU_LDF_BOTH ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000100ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU1_1FLOP ] = {
+ 0x0000000000000000ULL,
+ 0x0800000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_RMEM_CYC ] = {
+ 0x0000000000004000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_PTEG_SECONDARY ] = {
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L1_ICACHE_MISS ] = {
+ 0x0000000800000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_DISP_LLA ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000001000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_BOTH_RUN_CYC ] = {
+ 0x0020000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0200000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_ST_CHAINED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000200ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU1_FXDIV ] = {
+ 0x0000000000000000ULL,
+ 0x1000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FREQ_UP ] = {
+ 0x0000000400000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FAB_RETRY_SYS_PUMP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000010000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_LMEM ] = {
+ 0x0000000000100800ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PMC3_OVERFLOW ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU0_REJECT_SET_MPRED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000001ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU0_REJECT_DERAT_MPRED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000084ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU1_REJECT_STQ_FULL ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_BR_MPRED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000200ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SA_ST_MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0000080000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU0_REJECT_EXTERN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000008ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_BR_TAKEN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000200ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_ISLB_MISS ] = {
+ 0x0600000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_CYC ] = {
+ 0x0100200000283003ULL,
+ 0x0000000000000000ULL,
+ 0x5c00000481000018ULL,
+ 0x0000000000000005ULL
+ },
+ [ POWER6_PME_PM_FPU_FXDIV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000002ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_LLA_END ] = {
+ 0x0000020000000000ULL,
+ 0x0000000000001000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MEM0_DP_CL_WR_LOC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_LSU_REJECT_ULD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000210000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_1PLUS_PPC_CMPL ] = {
+ 0x0040000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PTEG_FROM_DMEM ] = {
+ 0x0000000040000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_WT_BR_MPRED_COUNT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0002040000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_GCT_FULL_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000002000ULL,
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_FROM_L25_SHR ] = {
+ 0x0000000000800000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DERAT_MISS_4K ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000002000000000ULL,
+ 0x0000000000000020ULL
+ },
+ [ POWER6_PME_PM_DC_PREF_STREAM_ALLOC ] = {
+ 0x0001000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU1_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x2000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_BR_MPRED_TA ] = {
+ 0x0000000000000028ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_POWER ] = {
+ 0x0000001400000000ULL,
+ 0x0000000000000000ULL,
+ 0x0200000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_RUN_INST_CMPL ] = {
+ 0xffffffffffffffffULL,
+ 0xffffffffffffffffULL,
+ 0xffffffffffffffffULL,
+ 0x000000000000003fULL
+ },
+ [ POWER6_PME_PM_GCT_EMPTY_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000002000ULL,
+ 0x0010000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LLA_COUNT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000080000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU0_REJECT_NO_SCRATCH ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000010ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_WT_IC_MISS ] = {
+ 0x0000000800000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000080000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_L3MISS ] = {
+ 0x0000000000000180ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000008ULL
+ },
+ [ POWER6_PME_PM_FPU_FPSCR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000001ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_VMX1_INST_ISSUED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000200000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FLUSH ] = {
+ 0x0002000000080000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_ST_HIT_L2 ] = {
+ 0x0000000000000000ULL,
+ 0x0000010000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_SYNC_CYC ] = {
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0061800000000010ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FAB_SYS_PUMP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000010000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_IC_PREF_REQ ] = {
+ 0x0004000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MEM0_DP_RQ_GLOB_LOC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU_ISSUE_0 ] = {
+ 0x0000000000000000ULL,
+ 0x0010000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_PRIO_2_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000004000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_VMX_SIMPLE_ISSUED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000100000ULL,
+ 0x0000000400000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_FPU1_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000800100000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_CW ] = {
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L3SA_REF ] = {
+ 0x0000000000000000ULL,
+ 0x0004000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_STCX ] = {
+ 0x0018000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SB_MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0000100000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU0_REJECT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000044ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_TB_BIT_TRANS ] = {
+ 0x0080000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THERMAL_MAX ] = {
+ 0x0000001000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU0_STF ] = {
+ 0x0000000000000000ULL,
+ 0x0080000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU1_FMA ] = {
+ 0x0000000000000000ULL,
+ 0x0800000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU1_REJECT_LHS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000020ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_INT ] = {
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_LLA_BOTH_CYC ] = {
+ 0x0040000000000000ULL,
+ 0x0000000000001000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_THERMAL_COUNT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0002020000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PMC4_REWIND ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DERAT_REF_16M ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000080ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU0_FCONV ] = {
+ 0x0000000000000000ULL,
+ 0x0400000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SA_LD_REQ_DATA ] = {
+ 0x0000000000000000ULL,
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_MEM_DP ] = {
+ 0x0000000000020800ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_VMX_FLOAT_ISSUED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_L2MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000020000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_PRIO_DIFF_1or2_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000010000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_VMX0_STALL ] = {
+ 0x0000000000000000ULL,
+ 0x0000000001000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = {
+ 0x0000000000000000ULL,
+ 0x0002000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_DERAT_MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000800ULL,
+ 0x0020004000000020ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU0_SINGLE ] = {
+ 0x0000000000000000ULL,
+ 0x0100000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU_ISSUE_STEERING ] = {
+ 0x0000000000000000ULL,
+ 0x0010000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_PRIO_1_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000004000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_VMX_COMPLEX_ISSUED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000100000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU_ISSUE_ST_FOLDED ] = {
+ 0x0000000000000000ULL,
+ 0x0020000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DFU_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000004000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_BR_PRED_CCACHE ] = {
+ 0x0000000000000018ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_ST_CMPL_INT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000002000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FAB_MMIO ] = {
+ 0x0000000000000000ULL,
+ 0x0000000020000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_VMX_SIMPLE_ISSUED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000400000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU_STF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0800000000000002ULL,
+ 0x0000000000000002ULL
+ },
+ [ POWER6_PME_PM_MEM1_DP_CL_WR_GLOB ] = {
+ 0x0000000000000000ULL,
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DATA_FROM_L3MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000002000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_GCT_NOSLOT_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000002000ULL,
+ 0x0010000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2_ST_REQ_DATA ] = {
+ 0x0000000000000000ULL,
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_TABLEWALK_COUNT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PTEG_FROM_L35_SHR ] = {
+ 0x0000000020000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_ISYNC ] = {
+ 0x0000184000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DATA_FROM_L25_SHR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000001000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L3SA_HIT ] = {
+ 0x0000000000000000ULL,
+ 0x0004000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DERAT_MISS_16G ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_PTEG_2ND_HALF ] = {
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SA_ST_REQ ] = {
+ 0x0000000000000000ULL,
+ 0x0001080000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_FROM_LMEM ] = {
+ 0x0000000002000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = {
+ 0x0000000000000000ULL,
+ 0x0002000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PTEG_FROM_L2 ] = {
+ 0x0000000008000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_PTEG_1ST_HALF ] = {
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_BR_MPRED_COUNT ] = {
+ 0x0000000000000024ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_IERAT_MISS_4K ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000100ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_BOTH_RUN_COUNT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0100000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_REJECT_ULD ] = {
+ 0x8000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_DL2L3_MOD_CYC ] = {
+ 0x0000000000002000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000040000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU0_FLOP ] = {
+ 0x0000000000000000ULL,
+ 0x0100000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU0_FEST ] = {
+ 0x0000000000000000ULL,
+ 0x0600000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_LSU0_REJECT_LHS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000020000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_VMX_RESULT_SAT_1 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000800000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_NO_ITAG_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000001000000000ULL,
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU1_REJECT_NO_SCRATCH ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000014ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_0INST_FETCH ] = {
+ 0x0080000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000100000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_WT_BR_MPRED ] = {
+ 0x0000000800000000ULL,
+ 0x0000000000000000ULL,
+ 0x0004000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L1_PREF ] = {
+ 0x0001000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_VMX_FLOAT_MULTICYCLE ] = {
+ 0x0000000000000000ULL,
+ 0x0000000001800000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_L25_SHR_CYC ] = {
+ 0x0000000000020000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_L3 ] = {
+ 0x0000000000010100ULL,
+ 0x000c000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000001ULL
+ },
+ [ POWER6_PME_PM_PMC2_OVERFLOW ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_VMX0_LD_WRBACK ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000400000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU0_DENORM ] = {
+ 0x0000000000000000ULL,
+ 0x0100000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_FETCH_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000002000ULL,
+ 0x0000010000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_LDF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000100ULL,
+ 0x0800000000000000ULL,
+ 0x0000000000000004ULL
+ },
+ [ POWER6_PME_PM_LSU_REJECT_L2_CORR ] = {
+ 0x0800000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DERAT_REF_64K ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000080ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_PRIO_3_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000004000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU_FMA ] = {
+ 0x0000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x0400000000000000ULL,
+ 0x0000000000000002ULL
+ },
+ [ POWER6_PME_PM_INST_FROM_L35_MOD ] = {
+ 0x0000000000800000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DFU_CONV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000002000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_FROM_L25_MOD ] = {
+ 0x0000000000400000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PTEG_FROM_L35_MOD ] = {
+ 0x0000000020000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_VMX_ST_ISSUED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000800000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_VMX_FLOAT_ISSUED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000100000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU0_REJECT_L2_CORR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000008ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_L2MISS ] = {
+ 0x0100000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU_FCONV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000004ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU_FXMULT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000001ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU1_FRSP ] = {
+ 0x0000000000000000ULL,
+ 0x4000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DERAT_REF_16M ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000001000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SB_CASTOUT_SHR ] = {
+ 0x0000000000000000ULL,
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_ONE_RUN_COUNT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_FROM_RMEM ] = {
+ 0x0000000002000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_BOTH_BUS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000200ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU1_FSQRT_FDIV ] = {
+ 0x0000000000000000ULL,
+ 0x0800000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2_LD_REQ_INST ] = {
+ 0x0000000000000000ULL,
+ 0x0000004000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_L35_SHR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000010000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_BR_PRED_CR ] = {
+ 0x0000000000000014ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_LSU0_REJECT_ULD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000020000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_REJECT ] = {
+ 0x0800000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_REJECT_LHS_BOTH ] = {
+ 0x1000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_GXO_ADDR_CYC_BUSY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_SRQ_EMPTY_COUNT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0008000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PTEG_FROM_L3 ] = {
+ 0x0000000010000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_VMX0_LD_ISSUED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000600000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FXU_PIPELINED_MULT_DIV ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000080000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU1_STF ] = {
+ 0x0000000000000000ULL,
+ 0x0800000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DFU_ADD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000002000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MEM_DP_CL_WR_GLOB ] = {
+ 0x0000000000000000ULL,
+ 0x0000000040000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_LSU1_REJECT_ULD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000040000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_ITLB_REF ] = {
+ 0x0200000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU0_REJECT_L2MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000400ULL,
+ 0x0000008000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_L35_SHR ] = {
+ 0x0000000000000300ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000001ULL
+ },
+ [ POWER6_PME_PM_MRK_DATA_FROM_RL2L3_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000008000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU0_FPSCR ] = {
+ 0x0000000000000000ULL,
+ 0x0200000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_L2 ] = {
+ 0x0000000000040080ULL,
+ 0x0000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_XER ] = {
+ 0x0000004000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FAB_NODE_PUMP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000010000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_VMX_RESULT_SAT_0_1 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000800000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LD_REF_L1 ] = {
+ 0x0000c00000000000ULL,
+ 0x0000000000000000ULL,
+ 0x2080000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_TLB_REF ] = {
+ 0x0200000100000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DC_PREF_OUT_OF_STREAMS ] = {
+ 0x0001000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FLUSH_FPU ] = {
+ 0x0002000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MEM1_DP_CL_WR_LOC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SB_LD_HIT ] = {
+ 0x0000000000000000ULL,
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FAB_DCLAIM ] = {
+ 0x0000000000000000ULL,
+ 0x0000000008000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MEM_DP_CL_WR_LOC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000040000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_BR_MPRED_CR ] = {
+ 0x0000000000000024ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_REJECT_EXTERN ] = {
+ 0x1000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_RL2L3_MOD ] = {
+ 0x0000000000010400ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_RU_WQ ] = {
+ 0x0000084000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LD_MISS_L1 ] = {
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL,
+ 0x1080084000000020ULL,
+ 0x0000000000000006ULL
+ },
+ [ POWER6_PME_PM_DC_INV_L2 ] = {
+ 0x0000000000000000ULL,
+ 0x0000008000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_RMEM ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x4000000000000001ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FXU0_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000080000ULL,
+ 0x4000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_FPQ ] = {
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_GX_DMA_READ ] = {
+ 0x0000000000000000ULL,
+ 0x0000000800000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU1_REJECT_PARTIAL_SECTOR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000010ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_0INST_FETCH_COUNT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000100000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PMC5_OVERFLOW ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SB_LD_REQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_PRIO_DIFF_0_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000010000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_RMEM ] = {
+ 0x0000000000004800ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000400ULL,
+ 0x0010000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_ST_REF_L1_BOTH ] = {
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_VMX_PERMUTE_ISSUED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000100000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_BR_TAKEN ] = {
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FAB_DMA ] = {
+ 0x0000000000000000ULL,
+ 0x0000000008000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_GCT_EMPTY_COUNT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0008010000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU1_SINGLE ] = {
+ 0x0000000000000000ULL,
+ 0x1000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SA_CASTOUT_SHR ] = {
+ 0x0000000000000000ULL,
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L3SB_REF ] = {
+ 0x0000000000000000ULL,
+ 0x0008000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU0_FRSP ] = {
+ 0x0000000000000000ULL,
+ 0x0400000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PMC4_SAVED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SA_DC_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_GXI_ADDR_CYC_BUSY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000400000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU0_FMA ] = {
+ 0x0000000000000000ULL,
+ 0x0080000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_SLB_MISS ] = {
+ 0x0400000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_ST_GPS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000002000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DERAT_REF_4K ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000080ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2_CASTOUT_SHR ] = {
+ 0x0000000000000000ULL,
+ 0x0000008000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_STCX_CR ] = {
+ 0x0000084000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU0_ST_FOLDED ] = {
+ 0x0000000000000000ULL,
+ 0x0400000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DATA_FROM_L21 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000800ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000020000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_L35_MOD ] = {
+ 0x0000000000208300ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000001ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_DL2L3_SHR ] = {
+ 0x0000000000008400ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_GXI_DATA_CYC_BUSY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000400000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_REJECT_STEAL ] = {
+ 0x1000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_ST_FIN ] = {
+ 0x0100000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_CR_LOGICAL ] = {
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0300000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_SEL_T0 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000020000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PTEG_RELOAD_VALID ] = {
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2_PREF_ST ] = {
+ 0x0000000000000000ULL,
+ 0x0002000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_STCX_FAIL ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000400000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU0_REJECT_LHS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000020ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DFU_EXP_EQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000000004000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_FP_FX_MULT ] = {
+ 0x0000010000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2_LD_MISS_DATA ] = {
+ 0x0000000000000000ULL,
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_L35_MOD_CYC ] = {
+ 0x0000000000208000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FLUSH_FXU ] = {
+ 0x0002000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU_ISSUE_1 ] = {
+ 0x0000000000000000ULL,
+ 0x0010000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_LMEM_CYC ] = {
+ 0x0000000000102000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_LSU_SOPS ] = {
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_PTEG_2ND_HALF ] = {
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRESH_TIMEO ] = {
+ 0x0040000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_REJECT_UST_BOTH ] = {
+ 0x4000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_REJECT_FAST ] = {
+ 0x0800000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_THRD_PRIO ] = {
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2_PREF_LD ] = {
+ 0x0000000000000000ULL,
+ 0x0002004000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU_FEST ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000004ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DATA_FROM_RMEM ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000008000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LD_MISS_L1_CYC ] = {
+ 0x0000000000001000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000020ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DERAT_MISS_4K ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_COMPLETION ] = {
+ 0x0000110000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0300000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU_ISSUE_STALL_ST ] = {
+ 0x0000000000000000ULL,
+ 0x0060000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SB_DC_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PTEG_FROM_L25_SHR ] = {
+ 0x0000000008000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PTEG_FROM_DL2L3_MOD ] = {
+ 0x0000000010000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FAB_CMD_RETRIED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000028000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_BR_PRED_LSTACK ] = {
+ 0x0000000000000018ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_GXO_DATA_CYC_BUSY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DFU_SUBNORM ] = {
+ 0x0000000000000000ULL,
+ 0x0000000004000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU_ISSUE_OOO ] = {
+ 0x0000000000000000ULL,
+ 0x0020000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_REJECT_ULD_BOTH ] = {
+ 0x8000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SB_ST_MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0000080000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_L25_MOD_CYC ] = {
+ 0x0000000000001000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_PTEG_1ST_HALF ] = {
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DERAT_MISS_16M ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_GX_DMA_WRITE ] = {
+ 0x0000000000000000ULL,
+ 0x0000000800000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000008000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MEM1_DP_RQ_GLOB_LOC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SB_LD_REQ_DATA ] = {
+ 0x0000000000000000ULL,
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SA_LD_MISS_INST ] = {
+ 0x0000000000000000ULL,
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_LSU0_REJECT_L2MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000800000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_IFU_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000400000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_FROM_L3 ] = {
+ 0x0000000000800000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FXU1_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000080000ULL,
+ 0x4000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_PRIO_4_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000008000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DATA_FROM_L35_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000002000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_REJECT_SET_MPRED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000001ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DERAT_MISS_16G ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000020ULL
+ },
+ [ POWER6_PME_PM_FPU0_FXDIV ] = {
+ 0x0000000000000000ULL,
+ 0x0100000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_LSU1_REJECT_UST ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000040000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU_ISSUE_DIV_SQRT_OVERLAP ] = {
+ 0x0000000000000000ULL,
+ 0x0060000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_FROM_L35_SHR ] = {
+ 0x0000000000800000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_LSU_REJECT_LHS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000010000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_LMQ_FULL_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000400ULL,
+ 0x0000008000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_SYNC_COUNT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0061800000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MEM0_DP_RQ_LOC_GLOB ] = {
+ 0x0000000000000000ULL,
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SA_CASTOUT_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0008008000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PTEG_FROM_MEM_DP ] = {
+ 0x0000000040000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_REJECT_SLOW ] = {
+ 0x2000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PTEG_FROM_L25_MOD ] = {
+ 0x0000000008000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_PRIO_7_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000008000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_SHR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_ST_REQ_L2 ] = {
+ 0x0000000000000000ULL,
+ 0x0000010000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_ST_REF_L1 ] = {
+ 0x0000c00000000000ULL,
+ 0x0000000000000000ULL,
+ 0x2000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU_ISSUE_STALL_THRD ] = {
+ 0x0000000000000000ULL,
+ 0x0040000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_RUN_COUNT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_RUN_CYC ] = {
+ 0xffffffffffffffffULL,
+ 0xffffffffffffffffULL,
+ 0xffffffffffffffffULL,
+ 0x000000000000003fULL
+ },
+ [ POWER6_PME_PM_PTEG_FROM_RMEM ] = {
+ 0x0000000040000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU0_LDF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000100ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_ST_MISS_L1 ] = {
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL,
+ 0x1080000000000000ULL,
+ 0x0000000000000004ULL
+ },
+ [ POWER6_PME_PM_INST_FROM_DL2L3_SHR ] = {
+ 0x0000000001000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SA_IC_INV ] = {
+ 0x0000000000000000ULL,
+ 0x0000400000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_ONE_RUN_CYC ] = {
+ 0x0020000000000002ULL,
+ 0x0000000000000000ULL,
+ 0x0001000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SB_LD_REQ_INST ] = {
+ 0x0000000000000000ULL,
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DATA_FROM_L25_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000800ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_XTHRD ] = {
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SB_ST_REQ ] = {
+ 0x0000000000000000ULL,
+ 0x0001080000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_FROM_L21 ] = {
+ 0x0000000004400000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_FROM_L3MISS ] = {
+ 0x0000000004000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000008ULL
+ },
+ [ POWER6_PME_PM_L3SB_HIT ] = {
+ 0x0000000000000000ULL,
+ 0x0008000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_EE_OFF_EXT_INT ] = {
+ 0x0080000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_FROM_DL2L3_MOD ] = {
+ 0x0000000001000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PMC6_OVERFLOW ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU_FLOP ] = {
+ 0x0000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FXU_BUSY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000040000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU1_FLOP ] = {
+ 0x0000000000000000ULL,
+ 0x1000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_IC_RELOAD_SHR ] = {
+ 0x0004000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_TABLEWALK_CYC ] = {
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_RL2L3_MOD_CYC ] = {
+ 0x0000000000010000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_PRIO_DIFF_5or6_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000010000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_IBUF_FULL_CYC ] = {
+ 0x0001000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000100000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SA_LD_REQ ] = {
+ 0x0000000000000000ULL,
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_VMX1_LD_WRBACK ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000400000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_FPU_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000800100000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_PRIO_5_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000008000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DFU_BACK2BACK ] = {
+ 0x0000000000000000ULL,
+ 0x0000000002000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DATA_FROM_LMEM ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000004000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_REJECT_LHS ] = {
+ 0x1000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_SPR ] = {
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FREQ_DOWN ] = {
+ 0x0000000400000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DFU_ENC_BCD_DPD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000004000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_GPR ] = {
+ 0x0000012000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU0_NCST ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000200ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_INST_ISSUED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000080000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_FROM_RL2L3_SHR ] = {
+ 0x0000000001000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU_DENORM ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000002ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PTEG_FROM_L3MISS ] = {
+ 0x0000000020000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_RUN_PURR ] = {
+ 0x0000000000000002ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_VMX0_LD_WRBACK ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2_MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0000104000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000008ULL
+ },
+ [ POWER6_PME_PM_MRK_DATA_FROM_L3 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000001000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_LSU1_REJECT_LHS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000040000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SB_LD_MISS_INST ] = {
+ 0x0000000000000000ULL,
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PTEG_FROM_RL2L3_SHR ] = {
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DERAT_MISS_64K ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000002000000000ULL,
+ 0x0000000000000020ULL
+ },
+ [ POWER6_PME_PM_LWSYNC ] = {
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU1_FXMULT ] = {
+ 0x0000000000000000ULL,
+ 0x2000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MEM0_DP_CL_WR_GLOB ] = {
+ 0x0000000000000000ULL,
+ 0x0000000080000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU0_REJECT_PARTIAL_SECTOR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000010ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_IMC_MATCH_CMPL ] = {
+ 0x0000000000000000ULL,
+ 0x0000001000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_THERMAL ] = {
+ 0x0000001400000000ULL,
+ 0x0000000000000000ULL,
+ 0x0004000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU_FRSP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000005ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_INST_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000080000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_SHR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000004000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DTLB_REF ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_L25_SHR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000010000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_LSU ] = {
+ 0x0000008000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU_FSQRT_FDIV ] = {
+ 0x0000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x0400000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_COUNT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0020008000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_PTEG_SECONDARY ] = {
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU1_FEST ] = {
+ 0x0000000000000000ULL,
+ 0x6000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SA_LD_HIT ] = {
+ 0x0000000000000000ULL,
+ 0x0000800000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_MEM_DP_CYC ] = {
+ 0x0000000000020000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_BR_MPRED_CCACHE ] = {
+ 0x0000000000000028ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_COUNT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0002000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU1_REJECT_SET_MPRED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000001ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU_ISSUE_2 ] = {
+ 0x0000000000000000ULL,
+ 0x0010000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU1_REJECT_L2_CORR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000008ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_DMEM ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000004000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MEM1_DP_RQ_LOC_GLOB ] = {
+ 0x0000000000000000ULL,
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000020000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_PRIO_0_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000004000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FXU0_BUSY_FXU1_IDLE ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000040000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU1_REJECT_DERAT_MPRED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000080ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_VMX1_LD_WRBACK ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000200000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_RL2L3_SHR_CYC ] = {
+ 0x0000000000001000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_IERAT_MISS_16M ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000100ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DATA_FROM_MEM_DP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000004000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LARX_L1HIT ] = {
+ 0x0010000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2_ST_MISS_DATA ] = {
+ 0x0000000000000000ULL,
+ 0x0000002000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU_ST_FOLDED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000004ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DATA_FROM_L35_SHR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000002000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_MULT_GPR ] = {
+ 0x0000110000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU0_1FLOP ] = {
+ 0x0000000000000000ULL,
+ 0x0080000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_IERAT_MISS_16G ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000100ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_IC_PREF_WRITE ] = {
+ 0x0004000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000020000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU0_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0200000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_L2_CYC ] = {
+ 0x0000000000040000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DERAT_REF_16G ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000080ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_BR_PRED ] = {
+ 0x0000000000000054ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_VMX1_LD_ISSUED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000600000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SB_CASTOUT_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0000200000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_FROM_DMEM ] = {
+ 0x0000000002000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_L35_SHR_CYC ] = {
+ 0x0000000000200000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU0_NCLD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000200ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FAB_RETRY_NODE_PUMP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000010000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_VMX0_INST_ISSUED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000200000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_L25_MOD ] = {
+ 0x0000000000020200ULL,
+ 0x0000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_ITLB_ISLB ] = {
+ 0x0000008000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000400ULL,
+ 0x0040000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_CONC_RUN_INST ] = {
+ 0x0020000000000002ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_L2 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000004000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PURR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000008ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DERAT_MISS_64K ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PMC2_REWIND ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_FROM_L2 ] = {
+ 0x0000000004400000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_DISP ] = {
+ 0x0000000000140001ULL,
+ 0x0000000000001000ULL,
+ 0x2000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_L25_SHR ] = {
+ 0x0000000000000200ULL,
+ 0x0000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L1_DCACHE_RELOAD_VALID ] = {
+ 0x0000000000040000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU1_REJECT_UST ] = {
+ 0x4000000000000000ULL,
+ 0x0000000000000002ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FAB_ADDR_COLLISION ] = {
+ 0x0000000000000000ULL,
+ 0x0000000020000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_FXU_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000200000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU0_REJECT_UST ] = {
+ 0x4000000000000000ULL,
+ 0x0000000000000002ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_PMC4_OVERFLOW ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_L3 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000020000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_FROM_L2MISS ] = {
+ 0x0000000004400000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SB_ST_HIT ] = {
+ 0x0000000000000000ULL,
+ 0x0001000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_WT_IC_MISS_COUNT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0080040000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DATA_FROM_DL2L3_SHR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000400ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_L35_MOD ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000010000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU1_FPSCR ] = {
+ 0x0000000000000000ULL,
+ 0x2000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_REJECT_UST ] = {
+ 0x4000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU0_DERAT_MISS ] = {
+ 0x0000000000000000ULL,
+ 0x00000000000000a0ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_MEM_DP ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000020000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DATA_FROM_L2 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000800ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU0_FSQRT_FDIV ] = {
+ 0x0000000000000000ULL,
+ 0x0080000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_FXU_SOPS ] = {
+ 0x0000040000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_FPU0_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000800100000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L2SB_LD_MISS_DATA ] = {
+ 0x0000000000000000ULL,
+ 0x0000020000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_SRQ_EMPTY_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000001ULL,
+ 0x0010000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_1PLUS_PPC_DISP ] = {
+ 0x0000000000100000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_VMX_ST_ISSUED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000001800000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_L2MISS ] = {
+ 0x0000000000000080ULL,
+ 0x0000100000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU0_REJECT_ULD ] = {
+ 0x8000000000000000ULL,
+ 0x0000000000000002ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_SUSPENDED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000010ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DFU_ADD_SHIFTED_BOTH ] = {
+ 0x0000000000000000ULL,
+ 0x0000000002000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU_REJECT_NO_SCRATCH ] = {
+ 0x2000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_STCX_FAIL ] = {
+ 0x0018000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU1_DENORM ] = {
+ 0x0000000000000000ULL,
+ 0x1000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_GCT_NOSLOT_COUNT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0008010000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_DL2L3_SHR_CYC ] = {
+ 0x0000000000008000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_L21 ] = {
+ 0x0000000000080080ULL,
+ 0x0000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FPU_1FLOP ] = {
+ 0x0000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x0400000000000000ULL,
+ 0x0000000000000002ULL
+ },
+ [ POWER6_PME_PM_LSU1_REJECT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000044ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_IC_REQ ] = {
+ 0x0004000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DFU_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000200000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_NOT_LLA_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_INST_FROM_L1 ] = {
+ 0x0000000000000000ULL,
+ 0x0000001000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_VMX_COMPLEX_ISSUED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_BRU_FIN ] = {
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU1_REJECT_EXTERN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000008ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_L21_CYC ] = {
+ 0x0000000000080000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_GXI_CYC_BUSY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000e00000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_LD_MISS_L1 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000200ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_L1_WRITE_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000001000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LLA_CYC ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000080000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DATA_FROM_L2MISS ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000001000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_GCT_FULL_COUNT ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000410000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MEM_DP_RQ_LOC_GLOB ] = {
+ 0x0000000000000000ULL,
+ 0x0000000040000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DATA_FROM_RL2L3_SHR ] = {
+ 0x0000000000000400ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_LSU_REJECT_UST ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000010000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_VMX_PERMUTE_ISSUED ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000100000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_PTEG_FROM_L21 ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000008000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = {
+ 0x0020000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_BR_MPRED ] = {
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LD_REQ_L2 ] = {
+ 0x0000000000000000ULL,
+ 0x0000010000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_FLUSH_ASYNC ] = {
+ 0x0002000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_HV_CYC ] = {
+ 0x0040000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0001000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU1_DERAT_MISS ] = {
+ 0x0000000000000000ULL,
+ 0x00000000000000a0ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_DPU_HELD_SMT ] = {
+ 0x0000001000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_LSU_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000001000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DATA_FROM_RL2L3_SHR ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x000000000000c000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_LSU0_REJECT_STQ_FULL ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000040ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_MRK_DERAT_REF_4K ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000001000000000ULL,
+ 0x0000000000000010ULL
+ },
+ [ POWER6_PME_PM_FPU_ISSUE_STALL_FPR ] = {
+ 0x0000000000000000ULL,
+ 0x0040000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_IFU_FIN ] = {
+ 0x0000000000000000ULL,
+ 0x0000000000080000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ },
+ [ POWER6_PME_PM_GXO_CYC_BUSY ] = {
+ 0x0000000000000000ULL,
+ 0x0000000e00000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL
+ }
+};
+
+static const pme_power_entry_t power6_pe[] = {
[ POWER6_PME_PM_LSU_REJECT_STQ_FULL ] = {
.pme_name = "PM_LSU_REJECT_STQ_FULL",
+ .pme_code = 0x1a0030,
.pme_short_desc = "LSU reject due to store queue full",
.pme_long_desc = "LSU reject due to store queue full",
- .pme_event_ids = { 243, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x2000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_STQ_FULL],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_STQ_FULL]
},
-#define POWER6_PME_PM_DPU_HELD_FXU_MULTI 1
[ POWER6_PME_PM_DPU_HELD_FXU_MULTI ] = {
.pme_name = "PM_DPU_HELD_FXU_MULTI",
+ .pme_code = 0x210a6,
.pme_short_desc = "DISP unit held due to FXU multicycle",
.pme_long_desc = "DISP unit held due to FXU multicycle",
- .pme_event_ids = { 37, 45, 36, 44, -1, -1 },
- .pme_group_vector = {
- 0x0000008000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_FXU_MULTI],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_FXU_MULTI]
},
-#define POWER6_PME_PM_VMX1_STALL 2
[ POWER6_PME_PM_VMX1_STALL ] = {
.pme_name = "PM_VMX1_STALL",
+ .pme_code = 0xb008c,
.pme_short_desc = "VMX1 stall",
.pme_long_desc = "VMX1 stall",
- .pme_event_ids = { 328, 335, 322, 320, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000001000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX1_STALL],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX1_STALL]
},
-#define POWER6_PME_PM_PMC2_SAVED 3
[ POWER6_PME_PM_PMC2_SAVED ] = {
.pme_name = "PM_PMC2_SAVED",
+ .pme_code = 0x100022,
.pme_short_desc = "PMC2 rewind value saved",
.pme_long_desc = "PMC2 rewind value saved",
- .pme_event_ids = { 291, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PMC2_SAVED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PMC2_SAVED]
},
-#define POWER6_PME_PM_L2SB_IC_INV 4
[ POWER6_PME_PM_L2SB_IC_INV ] = {
.pme_name = "PM_L2SB_IC_INV",
+ .pme_code = 0x5068c,
.pme_short_desc = "L2 slice B I cache invalidate",
.pme_long_desc = "L2 slice B I cache invalidate",
- .pme_event_ids = { 174, 183, 174, 180, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000400000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_IC_INV],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_IC_INV]
},
-#define POWER6_PME_PM_IERAT_MISS_64K 5
[ POWER6_PME_PM_IERAT_MISS_64K ] = {
.pme_name = "PM_IERAT_MISS_64K",
+ .pme_code = 0x392076,
.pme_short_desc = "IERAT misses for 64K page",
.pme_long_desc = "IERAT misses for 64K page",
- .pme_event_ids = { -1, -1, 344, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000100ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_IERAT_MISS_64K],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IERAT_MISS_64K]
},
-#define POWER6_PME_PM_THRD_PRIO_DIFF_3or4_CYC 6
[ POWER6_PME_PM_THRD_PRIO_DIFF_3or4_CYC ] = {
.pme_name = "PM_THRD_PRIO_DIFF_3or4_CYC",
+ .pme_code = 0x323040,
.pme_short_desc = "Cycles thread priority difference is 3 or 4",
.pme_long_desc = "Cycles thread priority difference is 3 or 4",
- .pme_event_ids = { -1, -1, 310, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000010000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_DIFF_3or4_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_DIFF_3or4_CYC]
},
-#define POWER6_PME_PM_LD_REF_L1_BOTH 7
[ POWER6_PME_PM_LD_REF_L1_BOTH ] = {
.pme_name = "PM_LD_REF_L1_BOTH",
+ .pme_code = 0x180036,
.pme_short_desc = "Both units L1 D cache load reference",
.pme_long_desc = "Both units L1 D cache load reference",
- .pme_event_ids = { 202, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000400000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LD_REF_L1_BOTH],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LD_REF_L1_BOTH]
},
-#define POWER6_PME_PM_FPU1_FCONV 8
[ POWER6_PME_PM_FPU1_FCONV ] = {
.pme_name = "PM_FPU1_FCONV",
+ .pme_code = 0xd10a8,
.pme_short_desc = "FPU1 executed FCONV instruction",
.pme_long_desc = "FPU1 executed FCONV instruction",
- .pme_event_ids = { 88, 97, 86, 94, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x4000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_FCONV],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_FCONV]
},
-#define POWER6_PME_PM_IBUF_FULL_COUNT 9
[ POWER6_PME_PM_IBUF_FULL_COUNT ] = {
.pme_name = "PM_IBUF_FULL_COUNT",
+ .pme_code = 0x40085,
.pme_short_desc = "Periods instruction buffer full",
.pme_long_desc = "Periods instruction buffer full",
- .pme_event_ids = { 338, 345, 332, 330, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000100000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_IBUF_FULL_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IBUF_FULL_COUNT]
},
-#define POWER6_PME_PM_MRK_LSU_DERAT_MISS 10
[ POWER6_PME_PM_MRK_LSU_DERAT_MISS ] = {
.pme_name = "PM_MRK_LSU_DERAT_MISS",
+ .pme_code = 0x400012,
.pme_short_desc = "Marked DERAT miss",
.pme_long_desc = "Marked DERAT miss",
- .pme_event_ids = { -1, -1, -1, 271, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000800000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU_DERAT_MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU_DERAT_MISS]
},
-#define POWER6_PME_PM_MRK_ST_CMPL 11
[ POWER6_PME_PM_MRK_ST_CMPL ] = {
.pme_name = "PM_MRK_ST_CMPL",
+ .pme_code = 0x100006,
.pme_short_desc = "Marked store instruction completed",
.pme_long_desc = "A sampled store has completed (data home)",
- .pme_event_ids = { 282, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000002000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_ST_CMPL],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_ST_CMPL]
},
-#define POWER6_PME_PM_L2_CASTOUT_MOD 12
[ POWER6_PME_PM_L2_CASTOUT_MOD ] = {
.pme_name = "PM_L2_CASTOUT_MOD",
+ .pme_code = 0x150630,
.pme_short_desc = "L2 castouts - Modified (M",
.pme_long_desc = " Mu",
- .pme_event_ids = { 185, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000008000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2_CASTOUT_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2_CASTOUT_MOD]
},
-#define POWER6_PME_PM_FPU1_ST_FOLDED 13
[ POWER6_PME_PM_FPU1_ST_FOLDED ] = {
.pme_name = "PM_FPU1_ST_FOLDED",
+ .pme_code = 0xd10ac,
.pme_short_desc = "FPU1 folded store",
.pme_long_desc = "FPU1 folded store",
- .pme_event_ids = { 100, 109, 98, 106, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x4000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_ST_FOLDED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_ST_FOLDED]
},
-#define POWER6_PME_PM_MRK_INST_TIMEO 14
[ POWER6_PME_PM_MRK_INST_TIMEO ] = {
.pme_name = "PM_MRK_INST_TIMEO",
+ .pme_code = 0x40003e,
.pme_short_desc = "Marked Instruction finish timeout ",
.pme_long_desc = "Marked Instruction finish timeout ",
- .pme_event_ids = { -1, -1, -1, 263, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000400000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_INST_TIMEO],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_INST_TIMEO]
},
-#define POWER6_PME_PM_DPU_WT 15
[ POWER6_PME_PM_DPU_WT ] = {
.pme_name = "PM_DPU_WT",
+ .pme_code = 0x300004,
.pme_short_desc = "Cycles DISP unit is stalled waiting for instructions",
.pme_long_desc = "Cycles DISP unit is stalled waiting for instructions",
- .pme_event_ids = { -1, -1, 54, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL,
- 0x0000000000000000ULL,
- 0x0004000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_WT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_WT]
},
-#define POWER6_PME_PM_DPU_HELD_RESTART 16
[ POWER6_PME_PM_DPU_HELD_RESTART ] = {
.pme_name = "PM_DPU_HELD_RESTART",
+ .pme_code = 0x30086,
.pme_short_desc = "DISP unit held after restart coming",
.pme_long_desc = "DISP unit held after restart coming",
- .pme_event_ids = { 47, 56, 46, 54, -1, -1 },
- .pme_group_vector = {
- 0x0000020000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_RESTART],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_RESTART]
},
-#define POWER6_PME_PM_IERAT_MISS 17
[ POWER6_PME_PM_IERAT_MISS ] = {
.pme_name = "PM_IERAT_MISS",
+ .pme_code = 0x420ce,
.pme_short_desc = "IERAT miss count",
.pme_long_desc = "IERAT miss count",
- .pme_event_ids = { 137, 146, 136, 143, -1, -1 },
- .pme_group_vector = {
- 0x0400000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_IERAT_MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IERAT_MISS]
},
-#define POWER6_PME_PM_FPU_SINGLE 18
[ POWER6_PME_PM_FPU_SINGLE ] = {
.pme_name = "PM_FPU_SINGLE",
+ .pme_code = 0x4c1030,
.pme_short_desc = "FPU executed single precision instruction",
.pme_long_desc = "FPU is executing single precision instruction. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, -1, 122, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000002ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_SINGLE],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_SINGLE]
},
-#define POWER6_PME_PM_MRK_PTEG_FROM_LMEM 19
[ POWER6_PME_PM_MRK_PTEG_FROM_LMEM ] = {
.pme_name = "PM_MRK_PTEG_FROM_LMEM",
+ .pme_code = 0x412042,
.pme_short_desc = "Marked PTEG loaded from local memory",
.pme_long_desc = "Marked PTEG loaded from local memory",
- .pme_event_ids = { -1, -1, -1, 278, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000040000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_LMEM],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_LMEM]
},
-#define POWER6_PME_PM_HV_COUNT 20
[ POWER6_PME_PM_HV_COUNT ] = {
.pme_name = "PM_HV_COUNT",
+ .pme_code = 0x200017,
.pme_short_desc = "Hypervisor Periods",
.pme_long_desc = "Periods when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)",
- .pme_event_ids = { -1, 351, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000800000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_HV_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_HV_COUNT]
},
-#define POWER6_PME_PM_L2SA_ST_HIT 21
[ POWER6_PME_PM_L2SA_ST_HIT ] = {
.pme_name = "PM_L2SA_ST_HIT",
+ .pme_code = 0x50786,
.pme_short_desc = "L2 slice A store hits",
.pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A,B, and C.",
- .pme_event_ids = { 168, 177, 168, 174, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0001000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_ST_HIT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_ST_HIT]
},
-#define POWER6_PME_PM_L2_LD_MISS_INST 22
[ POWER6_PME_PM_L2_LD_MISS_INST ] = {
.pme_name = "PM_L2_LD_MISS_INST",
+ .pme_code = 0x250530,
.pme_short_desc = "L2 instruction load misses",
.pme_long_desc = "L2 instruction load misses",
- .pme_event_ids = { -1, 196, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000004000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2_LD_MISS_INST],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2_LD_MISS_INST]
},
-#define POWER6_PME_PM_EXT_INT 23
[ POWER6_PME_PM_EXT_INT ] = {
.pme_name = "PM_EXT_INT",
+ .pme_code = 0x2000f8,
.pme_short_desc = "External interrupts",
.pme_long_desc = "An external interrupt occurred",
- .pme_event_ids = { -1, 67, 57, -1, -1, -1 },
- .pme_group_vector = {
- 0x0080000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_EXT_INT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_EXT_INT]
},
-#define POWER6_PME_PM_LSU1_LDF 24
[ POWER6_PME_PM_LSU1_LDF ] = {
.pme_name = "PM_LSU1_LDF",
+ .pme_code = 0x8008c,
.pme_short_desc = "LSU1 executed Floating Point load instruction",
.pme_long_desc = "A floating point load was executed from LSU unit 1",
- .pme_event_ids = { 221, 230, 216, 221, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000100ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_LDF],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_LDF]
},
-#define POWER6_PME_PM_FAB_CMD_ISSUED 25
[ POWER6_PME_PM_FAB_CMD_ISSUED ] = {
.pme_name = "PM_FAB_CMD_ISSUED",
+ .pme_code = 0x150130,
.pme_short_desc = "Fabric command issued",
.pme_long_desc = "Fabric command issued",
- .pme_event_ids = { 59, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000028000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FAB_CMD_ISSUED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FAB_CMD_ISSUED]
},
-#define POWER6_PME_PM_PTEG_FROM_L21 26
[ POWER6_PME_PM_PTEG_FROM_L21 ] = {
.pme_name = "PM_PTEG_FROM_L21",
+ .pme_code = 0x213048,
.pme_short_desc = "PTEG loaded from private L2 other core",
.pme_long_desc = "PTEG loaded from private L2 other core",
- .pme_event_ids = { -1, 305, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000018000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_L21],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_L21]
},
-#define POWER6_PME_PM_L2SA_MISS 27
[ POWER6_PME_PM_L2SA_MISS ] = {
.pme_name = "PM_L2SA_MISS",
+ .pme_code = 0x50584,
.pme_short_desc = "L2 slice A misses",
.pme_long_desc = "L2 slice A misses",
- .pme_event_ids = { 167, 176, 167, 173, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000100000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_MISS]
},
-#define POWER6_PME_PM_PTEG_FROM_RL2L3_MOD 28
[ POWER6_PME_PM_PTEG_FROM_RL2L3_MOD ] = {
.pme_name = "PM_PTEG_FROM_RL2L3_MOD",
+ .pme_code = 0x11304c,
.pme_short_desc = "PTEG loaded from remote L2 or L3 modified",
.pme_long_desc = "PTEG loaded from remote L2 or L3 modified",
- .pme_event_ids = { 299, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000080000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_RL2L3_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_RL2L3_MOD]
},
-#define POWER6_PME_PM_DPU_WT_COUNT 29
[ POWER6_PME_PM_DPU_WT_COUNT ] = {
.pme_name = "PM_DPU_WT_COUNT",
+ .pme_code = 0x300005,
.pme_short_desc = "Periods DISP unit is stalled waiting for instructions",
.pme_long_desc = "Periods DISP unit is stalled waiting for instructions",
- .pme_event_ids = { -1, -1, 340, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0002040000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_WT_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_WT_COUNT]
},
-#define POWER6_PME_PM_MRK_PTEG_FROM_L25_MOD 30
[ POWER6_PME_PM_MRK_PTEG_FROM_L25_MOD ] = {
.pme_name = "PM_MRK_PTEG_FROM_L25_MOD",
+ .pme_code = 0x312046,
.pme_short_desc = "Marked PTEG loaded from L2.5 modified",
.pme_long_desc = "Marked PTEG loaded from L2.5 modified",
- .pme_event_ids = { -1, -1, 272, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000008000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_L25_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_L25_MOD]
},
-#define POWER6_PME_PM_LD_HIT_L2 31
[ POWER6_PME_PM_LD_HIT_L2 ] = {
.pme_name = "PM_LD_HIT_L2",
+ .pme_code = 0x250730,
.pme_short_desc = "L2 D cache load hits",
.pme_long_desc = "L2 D cache load hits",
- .pme_event_ids = { -1, 209, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000010000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LD_HIT_L2],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LD_HIT_L2]
},
-#define POWER6_PME_PM_PTEG_FROM_DL2L3_SHR 32
[ POWER6_PME_PM_PTEG_FROM_DL2L3_SHR ] = {
.pme_name = "PM_PTEG_FROM_DL2L3_SHR",
+ .pme_code = 0x31304c,
.pme_short_desc = "PTEG loaded from distant L2 or L3 shared",
.pme_long_desc = "PTEG loaded from distant L2 or L3 shared",
- .pme_event_ids = { -1, -1, 290, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000080000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_DL2L3_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_DL2L3_SHR]
},
-#define POWER6_PME_PM_MEM_DP_RQ_GLOB_LOC 33
[ POWER6_PME_PM_MEM_DP_RQ_GLOB_LOC ] = {
.pme_name = "PM_MEM_DP_RQ_GLOB_LOC",
+ .pme_code = 0x150230,
.pme_short_desc = "Memory read queue marking cache line double pump state from global to local",
.pme_long_desc = "Memory read queue marking cache line double pump state from global to local",
- .pme_event_ids = { 257, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000040000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM_DP_RQ_GLOB_LOC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM_DP_RQ_GLOB_LOC]
},
-#define POWER6_PME_PM_L3SA_MISS 34
[ POWER6_PME_PM_L3SA_MISS ] = {
.pme_name = "PM_L3SA_MISS",
+ .pme_code = 0x50084,
.pme_short_desc = "L3 slice A misses",
.pme_long_desc = "L3 slice A misses",
- .pme_event_ids = { 192, 202, 190, 195, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0004000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L3SA_MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L3SA_MISS]
},
-#define POWER6_PME_PM_NO_ITAG_COUNT 35
[ POWER6_PME_PM_NO_ITAG_COUNT ] = {
.pme_name = "PM_NO_ITAG_COUNT",
+ .pme_code = 0x40089,
.pme_short_desc = "Periods no ITAG available",
.pme_long_desc = "Periods no ITAG available",
- .pme_event_ids = { 340, 347, 334, 332, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000400000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_NO_ITAG_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_NO_ITAG_COUNT]
},
-#define POWER6_PME_PM_DSLB_MISS 36
[ POWER6_PME_PM_DSLB_MISS ] = {
.pme_name = "PM_DSLB_MISS",
+ .pme_code = 0x830e8,
.pme_short_desc = "Data SLB misses",
.pme_long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve",
- .pme_event_ids = { 56, 65, 55, 63, -1, -1 },
- .pme_group_vector = {
- 0x0600000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DSLB_MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DSLB_MISS]
},
-#define POWER6_PME_PM_LSU_FLUSH_ALIGN 37
[ POWER6_PME_PM_LSU_FLUSH_ALIGN ] = {
.pme_name = "PM_LSU_FLUSH_ALIGN",
+ .pme_code = 0x220cc,
.pme_short_desc = "Flush caused by alignement exception",
.pme_long_desc = "Flush caused by alignement exception",
- .pme_event_ids = { 235, 244, 229, 235, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000800ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_FLUSH_ALIGN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_FLUSH_ALIGN]
},
-#define POWER6_PME_PM_DPU_HELD_FPU_CR 38
[ POWER6_PME_PM_DPU_HELD_FPU_CR ] = {
.pme_name = "PM_DPU_HELD_FPU_CR",
+ .pme_code = 0x210a0,
.pme_short_desc = "DISP unit held due to FPU updating CR",
.pme_long_desc = "DISP unit held due to FPU updating CR",
- .pme_event_ids = { 35, 43, 34, 42, -1, -1 },
- .pme_group_vector = {
- 0x0000188000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_FPU_CR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_FPU_CR]
},
-#define POWER6_PME_PM_PTEG_FROM_L2MISS 39
[ POWER6_PME_PM_PTEG_FROM_L2MISS ] = {
.pme_name = "PM_PTEG_FROM_L2MISS",
+ .pme_code = 0x113028,
.pme_short_desc = "PTEG loaded from L2 miss",
.pme_long_desc = "PTEG loaded from L2 miss",
- .pme_event_ids = { 296, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000010000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_L2MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_L2MISS]
},
-#define POWER6_PME_PM_MRK_DATA_FROM_DMEM 40
[ POWER6_PME_PM_MRK_DATA_FROM_DMEM ] = {
.pme_name = "PM_MRK_DATA_FROM_DMEM",
+ .pme_code = 0x20304a,
.pme_short_desc = "Marked data loaded from distant memory",
.pme_long_desc = "Marked data loaded from distant memory",
- .pme_event_ids = { -1, 269, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000400ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_VMX_COMPLEX_ISUED 41
- [ POWER6_PME_PM_VMX_COMPLEX_ISUED ] = {
- .pme_name = "PM_VMX_COMPLEX_ISUED",
- .pme_short_desc = "VMX instruction issued to complex",
- .pme_long_desc = "VMX instruction issued to complex",
- .pme_event_ids = { 329, 336, 323, 321, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000100000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_PTEG_FROM_LMEM 42
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_DMEM],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_DMEM]
+ },
[ POWER6_PME_PM_PTEG_FROM_LMEM ] = {
.pme_name = "PM_PTEG_FROM_LMEM",
+ .pme_code = 0x41304a,
.pme_short_desc = "PTEG loaded from local memory",
.pme_long_desc = "PTEG loaded from local memory",
- .pme_event_ids = { -1, -1, -1, 291, -1, -1 },
- .pme_group_vector = {
- 0x0000000060000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_MRK_DERAT_REF_64K 43
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_LMEM],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_LMEM]
+ },
[ POWER6_PME_PM_MRK_DERAT_REF_64K ] = {
.pme_name = "PM_MRK_DERAT_REF_64K",
+ .pme_code = 0x182044,
.pme_short_desc = "Marked DERAT reference for 64K page",
.pme_long_desc = "Marked DERAT reference for 64K page",
- .pme_event_ids = { 353, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000001000000000ULL,
- 0x0000000000000010ULL }
- },
-#define POWER6_PME_PM_L2SA_LD_REQ_INST 44
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DERAT_REF_64K],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DERAT_REF_64K]
+ },
[ POWER6_PME_PM_L2SA_LD_REQ_INST ] = {
.pme_name = "PM_L2SA_LD_REQ_INST",
+ .pme_code = 0x50580,
.pme_short_desc = "L2 slice A instruction load requests",
.pme_long_desc = "L2 slice A instruction load requests",
- .pme_event_ids = { 166, 175, 166, 172, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000040000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_MRK_DERAT_MISS_16M 45
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_LD_REQ_INST],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_LD_REQ_INST]
+ },
[ POWER6_PME_PM_MRK_DERAT_MISS_16M ] = {
.pme_name = "PM_MRK_DERAT_MISS_16M",
+ .pme_code = 0x392044,
.pme_short_desc = "Marked DERAT misses for 16M page",
.pme_long_desc = "A marked data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.",
- .pme_event_ids = { -1, -1, 346, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000002000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_DATA_FROM_DL2L3_MOD 46
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DERAT_MISS_16M],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DERAT_MISS_16M]
+ },
[ POWER6_PME_PM_DATA_FROM_DL2L3_MOD ] = {
.pme_name = "PM_DATA_FROM_DL2L3_MOD",
+ .pme_code = 0x40005c,
.pme_short_desc = "Data loaded from distant L2 or L3 modified",
.pme_long_desc = "Data loaded from distant L2 or L3 modified",
- .pme_event_ids = { -1, -1, -1, 13, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000400ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_FPU0_FXMULT 47
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_DL2L3_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_DL2L3_MOD]
+ },
[ POWER6_PME_PM_FPU0_FXMULT ] = {
.pme_name = "PM_FPU0_FXMULT",
+ .pme_code = 0xd0086,
.pme_short_desc = "FPU0 executed fixed point multiplication",
.pme_long_desc = "FPU0 executed fixed point multiplication",
- .pme_event_ids = { 82, 91, 80, 88, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0200000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_L3SB_MISS 48
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_FXMULT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_FXMULT]
+ },
[ POWER6_PME_PM_L3SB_MISS ] = {
.pme_name = "PM_L3SB_MISS",
+ .pme_code = 0x5008c,
.pme_short_desc = "L3 slice B misses",
.pme_long_desc = "L3 slice B misses",
- .pme_event_ids = { 195, 205, 193, 198, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0008000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_STCX_CANCEL 49
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L3SB_MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L3SB_MISS]
+ },
[ POWER6_PME_PM_STCX_CANCEL ] = {
.pme_name = "PM_STCX_CANCEL",
+ .pme_code = 0x830ec,
.pme_short_desc = "stcx cancel by core",
.pme_long_desc = "stcx cancel by core",
- .pme_event_ids = { 305, 311, 297, 296, -1, -1 },
- .pme_group_vector = {
- 0x0008000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_L2SA_LD_MISS_DATA 50
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_STCX_CANCEL],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_STCX_CANCEL]
+ },
[ POWER6_PME_PM_L2SA_LD_MISS_DATA ] = {
.pme_name = "PM_L2SA_LD_MISS_DATA",
+ .pme_code = 0x50482,
.pme_short_desc = "L2 slice A data load misses",
.pme_long_desc = "L2 slice A data load misses",
- .pme_event_ids = { 162, 171, 162, 168, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000020000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_IC_INV_L2 51
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_LD_MISS_DATA],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_LD_MISS_DATA]
+ },
[ POWER6_PME_PM_IC_INV_L2 ] = {
.pme_name = "PM_IC_INV_L2",
+ .pme_code = 0x250632,
.pme_short_desc = "L1 I cache entries invalidated from L2",
.pme_long_desc = "L1 I cache entries invalidated from L2",
- .pme_event_ids = { -1, 141, 131, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000008000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_DPU_HELD 52
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_IC_INV_L2],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IC_INV_L2]
+ },
[ POWER6_PME_PM_DPU_HELD ] = {
.pme_name = "PM_DPU_HELD",
+ .pme_code = 0x200004,
.pme_short_desc = "DISP unit held",
.pme_long_desc = "DISP unit held",
- .pme_event_ids = { -1, 38, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000002000000000ULL,
- 0x0000000000000000ULL,
- 0x0004000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_PMC1_OVERFLOW 53
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD]
+ },
[ POWER6_PME_PM_PMC1_OVERFLOW ] = {
.pme_name = "PM_PMC1_OVERFLOW",
+ .pme_code = 0x200014,
.pme_short_desc = "PMC1 Overflow",
.pme_long_desc = "PMC1 Overflow",
- .pme_event_ids = { -1, 303, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_THRD_PRIO_6_CYC 54
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PMC1_OVERFLOW],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PMC1_OVERFLOW]
+ },
[ POWER6_PME_PM_THRD_PRIO_6_CYC ] = {
.pme_name = "PM_THRD_PRIO_6_CYC",
+ .pme_code = 0x222046,
.pme_short_desc = "Cycles thread running at priority level 6",
.pme_long_desc = "Cycles thread running at priority level 6",
- .pme_event_ids = { -1, 323, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000008000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_MRK_PTEG_FROM_L3MISS 55
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_6_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_6_CYC]
+ },
[ POWER6_PME_PM_MRK_PTEG_FROM_L3MISS ] = {
.pme_name = "PM_MRK_PTEG_FROM_L3MISS",
+ .pme_code = 0x312054,
.pme_short_desc = "Marked PTEG loaded from L3 miss",
.pme_long_desc = "Marked PTEG loaded from L3 miss",
- .pme_event_ids = { -1, -1, 274, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000040000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_MRK_LSU0_REJECT_UST 56
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_L3MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_L3MISS]
+ },
[ POWER6_PME_PM_MRK_LSU0_REJECT_UST ] = {
.pme_name = "PM_MRK_LSU0_REJECT_UST",
+ .pme_code = 0x930e2,
.pme_short_desc = "LSU0 marked unaligned store reject",
.pme_long_desc = "LSU0 marked unaligned store reject",
- .pme_event_ids = { 272, 284, 266, 267, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000020000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_MRK_INST_DISP 57
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU0_REJECT_UST],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU0_REJECT_UST]
+ },
[ POWER6_PME_PM_MRK_INST_DISP ] = {
.pme_name = "PM_MRK_INST_DISP",
+ .pme_code = 0x10001a,
.pme_short_desc = "Marked instruction dispatched",
.pme_long_desc = "Marked instruction dispatched",
- .pme_event_ids = { 267, 279, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000080000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_LARX 58
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_INST_DISP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_INST_DISP]
+ },
[ POWER6_PME_PM_LARX ] = {
.pme_name = "PM_LARX",
+ .pme_code = 0x830ea,
.pme_short_desc = "Larx executed",
.pme_long_desc = "Larx executed",
- .pme_event_ids = { 197, 207, 195, 200, -1, -1 },
- .pme_group_vector = {
- 0x0018000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_INST_CMPL 59
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LARX],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LARX]
+ },
[ POWER6_PME_PM_INST_CMPL ] = {
.pme_name = "PM_INST_CMPL",
+ .pme_code = 0x2,
.pme_short_desc = "Instructions completed",
.pme_long_desc = "Number of PPC instructions completed. ",
- .pme_event_ids = { 139, 148, 138, 145, -1, -1 },
- .pme_group_vector = {
- 0x0100000000006001ULL,
- 0x0000000000000000ULL,
- 0x3800003ffffffe18ULL,
- 0x0000000000000038ULL }
- },
-#define POWER6_PME_PM_FXU_IDLE 60
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_CMPL],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_CMPL]
+ },
[ POWER6_PME_PM_FXU_IDLE ] = {
.pme_name = "PM_FXU_IDLE",
+ .pme_code = 0x100050,
.pme_short_desc = "FXU idle",
.pme_long_desc = "FXU0 and FXU1 are both idle",
- .pme_event_ids = { 117, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000040000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_MRK_DATA_FROM_DL2L3_MOD 61
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FXU_IDLE],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FXU_IDLE]
+ },
[ POWER6_PME_PM_MRK_DATA_FROM_DL2L3_MOD ] = {
.pme_name = "PM_MRK_DATA_FROM_DL2L3_MOD",
+ .pme_code = 0x40304c,
.pme_short_desc = "Marked data loaded from distant L2 or L3 modified",
.pme_long_desc = "Marked data loaded from distant L2 or L3 modified",
- .pme_event_ids = { -1, -1, -1, 256, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000400ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_L2_LD_REQ_DATA 62
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_DL2L3_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_DL2L3_MOD]
+ },
[ POWER6_PME_PM_L2_LD_REQ_DATA ] = {
.pme_name = "PM_L2_LD_REQ_DATA",
+ .pme_code = 0x150430,
.pme_short_desc = "L2 data load requests",
.pme_long_desc = "L2 data load requests",
- .pme_event_ids = { 186, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000002000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_LSU_DERAT_MISS_CYC 63
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2_LD_REQ_DATA],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2_LD_REQ_DATA]
+ },
[ POWER6_PME_PM_LSU_DERAT_MISS_CYC ] = {
.pme_name = "PM_LSU_DERAT_MISS_CYC",
+ .pme_code = 0x1000fc,
.pme_short_desc = "DERAT miss latency",
.pme_long_desc = "DERAT miss latency",
- .pme_event_ids = { 234, -1, -1, 234, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000800ULL,
- 0x0040000000000020ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_DPU_HELD_POWER_COUNT 64
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_DERAT_MISS_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_DERAT_MISS_CYC]
+ },
[ POWER6_PME_PM_DPU_HELD_POWER_COUNT ] = {
.pme_name = "PM_DPU_HELD_POWER_COUNT",
+ .pme_code = 0x20003d,
.pme_short_desc = "Periods DISP unit held due to Power Management",
.pme_long_desc = "Periods DISP unit held due to Power Management",
- .pme_event_ids = { -1, 356, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0100020000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_INST_FROM_RL2L3_MOD 65
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_POWER_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_POWER_COUNT]
+ },
[ POWER6_PME_PM_INST_FROM_RL2L3_MOD ] = {
.pme_name = "PM_INST_FROM_RL2L3_MOD",
+ .pme_code = 0x142044,
.pme_short_desc = "Instruction fetched from remote L2 or L3 modified",
.pme_long_desc = "Instruction fetched from remote L2 or L3 modified",
- .pme_event_ids = { 146, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000001000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_DATA_FROM_DMEM_CYC 66
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_RL2L3_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_RL2L3_MOD]
+ },
[ POWER6_PME_PM_DATA_FROM_DMEM_CYC ] = {
.pme_name = "PM_DATA_FROM_DMEM_CYC",
+ .pme_code = 0x20002e,
.pme_short_desc = "Load latency from distant memory",
.pme_long_desc = "Load latency from distant memory",
- .pme_event_ids = { -1, 14, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000004000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_DATA_FROM_DMEM 67
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_DMEM_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_DMEM_CYC]
+ },
[ POWER6_PME_PM_DATA_FROM_DMEM ] = {
.pme_name = "PM_DATA_FROM_DMEM",
+ .pme_code = 0x20005e,
.pme_short_desc = "Data loaded from distant memory",
.pme_long_desc = "Data loaded from distant memory",
- .pme_event_ids = { -1, 13, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000800ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_LSU_REJECT_PARTIAL_SECTOR 68
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_DMEM],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_DMEM]
+ },
[ POWER6_PME_PM_LSU_REJECT_PARTIAL_SECTOR ] = {
.pme_name = "PM_LSU_REJECT_PARTIAL_SECTOR",
+ .pme_code = 0x1a0032,
.pme_short_desc = "LSU reject due to partial sector valid",
.pme_long_desc = "LSU reject due to partial sector valid",
- .pme_event_ids = { 241, -1, -1, 242, -1, -1 },
- .pme_group_vector = {
- 0x2000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_LSU_REJECT_DERAT_MPRED 69
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_PARTIAL_SECTOR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_PARTIAL_SECTOR]
+ },
[ POWER6_PME_PM_LSU_REJECT_DERAT_MPRED ] = {
.pme_name = "PM_LSU_REJECT_DERAT_MPRED",
+ .pme_code = 0x2a0030,
.pme_short_desc = "LSU reject due to mispredicted DERAT",
.pme_long_desc = "LSU reject due to mispredicted DERAT",
- .pme_event_ids = { -1, 249, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0800000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_LSU1_REJECT_ULD 70
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_DERAT_MPRED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_DERAT_MPRED]
+ },
[ POWER6_PME_PM_LSU1_REJECT_ULD ] = {
.pme_name = "PM_LSU1_REJECT_ULD",
+ .pme_code = 0x90088,
.pme_short_desc = "LSU1 unaligned load reject",
.pme_long_desc = "LSU1 unaligned load reject",
- .pme_event_ids = { 231, 240, 226, 231, -1, -1 },
- .pme_group_vector = {
- 0x8000000000000000ULL,
- 0x0000000000000002ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_DATA_FROM_L3_CYC 71
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_REJECT_ULD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_REJECT_ULD]
+ },
[ POWER6_PME_PM_DATA_FROM_L3_CYC ] = {
.pme_name = "PM_DATA_FROM_L3_CYC",
+ .pme_code = 0x200022,
.pme_short_desc = "Load latency from L3",
.pme_long_desc = "Load latency from L3",
- .pme_event_ids = { -1, 21, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000010000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_FXU1_BUSY_FXU0_IDLE 72
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L3_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L3_CYC]
+ },
[ POWER6_PME_PM_FXU1_BUSY_FXU0_IDLE ] = {
.pme_name = "PM_FXU1_BUSY_FXU0_IDLE",
+ .pme_code = 0x400050,
.pme_short_desc = "FXU1 busy FXU0 idle",
.pme_long_desc = "FXU0 was idle while FXU1 was busy",
- .pme_event_ids = { -1, -1, -1, 124, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000040000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_INST_FROM_MEM_DP 73
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FXU1_BUSY_FXU0_IDLE],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FXU1_BUSY_FXU0_IDLE]
+ },
[ POWER6_PME_PM_INST_FROM_MEM_DP ] = {
.pme_name = "PM_INST_FROM_MEM_DP",
+ .pme_code = 0x142042,
.pme_short_desc = "Instruction fetched from double pump memory",
.pme_long_desc = "Instruction fetched from double pump memory",
- .pme_event_ids = { 145, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000002000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_LSU_FLUSH_DSI 74
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_MEM_DP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_MEM_DP]
+ },
[ POWER6_PME_PM_LSU_FLUSH_DSI ] = {
.pme_name = "PM_LSU_FLUSH_DSI",
+ .pme_code = 0x220ce,
.pme_short_desc = "Flush caused by DSI",
.pme_long_desc = "Flush caused by DSI",
- .pme_event_ids = { 236, 245, 230, 236, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000800ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_MRK_DERAT_REF_16G 75
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_FLUSH_DSI],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_FLUSH_DSI]
+ },
[ POWER6_PME_PM_MRK_DERAT_REF_16G ] = {
.pme_name = "PM_MRK_DERAT_REF_16G",
+ .pme_code = 0x482044,
.pme_short_desc = "Marked DERAT reference for 16G page",
.pme_long_desc = "Marked DERAT reference for 16G page",
- .pme_event_ids = { -1, -1, -1, 345, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000010ULL }
- },
-#define POWER6_PME_PM_LSU_LDF_BOTH 76
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DERAT_REF_16G],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DERAT_REF_16G]
+ },
[ POWER6_PME_PM_LSU_LDF_BOTH ] = {
.pme_name = "PM_LSU_LDF_BOTH",
+ .pme_code = 0x180038,
.pme_short_desc = "Both LSU units executed Floating Point load instruction",
.pme_long_desc = "Both LSU units executed Floating Point load instruction",
- .pme_event_ids = { 237, -1, 232, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000100ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_FPU1_1FLOP 77
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_LDF_BOTH],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_LDF_BOTH]
+ },
[ POWER6_PME_PM_FPU1_1FLOP ] = {
.pme_name = "PM_FPU1_1FLOP",
+ .pme_code = 0xc0088,
.pme_short_desc = "FPU1 executed add",
.pme_long_desc = " mult",
- .pme_event_ids = { 86, 95, 84, 92, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0800000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_DATA_FROM_RMEM_CYC 78
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_1FLOP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_1FLOP]
+ },
[ POWER6_PME_PM_DATA_FROM_RMEM_CYC ] = {
.pme_name = "PM_DATA_FROM_RMEM_CYC",
+ .pme_code = 0x40002c,
.pme_short_desc = "Load latency from remote memory",
.pme_long_desc = "Load latency from remote memory",
- .pme_event_ids = { -1, -1, -1, 23, -1, -1 },
- .pme_group_vector = {
- 0x0000000000004000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_INST_PTEG_SECONDARY 79
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_RMEM_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_RMEM_CYC]
+ },
[ POWER6_PME_PM_INST_PTEG_SECONDARY ] = {
.pme_name = "PM_INST_PTEG_SECONDARY",
+ .pme_code = 0x910ac,
.pme_short_desc = "Instruction table walk matched in secondary PTEG",
.pme_long_desc = "Instruction table walk matched in secondary PTEG",
- .pme_event_ids = { 150, 159, 150, 156, -1, -1 },
- .pme_group_vector = {
- 0x0000000200000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_L1_ICACHE_MISS 80
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_PTEG_SECONDARY],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_PTEG_SECONDARY]
+ },
[ POWER6_PME_PM_L1_ICACHE_MISS ] = {
.pme_name = "PM_L1_ICACHE_MISS",
+ .pme_code = 0x100056,
.pme_short_desc = "L1 I cache miss count",
.pme_long_desc = "L1 I cache miss count",
- .pme_event_ids = { 154, 163, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL,
- 0x0000000000000000ULL,
- 0x0000040000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_INST_DISP_LLA 81
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L1_ICACHE_MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L1_ICACHE_MISS]
+ },
[ POWER6_PME_PM_INST_DISP_LLA ] = {
.pme_name = "PM_INST_DISP_LLA",
+ .pme_code = 0x310a2,
.pme_short_desc = "Instruction dispatched under load look ahead",
.pme_long_desc = "Instruction dispatched under load look ahead",
- .pme_event_ids = { 140, 150, 140, 146, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000001000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_THRD_BOTH_RUN_CYC 82
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_DISP_LLA],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_DISP_LLA]
+ },
[ POWER6_PME_PM_THRD_BOTH_RUN_CYC ] = {
.pme_name = "PM_THRD_BOTH_RUN_CYC",
+ .pme_code = 0x400004,
.pme_short_desc = "Both threads in run cycles",
.pme_long_desc = "Both threads in run cycles",
- .pme_event_ids = { -1, -1, -1, 304, -1, -1 },
- .pme_group_vector = {
- 0x0020000000000000ULL,
- 0x0000000000000000ULL,
- 0x0200000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_LSU_ST_CHAINED 83
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_BOTH_RUN_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_BOTH_RUN_CYC]
+ },
[ POWER6_PME_PM_LSU_ST_CHAINED ] = {
.pme_name = "PM_LSU_ST_CHAINED",
+ .pme_code = 0x820ce,
.pme_short_desc = "number of chained stores",
.pme_long_desc = "number of chained stores",
- .pme_event_ids = { 246, 257, 240, 245, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000200ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_FPU1_FXDIV 84
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_ST_CHAINED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_ST_CHAINED]
+ },
[ POWER6_PME_PM_FPU1_FXDIV ] = {
.pme_name = "PM_FPU1_FXDIV",
+ .pme_code = 0xc10a8,
.pme_short_desc = "FPU1 executed fixed point division",
.pme_long_desc = "FPU1 executed fixed point division",
- .pme_event_ids = { 96, 105, 94, 102, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x1000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_FREQ_UP 85
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_FXDIV],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_FXDIV]
+ },
[ POWER6_PME_PM_FREQ_UP ] = {
.pme_name = "PM_FREQ_UP",
+ .pme_code = 0x40003c,
.pme_short_desc = "Frequency is being slewed up due to Power Management",
.pme_long_desc = "Frequency is being slewed up due to Power Management",
- .pme_event_ids = { -1, -1, -1, 123, -1, -1 },
- .pme_group_vector = {
- 0x0000000400000000ULL,
- 0x0000000000000000ULL,
- 0x0000020000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_FAB_RETRY_SYS_PUMP 86
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FREQ_UP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FREQ_UP]
+ },
[ POWER6_PME_PM_FAB_RETRY_SYS_PUMP ] = {
.pme_name = "PM_FAB_RETRY_SYS_PUMP",
+ .pme_code = 0x50182,
.pme_short_desc = "Retry of a system pump",
.pme_long_desc = " locally mastered ",
- .pme_event_ids = { 65, 75, 64, 71, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000010000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_DATA_FROM_LMEM 87
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FAB_RETRY_SYS_PUMP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FAB_RETRY_SYS_PUMP]
+ },
[ POWER6_PME_PM_DATA_FROM_LMEM ] = {
.pme_name = "PM_DATA_FROM_LMEM",
+ .pme_code = 0x40005e,
.pme_short_desc = "Data loaded from local memory",
.pme_long_desc = "Data loaded from local memory",
- .pme_event_ids = { -1, -1, -1, 20, -1, -1 },
- .pme_group_vector = {
- 0x0000000000100800ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_PMC3_OVERFLOW 88
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_LMEM],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_LMEM]
+ },
[ POWER6_PME_PM_PMC3_OVERFLOW ] = {
.pme_name = "PM_PMC3_OVERFLOW",
+ .pme_code = 0x400014,
.pme_short_desc = "PMC3 Overflow",
.pme_long_desc = "PMC3 Overflow",
- .pme_event_ids = { -1, -1, -1, 288, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_LSU0_REJECT_SET_MPRED 89
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PMC3_OVERFLOW],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PMC3_OVERFLOW]
+ },
[ POWER6_PME_PM_LSU0_REJECT_SET_MPRED ] = {
.pme_name = "PM_LSU0_REJECT_SET_MPRED",
+ .pme_code = 0xa0084,
.pme_short_desc = "LSU0 reject due to mispredicted set",
.pme_long_desc = "LSU0 reject due to mispredicted set",
- .pme_event_ids = { 216, 225, 211, 216, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000001ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_LSU0_REJECT_DERAT_MPRED 90
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT_SET_MPRED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT_SET_MPRED]
+ },
[ POWER6_PME_PM_LSU0_REJECT_DERAT_MPRED ] = {
.pme_name = "PM_LSU0_REJECT_DERAT_MPRED",
+ .pme_code = 0xa0082,
.pme_short_desc = "LSU0 reject due to mispredicted DERAT",
.pme_long_desc = "LSU0 reject due to mispredicted DERAT",
- .pme_event_ids = { 209, 218, 204, 209, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000084ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_LSU1_REJECT_STQ_FULL 91
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT_DERAT_MPRED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT_DERAT_MPRED]
+ },
[ POWER6_PME_PM_LSU1_REJECT_STQ_FULL ] = {
.pme_name = "PM_LSU1_REJECT_STQ_FULL",
+ .pme_code = 0xa0088,
.pme_short_desc = "LSU1 reject due to store queue full",
.pme_long_desc = "LSU1 reject due to store queue full",
- .pme_event_ids = { 230, 239, 225, 230, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000040ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_MRK_BR_MPRED 92
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_REJECT_STQ_FULL],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_REJECT_STQ_FULL]
+ },
[ POWER6_PME_PM_MRK_BR_MPRED ] = {
.pme_name = "PM_MRK_BR_MPRED",
+ .pme_code = 0x300052,
.pme_short_desc = "Marked branch mispredicted",
.pme_long_desc = "Marked branch mispredicted",
- .pme_event_ids = { -1, -1, 251, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000200ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_L2SA_ST_MISS 93
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_BR_MPRED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_BR_MPRED]
+ },
[ POWER6_PME_PM_L2SA_ST_MISS ] = {
.pme_name = "PM_L2SA_ST_MISS",
+ .pme_code = 0x50486,
.pme_short_desc = "L2 slice A store misses",
.pme_long_desc = "L2 slice A store misses",
- .pme_event_ids = { 169, 178, 169, 175, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000080000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_LSU0_REJECT_EXTERN 94
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_ST_MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_ST_MISS]
+ },
[ POWER6_PME_PM_LSU0_REJECT_EXTERN ] = {
.pme_name = "PM_LSU0_REJECT_EXTERN",
+ .pme_code = 0xa10a4,
.pme_short_desc = "LSU0 external reject request ",
.pme_long_desc = "LSU0 external reject request ",
- .pme_event_ids = { 210, 219, 205, 210, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000008ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_MRK_BR_TAKEN 95
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT_EXTERN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT_EXTERN]
+ },
[ POWER6_PME_PM_MRK_BR_TAKEN ] = {
.pme_name = "PM_MRK_BR_TAKEN",
+ .pme_code = 0x100052,
.pme_short_desc = "Marked branch taken",
.pme_long_desc = "Marked branch taken",
- .pme_event_ids = { 258, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000200ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_ISLB_MISS 96
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_BR_TAKEN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_BR_TAKEN]
+ },
[ POWER6_PME_PM_ISLB_MISS ] = {
.pme_name = "PM_ISLB_MISS",
+ .pme_code = 0x830e0,
.pme_short_desc = "Instruction SLB misses",
.pme_long_desc = "A SLB miss for an instruction fetch as occurred",
- .pme_event_ids = { 152, 161, 152, 158, -1, -1 },
- .pme_group_vector = {
- 0x0600000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_CYC 97
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_ISLB_MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_ISLB_MISS]
+ },
[ POWER6_PME_PM_CYC ] = {
.pme_name = "PM_CYC",
+ .pme_code = 0x1e,
.pme_short_desc = "Processor cycles",
.pme_long_desc = "Processor cycles",
- .pme_event_ids = { 12, 11, 10, 12, -1, -1 },
- .pme_group_vector = {
- 0x0100200000283003ULL,
- 0x0000000000000000ULL,
- 0x5c00000481000018ULL,
- 0x0000000000000005ULL }
- },
-#define POWER6_PME_PM_FPU_FXDIV 98
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_CYC]
+ },
[ POWER6_PME_PM_FPU_FXDIV ] = {
.pme_name = "PM_FPU_FXDIV",
+ .pme_code = 0x1c1034,
.pme_short_desc = "FPU executed fixed point division",
.pme_long_desc = "FPU executed fixed point division",
- .pme_event_ids = { 105, -1, -1, 110, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000002ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_DPU_HELD_LLA_END 99
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_FXDIV],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_FXDIV]
+ },
[ POWER6_PME_PM_DPU_HELD_LLA_END ] = {
.pme_name = "PM_DPU_HELD_LLA_END",
+ .pme_code = 0x30084,
.pme_short_desc = "DISP unit held due to load look ahead ended",
.pme_long_desc = "DISP unit held due to load look ahead ended",
- .pme_event_ids = { 43, 51, 42, 50, -1, -1 },
- .pme_group_vector = {
- 0x0000020000000000ULL,
- 0x0000000000001000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_MEM0_DP_CL_WR_LOC 100
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_LLA_END],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_LLA_END]
+ },
[ POWER6_PME_PM_MEM0_DP_CL_WR_LOC ] = {
.pme_name = "PM_MEM0_DP_CL_WR_LOC",
+ .pme_code = 0x50286,
.pme_short_desc = "cacheline write setting dp to local side 0",
.pme_long_desc = "cacheline write setting dp to local side 0",
- .pme_event_ids = { 249, 260, 243, 248, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000080000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_MRK_LSU_REJECT_ULD 101
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM0_DP_CL_WR_LOC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM0_DP_CL_WR_LOC]
+ },
[ POWER6_PME_PM_MRK_LSU_REJECT_ULD ] = {
.pme_name = "PM_MRK_LSU_REJECT_ULD",
+ .pme_code = 0x193034,
.pme_short_desc = "Marked unaligned load reject",
.pme_long_desc = "Marked unaligned load reject",
- .pme_event_ids = { 276, -1, -1, 274, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000210000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_1PLUS_PPC_CMPL 102
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU_REJECT_ULD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU_REJECT_ULD]
+ },
[ POWER6_PME_PM_1PLUS_PPC_CMPL ] = {
.pme_name = "PM_1PLUS_PPC_CMPL",
+ .pme_code = 0x100004,
.pme_short_desc = "One or more PPC instruction completed",
.pme_long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.",
- .pme_event_ids = { 1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0040000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_PTEG_FROM_DMEM 103
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_1PLUS_PPC_CMPL],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_1PLUS_PPC_CMPL]
+ },
[ POWER6_PME_PM_PTEG_FROM_DMEM ] = {
.pme_name = "PM_PTEG_FROM_DMEM",
+ .pme_code = 0x21304a,
.pme_short_desc = "PTEG loaded from distant memory",
.pme_long_desc = "PTEG loaded from distant memory",
- .pme_event_ids = { -1, 304, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000040000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_DPU_WT_BR_MPRED_COUNT 104
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_DMEM],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_DMEM]
+ },
[ POWER6_PME_PM_DPU_WT_BR_MPRED_COUNT ] = {
.pme_name = "PM_DPU_WT_BR_MPRED_COUNT",
+ .pme_code = 0x40000d,
.pme_short_desc = "Periods DISP unit is stalled due to branch misprediction",
.pme_long_desc = "Periods DISP unit is stalled due to branch misprediction",
- .pme_event_ids = { -1, -1, -1, 340, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0002040000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_GCT_FULL_CYC 105
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_WT_BR_MPRED_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_WT_BR_MPRED_COUNT]
+ },
[ POWER6_PME_PM_GCT_FULL_CYC ] = {
.pme_name = "PM_GCT_FULL_CYC",
+ .pme_code = 0x40086,
.pme_short_desc = "Cycles GCT full",
.pme_long_desc = "The ISU sends a signal indicating the gct is full. ",
- .pme_event_ids = { 120, 128, 119, 127, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000002000ULL,
- 0x0000400000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_INST_FROM_L25_SHR 106
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_GCT_FULL_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GCT_FULL_CYC]
+ },
[ POWER6_PME_PM_INST_FROM_L25_SHR ] = {
.pme_name = "PM_INST_FROM_L25_SHR",
+ .pme_code = 0x442046,
.pme_short_desc = "Instruction fetched from L2.5 shared",
.pme_long_desc = "Instruction fetched from L2.5 shared",
- .pme_event_ids = { -1, -1, -1, 150, -1, -1 },
- .pme_group_vector = {
- 0x0000000000800000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_MRK_DERAT_MISS_4K 107
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_L25_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_L25_SHR]
+ },
[ POWER6_PME_PM_MRK_DERAT_MISS_4K ] = {
.pme_name = "PM_MRK_DERAT_MISS_4K",
+ .pme_code = 0x292044,
.pme_short_desc = "Marked DERAT misses for 4K page",
.pme_long_desc = "A marked data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.",
- .pme_event_ids = { -1, 364, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000002000000000ULL,
- 0x0000000000000020ULL }
- },
-#define POWER6_PME_PM_DC_PREF_STREAM_ALLOC 108
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DERAT_MISS_4K],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DERAT_MISS_4K]
+ },
[ POWER6_PME_PM_DC_PREF_STREAM_ALLOC ] = {
.pme_name = "PM_DC_PREF_STREAM_ALLOC",
+ .pme_code = 0x810a2,
.pme_short_desc = "D cache new prefetch stream allocated",
.pme_long_desc = "A new Prefetch Stream was allocated",
- .pme_event_ids = { 22, 29, 21, 29, -1, -1 },
- .pme_group_vector = {
- 0x0001000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_FPU1_FIN 109
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DC_PREF_STREAM_ALLOC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DC_PREF_STREAM_ALLOC]
+ },
[ POWER6_PME_PM_FPU1_FIN ] = {
.pme_name = "PM_FPU1_FIN",
+ .pme_code = 0xd0088,
.pme_short_desc = "FPU1 produced a result",
.pme_long_desc = "fp1 finished, produced a result. This only indicates finish, not completion. ",
- .pme_event_ids = { 90, 99, 88, 96, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x2000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_BR_MPRED_TA 110
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_FIN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_FIN]
+ },
[ POWER6_PME_PM_BR_MPRED_TA ] = {
.pme_name = "PM_BR_MPRED_TA",
+ .pme_code = 0x410ac,
.pme_short_desc = "Branch mispredictions due to target address",
.pme_long_desc = "branch miss predict due to a target address prediction. This signal will be asserted each time the branch execution unit detects an incorrect target address prediction. This signal will be asserted after a valid branch execution unit issue and will cause a branch mispredict flush unless a flush is detected from an older instruction.",
- .pme_event_ids = { 7, 5, 5, 7, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000028ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_DPU_HELD_POWER 111
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_BR_MPRED_TA],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_BR_MPRED_TA]
+ },
[ POWER6_PME_PM_DPU_HELD_POWER ] = {
.pme_name = "PM_DPU_HELD_POWER",
+ .pme_code = 0x20003c,
.pme_short_desc = "DISP unit held due to Power Management",
.pme_long_desc = "DISP unit held due to Power Management",
- .pme_event_ids = { -1, 55, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000001400000000ULL,
- 0x0000000000000000ULL,
- 0x0200000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_RUN_INST_CMPL 112
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_POWER],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_POWER]
+ },
[ POWER6_PME_PM_RUN_INST_CMPL ] = {
.pme_name = "PM_RUN_INST_CMPL",
+ .pme_code = 0x500009,
.pme_short_desc = "Run instructions completed",
.pme_long_desc = "Number of run instructions completed. ",
- .pme_event_ids = { -1, -1, -1, -1, 0, -1 },
- .pme_group_vector = {
- 0xffffffffffffffffULL,
- 0xffffffffffffffffULL,
- 0xffffffffffffffffULL,
- 0x000000000000003fULL }
- },
-#define POWER6_PME_PM_GCT_EMPTY_CYC 113
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_RUN_INST_CMPL],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_RUN_INST_CMPL]
+ },
[ POWER6_PME_PM_GCT_EMPTY_CYC ] = {
.pme_name = "PM_GCT_EMPTY_CYC",
+ .pme_code = 0x1000f8,
.pme_short_desc = "Cycles GCT empty",
.pme_long_desc = "The Global Completion Table is completely empty",
- .pme_event_ids = { 119, 127, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000002000ULL,
- 0x0010000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_LLA_COUNT 114
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_GCT_EMPTY_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GCT_EMPTY_CYC]
+ },
[ POWER6_PME_PM_LLA_COUNT ] = {
.pme_name = "PM_LLA_COUNT",
+ .pme_code = 0xc01f,
.pme_short_desc = "Transitions into Load Look Ahead mode",
.pme_long_desc = "Transitions into Load Look Ahead mode",
- .pme_event_ids = { 347, 354, 339, 339, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000080000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_LSU0_REJECT_NO_SCRATCH 115
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LLA_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LLA_COUNT]
+ },
[ POWER6_PME_PM_LSU0_REJECT_NO_SCRATCH ] = {
.pme_name = "PM_LSU0_REJECT_NO_SCRATCH",
+ .pme_code = 0xa10a2,
.pme_short_desc = "LSU0 reject due to scratch register not available",
.pme_long_desc = "LSU0 reject due to scratch register not available",
- .pme_event_ids = { 214, 223, 209, 214, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000010ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_DPU_WT_IC_MISS 116
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT_NO_SCRATCH],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT_NO_SCRATCH]
+ },
[ POWER6_PME_PM_DPU_WT_IC_MISS ] = {
.pme_name = "PM_DPU_WT_IC_MISS",
+ .pme_code = 0x20000c,
.pme_short_desc = "Cycles DISP unit is stalled due to I cache miss",
.pme_long_desc = "Cycles DISP unit is stalled due to I cache miss",
- .pme_event_ids = { -1, 64, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL,
- 0x0000000000000000ULL,
- 0x0000080000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_DATA_FROM_L3MISS 117
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_WT_IC_MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_WT_IC_MISS]
+ },
[ POWER6_PME_PM_DATA_FROM_L3MISS ] = {
.pme_name = "PM_DATA_FROM_L3MISS",
+ .pme_code = 0x3000fe,
.pme_short_desc = "Data loaded from private L3 miss",
.pme_long_desc = "Data loaded from private L3 miss",
- .pme_event_ids = { -1, -1, 15, 19, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000180ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000008ULL }
- },
-#define POWER6_PME_PM_FPU_FPSCR 118
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L3MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L3MISS]
+ },
[ POWER6_PME_PM_FPU_FPSCR ] = {
.pme_name = "PM_FPU_FPSCR",
+ .pme_code = 0x2d0032,
.pme_short_desc = "FPU executed FPSCR instruction",
.pme_long_desc = "FPU executed FPSCR instruction",
- .pme_event_ids = { -1, 112, 100, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000001ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_VMX1_INST_ISSUED 119
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_FPSCR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_FPSCR]
+ },
[ POWER6_PME_PM_VMX1_INST_ISSUED ] = {
.pme_name = "PM_VMX1_INST_ISSUED",
+ .pme_code = 0x60088,
.pme_short_desc = "VMX1 instruction issued",
.pme_long_desc = "VMX1 instruction issued",
- .pme_event_ids = { 325, 332, 319, 317, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000200000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_FLUSH 120
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX1_INST_ISSUED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX1_INST_ISSUED]
+ },
[ POWER6_PME_PM_FLUSH ] = {
.pme_name = "PM_FLUSH",
+ .pme_code = 0x100010,
.pme_short_desc = "Flushes",
.pme_long_desc = "Flushes",
- .pme_event_ids = { 67, -1, -1, 73, -1, -1 },
- .pme_group_vector = {
- 0x0002000000080000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_ST_HIT_L2 121
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FLUSH],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FLUSH]
+ },
[ POWER6_PME_PM_ST_HIT_L2 ] = {
.pme_name = "PM_ST_HIT_L2",
+ .pme_code = 0x150732,
.pme_short_desc = "L2 D cache store hits",
.pme_long_desc = "L2 D cache store hits",
- .pme_event_ids = { 308, -1, -1, 298, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000010000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_SYNC_CYC 122
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_ST_HIT_L2],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_ST_HIT_L2]
+ },
[ POWER6_PME_PM_SYNC_CYC ] = {
.pme_name = "PM_SYNC_CYC",
+ .pme_code = 0x920cc,
.pme_short_desc = "Sync duration",
.pme_long_desc = "Sync duration",
- .pme_event_ids = { 312, 319, 303, 303, -1, -1 },
- .pme_group_vector = {
- 0x0000200000000000ULL,
- 0x0000000000000000ULL,
- 0x0061800000000010ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_FAB_SYS_PUMP 123
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_SYNC_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_SYNC_CYC]
+ },
[ POWER6_PME_PM_FAB_SYS_PUMP ] = {
.pme_name = "PM_FAB_SYS_PUMP",
+ .pme_code = 0x50180,
.pme_short_desc = "System pump operation",
.pme_long_desc = " locally mastered",
- .pme_event_ids = { 66, 76, 65, 72, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000010000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_IC_PREF_REQ 124
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FAB_SYS_PUMP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FAB_SYS_PUMP]
+ },
[ POWER6_PME_PM_IC_PREF_REQ ] = {
.pme_name = "PM_IC_PREF_REQ",
+ .pme_code = 0x4008c,
.pme_short_desc = "Instruction prefetch requests",
.pme_long_desc = "Asserted when a non-canceled prefetch is made to the cache interface unit (CIU).",
- .pme_event_ids = { 133, 142, 132, 139, -1, -1 },
- .pme_group_vector = {
- 0x0004000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_MEM0_DP_RQ_GLOB_LOC 125
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_IC_PREF_REQ],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IC_PREF_REQ]
+ },
[ POWER6_PME_PM_MEM0_DP_RQ_GLOB_LOC ] = {
.pme_name = "PM_MEM0_DP_RQ_GLOB_LOC",
+ .pme_code = 0x50280,
.pme_short_desc = "Memory read queue marking cache line double pump state from global to local side 0",
.pme_long_desc = "Memory read queue marking cache line double pump state from global to local side 0",
- .pme_event_ids = { 250, 261, 244, 249, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000080000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_FPU_ISSUE_0 126
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM0_DP_RQ_GLOB_LOC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM0_DP_RQ_GLOB_LOC]
+ },
[ POWER6_PME_PM_FPU_ISSUE_0 ] = {
.pme_name = "PM_FPU_ISSUE_0",
+ .pme_code = 0x320c6,
.pme_short_desc = "FPU issue 0 per cycle",
.pme_long_desc = "FPU issue 0 per cycle",
- .pme_event_ids = { 107, 115, 103, 112, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0010000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_THRD_PRIO_2_CYC 127
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_ISSUE_0],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_ISSUE_0]
+ },
[ POWER6_PME_PM_THRD_PRIO_2_CYC ] = {
.pme_name = "PM_THRD_PRIO_2_CYC",
+ .pme_code = 0x322040,
.pme_short_desc = "Cycles thread running at priority level 2",
.pme_long_desc = "Cycles thread running at priority level 2",
- .pme_event_ids = { -1, -1, 308, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000004000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_VMX_SIMPLE_ISSUED 128
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_2_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_2_CYC]
+ },
[ POWER6_PME_PM_VMX_SIMPLE_ISSUED ] = {
.pme_name = "PM_VMX_SIMPLE_ISSUED",
+ .pme_code = 0x70082,
.pme_short_desc = "VMX instruction issued to simple",
.pme_long_desc = "VMX instruction issued to simple",
- .pme_event_ids = { 335, 342, 329, 327, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000100000ULL,
- 0x0000000400000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_MRK_FPU1_FIN 129
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX_SIMPLE_ISSUED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX_SIMPLE_ISSUED]
+ },
[ POWER6_PME_PM_MRK_FPU1_FIN ] = {
.pme_name = "PM_MRK_FPU1_FIN",
+ .pme_code = 0xd008a,
.pme_short_desc = "Marked instruction FPU1 processing finished",
.pme_long_desc = "Marked instruction FPU1 processing finished",
- .pme_event_ids = { 266, 275, 260, 261, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000800100000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_DPU_HELD_CW 130
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_FPU1_FIN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_FPU1_FIN]
+ },
[ POWER6_PME_PM_DPU_HELD_CW ] = {
.pme_name = "PM_DPU_HELD_CW",
+ .pme_code = 0x20084,
.pme_short_desc = "DISP unit held due to cache writes ",
.pme_long_desc = "DISP unit held due to cache writes ",
- .pme_event_ids = { 33, 41, 32, 40, -1, -1 },
- .pme_group_vector = {
- 0x0000002000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_L3SA_REF 131
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_CW],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_CW]
+ },
[ POWER6_PME_PM_L3SA_REF ] = {
.pme_name = "PM_L3SA_REF",
+ .pme_code = 0x50080,
.pme_short_desc = "L3 slice A references",
.pme_long_desc = "L3 slice A references",
- .pme_event_ids = { 193, 203, 191, 196, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0004000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_STCX 132
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L3SA_REF],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L3SA_REF]
+ },
[ POWER6_PME_PM_STCX ] = {
.pme_name = "PM_STCX",
+ .pme_code = 0x830e6,
.pme_short_desc = "STCX executed",
.pme_long_desc = "STCX executed",
- .pme_event_ids = { 304, 310, 296, 295, -1, -1 },
- .pme_group_vector = {
- 0x0018000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_L2SB_MISS 133
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_STCX],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_STCX]
+ },
[ POWER6_PME_PM_L2SB_MISS ] = {
.pme_name = "PM_L2SB_MISS",
+ .pme_code = 0x5058c,
.pme_short_desc = "L2 slice B misses",
.pme_long_desc = "L2 slice B misses",
- .pme_event_ids = { 181, 190, 181, 187, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000100000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_LSU0_REJECT 134
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_MISS]
+ },
[ POWER6_PME_PM_LSU0_REJECT ] = {
.pme_name = "PM_LSU0_REJECT",
+ .pme_code = 0xa10a6,
.pme_short_desc = "LSU0 reject",
.pme_long_desc = "LSU0 reject",
- .pme_event_ids = { 208, 217, 203, 208, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000044ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_TB_BIT_TRANS 135
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT]
+ },
[ POWER6_PME_PM_TB_BIT_TRANS ] = {
.pme_name = "PM_TB_BIT_TRANS",
+ .pme_code = 0x100026,
.pme_short_desc = "Time Base bit transition",
.pme_long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 ",
- .pme_event_ids = { 313, -1, 304, -1, -1, -1 },
- .pme_group_vector = {
- 0x0080000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_THERMAL_MAX 136
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_TB_BIT_TRANS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_TB_BIT_TRANS]
+ },
[ POWER6_PME_PM_THERMAL_MAX ] = {
.pme_name = "PM_THERMAL_MAX",
+ .pme_code = 0x30002a,
.pme_short_desc = "Processor in thermal MAX",
.pme_long_desc = "Processor in thermal MAX",
- .pme_event_ids = { -1, -1, 305, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000001000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_FPU0_STF 137
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THERMAL_MAX],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THERMAL_MAX]
+ },
[ POWER6_PME_PM_FPU0_STF ] = {
.pme_name = "PM_FPU0_STF",
+ .pme_code = 0xc10a4,
.pme_short_desc = "FPU0 executed store instruction",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing a store instruction.",
- .pme_event_ids = { 84, 93, 82, 90, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0080000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_FPU1_FMA 138
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_STF],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_STF]
+ },
[ POWER6_PME_PM_FPU1_FMA ] = {
.pme_name = "PM_FPU1_FMA",
+ .pme_code = 0xc008a,
.pme_short_desc = "FPU1 executed multiply-add instruction",
.pme_long_desc = "This signal is active for one cycle when fp1 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 92, 101, 90, 98, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0800000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_LSU1_REJECT_LHS 139
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_FMA],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_FMA]
+ },
[ POWER6_PME_PM_LSU1_REJECT_LHS ] = {
.pme_name = "PM_LSU1_REJECT_LHS",
+ .pme_code = 0x9008e,
.pme_short_desc = "LSU1 load hit store reject",
.pme_long_desc = "LSU1 load hit store reject",
- .pme_event_ids = { 226, 235, 221, 226, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000020ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_DPU_HELD_INT 140
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_REJECT_LHS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_REJECT_LHS]
+ },
[ POWER6_PME_PM_DPU_HELD_INT ] = {
.pme_name = "PM_DPU_HELD_INT",
+ .pme_code = 0x310a8,
.pme_short_desc = "DISP unit held due to exception",
.pme_long_desc = "DISP unit held due to exception",
- .pme_event_ids = { 40, 48, 39, 47, -1, -1 },
- .pme_group_vector = {
- 0x0000020000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_THRD_LLA_BOTH_CYC 141
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_INT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_INT]
+ },
[ POWER6_PME_PM_THRD_LLA_BOTH_CYC ] = {
.pme_name = "PM_THRD_LLA_BOTH_CYC",
+ .pme_code = 0x400008,
.pme_short_desc = "Both threads in Load Look Ahead",
.pme_long_desc = "Both threads in Load Look Ahead",
- .pme_event_ids = { -1, -1, -1, 306, -1, -1 },
- .pme_group_vector = {
- 0x0040000000000000ULL,
- 0x0000000000001000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_DPU_HELD_THERMAL_COUNT 142
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_LLA_BOTH_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_LLA_BOTH_CYC]
+ },
[ POWER6_PME_PM_DPU_HELD_THERMAL_COUNT ] = {
.pme_name = "PM_DPU_HELD_THERMAL_COUNT",
+ .pme_code = 0x10002b,
.pme_short_desc = "Periods DISP unit held due to thermal condition",
.pme_long_desc = "Periods DISP unit held due to thermal condition",
- .pme_event_ids = { 348, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0002020000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_PMC4_REWIND 143
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_THERMAL_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_THERMAL_COUNT]
+ },
[ POWER6_PME_PM_PMC4_REWIND ] = {
.pme_name = "PM_PMC4_REWIND",
+ .pme_code = 0x100020,
.pme_short_desc = "PMC4 rewind event",
.pme_long_desc = "PMC4 rewind event",
- .pme_event_ids = { 293, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_DERAT_REF_16M 144
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PMC4_REWIND],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PMC4_REWIND]
+ },
[ POWER6_PME_PM_DERAT_REF_16M ] = {
.pme_name = "PM_DERAT_REF_16M",
+ .pme_code = 0x382070,
.pme_short_desc = "DERAT reference for 16M page",
.pme_long_desc = "DERAT reference for 16M page",
- .pme_event_ids = { -1, -1, 342, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000080ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_FPU0_FCONV 145
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DERAT_REF_16M],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DERAT_REF_16M]
+ },
[ POWER6_PME_PM_FPU0_FCONV ] = {
.pme_name = "PM_FPU0_FCONV",
+ .pme_code = 0xd10a0,
.pme_short_desc = "FPU0 executed FCONV instruction",
.pme_long_desc = "FPU0 executed FCONV instruction",
- .pme_event_ids = { 73, 82, 71, 79, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0400000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_L2SA_LD_REQ_DATA 146
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_FCONV],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_FCONV]
+ },
[ POWER6_PME_PM_L2SA_LD_REQ_DATA ] = {
.pme_name = "PM_L2SA_LD_REQ_DATA",
+ .pme_code = 0x50480,
.pme_short_desc = "L2 slice A data load requests",
.pme_long_desc = "L2 slice A data load requests",
- .pme_event_ids = { 165, 174, 165, 171, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000020000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_DATA_FROM_MEM_DP 147
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_LD_REQ_DATA],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_LD_REQ_DATA]
+ },
[ POWER6_PME_PM_DATA_FROM_MEM_DP ] = {
.pme_name = "PM_DATA_FROM_MEM_DP",
+ .pme_code = 0x10005e,
.pme_short_desc = "Data loaded from double pump memory",
.pme_long_desc = "Data loaded from double pump memory",
- .pme_event_ids = { 15, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000020800ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_MRK_VMX_FLOAT_ISSUED 148
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_MEM_DP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_MEM_DP]
+ },
[ POWER6_PME_PM_MRK_VMX_FLOAT_ISSUED ] = {
.pme_name = "PM_MRK_VMX_FLOAT_ISSUED",
+ .pme_code = 0x70088,
.pme_short_desc = "Marked VMX instruction issued to float",
.pme_long_desc = "Marked VMX instruction issued to float",
- .pme_event_ids = { 286, 298, 281, 283, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000100000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_MRK_PTEG_FROM_L2MISS 149
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_VMX_FLOAT_ISSUED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_VMX_FLOAT_ISSUED]
+ },
[ POWER6_PME_PM_MRK_PTEG_FROM_L2MISS ] = {
.pme_name = "PM_MRK_PTEG_FROM_L2MISS",
+ .pme_code = 0x412054,
.pme_short_desc = "Marked PTEG loaded from L2 miss",
.pme_long_desc = "Marked PTEG loaded from L2 miss",
- .pme_event_ids = { -1, -1, -1, 277, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000020000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_THRD_PRIO_DIFF_1or2_CYC 150
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_L2MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_L2MISS]
+ },
[ POWER6_PME_PM_THRD_PRIO_DIFF_1or2_CYC ] = {
.pme_name = "PM_THRD_PRIO_DIFF_1or2_CYC",
+ .pme_code = 0x223040,
.pme_short_desc = "Cycles thread priority difference is 1 or 2",
.pme_long_desc = "Cycles thread priority difference is 1 or 2",
- .pme_event_ids = { -1, 324, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000010000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_VMX0_STALL 151
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_DIFF_1or2_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_DIFF_1or2_CYC]
+ },
[ POWER6_PME_PM_VMX0_STALL ] = {
.pme_name = "PM_VMX0_STALL",
+ .pme_code = 0xb0084,
.pme_short_desc = "VMX0 stall",
.pme_long_desc = "VMX0 stall",
- .pme_event_ids = { 324, 331, 318, 316, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000001000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_IC_DEMAND_L2_BHT_REDIRECT 152
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX0_STALL],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX0_STALL]
+ },
[ POWER6_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = {
.pme_name = "PM_IC_DEMAND_L2_BHT_REDIRECT",
+ .pme_code = 0x420ca,
.pme_short_desc = "L2 I cache demand request due to BHT redirect",
.pme_long_desc = "L2 I cache demand request due to BHT redirect",
- .pme_event_ids = { 131, 139, 129, 137, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0002000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_LSU_DERAT_MISS 153
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_IC_DEMAND_L2_BHT_REDIRECT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IC_DEMAND_L2_BHT_REDIRECT]
+ },
[ POWER6_PME_PM_LSU_DERAT_MISS ] = {
.pme_name = "PM_LSU_DERAT_MISS",
+ .pme_code = 0x20000e,
.pme_short_desc = "DERAT misses",
.pme_long_desc = "Total DERAT Misses (Unit 0 + Unit 1). Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.",
- .pme_event_ids = { -1, 243, -1, 335, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000800ULL,
- 0x0020004000000020ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_FPU0_SINGLE 154
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_DERAT_MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_DERAT_MISS]
+ },
[ POWER6_PME_PM_FPU0_SINGLE ] = {
.pme_name = "PM_FPU0_SINGLE",
+ .pme_code = 0xc10a6,
.pme_short_desc = "FPU0 executed single precision instruction",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing single precision instruction.",
- .pme_event_ids = { 83, 92, 81, 89, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0100000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_FPU_ISSUE_STEERING 155
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_SINGLE],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_SINGLE]
+ },
[ POWER6_PME_PM_FPU_ISSUE_STEERING ] = {
.pme_name = "PM_FPU_ISSUE_STEERING",
+ .pme_code = 0x320c4,
.pme_short_desc = "FPU issue steering",
.pme_long_desc = "FPU issue steering",
- .pme_event_ids = { 115, 123, 111, 120, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0010000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
- },
-#define POWER6_PME_PM_THRD_PRIO_1_CYC 156
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_ISSUE_STEERING],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_ISSUE_STEERING]
+ },
[ POWER6_PME_PM_THRD_PRIO_1_CYC ] = {
.pme_name = "PM_THRD_PRIO_1_CYC",
+ .pme_code = 0x222040,
.pme_short_desc = "Cycles thread running at priority level 1",
.pme_long_desc = "Cycles thread running at priority level 1",
- .pme_event_ids = { -1, 322, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000004000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_1_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_1_CYC]
+ },
+ [ POWER6_PME_PM_VMX_COMPLEX_ISSUED ] = {
+ .pme_name = "PM_VMX_COMPLEX_ISSUED",
+ .pme_code = 0x70084,
+ .pme_short_desc = "VMX instruction issued to complex",
+ .pme_long_desc = "VMX instruction issued to complex",
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX_COMPLEX_ISSUED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX_COMPLEX_ISSUED]
},
-#define POWER6_PME_PM_FPU_ISSUE_ST_FOLDED 157
[ POWER6_PME_PM_FPU_ISSUE_ST_FOLDED ] = {
.pme_name = "PM_FPU_ISSUE_ST_FOLDED",
+ .pme_code = 0x320c2,
.pme_short_desc = "FPU issue a folded store",
.pme_long_desc = "FPU issue a folded store",
- .pme_event_ids = { 116, 124, 112, 121, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0020000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_ISSUE_ST_FOLDED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_ISSUE_ST_FOLDED]
},
-#define POWER6_PME_PM_DFU_FIN 158
[ POWER6_PME_PM_DFU_FIN ] = {
.pme_name = "PM_DFU_FIN",
+ .pme_code = 0xe0080,
.pme_short_desc = "DFU instruction finish",
.pme_long_desc = "DFU instruction finish",
- .pme_event_ids = { 29, 36, 28, 36, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000004000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DFU_FIN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DFU_FIN]
},
-#define POWER6_PME_PM_BR_PRED_CCACHE 159
[ POWER6_PME_PM_BR_PRED_CCACHE ] = {
.pme_name = "PM_BR_PRED_CCACHE",
+ .pme_code = 0x410a4,
.pme_short_desc = "Branch count cache prediction",
.pme_long_desc = "Branch count cache prediction",
- .pme_event_ids = { 9, 7, 7, 9, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000018ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_BR_PRED_CCACHE],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_BR_PRED_CCACHE]
},
-#define POWER6_PME_PM_MRK_ST_CMPL_INT 160
[ POWER6_PME_PM_MRK_ST_CMPL_INT ] = {
.pme_name = "PM_MRK_ST_CMPL_INT",
+ .pme_code = 0x300006,
.pme_short_desc = "Marked store completed with intervention",
.pme_long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention",
- .pme_event_ids = { -1, -1, 277, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000002000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_ST_CMPL_INT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_ST_CMPL_INT]
},
-#define POWER6_PME_PM_FAB_MMIO 161
[ POWER6_PME_PM_FAB_MMIO ] = {
.pme_name = "PM_FAB_MMIO",
+ .pme_code = 0x50186,
.pme_short_desc = "MMIO operation",
.pme_long_desc = " locally mastered",
- .pme_event_ids = { 62, 72, 61, 68, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000020000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FAB_MMIO],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FAB_MMIO]
},
-#define POWER6_PME_PM_MRK_VMX_SIMPLE_ISSUED 162
[ POWER6_PME_PM_MRK_VMX_SIMPLE_ISSUED ] = {
.pme_name = "PM_MRK_VMX_SIMPLE_ISSUED",
+ .pme_code = 0x7008a,
.pme_short_desc = "Marked VMX instruction issued to simple",
.pme_long_desc = "Marked VMX instruction issued to simple",
- .pme_event_ids = { 288, 300, 283, 285, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000400000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_VMX_SIMPLE_ISSUED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_VMX_SIMPLE_ISSUED]
},
-#define POWER6_PME_PM_FPU_STF 163
[ POWER6_PME_PM_FPU_STF ] = {
.pme_name = "PM_FPU_STF",
+ .pme_code = 0x3c1030,
.pme_short_desc = "FPU executed store instruction",
.pme_long_desc = "FPU is executing a store instruction. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, 113, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0800000000000002ULL,
- 0x0000000000000002ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_STF],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_STF]
},
-#define POWER6_PME_PM_MEM1_DP_CL_WR_GLOB 164
[ POWER6_PME_PM_MEM1_DP_CL_WR_GLOB ] = {
.pme_name = "PM_MEM1_DP_CL_WR_GLOB",
+ .pme_code = 0x5028c,
.pme_short_desc = "cacheline write setting dp to global side 1",
.pme_long_desc = "cacheline write setting dp to global side 1",
- .pme_event_ids = { 252, 263, 246, 251, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000100000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM1_DP_CL_WR_GLOB],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM1_DP_CL_WR_GLOB]
},
-#define POWER6_PME_PM_MRK_DATA_FROM_L3MISS 165
[ POWER6_PME_PM_MRK_DATA_FROM_L3MISS ] = {
.pme_name = "PM_MRK_DATA_FROM_L3MISS",
+ .pme_code = 0x303028,
.pme_short_desc = "Marked data loaded from L3 miss",
.pme_long_desc = "Marked data loaded from L3 miss",
- .pme_event_ids = { -1, -1, 255, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000002000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_L3MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_L3MISS]
},
-#define POWER6_PME_PM_GCT_NOSLOT_CYC 166
[ POWER6_PME_PM_GCT_NOSLOT_CYC ] = {
.pme_name = "PM_GCT_NOSLOT_CYC",
+ .pme_code = 0x100008,
.pme_short_desc = "Cycles no GCT slot allocated",
.pme_long_desc = "Cycles this thread does not have any slots allocated in the GCT.",
- .pme_event_ids = { 121, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000002000ULL,
- 0x0010000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_GCT_NOSLOT_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GCT_NOSLOT_CYC]
},
-#define POWER6_PME_PM_L2_ST_REQ_DATA 167
[ POWER6_PME_PM_L2_ST_REQ_DATA ] = {
.pme_name = "PM_L2_ST_REQ_DATA",
+ .pme_code = 0x250432,
.pme_short_desc = "L2 data store requests",
.pme_long_desc = "L2 data store requests",
- .pme_event_ids = { -1, 200, 188, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000002000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2_ST_REQ_DATA],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2_ST_REQ_DATA]
},
-#define POWER6_PME_PM_INST_TABLEWALK_COUNT 168
[ POWER6_PME_PM_INST_TABLEWALK_COUNT ] = {
.pme_name = "PM_INST_TABLEWALK_COUNT",
+ .pme_code = 0x920cb,
.pme_short_desc = "Periods doing instruction tablewalks",
.pme_long_desc = "Periods doing instruction tablewalks",
- .pme_event_ids = { 341, 348, 335, 333, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000200000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_TABLEWALK_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_TABLEWALK_COUNT]
},
-#define POWER6_PME_PM_PTEG_FROM_L35_SHR 169
[ POWER6_PME_PM_PTEG_FROM_L35_SHR ] = {
.pme_name = "PM_PTEG_FROM_L35_SHR",
+ .pme_code = 0x21304e,
.pme_short_desc = "PTEG loaded from L3.5 shared",
.pme_long_desc = "PTEG loaded from L3.5 shared",
- .pme_event_ids = { -1, 306, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000020000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_L35_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_L35_SHR]
},
-#define POWER6_PME_PM_DPU_HELD_ISYNC 170
[ POWER6_PME_PM_DPU_HELD_ISYNC ] = {
.pme_name = "PM_DPU_HELD_ISYNC",
+ .pme_code = 0x2008a,
.pme_short_desc = "DISP unit held due to ISYNC ",
.pme_long_desc = "DISP unit held due to ISYNC ",
- .pme_event_ids = { 41, 49, 40, 48, -1, -1 },
- .pme_group_vector = {
- 0x0000184000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_ISYNC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_ISYNC]
},
-#define POWER6_PME_PM_MRK_DATA_FROM_L25_SHR 171
[ POWER6_PME_PM_MRK_DATA_FROM_L25_SHR ] = {
.pme_name = "PM_MRK_DATA_FROM_L25_SHR",
+ .pme_code = 0x40304e,
.pme_short_desc = "Marked data loaded from L2.5 shared",
.pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a marked demand load",
- .pme_event_ids = { -1, -1, -1, 257, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000001000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_L25_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_L25_SHR]
},
-#define POWER6_PME_PM_L3SA_HIT 172
[ POWER6_PME_PM_L3SA_HIT ] = {
.pme_name = "PM_L3SA_HIT",
+ .pme_code = 0x50082,
.pme_short_desc = "L3 slice A hits",
.pme_long_desc = "L3 slice A hits",
- .pme_event_ids = { 191, 201, 189, 194, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0004000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L3SA_HIT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L3SA_HIT]
},
-#define POWER6_PME_PM_DERAT_MISS_16G 173
[ POWER6_PME_PM_DERAT_MISS_16G ] = {
.pme_name = "PM_DERAT_MISS_16G",
+ .pme_code = 0x492070,
.pme_short_desc = "DERAT misses for 16G page",
.pme_long_desc = "A data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.",
- .pme_event_ids = { -1, -1, -1, 343, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000040ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DERAT_MISS_16G],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DERAT_MISS_16G]
},
-#define POWER6_PME_PM_DATA_PTEG_2ND_HALF 174
[ POWER6_PME_PM_DATA_PTEG_2ND_HALF ] = {
.pme_name = "PM_DATA_PTEG_2ND_HALF",
+ .pme_code = 0x910a2,
.pme_short_desc = "Data table walk matched in second half priÂmary PTEG",
.pme_long_desc = "Data table walk matched in second half priÂmary PTEG",
- .pme_event_ids = { 18, 26, 18, 25, -1, -1 },
- .pme_group_vector = {
- 0x0000000100000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_PTEG_2ND_HALF],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_PTEG_2ND_HALF]
},
-#define POWER6_PME_PM_L2SA_ST_REQ 175
[ POWER6_PME_PM_L2SA_ST_REQ ] = {
.pme_name = "PM_L2SA_ST_REQ",
+ .pme_code = 0x50484,
.pme_short_desc = "L2 slice A store requests",
.pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C.",
- .pme_event_ids = { 170, 179, 170, 176, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0001080000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_ST_REQ],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_ST_REQ]
},
-#define POWER6_PME_PM_INST_FROM_LMEM 176
[ POWER6_PME_PM_INST_FROM_LMEM ] = {
.pme_name = "PM_INST_FROM_LMEM",
+ .pme_code = 0x442042,
.pme_short_desc = "Instruction fetched from local memory",
.pme_long_desc = "Instruction fetched from local memory",
- .pme_event_ids = { -1, -1, -1, 152, -1, -1 },
- .pme_group_vector = {
- 0x0000000002000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_LMEM],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_LMEM]
},
-#define POWER6_PME_PM_IC_DEMAND_L2_BR_REDIRECT 177
[ POWER6_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = {
.pme_name = "PM_IC_DEMAND_L2_BR_REDIRECT",
+ .pme_code = 0x420cc,
.pme_short_desc = "L2 I cache demand request due to branch redirect",
.pme_long_desc = "L2 I cache demand request due to branch redirect",
- .pme_event_ids = { 132, 140, 130, 138, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0002000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_IC_DEMAND_L2_BR_REDIRECT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IC_DEMAND_L2_BR_REDIRECT]
},
-#define POWER6_PME_PM_PTEG_FROM_L2 178
[ POWER6_PME_PM_PTEG_FROM_L2 ] = {
.pme_name = "PM_PTEG_FROM_L2",
+ .pme_code = 0x113048,
.pme_short_desc = "PTEG loaded from L2",
.pme_long_desc = "PTEG loaded from L2",
- .pme_event_ids = { 295, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000008000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_L2],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_L2]
},
-#define POWER6_PME_PM_DATA_PTEG_1ST_HALF 179
[ POWER6_PME_PM_DATA_PTEG_1ST_HALF ] = {
.pme_name = "PM_DATA_PTEG_1ST_HALF",
+ .pme_code = 0x910a0,
.pme_short_desc = "Data table walk matched in first half primary PTEG",
.pme_long_desc = "Data table walk matched in first half primary PTEG",
- .pme_event_ids = { 17, 25, 17, 24, -1, -1 },
- .pme_group_vector = {
- 0x0000000100000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_PTEG_1ST_HALF],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_PTEG_1ST_HALF]
},
-#define POWER6_PME_PM_BR_MPRED_COUNT 180
[ POWER6_PME_PM_BR_MPRED_COUNT ] = {
.pme_name = "PM_BR_MPRED_COUNT",
+ .pme_code = 0x410aa,
.pme_short_desc = "Branch misprediction due to count prediction",
.pme_long_desc = "Branch misprediction due to count prediction",
- .pme_event_ids = { 5, 3, 3, 5, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000024ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_BR_MPRED_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_BR_MPRED_COUNT]
},
-#define POWER6_PME_PM_IERAT_MISS_4K 181
[ POWER6_PME_PM_IERAT_MISS_4K ] = {
.pme_name = "PM_IERAT_MISS_4K",
+ .pme_code = 0x492076,
.pme_short_desc = "IERAT misses for 4K page",
.pme_long_desc = "IERAT misses for 4K page",
- .pme_event_ids = { -1, -1, -1, 344, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000100ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_IERAT_MISS_4K],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IERAT_MISS_4K]
},
-#define POWER6_PME_PM_THRD_BOTH_RUN_COUNT 182
[ POWER6_PME_PM_THRD_BOTH_RUN_COUNT ] = {
.pme_name = "PM_THRD_BOTH_RUN_COUNT",
+ .pme_code = 0x400005,
.pme_short_desc = "Periods both threads in run cycles",
.pme_long_desc = "Periods both threads in run cycles",
- .pme_event_ids = { -1, -1, -1, 336, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0100000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_BOTH_RUN_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_BOTH_RUN_COUNT]
},
-#define POWER6_PME_PM_LSU_REJECT_ULD 183
[ POWER6_PME_PM_LSU_REJECT_ULD ] = {
.pme_name = "PM_LSU_REJECT_ULD",
+ .pme_code = 0x190030,
.pme_short_desc = "Unaligned load reject",
.pme_long_desc = "Unaligned load reject",
- .pme_event_ids = { 244, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x8000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_ULD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_ULD]
},
-#define POWER6_PME_PM_DATA_FROM_DL2L3_MOD_CYC 184
[ POWER6_PME_PM_DATA_FROM_DL2L3_MOD_CYC ] = {
.pme_name = "PM_DATA_FROM_DL2L3_MOD_CYC",
+ .pme_code = 0x40002a,
.pme_short_desc = "Load latency from distant L2 or L3 modified",
.pme_long_desc = "Load latency from distant L2 or L3 modified",
- .pme_event_ids = { -1, -1, -1, 14, -1, -1 },
- .pme_group_vector = {
- 0x0000000000002000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_DL2L3_MOD_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_DL2L3_MOD_CYC]
},
-#define POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_MOD 185
[ POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_MOD ] = {
.pme_name = "PM_MRK_PTEG_FROM_RL2L3_MOD",
+ .pme_code = 0x112044,
.pme_short_desc = "Marked PTEG loaded from remote L2 or L3 modified",
.pme_long_desc = "Marked PTEG loaded from remote L2 or L3 modified",
- .pme_event_ids = { 280, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000040000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_MOD]
},
-#define POWER6_PME_PM_FPU0_FLOP 186
[ POWER6_PME_PM_FPU0_FLOP ] = {
.pme_name = "PM_FPU0_FLOP",
+ .pme_code = 0xc0086,
.pme_short_desc = "FPU0 executed 1FLOP",
.pme_long_desc = " FMA",
- .pme_event_ids = { 76, 85, 74, 82, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0100000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_FLOP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_FLOP]
},
-#define POWER6_PME_PM_FPU0_FEST 187
[ POWER6_PME_PM_FPU0_FEST ] = {
.pme_name = "PM_FPU0_FEST",
+ .pme_code = 0xd10a6,
.pme_short_desc = "FPU0 executed FEST instruction",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ",
- .pme_event_ids = { 74, 83, 72, 80, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0600000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_FEST],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_FEST]
},
-#define POWER6_PME_PM_MRK_LSU0_REJECT_LHS 188
[ POWER6_PME_PM_MRK_LSU0_REJECT_LHS ] = {
.pme_name = "PM_MRK_LSU0_REJECT_LHS",
+ .pme_code = 0x930e6,
.pme_short_desc = "LSU0 marked load hit store reject",
.pme_long_desc = "LSU0 marked load hit store reject",
- .pme_event_ids = { 270, 282, 264, 265, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000020000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU0_REJECT_LHS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU0_REJECT_LHS]
},
-#define POWER6_PME_PM_VMX_RESULT_SAT_1 189
[ POWER6_PME_PM_VMX_RESULT_SAT_1 ] = {
.pme_name = "PM_VMX_RESULT_SAT_1",
+ .pme_code = 0xb0086,
.pme_short_desc = "VMX valid result with sat=1",
.pme_long_desc = "VMX valid result with sat=1",
- .pme_event_ids = { 334, 341, 328, 326, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000800000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX_RESULT_SAT_1],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX_RESULT_SAT_1]
},
-#define POWER6_PME_PM_NO_ITAG_CYC 190
[ POWER6_PME_PM_NO_ITAG_CYC ] = {
.pme_name = "PM_NO_ITAG_CYC",
+ .pme_code = 0x40088,
.pme_short_desc = "Cyles no ITAG available",
.pme_long_desc = "Cyles no ITAG available",
- .pme_event_ids = { 290, 302, 285, 287, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000001000000000ULL,
- 0x0000400000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_NO_ITAG_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_NO_ITAG_CYC]
},
-#define POWER6_PME_PM_LSU1_REJECT_NO_SCRATCH 191
[ POWER6_PME_PM_LSU1_REJECT_NO_SCRATCH ] = {
.pme_name = "PM_LSU1_REJECT_NO_SCRATCH",
+ .pme_code = 0xa10aa,
.pme_short_desc = "LSU1 reject due to scratch register not available",
.pme_long_desc = "LSU1 reject due to scratch register not available",
- .pme_event_ids = { 227, 236, 222, 227, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000014ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_REJECT_NO_SCRATCH],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_REJECT_NO_SCRATCH]
},
-#define POWER6_PME_PM_0INST_FETCH 192
[ POWER6_PME_PM_0INST_FETCH ] = {
.pme_name = "PM_0INST_FETCH",
+ .pme_code = 0x40080,
.pme_short_desc = "No instructions fetched",
.pme_long_desc = "No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)",
- .pme_event_ids = { 0, 0, 0, 0, -1, -1 },
- .pme_group_vector = {
- 0x0080000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000100000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_0INST_FETCH],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_0INST_FETCH]
},
-#define POWER6_PME_PM_DPU_WT_BR_MPRED 193
[ POWER6_PME_PM_DPU_WT_BR_MPRED ] = {
.pme_name = "PM_DPU_WT_BR_MPRED",
+ .pme_code = 0x40000c,
.pme_short_desc = "Cycles DISP unit is stalled due to branch misprediction",
.pme_long_desc = "Cycles DISP unit is stalled due to branch misprediction",
- .pme_event_ids = { -1, -1, -1, 62, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL,
- 0x0000000000000000ULL,
- 0x0004000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_WT_BR_MPRED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_WT_BR_MPRED]
},
-#define POWER6_PME_PM_L1_PREF 194
[ POWER6_PME_PM_L1_PREF ] = {
.pme_name = "PM_L1_PREF",
+ .pme_code = 0x810a4,
.pme_short_desc = "L1 cache data prefetches",
.pme_long_desc = "A request to prefetch data into the L1 was made",
- .pme_event_ids = { 155, 164, 155, 161, -1, -1 },
- .pme_group_vector = {
- 0x0001000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L1_PREF],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L1_PREF]
},
-#define POWER6_PME_PM_VMX_FLOAT_MULTICYCLE 195
[ POWER6_PME_PM_VMX_FLOAT_MULTICYCLE ] = {
.pme_name = "PM_VMX_FLOAT_MULTICYCLE",
+ .pme_code = 0xb0082,
.pme_short_desc = "VMX multi-cycle floating point instruction issued",
.pme_long_desc = "VMX multi-cycle floating point instruction issued",
- .pme_event_ids = { 331, 338, 325, 323, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000001800000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX_FLOAT_MULTICYCLE],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX_FLOAT_MULTICYCLE]
},
-#define POWER6_PME_PM_DATA_FROM_L25_SHR_CYC 196
[ POWER6_PME_PM_DATA_FROM_L25_SHR_CYC ] = {
.pme_name = "PM_DATA_FROM_L25_SHR_CYC",
+ .pme_code = 0x200024,
.pme_short_desc = "Load latency from L2.5 shared",
.pme_long_desc = "Load latency from L2.5 shared",
- .pme_event_ids = { -1, 16, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000020000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L25_SHR_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L25_SHR_CYC]
},
-#define POWER6_PME_PM_DATA_FROM_L3 197
[ POWER6_PME_PM_DATA_FROM_L3 ] = {
.pme_name = "PM_DATA_FROM_L3",
+ .pme_code = 0x300058,
.pme_short_desc = "Data loaded from L3",
.pme_long_desc = "DL1 was reloaded from the local L3 due to a demand load",
- .pme_event_ids = { -1, -1, 14, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000010100ULL,
- 0x000c000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000001ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L3],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L3]
},
-#define POWER6_PME_PM_PMC2_OVERFLOW 198
[ POWER6_PME_PM_PMC2_OVERFLOW ] = {
.pme_name = "PM_PMC2_OVERFLOW",
+ .pme_code = 0x300014,
.pme_short_desc = "PMC2 Overflow",
.pme_long_desc = "PMC2 Overflow",
- .pme_event_ids = { -1, -1, 286, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PMC2_OVERFLOW],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PMC2_OVERFLOW]
},
-#define POWER6_PME_PM_VMX0_LD_WRBACK 199
[ POWER6_PME_PM_VMX0_LD_WRBACK ] = {
.pme_name = "PM_VMX0_LD_WRBACK",
+ .pme_code = 0x60084,
.pme_short_desc = "VMX0 load writeback valid",
.pme_long_desc = "VMX0 load writeback valid",
- .pme_event_ids = { 323, 330, 317, 315, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000400000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX0_LD_WRBACK],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX0_LD_WRBACK]
},
-#define POWER6_PME_PM_FPU0_DENORM 200
[ POWER6_PME_PM_FPU0_DENORM ] = {
.pme_name = "PM_FPU0_DENORM",
+ .pme_code = 0xc10a2,
.pme_short_desc = "FPU0 received denormalized data",
.pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.",
- .pme_event_ids = { 72, 81, 70, 78, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0100000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_DENORM],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_DENORM]
},
-#define POWER6_PME_PM_INST_FETCH_CYC 201
[ POWER6_PME_PM_INST_FETCH_CYC ] = {
.pme_name = "PM_INST_FETCH_CYC",
+ .pme_code = 0x420c8,
.pme_short_desc = "Cycles at least 1 instruction fetched",
.pme_long_desc = "Asserted each cycle when the IFU sends at least one instruction to the IDU. ",
- .pme_event_ids = { 141, 151, 141, 147, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000002000ULL,
- 0x0000010000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FETCH_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FETCH_CYC]
},
-#define POWER6_PME_PM_LSU_LDF 202
[ POWER6_PME_PM_LSU_LDF ] = {
.pme_name = "PM_LSU_LDF",
+ .pme_code = 0x280032,
.pme_short_desc = "LSU executed Floating Point load instruction",
.pme_long_desc = "LSU executed Floating Point load instruction",
- .pme_event_ids = { -1, 246, 231, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000100ULL,
- 0x0800000000000000ULL,
- 0x0000000000000004ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_LDF],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_LDF]
},
-#define POWER6_PME_PM_LSU_REJECT_L2_CORR 203
[ POWER6_PME_PM_LSU_REJECT_L2_CORR ] = {
.pme_name = "PM_LSU_REJECT_L2_CORR",
+ .pme_code = 0x1a1034,
.pme_short_desc = "LSU reject due to L2 correctable error",
.pme_long_desc = "LSU reject due to L2 correctable error",
- .pme_event_ids = { 239, -1, -1, 239, -1, -1 },
- .pme_group_vector = {
- 0x0800000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_L2_CORR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_L2_CORR]
},
-#define POWER6_PME_PM_DERAT_REF_64K 204
[ POWER6_PME_PM_DERAT_REF_64K ] = {
.pme_name = "PM_DERAT_REF_64K",
+ .pme_code = 0x282070,
.pme_short_desc = "DERAT reference for 64K page",
.pme_long_desc = "DERAT reference for 64K page",
- .pme_event_ids = { -1, 360, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000080ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DERAT_REF_64K],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DERAT_REF_64K]
},
-#define POWER6_PME_PM_THRD_PRIO_3_CYC 205
[ POWER6_PME_PM_THRD_PRIO_3_CYC ] = {
.pme_name = "PM_THRD_PRIO_3_CYC",
+ .pme_code = 0x422040,
.pme_short_desc = "Cycles thread running at priority level 3",
.pme_long_desc = "Cycles thread running at priority level 3",
- .pme_event_ids = { -1, -1, -1, 307, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000004000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_3_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_3_CYC]
},
-#define POWER6_PME_PM_FPU_FMA 206
[ POWER6_PME_PM_FPU_FMA ] = {
.pme_name = "PM_FPU_FMA",
+ .pme_code = 0x2c0030,
.pme_short_desc = "FPU executed multiply-add instruction",
.pme_long_desc = "This signal is active for one cycle when FPU is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, 111, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x8000000000000000ULL,
- 0x0400000000000000ULL,
- 0x0000000000000002ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_FMA],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_FMA]
},
-#define POWER6_PME_PM_INST_FROM_L35_MOD 207
[ POWER6_PME_PM_INST_FROM_L35_MOD ] = {
.pme_name = "PM_INST_FROM_L35_MOD",
+ .pme_code = 0x142046,
.pme_short_desc = "Instruction fetched from L3.5 modified",
.pme_long_desc = "Instruction fetched from L3.5 modified",
- .pme_event_ids = { 144, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000800000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_L35_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_L35_MOD]
},
-#define POWER6_PME_PM_DFU_CONV 208
[ POWER6_PME_PM_DFU_CONV ] = {
.pme_name = "PM_DFU_CONV",
+ .pme_code = 0xe008e,
.pme_short_desc = "DFU convert from fixed op",
.pme_long_desc = "DFU convert from fixed op",
- .pme_event_ids = { 26, 33, 25, 33, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000002000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DFU_CONV],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DFU_CONV]
},
-#define POWER6_PME_PM_INST_FROM_L25_MOD 209
[ POWER6_PME_PM_INST_FROM_L25_MOD ] = {
.pme_name = "PM_INST_FROM_L25_MOD",
+ .pme_code = 0x342046,
.pme_short_desc = "Instruction fetched from L2.5 modified",
.pme_long_desc = "Instruction fetched from L2.5 modified",
- .pme_event_ids = { -1, -1, 144, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000400000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_L25_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_L25_MOD]
},
-#define POWER6_PME_PM_PTEG_FROM_L35_MOD 210
[ POWER6_PME_PM_PTEG_FROM_L35_MOD ] = {
.pme_name = "PM_PTEG_FROM_L35_MOD",
+ .pme_code = 0x11304e,
.pme_short_desc = "PTEG loaded from L3.5 modified",
.pme_long_desc = "PTEG loaded from L3.5 modified",
- .pme_event_ids = { 297, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000020000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_L35_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_L35_MOD]
},
-#define POWER6_PME_PM_MRK_VMX_ST_ISSUED 211
[ POWER6_PME_PM_MRK_VMX_ST_ISSUED ] = {
.pme_name = "PM_MRK_VMX_ST_ISSUED",
+ .pme_code = 0xb0088,
.pme_short_desc = "Marked VMX store issued",
.pme_long_desc = "Marked VMX store issued",
- .pme_event_ids = { 289, 301, 284, 286, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000800000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_VMX_ST_ISSUED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_VMX_ST_ISSUED]
},
-#define POWER6_PME_PM_VMX_FLOAT_ISSUED 212
[ POWER6_PME_PM_VMX_FLOAT_ISSUED ] = {
.pme_name = "PM_VMX_FLOAT_ISSUED",
+ .pme_code = 0x70080,
.pme_short_desc = "VMX instruction issued to float",
.pme_long_desc = "VMX instruction issued to float",
- .pme_event_ids = { 330, 337, 324, 322, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000100000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX_FLOAT_ISSUED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX_FLOAT_ISSUED]
},
-#define POWER6_PME_PM_LSU0_REJECT_L2_CORR 213
[ POWER6_PME_PM_LSU0_REJECT_L2_CORR ] = {
.pme_name = "PM_LSU0_REJECT_L2_CORR",
+ .pme_code = 0xa10a0,
.pme_short_desc = "LSU0 reject due to L2 correctable error",
.pme_long_desc = "LSU0 reject due to L2 correctable error",
- .pme_event_ids = { 212, 221, 207, 212, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000008ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT_L2_CORR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT_L2_CORR]
},
-#define POWER6_PME_PM_THRD_L2MISS 214
[ POWER6_PME_PM_THRD_L2MISS ] = {
.pme_name = "PM_THRD_L2MISS",
+ .pme_code = 0x310a0,
.pme_short_desc = "Thread in L2 miss",
.pme_long_desc = "Thread in L2 miss",
- .pme_event_ids = { 314, 321, 307, 305, -1, -1 },
- .pme_group_vector = {
- 0x0100000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_L2MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_L2MISS]
},
-#define POWER6_PME_PM_FPU_FCONV 215
[ POWER6_PME_PM_FPU_FCONV ] = {
.pme_name = "PM_FPU_FCONV",
+ .pme_code = 0x1d1034,
.pme_short_desc = "FPU executed FCONV instruction",
.pme_long_desc = "FPU executed FCONV instruction",
- .pme_event_ids = { 102, -1, -1, 107, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000004ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_FCONV],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_FCONV]
},
-#define POWER6_PME_PM_FPU_FXMULT 216
[ POWER6_PME_PM_FPU_FXMULT ] = {
.pme_name = "PM_FPU_FXMULT",
+ .pme_code = 0x1d0032,
.pme_short_desc = "FPU executed fixed point multiplication",
.pme_long_desc = "FPU executed fixed point multiplication",
- .pme_event_ids = { 106, -1, -1, 111, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000001ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_FXMULT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_FXMULT]
},
-#define POWER6_PME_PM_FPU1_FRSP 217
[ POWER6_PME_PM_FPU1_FRSP ] = {
.pme_name = "PM_FPU1_FRSP",
+ .pme_code = 0xd10aa,
.pme_short_desc = "FPU1 executed FRSP instruction",
.pme_long_desc = "FPU1 executed FRSP instruction",
- .pme_event_ids = { 94, 103, 92, 100, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x4000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_FRSP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_FRSP]
},
-#define POWER6_PME_PM_MRK_DERAT_REF_16M 218
[ POWER6_PME_PM_MRK_DERAT_REF_16M ] = {
.pme_name = "PM_MRK_DERAT_REF_16M",
+ .pme_code = 0x382044,
.pme_short_desc = "Marked DERAT reference for 16M page",
.pme_long_desc = "Marked DERAT reference for 16M page",
- .pme_event_ids = { -1, -1, 345, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000001000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DERAT_REF_16M],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DERAT_REF_16M]
},
-#define POWER6_PME_PM_L2SB_CASTOUT_SHR 219
[ POWER6_PME_PM_L2SB_CASTOUT_SHR ] = {
.pme_name = "PM_L2SB_CASTOUT_SHR",
+ .pme_code = 0x5068a,
.pme_short_desc = "L2 slice B castouts - Shared",
.pme_long_desc = "L2 slice B castouts - Shared",
- .pme_event_ids = { 172, 181, 172, 178, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000200000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_CASTOUT_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_CASTOUT_SHR]
},
-#define POWER6_PME_PM_THRD_ONE_RUN_COUNT 220
[ POWER6_PME_PM_THRD_ONE_RUN_COUNT ] = {
.pme_name = "PM_THRD_ONE_RUN_COUNT",
+ .pme_code = 0x1000fb,
.pme_short_desc = "Periods one of the threads in run cycles",
.pme_long_desc = "Periods one of the threads in run cycles",
- .pme_event_ids = { 344, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000800000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_ONE_RUN_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_ONE_RUN_COUNT]
},
-#define POWER6_PME_PM_INST_FROM_RMEM 221
[ POWER6_PME_PM_INST_FROM_RMEM ] = {
.pme_name = "PM_INST_FROM_RMEM",
+ .pme_code = 0x342042,
.pme_short_desc = "Instruction fetched from remote memory",
.pme_long_desc = "Instruction fetched from remote memory",
- .pme_event_ids = { -1, -1, 147, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000002000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_RMEM],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_RMEM]
},
-#define POWER6_PME_PM_LSU_BOTH_BUS 222
[ POWER6_PME_PM_LSU_BOTH_BUS ] = {
.pme_name = "PM_LSU_BOTH_BUS",
+ .pme_code = 0x810aa,
.pme_short_desc = "Both data return buses busy simultaneously",
.pme_long_desc = "Both data return buses busy simultaneously",
- .pme_event_ids = { 233, 242, 228, 233, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000200ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_BOTH_BUS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_BOTH_BUS]
},
-#define POWER6_PME_PM_FPU1_FSQRT_FDIV 223
[ POWER6_PME_PM_FPU1_FSQRT_FDIV ] = {
.pme_name = "PM_FPU1_FSQRT_FDIV",
+ .pme_code = 0xc008c,
.pme_short_desc = "FPU1 executed FSQRT or FDIV instruction",
.pme_long_desc = "FPU1 executed FSQRT or FDIV instruction",
- .pme_event_ids = { 95, 104, 93, 101, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0800000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_FSQRT_FDIV],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_FSQRT_FDIV]
},
-#define POWER6_PME_PM_L2_LD_REQ_INST 224
[ POWER6_PME_PM_L2_LD_REQ_INST ] = {
.pme_name = "PM_L2_LD_REQ_INST",
+ .pme_code = 0x150530,
.pme_short_desc = "L2 instruction load requests",
.pme_long_desc = "L2 instruction load requests",
- .pme_event_ids = { 187, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000004000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2_LD_REQ_INST],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2_LD_REQ_INST]
},
-#define POWER6_PME_PM_MRK_PTEG_FROM_L35_SHR 225
[ POWER6_PME_PM_MRK_PTEG_FROM_L35_SHR ] = {
.pme_name = "PM_MRK_PTEG_FROM_L35_SHR",
+ .pme_code = 0x212046,
.pme_short_desc = "Marked PTEG loaded from L3.5 shared",
.pme_long_desc = "Marked PTEG loaded from L3.5 shared",
- .pme_event_ids = { -1, 291, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000010000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_L35_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_L35_SHR]
},
-#define POWER6_PME_PM_BR_PRED_CR 226
[ POWER6_PME_PM_BR_PRED_CR ] = {
.pme_name = "PM_BR_PRED_CR",
+ .pme_code = 0x410a2,
.pme_short_desc = "A conditional branch was predicted",
.pme_long_desc = " CR prediction",
- .pme_event_ids = { 10, 8, 8, 10, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000014ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_BR_PRED_CR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_BR_PRED_CR]
},
-#define POWER6_PME_PM_MRK_LSU0_REJECT_ULD 227
[ POWER6_PME_PM_MRK_LSU0_REJECT_ULD ] = {
.pme_name = "PM_MRK_LSU0_REJECT_ULD",
+ .pme_code = 0x930e0,
.pme_short_desc = "LSU0 marked unaligned load reject",
.pme_long_desc = "LSU0 marked unaligned load reject",
- .pme_event_ids = { 271, 283, 265, 266, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000020000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU0_REJECT_ULD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU0_REJECT_ULD]
},
-#define POWER6_PME_PM_LSU_REJECT 228
[ POWER6_PME_PM_LSU_REJECT ] = {
.pme_name = "PM_LSU_REJECT",
+ .pme_code = 0x4a1030,
.pme_short_desc = "LSU reject",
.pme_long_desc = "LSU reject",
- .pme_event_ids = { -1, -1, -1, 238, -1, -1 },
- .pme_group_vector = {
- 0x0800000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT]
},
-#define POWER6_PME_PM_LSU_REJECT_LHS_BOTH 229
[ POWER6_PME_PM_LSU_REJECT_LHS_BOTH ] = {
.pme_name = "PM_LSU_REJECT_LHS_BOTH",
+ .pme_code = 0x290038,
.pme_short_desc = "Load hit store reject both units",
.pme_long_desc = "Load hit store reject both units",
- .pme_event_ids = { -1, 250, -1, 241, -1, -1 },
- .pme_group_vector = {
- 0x1000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_LHS_BOTH],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_LHS_BOTH]
},
-#define POWER6_PME_PM_GXO_ADDR_CYC_BUSY 230
[ POWER6_PME_PM_GXO_ADDR_CYC_BUSY ] = {
.pme_name = "PM_GXO_ADDR_CYC_BUSY",
+ .pme_code = 0x50382,
.pme_short_desc = "Outbound GX address utilization (# of cycles address out is valid)",
.pme_long_desc = "Outbound GX address utilization (# of cycles address out is valid)",
- .pme_event_ids = { 125, 132, 123, 131, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000200000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_GXO_ADDR_CYC_BUSY],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GXO_ADDR_CYC_BUSY]
},
-#define POWER6_PME_PM_LSU_SRQ_EMPTY_COUNT 231
[ POWER6_PME_PM_LSU_SRQ_EMPTY_COUNT ] = {
.pme_name = "PM_LSU_SRQ_EMPTY_COUNT",
+ .pme_code = 0x40001d,
.pme_short_desc = "Periods SRQ empty",
.pme_long_desc = "The Store Request Queue is empty",
- .pme_event_ids = { -1, -1, -1, 341, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0008000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_SRQ_EMPTY_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_SRQ_EMPTY_COUNT]
},
-#define POWER6_PME_PM_PTEG_FROM_L3 232
[ POWER6_PME_PM_PTEG_FROM_L3 ] = {
.pme_name = "PM_PTEG_FROM_L3",
+ .pme_code = 0x313048,
.pme_short_desc = "PTEG loaded from L3",
.pme_long_desc = "PTEG loaded from L3",
- .pme_event_ids = { -1, -1, 292, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000010000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_L3],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_L3]
},
-#define POWER6_PME_PM_VMX0_LD_ISSUED 233
[ POWER6_PME_PM_VMX0_LD_ISSUED ] = {
.pme_name = "PM_VMX0_LD_ISSUED",
+ .pme_code = 0x60082,
.pme_short_desc = "VMX0 load issued",
.pme_long_desc = "VMX0 load issued",
- .pme_event_ids = { 322, 329, 316, 314, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000600000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX0_LD_ISSUED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX0_LD_ISSUED]
},
-#define POWER6_PME_PM_FXU_PIPELINED_MULT_DIV 234
[ POWER6_PME_PM_FXU_PIPELINED_MULT_DIV ] = {
.pme_name = "PM_FXU_PIPELINED_MULT_DIV",
+ .pme_code = 0x210ae,
.pme_short_desc = "Fix point multiply/divide pipelined",
.pme_long_desc = "Fix point multiply/divide pipelined",
- .pme_event_ids = { 118, 126, 118, 126, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000080000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FXU_PIPELINED_MULT_DIV],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FXU_PIPELINED_MULT_DIV]
},
-#define POWER6_PME_PM_FPU1_STF 235
[ POWER6_PME_PM_FPU1_STF ] = {
.pme_name = "PM_FPU1_STF",
+ .pme_code = 0xc10ac,
.pme_short_desc = "FPU1 executed store instruction",
.pme_long_desc = "This signal is active for one cycle when fp1 is executing a store instruction.",
- .pme_event_ids = { 99, 108, 97, 105, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0800000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_STF],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_STF]
},
-#define POWER6_PME_PM_DFU_ADD 236
[ POWER6_PME_PM_DFU_ADD ] = {
.pme_name = "PM_DFU_ADD",
+ .pme_code = 0xe008c,
.pme_short_desc = "DFU add type instruction",
.pme_long_desc = "DFU add type instruction",
- .pme_event_ids = { 23, 30, 22, 30, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000002000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DFU_ADD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DFU_ADD]
},
-#define POWER6_PME_PM_MEM_DP_CL_WR_GLOB 237
[ POWER6_PME_PM_MEM_DP_CL_WR_GLOB ] = {
.pme_name = "PM_MEM_DP_CL_WR_GLOB",
+ .pme_code = 0x250232,
.pme_short_desc = "cache line write setting double pump state to global",
.pme_long_desc = "cache line write setting double pump state to global",
- .pme_event_ids = { -1, 267, 250, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000040000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM_DP_CL_WR_GLOB],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM_DP_CL_WR_GLOB]
},
-#define POWER6_PME_PM_MRK_LSU1_REJECT_ULD 238
[ POWER6_PME_PM_MRK_LSU1_REJECT_ULD ] = {
.pme_name = "PM_MRK_LSU1_REJECT_ULD",
+ .pme_code = 0x930e8,
.pme_short_desc = "LSU1 marked unaligned load reject",
.pme_long_desc = "LSU1 marked unaligned load reject",
- .pme_event_ids = { 274, 286, 268, 269, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000040000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU1_REJECT_ULD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU1_REJECT_ULD]
},
-#define POWER6_PME_PM_ITLB_REF 239
[ POWER6_PME_PM_ITLB_REF ] = {
.pme_name = "PM_ITLB_REF",
+ .pme_code = 0x920c2,
.pme_short_desc = "Instruction TLB reference",
.pme_long_desc = "Instruction TLB reference",
- .pme_event_ids = { 153, 162, 153, 159, -1, -1 },
- .pme_group_vector = {
- 0x0200000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_ITLB_REF],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_ITLB_REF]
},
-#define POWER6_PME_PM_LSU0_REJECT_L2MISS 240
[ POWER6_PME_PM_LSU0_REJECT_L2MISS ] = {
.pme_name = "PM_LSU0_REJECT_L2MISS",
+ .pme_code = 0x90084,
.pme_short_desc = "LSU0 L2 miss reject",
.pme_long_desc = "LSU0 L2 miss reject",
- .pme_event_ids = { 211, 220, 206, 211, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000400ULL,
- 0x0000008000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT_L2MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT_L2MISS]
},
-#define POWER6_PME_PM_DATA_FROM_L35_SHR 241
[ POWER6_PME_PM_DATA_FROM_L35_SHR ] = {
.pme_name = "PM_DATA_FROM_L35_SHR",
+ .pme_code = 0x20005a,
.pme_short_desc = "Data loaded from L3.5 shared",
.pme_long_desc = "Data loaded from L3.5 shared",
- .pme_event_ids = { -1, 19, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000300ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000001ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L35_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L35_SHR]
},
-#define POWER6_PME_PM_MRK_DATA_FROM_RL2L3_MOD 242
[ POWER6_PME_PM_MRK_DATA_FROM_RL2L3_MOD ] = {
.pme_name = "PM_MRK_DATA_FROM_RL2L3_MOD",
+ .pme_code = 0x10304c,
.pme_short_desc = "Marked data loaded from remote L2 or L3 modified",
.pme_long_desc = "Marked data loaded from remote L2 or L3 modified",
- .pme_event_ids = { 263, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000008000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_RL2L3_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_RL2L3_MOD]
},
-#define POWER6_PME_PM_FPU0_FPSCR 243
[ POWER6_PME_PM_FPU0_FPSCR ] = {
.pme_name = "PM_FPU0_FPSCR",
+ .pme_code = 0xd0084,
.pme_short_desc = "FPU0 executed FPSCR instruction",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing fpscr move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*. mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs",
- .pme_event_ids = { 78, 87, 76, 84, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0200000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_FPSCR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_FPSCR]
},
-#define POWER6_PME_PM_DATA_FROM_L2 244
[ POWER6_PME_PM_DATA_FROM_L2 ] = {
.pme_name = "PM_DATA_FROM_L2",
+ .pme_code = 0x100058,
.pme_short_desc = "Data loaded from L2",
.pme_long_desc = "DL1 was reloaded from the local L2 due to a demand load",
- .pme_event_ids = { 13, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000040080ULL,
- 0x0000000000000000ULL,
- 0x8000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L2],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L2]
},
-#define POWER6_PME_PM_DPU_HELD_XER 245
[ POWER6_PME_PM_DPU_HELD_XER ] = {
.pme_name = "PM_DPU_HELD_XER",
+ .pme_code = 0x20088,
.pme_short_desc = "DISP unit held due to XER dependency",
.pme_long_desc = "DISP unit held due to XER dependency",
- .pme_event_ids = { 54, 62, 52, 60, -1, -1 },
- .pme_group_vector = {
- 0x0000004000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_XER],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_XER]
},
-#define POWER6_PME_PM_FAB_NODE_PUMP 246
[ POWER6_PME_PM_FAB_NODE_PUMP ] = {
.pme_name = "PM_FAB_NODE_PUMP",
+ .pme_code = 0x50188,
.pme_short_desc = "Node pump operation",
.pme_long_desc = " locally mastered",
- .pme_event_ids = { 63, 73, 62, 69, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000010000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FAB_NODE_PUMP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FAB_NODE_PUMP]
},
-#define POWER6_PME_PM_VMX_RESULT_SAT_0_1 247
[ POWER6_PME_PM_VMX_RESULT_SAT_0_1 ] = {
.pme_name = "PM_VMX_RESULT_SAT_0_1",
+ .pme_code = 0xb008e,
.pme_short_desc = "VMX valid result with sat bit is set (0->1)",
.pme_long_desc = "VMX valid result with sat bit is set (0->1)",
- .pme_event_ids = { 333, 340, 327, 325, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000800000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX_RESULT_SAT_0_1],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX_RESULT_SAT_0_1]
},
-#define POWER6_PME_PM_LD_REF_L1 248
[ POWER6_PME_PM_LD_REF_L1 ] = {
.pme_name = "PM_LD_REF_L1",
+ .pme_code = 0x80082,
.pme_short_desc = "L1 D cache load references",
.pme_long_desc = "Total DL1 Load references",
- .pme_event_ids = { 201, 212, 198, 203, -1, -1 },
- .pme_group_vector = {
- 0x0000c00000000000ULL,
- 0x0000000000000000ULL,
- 0x2080000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LD_REF_L1],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LD_REF_L1]
},
-#define POWER6_PME_PM_TLB_REF 249
[ POWER6_PME_PM_TLB_REF ] = {
.pme_name = "PM_TLB_REF",
+ .pme_code = 0x920c8,
.pme_short_desc = "TLB reference",
.pme_long_desc = "TLB reference",
- .pme_event_ids = { 320, 327, 314, 312, -1, -1 },
- .pme_group_vector = {
- 0x0200000100000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_TLB_REF],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_TLB_REF]
},
-#define POWER6_PME_PM_DC_PREF_OUT_OF_STREAMS 250
[ POWER6_PME_PM_DC_PREF_OUT_OF_STREAMS ] = {
.pme_name = "PM_DC_PREF_OUT_OF_STREAMS",
+ .pme_code = 0x810a0,
.pme_short_desc = "D cache out of streams",
.pme_long_desc = "out of streams",
- .pme_event_ids = { 21, 28, 20, 28, -1, -1 },
- .pme_group_vector = {
- 0x0001000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DC_PREF_OUT_OF_STREAMS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DC_PREF_OUT_OF_STREAMS]
},
-#define POWER6_PME_PM_FLUSH_FPU 251
[ POWER6_PME_PM_FLUSH_FPU ] = {
.pme_name = "PM_FLUSH_FPU",
+ .pme_code = 0x230ec,
.pme_short_desc = "Flush caused by FPU exception",
.pme_long_desc = "Flush caused by FPU exception",
- .pme_event_ids = { 69, 78, 67, 75, -1, -1 },
- .pme_group_vector = {
- 0x0002000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FLUSH_FPU],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FLUSH_FPU]
},
-#define POWER6_PME_PM_MEM1_DP_CL_WR_LOC 252
[ POWER6_PME_PM_MEM1_DP_CL_WR_LOC ] = {
.pme_name = "PM_MEM1_DP_CL_WR_LOC",
+ .pme_code = 0x5028e,
.pme_short_desc = "cacheline write setting dp to local side 1",
.pme_long_desc = "cacheline write setting dp to local side 1",
- .pme_event_ids = { 253, 264, 247, 252, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000100000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM1_DP_CL_WR_LOC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM1_DP_CL_WR_LOC]
},
-#define POWER6_PME_PM_L2SB_LD_HIT 253
[ POWER6_PME_PM_L2SB_LD_HIT ] = {
.pme_name = "PM_L2SB_LD_HIT",
+ .pme_code = 0x5078a,
.pme_short_desc = "L2 slice B load hits",
.pme_long_desc = "L2 slice B load hits",
- .pme_event_ids = { 175, 184, 175, 181, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000800000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_LD_HIT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_LD_HIT]
},
-#define POWER6_PME_PM_FAB_DCLAIM 254
[ POWER6_PME_PM_FAB_DCLAIM ] = {
.pme_name = "PM_FAB_DCLAIM",
+ .pme_code = 0x50184,
.pme_short_desc = "Dclaim operation",
.pme_long_desc = " locally mastered",
- .pme_event_ids = { 60, 70, 59, 66, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000008000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FAB_DCLAIM],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FAB_DCLAIM]
},
-#define POWER6_PME_PM_MEM_DP_CL_WR_LOC 255
[ POWER6_PME_PM_MEM_DP_CL_WR_LOC ] = {
.pme_name = "PM_MEM_DP_CL_WR_LOC",
+ .pme_code = 0x150232,
.pme_short_desc = "cache line write setting double pump state to local",
.pme_long_desc = "cache line write setting double pump state to local",
- .pme_event_ids = { 256, -1, -1, 255, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000040000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM_DP_CL_WR_LOC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM_DP_CL_WR_LOC]
},
-#define POWER6_PME_PM_BR_MPRED_CR 256
[ POWER6_PME_PM_BR_MPRED_CR ] = {
.pme_name = "PM_BR_MPRED_CR",
+ .pme_code = 0x410a8,
.pme_short_desc = "Branch mispredictions due to CR bit setting",
.pme_long_desc = "This signal is asserted when the branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This signal is asserted after a branch issue event and will result in a branch redirect flush if not overridden by a flush of an older instruction.",
- .pme_event_ids = { 6, 4, 4, 6, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000024ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_BR_MPRED_CR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_BR_MPRED_CR]
},
-#define POWER6_PME_PM_LSU_REJECT_EXTERN 257
[ POWER6_PME_PM_LSU_REJECT_EXTERN ] = {
.pme_name = "PM_LSU_REJECT_EXTERN",
+ .pme_code = 0x3a1030,
.pme_short_desc = "LSU external reject request ",
.pme_long_desc = "LSU external reject request ",
- .pme_event_ids = { -1, -1, 235, -1, -1, -1 },
- .pme_group_vector = {
- 0x1000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_EXTERN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_EXTERN]
},
-#define POWER6_PME_PM_DATA_FROM_RL2L3_MOD 258
[ POWER6_PME_PM_DATA_FROM_RL2L3_MOD ] = {
.pme_name = "PM_DATA_FROM_RL2L3_MOD",
+ .pme_code = 0x10005c,
.pme_short_desc = "Data loaded from remote L2 or L3 modified",
.pme_long_desc = "Data loaded from remote L2 or L3 modified",
- .pme_event_ids = { 16, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000010400ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_RL2L3_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_RL2L3_MOD]
},
-#define POWER6_PME_PM_DPU_HELD_RU_WQ 259
[ POWER6_PME_PM_DPU_HELD_RU_WQ ] = {
.pme_name = "PM_DPU_HELD_RU_WQ",
+ .pme_code = 0x2008e,
.pme_short_desc = "DISP unit held due to RU FXU write queue full",
.pme_long_desc = "DISP unit held due to RU FXU write queue full",
- .pme_event_ids = { 48, 57, 47, 55, -1, -1 },
- .pme_group_vector = {
- 0x0000084000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_RU_WQ],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_RU_WQ]
},
-#define POWER6_PME_PM_LD_MISS_L1 260
[ POWER6_PME_PM_LD_MISS_L1 ] = {
.pme_name = "PM_LD_MISS_L1",
+ .pme_code = 0x80080,
.pme_short_desc = "L1 D cache load misses",
.pme_long_desc = "Total DL1 Load references that miss the DL1",
- .pme_event_ids = { 199, 210, 197, 202, -1, -1 },
- .pme_group_vector = {
- 0x0000800000000000ULL,
- 0x0000000000000000ULL,
- 0x1080084000000020ULL,
- 0x0000000000000006ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LD_MISS_L1],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LD_MISS_L1]
},
-#define POWER6_PME_PM_DC_INV_L2 261
[ POWER6_PME_PM_DC_INV_L2 ] = {
.pme_name = "PM_DC_INV_L2",
+ .pme_code = 0x150632,
.pme_short_desc = "L1 D cache entries invalidated from L2",
.pme_long_desc = "A dcache invalidated was received from the L2 because a line in L2 was castout.",
- .pme_event_ids = { 20, -1, -1, 27, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000008000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DC_INV_L2],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DC_INV_L2]
},
-#define POWER6_PME_PM_MRK_PTEG_FROM_RMEM 262
[ POWER6_PME_PM_MRK_PTEG_FROM_RMEM ] = {
.pme_name = "PM_MRK_PTEG_FROM_RMEM",
+ .pme_code = 0x312042,
.pme_short_desc = "Marked PTEG loaded from remote memory",
.pme_long_desc = "Marked PTEG loaded from remote memory",
- .pme_event_ids = { -1, -1, 275, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000080000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_RMEM],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_RMEM]
},
-#define POWER6_PME_PM_FPU_FIN 263
[ POWER6_PME_PM_FPU_FIN ] = {
.pme_name = "PM_FPU_FIN",
+ .pme_code = 0x1d0030,
.pme_short_desc = "FPU produced a result",
.pme_long_desc = "FPU finished, produced a result This only indicates finish, not completion. Combined Unit 0 + Unit 1",
- .pme_event_ids = { 103, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x4000000000000001ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_FIN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_FIN]
},
-#define POWER6_PME_PM_FXU0_FIN 264
[ POWER6_PME_PM_FXU0_FIN ] = {
.pme_name = "PM_FXU0_FIN",
+ .pme_code = 0x300016,
.pme_short_desc = "FXU0 produced a result",
.pme_long_desc = "The Fixed Point unit 0 finished an instruction and produced a result",
- .pme_event_ids = { -1, -1, 117, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000080000ULL,
- 0x4000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FXU0_FIN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FXU0_FIN]
},
-#define POWER6_PME_PM_DPU_HELD_FPQ 265
[ POWER6_PME_PM_DPU_HELD_FPQ ] = {
.pme_name = "PM_DPU_HELD_FPQ",
+ .pme_code = 0x20086,
.pme_short_desc = "DISP unit held due to FPU issue queue full",
.pme_long_desc = "DISP unit held due to FPU issue queue full",
- .pme_event_ids = { 34, 42, 33, 41, -1, -1 },
- .pme_group_vector = {
- 0x0000002000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_FPQ],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_FPQ]
},
-#define POWER6_PME_PM_GX_DMA_READ 266
[ POWER6_PME_PM_GX_DMA_READ ] = {
.pme_name = "PM_GX_DMA_READ",
+ .pme_code = 0x5038c,
.pme_short_desc = "DMA Read Request",
.pme_long_desc = "DMA Read Request",
- .pme_event_ids = { 128, 135, 126, 134, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000800000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_GX_DMA_READ],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GX_DMA_READ]
},
-#define POWER6_PME_PM_LSU1_REJECT_PARTIAL_SECTOR 267
[ POWER6_PME_PM_LSU1_REJECT_PARTIAL_SECTOR ] = {
.pme_name = "PM_LSU1_REJECT_PARTIAL_SECTOR",
+ .pme_code = 0xa008e,
.pme_short_desc = "LSU1 reject due to partial sector valid",
.pme_long_desc = "LSU1 reject due to partial sector valid",
- .pme_event_ids = { 228, 237, 223, 228, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000010ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_REJECT_PARTIAL_SECTOR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_REJECT_PARTIAL_SECTOR]
},
-#define POWER6_PME_PM_0INST_FETCH_COUNT 268
[ POWER6_PME_PM_0INST_FETCH_COUNT ] = {
.pme_name = "PM_0INST_FETCH_COUNT",
+ .pme_code = 0x40081,
.pme_short_desc = "Periods with no instructions fetched",
.pme_long_desc = "No instructions were fetched this periods (due to IFU hold, redirect, or icache miss)",
- .pme_event_ids = { 337, 344, 331, 329, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000100000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_0INST_FETCH_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_0INST_FETCH_COUNT]
},
-#define POWER6_PME_PM_PMC5_OVERFLOW 269
[ POWER6_PME_PM_PMC5_OVERFLOW ] = {
.pme_name = "PM_PMC5_OVERFLOW",
+ .pme_code = 0x100024,
.pme_short_desc = "PMC5 Overflow",
.pme_long_desc = "PMC5 Overflow",
- .pme_event_ids = { 294, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PMC5_OVERFLOW],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PMC5_OVERFLOW]
},
-#define POWER6_PME_PM_L2SB_LD_REQ 270
[ POWER6_PME_PM_L2SB_LD_REQ ] = {
.pme_name = "PM_L2SB_LD_REQ",
+ .pme_code = 0x50788,
.pme_short_desc = "L2 slice B load requests ",
.pme_long_desc = "L2 slice B load requests ",
- .pme_event_ids = { 178, 187, 178, 184, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000800000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_LD_REQ],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_LD_REQ]
},
-#define POWER6_PME_PM_THRD_PRIO_DIFF_0_CYC 271
[ POWER6_PME_PM_THRD_PRIO_DIFF_0_CYC ] = {
.pme_name = "PM_THRD_PRIO_DIFF_0_CYC",
+ .pme_code = 0x123040,
.pme_short_desc = "Cycles no thread priority difference",
.pme_long_desc = "Cycles no thread priority difference",
- .pme_event_ids = { 318, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000010000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_DIFF_0_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_DIFF_0_CYC]
},
-#define POWER6_PME_PM_DATA_FROM_RMEM 272
[ POWER6_PME_PM_DATA_FROM_RMEM ] = {
.pme_name = "PM_DATA_FROM_RMEM",
+ .pme_code = 0x30005e,
.pme_short_desc = "Data loaded from remote memory",
.pme_long_desc = "Data loaded from remote memory",
- .pme_event_ids = { -1, -1, 16, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000004800ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_RMEM],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_RMEM]
},
-#define POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC 273
[ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC ] = {
.pme_name = "PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC",
+ .pme_code = 0x30001c,
.pme_short_desc = "Cycles both threads LMQ and SRQ empty",
.pme_long_desc = "Cycles both threads LMQ and SRQ empty",
- .pme_event_ids = { -1, -1, 234, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000400ULL,
- 0x0010000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC]
},
-#define POWER6_PME_PM_ST_REF_L1_BOTH 274
[ POWER6_PME_PM_ST_REF_L1_BOTH ] = {
.pme_name = "PM_ST_REF_L1_BOTH",
+ .pme_code = 0x280038,
.pme_short_desc = "Both units L1 D cache store reference",
.pme_long_desc = "Both units L1 D cache store reference",
- .pme_event_ids = { -1, 316, -1, 301, -1, -1 },
- .pme_group_vector = {
- 0x0000400000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_ST_REF_L1_BOTH],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_ST_REF_L1_BOTH]
},
-#define POWER6_PME_PM_VMX_PERMUTE_ISSUED 275
[ POWER6_PME_PM_VMX_PERMUTE_ISSUED ] = {
.pme_name = "PM_VMX_PERMUTE_ISSUED",
+ .pme_code = 0x70086,
.pme_short_desc = "VMX instruction issued to permute",
.pme_long_desc = "VMX instruction issued to permute",
- .pme_event_ids = { 332, 339, 326, 324, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000100000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX_PERMUTE_ISSUED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX_PERMUTE_ISSUED]
},
-#define POWER6_PME_PM_BR_TAKEN 276
[ POWER6_PME_PM_BR_TAKEN ] = {
.pme_name = "PM_BR_TAKEN",
+ .pme_code = 0x200052,
.pme_short_desc = "Branches taken",
.pme_long_desc = "Branches taken",
- .pme_event_ids = { -1, 10, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000040ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_BR_TAKEN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_BR_TAKEN]
},
-#define POWER6_PME_PM_FAB_DMA 277
[ POWER6_PME_PM_FAB_DMA ] = {
.pme_name = "PM_FAB_DMA",
+ .pme_code = 0x5018c,
.pme_short_desc = "DMA operation",
.pme_long_desc = " locally mastered",
- .pme_event_ids = { 61, 71, 60, 67, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000008000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FAB_DMA],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FAB_DMA]
},
-#define POWER6_PME_PM_GCT_EMPTY_COUNT 278
[ POWER6_PME_PM_GCT_EMPTY_COUNT ] = {
.pme_name = "PM_GCT_EMPTY_COUNT",
+ .pme_code = 0x200009,
.pme_short_desc = "Periods GCT empty",
.pme_long_desc = "The Global Completion Table is completely empty.",
- .pme_event_ids = { -1, 358, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0008010000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_GCT_EMPTY_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GCT_EMPTY_COUNT]
},
-#define POWER6_PME_PM_FPU1_SINGLE 279
[ POWER6_PME_PM_FPU1_SINGLE ] = {
.pme_name = "PM_FPU1_SINGLE",
+ .pme_code = 0xc10ae,
.pme_short_desc = "FPU1 executed single precision instruction",
.pme_long_desc = "This signal is active for one cycle when fp1 is executing single precision instruction.",
- .pme_event_ids = { 98, 107, 96, 104, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x1000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_SINGLE],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_SINGLE]
},
-#define POWER6_PME_PM_L2SA_CASTOUT_SHR 280
[ POWER6_PME_PM_L2SA_CASTOUT_SHR ] = {
.pme_name = "PM_L2SA_CASTOUT_SHR",
+ .pme_code = 0x50682,
.pme_short_desc = "L2 slice A castouts - Shared",
.pme_long_desc = "L2 slice A castouts - Shared",
- .pme_event_ids = { 158, 167, 158, 164, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000200000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_CASTOUT_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_CASTOUT_SHR]
},
-#define POWER6_PME_PM_L3SB_REF 281
[ POWER6_PME_PM_L3SB_REF ] = {
.pme_name = "PM_L3SB_REF",
+ .pme_code = 0x50088,
.pme_short_desc = "L3 slice B references",
.pme_long_desc = "L3 slice B references",
- .pme_event_ids = { 196, 206, 194, 199, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0008000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L3SB_REF],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L3SB_REF]
},
-#define POWER6_PME_PM_FPU0_FRSP 282
[ POWER6_PME_PM_FPU0_FRSP ] = {
.pme_name = "PM_FPU0_FRSP",
+ .pme_code = 0xd10a2,
.pme_short_desc = "FPU0 executed FRSP instruction",
.pme_long_desc = "FPU0 executed FRSP instruction",
- .pme_event_ids = { 79, 88, 77, 85, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0400000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_FRSP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_FRSP]
},
-#define POWER6_PME_PM_PMC4_SAVED 283
[ POWER6_PME_PM_PMC4_SAVED ] = {
.pme_name = "PM_PMC4_SAVED",
+ .pme_code = 0x300022,
.pme_short_desc = "PMC4 rewind value saved",
.pme_long_desc = "PMC4 rewind value saved",
- .pme_event_ids = { -1, -1, 288, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PMC4_SAVED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PMC4_SAVED]
},
-#define POWER6_PME_PM_L2SA_DC_INV 284
[ POWER6_PME_PM_L2SA_DC_INV ] = {
.pme_name = "PM_L2SA_DC_INV",
+ .pme_code = 0x50686,
.pme_short_desc = "L2 slice A D cache invalidate",
.pme_long_desc = "L2 slice A D cache invalidate",
- .pme_event_ids = { 159, 168, 159, 165, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000400000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_DC_INV],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_DC_INV]
},
-#define POWER6_PME_PM_GXI_ADDR_CYC_BUSY 285
[ POWER6_PME_PM_GXI_ADDR_CYC_BUSY ] = {
.pme_name = "PM_GXI_ADDR_CYC_BUSY",
+ .pme_code = 0x50388,
.pme_short_desc = "Inbound GX address utilization (# of cycle address is in valid)",
.pme_long_desc = "Inbound GX address utilization (# of cycle address is in valid)",
- .pme_event_ids = { 122, 129, 120, 128, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000400000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_GXI_ADDR_CYC_BUSY],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GXI_ADDR_CYC_BUSY]
},
-#define POWER6_PME_PM_FPU0_FMA 286
[ POWER6_PME_PM_FPU0_FMA ] = {
.pme_name = "PM_FPU0_FMA",
+ .pme_code = 0xc0082,
.pme_short_desc = "FPU0 executed multiply-add instruction",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 77, 86, 75, 83, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0080000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_FMA],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_FMA]
},
-#define POWER6_PME_PM_SLB_MISS 287
[ POWER6_PME_PM_SLB_MISS ] = {
.pme_name = "PM_SLB_MISS",
+ .pme_code = 0x183034,
.pme_short_desc = "SLB misses",
.pme_long_desc = "SLB misses",
- .pme_event_ids = { 303, -1, -1, 294, -1, -1 },
- .pme_group_vector = {
- 0x0400000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_SLB_MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_SLB_MISS]
},
-#define POWER6_PME_PM_MRK_ST_GPS 288
[ POWER6_PME_PM_MRK_ST_GPS ] = {
.pme_name = "PM_MRK_ST_GPS",
+ .pme_code = 0x200006,
.pme_short_desc = "Marked store sent to GPS",
.pme_long_desc = "A sampled store has been sent to the memory subsystem",
- .pme_event_ids = { -1, 294, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000002000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_ST_GPS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_ST_GPS]
},
-#define POWER6_PME_PM_DERAT_REF_4K 289
[ POWER6_PME_PM_DERAT_REF_4K ] = {
.pme_name = "PM_DERAT_REF_4K",
+ .pme_code = 0x182070,
.pme_short_desc = "DERAT reference for 4K page",
.pme_long_desc = "DERAT reference for 4K page",
- .pme_event_ids = { 350, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000080ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DERAT_REF_4K],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DERAT_REF_4K]
},
-#define POWER6_PME_PM_L2_CASTOUT_SHR 290
[ POWER6_PME_PM_L2_CASTOUT_SHR ] = {
.pme_name = "PM_L2_CASTOUT_SHR",
+ .pme_code = 0x250630,
.pme_short_desc = "L2 castouts - Shared (T",
.pme_long_desc = " Te",
- .pme_event_ids = { -1, 194, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000008000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2_CASTOUT_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2_CASTOUT_SHR]
},
-#define POWER6_PME_PM_DPU_HELD_STCX_CR 291
[ POWER6_PME_PM_DPU_HELD_STCX_CR ] = {
.pme_name = "PM_DPU_HELD_STCX_CR",
+ .pme_code = 0x2008c,
.pme_short_desc = "DISP unit held due to STCX updating CR ",
.pme_long_desc = "DISP unit held due to STCX updating CR ",
- .pme_event_ids = { 51, 60, 50, 58, -1, -1 },
- .pme_group_vector = {
- 0x0000084000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_STCX_CR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_STCX_CR]
},
-#define POWER6_PME_PM_FPU0_ST_FOLDED 292
[ POWER6_PME_PM_FPU0_ST_FOLDED ] = {
.pme_name = "PM_FPU0_ST_FOLDED",
+ .pme_code = 0xd10a4,
.pme_short_desc = "FPU0 folded store",
.pme_long_desc = "FPU0 folded store",
- .pme_event_ids = { 85, 94, 83, 91, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0400000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_ST_FOLDED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_ST_FOLDED]
},
-#define POWER6_PME_PM_MRK_DATA_FROM_L21 293
[ POWER6_PME_PM_MRK_DATA_FROM_L21 ] = {
.pme_name = "PM_MRK_DATA_FROM_L21",
+ .pme_code = 0x203048,
.pme_short_desc = "Marked data loaded from private L2 other core",
.pme_long_desc = "Marked data loaded from private L2 other core",
- .pme_event_ids = { -1, 270, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000800ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_L21],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_L21]
},
-#define POWER6_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC 294
[ POWER6_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC ] = {
.pme_name = "PM_THRD_PRIO_DIFF_minus3or4_CYC",
+ .pme_code = 0x323046,
.pme_short_desc = "Cycles thread priority difference is -3 or -4",
.pme_long_desc = "Cycles thread priority difference is -3 or -4",
- .pme_event_ids = { -1, -1, 311, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000020000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC]
},
-#define POWER6_PME_PM_DATA_FROM_L35_MOD 295
[ POWER6_PME_PM_DATA_FROM_L35_MOD ] = {
.pme_name = "PM_DATA_FROM_L35_MOD",
+ .pme_code = 0x10005a,
.pme_short_desc = "Data loaded from L3.5 modified",
.pme_long_desc = "Data loaded from L3.5 modified",
- .pme_event_ids = { 14, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000208300ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000001ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L35_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L35_MOD]
},
-#define POWER6_PME_PM_DATA_FROM_DL2L3_SHR 296
[ POWER6_PME_PM_DATA_FROM_DL2L3_SHR ] = {
.pme_name = "PM_DATA_FROM_DL2L3_SHR",
+ .pme_code = 0x30005c,
.pme_short_desc = "Data loaded from distant L2 or L3 shared",
.pme_long_desc = "Data loaded from distant L2 or L3 shared",
- .pme_event_ids = { -1, -1, 11, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000008400ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_DL2L3_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_DL2L3_SHR]
},
-#define POWER6_PME_PM_GXI_DATA_CYC_BUSY 297
[ POWER6_PME_PM_GXI_DATA_CYC_BUSY ] = {
.pme_name = "PM_GXI_DATA_CYC_BUSY",
+ .pme_code = 0x5038a,
.pme_short_desc = "Inbound GX Data utilization (# of cycle data in is valid)",
.pme_long_desc = "Inbound GX Data utilization (# of cycle data in is valid)",
- .pme_event_ids = { 124, 131, 122, 130, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000400000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_GXI_DATA_CYC_BUSY],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GXI_DATA_CYC_BUSY]
},
-#define POWER6_PME_PM_LSU_REJECT_STEAL 298
[ POWER6_PME_PM_LSU_REJECT_STEAL ] = {
.pme_name = "PM_LSU_REJECT_STEAL",
+ .pme_code = 0x9008c,
.pme_short_desc = "LSU reject due to steal",
.pme_long_desc = "LSU reject due to steal",
- .pme_event_ids = { 242, 254, 239, 243, -1, -1 },
- .pme_group_vector = {
- 0x1000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_STEAL],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_STEAL]
},
-#define POWER6_PME_PM_ST_FIN 299
[ POWER6_PME_PM_ST_FIN ] = {
.pme_name = "PM_ST_FIN",
+ .pme_code = 0x100054,
.pme_short_desc = "Store instructions finished",
.pme_long_desc = "Store instructions finished",
- .pme_event_ids = { 307, 313, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0100000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_ST_FIN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_ST_FIN]
},
-#define POWER6_PME_PM_DPU_HELD_CR_LOGICAL 300
[ POWER6_PME_PM_DPU_HELD_CR_LOGICAL ] = {
.pme_name = "PM_DPU_HELD_CR_LOGICAL",
+ .pme_code = 0x3008e,
.pme_short_desc = "DISP unit held due to CR",
.pme_long_desc = " LR or CTR updated by CR logical",
- .pme_event_ids = { 32, 40, 31, 39, -1, -1 },
- .pme_group_vector = {
- 0x0000040000000000ULL,
- 0x0000000000000000ULL,
- 0x0300000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_CR_LOGICAL],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_CR_LOGICAL]
},
-#define POWER6_PME_PM_THRD_SEL_T0 301
[ POWER6_PME_PM_THRD_SEL_T0 ] = {
.pme_name = "PM_THRD_SEL_T0",
+ .pme_code = 0x310a6,
.pme_short_desc = "Decode selected thread 0",
.pme_long_desc = "Decode selected thread 0",
- .pme_event_ids = { 319, 326, 312, 311, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000020000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_SEL_T0],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_SEL_T0]
},
-#define POWER6_PME_PM_PTEG_RELOAD_VALID 302
[ POWER6_PME_PM_PTEG_RELOAD_VALID ] = {
.pme_name = "PM_PTEG_RELOAD_VALID",
+ .pme_code = 0x130e8,
.pme_short_desc = "TLB reload valid",
.pme_long_desc = "TLB reload valid",
- .pme_event_ids = { 300, 308, 295, 292, -1, -1 },
- .pme_group_vector = {
- 0x0000000080000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_RELOAD_VALID],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_RELOAD_VALID]
},
-#define POWER6_PME_PM_L2_PREF_ST 303
[ POWER6_PME_PM_L2_PREF_ST ] = {
.pme_name = "PM_L2_PREF_ST",
+ .pme_code = 0x810a8,
.pme_short_desc = "L2 cache prefetches",
.pme_long_desc = "L2 cache prefetches",
- .pme_event_ids = { 189, 199, 187, 192, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0002000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2_PREF_ST],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2_PREF_ST]
},
-#define POWER6_PME_PM_MRK_STCX_FAIL 304
[ POWER6_PME_PM_MRK_STCX_FAIL ] = {
.pme_name = "PM_MRK_STCX_FAIL",
+ .pme_code = 0x830e4,
.pme_short_desc = "Marked STCX failed",
.pme_long_desc = "A marked stcx (stwcx or stdcx) failed",
- .pme_event_ids = { 281, 293, 276, 279, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000400000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_STCX_FAIL],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_STCX_FAIL]
},
-#define POWER6_PME_PM_LSU0_REJECT_LHS 305
[ POWER6_PME_PM_LSU0_REJECT_LHS ] = {
.pme_name = "PM_LSU0_REJECT_LHS",
+ .pme_code = 0x90086,
.pme_short_desc = "LSU0 load hit store reject",
.pme_long_desc = "LSU0 load hit store reject",
- .pme_event_ids = { 213, 222, 208, 213, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000020ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT_LHS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT_LHS]
},
-#define POWER6_PME_PM_DFU_EXP_EQ 306
[ POWER6_PME_PM_DFU_EXP_EQ ] = {
.pme_name = "PM_DFU_EXP_EQ",
+ .pme_code = 0xe0084,
.pme_short_desc = "DFU operand exponents are equal for add type",
.pme_long_desc = "DFU operand exponents are equal for add type",
- .pme_event_ids = { 28, 35, 27, 35, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000004000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DFU_EXP_EQ],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DFU_EXP_EQ]
},
-#define POWER6_PME_PM_DPU_HELD_FP_FX_MULT 307
[ POWER6_PME_PM_DPU_HELD_FP_FX_MULT ] = {
.pme_name = "PM_DPU_HELD_FP_FX_MULT",
+ .pme_code = 0x210a8,
.pme_short_desc = "DISP unit held due to non fixed multiple/divide after fixed multiply/divide",
.pme_long_desc = "DISP unit held due to non fixed multiple/divide after fixed multiply/divide",
- .pme_event_ids = { 36, 44, 35, 43, -1, -1 },
- .pme_group_vector = {
- 0x0000010000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_FP_FX_MULT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_FP_FX_MULT]
},
-#define POWER6_PME_PM_L2_LD_MISS_DATA 308
[ POWER6_PME_PM_L2_LD_MISS_DATA ] = {
.pme_name = "PM_L2_LD_MISS_DATA",
+ .pme_code = 0x250430,
.pme_short_desc = "L2 data load misses",
.pme_long_desc = "L2 data load misses",
- .pme_event_ids = { -1, 195, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000002000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2_LD_MISS_DATA],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2_LD_MISS_DATA]
},
-#define POWER6_PME_PM_DATA_FROM_L35_MOD_CYC 309
[ POWER6_PME_PM_DATA_FROM_L35_MOD_CYC ] = {
.pme_name = "PM_DATA_FROM_L35_MOD_CYC",
+ .pme_code = 0x400026,
.pme_short_desc = "Load latency from L3.5 modified",
.pme_long_desc = "Load latency from L3.5 modified",
- .pme_event_ids = { -1, -1, -1, 18, -1, -1 },
- .pme_group_vector = {
- 0x0000000000208000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L35_MOD_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L35_MOD_CYC]
},
-#define POWER6_PME_PM_FLUSH_FXU 310
[ POWER6_PME_PM_FLUSH_FXU ] = {
.pme_name = "PM_FLUSH_FXU",
+ .pme_code = 0x230ea,
.pme_short_desc = "Flush caused by FXU exception",
.pme_long_desc = "Flush caused by FXU exception",
- .pme_event_ids = { 70, 79, 68, 76, -1, -1 },
- .pme_group_vector = {
- 0x0002000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FLUSH_FXU],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FLUSH_FXU]
},
-#define POWER6_PME_PM_FPU_ISSUE_1 311
[ POWER6_PME_PM_FPU_ISSUE_1 ] = {
.pme_name = "PM_FPU_ISSUE_1",
+ .pme_code = 0x320c8,
.pme_short_desc = "FPU issue 1 per cycle",
.pme_long_desc = "FPU issue 1 per cycle",
- .pme_event_ids = { 108, 116, 104, 113, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0010000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_ISSUE_1],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_ISSUE_1]
},
-#define POWER6_PME_PM_DATA_FROM_LMEM_CYC 312
[ POWER6_PME_PM_DATA_FROM_LMEM_CYC ] = {
.pme_name = "PM_DATA_FROM_LMEM_CYC",
+ .pme_code = 0x20002c,
.pme_short_desc = "Load latency from local memory",
.pme_long_desc = "Load latency from local memory",
- .pme_event_ids = { -1, 22, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000102000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_LMEM_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_LMEM_CYC]
},
-#define POWER6_PME_PM_DPU_HELD_LSU_SOPS 313
[ POWER6_PME_PM_DPU_HELD_LSU_SOPS ] = {
.pme_name = "PM_DPU_HELD_LSU_SOPS",
+ .pme_code = 0x30080,
.pme_short_desc = "DISP unit held due to LSU slow ops (sync",
.pme_long_desc = " tlbie",
- .pme_event_ids = { 45, 53, 44, 52, -1, -1 },
- .pme_group_vector = {
- 0x0000200000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_LSU_SOPS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_LSU_SOPS]
},
-#define POWER6_PME_PM_INST_PTEG_2ND_HALF 314
[ POWER6_PME_PM_INST_PTEG_2ND_HALF ] = {
.pme_name = "PM_INST_PTEG_2ND_HALF",
+ .pme_code = 0x910aa,
.pme_short_desc = "Instruction table walk matched in second half primary PTEG",
.pme_long_desc = "Instruction table walk matched in second half primary PTEG",
- .pme_event_ids = { 149, 158, 149, 155, -1, -1 },
- .pme_group_vector = {
- 0x0000000200000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_PTEG_2ND_HALF],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_PTEG_2ND_HALF]
},
-#define POWER6_PME_PM_THRESH_TIMEO 315
[ POWER6_PME_PM_THRESH_TIMEO ] = {
.pme_name = "PM_THRESH_TIMEO",
+ .pme_code = 0x300018,
.pme_short_desc = "Threshold timeout",
.pme_long_desc = "The threshold timer expired",
- .pme_event_ids = { -1, -1, 313, -1, -1, -1 },
- .pme_group_vector = {
- 0x0040000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRESH_TIMEO],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRESH_TIMEO]
},
-#define POWER6_PME_PM_LSU_REJECT_UST_BOTH 316
[ POWER6_PME_PM_LSU_REJECT_UST_BOTH ] = {
.pme_name = "PM_LSU_REJECT_UST_BOTH",
+ .pme_code = 0x190036,
.pme_short_desc = "Unaligned store reject both units",
.pme_long_desc = "Unaligned store reject both units",
- .pme_event_ids = { 245, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x4000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_UST_BOTH],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_UST_BOTH]
},
-#define POWER6_PME_PM_LSU_REJECT_FAST 317
[ POWER6_PME_PM_LSU_REJECT_FAST ] = {
.pme_name = "PM_LSU_REJECT_FAST",
+ .pme_code = 0x30003e,
.pme_short_desc = "LSU fast reject",
.pme_long_desc = "LSU fast reject",
- .pme_event_ids = { -1, -1, 236, -1, -1, -1 },
- .pme_group_vector = {
- 0x0800000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_FAST],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_FAST]
},
-#define POWER6_PME_PM_DPU_HELD_THRD_PRIO 318
[ POWER6_PME_PM_DPU_HELD_THRD_PRIO ] = {
.pme_name = "PM_DPU_HELD_THRD_PRIO",
+ .pme_code = 0x3008a,
.pme_short_desc = "DISP unit held due to lower priority thread",
.pme_long_desc = "DISP unit held due to lower priority thread",
- .pme_event_ids = { 53, 61, 51, 59, -1, -1 },
- .pme_group_vector = {
- 0x0000040000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_THRD_PRIO],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_THRD_PRIO]
},
-#define POWER6_PME_PM_L2_PREF_LD 319
[ POWER6_PME_PM_L2_PREF_LD ] = {
.pme_name = "PM_L2_PREF_LD",
+ .pme_code = 0x810a6,
.pme_short_desc = "L2 cache prefetches",
.pme_long_desc = "L2 cache prefetches",
- .pme_event_ids = { 188, 198, 186, 191, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0002004000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2_PREF_LD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2_PREF_LD]
},
-#define POWER6_PME_PM_FPU_FEST 320
[ POWER6_PME_PM_FPU_FEST ] = {
.pme_name = "PM_FPU_FEST",
+ .pme_code = 0x4d1030,
.pme_short_desc = "FPU executed FEST instruction",
.pme_long_desc = "This signal is active for one cycle when executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. Combined Unit 0 + Unit 1.",
- .pme_event_ids = { -1, -1, -1, 108, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000004ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_FEST],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_FEST]
},
-#define POWER6_PME_PM_MRK_DATA_FROM_RMEM 321
[ POWER6_PME_PM_MRK_DATA_FROM_RMEM ] = {
.pme_name = "PM_MRK_DATA_FROM_RMEM",
+ .pme_code = 0x30304a,
.pme_short_desc = "Marked data loaded from remote memory",
.pme_long_desc = "Marked data loaded from remote memory",
- .pme_event_ids = { -1, -1, 256, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000008000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_RMEM],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_RMEM]
},
-#define POWER6_PME_PM_LD_MISS_L1_CYC 322
[ POWER6_PME_PM_LD_MISS_L1_CYC ] = {
.pme_name = "PM_LD_MISS_L1_CYC",
+ .pme_code = 0x10000c,
.pme_short_desc = "L1 data load miss cycles",
.pme_long_desc = "L1 data load miss cycles",
- .pme_event_ids = { 200, 211, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000001000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000020ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LD_MISS_L1_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LD_MISS_L1_CYC]
},
-#define POWER6_PME_PM_DERAT_MISS_4K 323
[ POWER6_PME_PM_DERAT_MISS_4K ] = {
.pme_name = "PM_DERAT_MISS_4K",
+ .pme_code = 0x192070,
.pme_short_desc = "DERAT misses for 4K page",
.pme_long_desc = "A data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.",
- .pme_event_ids = { 351, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000040ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DERAT_MISS_4K],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DERAT_MISS_4K]
},
-#define POWER6_PME_PM_DPU_HELD_COMPLETION 324
[ POWER6_PME_PM_DPU_HELD_COMPLETION ] = {
.pme_name = "PM_DPU_HELD_COMPLETION",
+ .pme_code = 0x210ac,
.pme_short_desc = "DISP unit held due to completion holding dispatch ",
.pme_long_desc = "DISP unit held due to completion holding dispatch ",
- .pme_event_ids = { 31, 39, 30, 38, -1, -1 },
- .pme_group_vector = {
- 0x0000110000000000ULL,
- 0x0000000000000000ULL,
- 0x0300000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_COMPLETION],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_COMPLETION]
},
-#define POWER6_PME_PM_FPU_ISSUE_STALL_ST 325
[ POWER6_PME_PM_FPU_ISSUE_STALL_ST ] = {
.pme_name = "PM_FPU_ISSUE_STALL_ST",
+ .pme_code = 0x320ce,
.pme_short_desc = "FPU issue stalled due to store",
.pme_long_desc = "FPU issue stalled due to store",
- .pme_event_ids = { 113, 121, 109, 118, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0060000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_ISSUE_STALL_ST],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_ISSUE_STALL_ST]
},
-#define POWER6_PME_PM_L2SB_DC_INV 326
[ POWER6_PME_PM_L2SB_DC_INV ] = {
.pme_name = "PM_L2SB_DC_INV",
+ .pme_code = 0x5068e,
.pme_short_desc = "L2 slice B D cache invalidate",
.pme_long_desc = "L2 slice B D cache invalidate",
- .pme_event_ids = { 173, 182, 173, 179, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000400000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_DC_INV],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_DC_INV]
},
-#define POWER6_PME_PM_PTEG_FROM_L25_SHR 327
[ POWER6_PME_PM_PTEG_FROM_L25_SHR ] = {
.pme_name = "PM_PTEG_FROM_L25_SHR",
+ .pme_code = 0x41304e,
.pme_short_desc = "PTEG loaded from L2.5 shared",
.pme_long_desc = "PTEG loaded from L2.5 shared",
- .pme_event_ids = { -1, -1, -1, 290, -1, -1 },
- .pme_group_vector = {
- 0x0000000008000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_L25_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_L25_SHR]
},
-#define POWER6_PME_PM_PTEG_FROM_DL2L3_MOD 328
[ POWER6_PME_PM_PTEG_FROM_DL2L3_MOD ] = {
.pme_name = "PM_PTEG_FROM_DL2L3_MOD",
+ .pme_code = 0x41304c,
.pme_short_desc = "PTEG loaded from distant L2 or L3 modified",
.pme_long_desc = "PTEG loaded from distant L2 or L3 modified",
- .pme_event_ids = { -1, -1, -1, 289, -1, -1 },
- .pme_group_vector = {
- 0x0000000010000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_DL2L3_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_DL2L3_MOD]
},
-#define POWER6_PME_PM_FAB_CMD_RETRIED 329
[ POWER6_PME_PM_FAB_CMD_RETRIED ] = {
.pme_name = "PM_FAB_CMD_RETRIED",
+ .pme_code = 0x250130,
.pme_short_desc = "Fabric command retried",
.pme_long_desc = "Fabric command retried",
- .pme_event_ids = { -1, 69, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000028000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FAB_CMD_RETRIED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FAB_CMD_RETRIED]
},
-#define POWER6_PME_PM_BR_PRED_LSTACK 330
[ POWER6_PME_PM_BR_PRED_LSTACK ] = {
.pme_name = "PM_BR_PRED_LSTACK",
+ .pme_code = 0x410a6,
.pme_short_desc = "A conditional branch was predicted",
.pme_long_desc = " link stack",
- .pme_event_ids = { 11, 9, 9, 11, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000018ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_BR_PRED_LSTACK],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_BR_PRED_LSTACK]
},
-#define POWER6_PME_PM_GXO_DATA_CYC_BUSY 331
[ POWER6_PME_PM_GXO_DATA_CYC_BUSY ] = {
.pme_name = "PM_GXO_DATA_CYC_BUSY",
+ .pme_code = 0x50384,
.pme_short_desc = "Outbound GX Data utilization (# of cycles data out is valid)",
.pme_long_desc = "Outbound GX Data utilization (# of cycles data out is valid)",
- .pme_event_ids = { 127, 134, 125, 133, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000200000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_GXO_DATA_CYC_BUSY],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GXO_DATA_CYC_BUSY]
},
-#define POWER6_PME_PM_DFU_SUBNORM 332
[ POWER6_PME_PM_DFU_SUBNORM ] = {
.pme_name = "PM_DFU_SUBNORM",
+ .pme_code = 0xe0086,
.pme_short_desc = "DFU result is a subnormal",
.pme_long_desc = "DFU result is a subnormal",
- .pme_event_ids = { 30, 37, 29, 37, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000004000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DFU_SUBNORM],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DFU_SUBNORM]
},
-#define POWER6_PME_PM_FPU_ISSUE_OOO 333
[ POWER6_PME_PM_FPU_ISSUE_OOO ] = {
.pme_name = "PM_FPU_ISSUE_OOO",
+ .pme_code = 0x320c0,
.pme_short_desc = "FPU issue out-of-order",
.pme_long_desc = "FPU issue out-of-order",
- .pme_event_ids = { 111, 119, 107, 116, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0020000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_ISSUE_OOO],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_ISSUE_OOO]
},
-#define POWER6_PME_PM_LSU_REJECT_ULD_BOTH 334
[ POWER6_PME_PM_LSU_REJECT_ULD_BOTH ] = {
.pme_name = "PM_LSU_REJECT_ULD_BOTH",
+ .pme_code = 0x290036,
.pme_short_desc = "Unaligned load reject both units",
.pme_long_desc = "Unaligned load reject both units",
- .pme_event_ids = { -1, 255, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x8000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_ULD_BOTH],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_ULD_BOTH]
},
-#define POWER6_PME_PM_L2SB_ST_MISS 335
[ POWER6_PME_PM_L2SB_ST_MISS ] = {
.pme_name = "PM_L2SB_ST_MISS",
+ .pme_code = 0x5048e,
.pme_short_desc = "L2 slice B store misses",
.pme_long_desc = "L2 slice B store misses",
- .pme_event_ids = { 183, 192, 183, 189, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000080000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_ST_MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_ST_MISS]
},
-#define POWER6_PME_PM_DATA_FROM_L25_MOD_CYC 336
[ POWER6_PME_PM_DATA_FROM_L25_MOD_CYC ] = {
.pme_name = "PM_DATA_FROM_L25_MOD_CYC",
+ .pme_code = 0x400024,
.pme_short_desc = "Load latency from L2.5 modified",
.pme_long_desc = "Load latency from L2.5 modified",
- .pme_event_ids = { -1, -1, -1, 17, -1, -1 },
- .pme_group_vector = {
- 0x0000000000001000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L25_MOD_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L25_MOD_CYC]
},
-#define POWER6_PME_PM_INST_PTEG_1ST_HALF 337
[ POWER6_PME_PM_INST_PTEG_1ST_HALF ] = {
.pme_name = "PM_INST_PTEG_1ST_HALF",
+ .pme_code = 0x910a8,
.pme_short_desc = "Instruction table walk matched in first half primary PTEG",
.pme_long_desc = "Instruction table walk matched in first half primary PTEG",
- .pme_event_ids = { 148, 157, 148, 154, -1, -1 },
- .pme_group_vector = {
- 0x0000000200000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_PTEG_1ST_HALF],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_PTEG_1ST_HALF]
},
-#define POWER6_PME_PM_DERAT_MISS_16M 338
[ POWER6_PME_PM_DERAT_MISS_16M ] = {
.pme_name = "PM_DERAT_MISS_16M",
+ .pme_code = 0x392070,
.pme_short_desc = "DERAT misses for 16M page",
.pme_long_desc = "A data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.",
- .pme_event_ids = { -1, -1, 343, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000040ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DERAT_MISS_16M],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DERAT_MISS_16M]
},
-#define POWER6_PME_PM_GX_DMA_WRITE 339
[ POWER6_PME_PM_GX_DMA_WRITE ] = {
.pme_name = "PM_GX_DMA_WRITE",
+ .pme_code = 0x5038e,
.pme_short_desc = "All DMA Write Requests (including dma wrt lgcy)",
.pme_long_desc = "All DMA Write Requests (including dma wrt lgcy)",
- .pme_event_ids = { 129, 136, 127, 135, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000800000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_GX_DMA_WRITE],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GX_DMA_WRITE]
},
-#define POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_MOD 340
[ POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_MOD ] = {
.pme_name = "PM_MRK_PTEG_FROM_DL2L3_MOD",
+ .pme_code = 0x412044,
.pme_short_desc = "Marked PTEG loaded from distant L2 or L3 modified",
.pme_long_desc = "Marked PTEG loaded from distant L2 or L3 modified",
- .pme_event_ids = { -1, -1, -1, 275, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000008000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_MOD]
},
-#define POWER6_PME_PM_MEM1_DP_RQ_GLOB_LOC 341
[ POWER6_PME_PM_MEM1_DP_RQ_GLOB_LOC ] = {
.pme_name = "PM_MEM1_DP_RQ_GLOB_LOC",
+ .pme_code = 0x50288,
.pme_short_desc = "Memory read queue marking cache line double pump state from global to local side 1",
.pme_long_desc = "Memory read queue marking cache line double pump state from global to local side 1",
- .pme_event_ids = { 254, 265, 248, 253, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000100000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM1_DP_RQ_GLOB_LOC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM1_DP_RQ_GLOB_LOC]
},
-#define POWER6_PME_PM_L2SB_LD_REQ_DATA 342
[ POWER6_PME_PM_L2SB_LD_REQ_DATA ] = {
.pme_name = "PM_L2SB_LD_REQ_DATA",
+ .pme_code = 0x50488,
.pme_short_desc = "L2 slice B data load requests",
.pme_long_desc = "L2 slice B data load requests",
- .pme_event_ids = { 179, 188, 179, 185, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000020000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_LD_REQ_DATA],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_LD_REQ_DATA]
},
-#define POWER6_PME_PM_L2SA_LD_MISS_INST 343
[ POWER6_PME_PM_L2SA_LD_MISS_INST ] = {
.pme_name = "PM_L2SA_LD_MISS_INST",
+ .pme_code = 0x50582,
.pme_short_desc = "L2 slice A instruction load misses",
.pme_long_desc = "L2 slice A instruction load misses",
- .pme_event_ids = { 163, 172, 163, 169, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000040000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_LD_MISS_INST],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_LD_MISS_INST]
},
-#define POWER6_PME_PM_MRK_LSU0_REJECT_L2MISS 344
[ POWER6_PME_PM_MRK_LSU0_REJECT_L2MISS ] = {
.pme_name = "PM_MRK_LSU0_REJECT_L2MISS",
+ .pme_code = 0x930e4,
.pme_short_desc = "LSU0 marked L2 miss reject",
.pme_long_desc = "LSU0 marked L2 miss reject",
- .pme_event_ids = { 269, 281, 263, 264, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000800000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU0_REJECT_L2MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU0_REJECT_L2MISS]
},
-#define POWER6_PME_PM_MRK_IFU_FIN 345
[ POWER6_PME_PM_MRK_IFU_FIN ] = {
.pme_name = "PM_MRK_IFU_FIN",
+ .pme_code = 0x20000a,
.pme_short_desc = "Marked instruction IFU processing finished",
.pme_long_desc = "Marked instruction IFU processing finished",
- .pme_event_ids = { -1, 278, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000400000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_IFU_FIN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_IFU_FIN]
},
-#define POWER6_PME_PM_INST_FROM_L3 346
[ POWER6_PME_PM_INST_FROM_L3 ] = {
.pme_name = "PM_INST_FROM_L3",
+ .pme_code = 0x342040,
.pme_short_desc = "Instruction fetched from L3",
.pme_long_desc = "An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions",
- .pme_event_ids = { -1, -1, 145, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000800000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_L3],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_L3]
},
-#define POWER6_PME_PM_FXU1_FIN 347
[ POWER6_PME_PM_FXU1_FIN ] = {
.pme_name = "PM_FXU1_FIN",
+ .pme_code = 0x400016,
.pme_short_desc = "FXU1 produced a result",
.pme_long_desc = "The Fixed Point unit 1 finished an instruction and produced a result",
- .pme_event_ids = { -1, -1, -1, 125, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000080000ULL,
- 0x4000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FXU1_FIN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FXU1_FIN]
},
-#define POWER6_PME_PM_THRD_PRIO_4_CYC 348
[ POWER6_PME_PM_THRD_PRIO_4_CYC ] = {
.pme_name = "PM_THRD_PRIO_4_CYC",
+ .pme_code = 0x422046,
.pme_short_desc = "Cycles thread running at priority level 4",
.pme_long_desc = "Cycles thread running at priority level 4",
- .pme_event_ids = { -1, -1, -1, 308, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000008000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_4_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_4_CYC]
},
-#define POWER6_PME_PM_MRK_DATA_FROM_L35_MOD 349
[ POWER6_PME_PM_MRK_DATA_FROM_L35_MOD ] = {
.pme_name = "PM_MRK_DATA_FROM_L35_MOD",
+ .pme_code = 0x10304e,
.pme_short_desc = "Marked data loaded from L3.5 modified",
.pme_long_desc = "Marked data loaded from L3.5 modified",
- .pme_event_ids = { 261, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000002000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_L35_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_L35_MOD]
},
-#define POWER6_PME_PM_LSU_REJECT_SET_MPRED 350
[ POWER6_PME_PM_LSU_REJECT_SET_MPRED ] = {
.pme_name = "PM_LSU_REJECT_SET_MPRED",
+ .pme_code = 0x2a0032,
.pme_short_desc = "LSU reject due to mispredicted set",
.pme_long_desc = "LSU reject due to mispredicted set",
- .pme_event_ids = { -1, 252, 238, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000001ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_SET_MPRED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_SET_MPRED]
},
-#define POWER6_PME_PM_MRK_DERAT_MISS_16G 351
[ POWER6_PME_PM_MRK_DERAT_MISS_16G ] = {
.pme_name = "PM_MRK_DERAT_MISS_16G",
+ .pme_code = 0x492044,
.pme_short_desc = "Marked DERAT misses for 16G page",
.pme_long_desc = "A marked data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.",
- .pme_event_ids = { -1, -1, -1, 346, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000020ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DERAT_MISS_16G],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DERAT_MISS_16G]
},
-#define POWER6_PME_PM_FPU0_FXDIV 352
[ POWER6_PME_PM_FPU0_FXDIV ] = {
.pme_name = "PM_FPU0_FXDIV",
+ .pme_code = 0xc10a0,
.pme_short_desc = "FPU0 executed fixed point division",
.pme_long_desc = "FPU0 executed fixed point division",
- .pme_event_ids = { 81, 90, 79, 87, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0100000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_FXDIV],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_FXDIV]
},
-#define POWER6_PME_PM_MRK_LSU1_REJECT_UST 353
[ POWER6_PME_PM_MRK_LSU1_REJECT_UST ] = {
.pme_name = "PM_MRK_LSU1_REJECT_UST",
+ .pme_code = 0x930ea,
.pme_short_desc = "LSU1 marked unaligned store reject",
.pme_long_desc = "LSU1 marked unaligned store reject",
- .pme_event_ids = { 275, 287, 269, 270, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000040000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU1_REJECT_UST],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU1_REJECT_UST]
},
-#define POWER6_PME_PM_FPU_ISSUE_DIV_SQRT_OVERLAP 354
[ POWER6_PME_PM_FPU_ISSUE_DIV_SQRT_OVERLAP ] = {
.pme_name = "PM_FPU_ISSUE_DIV_SQRT_OVERLAP",
+ .pme_code = 0x320cc,
.pme_short_desc = "FPU divide/sqrt overlapped with other divide/sqrt",
.pme_long_desc = "FPU divide/sqrt overlapped with other divide/sqrt",
- .pme_event_ids = { 110, 118, 106, 115, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0060000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_ISSUE_DIV_SQRT_OVERLAP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_ISSUE_DIV_SQRT_OVERLAP]
},
-#define POWER6_PME_PM_INST_FROM_L35_SHR 355
[ POWER6_PME_PM_INST_FROM_L35_SHR ] = {
.pme_name = "PM_INST_FROM_L35_SHR",
+ .pme_code = 0x242046,
.pme_short_desc = "Instruction fetched from L3.5 shared",
.pme_long_desc = "Instruction fetched from L3.5 shared",
- .pme_event_ids = { -1, 155, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000800000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_L35_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_L35_SHR]
},
-#define POWER6_PME_PM_MRK_LSU_REJECT_LHS 356
[ POWER6_PME_PM_MRK_LSU_REJECT_LHS ] = {
.pme_name = "PM_MRK_LSU_REJECT_LHS",
+ .pme_code = 0x493030,
.pme_short_desc = "Marked load hit store reject",
.pme_long_desc = "Marked load hit store reject",
- .pme_event_ids = { -1, -1, -1, 273, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000010000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU_REJECT_LHS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU_REJECT_LHS]
},
-#define POWER6_PME_PM_LSU_LMQ_FULL_CYC 357
[ POWER6_PME_PM_LSU_LMQ_FULL_CYC ] = {
.pme_name = "PM_LSU_LMQ_FULL_CYC",
+ .pme_code = 0x810ac,
.pme_short_desc = "Cycles LMQ full",
.pme_long_desc = "The LMQ was full",
- .pme_event_ids = { 238, 247, 233, 237, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000400ULL,
- 0x0000008000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_LMQ_FULL_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_LMQ_FULL_CYC]
},
-#define POWER6_PME_PM_SYNC_COUNT 358
[ POWER6_PME_PM_SYNC_COUNT ] = {
.pme_name = "PM_SYNC_COUNT",
+ .pme_code = 0x920cd,
.pme_short_desc = "SYNC instructions completed",
.pme_long_desc = "SYNC instructions completed",
- .pme_event_ids = { 342, 349, 336, 334, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0061800000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_SYNC_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_SYNC_COUNT]
},
-#define POWER6_PME_PM_MEM0_DP_RQ_LOC_GLOB 359
[ POWER6_PME_PM_MEM0_DP_RQ_LOC_GLOB ] = {
.pme_name = "PM_MEM0_DP_RQ_LOC_GLOB",
+ .pme_code = 0x50282,
.pme_short_desc = "Memory read queue marking cache line double pump state from local to global side 0",
.pme_long_desc = "Memory read queue marking cache line double pump state from local to global side 0",
- .pme_event_ids = { 251, 262, 245, 250, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000080000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM0_DP_RQ_LOC_GLOB],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM0_DP_RQ_LOC_GLOB]
},
-#define POWER6_PME_PM_L2SA_CASTOUT_MOD 360
[ POWER6_PME_PM_L2SA_CASTOUT_MOD ] = {
.pme_name = "PM_L2SA_CASTOUT_MOD",
+ .pme_code = 0x50680,
.pme_short_desc = "L2 slice A castouts - Modified",
.pme_long_desc = "L2 slice A castouts - Modified",
- .pme_event_ids = { 157, 166, 157, 163, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000200000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_CASTOUT_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_CASTOUT_MOD]
},
-#define POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT 361
[ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT ] = {
.pme_name = "PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT",
+ .pme_code = 0x30001d,
.pme_short_desc = "Periods both threads LMQ and SRQ empty",
.pme_long_desc = "Periods both threads LMQ and SRQ empty",
- .pme_event_ids = { -1, -1, 341, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0008008000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT]
},
-#define POWER6_PME_PM_PTEG_FROM_MEM_DP 362
[ POWER6_PME_PM_PTEG_FROM_MEM_DP ] = {
.pme_name = "PM_PTEG_FROM_MEM_DP",
+ .pme_code = 0x11304a,
.pme_short_desc = "PTEG loaded from double pump memory",
.pme_long_desc = "PTEG loaded from double pump memory",
- .pme_event_ids = { 298, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000040000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_MEM_DP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_MEM_DP]
},
-#define POWER6_PME_PM_LSU_REJECT_SLOW 363
[ POWER6_PME_PM_LSU_REJECT_SLOW ] = {
.pme_name = "PM_LSU_REJECT_SLOW",
+ .pme_code = 0x20003e,
.pme_short_desc = "LSU slow reject",
.pme_long_desc = "LSU slow reject",
- .pme_event_ids = { -1, 253, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x2000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_SLOW],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_SLOW]
},
-#define POWER6_PME_PM_PTEG_FROM_L25_MOD 364
[ POWER6_PME_PM_PTEG_FROM_L25_MOD ] = {
.pme_name = "PM_PTEG_FROM_L25_MOD",
+ .pme_code = 0x31304e,
.pme_short_desc = "PTEG loaded from L2.5 modified",
.pme_long_desc = "PTEG loaded from L2.5 modified",
- .pme_event_ids = { -1, -1, 291, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000008000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_L25_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_L25_MOD]
},
-#define POWER6_PME_PM_THRD_PRIO_7_CYC 365
[ POWER6_PME_PM_THRD_PRIO_7_CYC ] = {
.pme_name = "PM_THRD_PRIO_7_CYC",
+ .pme_code = 0x122046,
.pme_short_desc = "Cycles thread running at priority level 7",
.pme_long_desc = "Cycles thread running at priority level 7",
- .pme_event_ids = { 317, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000008000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_7_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_7_CYC]
},
-#define POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_SHR 366
[ POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_SHR ] = {
.pme_name = "PM_MRK_PTEG_FROM_RL2L3_SHR",
+ .pme_code = 0x212044,
.pme_short_desc = "Marked PTEG loaded from remote L2 or L3 shared",
.pme_long_desc = "Marked PTEG loaded from remote L2 or L3 shared",
- .pme_event_ids = { -1, 292, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000080000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_SHR]
},
-#define POWER6_PME_PM_ST_REQ_L2 367
[ POWER6_PME_PM_ST_REQ_L2 ] = {
.pme_name = "PM_ST_REQ_L2",
+ .pme_code = 0x250732,
.pme_short_desc = "L2 store requests",
.pme_long_desc = "L2 store requests",
- .pme_event_ids = { -1, 317, 301, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000010000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_ST_REQ_L2],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_ST_REQ_L2]
},
-#define POWER6_PME_PM_ST_REF_L1 368
[ POWER6_PME_PM_ST_REF_L1 ] = {
.pme_name = "PM_ST_REF_L1",
+ .pme_code = 0x80086,
.pme_short_desc = "L1 D cache store references",
.pme_long_desc = "Total DL1 Store references",
- .pme_event_ids = { 310, 315, 300, 300, -1, -1 },
- .pme_group_vector = {
- 0x0000c00000000000ULL,
- 0x0000000000000000ULL,
- 0x2000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_ST_REF_L1],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_ST_REF_L1]
},
-#define POWER6_PME_PM_FPU_ISSUE_STALL_THRD 369
[ POWER6_PME_PM_FPU_ISSUE_STALL_THRD ] = {
.pme_name = "PM_FPU_ISSUE_STALL_THRD",
+ .pme_code = 0x330e0,
.pme_short_desc = "FPU issue stalled due to thread resource conflict",
.pme_long_desc = "FPU issue stalled due to thread resource conflict",
- .pme_event_ids = { 114, 122, 110, 119, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0040000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_ISSUE_STALL_THRD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_ISSUE_STALL_THRD]
},
-#define POWER6_PME_PM_RUN_COUNT 370
[ POWER6_PME_PM_RUN_COUNT ] = {
.pme_name = "PM_RUN_COUNT",
+ .pme_code = 0x10000b,
.pme_short_desc = "Run Periods",
.pme_long_desc = "Processor Periods gated by the run latch",
- .pme_event_ids = { 343, 350, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000200000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_RUN_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_RUN_COUNT]
},
-#define POWER6_PME_PM_RUN_CYC 371
[ POWER6_PME_PM_RUN_CYC ] = {
.pme_name = "PM_RUN_CYC",
+ .pme_code = 0x10000a,
.pme_short_desc = "Run cycles",
.pme_long_desc = "Processor Cycles gated by the run latch",
- .pme_event_ids = { 302, 309, -1, -1, -1, 0 },
- .pme_group_vector = {
- 0xffffffffffffffffULL,
- 0xffffffffffffffffULL,
- 0xffffffffffffffffULL,
- 0x000000000000003fULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_RUN_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_RUN_CYC]
},
-#define POWER6_PME_PM_PTEG_FROM_RMEM 372
[ POWER6_PME_PM_PTEG_FROM_RMEM ] = {
.pme_name = "PM_PTEG_FROM_RMEM",
+ .pme_code = 0x31304a,
.pme_short_desc = "PTEG loaded from remote memory",
.pme_long_desc = "PTEG loaded from remote memory",
- .pme_event_ids = { -1, -1, 294, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000040000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_RMEM],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_RMEM]
},
-#define POWER6_PME_PM_LSU0_LDF 373
[ POWER6_PME_PM_LSU0_LDF ] = {
.pme_name = "PM_LSU0_LDF",
+ .pme_code = 0x80084,
.pme_short_desc = "LSU0 executed Floating Point load instruction",
.pme_long_desc = "A floating point load was executed from LSU unit 0",
- .pme_event_ids = { 205, 214, 200, 205, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000100ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_LDF],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_LDF]
},
-#define POWER6_PME_PM_ST_MISS_L1 374
[ POWER6_PME_PM_ST_MISS_L1 ] = {
.pme_name = "PM_ST_MISS_L1",
+ .pme_code = 0x80088,
.pme_short_desc = "L1 D cache store misses",
.pme_long_desc = "A store missed the dcache",
- .pme_event_ids = { 309, 314, 299, 299, -1, -1 },
- .pme_group_vector = {
- 0x0000800000000000ULL,
- 0x0000000000000000ULL,
- 0x1080000000000000ULL,
- 0x0000000000000004ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_ST_MISS_L1],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_ST_MISS_L1]
},
-#define POWER6_PME_PM_INST_FROM_DL2L3_SHR 375
[ POWER6_PME_PM_INST_FROM_DL2L3_SHR ] = {
.pme_name = "PM_INST_FROM_DL2L3_SHR",
+ .pme_code = 0x342044,
.pme_short_desc = "Instruction fetched from distant L2 or L3 shared",
.pme_long_desc = "Instruction fetched from distant L2 or L3 shared",
- .pme_event_ids = { -1, -1, 142, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000001000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_DL2L3_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_DL2L3_SHR]
},
-#define POWER6_PME_PM_L2SA_IC_INV 376
[ POWER6_PME_PM_L2SA_IC_INV ] = {
.pme_name = "PM_L2SA_IC_INV",
+ .pme_code = 0x50684,
.pme_short_desc = "L2 slice A I cache invalidate",
.pme_long_desc = "L2 slice A I cache invalidate",
- .pme_event_ids = { 160, 169, 160, 166, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000400000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_IC_INV],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_IC_INV]
},
-#define POWER6_PME_PM_THRD_ONE_RUN_CYC 377
[ POWER6_PME_PM_THRD_ONE_RUN_CYC ] = {
.pme_name = "PM_THRD_ONE_RUN_CYC",
+ .pme_code = 0x100016,
.pme_short_desc = "One of the threads in run cycles",
.pme_long_desc = "One of the threads in run cycles",
- .pme_event_ids = { 315, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0020000000000002ULL,
- 0x0000000000000000ULL,
- 0x0001000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_ONE_RUN_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_ONE_RUN_CYC]
},
-#define POWER6_PME_PM_L2SB_LD_REQ_INST 378
[ POWER6_PME_PM_L2SB_LD_REQ_INST ] = {
.pme_name = "PM_L2SB_LD_REQ_INST",
+ .pme_code = 0x50588,
.pme_short_desc = "L2 slice B instruction load requests",
.pme_long_desc = "L2 slice B instruction load requests",
- .pme_event_ids = { 180, 189, 180, 186, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000040000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_LD_REQ_INST],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_LD_REQ_INST]
},
-#define POWER6_PME_PM_MRK_DATA_FROM_L25_MOD 379
[ POWER6_PME_PM_MRK_DATA_FROM_L25_MOD ] = {
.pme_name = "PM_MRK_DATA_FROM_L25_MOD",
+ .pme_code = 0x30304e,
.pme_short_desc = "Marked data loaded from L2.5 modified",
.pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a marked demand load",
- .pme_event_ids = { -1, -1, 253, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000800ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_L25_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_L25_MOD]
},
-#define POWER6_PME_PM_DPU_HELD_XTHRD 380
[ POWER6_PME_PM_DPU_HELD_XTHRD ] = {
.pme_name = "PM_DPU_HELD_XTHRD",
+ .pme_code = 0x30082,
.pme_short_desc = "DISP unit held due to cross thread resource conflicts",
.pme_long_desc = "DISP unit held due to cross thread resource conflicts",
- .pme_event_ids = { 55, 63, 53, 61, -1, -1 },
- .pme_group_vector = {
- 0x0000020000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_XTHRD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_XTHRD]
},
-#define POWER6_PME_PM_L2SB_ST_REQ 381
[ POWER6_PME_PM_L2SB_ST_REQ ] = {
.pme_name = "PM_L2SB_ST_REQ",
+ .pme_code = 0x5048c,
.pme_short_desc = "L2 slice B store requests",
.pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C.",
- .pme_event_ids = { 184, 193, 184, 190, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0001080000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_ST_REQ],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_ST_REQ]
},
-#define POWER6_PME_PM_INST_FROM_L21 382
[ POWER6_PME_PM_INST_FROM_L21 ] = {
.pme_name = "PM_INST_FROM_L21",
+ .pme_code = 0x242040,
.pme_short_desc = "Instruction fetched from private L2 other core",
.pme_long_desc = "Instruction fetched from private L2 other core",
- .pme_event_ids = { -1, 154, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000004400000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_L21],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_L21]
},
-#define POWER6_PME_PM_INST_FROM_L3MISS 383
[ POWER6_PME_PM_INST_FROM_L3MISS ] = {
.pme_name = "PM_INST_FROM_L3MISS",
+ .pme_code = 0x342054,
.pme_short_desc = "Instruction fetched missed L3",
.pme_long_desc = "Instruction fetched missed L3",
- .pme_event_ids = { -1, -1, 146, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000004000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000008ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_L3MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_L3MISS]
},
-#define POWER6_PME_PM_L3SB_HIT 384
[ POWER6_PME_PM_L3SB_HIT ] = {
.pme_name = "PM_L3SB_HIT",
+ .pme_code = 0x5008a,
.pme_short_desc = "L3 slice B hits",
.pme_long_desc = "L3 slice B hits",
- .pme_event_ids = { 194, 204, 192, 197, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0008000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L3SB_HIT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L3SB_HIT]
},
-#define POWER6_PME_PM_EE_OFF_EXT_INT 385
[ POWER6_PME_PM_EE_OFF_EXT_INT ] = {
.pme_name = "PM_EE_OFF_EXT_INT",
+ .pme_code = 0x230ee,
.pme_short_desc = "Cycles MSR(EE) bit off and external interrupt pending",
.pme_long_desc = "Cycles MSR(EE) bit off and external interrupt pending",
- .pme_event_ids = { 57, 66, 56, 64, -1, -1 },
- .pme_group_vector = {
- 0x0080000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_EE_OFF_EXT_INT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_EE_OFF_EXT_INT]
},
-#define POWER6_PME_PM_INST_FROM_DL2L3_MOD 386
[ POWER6_PME_PM_INST_FROM_DL2L3_MOD ] = {
.pme_name = "PM_INST_FROM_DL2L3_MOD",
+ .pme_code = 0x442044,
.pme_short_desc = "Instruction fetched from distant L2 or L3 modified",
.pme_long_desc = "Instruction fetched from distant L2 or L3 modified",
- .pme_event_ids = { -1, -1, -1, 148, -1, -1 },
- .pme_group_vector = {
- 0x0000000001000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_DL2L3_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_DL2L3_MOD]
},
-#define POWER6_PME_PM_PMC6_OVERFLOW 387
[ POWER6_PME_PM_PMC6_OVERFLOW ] = {
.pme_name = "PM_PMC6_OVERFLOW",
+ .pme_code = 0x300024,
.pme_short_desc = "PMC6 Overflow",
.pme_long_desc = "PMC6 Overflow",
- .pme_event_ids = { -1, -1, 289, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PMC6_OVERFLOW],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PMC6_OVERFLOW]
},
-#define POWER6_PME_PM_FPU_FLOP 388
[ POWER6_PME_PM_FPU_FLOP ] = {
.pme_name = "PM_FPU_FLOP",
+ .pme_code = 0x1c0032,
.pme_short_desc = "FPU executed 1FLOP",
.pme_long_desc = " FMA",
- .pme_event_ids = { 104, -1, -1, 109, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x8000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_FLOP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_FLOP]
},
-#define POWER6_PME_PM_FXU_BUSY 389
[ POWER6_PME_PM_FXU_BUSY ] = {
.pme_name = "PM_FXU_BUSY",
+ .pme_code = 0x200050,
.pme_short_desc = "FXU busy",
.pme_long_desc = "FXU0 and FXU1 are both busy",
- .pme_event_ids = { -1, 125, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000040000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FXU_BUSY],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FXU_BUSY]
},
-#define POWER6_PME_PM_FPU1_FLOP 390
[ POWER6_PME_PM_FPU1_FLOP ] = {
.pme_name = "PM_FPU1_FLOP",
+ .pme_code = 0xc008e,
.pme_short_desc = "FPU1 executed 1FLOP",
.pme_long_desc = " FMA",
- .pme_event_ids = { 91, 100, 89, 97, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x1000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_FLOP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_FLOP]
},
-#define POWER6_PME_PM_IC_RELOAD_SHR 391
[ POWER6_PME_PM_IC_RELOAD_SHR ] = {
.pme_name = "PM_IC_RELOAD_SHR",
+ .pme_code = 0x4008e,
.pme_short_desc = "I cache line reloading to be shared by threads",
.pme_long_desc = "I cache line reloading to be shared by threads",
- .pme_event_ids = { 135, 144, 134, 141, -1, -1 },
- .pme_group_vector = {
- 0x0004000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_IC_RELOAD_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IC_RELOAD_SHR]
},
-#define POWER6_PME_PM_INST_TABLEWALK_CYC 392
[ POWER6_PME_PM_INST_TABLEWALK_CYC ] = {
.pme_name = "PM_INST_TABLEWALK_CYC",
+ .pme_code = 0x920ca,
.pme_short_desc = "Cycles doing instruction tablewalks",
.pme_long_desc = "Cycles doing instruction tablewalks",
- .pme_event_ids = { 151, 160, 151, 157, -1, -1 },
- .pme_group_vector = {
- 0x0000000200000000ULL,
- 0x0000000000000000ULL,
- 0x0000200000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_TABLEWALK_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_TABLEWALK_CYC]
},
-#define POWER6_PME_PM_DATA_FROM_RL2L3_MOD_CYC 393
[ POWER6_PME_PM_DATA_FROM_RL2L3_MOD_CYC ] = {
.pme_name = "PM_DATA_FROM_RL2L3_MOD_CYC",
+ .pme_code = 0x400028,
.pme_short_desc = "Load latency from remote L2 or L3 modified",
.pme_long_desc = "Load latency from remote L2 or L3 modified",
- .pme_event_ids = { -1, -1, -1, 22, -1, -1 },
- .pme_group_vector = {
- 0x0000000000010000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_RL2L3_MOD_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_RL2L3_MOD_CYC]
},
-#define POWER6_PME_PM_THRD_PRIO_DIFF_5or6_CYC 394
[ POWER6_PME_PM_THRD_PRIO_DIFF_5or6_CYC ] = {
.pme_name = "PM_THRD_PRIO_DIFF_5or6_CYC",
+ .pme_code = 0x423040,
.pme_short_desc = "Cycles thread priority difference is 5 or 6",
.pme_long_desc = "Cycles thread priority difference is 5 or 6",
- .pme_event_ids = { -1, -1, -1, 309, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000010000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_DIFF_5or6_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_DIFF_5or6_CYC]
},
-#define POWER6_PME_PM_IBUF_FULL_CYC 395
[ POWER6_PME_PM_IBUF_FULL_CYC ] = {
.pme_name = "PM_IBUF_FULL_CYC",
+ .pme_code = 0x40084,
.pme_short_desc = "Cycles instruction buffer full",
.pme_long_desc = "Cycles instruction buffer full",
- .pme_event_ids = { 130, 138, 128, 136, -1, -1 },
- .pme_group_vector = {
- 0x0001000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000100000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_IBUF_FULL_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IBUF_FULL_CYC]
},
-#define POWER6_PME_PM_L2SA_LD_REQ 396
[ POWER6_PME_PM_L2SA_LD_REQ ] = {
.pme_name = "PM_L2SA_LD_REQ",
+ .pme_code = 0x50780,
.pme_short_desc = "L2 slice A load requests ",
.pme_long_desc = "L2 slice A load requests ",
- .pme_event_ids = { 164, 173, 164, 170, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000800000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_LD_REQ],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_LD_REQ]
},
-#define POWER6_PME_PM_VMX1_LD_WRBACK 397
[ POWER6_PME_PM_VMX1_LD_WRBACK ] = {
.pme_name = "PM_VMX1_LD_WRBACK",
+ .pme_code = 0x6008c,
.pme_short_desc = "VMX1 load writeback valid",
.pme_long_desc = "VMX1 load writeback valid",
- .pme_event_ids = { 327, 334, 321, 319, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000400000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX1_LD_WRBACK],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX1_LD_WRBACK]
},
-#define POWER6_PME_PM_MRK_FPU_FIN 398
[ POWER6_PME_PM_MRK_FPU_FIN ] = {
.pme_name = "PM_MRK_FPU_FIN",
+ .pme_code = 0x2d0030,
.pme_short_desc = "Marked instruction FPU processing finished",
.pme_long_desc = "One of the Floating Point Units finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, 276, 261, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000800100000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_FPU_FIN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_FPU_FIN]
},
-#define POWER6_PME_PM_THRD_PRIO_5_CYC 399
[ POWER6_PME_PM_THRD_PRIO_5_CYC ] = {
.pme_name = "PM_THRD_PRIO_5_CYC",
+ .pme_code = 0x322046,
.pme_short_desc = "Cycles thread running at priority level 5",
.pme_long_desc = "Cycles thread running at priority level 5",
- .pme_event_ids = { -1, -1, 309, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000008000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_5_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_5_CYC]
},
-#define POWER6_PME_PM_DFU_BACK2BACK 400
[ POWER6_PME_PM_DFU_BACK2BACK ] = {
.pme_name = "PM_DFU_BACK2BACK",
+ .pme_code = 0xe0082,
.pme_short_desc = "DFU back to back operations executed",
.pme_long_desc = "DFU back to back operations executed",
- .pme_event_ids = { 25, 32, 24, 32, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000002000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DFU_BACK2BACK],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DFU_BACK2BACK]
},
-#define POWER6_PME_PM_MRK_DATA_FROM_LMEM 401
[ POWER6_PME_PM_MRK_DATA_FROM_LMEM ] = {
.pme_name = "PM_MRK_DATA_FROM_LMEM",
+ .pme_code = 0x40304a,
.pme_short_desc = "Marked data loaded from local memory",
.pme_long_desc = "Marked data loaded from local memory",
- .pme_event_ids = { -1, -1, -1, 258, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000004000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_LMEM],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_LMEM]
},
-#define POWER6_PME_PM_LSU_REJECT_LHS 402
[ POWER6_PME_PM_LSU_REJECT_LHS ] = {
.pme_name = "PM_LSU_REJECT_LHS",
+ .pme_code = 0x190032,
.pme_short_desc = "Load hit store reject",
.pme_long_desc = "Load hit store reject",
- .pme_event_ids = { 240, -1, -1, 240, -1, -1 },
- .pme_group_vector = {
- 0x1000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_LHS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_LHS]
},
-#define POWER6_PME_PM_DPU_HELD_SPR 403
[ POWER6_PME_PM_DPU_HELD_SPR ] = {
.pme_name = "PM_DPU_HELD_SPR",
+ .pme_code = 0x3008c,
.pme_short_desc = "DISP unit held due to MTSPR/MFSPR",
.pme_long_desc = "DISP unit held due to MTSPR/MFSPR",
- .pme_event_ids = { 50, 59, 49, 57, -1, -1 },
- .pme_group_vector = {
- 0x0000040000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_SPR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_SPR]
},
-#define POWER6_PME_PM_FREQ_DOWN 404
[ POWER6_PME_PM_FREQ_DOWN ] = {
.pme_name = "PM_FREQ_DOWN",
+ .pme_code = 0x30003c,
.pme_short_desc = "Frequency is being slewed down due to Power Management",
.pme_long_desc = "Frequency is being slewed down due to Power Management",
- .pme_event_ids = { -1, -1, 115, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000400000000ULL,
- 0x0000000000000000ULL,
- 0x0000020000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FREQ_DOWN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FREQ_DOWN]
},
-#define POWER6_PME_PM_DFU_ENC_BCD_DPD 405
[ POWER6_PME_PM_DFU_ENC_BCD_DPD ] = {
.pme_name = "PM_DFU_ENC_BCD_DPD",
+ .pme_code = 0xe008a,
.pme_short_desc = "DFU Encode BCD to DPD",
.pme_long_desc = "DFU Encode BCD to DPD",
- .pme_event_ids = { 27, 34, 26, 34, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000004000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DFU_ENC_BCD_DPD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DFU_ENC_BCD_DPD]
},
-#define POWER6_PME_PM_DPU_HELD_GPR 406
[ POWER6_PME_PM_DPU_HELD_GPR ] = {
.pme_name = "PM_DPU_HELD_GPR",
+ .pme_code = 0x20080,
.pme_short_desc = "DISP unit held due to GPR dependencies",
.pme_long_desc = "DISP unit held due to GPR dependencies",
- .pme_event_ids = { 39, 47, 38, 46, -1, -1 },
- .pme_group_vector = {
- 0x0000012000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_GPR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_GPR]
},
-#define POWER6_PME_PM_LSU0_NCST 407
[ POWER6_PME_PM_LSU0_NCST ] = {
.pme_name = "PM_LSU0_NCST",
+ .pme_code = 0x820cc,
.pme_short_desc = "LSU0 non-cachable stores",
.pme_long_desc = "LSU0 non-cachable stores",
- .pme_event_ids = { 207, 216, 202, 207, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000200ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_NCST],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_NCST]
},
-#define POWER6_PME_PM_MRK_INST_ISSUED 408
[ POWER6_PME_PM_MRK_INST_ISSUED ] = {
.pme_name = "PM_MRK_INST_ISSUED",
+ .pme_code = 0x10001c,
.pme_short_desc = "Marked instruction issued",
.pme_long_desc = "Marked instruction issued",
- .pme_event_ids = { 268, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000080000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_INST_ISSUED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_INST_ISSUED]
},
-#define POWER6_PME_PM_INST_FROM_RL2L3_SHR 409
[ POWER6_PME_PM_INST_FROM_RL2L3_SHR ] = {
.pme_name = "PM_INST_FROM_RL2L3_SHR",
+ .pme_code = 0x242044,
.pme_short_desc = "Instruction fetched from remote L2 or L3 shared",
.pme_long_desc = "Instruction fetched from remote L2 or L3 shared",
- .pme_event_ids = { -1, 156, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000001000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_RL2L3_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_RL2L3_SHR]
},
-#define POWER6_PME_PM_FPU_DENORM 410
[ POWER6_PME_PM_FPU_DENORM ] = {
.pme_name = "PM_FPU_DENORM",
+ .pme_code = 0x2c1034,
.pme_short_desc = "FPU received denormalized data",
.pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, 110, 99, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000002ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_DENORM],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_DENORM]
},
-#define POWER6_PME_PM_PTEG_FROM_L3MISS 411
[ POWER6_PME_PM_PTEG_FROM_L3MISS ] = {
.pme_name = "PM_PTEG_FROM_L3MISS",
+ .pme_code = 0x313028,
.pme_short_desc = "PTEG loaded from L3 miss",
.pme_long_desc = "PTEG loaded from L3 miss",
- .pme_event_ids = { -1, -1, 293, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000020000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_L3MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_L3MISS]
},
-#define POWER6_PME_PM_RUN_PURR 412
[ POWER6_PME_PM_RUN_PURR ] = {
.pme_name = "PM_RUN_PURR",
+ .pme_code = 0x4000f4,
.pme_short_desc = "Run PURR Event",
.pme_long_desc = "Run PURR Event",
- .pme_event_ids = { -1, -1, -1, 347, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000002ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_RUN_PURR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_RUN_PURR]
},
-#define POWER6_PME_PM_MRK_VMX0_LD_WRBACK 413
[ POWER6_PME_PM_MRK_VMX0_LD_WRBACK ] = {
.pme_name = "PM_MRK_VMX0_LD_WRBACK",
+ .pme_code = 0x60086,
.pme_short_desc = "Marked VMX0 load writeback valid",
.pme_long_desc = "Marked VMX0 load writeback valid",
- .pme_event_ids = { 283, 295, 278, 280, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000200000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_VMX0_LD_WRBACK],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_VMX0_LD_WRBACK]
},
-#define POWER6_PME_PM_L2_MISS 414
[ POWER6_PME_PM_L2_MISS ] = {
.pme_name = "PM_L2_MISS",
+ .pme_code = 0x250532,
.pme_short_desc = "L2 cache misses",
.pme_long_desc = "L2 cache misses",
- .pme_event_ids = { -1, 197, 185, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000104000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000008ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2_MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2_MISS]
},
-#define POWER6_PME_PM_MRK_DATA_FROM_L3 415
[ POWER6_PME_PM_MRK_DATA_FROM_L3 ] = {
.pme_name = "PM_MRK_DATA_FROM_L3",
+ .pme_code = 0x303048,
.pme_short_desc = "Marked data loaded from L3",
.pme_long_desc = "DL1 was reloaded from the local L3 due to a marked demand load",
- .pme_event_ids = { -1, -1, 254, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000001000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_L3],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_L3]
},
-#define POWER6_PME_PM_MRK_LSU1_REJECT_LHS 416
[ POWER6_PME_PM_MRK_LSU1_REJECT_LHS ] = {
.pme_name = "PM_MRK_LSU1_REJECT_LHS",
+ .pme_code = 0x930ee,
.pme_short_desc = "LSU1 marked load hit store reject",
.pme_long_desc = "LSU1 marked load hit store reject",
- .pme_event_ids = { 273, 285, 267, 268, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000040000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU1_REJECT_LHS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU1_REJECT_LHS]
},
-#define POWER6_PME_PM_L2SB_LD_MISS_INST 417
[ POWER6_PME_PM_L2SB_LD_MISS_INST ] = {
.pme_name = "PM_L2SB_LD_MISS_INST",
+ .pme_code = 0x5058a,
.pme_short_desc = "L2 slice B instruction load misses",
.pme_long_desc = "L2 slice B instruction load misses",
- .pme_event_ids = { 177, 186, 177, 183, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000040000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_LD_MISS_INST],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_LD_MISS_INST]
},
-#define POWER6_PME_PM_PTEG_FROM_RL2L3_SHR 418
[ POWER6_PME_PM_PTEG_FROM_RL2L3_SHR ] = {
.pme_name = "PM_PTEG_FROM_RL2L3_SHR",
+ .pme_code = 0x21304c,
.pme_short_desc = "PTEG loaded from remote L2 or L3 shared",
.pme_long_desc = "PTEG loaded from remote L2 or L3 shared",
- .pme_event_ids = { -1, 307, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000080000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_RL2L3_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_RL2L3_SHR]
},
-#define POWER6_PME_PM_MRK_DERAT_MISS_64K 419
[ POWER6_PME_PM_MRK_DERAT_MISS_64K ] = {
.pme_name = "PM_MRK_DERAT_MISS_64K",
+ .pme_code = 0x192044,
.pme_short_desc = "Marked DERAT misses for 64K page",
.pme_long_desc = "A marked data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.",
- .pme_event_ids = { 354, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000002000000000ULL,
- 0x0000000000000020ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DERAT_MISS_64K],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DERAT_MISS_64K]
},
-#define POWER6_PME_PM_LWSYNC 420
[ POWER6_PME_PM_LWSYNC ] = {
.pme_name = "PM_LWSYNC",
+ .pme_code = 0x810ae,
.pme_short_desc = "Isync instruction completed",
.pme_long_desc = "Isync instruction completed",
- .pme_event_ids = { 247, 258, 241, 246, -1, -1 },
- .pme_group_vector = {
- 0x0000200000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LWSYNC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LWSYNC]
},
-#define POWER6_PME_PM_FPU1_FXMULT 421
[ POWER6_PME_PM_FPU1_FXMULT ] = {
.pme_name = "PM_FPU1_FXMULT",
+ .pme_code = 0xd008e,
.pme_short_desc = "FPU1 executed fixed point multiplication",
.pme_long_desc = "FPU1 executed fixed point multiplication",
- .pme_event_ids = { 97, 106, 95, 103, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x2000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_FXMULT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_FXMULT]
},
-#define POWER6_PME_PM_MEM0_DP_CL_WR_GLOB 422
[ POWER6_PME_PM_MEM0_DP_CL_WR_GLOB ] = {
.pme_name = "PM_MEM0_DP_CL_WR_GLOB",
+ .pme_code = 0x50284,
.pme_short_desc = "cacheline write setting dp to global side 0",
.pme_long_desc = "cacheline write setting dp to global side 0",
- .pme_event_ids = { 248, 259, 242, 247, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000080000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM0_DP_CL_WR_GLOB],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM0_DP_CL_WR_GLOB]
},
-#define POWER6_PME_PM_LSU0_REJECT_PARTIAL_SECTOR 423
[ POWER6_PME_PM_LSU0_REJECT_PARTIAL_SECTOR ] = {
.pme_name = "PM_LSU0_REJECT_PARTIAL_SECTOR",
+ .pme_code = 0xa0086,
.pme_short_desc = "LSU0 reject due to partial sector valid",
.pme_long_desc = "LSU0 reject due to partial sector valid",
- .pme_event_ids = { 215, 224, 210, 215, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000010ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT_PARTIAL_SECTOR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT_PARTIAL_SECTOR]
},
-#define POWER6_PME_PM_INST_IMC_MATCH_CMPL 424
[ POWER6_PME_PM_INST_IMC_MATCH_CMPL ] = {
.pme_name = "PM_INST_IMC_MATCH_CMPL",
+ .pme_code = 0x1000f0,
.pme_short_desc = "IMC matched instructions completed",
.pme_long_desc = "Number of instructions resulting from the marked instructions expansion that completed.",
- .pme_event_ids = { 147, -1, -1, 153, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000001000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_IMC_MATCH_CMPL],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_IMC_MATCH_CMPL]
},
-#define POWER6_PME_PM_DPU_HELD_THERMAL 425
[ POWER6_PME_PM_DPU_HELD_THERMAL ] = {
.pme_name = "PM_DPU_HELD_THERMAL",
+ .pme_code = 0x10002a,
.pme_short_desc = "DISP unit held due to thermal condition",
.pme_long_desc = "DISP unit held due to thermal condition",
- .pme_event_ids = { 52, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000001400000000ULL,
- 0x0000000000000000ULL,
- 0x0004000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_THERMAL],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_THERMAL]
},
-#define POWER6_PME_PM_FPU_FRSP 426
[ POWER6_PME_PM_FPU_FRSP ] = {
.pme_name = "PM_FPU_FRSP",
+ .pme_code = 0x2d1034,
.pme_short_desc = "FPU executed FRSP instruction",
.pme_long_desc = "FPU executed FRSP instruction",
- .pme_event_ids = { -1, 113, 101, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000005ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_FRSP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_FRSP]
},
-#define POWER6_PME_PM_MRK_INST_FIN 427
[ POWER6_PME_PM_MRK_INST_FIN ] = {
.pme_name = "PM_MRK_INST_FIN",
+ .pme_code = 0x30000a,
.pme_short_desc = "Marked instruction finished",
.pme_long_desc = "One of the execution units finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, -1, 262, 262, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000080000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_INST_FIN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_INST_FIN]
},
-#define POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_SHR 428
[ POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_SHR ] = {
.pme_name = "PM_MRK_PTEG_FROM_DL2L3_SHR",
+ .pme_code = 0x312044,
.pme_short_desc = "Marked PTEG loaded from distant L2 or L3 shared",
.pme_long_desc = "Marked PTEG loaded from distant L2 or L3 shared",
- .pme_event_ids = { -1, -1, 271, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000004000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_SHR]
},
-#define POWER6_PME_PM_MRK_DTLB_REF 429
[ POWER6_PME_PM_MRK_DTLB_REF ] = {
.pme_name = "PM_MRK_DTLB_REF",
+ .pme_code = 0x920c0,
.pme_short_desc = "Marked Data TLB reference",
.pme_long_desc = "Marked Data TLB reference",
- .pme_event_ids = { 264, 273, 258, 259, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000200000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DTLB_REF],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DTLB_REF]
},
-#define POWER6_PME_PM_MRK_PTEG_FROM_L25_SHR 430
[ POWER6_PME_PM_MRK_PTEG_FROM_L25_SHR ] = {
.pme_name = "PM_MRK_PTEG_FROM_L25_SHR",
+ .pme_code = 0x412046,
.pme_short_desc = "Marked PTEG loaded from L2.5 shared",
.pme_long_desc = "Marked PTEG loaded from L2.5 shared",
- .pme_event_ids = { -1, -1, -1, 276, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000010000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_L25_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_L25_SHR]
},
-#define POWER6_PME_PM_DPU_HELD_LSU 431
[ POWER6_PME_PM_DPU_HELD_LSU ] = {
.pme_name = "PM_DPU_HELD_LSU",
+ .pme_code = 0x210a2,
.pme_short_desc = "DISP unit held due to LSU move or invalidate SLB and SR",
.pme_long_desc = "DISP unit held due to LSU move or invalidate SLB and SR",
- .pme_event_ids = { 44, 52, 43, 51, -1, -1 },
- .pme_group_vector = {
- 0x0000008000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_LSU],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_LSU]
},
-#define POWER6_PME_PM_FPU_FSQRT_FDIV 432
[ POWER6_PME_PM_FPU_FSQRT_FDIV ] = {
.pme_name = "PM_FPU_FSQRT_FDIV",
+ .pme_code = 0x2c0032,
.pme_short_desc = "FPU executed FSQRT or FDIV instruction",
.pme_long_desc = "FPU executed FSQRT or FDIV instruction",
- .pme_event_ids = { -1, 114, 102, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x8000000000000000ULL,
- 0x0400000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_FSQRT_FDIV],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_FSQRT_FDIV]
},
-#define POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_COUNT 433
[ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_COUNT ] = {
.pme_name = "PM_LSU_LMQ_SRQ_EMPTY_COUNT",
+ .pme_code = 0x20001d,
.pme_short_desc = "Periods LMQ and SRQ empty",
.pme_long_desc = "Periods when both the LMQ and SRQ are empty (LSU is idle)",
- .pme_event_ids = { -1, 359, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0020008000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_COUNT]
},
-#define POWER6_PME_PM_DATA_PTEG_SECONDARY 434
[ POWER6_PME_PM_DATA_PTEG_SECONDARY ] = {
.pme_name = "PM_DATA_PTEG_SECONDARY",
+ .pme_code = 0x910a4,
.pme_short_desc = "Data table walk matched in secondary PTEG",
.pme_long_desc = "Data table walk matched in secondary PTEG",
- .pme_event_ids = { 19, 27, 19, 26, -1, -1 },
- .pme_group_vector = {
- 0x0000000100000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_PTEG_SECONDARY],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_PTEG_SECONDARY]
},
-#define POWER6_PME_PM_FPU1_FEST 435
[ POWER6_PME_PM_FPU1_FEST ] = {
.pme_name = "PM_FPU1_FEST",
+ .pme_code = 0xd10ae,
.pme_short_desc = "FPU1 executed FEST instruction",
.pme_long_desc = "This signal is active for one cycle when fp1 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ",
- .pme_event_ids = { 89, 98, 87, 95, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x6000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_FEST],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_FEST]
},
-#define POWER6_PME_PM_L2SA_LD_HIT 436
[ POWER6_PME_PM_L2SA_LD_HIT ] = {
.pme_name = "PM_L2SA_LD_HIT",
+ .pme_code = 0x50782,
.pme_short_desc = "L2 slice A load hits",
.pme_long_desc = "L2 slice A load hits",
- .pme_event_ids = { 161, 170, 161, 167, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000800000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_LD_HIT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_LD_HIT]
},
-#define POWER6_PME_PM_DATA_FROM_MEM_DP_CYC 437
[ POWER6_PME_PM_DATA_FROM_MEM_DP_CYC ] = {
.pme_name = "PM_DATA_FROM_MEM_DP_CYC",
+ .pme_code = 0x40002e,
.pme_short_desc = "Load latency from double pump memory",
.pme_long_desc = "Load latency from double pump memory",
- .pme_event_ids = { -1, -1, -1, 21, -1, -1 },
- .pme_group_vector = {
- 0x0000000000020000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_MEM_DP_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_MEM_DP_CYC]
},
-#define POWER6_PME_PM_BR_MPRED_CCACHE 438
[ POWER6_PME_PM_BR_MPRED_CCACHE ] = {
.pme_name = "PM_BR_MPRED_CCACHE",
+ .pme_code = 0x410ae,
.pme_short_desc = "Branch misprediction due to count cache prediction",
.pme_long_desc = "Branch misprediction due to count cache prediction",
- .pme_event_ids = { 4, 2, 2, 4, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000028ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_BR_MPRED_CCACHE],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_BR_MPRED_CCACHE]
},
-#define POWER6_PME_PM_DPU_HELD_COUNT 439
[ POWER6_PME_PM_DPU_HELD_COUNT ] = {
.pme_name = "PM_DPU_HELD_COUNT",
+ .pme_code = 0x200005,
.pme_short_desc = "Periods DISP unit held",
.pme_long_desc = "Dispatch unit held",
- .pme_event_ids = { -1, 355, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0002000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_COUNT]
},
-#define POWER6_PME_PM_LSU1_REJECT_SET_MPRED 440
[ POWER6_PME_PM_LSU1_REJECT_SET_MPRED ] = {
.pme_name = "PM_LSU1_REJECT_SET_MPRED",
+ .pme_code = 0xa008c,
.pme_short_desc = "LSU1 reject due to mispredicted set",
.pme_long_desc = "LSU1 reject due to mispredicted set",
- .pme_event_ids = { 229, 238, 224, 229, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000001ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_REJECT_SET_MPRED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_REJECT_SET_MPRED]
},
-#define POWER6_PME_PM_FPU_ISSUE_2 441
[ POWER6_PME_PM_FPU_ISSUE_2 ] = {
.pme_name = "PM_FPU_ISSUE_2",
+ .pme_code = 0x320ca,
.pme_short_desc = "FPU issue 2 per cycle",
.pme_long_desc = "FPU issue 2 per cycle",
- .pme_event_ids = { 109, 117, 105, 114, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0010000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_ISSUE_2],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_ISSUE_2]
},
-#define POWER6_PME_PM_LSU1_REJECT_L2_CORR 442
[ POWER6_PME_PM_LSU1_REJECT_L2_CORR ] = {
.pme_name = "PM_LSU1_REJECT_L2_CORR",
+ .pme_code = 0xa10a8,
.pme_short_desc = "LSU1 reject due to L2 correctable error",
.pme_long_desc = "LSU1 reject due to L2 correctable error",
- .pme_event_ids = { 225, 234, 220, 225, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000008ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_REJECT_L2_CORR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_REJECT_L2_CORR]
},
-#define POWER6_PME_PM_MRK_PTEG_FROM_DMEM 443
[ POWER6_PME_PM_MRK_PTEG_FROM_DMEM ] = {
.pme_name = "PM_MRK_PTEG_FROM_DMEM",
+ .pme_code = 0x212042,
.pme_short_desc = "Marked PTEG loaded from distant memory",
.pme_long_desc = "Marked PTEG loaded from distant memory",
- .pme_event_ids = { -1, 289, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000004000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_DMEM],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_DMEM]
},
-#define POWER6_PME_PM_MEM1_DP_RQ_LOC_GLOB 444
[ POWER6_PME_PM_MEM1_DP_RQ_LOC_GLOB ] = {
.pme_name = "PM_MEM1_DP_RQ_LOC_GLOB",
+ .pme_code = 0x5028a,
.pme_short_desc = "Memory read queue marking cache line double pump state from local to global side 1",
.pme_long_desc = "Memory read queue marking cache line double pump state from local to global side 1",
- .pme_event_ids = { 255, 266, 249, 254, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000100000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM1_DP_RQ_LOC_GLOB],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM1_DP_RQ_LOC_GLOB]
},
-#define POWER6_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC 445
[ POWER6_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC ] = {
.pme_name = "PM_THRD_PRIO_DIFF_minus1or2_CYC",
+ .pme_code = 0x223046,
.pme_short_desc = "Cycles thread priority difference is -1 or -2",
.pme_long_desc = "Cycles thread priority difference is -1 or -2",
- .pme_event_ids = { -1, 325, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000020000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC]
},
-#define POWER6_PME_PM_THRD_PRIO_0_CYC 446
[ POWER6_PME_PM_THRD_PRIO_0_CYC ] = {
.pme_name = "PM_THRD_PRIO_0_CYC",
+ .pme_code = 0x122040,
.pme_short_desc = "Cycles thread running at priority level 0",
.pme_long_desc = "Cycles thread running at priority level 0",
- .pme_event_ids = { 316, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000004000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_0_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_0_CYC]
},
-#define POWER6_PME_PM_FXU0_BUSY_FXU1_IDLE 447
[ POWER6_PME_PM_FXU0_BUSY_FXU1_IDLE ] = {
.pme_name = "PM_FXU0_BUSY_FXU1_IDLE",
+ .pme_code = 0x300050,
.pme_short_desc = "FXU0 busy FXU1 idle",
.pme_long_desc = "FXU0 is busy while FXU1 was idle",
- .pme_event_ids = { -1, -1, 116, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000040000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FXU0_BUSY_FXU1_IDLE],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FXU0_BUSY_FXU1_IDLE]
},
-#define POWER6_PME_PM_LSU1_REJECT_DERAT_MPRED 448
[ POWER6_PME_PM_LSU1_REJECT_DERAT_MPRED ] = {
.pme_name = "PM_LSU1_REJECT_DERAT_MPRED",
+ .pme_code = 0xa008a,
.pme_short_desc = "LSU1 reject due to mispredicted DERAT",
.pme_long_desc = "LSU1 reject due to mispredicted DERAT",
- .pme_event_ids = { 223, 232, 218, 223, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000080ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_REJECT_DERAT_MPRED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_REJECT_DERAT_MPRED]
},
-#define POWER6_PME_PM_MRK_VMX1_LD_WRBACK 449
[ POWER6_PME_PM_MRK_VMX1_LD_WRBACK ] = {
.pme_name = "PM_MRK_VMX1_LD_WRBACK",
+ .pme_code = 0x6008e,
.pme_short_desc = "Marked VMX1 load writeback valid",
.pme_long_desc = "Marked VMX1 load writeback valid",
- .pme_event_ids = { 284, 296, 279, 281, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000200000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_VMX1_LD_WRBACK],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_VMX1_LD_WRBACK]
},
-#define POWER6_PME_PM_DATA_FROM_RL2L3_SHR_CYC 450
[ POWER6_PME_PM_DATA_FROM_RL2L3_SHR_CYC ] = {
.pme_name = "PM_DATA_FROM_RL2L3_SHR_CYC",
+ .pme_code = 0x200028,
.pme_short_desc = "Load latency from remote L2 or L3 shared",
.pme_long_desc = "Load latency from remote L2 or L3 shared",
- .pme_event_ids = { -1, 24, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000001000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_RL2L3_SHR_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_RL2L3_SHR_CYC]
},
-#define POWER6_PME_PM_IERAT_MISS_16M 451
[ POWER6_PME_PM_IERAT_MISS_16M ] = {
.pme_name = "PM_IERAT_MISS_16M",
+ .pme_code = 0x292076,
.pme_short_desc = "IERAT misses for 16M page",
.pme_long_desc = "IERAT misses for 16M page",
- .pme_event_ids = { -1, 362, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000100ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_IERAT_MISS_16M],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IERAT_MISS_16M]
},
-#define POWER6_PME_PM_MRK_DATA_FROM_MEM_DP 452
[ POWER6_PME_PM_MRK_DATA_FROM_MEM_DP ] = {
.pme_name = "PM_MRK_DATA_FROM_MEM_DP",
+ .pme_code = 0x10304a,
.pme_short_desc = "Marked data loaded from double pump memory",
.pme_long_desc = "Marked data loaded from double pump memory",
- .pme_event_ids = { 262, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000004000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_MEM_DP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_MEM_DP]
},
-#define POWER6_PME_PM_LARX_L1HIT 453
[ POWER6_PME_PM_LARX_L1HIT ] = {
.pme_name = "PM_LARX_L1HIT",
+ .pme_code = 0x830e2,
.pme_short_desc = "larx hits in L1",
.pme_long_desc = "larx hits in L1",
- .pme_event_ids = { 198, 208, 196, 201, -1, -1 },
- .pme_group_vector = {
- 0x0010000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LARX_L1HIT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LARX_L1HIT]
},
-#define POWER6_PME_PM_L2_ST_MISS_DATA 454
[ POWER6_PME_PM_L2_ST_MISS_DATA ] = {
.pme_name = "PM_L2_ST_MISS_DATA",
+ .pme_code = 0x150432,
.pme_short_desc = "L2 data store misses",
.pme_long_desc = "L2 data store misses",
- .pme_event_ids = { 190, -1, -1, 193, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000002000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2_ST_MISS_DATA],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2_ST_MISS_DATA]
},
-#define POWER6_PME_PM_FPU_ST_FOLDED 455
[ POWER6_PME_PM_FPU_ST_FOLDED ] = {
.pme_name = "PM_FPU_ST_FOLDED",
+ .pme_code = 0x3d1030,
.pme_short_desc = "FPU folded store",
.pme_long_desc = "FPU folded store",
- .pme_event_ids = { -1, -1, 114, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000004ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_ST_FOLDED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_ST_FOLDED]
},
-#define POWER6_PME_PM_MRK_DATA_FROM_L35_SHR 456
[ POWER6_PME_PM_MRK_DATA_FROM_L35_SHR ] = {
.pme_name = "PM_MRK_DATA_FROM_L35_SHR",
+ .pme_code = 0x20304e,
.pme_short_desc = "Marked data loaded from L3.5 shared",
.pme_long_desc = "Marked data loaded from L3.5 shared",
- .pme_event_ids = { -1, 271, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000002000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_L35_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_L35_SHR]
},
-#define POWER6_PME_PM_DPU_HELD_MULT_GPR 457
[ POWER6_PME_PM_DPU_HELD_MULT_GPR ] = {
.pme_name = "PM_DPU_HELD_MULT_GPR",
+ .pme_code = 0x210aa,
.pme_short_desc = "DISP unit held due to multiple/divide multiply/divide GPR dependencies",
.pme_long_desc = "DISP unit held due to multiple/divide multiply/divide GPR dependencies",
- .pme_event_ids = { 46, 54, 45, 53, -1, -1 },
- .pme_group_vector = {
- 0x0000110000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_MULT_GPR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_MULT_GPR]
},
-#define POWER6_PME_PM_FPU0_1FLOP 458
[ POWER6_PME_PM_FPU0_1FLOP ] = {
.pme_name = "PM_FPU0_1FLOP",
+ .pme_code = 0xc0080,
.pme_short_desc = "FPU0 executed add",
.pme_long_desc = " mult",
- .pme_event_ids = { 71, 80, 69, 77, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0080000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_1FLOP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_1FLOP]
},
-#define POWER6_PME_PM_IERAT_MISS_16G 459
[ POWER6_PME_PM_IERAT_MISS_16G ] = {
.pme_name = "PM_IERAT_MISS_16G",
+ .pme_code = 0x192076,
.pme_short_desc = "IERAT misses for 16G page",
.pme_long_desc = "IERAT misses for 16G page",
- .pme_event_ids = { 352, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000100ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_IERAT_MISS_16G],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IERAT_MISS_16G]
},
-#define POWER6_PME_PM_IC_PREF_WRITE 460
[ POWER6_PME_PM_IC_PREF_WRITE ] = {
.pme_name = "PM_IC_PREF_WRITE",
+ .pme_code = 0x430e0,
.pme_short_desc = "Instruction prefetch written into I cache",
.pme_long_desc = "Instruction prefetch written into I cache",
- .pme_event_ids = { 134, 143, 133, 140, -1, -1 },
- .pme_group_vector = {
- 0x0004000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_IC_PREF_WRITE],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IC_PREF_WRITE]
},
-#define POWER6_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC 461
[ POWER6_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC ] = {
.pme_name = "PM_THRD_PRIO_DIFF_minus5or6_CYC",
+ .pme_code = 0x423046,
.pme_short_desc = "Cycles thread priority difference is -5 or -6",
.pme_long_desc = "Cycles thread priority difference is -5 or -6",
- .pme_event_ids = { -1, -1, -1, 310, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000020000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC]
},
-#define POWER6_PME_PM_FPU0_FIN 462
[ POWER6_PME_PM_FPU0_FIN ] = {
.pme_name = "PM_FPU0_FIN",
+ .pme_code = 0xd0080,
.pme_short_desc = "FPU0 produced a result",
.pme_long_desc = "fp0 finished, produced a result This only indicates finish, not completion. ",
- .pme_event_ids = { 75, 84, 73, 81, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0200000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_FIN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_FIN]
},
-#define POWER6_PME_PM_DATA_FROM_L2_CYC 463
[ POWER6_PME_PM_DATA_FROM_L2_CYC ] = {
.pme_name = "PM_DATA_FROM_L2_CYC",
+ .pme_code = 0x200020,
.pme_short_desc = "Load latency from L2",
.pme_long_desc = "Load latency from L2",
- .pme_event_ids = { -1, 18, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000040000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L2_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L2_CYC]
},
-#define POWER6_PME_PM_DERAT_REF_16G 464
[ POWER6_PME_PM_DERAT_REF_16G ] = {
.pme_name = "PM_DERAT_REF_16G",
+ .pme_code = 0x482070,
.pme_short_desc = "DERAT reference for 16G page",
.pme_long_desc = "DERAT reference for 16G page",
- .pme_event_ids = { -1, -1, -1, 342, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000080ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DERAT_REF_16G],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DERAT_REF_16G]
},
-#define POWER6_PME_PM_BR_PRED 465
[ POWER6_PME_PM_BR_PRED ] = {
.pme_name = "PM_BR_PRED",
+ .pme_code = 0x410a0,
.pme_short_desc = "A conditional branch was predicted",
.pme_long_desc = "A conditional branch was predicted",
- .pme_event_ids = { 8, 6, 6, 8, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000054ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_BR_PRED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_BR_PRED]
},
-#define POWER6_PME_PM_VMX1_LD_ISSUED 466
[ POWER6_PME_PM_VMX1_LD_ISSUED ] = {
.pme_name = "PM_VMX1_LD_ISSUED",
+ .pme_code = 0x6008a,
.pme_short_desc = "VMX1 load issued",
.pme_long_desc = "VMX1 load issued",
- .pme_event_ids = { 326, 333, 320, 318, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000600000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX1_LD_ISSUED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX1_LD_ISSUED]
},
-#define POWER6_PME_PM_L2SB_CASTOUT_MOD 467
[ POWER6_PME_PM_L2SB_CASTOUT_MOD ] = {
.pme_name = "PM_L2SB_CASTOUT_MOD",
+ .pme_code = 0x50688,
.pme_short_desc = "L2 slice B castouts - Modified",
.pme_long_desc = "L2 slice B castouts - Modified",
- .pme_event_ids = { 171, 180, 171, 177, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000200000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_CASTOUT_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_CASTOUT_MOD]
},
-#define POWER6_PME_PM_INST_FROM_DMEM 468
[ POWER6_PME_PM_INST_FROM_DMEM ] = {
.pme_name = "PM_INST_FROM_DMEM",
+ .pme_code = 0x242042,
.pme_short_desc = "Instruction fetched from distant memory",
.pme_long_desc = "Instruction fetched from distant memory",
- .pme_event_ids = { -1, 152, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000002000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_DMEM],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_DMEM]
},
-#define POWER6_PME_PM_DATA_FROM_L35_SHR_CYC 469
[ POWER6_PME_PM_DATA_FROM_L35_SHR_CYC ] = {
.pme_name = "PM_DATA_FROM_L35_SHR_CYC",
+ .pme_code = 0x200026,
.pme_short_desc = "Load latency from L3.5 shared",
.pme_long_desc = "Load latency from L3.5 shared",
- .pme_event_ids = { -1, 20, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000200000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L35_SHR_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L35_SHR_CYC]
},
-#define POWER6_PME_PM_LSU0_NCLD 470
[ POWER6_PME_PM_LSU0_NCLD ] = {
.pme_name = "PM_LSU0_NCLD",
+ .pme_code = 0x820ca,
.pme_short_desc = "LSU0 non-cacheable loads",
.pme_long_desc = "LSU0 non-cacheable loads",
- .pme_event_ids = { 206, 215, 201, 206, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000200ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_NCLD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_NCLD]
},
-#define POWER6_PME_PM_FAB_RETRY_NODE_PUMP 471
[ POWER6_PME_PM_FAB_RETRY_NODE_PUMP ] = {
.pme_name = "PM_FAB_RETRY_NODE_PUMP",
+ .pme_code = 0x5018a,
.pme_short_desc = "Retry of a node pump",
.pme_long_desc = " locally mastered",
- .pme_event_ids = { 64, 74, 63, 70, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000010000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FAB_RETRY_NODE_PUMP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FAB_RETRY_NODE_PUMP]
},
-#define POWER6_PME_PM_VMX0_INST_ISSUED 472
[ POWER6_PME_PM_VMX0_INST_ISSUED ] = {
.pme_name = "PM_VMX0_INST_ISSUED",
+ .pme_code = 0x60080,
.pme_short_desc = "VMX0 instruction issued",
.pme_long_desc = "VMX0 instruction issued",
- .pme_event_ids = { 321, 328, 315, 313, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000200000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX0_INST_ISSUED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX0_INST_ISSUED]
},
-#define POWER6_PME_PM_DATA_FROM_L25_MOD 473
[ POWER6_PME_PM_DATA_FROM_L25_MOD ] = {
.pme_name = "PM_DATA_FROM_L25_MOD",
+ .pme_code = 0x30005a,
.pme_short_desc = "Data loaded from L2.5 modified",
.pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a demand load",
- .pme_event_ids = { -1, -1, 12, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000020200ULL,
- 0x0000000000000000ULL,
- 0x8000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L25_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L25_MOD]
},
-#define POWER6_PME_PM_DPU_HELD_ITLB_ISLB 474
[ POWER6_PME_PM_DPU_HELD_ITLB_ISLB ] = {
.pme_name = "PM_DPU_HELD_ITLB_ISLB",
+ .pme_code = 0x210a4,
.pme_short_desc = "DISP unit held due to SLB or TLB invalidates ",
.pme_long_desc = "DISP unit held due to SLB or TLB invalidates ",
- .pme_event_ids = { 42, 50, 41, 49, -1, -1 },
- .pme_group_vector = {
- 0x0000008000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_ITLB_ISLB],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_ITLB_ISLB]
},
-#define POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 475
[ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = {
.pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC",
+ .pme_code = 0x20001c,
.pme_short_desc = "Cycles LMQ and SRQ empty",
.pme_long_desc = "Cycles when both the LMQ and SRQ are empty (LSU is idle)",
- .pme_event_ids = { -1, 248, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000400ULL,
- 0x0040000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC]
},
-#define POWER6_PME_PM_THRD_CONC_RUN_INST 476
[ POWER6_PME_PM_THRD_CONC_RUN_INST ] = {
.pme_name = "PM_THRD_CONC_RUN_INST",
+ .pme_code = 0x300026,
.pme_short_desc = "Concurrent run instructions",
.pme_long_desc = "Concurrent run instructions",
- .pme_event_ids = { -1, -1, 306, -1, -1, -1 },
- .pme_group_vector = {
- 0x0020000000000002ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_CONC_RUN_INST],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_CONC_RUN_INST]
},
-#define POWER6_PME_PM_MRK_PTEG_FROM_L2 477
[ POWER6_PME_PM_MRK_PTEG_FROM_L2 ] = {
.pme_name = "PM_MRK_PTEG_FROM_L2",
+ .pme_code = 0x112040,
.pme_short_desc = "Marked PTEG loaded from L2.5 modified",
.pme_long_desc = "Marked PTEG loaded from L2.5 modified",
- .pme_event_ids = { 277, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000004000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_L2],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_L2]
},
-#define POWER6_PME_PM_PURR 478
[ POWER6_PME_PM_PURR ] = {
.pme_name = "PM_PURR",
+ .pme_code = 0x10000e,
.pme_short_desc = "PURR Event",
.pme_long_desc = "PURR Event",
- .pme_event_ids = { 301, -1, -1, 293, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000008ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PURR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PURR]
},
-#define POWER6_PME_PM_DERAT_MISS_64K 479
[ POWER6_PME_PM_DERAT_MISS_64K ] = {
.pme_name = "PM_DERAT_MISS_64K",
+ .pme_code = 0x292070,
.pme_short_desc = "DERAT misses for 64K page",
.pme_long_desc = "A data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.",
- .pme_event_ids = { -1, 361, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000040ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DERAT_MISS_64K],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DERAT_MISS_64K]
},
-#define POWER6_PME_PM_PMC2_REWIND 480
[ POWER6_PME_PM_PMC2_REWIND ] = {
.pme_name = "PM_PMC2_REWIND",
+ .pme_code = 0x300020,
.pme_short_desc = "PMC2 rewind event",
.pme_long_desc = "PMC2 rewind event",
- .pme_event_ids = { -1, -1, 287, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PMC2_REWIND],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PMC2_REWIND]
},
-#define POWER6_PME_PM_INST_FROM_L2 481
[ POWER6_PME_PM_INST_FROM_L2 ] = {
.pme_name = "PM_INST_FROM_L2",
+ .pme_code = 0x142040,
.pme_short_desc = "Instructions fetched from L2",
.pme_long_desc = "An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions",
- .pme_event_ids = { 143, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000004400000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_L2],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_L2]
},
-#define POWER6_PME_PM_INST_DISP 482
[ POWER6_PME_PM_INST_DISP ] = {
.pme_name = "PM_INST_DISP",
+ .pme_code = 0x200012,
.pme_short_desc = "Instructions dispatched",
.pme_long_desc = "The ISU sends the number of instructions dispatched.",
- .pme_event_ids = { -1, 149, 139, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000140001ULL,
- 0x0000000000001000ULL,
- 0x2000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_DISP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_DISP]
},
-#define POWER6_PME_PM_DATA_FROM_L25_SHR 483
[ POWER6_PME_PM_DATA_FROM_L25_SHR ] = {
.pme_name = "PM_DATA_FROM_L25_SHR",
+ .pme_code = 0x40005a,
.pme_short_desc = "Data loaded from L2.5 shared",
.pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a demand load",
- .pme_event_ids = { -1, -1, -1, 16, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000200ULL,
- 0x0000000000000000ULL,
- 0x8000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L25_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L25_SHR]
},
-#define POWER6_PME_PM_L1_DCACHE_RELOAD_VALID 484
[ POWER6_PME_PM_L1_DCACHE_RELOAD_VALID ] = {
.pme_name = "PM_L1_DCACHE_RELOAD_VALID",
+ .pme_code = 0x3000f6,
.pme_short_desc = "L1 reload data source valid",
.pme_long_desc = "The data source information is valid",
- .pme_event_ids = { -1, -1, 154, 160, -1, -1 },
- .pme_group_vector = {
- 0x0000000000040000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L1_DCACHE_RELOAD_VALID],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L1_DCACHE_RELOAD_VALID]
},
-#define POWER6_PME_PM_LSU1_REJECT_UST 485
[ POWER6_PME_PM_LSU1_REJECT_UST ] = {
.pme_name = "PM_LSU1_REJECT_UST",
+ .pme_code = 0x9008a,
.pme_short_desc = "LSU1 unaligned store reject",
.pme_long_desc = "LSU1 unaligned store reject",
- .pme_event_ids = { 232, 241, 227, 232, -1, -1 },
- .pme_group_vector = {
- 0x4000000000000000ULL,
- 0x0000000000000002ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_REJECT_UST],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_REJECT_UST]
},
-#define POWER6_PME_PM_FAB_ADDR_COLLISION 486
[ POWER6_PME_PM_FAB_ADDR_COLLISION ] = {
.pme_name = "PM_FAB_ADDR_COLLISION",
+ .pme_code = 0x5018e,
.pme_short_desc = "local node launch collision with off-node address ",
.pme_long_desc = "local node launch collision with off-node address ",
- .pme_event_ids = { 58, 68, 58, 65, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000020000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FAB_ADDR_COLLISION],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FAB_ADDR_COLLISION]
},
-#define POWER6_PME_PM_MRK_FXU_FIN 487
[ POWER6_PME_PM_MRK_FXU_FIN ] = {
.pme_name = "PM_MRK_FXU_FIN",
+ .pme_code = 0x20001a,
.pme_short_desc = "Marked instruction FXU processing finished",
.pme_long_desc = "The fixed point units (Unit 0 + Unit 1) finished a marked instruction. Instructions that finish may not necessary complete.",
- .pme_event_ids = { -1, 277, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000200000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_FXU_FIN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_FXU_FIN]
},
-#define POWER6_PME_PM_LSU0_REJECT_UST 488
[ POWER6_PME_PM_LSU0_REJECT_UST ] = {
.pme_name = "PM_LSU0_REJECT_UST",
+ .pme_code = 0x90082,
.pme_short_desc = "LSU0 unaligned store reject",
.pme_long_desc = "LSU0 unaligned store reject",
- .pme_event_ids = { 219, 228, 214, 219, -1, -1 },
- .pme_group_vector = {
- 0x4000000000000000ULL,
- 0x0000000000000002ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT_UST],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT_UST]
},
-#define POWER6_PME_PM_PMC4_OVERFLOW 489
[ POWER6_PME_PM_PMC4_OVERFLOW ] = {
.pme_name = "PM_PMC4_OVERFLOW",
+ .pme_code = 0x100014,
.pme_short_desc = "PMC4 Overflow",
.pme_long_desc = "PMC4 Overflow",
- .pme_event_ids = { 292, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_PMC4_OVERFLOW],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PMC4_OVERFLOW]
},
-#define POWER6_PME_PM_MRK_PTEG_FROM_L3 490
[ POWER6_PME_PM_MRK_PTEG_FROM_L3 ] = {
.pme_name = "PM_MRK_PTEG_FROM_L3",
+ .pme_code = 0x312040,
.pme_short_desc = "Marked PTEG loaded from L3",
.pme_long_desc = "Marked PTEG loaded from L3",
- .pme_event_ids = { -1, -1, 273, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000020000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_L3],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_L3]
},
-#define POWER6_PME_PM_INST_FROM_L2MISS 491
[ POWER6_PME_PM_INST_FROM_L2MISS ] = {
.pme_name = "PM_INST_FROM_L2MISS",
+ .pme_code = 0x442054,
.pme_short_desc = "Instructions fetched missed L2",
.pme_long_desc = "An instruction fetch group was fetched from beyond L2.",
- .pme_event_ids = { -1, -1, -1, 151, -1, -1 },
- .pme_group_vector = {
- 0x0000000004400000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_L2MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_L2MISS]
},
-#define POWER6_PME_PM_L2SB_ST_HIT 492
[ POWER6_PME_PM_L2SB_ST_HIT ] = {
.pme_name = "PM_L2SB_ST_HIT",
+ .pme_code = 0x5078e,
.pme_short_desc = "L2 slice B store hits",
.pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A,B, and C.",
- .pme_event_ids = { 182, 191, 182, 188, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0001000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_ST_HIT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_ST_HIT]
},
-#define POWER6_PME_PM_DPU_WT_IC_MISS_COUNT 493
[ POWER6_PME_PM_DPU_WT_IC_MISS_COUNT ] = {
.pme_name = "PM_DPU_WT_IC_MISS_COUNT",
+ .pme_code = 0x20000d,
.pme_short_desc = "Periods DISP unit is stalled due to I cache miss",
.pme_long_desc = "Periods DISP unit is stalled due to I cache miss",
- .pme_event_ids = { -1, 357, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0080040000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_WT_IC_MISS_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_WT_IC_MISS_COUNT]
},
-#define POWER6_PME_PM_MRK_DATA_FROM_DL2L3_SHR 494
[ POWER6_PME_PM_MRK_DATA_FROM_DL2L3_SHR ] = {
.pme_name = "PM_MRK_DATA_FROM_DL2L3_SHR",
+ .pme_code = 0x30304c,
.pme_short_desc = "Marked data loaded from distant L2 or L3 shared",
.pme_long_desc = "Marked data loaded from distant L2 or L3 shared",
- .pme_event_ids = { -1, -1, 252, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000400ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_DL2L3_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_DL2L3_SHR]
},
-#define POWER6_PME_PM_MRK_PTEG_FROM_L35_MOD 495
[ POWER6_PME_PM_MRK_PTEG_FROM_L35_MOD ] = {
.pme_name = "PM_MRK_PTEG_FROM_L35_MOD",
+ .pme_code = 0x112046,
.pme_short_desc = "Marked PTEG loaded from L3.5 modified",
.pme_long_desc = "Marked PTEG loaded from L3.5 modified",
- .pme_event_ids = { 278, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000010000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_L35_MOD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_L35_MOD]
},
-#define POWER6_PME_PM_FPU1_FPSCR 496
[ POWER6_PME_PM_FPU1_FPSCR ] = {
.pme_name = "PM_FPU1_FPSCR",
+ .pme_code = 0xd008c,
.pme_short_desc = "FPU1 executed FPSCR instruction",
.pme_long_desc = "FPU1 executed FPSCR instruction",
- .pme_event_ids = { 93, 102, 91, 99, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x2000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_FPSCR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_FPSCR]
},
-#define POWER6_PME_PM_LSU_REJECT_UST 497
[ POWER6_PME_PM_LSU_REJECT_UST ] = {
.pme_name = "PM_LSU_REJECT_UST",
+ .pme_code = 0x290030,
.pme_short_desc = "Unaligned store reject",
.pme_long_desc = "Unaligned store reject",
- .pme_event_ids = { -1, 256, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x4000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_UST],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_UST]
},
-#define POWER6_PME_PM_LSU0_DERAT_MISS 498
[ POWER6_PME_PM_LSU0_DERAT_MISS ] = {
.pme_name = "PM_LSU0_DERAT_MISS",
+ .pme_code = 0x910a6,
.pme_short_desc = "LSU0 DERAT misses",
.pme_long_desc = "A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.",
- .pme_event_ids = { 204, 213, 199, 204, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x00000000000000a0ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_DERAT_MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_DERAT_MISS]
},
-#define POWER6_PME_PM_MRK_PTEG_FROM_MEM_DP 499
[ POWER6_PME_PM_MRK_PTEG_FROM_MEM_DP ] = {
.pme_name = "PM_MRK_PTEG_FROM_MEM_DP",
+ .pme_code = 0x112042,
.pme_short_desc = "Marked PTEG loaded from double pump memory",
.pme_long_desc = "Marked PTEG loaded from double pump memory",
- .pme_event_ids = { 279, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000020000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_MEM_DP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_MEM_DP]
},
-#define POWER6_PME_PM_MRK_DATA_FROM_L2 500
[ POWER6_PME_PM_MRK_DATA_FROM_L2 ] = {
.pme_name = "PM_MRK_DATA_FROM_L2",
+ .pme_code = 0x103048,
.pme_short_desc = "Marked data loaded from L2",
.pme_long_desc = "DL1 was reloaded from the local L2 due to a marked demand load",
- .pme_event_ids = { 259, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000800ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_L2],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_L2]
},
-#define POWER6_PME_PM_FPU0_FSQRT_FDIV 501
[ POWER6_PME_PM_FPU0_FSQRT_FDIV ] = {
.pme_name = "PM_FPU0_FSQRT_FDIV",
+ .pme_code = 0xc0084,
.pme_short_desc = "FPU0 executed FSQRT or FDIV instruction",
.pme_long_desc = "FPU0 executed FSQRT or FDIV instruction",
- .pme_event_ids = { 80, 89, 78, 86, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0080000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_FSQRT_FDIV],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_FSQRT_FDIV]
},
-#define POWER6_PME_PM_DPU_HELD_FXU_SOPS 502
[ POWER6_PME_PM_DPU_HELD_FXU_SOPS ] = {
.pme_name = "PM_DPU_HELD_FXU_SOPS",
+ .pme_code = 0x30088,
.pme_short_desc = "DISP unit held due to FXU slow ops (mtmsr",
.pme_long_desc = " scv",
- .pme_event_ids = { 38, 46, 37, 45, -1, -1 },
- .pme_group_vector = {
- 0x0000040000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_FXU_SOPS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_FXU_SOPS]
},
-#define POWER6_PME_PM_MRK_FPU0_FIN 503
[ POWER6_PME_PM_MRK_FPU0_FIN ] = {
.pme_name = "PM_MRK_FPU0_FIN",
+ .pme_code = 0xd0082,
.pme_short_desc = "Marked instruction FPU0 processing finished",
.pme_long_desc = "Marked instruction FPU0 processing finished",
- .pme_event_ids = { 265, 274, 259, 260, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000800100000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_FPU0_FIN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_FPU0_FIN]
},
-#define POWER6_PME_PM_L2SB_LD_MISS_DATA 504
[ POWER6_PME_PM_L2SB_LD_MISS_DATA ] = {
.pme_name = "PM_L2SB_LD_MISS_DATA",
+ .pme_code = 0x5048a,
.pme_short_desc = "L2 slice B data load misses",
.pme_long_desc = "L2 slice B data load misses",
- .pme_event_ids = { 176, 185, 176, 182, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000020000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_LD_MISS_DATA],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_LD_MISS_DATA]
},
-#define POWER6_PME_PM_LSU_SRQ_EMPTY_CYC 505
[ POWER6_PME_PM_LSU_SRQ_EMPTY_CYC ] = {
.pme_name = "PM_LSU_SRQ_EMPTY_CYC",
+ .pme_code = 0x40001c,
.pme_short_desc = "Cycles SRQ empty",
.pme_long_desc = "The Store Request Queue is empty",
- .pme_event_ids = { -1, -1, -1, 244, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000001ULL,
- 0x0010000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_SRQ_EMPTY_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_SRQ_EMPTY_CYC]
},
-#define POWER6_PME_PM_1PLUS_PPC_DISP 506
[ POWER6_PME_PM_1PLUS_PPC_DISP ] = {
.pme_name = "PM_1PLUS_PPC_DISP",
+ .pme_code = 0x100012,
.pme_short_desc = "Cycles at least one instruction dispatched",
.pme_long_desc = "Cycles at least one instruction dispatched",
- .pme_event_ids = { 2, -1, -1, 1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000100000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_1PLUS_PPC_DISP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_1PLUS_PPC_DISP]
},
-#define POWER6_PME_PM_VMX_ST_ISSUED 507
[ POWER6_PME_PM_VMX_ST_ISSUED ] = {
.pme_name = "PM_VMX_ST_ISSUED",
+ .pme_code = 0xb0080,
.pme_short_desc = "VMX store issued",
.pme_long_desc = "VMX store issued",
- .pme_event_ids = { 336, 343, 330, 328, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000001800000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX_ST_ISSUED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX_ST_ISSUED]
},
-#define POWER6_PME_PM_DATA_FROM_L2MISS 508
[ POWER6_PME_PM_DATA_FROM_L2MISS ] = {
.pme_name = "PM_DATA_FROM_L2MISS",
+ .pme_code = 0x2000fe,
.pme_short_desc = "Data loaded missed L2",
.pme_long_desc = "DL1 was reloaded from beyond L2.",
- .pme_event_ids = { -1, 17, 13, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000080ULL,
- 0x0000100000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L2MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L2MISS]
},
-#define POWER6_PME_PM_LSU0_REJECT_ULD 509
[ POWER6_PME_PM_LSU0_REJECT_ULD ] = {
.pme_name = "PM_LSU0_REJECT_ULD",
+ .pme_code = 0x90080,
.pme_short_desc = "LSU0 unaligned load reject",
.pme_long_desc = "LSU0 unaligned load reject",
- .pme_event_ids = { 218, 227, 213, 218, -1, -1 },
- .pme_group_vector = {
- 0x8000000000000000ULL,
- 0x0000000000000002ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT_ULD],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT_ULD]
},
-#define POWER6_PME_PM_SUSPENDED 510
[ POWER6_PME_PM_SUSPENDED ] = {
.pme_name = "PM_SUSPENDED",
+ .pme_code = 0x0,
.pme_short_desc = "Suspended",
.pme_long_desc = "Suspended",
- .pme_event_ids = { 311, 318, 302, 302, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000010ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_SUSPENDED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_SUSPENDED]
},
-#define POWER6_PME_PM_DFU_ADD_SHIFTED_BOTH 511
[ POWER6_PME_PM_DFU_ADD_SHIFTED_BOTH ] = {
.pme_name = "PM_DFU_ADD_SHIFTED_BOTH",
+ .pme_code = 0xe0088,
.pme_short_desc = "DFU add type with both operands shifted",
.pme_long_desc = "DFU add type with both operands shifted",
- .pme_event_ids = { 24, 31, 23, 31, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000002000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DFU_ADD_SHIFTED_BOTH],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DFU_ADD_SHIFTED_BOTH]
},
-#define POWER6_PME_PM_LSU_REJECT_NO_SCRATCH 512
[ POWER6_PME_PM_LSU_REJECT_NO_SCRATCH ] = {
.pme_name = "PM_LSU_REJECT_NO_SCRATCH",
+ .pme_code = 0x2a1034,
.pme_short_desc = "LSU reject due to scratch register not available",
.pme_long_desc = "LSU reject due to scratch register not available",
- .pme_event_ids = { -1, 251, 237, -1, -1, -1 },
- .pme_group_vector = {
- 0x2000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_NO_SCRATCH],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_NO_SCRATCH]
},
-#define POWER6_PME_PM_STCX_FAIL 513
[ POWER6_PME_PM_STCX_FAIL ] = {
.pme_name = "PM_STCX_FAIL",
+ .pme_code = 0x830ee,
.pme_short_desc = "STCX failed",
.pme_long_desc = "A stcx (stwcx or stdcx) failed",
- .pme_event_ids = { 306, 312, 298, 297, -1, -1 },
- .pme_group_vector = {
- 0x0018000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_STCX_FAIL],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_STCX_FAIL]
},
-#define POWER6_PME_PM_FPU1_DENORM 514
[ POWER6_PME_PM_FPU1_DENORM ] = {
.pme_name = "PM_FPU1_DENORM",
+ .pme_code = 0xc10aa,
.pme_short_desc = "FPU1 received denormalized data",
.pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.",
- .pme_event_ids = { 87, 96, 85, 93, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x1000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_DENORM],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_DENORM]
},
-#define POWER6_PME_PM_GCT_NOSLOT_COUNT 515
[ POWER6_PME_PM_GCT_NOSLOT_COUNT ] = {
.pme_name = "PM_GCT_NOSLOT_COUNT",
+ .pme_code = 0x100009,
.pme_short_desc = "Periods no GCT slot allocated",
.pme_long_desc = "Periods this thread does not have any slots allocated in the GCT.",
- .pme_event_ids = { 349, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0008010000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_GCT_NOSLOT_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GCT_NOSLOT_COUNT]
},
-#define POWER6_PME_PM_DATA_FROM_DL2L3_SHR_CYC 516
[ POWER6_PME_PM_DATA_FROM_DL2L3_SHR_CYC ] = {
.pme_name = "PM_DATA_FROM_DL2L3_SHR_CYC",
+ .pme_code = 0x20002a,
.pme_short_desc = "Load latency from distant L2 or L3 shared",
.pme_long_desc = "Load latency from distant L2 or L3 shared",
- .pme_event_ids = { -1, 12, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000008000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_DL2L3_SHR_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_DL2L3_SHR_CYC]
},
-#define POWER6_PME_PM_DATA_FROM_L21 517
[ POWER6_PME_PM_DATA_FROM_L21 ] = {
.pme_name = "PM_DATA_FROM_L21",
+ .pme_code = 0x200058,
.pme_short_desc = "Data loaded from private L2 other core",
.pme_long_desc = "Data loaded from private L2 other core",
- .pme_event_ids = { -1, 15, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000080080ULL,
- 0x0000000000000000ULL,
- 0x8000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L21],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L21]
},
-#define POWER6_PME_PM_FPU_1FLOP 518
[ POWER6_PME_PM_FPU_1FLOP ] = {
.pme_name = "PM_FPU_1FLOP",
+ .pme_code = 0x1c0030,
.pme_short_desc = "FPU executed one flop instruction ",
.pme_long_desc = "This event counts the number of one flop instructions. These could be fadd*, fmul*, fsub*, fneg+, fabs+, fnabs+, fres+, frsqrte+, fcmp**, or fsel where XYZ* means XYZ, XYZs, XYZ., XYZs., XYZ+ means XYZ, XYZ., and XYZ** means XYZu, XYZo.",
- .pme_event_ids = { 101, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x8000000000000000ULL,
- 0x0400000000000000ULL,
- 0x0000000000000002ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_1FLOP],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_1FLOP]
},
-#define POWER6_PME_PM_LSU1_REJECT 519
[ POWER6_PME_PM_LSU1_REJECT ] = {
.pme_name = "PM_LSU1_REJECT",
+ .pme_code = 0xa10ae,
.pme_short_desc = "LSU1 reject",
.pme_long_desc = "LSU1 reject",
- .pme_event_ids = { 222, 231, 217, 222, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000044ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_REJECT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_REJECT]
},
-#define POWER6_PME_PM_IC_REQ 520
[ POWER6_PME_PM_IC_REQ ] = {
.pme_name = "PM_IC_REQ",
+ .pme_code = 0x4008a,
.pme_short_desc = "I cache demand of prefetch request",
.pme_long_desc = "I cache demand of prefetch request",
- .pme_event_ids = { 136, 145, 135, 142, -1, -1 },
- .pme_group_vector = {
- 0x0004000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_IC_REQ],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IC_REQ]
},
-#define POWER6_PME_PM_MRK_DFU_FIN 521
[ POWER6_PME_PM_MRK_DFU_FIN ] = {
.pme_name = "PM_MRK_DFU_FIN",
+ .pme_code = 0x300008,
.pme_short_desc = "DFU marked instruction finish",
.pme_long_desc = "DFU marked instruction finish",
- .pme_event_ids = { -1, -1, 257, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000200000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DFU_FIN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DFU_FIN]
},
-#define POWER6_PME_PM_NOT_LLA_CYC 522
[ POWER6_PME_PM_NOT_LLA_CYC ] = {
.pme_name = "PM_NOT_LLA_CYC",
+ .pme_code = 0x401e,
.pme_short_desc = "Load Look Ahead not Active",
.pme_long_desc = "Load Look Ahead not Active",
- .pme_event_ids = { 346, 353, 338, 338, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_NOT_LLA_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_NOT_LLA_CYC]
},
-#define POWER6_PME_PM_INST_FROM_L1 523
[ POWER6_PME_PM_INST_FROM_L1 ] = {
.pme_name = "PM_INST_FROM_L1",
+ .pme_code = 0x40082,
.pme_short_desc = "Instruction fetched from L1",
.pme_long_desc = "An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions",
- .pme_event_ids = { 142, 153, 143, 149, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000001000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_L1],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_L1]
},
-#define POWER6_PME_PM_MRK_VMX_COMPLEX_ISSUED 524
[ POWER6_PME_PM_MRK_VMX_COMPLEX_ISSUED ] = {
.pme_name = "PM_MRK_VMX_COMPLEX_ISSUED",
+ .pme_code = 0x7008c,
.pme_short_desc = "Marked VMX instruction issued to complex",
.pme_long_desc = "Marked VMX instruction issued to complex",
- .pme_event_ids = { 285, 297, 280, 282, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000100000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_VMX_COMPLEX_ISSUED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_VMX_COMPLEX_ISSUED]
},
-#define POWER6_PME_PM_BRU_FIN 525
[ POWER6_PME_PM_BRU_FIN ] = {
.pme_name = "PM_BRU_FIN",
+ .pme_code = 0x430e6,
.pme_short_desc = "BRU produced a result",
.pme_long_desc = "BRU produced a result",
- .pme_event_ids = { 3, 1, 1, 2, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000040ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_BRU_FIN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_BRU_FIN]
},
-#define POWER6_PME_PM_LSU1_REJECT_EXTERN 526
[ POWER6_PME_PM_LSU1_REJECT_EXTERN ] = {
.pme_name = "PM_LSU1_REJECT_EXTERN",
+ .pme_code = 0xa10ac,
.pme_short_desc = "LSU1 external reject request ",
.pme_long_desc = "LSU1 external reject request ",
- .pme_event_ids = { 224, 233, 219, 224, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000008ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_REJECT_EXTERN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_REJECT_EXTERN]
},
-#define POWER6_PME_PM_DATA_FROM_L21_CYC 527
[ POWER6_PME_PM_DATA_FROM_L21_CYC ] = {
.pme_name = "PM_DATA_FROM_L21_CYC",
+ .pme_code = 0x400020,
.pme_short_desc = "Load latency from private L2 other core",
.pme_long_desc = "Load latency from private L2 other core",
- .pme_event_ids = { -1, -1, -1, 15, -1, -1 },
- .pme_group_vector = {
- 0x0000000000080000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L21_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L21_CYC]
},
-#define POWER6_PME_PM_GXI_CYC_BUSY 528
[ POWER6_PME_PM_GXI_CYC_BUSY ] = {
.pme_name = "PM_GXI_CYC_BUSY",
+ .pme_code = 0x50386,
.pme_short_desc = "Inbound GX bus utilizations (# of cycles in use)",
.pme_long_desc = "Inbound GX bus utilizations (# of cycles in use)",
- .pme_event_ids = { 123, 130, 121, 129, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000e00000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_GXI_CYC_BUSY],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GXI_CYC_BUSY]
},
-#define POWER6_PME_PM_MRK_LD_MISS_L1 529
[ POWER6_PME_PM_MRK_LD_MISS_L1 ] = {
.pme_name = "PM_MRK_LD_MISS_L1",
+ .pme_code = 0x200056,
.pme_short_desc = "Marked L1 D cache load misses",
.pme_long_desc = "Marked L1 D cache load misses",
- .pme_event_ids = { -1, 280, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000200ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LD_MISS_L1],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LD_MISS_L1]
},
-#define POWER6_PME_PM_L1_WRITE_CYC 530
[ POWER6_PME_PM_L1_WRITE_CYC ] = {
.pme_name = "PM_L1_WRITE_CYC",
+ .pme_code = 0x430e2,
.pme_short_desc = "Cycles writing to instruction L1",
.pme_long_desc = "This signal is asserted each cycle a cache write is active.",
- .pme_event_ids = { 156, 165, 156, 162, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000001000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_L1_WRITE_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L1_WRITE_CYC]
},
-#define POWER6_PME_PM_LLA_CYC 531
[ POWER6_PME_PM_LLA_CYC ] = {
.pme_name = "PM_LLA_CYC",
+ .pme_code = 0xc01e,
.pme_short_desc = "Load Look Ahead Active",
.pme_long_desc = "Load Look Ahead Active",
- .pme_event_ids = { 345, 352, 337, 337, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000080000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LLA_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LLA_CYC]
},
-#define POWER6_PME_PM_MRK_DATA_FROM_L2MISS 532
[ POWER6_PME_PM_MRK_DATA_FROM_L2MISS ] = {
.pme_name = "PM_MRK_DATA_FROM_L2MISS",
+ .pme_code = 0x103028,
.pme_short_desc = "Marked data loaded missed L2",
.pme_long_desc = "DL1 was reloaded from beyond L2 due to a marked demand load.",
- .pme_event_ids = { 260, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000001000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_L2MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_L2MISS]
},
-#define POWER6_PME_PM_GCT_FULL_COUNT 533
[ POWER6_PME_PM_GCT_FULL_COUNT ] = {
.pme_name = "PM_GCT_FULL_COUNT",
+ .pme_code = 0x40087,
.pme_short_desc = "Periods GCT full",
.pme_long_desc = "The ISU sends a signal indicating the gct is full.",
- .pme_event_ids = { 339, 346, 333, 331, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000410000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_GCT_FULL_COUNT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GCT_FULL_COUNT]
},
-#define POWER6_PME_PM_MEM_DP_RQ_LOC_GLOB 534
[ POWER6_PME_PM_MEM_DP_RQ_LOC_GLOB ] = {
.pme_name = "PM_MEM_DP_RQ_LOC_GLOB",
+ .pme_code = 0x250230,
.pme_short_desc = "Memory read queue marking cache line double pump state from local to global",
.pme_long_desc = "Memory read queue marking cache line double pump state from local to global",
- .pme_event_ids = { -1, 268, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000040000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM_DP_RQ_LOC_GLOB],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM_DP_RQ_LOC_GLOB]
},
-#define POWER6_PME_PM_DATA_FROM_RL2L3_SHR 535
[ POWER6_PME_PM_DATA_FROM_RL2L3_SHR ] = {
.pme_name = "PM_DATA_FROM_RL2L3_SHR",
+ .pme_code = 0x20005c,
.pme_short_desc = "Data loaded from remote L2 or L3 shared",
.pme_long_desc = "Data loaded from remote L2 or L3 shared",
- .pme_event_ids = { -1, 23, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000400ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_RL2L3_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_RL2L3_SHR]
},
-#define POWER6_PME_PM_MRK_LSU_REJECT_UST 536
[ POWER6_PME_PM_MRK_LSU_REJECT_UST ] = {
.pme_name = "PM_MRK_LSU_REJECT_UST",
+ .pme_code = 0x293034,
.pme_short_desc = "Marked unaligned store reject",
.pme_long_desc = "Marked unaligned store reject",
- .pme_event_ids = { -1, 288, 270, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000010000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU_REJECT_UST],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU_REJECT_UST]
},
-#define POWER6_PME_PM_MRK_VMX_PERMUTE_ISSUED 537
[ POWER6_PME_PM_MRK_VMX_PERMUTE_ISSUED ] = {
.pme_name = "PM_MRK_VMX_PERMUTE_ISSUED",
+ .pme_code = 0x7008e,
.pme_short_desc = "Marked VMX instruction issued to permute",
.pme_long_desc = "Marked VMX instruction issued to permute",
- .pme_event_ids = { 287, 299, 282, 284, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000100000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_VMX_PERMUTE_ISSUED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_VMX_PERMUTE_ISSUED]
},
-#define POWER6_PME_PM_MRK_PTEG_FROM_L21 538
[ POWER6_PME_PM_MRK_PTEG_FROM_L21 ] = {
.pme_name = "PM_MRK_PTEG_FROM_L21",
+ .pme_code = 0x212040,
.pme_short_desc = "Marked PTEG loaded from private L2 other core",
.pme_long_desc = "Marked PTEG loaded from private L2 other core",
- .pme_event_ids = { -1, 290, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000008000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_L21],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_L21]
},
-#define POWER6_PME_PM_THRD_GRP_CMPL_BOTH_CYC 539
[ POWER6_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = {
.pme_name = "PM_THRD_GRP_CMPL_BOTH_CYC",
+ .pme_code = 0x200018,
.pme_short_desc = "Cycles group completed by both threads",
.pme_long_desc = "Cycles group completed by both threads",
- .pme_event_ids = { -1, 320, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0020000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_GRP_CMPL_BOTH_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_GRP_CMPL_BOTH_CYC]
},
-#define POWER6_PME_PM_BR_MPRED 540
[ POWER6_PME_PM_BR_MPRED ] = {
.pme_name = "PM_BR_MPRED",
+ .pme_code = 0x400052,
.pme_short_desc = "Branches incorrectly predicted",
.pme_long_desc = "Branches incorrectly predicted",
- .pme_event_ids = { -1, -1, -1, 3, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000040ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_BR_MPRED],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_BR_MPRED]
},
-#define POWER6_PME_PM_LD_REQ_L2 541
[ POWER6_PME_PM_LD_REQ_L2 ] = {
.pme_name = "PM_LD_REQ_L2",
+ .pme_code = 0x150730,
.pme_short_desc = "L2 load requests ",
.pme_long_desc = "L2 load requests ",
- .pme_event_ids = { 203, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000010000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LD_REQ_L2],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LD_REQ_L2]
},
-#define POWER6_PME_PM_FLUSH_ASYNC 542
[ POWER6_PME_PM_FLUSH_ASYNC ] = {
.pme_name = "PM_FLUSH_ASYNC",
+ .pme_code = 0x220ca,
.pme_short_desc = "Flush caused by asynchronous exception",
.pme_long_desc = "Flush caused by asynchronous exception",
- .pme_event_ids = { 68, 77, 66, 74, -1, -1 },
- .pme_group_vector = {
- 0x0002000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FLUSH_ASYNC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FLUSH_ASYNC]
},
-#define POWER6_PME_PM_HV_CYC 543
[ POWER6_PME_PM_HV_CYC ] = {
.pme_name = "PM_HV_CYC",
+ .pme_code = 0x200016,
.pme_short_desc = "Hypervisor Cycles",
.pme_long_desc = "Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)",
- .pme_event_ids = { -1, 137, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0040000000000000ULL,
- 0x0000000000000000ULL,
- 0x0001000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_HV_CYC],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_HV_CYC]
},
-#define POWER6_PME_PM_LSU1_DERAT_MISS 544
[ POWER6_PME_PM_LSU1_DERAT_MISS ] = {
.pme_name = "PM_LSU1_DERAT_MISS",
+ .pme_code = 0x910ae,
.pme_short_desc = "LSU1 DERAT misses",
.pme_long_desc = "A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.",
- .pme_event_ids = { 220, 229, 215, 220, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x00000000000000a0ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_DERAT_MISS],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_DERAT_MISS]
},
-#define POWER6_PME_PM_DPU_HELD_SMT 545
[ POWER6_PME_PM_DPU_HELD_SMT ] = {
.pme_name = "PM_DPU_HELD_SMT",
+ .pme_code = 0x20082,
.pme_short_desc = "DISP unit held due to SMT conflicts ",
.pme_long_desc = "DISP unit held due to SMT conflicts ",
- .pme_event_ids = { 49, 58, 48, 56, -1, -1 },
- .pme_group_vector = {
- 0x0000001000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_SMT],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_SMT]
},
-#define POWER6_PME_PM_MRK_LSU_FIN 546
[ POWER6_PME_PM_MRK_LSU_FIN ] = {
.pme_name = "PM_MRK_LSU_FIN",
+ .pme_code = 0x40001a,
.pme_short_desc = "Marked instruction LSU processing finished",
.pme_long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, -1, -1, 272, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000001000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU_FIN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU_FIN]
},
-#define POWER6_PME_PM_MRK_DATA_FROM_RL2L3_SHR 547
[ POWER6_PME_PM_MRK_DATA_FROM_RL2L3_SHR ] = {
.pme_name = "PM_MRK_DATA_FROM_RL2L3_SHR",
+ .pme_code = 0x20304c,
.pme_short_desc = "Marked data loaded from remote L2 or L3 shared",
.pme_long_desc = "Marked data loaded from remote L2 or L3 shared",
- .pme_event_ids = { -1, 272, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x000000000000c000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_RL2L3_SHR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_RL2L3_SHR]
},
-#define POWER6_PME_PM_LSU0_REJECT_STQ_FULL 548
[ POWER6_PME_PM_LSU0_REJECT_STQ_FULL ] = {
.pme_name = "PM_LSU0_REJECT_STQ_FULL",
+ .pme_code = 0xa0080,
.pme_short_desc = "LSU0 reject due to store queue full",
.pme_long_desc = "LSU0 reject due to store queue full",
- .pme_event_ids = { 217, 226, 212, 217, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000040ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT_STQ_FULL],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT_STQ_FULL]
},
-#define POWER6_PME_PM_MRK_DERAT_REF_4K 549
[ POWER6_PME_PM_MRK_DERAT_REF_4K ] = {
.pme_name = "PM_MRK_DERAT_REF_4K",
+ .pme_code = 0x282044,
.pme_short_desc = "Marked DERAT reference for 4K page",
.pme_long_desc = "Marked DERAT reference for 4K page",
- .pme_event_ids = { -1, 363, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000001000000000ULL,
- 0x0000000000000010ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DERAT_REF_4K],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DERAT_REF_4K]
},
-#define POWER6_PME_PM_FPU_ISSUE_STALL_FPR 550
[ POWER6_PME_PM_FPU_ISSUE_STALL_FPR ] = {
.pme_name = "PM_FPU_ISSUE_STALL_FPR",
+ .pme_code = 0x330e2,
.pme_short_desc = "FPU issue stalled due to FPR dependencies",
.pme_long_desc = "FPU issue stalled due to FPR dependencies",
- .pme_event_ids = { 112, 120, 108, 117, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0040000000000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_ISSUE_STALL_FPR],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_ISSUE_STALL_FPR]
},
-#define POWER6_PME_PM_IFU_FIN 551
[ POWER6_PME_PM_IFU_FIN ] = {
.pme_name = "PM_IFU_FIN",
+ .pme_code = 0x430e4,
.pme_short_desc = "IFU finished an instruction",
.pme_long_desc = "IFU finished an instruction",
- .pme_event_ids = { 138, 147, 137, 144, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000000080000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_IFU_FIN],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IFU_FIN]
},
-#define POWER6_PME_PM_GXO_CYC_BUSY 552
[ POWER6_PME_PM_GXO_CYC_BUSY ] = {
.pme_name = "PM_GXO_CYC_BUSY",
+ .pme_code = 0x50380,
.pme_short_desc = "Outbound GX bus utilizations (# of cycles in use)",
.pme_long_desc = "Outbound GX bus utilizations (# of cycles in use)",
- .pme_event_ids = { 126, 133, 124, 132, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL,
- 0x0000000e00000000ULL,
- 0x0000000000000000ULL,
- 0x0000000000000000ULL }
+ .pme_event_ids = power6_event_ids[POWER6_PME_PM_GXO_CYC_BUSY],
+ .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GXO_CYC_BUSY]
}
};
#define POWER6_PME_EVENT_COUNT 553
-static pmg_power6_group_t power6_groups[] = {
+static const int power6_group_event_ids[][POWER6_NUM_EVENT_COUNTERS] = {
+ [ 0 ] = { 302, 148, 139, 12, 0, 0 },
+ [ 1 ] = { 315, 11, 306, 347, 0, 0 },
+ [ 2 ] = { 10, 4, 6, 5, 0, 0 },
+ [ 3 ] = { 9, 9, 2, 7, 0, 0 },
+ [ 4 ] = { 8, 8, 7, 11, 0, 0 },
+ [ 5 ] = { 6, 3, 5, 4, 0, 0 },
+ [ 6 ] = { 8, 10, 1, 3, 0, 0 },
+ [ 7 ] = { 13, 15, 13, 19, 0, 0 },
+ [ 8 ] = { 14, 19, 14, 19, 0, 0 },
+ [ 9 ] = { 14, 19, 12, 16, 0, 0 },
+ [ 10 ] = { 16, 23, 11, 13, 0, 0 },
+ [ 11 ] = { 15, 13, 16, 20, 0, 0 },
+ [ 12 ] = { 200, 24, 10, 17, 0, 0 },
+ [ 13 ] = { 139, 22, 10, 14, 0, 0 },
+ [ 14 ] = { 139, 14, 16, 23, 0, 0 },
+ [ 15 ] = { 14, 12, 11, 18, 0, 0 },
+ [ 16 ] = { 16, 21, 14, 22, 0, 0 },
+ [ 17 ] = { 15, 16, 12, 21, 0, 0 },
+ [ 18 ] = { 13, 18, 139, 160, 0, 0 },
+ [ 19 ] = { 67, 15, 10, 15, 0, 0 },
+ [ 20 ] = { 2, 22, 139, 20, 0, 0 },
+ [ 21 ] = { 14, 20, 10, 18, 0, 0 },
+ [ 22 ] = { 143, 154, 144, 151, 0, 0 },
+ [ 23 ] = { 144, 155, 145, 150, 0, 0 },
+ [ 24 ] = { 146, 156, 142, 148, 0, 0 },
+ [ 25 ] = { 145, 152, 147, 152, 0, 0 },
+ [ 26 ] = { 143, 154, 146, 151, 0, 0 },
+ [ 27 ] = { 295, 305, 291, 290, 0, 0 },
+ [ 28 ] = { 296, 305, 292, 289, 0, 0 },
+ [ 29 ] = { 297, 306, 293, 291, 0, 0 },
+ [ 30 ] = { 298, 304, 294, 291, 0, 0 },
+ [ 31 ] = { 299, 307, 290, 292, 0, 0 },
+ [ 32 ] = { 17, 26, 19, 312, 0, 0 },
+ [ 33 ] = { 148, 158, 150, 157, 0, 0 },
+ [ 34 ] = { 52, 55, 115, 123, 0, 0 },
+ [ 35 ] = { 154, 64, 54, 62, 0, 0 },
+ [ 36 ] = { 52, 55, 305, 56, 0, 0 },
+ [ 37 ] = { 39, 38, 32, 41, 0, 0 },
+ [ 38 ] = { 54, 49, 50, 55, 0, 0 },
+ [ 39 ] = { 35, 52, 41, 44, 0, 0 },
+ [ 40 ] = { 36, 54, 30, 46, 0, 0 },
+ [ 41 ] = { 40, 63, 42, 54, 0, 0 },
+ [ 42 ] = { 38, 61, 49, 39, 0, 0 },
+ [ 43 ] = { 41, 60, 47, 42, 0, 0 },
+ [ 44 ] = { 41, 43, 45, 38, 0, 0 },
+ [ 45 ] = { 247, 11, 303, 52, 0, 0 },
+ [ 46 ] = { 202, 212, 300, 301, 0, 0 },
+ [ 47 ] = { 310, 212, 299, 202, 0, 0 },
+ [ 48 ] = { 21, 29, 155, 136, 0, 0 },
+ [ 49 ] = { 67, 77, 67, 76, 0, 0 },
+ [ 50 ] = { 136, 142, 134, 140, 0, 0 },
+ [ 51 ] = { 304, 311, 298, 200, 0, 0 },
+ [ 52 ] = { 197, 208, 296, 297, 0, 0 },
+ [ 53 ] = { 315, 320, 306, 304, 0, 0 },
+ [ 54 ] = { 1, 137, 313, 306, 0, 0 },
+ [ 55 ] = { 57, 67, 304, 0, 0, 0 },
+ [ 56 ] = { 307, 321, 10, 145, 0, 0 },
+ [ 57 ] = { 152, 65, 314, 159, 0, 0 },
+ [ 58 ] = { 152, 65, 136, 294, 0, 0 },
+ [ 59 ] = { 239, 249, 236, 238, 0, 0 },
+ [ 60 ] = { 240, 250, 235, 243, 0, 0 },
+ [ 61 ] = { 243, 253, 237, 242, 0, 0 },
+ [ 62 ] = { 245, 256, 214, 232, 0, 0 },
+ [ 63 ] = { 244, 255, 213, 231, 0, 0 },
+ [ 64 ] = { 216, 238, 238, 244, 0, 0 },
+ [ 65 ] = { 218, 241, 214, 231, 0, 0 },
+ [ 66 ] = { 208, 218, 217, 227, 0, 0 },
+ [ 67 ] = { 210, 221, 219, 225, 0, 0 },
+ [ 68 ] = { 214, 224, 222, 228, 0, 0 },
+ [ 69 ] = { 213, 213, 221, 220, 0, 0 },
+ [ 70 ] = { 217, 217, 225, 222, 0, 0 },
+ [ 71 ] = { 209, 213, 218, 220, 0, 0 },
+ [ 72 ] = { 237, 246, 200, 221, 0, 0 },
+ [ 73 ] = { 206, 216, 240, 233, 0, 0 },
+ [ 74 ] = { 238, 248, 234, 211, 0, 0 },
+ [ 75 ] = { 234, 243, 229, 236, 0, 0 },
+ [ 76 ] = { 140, 51, 139, 306, 0, 0 },
+ [ 77 ] = { 121, 127, 119, 147, 0, 0 },
+ [ 78 ] = { 316, 322, 308, 307, 0, 0 },
+ [ 79 ] = { 317, 323, 309, 308, 0, 0 },
+ [ 80 ] = { 318, 324, 310, 309, 0, 0 },
+ [ 81 ] = { 319, 325, 311, 310, 0, 0 },
+ [ 82 ] = { 117, 125, 116, 124, 0, 0 },
+ [ 83 ] = { 118, 147, 117, 125, 0, 0 },
+ [ 84 ] = { 329, 337, 329, 324, 0, 0 },
+ [ 85 ] = { 321, 332, 316, 318, 0, 0 },
+ [ 86 ] = { 322, 330, 320, 319, 0, 0 },
+ [ 87 ] = { 331, 340, 328, 328, 0, 0 },
+ [ 88 ] = { 336, 331, 322, 323, 0, 0 },
+ [ 89 ] = { 23, 31, 24, 33, 0, 0 },
+ [ 90 ] = { 27, 35, 28, 37, 0, 0 },
+ [ 91 ] = { 59, 69, 59, 67, 0, 0 },
+ [ 92 ] = { 63, 74, 64, 72, 0, 0 },
+ [ 93 ] = { 59, 69, 58, 68, 0, 0 },
+ [ 94 ] = { 257, 268, 250, 255, 0, 0 },
+ [ 95 ] = { 250, 262, 242, 248, 0, 0 },
+ [ 96 ] = { 254, 266, 246, 252, 0, 0 },
+ [ 97 ] = { 126, 132, 125, 129, 0, 0 },
+ [ 98 ] = { 123, 129, 122, 132, 0, 0 },
+ [ 99 ] = { 126, 130, 126, 135, 0, 0 },
+ [ 100 ] = { 142, 165, 285, 153, 0, 0 },
+ [ 101 ] = { 186, 195, 188, 193, 0, 0 },
+ [ 102 ] = { 187, 196, 185, 191, 0, 0 },
+ [ 103 ] = { 185, 194, 131, 27, 0, 0 },
+ [ 104 ] = { 203, 209, 301, 298, 0, 0 },
+ [ 105 ] = { 165, 171, 179, 182, 0, 0 },
+ [ 106 ] = { 166, 172, 180, 183, 0, 0 },
+ [ 107 ] = { 170, 178, 184, 189, 0, 0 },
+ [ 108 ] = { 167, 197, 13, 187, 0, 0 },
+ [ 109 ] = { 157, 167, 171, 178, 0, 0 },
+ [ 110 ] = { 160, 168, 174, 179, 0, 0 },
+ [ 111 ] = { 164, 170, 178, 181, 0, 0 },
+ [ 112 ] = { 170, 177, 184, 188, 0, 0 },
+ [ 113 ] = { 131, 140, 187, 191, 0, 0 },
+ [ 114 ] = { 193, 201, 14, 195, 0, 0 },
+ [ 115 ] = { 196, 204, 14, 198, 0, 0 },
+ [ 116 ] = { 107, 116, 105, 120, 0, 0 },
+ [ 117 ] = { 111, 124, 106, 118, 0, 0 },
+ [ 118 ] = { 114, 120, 106, 118, 0, 0 },
+ [ 119 ] = { 71, 86, 78, 90, 0, 0 },
+ [ 120 ] = { 76, 90, 70, 89, 0, 0 },
+ [ 121 ] = { 75, 83, 76, 88, 0, 0 },
+ [ 122 ] = { 73, 88, 83, 80, 0, 0 },
+ [ 123 ] = { 86, 101, 93, 105, 0, 0 },
+ [ 124 ] = { 91, 105, 85, 104, 0, 0 },
+ [ 125 ] = { 90, 98, 91, 103, 0, 0 },
+ [ 126 ] = { 88, 103, 98, 95, 0, 0 },
+ [ 127 ] = { 101, 111, 102, 109, 0, 0 },
+ [ 128 ] = { 103, 113, 100, 111, 0, 0 },
+ [ 129 ] = { 105, 110, 113, 122, 0, 0 },
+ [ 130 ] = { 102, 113, 114, 108, 0, 0 },
+ [ 131 ] = { 301, 309, 10, 145, 0, 0 },
+ [ 132 ] = { 311, 11, 303, 145, 0, 0 },
+ [ 133 ] = { 200, 243, 197, 234, 0, 0 },
+ [ 134 ] = { 351, 361, 343, 343, 0, 0 },
+ [ 135 ] = { 350, 360, 342, 342, 0, 0 },
+ [ 136 ] = { 352, 362, 344, 344, 0, 0 },
+ [ 137 ] = { 258, 280, 251, 145, 0, 0 },
+ [ 138 ] = { 139, 269, 252, 256, 0, 0 },
+ [ 139 ] = { 259, 270, 253, 145, 0, 0 },
+ [ 140 ] = { 260, 148, 254, 257, 0, 0 },
+ [ 141 ] = { 261, 271, 255, 145, 0, 0 },
+ [ 142 ] = { 262, 272, 138, 258, 0, 0 },
+ [ 143 ] = { 263, 272, 256, 145, 0, 0 },
+ [ 144 ] = { 276, 288, 138, 273, 0, 0 },
+ [ 145 ] = { 270, 283, 266, 145, 0, 0 },
+ [ 146 ] = { 273, 286, 269, 145, 0, 0 },
+ [ 147 ] = { 268, 279, 262, 145, 0, 0 },
+ [ 148 ] = { 265, 275, 261, 145, 0, 0 },
+ [ 149 ] = { 276, 277, 257, 145, 0, 0 },
+ [ 150 ] = { 281, 278, 138, 263, 0, 0 },
+ [ 151 ] = { 289, 281, 138, 271, 0, 0 },
+ [ 152 ] = { 12, 11, 138, 272, 0, 0 },
+ [ 153 ] = { 282, 294, 277, 145, 0, 0 },
+ [ 154 ] = { 277, 289, 271, 145, 0, 0 },
+ [ 155 ] = { 139, 290, 272, 275, 0, 0 },
+ [ 156 ] = { 278, 291, 138, 276, 0, 0 },
+ [ 157 ] = { 279, 148, 273, 277, 0, 0 },
+ [ 158 ] = { 280, 148, 274, 278, 0, 0 },
+ [ 159 ] = { 12, 292, 275, 145, 0, 0 },
+ [ 160 ] = { 285, 298, 282, 145, 0, 0 },
+ [ 161 ] = { 283, 296, 258, 145, 0, 0 },
+ [ 162 ] = { 288, 342, 10, 145, 0, 0 },
+ [ 163 ] = { 265, 276, 260, 145, 0, 0 },
+ [ 164 ] = { 353, 363, 345, 145, 0, 0 },
+ [ 165 ] = { 354, 364, 346, 145, 0, 0 },
+ [ 166 ] = { 199, 243, 197, 335, 0, 0 },
+ [ 167 ] = { 238, 359, 341, 211, 0, 0 },
+ [ 168 ] = { 349, 358, 333, 147, 0, 0 },
+ [ 169 ] = { 348, 356, 115, 123, 0, 0 },
+ [ 170 ] = { 154, 357, 340, 340, 0, 0 },
+ [ 171 ] = { 199, 64, 339, 337, 0, 0 },
+ [ 172 ] = { 337, 0, 332, 136, 0, 0 },
+ [ 173 ] = { 343, 309, 335, 157, 0, 0 },
+ [ 174 ] = { 339, 128, 334, 287, 0, 0 },
+ [ 175 ] = { 344, 351, 336, 303, 0, 0 },
+ [ 176 ] = { 315, 137, 336, 303, 0, 0 },
+ [ 177 ] = { 348, 355, 340, 340, 0, 0 },
+ [ 178 ] = { 52, 38, 54, 62, 0, 0 },
+ [ 179 ] = { 349, 358, 341, 341, 0, 0 },
+ [ 180 ] = { 121, 127, 234, 244, 0, 0 },
+ [ 181 ] = { 342, 359, 303, 335, 0, 0 },
+ [ 182 ] = { 312, 248, 336, 234, 0, 0 },
+ [ 183 ] = { 309, 357, 197, 203, 0, 0 },
+ [ 184 ] = { 31, 356, 31, 336, 0, 0 },
+ [ 185 ] = { 31, 55, 31, 304, 0, 0 },
+ [ 186 ] = { 101, 111, 102, 12, 0, 0 },
+ [ 187 ] = { 139, 246, 113, 12, 0, 0 },
+ [ 188 ] = { 12, 210, 299, 145, 0, 0 },
+ [ 189 ] = { 139, 149, 198, 300, 0, 0 },
+ [ 190 ] = { 103, 11, 117, 125, 0, 0 },
+ [ 191 ] = { 13, 15, 12, 16, 0, 0 },
+ [ 192 ] = { 14, 19, 14, 12, 0, 0 },
+ [ 193 ] = { 101, 111, 113, 202, 0, 0 },
+ [ 194 ] = { 199, 11, 231, 299, 0, 0 },
+ [ 195 ] = { 139, 197, 146, 19, 0, 0 },
+ [ 196 ] = { 353, 363, 138, 345, 0, 0 },
+ [ 197 ] = { 354, 364, 138, 346, 0, 0 }
+};
+
+static const pmg_power_group_t power6_groups[] = {
[ 0 ] = {
.pmg_name = "pm_utilization",
.pmg_desc = "CPI and utilization data",
- .pmg_event_ids = { 302, 148, 139, 12, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[0],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000000a02121eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6672,7 +9093,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 1 ] = {
.pmg_name = "pm_utilization_capacity",
.pmg_desc = "CPU utilization and capacity",
- .pmg_event_ids = { 315, 11, 306, 347, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[1],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00000000fa1ef4f4ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6680,7 +9101,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 2 ] = {
.pmg_name = "pm_branch",
.pmg_desc = "Branch operations",
- .pmg_event_ids = { 10, 4, 6, 5, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[2],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x04000000a2a8808aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6688,7 +9109,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 3 ] = {
.pmg_name = "pm_branch2",
.pmg_desc = "Branch operations",
- .pmg_event_ids = { 9, 9, 2, 7, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[3],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x04000000a4a68e8cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6696,7 +9117,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 4 ] = {
.pmg_name = "pm_branch3",
.pmg_desc = "Branch operations",
- .pmg_event_ids = { 8, 8, 7, 11, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[4],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x04000000a0a28486ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6704,7 +9125,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 5 ] = {
.pmg_name = "pm_branch4",
.pmg_desc = "Branch operations",
- .pmg_event_ids = { 6, 3, 5, 4, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[5],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x04000000a8aa8c8eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6712,7 +9133,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 6 ] = {
.pmg_name = "pm_branch5",
.pmg_desc = "Branch operations",
- .pmg_event_ids = { 8, 10, 1, 3, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[6],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x04040000a052c652ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6720,7 +9141,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 7 ] = {
.pmg_name = "pm_dsource",
.pmg_desc = "Data source",
- .pmg_event_ids = { 13, 15, 13, 19, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[7],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000058585656ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6728,7 +9149,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 8 ] = {
.pmg_name = "pm_dsource2",
.pmg_desc = "Data sources",
- .pmg_event_ids = { 14, 19, 14, 19, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[8],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000005a5a5856ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6736,7 +9157,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 9 ] = {
.pmg_name = "pm_dsource3",
.pmg_desc = "Data sources",
- .pmg_event_ids = { 14, 19, 12, 16, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[9],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000005a5a5a5aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6744,7 +9165,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 10 ] = {
.pmg_name = "pm_dsource4",
.pmg_desc = "Data sources",
- .pmg_event_ids = { 16, 23, 11, 13, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[10],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000005c5c5c5cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6752,7 +9173,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 11 ] = {
.pmg_name = "pm_dsource5",
.pmg_desc = "Data sources",
- .pmg_event_ids = { 15, 13, 16, 20, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[11],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000005e5e5e5eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6760,7 +9181,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 12 ] = {
.pmg_name = "pm_dlatencies",
.pmg_desc = "Data latencies",
- .pmg_event_ids = { 200, 24, 10, 17, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[12],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000000c281e24ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6768,7 +9189,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 13 ] = {
.pmg_name = "pm_dlatencies2",
.pmg_desc = "Data latencies",
- .pmg_event_ids = { 139, 22, 10, 14, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[13],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00000000022c1e2aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6776,7 +9197,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 14 ] = {
.pmg_name = "pm_dlatencies3",
.pmg_desc = "Data latencies",
- .pmg_event_ids = { 139, 14, 16, 23, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[14],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00000000022e5e2cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6784,7 +9205,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 15 ] = {
.pmg_name = "pm_dlatencies4",
.pmg_desc = "Data latencies",
- .pmg_event_ids = { 14, 12, 11, 18, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[15],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000005a2a5c26ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6792,7 +9213,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 16 ] = {
.pmg_name = "pm_dlatencies5",
.pmg_desc = "Data latencies",
- .pmg_event_ids = { 16, 21, 14, 22, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[16],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000005c225828ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6800,7 +9221,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 17 ] = {
.pmg_name = "pm_dlatencies6",
.pmg_desc = "Data latencies",
- .pmg_event_ids = { 15, 16, 12, 21, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[17],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000005e245a2eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6808,7 +9229,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 18 ] = {
.pmg_name = "pm_dlatencies7",
.pmg_desc = "Data latencies",
- .pmg_event_ids = { 13, 18, 139, 160, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[18],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000005820120eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6816,7 +9237,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 19 ] = {
.pmg_name = "pm_dlatencies8",
.pmg_desc = "Data latencies",
- .pmg_event_ids = { 67, 15, 10, 15, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[19],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000010581e20ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6824,7 +9245,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 20 ] = {
.pmg_name = "pm_dlatencies9",
.pmg_desc = "Data latencies",
- .pmg_event_ids = { 2, 22, 139, 20, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[20],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00000000122c125eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6832,7 +9253,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 21 ] = {
.pmg_name = "pm_dlatencies10",
.pmg_desc = "Data latencies",
- .pmg_event_ids = { 14, 20, 10, 18, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[21],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000005a261e26ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6840,7 +9261,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 22 ] = {
.pmg_name = "pm_isource",
.pmg_desc = "Instruction sources",
- .pmg_event_ids = { 143, 154, 144, 151, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[22],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0040000040404654ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6848,7 +9269,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 23 ] = {
.pmg_name = "pm_isource2",
.pmg_desc = "Instruction sources",
- .pmg_event_ids = { 144, 155, 145, 150, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[23],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0040000046464046ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6856,7 +9277,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 24 ] = {
.pmg_name = "pm_isource3",
.pmg_desc = "Instruction sources",
- .pmg_event_ids = { 146, 156, 142, 148, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[24],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0040000044444444ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6864,7 +9285,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 25 ] = {
.pmg_name = "pm_isource4",
.pmg_desc = "Instruction sources",
- .pmg_event_ids = { 145, 152, 147, 152, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[25],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0040000042424242ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6872,7 +9293,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 26 ] = {
.pmg_name = "pm_isource5",
.pmg_desc = "Instruction sources",
- .pmg_event_ids = { 143, 154, 146, 151, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[26],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0040000040405454ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6880,7 +9301,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 27 ] = {
.pmg_name = "pm_pteg",
.pmg_desc = "PTEG sources",
- .pmg_event_ids = { 295, 305, 291, 290, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[27],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0001000048484e4eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6888,7 +9309,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 28 ] = {
.pmg_name = "pm_pteg2",
.pmg_desc = "PTEG sources",
- .pmg_event_ids = { 296, 305, 292, 289, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[28],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000100002848484cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6896,7 +9317,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 29 ] = {
.pmg_name = "pm_pteg3",
.pmg_desc = "PTEG sources",
- .pmg_event_ids = { 297, 306, 293, 291, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[29],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000100004e4e284aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6904,7 +9325,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 30 ] = {
.pmg_name = "pm_pteg4",
.pmg_desc = "PTEG sources",
- .pmg_event_ids = { 298, 304, 294, 291, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[30],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000100004a4a4a4aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6912,7 +9333,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 31 ] = {
.pmg_name = "pm_pteg5",
.pmg_desc = "PTEG sources",
- .pmg_event_ids = { 299, 307, 290, 292, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[31],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000100004c4c4cc8ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6920,7 +9341,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 32 ] = {
.pmg_name = "pm_data_tablewalk",
.pmg_desc = "Data tablewalks",
- .pmg_event_ids = { 17, 26, 19, 312, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[32],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x09900000a0a284e8ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6928,7 +9349,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 33 ] = {
.pmg_name = "pm_inst_tablewalk",
.pmg_desc = "Instruction tablewalks",
- .pmg_event_ids = { 148, 158, 150, 157, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[33],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x09900000a8aa8ceaULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6936,7 +9357,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 34 ] = {
.pmg_name = "pm_freq",
.pmg_desc = "Frequency events",
- .pmg_event_ids = { 52, 55, 115, 123, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[34],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000002a3c3c3cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6944,7 +9365,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 35 ] = {
.pmg_name = "pm_disp_wait",
.pmg_desc = "Dispatch stalls",
- .pmg_event_ids = { 154, 64, 54, 62, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[35],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00000000560c040cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6952,7 +9373,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 36 ] = {
.pmg_name = "pm_disp_held",
.pmg_desc = "Dispatch held conditions",
- .pmg_event_ids = { 52, 55, 305, 56, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[36],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x200000002a3c2aa2ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6960,7 +9381,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 37 ] = {
.pmg_name = "pm_disp_held2",
.pmg_desc = "Dispatch held conditions",
- .pmg_event_ids = { 39, 38, 32, 41, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[37],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x200000008004a4a6ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6968,7 +9389,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 38 ] = {
.pmg_name = "pm_disp_held3",
.pmg_desc = "Dispatch held conditions",
- .pmg_event_ids = { 54, 49, 50, 55, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[38],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x20000000888aacaeULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6976,7 +9397,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 39 ] = {
.pmg_name = "pm_disp_held4",
.pmg_desc = "Dispatch held conditions",
- .pmg_event_ids = { 35, 52, 41, 44, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[39],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x02000000a0a28486ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6984,7 +9405,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 40 ] = {
.pmg_name = "pm_disp_held5",
.pmg_desc = "Dispatch held conditions",
- .pmg_event_ids = { 36, 54, 30, 46, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[40],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x22000000a8aa8ca0ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -6992,7 +9413,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 41 ] = {
.pmg_name = "pm_disp_held6",
.pmg_desc = "Dispatch held conditions",
- .pmg_event_ids = { 40, 63, 42, 54, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[41],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x33000000a882a4a6ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7000,7 +9421,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 42 ] = {
.pmg_name = "pm_disp_held7",
.pmg_desc = "Dispatch held conditions",
- .pmg_event_ids = { 38, 61, 49, 39, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[42],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x30000000888aacaeULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7008,7 +9429,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 43 ] = {
.pmg_name = "pm_disp_held8",
.pmg_desc = "Dispatch held conditions",
- .pmg_event_ids = { 41, 60, 47, 42, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[43],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x220000008a8cae80ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7016,7 +9437,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 44 ] = {
.pmg_name = "pm_disp_held9",
.pmg_desc = "Dispatch held conditions",
- .pmg_event_ids = { 41, 43, 45, 38, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[44],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x220000008aa08a8cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7024,7 +9445,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 45 ] = {
.pmg_name = "pm_sync",
.pmg_desc = "Sync events",
- .pmg_event_ids = { 247, 11, 303, 52, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[45],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x38900000ae1eeca0ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7032,7 +9453,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 46 ] = {
.pmg_name = "pm_L1_ref",
.pmg_desc = "L1 references",
- .pmg_event_ids = { 202, 212, 300, 301, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[46],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x80000000368aa63aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7040,7 +9461,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 47 ] = {
.pmg_name = "pm_L1_ldst",
.pmg_desc = "L1 load/store ref/miss",
- .pmg_event_ids = { 310, 212, 299, 202, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[47],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x800000003230a8a0ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7048,7 +9469,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 48 ] = {
.pmg_name = "pm_streams",
.pmg_desc = "Streams",
- .pmg_event_ids = { 21, 29, 155, 136, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[48],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x48000000a0a284a4ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7056,7 +9477,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 49 ] = {
.pmg_name = "pm_flush",
.pmg_desc = "Flushes",
- .pmg_event_ids = { 67, 77, 67, 76, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[49],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0022000010cacccaULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7064,7 +9485,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 50 ] = {
.pmg_name = "pm_prefetch",
.pmg_desc = "I cache Prefetches",
- .pmg_event_ids = { 136, 142, 134, 140, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[50],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x400400008a8caec0ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7072,7 +9493,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 51 ] = {
.pmg_name = "pm_stcx",
.pmg_desc = "STCX",
- .pmg_event_ids = { 304, 311, 298, 200, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[51],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00080000e6eccecaULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7080,7 +9501,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 52 ] = {
.pmg_name = "pm_larx",
.pmg_desc = "LARX",
- .pmg_event_ids = { 197, 208, 296, 297, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[52],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00080000eae2c6ceULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7088,7 +9509,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 53 ] = {
.pmg_name = "pm_thread_cyc",
.pmg_desc = "Thread cycles",
- .pmg_event_ids = { 315, 320, 306, 304, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[53],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000016182604ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7096,7 +9517,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 54 ] = {
.pmg_name = "pm_misc",
.pmg_desc = "Misc",
- .pmg_event_ids = { 1, 137, 313, 306, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[54],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000004161808ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7104,7 +9525,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 55 ] = {
.pmg_name = "pm_misc2",
.pmg_desc = "Misc",
- .pmg_event_ids = { 57, 67, 304, 0, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[55],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x40020000eef8f8a0ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7112,7 +9533,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 56 ] = {
.pmg_name = "pm_misc3",
.pmg_desc = "Misc",
- .pmg_event_ids = { 307, 321, 10, 145, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[56],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0300000054a01e02ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7120,7 +9541,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 57 ] = {
.pmg_name = "pm_tlb_slb",
.pmg_desc = "TLB and SLB events",
- .pmg_event_ids = { 152, 65, 314, 159, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[57],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00980000e0e8e8e2ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7128,7 +9549,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 58 ] = {
.pmg_name = "pm_slb_miss",
.pmg_desc = "SLB Misses",
- .pmg_event_ids = { 152, 65, 136, 294, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[58],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00480001e0e8ee32ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7136,7 +9557,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 59 ] = {
.pmg_name = "pm_rejects",
.pmg_desc = "Reject events",
- .pmg_event_ids = { 239, 249, 236, 238, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[59],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xaa00000034303e30ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7144,7 +9565,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 60 ] = {
.pmg_name = "pm_rejects2",
.pmg_desc = "Reject events",
- .pmg_event_ids = { 240, 250, 235, 243, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[60],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x9a000000323830acULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7152,7 +9573,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 61 ] = {
.pmg_name = "pm_rejects3",
.pmg_desc = "Reject events",
- .pmg_event_ids = { 243, 253, 237, 242, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[61],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xaa000000303e3234ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7160,7 +9581,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 62 ] = {
.pmg_name = "pm_rejects4",
.pmg_desc = "Unaligned store rejects",
- .pmg_event_ids = { 245, 256, 214, 232, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[62],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x900000003630a2aaULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7168,7 +9589,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 63 ] = {
.pmg_name = "pm_rejects5",
.pmg_desc = "Unaligned load rejects",
- .pmg_event_ids = { 244, 255, 213, 231, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[63],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x900000003036a0a8ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7176,7 +9597,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 64 ] = {
.pmg_name = "pm_rejects6",
.pmg_desc = "Set mispredictions rejects",
- .pmg_event_ids = { 216, 238, 238, 244, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[64],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xa0000000848c341cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7184,7 +9605,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 65 ] = {
.pmg_name = "pm_rejects_unit",
.pmg_desc = "Unaligned reject events by unit",
- .pmg_event_ids = { 218, 241, 214, 231, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[65],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x90000000808aa2a8ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7192,7 +9613,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 66 ] = {
.pmg_name = "pm_rejects_unit2",
.pmg_desc = "Reject events by unit",
- .pmg_event_ids = { 208, 218, 217, 227, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[66],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xaa000000a6828e8aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7200,7 +9621,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 67 ] = {
.pmg_name = "pm_rejects_unit3",
.pmg_desc = "Reject events by unit",
- .pmg_event_ids = { 210, 221, 219, 225, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[67],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0a000000a4a08c88ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7208,7 +9629,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 68 ] = {
.pmg_name = "pm_rejects_unit4",
.pmg_desc = "Reject events by unit",
- .pmg_event_ids = { 214, 224, 222, 228, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[68],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xaa000000a2868aaeULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7216,7 +9637,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 69 ] = {
.pmg_name = "pm_rejects_unit5",
.pmg_desc = "Reject events by unit",
- .pmg_event_ids = { 213, 213, 221, 220, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[69],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x9900000086a6ae8eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7224,7 +9645,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 70 ] = {
.pmg_name = "pm_rejects_unit6",
.pmg_desc = "Reject events by unit",
- .pmg_event_ids = { 217, 217, 225, 222, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[70],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xaa00000080a6a88eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7232,7 +9653,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 71 ] = {
.pmg_name = "pm_rejects_unit7",
.pmg_desc = "Reject events by unit",
- .pmg_event_ids = { 209, 213, 218, 220, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[71],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xa900000082a6aa8eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7240,7 +9661,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 72 ] = {
.pmg_name = "pm_ldf",
.pmg_desc = "Floating Point loads",
- .pmg_event_ids = { 237, 246, 200, 221, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[72],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x800000003832a4acULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7248,7 +9669,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 73 ] = {
.pmg_name = "pm_lsu_misc",
.pmg_desc = "LSU events",
- .pmg_event_ids = { 206, 216, 240, 233, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[73],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x08800000caccee8aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7256,7 +9677,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 74 ] = {
.pmg_name = "pm_lsu_lmq",
.pmg_desc = "LSU LMQ events",
- .pmg_event_ids = { 238, 248, 234, 211, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[74],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x98000000ac1c1ca4ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7264,7 +9685,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 75 ] = {
.pmg_name = "pm_lsu_flush_derat_miss",
.pmg_desc = "LSU flush and DERAT misses",
- .pmg_event_ids = { 234, 243, 229, 236, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[75],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00200000fc0eeceeULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7272,7 +9693,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 76 ] = {
.pmg_name = "pm_lla",
.pmg_desc = "Look Load Ahead events",
- .pmg_event_ids = { 140, 51, 139, 306, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[76],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x33000000a2841208ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7280,7 +9701,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 77 ] = {
.pmg_name = "pm_gct",
.pmg_desc = "GCT events",
- .pmg_event_ids = { 121, 127, 119, 147, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[77],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x404000000808a6e8ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7288,7 +9709,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 78 ] = {
.pmg_name = "pm_smt_priorities",
.pmg_desc = "Thread priority events",
- .pmg_event_ids = { 316, 322, 308, 307, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[78],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0020000040404040ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7296,7 +9717,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 79 ] = {
.pmg_name = "pm_smt_priorities2",
.pmg_desc = "Thread priority events",
- .pmg_event_ids = { 317, 323, 309, 308, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[79],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0020000046464646ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7304,7 +9725,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 80 ] = {
.pmg_name = "pm_smt_priorities3",
.pmg_desc = "Thread priority differences events",
- .pmg_event_ids = { 318, 324, 310, 309, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[80],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0002000040404040ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7312,7 +9733,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 81 ] = {
.pmg_name = "pm_smt_priorities4",
.pmg_desc = "Thread priority differences events",
- .pmg_event_ids = { 319, 325, 311, 310, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[81],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x03020000a6464646ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7320,7 +9741,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 82 ] = {
.pmg_name = "pm_fxu",
.pmg_desc = "FXU events",
- .pmg_event_ids = { 117, 125, 116, 124, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[82],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000050505050ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7328,7 +9749,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 83 ] = {
.pmg_name = "pm_fxu2",
.pmg_desc = "FXU events",
- .pmg_event_ids = { 118, 147, 117, 125, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[83],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x02040000aee41616ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7336,7 +9757,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 84 ] = {
.pmg_name = "pm_vmx",
.pmg_desc = "VMX events",
- .pmg_event_ids = { 329, 337, 329, 324, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[84],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x700000008480a2a6ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7344,7 +9765,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 85 ] = {
.pmg_name = "pm_vmx2",
.pmg_desc = "VMX events",
- .pmg_event_ids = { 321, 332, 316, 318, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[85],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x600000008088a2aaULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7352,7 +9773,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 86 ] = {
.pmg_name = "pm_vmx3",
.pmg_desc = "VMX events",
- .pmg_event_ids = { 322, 330, 320, 319, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[86],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x600000008284aaacULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7360,7 +9781,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 87 ] = {
.pmg_name = "pm_vmx4",
.pmg_desc = "VMX events",
- .pmg_event_ids = { 331, 340, 328, 328, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[87],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xb0000000828ea6a0ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7368,7 +9789,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 88 ] = {
.pmg_name = "pm_vmx5",
.pmg_desc = "VMX events",
- .pmg_event_ids = { 336, 331, 322, 323, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[88],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xb00000008084aca2ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7376,7 +9797,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 89 ] = {
.pmg_name = "pm_dfu",
.pmg_desc = "DFU events",
- .pmg_event_ids = { 23, 31, 24, 33, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[89],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xe00000008c88a2aeULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7384,7 +9805,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 90 ] = {
.pmg_name = "pm_dfu2",
.pmg_desc = "DFU events",
- .pmg_event_ids = { 27, 35, 28, 37, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[90],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xe00000008a84a0a6ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7392,7 +9813,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 91 ] = {
.pmg_name = "pm_fab",
.pmg_desc = "Fabric events",
- .pmg_event_ids = { 59, 69, 59, 67, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[91],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x500020003030a4acULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7400,7 +9821,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 92 ] = {
.pmg_name = "pm_fab2",
.pmg_desc = "Fabric events",
- .pmg_event_ids = { 63, 74, 64, 72, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[92],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x50002000888aa2a0ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7408,7 +9829,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 93 ] = {
.pmg_name = "pm_fab3",
.pmg_desc = "Fabric events",
- .pmg_event_ids = { 59, 69, 58, 68, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[93],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x500020003030aea6ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7416,7 +9837,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 94 ] = {
.pmg_name = "pm_mem_dblpump",
.pmg_desc = "Double pump",
- .pmg_event_ids = { 257, 268, 250, 255, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[94],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x5000400030303434ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7424,7 +9845,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 95 ] = {
.pmg_name = "pm_mem0_dblpump",
.pmg_desc = "MCS0 Double pump",
- .pmg_event_ids = { 250, 262, 242, 248, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[95],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x500040008082a4a6ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7432,7 +9853,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 96 ] = {
.pmg_name = "pm_mem1_dblpump",
.pmg_desc = "MCS1 Double pump",
- .pmg_event_ids = { 254, 266, 246, 252, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[96],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x50004000888aacaeULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7440,7 +9861,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 97 ] = {
.pmg_name = "pm_gxo",
.pmg_desc = "GX outbound",
- .pmg_event_ids = { 126, 132, 125, 129, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[97],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x500060008082a4a6ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7448,7 +9869,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 98 ] = {
.pmg_name = "pm_gxi",
.pmg_desc = "GX inbound",
- .pmg_event_ids = { 123, 129, 122, 132, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[98],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x500060008688aaa0ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7456,7 +9877,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 99 ] = {
.pmg_name = "pm_gx_dma",
.pmg_desc = "DMA events",
- .pmg_event_ids = { 126, 130, 126, 135, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[99],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x500060008086acaeULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7464,7 +9885,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 100 ] = {
.pmg_name = "pm_L1_misc",
.pmg_desc = "L1 misc events",
- .pmg_event_ids = { 142, 165, 285, 153, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[100],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x4004000082e2a80aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7472,7 +9893,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 101 ] = {
.pmg_name = "pm_L2_data",
.pmg_desc = "L2 load and store data",
- .pmg_event_ids = { 186, 195, 188, 193, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[101],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x5000800030303434ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7480,7 +9901,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 102 ] = {
.pmg_name = "pm_L2_ld_inst",
.pmg_desc = "L2 Load instructions",
- .pmg_event_ids = { 187, 196, 185, 191, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[102],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x5800a00030303486ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7488,7 +9909,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 103 ] = {
.pmg_name = "pm_L2_castout_invalidate",
.pmg_desc = "L2 castout and invalidate events",
- .pmg_event_ids = { 185, 194, 131, 27, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[103],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x5000c00030303434ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7496,7 +9917,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 104 ] = {
.pmg_name = "pm_L2_ldst_reqhit",
.pmg_desc = "L2 load and store requests and hits",
- .pmg_event_ids = { 203, 209, 301, 298, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[104],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x5000e00030303434ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7504,7 +9925,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 105 ] = {
.pmg_name = "pm_L2_ld_data_slice",
.pmg_desc = "L2 data loads by slice",
- .pmg_event_ids = { 165, 171, 179, 182, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[105],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x500080008082a8aaULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7512,7 +9933,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 106 ] = {
.pmg_name = "pm_L2_ld_inst_slice",
.pmg_desc = "L2 instruction loads by slice",
- .pmg_event_ids = { 166, 172, 180, 183, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[106],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x5000a0008082a8aaULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7520,7 +9941,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 107 ] = {
.pmg_name = "pm_L2_st_slice",
.pmg_desc = "L2 slice stores by slice",
- .pmg_event_ids = { 170, 178, 184, 189, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[107],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x500080008486acaeULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7528,7 +9949,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 108 ] = {
.pmg_name = "pm_L2miss_slice",
.pmg_desc = "L2 misses by slice",
- .pmg_event_ids = { 167, 197, 13, 187, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[108],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x5000a000843256acULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7536,7 +9957,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 109 ] = {
.pmg_name = "pm_L2_castout_slice",
.pmg_desc = "L2 castouts by slice",
- .pmg_event_ids = { 157, 167, 171, 178, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[109],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x5000c0008082a8aaULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7544,7 +9965,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 110 ] = {
.pmg_name = "pm_L2_invalidate_slice",
.pmg_desc = "L2 invalidate by slice",
- .pmg_event_ids = { 160, 168, 174, 179, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[110],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x5000c0008486acaeULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7552,7 +9973,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 111 ] = {
.pmg_name = "pm_L2_ld_reqhit_slice",
.pmg_desc = "L2 load requests and hist by slice",
- .pmg_event_ids = { 164, 170, 178, 181, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[111],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x5000e0008082a8aaULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7560,7 +9981,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 112 ] = {
.pmg_name = "pm_L2_st_reqhit_slice",
.pmg_desc = "L2 store requests and hist by slice",
- .pmg_event_ids = { 170, 177, 184, 188, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[112],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x5000e0008486acaeULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7568,7 +9989,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 113 ] = {
.pmg_name = "pm_L2_redir_pref",
.pmg_desc = "L2 redirect and prefetch",
- .pmg_event_ids = { 131, 140, 187, 191, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[113],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x08400000cacc8886ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7576,7 +9997,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 114 ] = {
.pmg_name = "pm_L3_SliceA",
.pmg_desc = "L3 slice A events",
- .pmg_event_ids = { 193, 201, 14, 195, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[114],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x50000000303058a4ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7584,7 +10005,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 115 ] = {
.pmg_name = "pm_L3_SliceB",
.pmg_desc = "L3 slice B events",
- .pmg_event_ids = { 196, 204, 14, 198, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[115],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x50000000888a58acULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7592,7 +10013,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 116 ] = {
.pmg_name = "pm_fpu_issue",
.pmg_desc = "FPU issue events",
- .pmg_event_ids = { 107, 116, 105, 120, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[116],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00300000c6c8eae4ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7600,7 +10021,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 117 ] = {
.pmg_name = "pm_fpu_issue2",
.pmg_desc = "FPU issue events",
- .pmg_event_ids = { 111, 124, 106, 118, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[117],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00300000c0c2eceeULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7608,7 +10029,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 118 ] = {
.pmg_name = "pm_fpu_issue3",
.pmg_desc = "FPU issue events",
- .pmg_event_ids = { 114, 120, 106, 118, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[118],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00330000e0e2eceeULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7616,7 +10037,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 119 ] = {
.pmg_name = "pm_fpu0_flop",
.pmg_desc = "FPU0 flop events",
- .pmg_event_ids = { 71, 86, 78, 90, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[119],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xcc0000008082a484ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7624,7 +10045,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 120 ] = {
.pmg_name = "pm_fpu0_misc",
.pmg_desc = "FPU0 events",
- .pmg_event_ids = { 76, 90, 70, 89, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[120],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xcc00000086a08286ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7632,7 +10053,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 121 ] = {
.pmg_name = "pm_fpu0_misc2",
.pmg_desc = "FPU0 events",
- .pmg_event_ids = { 75, 83, 76, 88, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[121],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xdd00000080a6a4a6ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7640,7 +10061,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 122 ] = {
.pmg_name = "pm_fpu0_misc3",
.pmg_desc = "FPU0 events",
- .pmg_event_ids = { 73, 88, 83, 80, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[122],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0d000000a0a28486ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7648,7 +10069,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 123 ] = {
.pmg_name = "pm_fpu1_flop",
.pmg_desc = "FPU1 flop events",
- .pmg_event_ids = { 86, 101, 93, 105, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[123],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xcc000000888aac8cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7656,7 +10077,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 124 ] = {
.pmg_name = "pm_fpu1_misc",
.pmg_desc = "FPU1 events",
- .pmg_event_ids = { 91, 105, 85, 104, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[124],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xcc0000008ea88a8eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7664,7 +10085,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 125 ] = {
.pmg_name = "pm_fpu1_misc2",
.pmg_desc = "FPU1 events",
- .pmg_event_ids = { 90, 98, 91, 103, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[125],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xdd00000088aeacaeULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7672,7 +10093,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 126 ] = {
.pmg_name = "pm_fpu1_misc3",
.pmg_desc = "FPU1 events",
- .pmg_event_ids = { 88, 103, 98, 95, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[126],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0d000000a8aa8c8eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7680,7 +10101,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 127 ] = {
.pmg_name = "pm_fpu_flop",
.pmg_desc = "FPU flop events",
- .pmg_event_ids = { 101, 111, 102, 109, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[127],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xc000000030303434ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7688,7 +10109,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 128 ] = {
.pmg_name = "pm_fpu_misc",
.pmg_desc = "FPU events",
- .pmg_event_ids = { 103, 113, 100, 111, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[128],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xdd00000030343434ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7696,7 +10117,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 129 ] = {
.pmg_name = "pm_fpu_misc2",
.pmg_desc = "FPU events",
- .pmg_event_ids = { 105, 110, 113, 122, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[129],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0c00000034343030ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7704,7 +10125,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 130 ] = {
.pmg_name = "pm_fpu_misc3",
.pmg_desc = "FPU events",
- .pmg_event_ids = { 102, 113, 114, 108, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[130],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0d00000034343030ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7712,7 +10133,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 131 ] = {
.pmg_name = "pm_purr",
.pmg_desc = "PURR events",
- .pmg_event_ids = { 301, 309, 10, 145, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[131],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000000ef41e02ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7720,7 +10141,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 132 ] = {
.pmg_name = "pm_suspend",
.pmg_desc = "SUSPENDED events",
- .pmg_event_ids = { 311, 11, 303, 145, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[132],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00900000001eec02ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7728,7 +10149,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 133 ] = {
.pmg_name = "pm_dcache",
.pmg_desc = "D cache",
- .pmg_event_ids = { 200, 243, 197, 234, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[133],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000000c0e0c06ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7736,7 +10157,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 134 ] = {
.pmg_name = "pm_derat_miss",
.pmg_desc = "DERAT miss",
- .pmg_event_ids = { 351, 361, 343, 343, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[134],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0090000f40404040ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7744,7 +10165,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 135 ] = {
.pmg_name = "pm_derat_ref",
.pmg_desc = "DERAT ref",
- .pmg_event_ids = { 350, 360, 342, 342, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[135],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0080000f40404040ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7752,7 +10173,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 136 ] = {
.pmg_name = "pm_ierat_miss",
.pmg_desc = "IERAT miss",
- .pmg_event_ids = { 352, 362, 344, 344, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[136],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0090000f46464646ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -7760,7 +10181,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 137 ] = {
.pmg_name = "pm_mrk_br",
.pmg_desc = "Marked Branch events",
- .pmg_event_ids = { 258, 280, 251, 145, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[137],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000052565202ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7768,7 +10189,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 138 ] = {
.pmg_name = "pm_mrk_dsource",
.pmg_desc = "Marked data sources",
- .pmg_event_ids = { 139, 269, 252, 256, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[138],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00000000024a4c4cULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7776,7 +10197,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 139 ] = {
.pmg_name = "pm_mrk_dsource2",
.pmg_desc = "Marked data sources",
- .pmg_event_ids = { 259, 270, 253, 145, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[139],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000048484e02ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7784,7 +10205,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 140 ] = {
.pmg_name = "pm_mrk_dsource3",
.pmg_desc = "Marked data sources",
- .pmg_event_ids = { 260, 148, 254, 257, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[140],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000002802484eULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7792,7 +10213,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 141 ] = {
.pmg_name = "pm_mrk_dsource4",
.pmg_desc = "Marked data sources",
- .pmg_event_ids = { 261, 271, 255, 145, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[141],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000004e4e2802ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7800,7 +10221,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 142 ] = {
.pmg_name = "pm_mrk_dsource5",
.pmg_desc = "Marked data sources",
- .pmg_event_ids = { 262, 272, 138, 258, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[142],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000004a4c024aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7808,7 +10229,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 143 ] = {
.pmg_name = "pm_mrk_dsource6",
.pmg_desc = "Marked data sources",
- .pmg_event_ids = { 263, 272, 256, 145, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[143],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000004c4c4a02ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7816,7 +10237,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 144 ] = {
.pmg_name = "pm_mrk_rejects",
.pmg_desc = "Marked rejects",
- .pmg_event_ids = { 276, 288, 138, 273, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[144],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0009000d34340230ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7824,7 +10245,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 145 ] = {
.pmg_name = "pm_mrk_rejects2",
.pmg_desc = "Marked rejects LSU0",
- .pmg_event_ids = { 270, 283, 266, 145, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[145],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00090000e6e0c202ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7832,7 +10253,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 146 ] = {
.pmg_name = "pm_mrk_rejects3",
.pmg_desc = "Marked rejects LSU1",
- .pmg_event_ids = { 273, 286, 269, 145, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[146],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00090000eee8ca02ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7840,7 +10261,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 147 ] = {
.pmg_name = "pm_mrk_inst",
.pmg_desc = "Marked instruction events",
- .pmg_event_ids = { 268, 279, 262, 145, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[147],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000001c100a02ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7848,7 +10269,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 148 ] = {
.pmg_name = "pm_mrk_fpu_fin",
.pmg_desc = "Marked Floating Point instructions finished",
- .pmg_event_ids = { 265, 275, 261, 145, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[148],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xd0000000828a1a02ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7856,7 +10277,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 149 ] = {
.pmg_name = "pm_mrk_misc",
.pmg_desc = "Marked misc events",
- .pmg_event_ids = { 276, 277, 257, 145, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[149],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00090008341a0802ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7864,7 +10285,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 150 ] = {
.pmg_name = "pm_mrk_misc2",
.pmg_desc = "Marked misc events",
- .pmg_event_ids = { 281, 278, 138, 263, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[150],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00080000e40a023eULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7872,7 +10293,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 151 ] = {
.pmg_name = "pm_mrk_misc3",
.pmg_desc = "Marked misc events",
- .pmg_event_ids = { 289, 281, 138, 271, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[151],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xb009000088e40212ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7880,7 +10301,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 152 ] = {
.pmg_name = "pm_mrk_misc4",
.pmg_desc = "Marked misc events",
- .pmg_event_ids = { 12, 11, 138, 272, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[152],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000001e1e021aULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7888,7 +10309,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 153 ] = {
.pmg_name = "pm_mrk_st",
.pmg_desc = "Marked stores events",
- .pmg_event_ids = { 282, 294, 277, 145, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[153],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000006060602ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7896,7 +10317,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 154 ] = {
.pmg_name = "pm_mrk_pteg",
.pmg_desc = "Marked PTEG",
- .pmg_event_ids = { 277, 289, 271, 145, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[154],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0010000040424402ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7904,7 +10325,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 155 ] = {
.pmg_name = "pm_mrk_pteg2",
.pmg_desc = "Marked PTEG",
- .pmg_event_ids = { 139, 290, 272, 275, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[155],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0010000002404644ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7912,7 +10333,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 156 ] = {
.pmg_name = "pm_mrk_pteg3",
.pmg_desc = "Marked PTEG",
- .pmg_event_ids = { 278, 291, 138, 276, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[156],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0010000046460246ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7920,7 +10341,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 157 ] = {
.pmg_name = "pm_mrk_pteg4",
.pmg_desc = "Marked PTEG",
- .pmg_event_ids = { 279, 148, 273, 277, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[157],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0010000042024054ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7928,7 +10349,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 158 ] = {
.pmg_name = "pm_mrk_pteg5",
.pmg_desc = "Marked PTEG",
- .pmg_event_ids = { 280, 148, 274, 278, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[158],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0010000044025442ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7936,7 +10357,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 159 ] = {
.pmg_name = "pm_mrk_pteg6",
.pmg_desc = "Marked PTEG",
- .pmg_event_ids = { 12, 292, 275, 145, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[159],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x001000001e444202ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7944,7 +10365,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 160 ] = {
.pmg_name = "pm_mrk_vmx",
.pmg_desc = "Marked VMX",
- .pmg_event_ids = { 285, 298, 282, 145, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[160],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x700000008c88ae02ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7952,7 +10373,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 161 ] = {
.pmg_name = "pm_mrk_vmx2",
.pmg_desc = "Marked VMX",
- .pmg_event_ids = { 283, 296, 258, 145, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[161],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x60900000868ee002ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7960,7 +10381,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 162 ] = {
.pmg_name = "pm_mrk_vmx3",
.pmg_desc = "Marked VMX",
- .pmg_event_ids = { 288, 342, 10, 145, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[162],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x700000008a821e02ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7968,7 +10389,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 163 ] = {
.pmg_name = "pm_mrk_fp",
.pmg_desc = "Marked FP events",
- .pmg_event_ids = { 265, 276, 260, 145, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[163],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xd00000008230aa02ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7976,7 +10397,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 164 ] = {
.pmg_name = "pm_mrk_derat_ref",
.pmg_desc = "Marked DERAT ref",
- .pmg_event_ids = { 353, 363, 345, 145, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[164],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0080000044444402ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7984,7 +10405,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 165 ] = {
.pmg_name = "pm_mrk_derat_miss",
.pmg_desc = "Marked DERAT miss",
- .pmg_event_ids = { 354, 364, 346, 145, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[165],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0090000044444402ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -7992,7 +10413,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 166 ] = {
.pmg_name = "pm_dcache_edge",
.pmg_desc = "D cache - edge",
- .pmg_event_ids = { 199, 243, 197, 335, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[166],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000000d0e0c07ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8000,7 +10421,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 167 ] = {
.pmg_name = "pm_lsu_lmq_edge",
.pmg_desc = "LSU LMQ events - edge",
- .pmg_event_ids = { 238, 359, 341, 211, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[167],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x98000000ac1d1da4ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8008,7 +10429,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 168 ] = {
.pmg_name = "pm_gct_edge",
.pmg_desc = "GCT events - edge",
- .pmg_event_ids = { 349, 358, 333, 147, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[168],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x404000000909a7e8ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8016,7 +10437,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 169 ] = {
.pmg_name = "pm_freq_edge",
.pmg_desc = "Frequency events - edge",
- .pmg_event_ids = { 348, 356, 115, 123, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[169],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000002b3d3c3cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8024,7 +10445,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 170 ] = {
.pmg_name = "pm_disp_wait_edge",
.pmg_desc = "Dispatch stalls - edge",
- .pmg_event_ids = { 154, 357, 340, 340, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[170],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00000000560d050dULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8032,7 +10453,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 171 ] = {
.pmg_name = "pm_edge1",
.pmg_desc = "EDGE event group",
- .pmg_event_ids = { 199, 64, 339, 337, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[171],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000006300d0c1f1eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8040,7 +10461,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 172 ] = {
.pmg_name = "pm_edge2",
.pmg_desc = "EDGE event group",
- .pmg_event_ids = { 337, 0, 332, 136, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[172],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x400000008180a5a4ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8048,7 +10469,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 173 ] = {
.pmg_name = "pm_edge3",
.pmg_desc = "EDGE event group",
- .pmg_event_ids = { 343, 309, 335, 157, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[173],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x009000000bf4ebeaULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8056,7 +10477,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 174 ] = {
.pmg_name = "pm_edge4",
.pmg_desc = "EDGE event group",
- .pmg_event_ids = { 339, 128, 334, 287, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[174],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x400000008786a9a8ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8064,7 +10485,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 175 ] = {
.pmg_name = "pm_edge5",
.pmg_desc = "EDGE event group",
- .pmg_event_ids = { 344, 351, 336, 303, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[175],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00900000fb17edecULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8072,7 +10493,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 176 ] = {
.pmg_name = "pm_noedge5",
.pmg_desc = "EDGE event group",
- .pmg_event_ids = { 315, 137, 336, 303, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[176],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00900000fa16edecULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8080,7 +10501,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 177 ] = {
.pmg_name = "pm_edge6",
.pmg_desc = "EDGE event group",
- .pmg_event_ids = { 348, 355, 340, 340, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[177],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000002b05050dULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8088,7 +10509,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 178 ] = {
.pmg_name = "pm_noedge6",
.pmg_desc = "EDGE event group",
- .pmg_event_ids = { 52, 38, 54, 62, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[178],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000002a04040cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8096,7 +10517,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 179 ] = {
.pmg_name = "pm_edge7",
.pmg_desc = "EDGE event group",
- .pmg_event_ids = { 349, 358, 341, 341, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[179],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000009091d1dULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8104,7 +10525,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 180 ] = {
.pmg_name = "pm_noedge7",
.pmg_desc = "NOEDGE event group",
- .pmg_event_ids = { 121, 127, 234, 244, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[180],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000008081c1cULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8112,7 +10533,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 181 ] = {
.pmg_name = "pm_edge8",
.pmg_desc = "EDGE event group",
- .pmg_event_ids = { 342, 359, 303, 335, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[181],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00900000cd1dec07ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8120,7 +10541,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 182 ] = {
.pmg_name = "pm_noedge8",
.pmg_desc = "NOEDGE event group",
- .pmg_event_ids = { 312, 248, 336, 234, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[182],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00900000cc1ced06ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8128,7 +10549,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 183 ] = {
.pmg_name = "pm_edge9",
.pmg_desc = "EDGE event group",
- .pmg_event_ids = { 309, 357, 197, 203, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[183],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x80000000880d0ca2ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8136,7 +10557,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 184 ] = {
.pmg_name = "pm_edge10",
.pmg_desc = "EDGE event group",
- .pmg_event_ids = { 31, 356, 31, 336, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[184],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x32000000ac3dae05ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8144,7 +10565,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 185 ] = {
.pmg_name = "pm_noedge10",
.pmg_desc = "NOEDGE event group",
- .pmg_event_ids = { 31, 55, 31, 304, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[185],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x32000000ac3cae04ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8152,7 +10573,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 186 ] = {
.pmg_name = "pm_hpm1",
.pmg_desc = "HPM group",
- .pmg_event_ids = { 101, 111, 102, 12, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[186],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xc00000003030341eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8160,7 +10581,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 187 ] = {
.pmg_name = "pm_hpm2",
.pmg_desc = "HPM group",
- .pmg_event_ids = { 139, 246, 113, 12, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[187],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x8c0000000232301eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8168,7 +10589,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 188 ] = {
.pmg_name = "pm_hpm3",
.pmg_desc = "HPM group",
- .pmg_event_ids = { 12, 210, 299, 145, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[188],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x800000001e80f002ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8176,7 +10597,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 189 ] = {
.pmg_name = "pm_hpm4",
.pmg_desc = "HPM group",
- .pmg_event_ids = { 139, 149, 198, 300, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[189],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x800000000212a234ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8184,7 +10605,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 190 ] = {
.pmg_name = "pm_hpm5",
.pmg_desc = "HPM group",
- .pmg_event_ids = { 103, 11, 117, 125, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[190],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xd0000000301e1616ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8192,7 +10613,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 191 ] = {
.pmg_name = "pm_hpm6",
.pmg_desc = "HPM group",
- .pmg_event_ids = { 13, 15, 12, 16, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[191],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0000000058585a5aULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8200,7 +10621,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 192 ] = {
.pmg_name = "pm_hpm7",
.pmg_desc = "HPM group",
- .pmg_event_ids = { 14, 19, 14, 12, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[192],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000000005a5a581eULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8208,7 +10629,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 193 ] = {
.pmg_name = "pm_hpm8",
.pmg_desc = "HPM group",
- .pmg_event_ids = { 101, 111, 113, 202, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[193],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0xcc000000303030f0ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8216,7 +10637,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 194 ] = {
.pmg_name = "pm_hpm9",
.pmg_desc = "HPM group",
- .pmg_event_ids = { 199, 11, 231, 299, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[194],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x80000000801e34a8ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8224,7 +10645,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 195 ] = {
.pmg_name = "pm_hpm10",
.pmg_desc = "HPM group",
- .pmg_event_ids = { 139, 197, 146, 19, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[195],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x5040a00002325456ULL,
.pmg_mmcra = 0x0000000000000000ULL
@@ -8232,7 +10653,7 @@ static pmg_power6_group_t power6_groups[] = {
[ 196 ] = {
.pmg_name = "pm_mrk_derat_ref2",
.pmg_desc = "Marked DERAT ref",
- .pmg_event_ids = { 353, 363, 138, 345, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[196],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0080000044440244ULL,
.pmg_mmcra = 0x0000000000000001ULL
@@ -8240,11 +10661,12 @@ static pmg_power6_group_t power6_groups[] = {
[ 197 ] = {
.pmg_name = "pm_mrk_derat_miss2",
.pmg_desc = "Marked DERAT miss",
- .pmg_event_ids = { 354, 364, 138, 346, 0, 0 },
+ .pmg_event_ids = power6_group_event_ids[197],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x0090000044440244ULL,
.pmg_mmcra = 0x0000000000000001ULL
}
};
+
#endif
diff --git a/src/libpfm-3.y/lib/powerpc_reg.h b/src/libpfm-3.y/lib/powerpc_reg.h
index 76c94a4e8463911f4686832e9df80bc6d679a8a7..1c9f75741c49a32ed2e31e5ab3ba228ccdf0085f 100644
--- a/src/libpfm-3.y/lib/powerpc_reg.h
+++ b/src/libpfm-3.y/lib/powerpc_reg.h
@@ -77,6 +77,7 @@
#define PV_POWER5p 0x003B
#define PV_970FX 0x003C
#define PV_POWER6 0x003E
+#define PV_POWER7 0x003F
#define PV_630 0x0040
#define PV_630p 0x0041
#define PV_970MP 0x0044
diff --git a/src/libpfm-3.y/lib/ppc970_events.h b/src/libpfm-3.y/lib/ppc970_events.h
index e9ef7e316860d49d42073e071fb903ef7f3ccce3..bef169bbafd609f7963b15cec0eaa572e1731e1c 100644
--- a/src/libpfm-3.y/lib/ppc970_events.h
+++ b/src/libpfm-3.y/lib/ppc970_events.h
@@ -20,1950 +20,2863 @@
* hand.
*
*/
-static pme_ppc970_entry_t ppc970_pe[] = {
#define PPC970_PME_PM_LSU_REJECT_RELOAD_CDF 0
+#define PPC970_PME_PM_MRK_LSU_SRQ_INST_VALID 1
+#define PPC970_PME_PM_FPU1_SINGLE 2
+#define PPC970_PME_PM_FPU0_STALL3 3
+#define PPC970_PME_PM_TB_BIT_TRANS 4
+#define PPC970_PME_PM_GPR_MAP_FULL_CYC 5
+#define PPC970_PME_PM_MRK_ST_CMPL 6
+#define PPC970_PME_PM_FPU0_STF 7
+#define PPC970_PME_PM_FPU1_FMA 8
+#define PPC970_PME_PM_LSU1_FLUSH_ULD 9
+#define PPC970_PME_PM_MRK_INST_FIN 10
+#define PPC970_PME_PM_MRK_LSU0_FLUSH_UST 11
+#define PPC970_PME_PM_LSU_LRQ_S0_ALLOC 12
+#define PPC970_PME_PM_FPU_FDIV 13
+#define PPC970_PME_PM_FPU0_FULL_CYC 14
+#define PPC970_PME_PM_FPU_SINGLE 15
+#define PPC970_PME_PM_FPU0_FMA 16
+#define PPC970_PME_PM_MRK_LSU1_FLUSH_ULD 17
+#define PPC970_PME_PM_LSU1_FLUSH_LRQ 18
+#define PPC970_PME_PM_DTLB_MISS 19
+#define PPC970_PME_PM_MRK_ST_MISS_L1 20
+#define PPC970_PME_PM_EXT_INT 21
+#define PPC970_PME_PM_MRK_LSU1_FLUSH_LRQ 22
+#define PPC970_PME_PM_MRK_ST_GPS 23
+#define PPC970_PME_PM_GRP_DISP_SUCCESS 24
+#define PPC970_PME_PM_LSU1_LDF 25
+#define PPC970_PME_PM_LSU0_SRQ_STFWD 26
+#define PPC970_PME_PM_CR_MAP_FULL_CYC 27
+#define PPC970_PME_PM_MRK_LSU0_FLUSH_ULD 28
+#define PPC970_PME_PM_LSU_DERAT_MISS 29
+#define PPC970_PME_PM_FPU0_SINGLE 30
+#define PPC970_PME_PM_FPU1_FDIV 31
+#define PPC970_PME_PM_FPU1_FEST 32
+#define PPC970_PME_PM_FPU0_FRSP_FCONV 33
+#define PPC970_PME_PM_GCT_EMPTY_SRQ_FULL 34
+#define PPC970_PME_PM_MRK_ST_CMPL_INT 35
+#define PPC970_PME_PM_FLUSH_BR_MPRED 36
+#define PPC970_PME_PM_FXU_FIN 37
+#define PPC970_PME_PM_FPU_STF 38
+#define PPC970_PME_PM_DSLB_MISS 39
+#define PPC970_PME_PM_FXLS1_FULL_CYC 40
+#define PPC970_PME_PM_LSU_LMQ_LHR_MERGE 41
+#define PPC970_PME_PM_MRK_STCX_FAIL 42
+#define PPC970_PME_PM_FXU0_BUSY_FXU1_IDLE 43
+#define PPC970_PME_PM_MRK_DATA_FROM_L25_SHR 44
+#define PPC970_PME_PM_LSU_FLUSH_ULD 45
+#define PPC970_PME_PM_MRK_BRU_FIN 46
+#define PPC970_PME_PM_IERAT_XLATE_WR 47
+#define PPC970_PME_PM_DATA_FROM_MEM 48
+#define PPC970_PME_PM_FPR_MAP_FULL_CYC 49
+#define PPC970_PME_PM_FPU1_FULL_CYC 50
+#define PPC970_PME_PM_FPU0_FIN 51
+#define PPC970_PME_PM_GRP_BR_REDIR 52
+#define PPC970_PME_PM_THRESH_TIMEO 53
+#define PPC970_PME_PM_FPU_FSQRT 54
+#define PPC970_PME_PM_MRK_LSU0_FLUSH_LRQ 55
+#define PPC970_PME_PM_PMC1_OVERFLOW 56
+#define PPC970_PME_PM_FXLS0_FULL_CYC 57
+#define PPC970_PME_PM_FPU0_ALL 58
+#define PPC970_PME_PM_DATA_TABLEWALK_CYC 59
+#define PPC970_PME_PM_FPU0_FEST 60
+#define PPC970_PME_PM_DATA_FROM_L25_MOD 61
+#define PPC970_PME_PM_LSU0_REJECT_ERAT_MISS 62
+#define PPC970_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 63
+#define PPC970_PME_PM_LSU0_REJECT_RELOAD_CDF 64
+#define PPC970_PME_PM_FPU_FEST 65
+#define PPC970_PME_PM_0INST_FETCH 66
+#define PPC970_PME_PM_LD_MISS_L1_LSU0 67
+#define PPC970_PME_PM_LSU1_REJECT_RELOAD_CDF 68
+#define PPC970_PME_PM_L1_PREF 69
+#define PPC970_PME_PM_FPU1_STALL3 70
+#define PPC970_PME_PM_BRQ_FULL_CYC 71
+#define PPC970_PME_PM_PMC8_OVERFLOW 72
+#define PPC970_PME_PM_PMC7_OVERFLOW 73
+#define PPC970_PME_PM_WORK_HELD 74
+#define PPC970_PME_PM_MRK_LD_MISS_L1_LSU0 75
+#define PPC970_PME_PM_FXU_IDLE 76
+#define PPC970_PME_PM_INST_CMPL 77
+#define PPC970_PME_PM_LSU1_FLUSH_UST 78
+#define PPC970_PME_PM_LSU0_FLUSH_ULD 79
+#define PPC970_PME_PM_LSU_FLUSH 80
+#define PPC970_PME_PM_INST_FROM_L2 81
+#define PPC970_PME_PM_LSU1_REJECT_LMQ_FULL 82
+#define PPC970_PME_PM_PMC2_OVERFLOW 83
+#define PPC970_PME_PM_FPU0_DENORM 84
+#define PPC970_PME_PM_FPU1_FMOV_FEST 85
+#define PPC970_PME_PM_GRP_DISP_REJECT 86
+#define PPC970_PME_PM_LSU_LDF 87
+#define PPC970_PME_PM_INST_DISP 88
+#define PPC970_PME_PM_DATA_FROM_L25_SHR 89
+#define PPC970_PME_PM_L1_DCACHE_RELOAD_VALID 90
+#define PPC970_PME_PM_MRK_GRP_ISSUED 91
+#define PPC970_PME_PM_FPU_FMA 92
+#define PPC970_PME_PM_MRK_CRU_FIN 93
+#define PPC970_PME_PM_MRK_LSU1_FLUSH_UST 94
+#define PPC970_PME_PM_MRK_FXU_FIN 95
+#define PPC970_PME_PM_LSU1_REJECT_ERAT_MISS 96
+#define PPC970_PME_PM_BR_ISSUED 97
+#define PPC970_PME_PM_PMC4_OVERFLOW 98
+#define PPC970_PME_PM_EE_OFF 99
+#define PPC970_PME_PM_INST_FROM_L25_MOD 100
+#define PPC970_PME_PM_ITLB_MISS 101
+#define PPC970_PME_PM_FXU1_BUSY_FXU0_IDLE 102
+#define PPC970_PME_PM_GRP_DISP_VALID 103
+#define PPC970_PME_PM_MRK_GRP_DISP 104
+#define PPC970_PME_PM_LSU_FLUSH_UST 105
+#define PPC970_PME_PM_FXU1_FIN 106
+#define PPC970_PME_PM_GRP_CMPL 107
+#define PPC970_PME_PM_FPU_FRSP_FCONV 108
+#define PPC970_PME_PM_MRK_LSU0_FLUSH_SRQ 109
+#define PPC970_PME_PM_LSU_LMQ_FULL_CYC 110
+#define PPC970_PME_PM_ST_REF_L1_LSU0 111
+#define PPC970_PME_PM_LSU0_DERAT_MISS 112
+#define PPC970_PME_PM_LSU_SRQ_SYNC_CYC 113
+#define PPC970_PME_PM_FPU_STALL3 114
+#define PPC970_PME_PM_LSU_REJECT_ERAT_MISS 115
+#define PPC970_PME_PM_MRK_DATA_FROM_L2 116
+#define PPC970_PME_PM_LSU0_FLUSH_SRQ 117
+#define PPC970_PME_PM_FPU0_FMOV_FEST 118
+#define PPC970_PME_PM_LD_REF_L1_LSU0 119
+#define PPC970_PME_PM_LSU1_FLUSH_SRQ 120
+#define PPC970_PME_PM_GRP_BR_MPRED 121
+#define PPC970_PME_PM_LSU_LMQ_S0_ALLOC 122
+#define PPC970_PME_PM_LSU0_REJECT_LMQ_FULL 123
+#define PPC970_PME_PM_ST_REF_L1 124
+#define PPC970_PME_PM_MRK_VMX_FIN 125
+#define PPC970_PME_PM_LSU_SRQ_EMPTY_CYC 126
+#define PPC970_PME_PM_FPU1_STF 127
+#define PPC970_PME_PM_RUN_CYC 128
+#define PPC970_PME_PM_LSU_LMQ_S0_VALID 129
+#define PPC970_PME_PM_LSU0_LDF 130
+#define PPC970_PME_PM_LSU_LRQ_S0_VALID 131
+#define PPC970_PME_PM_PMC3_OVERFLOW 132
+#define PPC970_PME_PM_MRK_IMR_RELOAD 133
+#define PPC970_PME_PM_MRK_GRP_TIMEO 134
+#define PPC970_PME_PM_FPU_FMOV_FEST 135
+#define PPC970_PME_PM_GRP_DISP_BLK_SB_CYC 136
+#define PPC970_PME_PM_XER_MAP_FULL_CYC 137
+#define PPC970_PME_PM_ST_MISS_L1 138
+#define PPC970_PME_PM_STOP_COMPLETION 139
+#define PPC970_PME_PM_MRK_GRP_CMPL 140
+#define PPC970_PME_PM_ISLB_MISS 141
+#define PPC970_PME_PM_SUSPENDED 142
+#define PPC970_PME_PM_CYC 143
+#define PPC970_PME_PM_LD_MISS_L1_LSU1 144
+#define PPC970_PME_PM_STCX_FAIL 145
+#define PPC970_PME_PM_LSU1_SRQ_STFWD 146
+#define PPC970_PME_PM_GRP_DISP 147
+#define PPC970_PME_PM_L2_PREF 148
+#define PPC970_PME_PM_FPU1_DENORM 149
+#define PPC970_PME_PM_DATA_FROM_L2 150
+#define PPC970_PME_PM_FPU0_FPSCR 151
+#define PPC970_PME_PM_MRK_DATA_FROM_L25_MOD 152
+#define PPC970_PME_PM_FPU0_FSQRT 153
+#define PPC970_PME_PM_LD_REF_L1 154
+#define PPC970_PME_PM_MRK_L1_RELOAD_VALID 155
+#define PPC970_PME_PM_1PLUS_PPC_CMPL 156
+#define PPC970_PME_PM_INST_FROM_L1 157
+#define PPC970_PME_PM_EE_OFF_EXT_INT 158
+#define PPC970_PME_PM_PMC6_OVERFLOW 159
+#define PPC970_PME_PM_LSU_LRQ_FULL_CYC 160
+#define PPC970_PME_PM_IC_PREF_INSTALL 161
+#define PPC970_PME_PM_DC_PREF_OUT_OF_STREAMS 162
+#define PPC970_PME_PM_MRK_LSU1_FLUSH_SRQ 163
+#define PPC970_PME_PM_GCT_FULL_CYC 164
+#define PPC970_PME_PM_INST_FROM_MEM 165
+#define PPC970_PME_PM_FLUSH_LSU_BR_MPRED 166
+#define PPC970_PME_PM_FXU_BUSY 167
+#define PPC970_PME_PM_ST_REF_L1_LSU1 168
+#define PPC970_PME_PM_MRK_LD_MISS_L1 169
+#define PPC970_PME_PM_L1_WRITE_CYC 170
+#define PPC970_PME_PM_LSU_REJECT_LMQ_FULL 171
+#define PPC970_PME_PM_FPU_ALL 172
+#define PPC970_PME_PM_LSU_SRQ_S0_ALLOC 173
+#define PPC970_PME_PM_INST_FROM_L25_SHR 174
+#define PPC970_PME_PM_GRP_MRK 175
+#define PPC970_PME_PM_BR_MPRED_CR 176
+#define PPC970_PME_PM_DC_PREF_STREAM_ALLOC 177
+#define PPC970_PME_PM_FPU1_FIN 178
+#define PPC970_PME_PM_LSU_REJECT_SRQ 179
+#define PPC970_PME_PM_BR_MPRED_TA 180
+#define PPC970_PME_PM_CRQ_FULL_CYC 181
+#define PPC970_PME_PM_LD_MISS_L1 182
+#define PPC970_PME_PM_INST_FROM_PREF 183
+#define PPC970_PME_PM_STCX_PASS 184
+#define PPC970_PME_PM_DC_INV_L2 185
+#define PPC970_PME_PM_LSU_SRQ_FULL_CYC 186
+#define PPC970_PME_PM_LSU0_FLUSH_LRQ 187
+#define PPC970_PME_PM_LSU_SRQ_S0_VALID 188
+#define PPC970_PME_PM_LARX_LSU0 189
+#define PPC970_PME_PM_GCT_EMPTY_CYC 190
+#define PPC970_PME_PM_FPU1_ALL 191
+#define PPC970_PME_PM_FPU1_FSQRT 192
+#define PPC970_PME_PM_FPU_FIN 193
+#define PPC970_PME_PM_LSU_SRQ_STFWD 194
+#define PPC970_PME_PM_MRK_LD_MISS_L1_LSU1 195
+#define PPC970_PME_PM_FXU0_FIN 196
+#define PPC970_PME_PM_MRK_FPU_FIN 197
+#define PPC970_PME_PM_PMC5_OVERFLOW 198
+#define PPC970_PME_PM_SNOOP_TLBIE 199
+#define PPC970_PME_PM_FPU1_FRSP_FCONV 200
+#define PPC970_PME_PM_FPU0_FDIV 201
+#define PPC970_PME_PM_LD_REF_L1_LSU1 202
+#define PPC970_PME_PM_HV_CYC 203
+#define PPC970_PME_PM_LR_CTR_MAP_FULL_CYC 204
+#define PPC970_PME_PM_FPU_DENORM 205
+#define PPC970_PME_PM_LSU0_REJECT_SRQ 206
+#define PPC970_PME_PM_LSU1_REJECT_SRQ 207
+#define PPC970_PME_PM_LSU1_DERAT_MISS 208
+#define PPC970_PME_PM_IC_PREF_REQ 209
+#define PPC970_PME_PM_MRK_LSU_FIN 210
+#define PPC970_PME_PM_MRK_DATA_FROM_MEM 211
+#define PPC970_PME_PM_LSU0_FLUSH_UST 212
+#define PPC970_PME_PM_LSU_FLUSH_LRQ 213
+#define PPC970_PME_PM_LSU_FLUSH_SRQ 214
+
+
+static const int ppc970_event_ids[][PPC970_NUM_EVENT_COUNTERS] = {
+ [ PPC970_PME_PM_LSU_REJECT_RELOAD_CDF ] = { -1, -1, -1, -1, -1, 68, -1, -1 },
+ [ PPC970_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { -1, -1, 63, 61, -1, -1, 60, 61 },
+ [ PPC970_PME_PM_FPU1_SINGLE ] = { 23, 22, -1, -1, 24, 23, -1, -1 },
+ [ PPC970_PME_PM_FPU0_STALL3 ] = { 15, 14, -1, -1, 16, 15, -1, -1 },
+ [ PPC970_PME_PM_TB_BIT_TRANS ] = { -1, -1, -1, -1, -1, -1, -1, 67 },
+ [ PPC970_PME_PM_GPR_MAP_FULL_CYC ] = { -1, -1, 28, 28, -1, -1, 27, 27 },
+ [ PPC970_PME_PM_MRK_ST_CMPL ] = { 79, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_FPU0_STF ] = { 16, 15, -1, -1, 17, 16, -1, -1 },
+ [ PPC970_PME_PM_FPU1_FMA ] = { 20, 19, -1, -1, 21, 20, -1, -1 },
+ [ PPC970_PME_PM_LSU1_FLUSH_ULD ] = { 58, 57, -1, -1, 60, 57, -1, -1 },
+ [ PPC970_PME_PM_MRK_INST_FIN ] = { -1, -1, -1, -1, -1, -1, 50, -1 },
+ [ PPC970_PME_PM_MRK_LSU0_FLUSH_UST ] = { -1, -1, 58, 56, -1, -1, 55, 55 },
+ [ PPC970_PME_PM_LSU_LRQ_S0_ALLOC ] = { 66, 66, -1, -1, 68, 66, -1, -1 },
+ [ PPC970_PME_PM_FPU_FDIV ] = { 27, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_FPU0_FULL_CYC ] = { 13, 12, -1, -1, 14, 13, -1, -1 },
+ [ PPC970_PME_PM_FPU_SINGLE ] = { -1, -1, -1, -1, 28, -1, -1, -1 },
+ [ PPC970_PME_PM_FPU0_FMA ] = { 11, 10, -1, -1, 12, 11, -1, -1 },
+ [ PPC970_PME_PM_MRK_LSU1_FLUSH_ULD ] = { -1, -1, 61, 59, -1, -1, 58, 58 },
+ [ PPC970_PME_PM_LSU1_FLUSH_LRQ ] = { 56, 55, -1, -1, 58, 55, -1, -1 },
+ [ PPC970_PME_PM_DTLB_MISS ] = { 6, 5, -1, -1, 7, 6, -1, -1 },
+ [ PPC970_PME_PM_MRK_ST_MISS_L1 ] = { 80, 76, -1, -1, 79, 79, -1, -1 },
+ [ PPC970_PME_PM_EXT_INT ] = { -1, -1, -1, -1, -1, -1, -1, 10 },
+ [ PPC970_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { -1, -1, 59, 57, -1, -1, 56, 56 },
+ [ PPC970_PME_PM_MRK_ST_GPS ] = { -1, -1, -1, -1, -1, 78, -1, -1 },
+ [ PPC970_PME_PM_GRP_DISP_SUCCESS ] = { -1, -1, -1, -1, 34, -1, -1, -1 },
+ [ PPC970_PME_PM_LSU1_LDF ] = { -1, -1, 43, 40, -1, -1, 40, 41 },
+ [ PPC970_PME_PM_LSU0_SRQ_STFWD ] = { 54, 53, -1, -1, 56, 53, -1, -1 },
+ [ PPC970_PME_PM_CR_MAP_FULL_CYC ] = { 1, 1, -1, -1, 2, 1, -1, -1 },
+ [ PPC970_PME_PM_MRK_LSU0_FLUSH_ULD ] = { -1, -1, 57, 55, -1, -1, 54, 54 },
+ [ PPC970_PME_PM_LSU_DERAT_MISS ] = { -1, -1, -1, -1, -1, 64, -1, -1 },
+ [ PPC970_PME_PM_FPU0_SINGLE ] = { 14, 13, -1, -1, 15, 14, -1, -1 },
+ [ PPC970_PME_PM_FPU1_FDIV ] = { 19, 18, -1, -1, 20, 19, -1, -1 },
+ [ PPC970_PME_PM_FPU1_FEST ] = { -1, -1, 18, 18, -1, -1, 17, 18 },
+ [ PPC970_PME_PM_FPU0_FRSP_FCONV ] = { -1, -1, 17, 17, -1, -1, 16, 17 },
+ [ PPC970_PME_PM_GCT_EMPTY_SRQ_FULL ] = { -1, 27, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_MRK_ST_CMPL_INT ] = { -1, -1, 64, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_FLUSH_BR_MPRED ] = { -1, -1, 11, 11, -1, -1, 10, 11 },
+ [ PPC970_PME_PM_FXU_FIN ] = { -1, -1, 27, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_FPU_STF ] = { -1, -1, -1, -1, -1, 27, -1, -1 },
+ [ PPC970_PME_PM_DSLB_MISS ] = { 5, 4, -1, -1, 6, 5, -1, -1 },
+ [ PPC970_PME_PM_FXLS1_FULL_CYC ] = { -1, -1, 24, 24, -1, -1, 23, 24 },
+ [ PPC970_PME_PM_LSU_LMQ_LHR_MERGE ] = { -1, -1, 46, 43, -1, -1, 43, 45 },
+ [ PPC970_PME_PM_MRK_STCX_FAIL ] = { 78, 75, -1, -1, 78, 77, -1, -1 },
+ [ PPC970_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { -1, -1, -1, -1, -1, -1, 24, -1 },
+ [ PPC970_PME_PM_MRK_DATA_FROM_L25_SHR ] = { -1, -1, -1, -1, 73, -1, -1, -1 },
+ [ PPC970_PME_PM_LSU_FLUSH_ULD ] = { 65, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_MRK_BRU_FIN ] = { -1, 71, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_IERAT_XLATE_WR ] = { 36, 36, -1, -1, 39, 36, -1, -1 },
+ [ PPC970_PME_PM_DATA_FROM_MEM ] = { -1, -1, 5, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_FPR_MAP_FULL_CYC ] = { 7, 6, -1, -1, 8, 7, -1, -1 },
+ [ PPC970_PME_PM_FPU1_FULL_CYC ] = { 22, 21, -1, -1, 23, 22, -1, -1 },
+ [ PPC970_PME_PM_FPU0_FIN ] = { -1, -1, 14, 14, -1, -1, 13, 14 },
+ [ PPC970_PME_PM_GRP_BR_REDIR ] = { 31, 30, -1, -1, 32, 31, -1, -1 },
+ [ PPC970_PME_PM_THRESH_TIMEO ] = { -1, 83, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_FPU_FSQRT ] = { -1, -1, -1, -1, -1, 26, -1, -1 },
+ [ PPC970_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { -1, -1, 55, 53, -1, -1, 52, 52 },
+ [ PPC970_PME_PM_PMC1_OVERFLOW ] = { -1, 77, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_FXLS0_FULL_CYC ] = { -1, -1, 23, 23, -1, -1, 22, 23 },
+ [ PPC970_PME_PM_FPU0_ALL ] = { 8, 7, -1, -1, 9, 8, -1, -1 },
+ [ PPC970_PME_PM_DATA_TABLEWALK_CYC ] = { 4, 3, -1, -1, 5, 4, -1, -1 },
+ [ PPC970_PME_PM_FPU0_FEST ] = { -1, -1, 13, 13, -1, -1, 12, 13 },
+ [ PPC970_PME_PM_DATA_FROM_L25_MOD ] = { -1, -1, -1, -1, -1, 3, -1, -1 },
+ [ PPC970_PME_PM_LSU0_REJECT_ERAT_MISS ] = { 50, 49, -1, -1, 52, 49, -1, -1 },
+ [ PPC970_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { -1, 65, 49, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_LSU0_REJECT_RELOAD_CDF ] = { 52, 51, -1, -1, 54, 51, -1, -1 },
+ [ PPC970_PME_PM_FPU_FEST ] = { -1, -1, 22, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_0INST_FETCH ] = { -1, -1, -1, 0, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_LD_MISS_L1_LSU0 ] = { -1, -1, 38, 35, -1, -1, 35, 35 },
+ [ PPC970_PME_PM_LSU1_REJECT_RELOAD_CDF ] = { 62, 61, -1, -1, 64, 61, -1, -1 },
+ [ PPC970_PME_PM_L1_PREF ] = { -1, -1, 34, 32, -1, -1, 32, 32 },
+ [ PPC970_PME_PM_FPU1_STALL3 ] = { 24, 23, -1, -1, 25, 24, -1, -1 },
+ [ PPC970_PME_PM_BRQ_FULL_CYC ] = { 0, 0, -1, -1, 1, 0, -1, -1 },
+ [ PPC970_PME_PM_PMC8_OVERFLOW ] = { 81, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_PMC7_OVERFLOW ] = { -1, -1, -1, -1, -1, -1, -1, 62 },
+ [ PPC970_PME_PM_WORK_HELD ] = { -1, 84, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { 76, 73, -1, -1, 76, 75, -1, -1 },
+ [ PPC970_PME_PM_FXU_IDLE ] = { -1, -1, -1, -1, 29, -1, -1, -1 },
+ [ PPC970_PME_PM_INST_CMPL ] = { 37, 37, 31, 30, 40, 37, 30, 30 },
+ [ PPC970_PME_PM_LSU1_FLUSH_UST ] = { 59, 58, -1, -1, 61, 58, -1, -1 },
+ [ PPC970_PME_PM_LSU0_FLUSH_ULD ] = { 48, 47, -1, -1, 50, 47, -1, -1 },
+ [ PPC970_PME_PM_LSU_FLUSH ] = { -1, -1, 44, 41, -1, -1, 41, 42 },
+ [ PPC970_PME_PM_INST_FROM_L2 ] = { 40, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_LSU1_REJECT_LMQ_FULL ] = { 61, 60, -1, -1, 63, 60, -1, -1 },
+ [ PPC970_PME_PM_PMC2_OVERFLOW ] = { -1, -1, 66, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_FPU0_DENORM ] = { 9, 8, -1, -1, 10, 9, -1, -1 },
+ [ PPC970_PME_PM_FPU1_FMOV_FEST ] = { -1, -1, 20, 20, -1, -1, 19, 20 },
+ [ PPC970_PME_PM_GRP_DISP_REJECT ] = { 32, 32, -1, -1, 33, 32, -1, 29 },
+ [ PPC970_PME_PM_LSU_LDF ] = { -1, -1, -1, -1, -1, -1, -1, 43 },
+ [ PPC970_PME_PM_INST_DISP ] = { 38, 38, -1, -1, 41, 38, -1, -1 },
+ [ PPC970_PME_PM_DATA_FROM_L25_SHR ] = { -1, -1, -1, -1, 4, -1, -1, -1 },
+ [ PPC970_PME_PM_L1_DCACHE_RELOAD_VALID ] = { -1, -1, 33, 31, -1, -1, 31, 31 },
+ [ PPC970_PME_PM_MRK_GRP_ISSUED ] = { -1, -1, -1, -1, -1, 73, -1, -1 },
+ [ PPC970_PME_PM_FPU_FMA ] = { -1, 25, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_MRK_CRU_FIN ] = { -1, -1, -1, 50, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_MRK_LSU1_FLUSH_UST ] = { -1, -1, 62, 60, -1, -1, 59, 59 },
+ [ PPC970_PME_PM_MRK_FXU_FIN ] = { -1, -1, -1, -1, -1, 72, -1, -1 },
+ [ PPC970_PME_PM_LSU1_REJECT_ERAT_MISS ] = { 60, 59, -1, -1, 62, 59, -1, -1 },
+ [ PPC970_PME_PM_BR_ISSUED ] = { -1, -1, 0, 1, -1, -1, 0, 0 },
+ [ PPC970_PME_PM_PMC4_OVERFLOW ] = { -1, -1, -1, -1, 80, -1, -1, -1 },
+ [ PPC970_PME_PM_EE_OFF ] = { -1, -1, 9, 9, -1, -1, 8, 8 },
+ [ PPC970_PME_PM_INST_FROM_L25_MOD ] = { -1, -1, -1, -1, -1, 39, -1, -1 },
+ [ PPC970_PME_PM_ITLB_MISS ] = { 42, 41, -1, -1, 44, 41, -1, -1 },
+ [ PPC970_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { -1, -1, -1, 26, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_GRP_DISP_VALID ] = { 33, 33, -1, -1, 35, 33, -1, -1 },
+ [ PPC970_PME_PM_MRK_GRP_DISP ] = { 73, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_LSU_FLUSH_UST ] = { -1, 64, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_FXU1_FIN ] = { -1, -1, 26, 27, -1, -1, 26, 26 },
+ [ PPC970_PME_PM_GRP_CMPL ] = { -1, -1, -1, -1, -1, -1, 28, -1 },
+ [ PPC970_PME_PM_FPU_FRSP_FCONV ] = { -1, -1, -1, -1, -1, -1, 21, -1 },
+ [ PPC970_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { -1, -1, 56, 54, -1, -1, 53, 53 },
+ [ PPC970_PME_PM_LSU_LMQ_FULL_CYC ] = { -1, -1, 45, 42, -1, -1, 42, 44 },
+ [ PPC970_PME_PM_ST_REF_L1_LSU0 ] = { -1, -1, 69, 64, -1, -1, 64, 64 },
+ [ PPC970_PME_PM_LSU0_DERAT_MISS ] = { 45, 44, -1, -1, 47, 44, -1, -1 },
+ [ PPC970_PME_PM_LSU_SRQ_SYNC_CYC ] = { -1, -1, 52, 49, -1, -1, 48, 50 },
+ [ PPC970_PME_PM_FPU_STALL3 ] = { -1, 26, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_LSU_REJECT_ERAT_MISS ] = { -1, -1, -1, -1, 70, -1, -1, -1 },
+ [ PPC970_PME_PM_MRK_DATA_FROM_L2 ] = { 72, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_LSU0_FLUSH_SRQ ] = { 47, 46, -1, -1, 49, 46, -1, -1 },
+ [ PPC970_PME_PM_FPU0_FMOV_FEST ] = { -1, -1, 15, 15, -1, -1, 14, 15 },
+ [ PPC970_PME_PM_LD_REF_L1_LSU0 ] = { -1, -1, 40, 37, -1, -1, 37, 38 },
+ [ PPC970_PME_PM_LSU1_FLUSH_SRQ ] = { 57, 56, -1, -1, 59, 56, -1, -1 },
+ [ PPC970_PME_PM_GRP_BR_MPRED ] = { 30, 29, -1, -1, 31, 30, -1, -1 },
+ [ PPC970_PME_PM_LSU_LMQ_S0_ALLOC ] = { -1, -1, 47, 44, -1, -1, 44, 46 },
+ [ PPC970_PME_PM_LSU0_REJECT_LMQ_FULL ] = { 51, 50, -1, -1, 53, 50, -1, -1 },
+ [ PPC970_PME_PM_ST_REF_L1 ] = { -1, -1, -1, -1, -1, -1, 63, -1 },
+ [ PPC970_PME_PM_MRK_VMX_FIN ] = { -1, -1, 65, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_LSU_SRQ_EMPTY_CYC ] = { -1, -1, -1, 47, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_FPU1_STF ] = { 25, 24, -1, -1, 26, 25, -1, -1 },
+ [ PPC970_PME_PM_RUN_CYC ] = { 82, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_LSU_LMQ_S0_VALID ] = { -1, -1, 48, 45, -1, -1, 45, 47 },
+ [ PPC970_PME_PM_LSU0_LDF ] = { -1, -1, 42, 39, -1, -1, 39, 40 },
+ [ PPC970_PME_PM_LSU_LRQ_S0_VALID ] = { 67, 67, -1, -1, 69, 67, -1, -1 },
+ [ PPC970_PME_PM_PMC3_OVERFLOW ] = { -1, -1, -1, 62, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_MRK_IMR_RELOAD ] = { 74, 72, -1, -1, 75, 74, -1, -1 },
+ [ PPC970_PME_PM_MRK_GRP_TIMEO ] = { -1, -1, -1, -1, 74, -1, -1, -1 },
+ [ PPC970_PME_PM_FPU_FMOV_FEST ] = { -1, -1, -1, -1, -1, -1, -1, 22 },
+ [ PPC970_PME_PM_GRP_DISP_BLK_SB_CYC ] = { -1, -1, 29, 29, -1, -1, 29, 28 },
+ [ PPC970_PME_PM_XER_MAP_FULL_CYC ] = { 88, 85, -1, -1, 86, 86, -1, -1 },
+ [ PPC970_PME_PM_ST_MISS_L1 ] = { 86, 81, 68, 63, 84, 84, 62, 63 },
+ [ PPC970_PME_PM_STOP_COMPLETION ] = { -1, -1, 67, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_MRK_GRP_CMPL ] = { -1, -1, -1, 51, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_ISLB_MISS ] = { 41, 40, -1, -1, 43, 40, -1, -1 },
+ [ PPC970_PME_PM_SUSPENDED ] = { 87, 82, 71, 66, 85, 85, 66, 66 },
+ [ PPC970_PME_PM_CYC ] = { 2, 2, 4, 5, 3, 2, 4, 4 },
+ [ PPC970_PME_PM_LD_MISS_L1_LSU1 ] = { -1, -1, 39, 36, -1, -1, 36, 36 },
+ [ PPC970_PME_PM_STCX_FAIL ] = { 84, 79, -1, -1, 82, 82, -1, -1 },
+ [ PPC970_PME_PM_LSU1_SRQ_STFWD ] = { 64, 63, -1, -1, 66, 63, -1, -1 },
+ [ PPC970_PME_PM_GRP_DISP ] = { -1, 31, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_L2_PREF ] = { -1, -1, 36, 34, -1, -1, 34, 34 },
+ [ PPC970_PME_PM_FPU1_DENORM ] = { 18, 17, -1, -1, 19, 18, -1, -1 },
+ [ PPC970_PME_PM_DATA_FROM_L2 ] = { 3, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_FPU0_FPSCR ] = { -1, -1, 16, 16, -1, -1, 15, 16 },
+ [ PPC970_PME_PM_MRK_DATA_FROM_L25_MOD ] = { -1, -1, -1, -1, -1, 71, -1, -1 },
+ [ PPC970_PME_PM_FPU0_FSQRT ] = { 12, 11, -1, -1, 13, 12, -1, -1 },
+ [ PPC970_PME_PM_LD_REF_L1 ] = { -1, -1, -1, -1, -1, -1, -1, 37 },
+ [ PPC970_PME_PM_MRK_L1_RELOAD_VALID ] = { -1, -1, 54, 52, -1, -1, 51, 51 },
+ [ PPC970_PME_PM_1PLUS_PPC_CMPL ] = { -1, -1, -1, -1, 0, -1, -1, -1 },
+ [ PPC970_PME_PM_INST_FROM_L1 ] = { 39, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_EE_OFF_EXT_INT ] = { -1, -1, 10, 10, -1, -1, 9, 9 },
+ [ PPC970_PME_PM_PMC6_OVERFLOW ] = { -1, -1, -1, -1, -1, -1, 61, -1 },
+ [ PPC970_PME_PM_LSU_LRQ_FULL_CYC ] = { -1, -1, 50, 46, -1, -1, 46, 48 },
+ [ PPC970_PME_PM_IC_PREF_INSTALL ] = { 34, 34, -1, -1, 37, 34, -1, -1 },
+ [ PPC970_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { -1, -1, 7, 7, -1, -1, 6, 6 },
+ [ PPC970_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { -1, -1, 60, 58, -1, -1, 57, 57 },
+ [ PPC970_PME_PM_GCT_FULL_CYC ] = { 29, 28, -1, -1, 30, 29, -1, -1 },
+ [ PPC970_PME_PM_INST_FROM_MEM ] = { -1, 39, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_FLUSH_LSU_BR_MPRED ] = { -1, -1, 12, 12, -1, -1, 11, 12 },
+ [ PPC970_PME_PM_FXU_BUSY ] = { -1, -1, -1, -1, -1, 28, -1, -1 },
+ [ PPC970_PME_PM_ST_REF_L1_LSU1 ] = { -1, -1, 70, 65, -1, -1, 65, 65 },
+ [ PPC970_PME_PM_MRK_LD_MISS_L1 ] = { 75, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_L1_WRITE_CYC ] = { -1, -1, 35, 33, -1, -1, 33, 33 },
+ [ PPC970_PME_PM_LSU_REJECT_LMQ_FULL ] = { -1, 68, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_FPU_ALL ] = { -1, -1, -1, -1, 27, -1, -1, -1 },
+ [ PPC970_PME_PM_LSU_SRQ_S0_ALLOC ] = { 69, 69, -1, -1, 71, 69, -1, -1 },
+ [ PPC970_PME_PM_INST_FROM_L25_SHR ] = { -1, -1, -1, -1, 42, -1, -1, -1 },
+ [ PPC970_PME_PM_GRP_MRK ] = { -1, -1, -1, -1, 36, -1, -1, -1 },
+ [ PPC970_PME_PM_BR_MPRED_CR ] = { -1, -1, 1, 2, -1, -1, 1, 1 },
+ [ PPC970_PME_PM_DC_PREF_STREAM_ALLOC ] = { -1, -1, 8, 8, -1, -1, 7, 7 },
+ [ PPC970_PME_PM_FPU1_FIN ] = { -1, -1, 19, 19, -1, -1, 18, 19 },
+ [ PPC970_PME_PM_LSU_REJECT_SRQ ] = { 68, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_BR_MPRED_TA ] = { -1, -1, 2, 3, -1, -1, 2, 2 },
+ [ PPC970_PME_PM_CRQ_FULL_CYC ] = { -1, -1, 3, 4, -1, -1, 3, 3 },
+ [ PPC970_PME_PM_LD_MISS_L1 ] = { -1, -1, 37, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_INST_FROM_PREF ] = { -1, -1, 32, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_STCX_PASS ] = { 85, 80, -1, -1, 83, 83, -1, -1 },
+ [ PPC970_PME_PM_DC_INV_L2 ] = { -1, -1, 6, 6, -1, -1, 5, 5 },
+ [ PPC970_PME_PM_LSU_SRQ_FULL_CYC ] = { -1, -1, 51, 48, -1, -1, 47, 49 },
+ [ PPC970_PME_PM_LSU0_FLUSH_LRQ ] = { 46, 45, -1, -1, 48, 45, -1, -1 },
+ [ PPC970_PME_PM_LSU_SRQ_S0_VALID ] = { 70, 70, -1, -1, 72, 70, -1, -1 },
+ [ PPC970_PME_PM_LARX_LSU0 ] = { 43, 42, -1, -1, 45, 42, -1, -1 },
+ [ PPC970_PME_PM_GCT_EMPTY_CYC ] = { 28, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_FPU1_ALL ] = { 17, 16, -1, -1, 18, 17, -1, -1 },
+ [ PPC970_PME_PM_FPU1_FSQRT ] = { 21, 20, -1, -1, 22, 21, -1, -1 },
+ [ PPC970_PME_PM_FPU_FIN ] = { -1, -1, -1, 22, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_LSU_SRQ_STFWD ] = { 71, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { 77, 74, -1, -1, 77, 76, -1, -1 },
+ [ PPC970_PME_PM_FXU0_FIN ] = { -1, -1, 25, 25, -1, -1, 25, 25 },
+ [ PPC970_PME_PM_MRK_FPU_FIN ] = { -1, -1, -1, -1, -1, -1, 49, -1 },
+ [ PPC970_PME_PM_PMC5_OVERFLOW ] = { -1, -1, -1, -1, -1, 80, -1, -1 },
+ [ PPC970_PME_PM_SNOOP_TLBIE ] = { 83, 78, -1, -1, 81, 81, -1, -1 },
+ [ PPC970_PME_PM_FPU1_FRSP_FCONV ] = { -1, -1, 21, 21, -1, -1, 20, 21 },
+ [ PPC970_PME_PM_FPU0_FDIV ] = { 10, 9, -1, -1, 11, 10, -1, -1 },
+ [ PPC970_PME_PM_LD_REF_L1_LSU1 ] = { -1, -1, 41, 38, -1, -1, 38, 39 },
+ [ PPC970_PME_PM_HV_CYC ] = { -1, -1, 30, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_LR_CTR_MAP_FULL_CYC ] = { 44, 43, -1, -1, 46, 43, -1, -1 },
+ [ PPC970_PME_PM_FPU_DENORM ] = { 26, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_LSU0_REJECT_SRQ ] = { 53, 52, -1, -1, 55, 52, -1, -1 },
+ [ PPC970_PME_PM_LSU1_REJECT_SRQ ] = { 63, 62, -1, -1, 65, 62, -1, -1 },
+ [ PPC970_PME_PM_LSU1_DERAT_MISS ] = { 55, 54, -1, -1, 57, 54, -1, -1 },
+ [ PPC970_PME_PM_IC_PREF_REQ ] = { 35, 35, -1, -1, 38, 35, -1, -1 },
+ [ PPC970_PME_PM_MRK_LSU_FIN ] = { -1, -1, -1, -1, -1, -1, -1, 60 },
+ [ PPC970_PME_PM_MRK_DATA_FROM_MEM ] = { -1, -1, 53, -1, -1, -1, -1, -1 },
+ [ PPC970_PME_PM_LSU0_FLUSH_UST ] = { 49, 48, -1, -1, 51, 48, -1, -1 },
+ [ PPC970_PME_PM_LSU_FLUSH_LRQ ] = { -1, -1, -1, -1, -1, 65, -1, -1 },
+ [ PPC970_PME_PM_LSU_FLUSH_SRQ ] = { -1, -1, -1, -1, 67, -1, -1, -1 }
+};
+
+static const unsigned long long ppc970_group_vecs[][PPC970_NUM_GROUP_VEC] = {
+ [ PPC970_PME_PM_LSU_REJECT_RELOAD_CDF ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_MRK_LSU_SRQ_INST_VALID ] = {
+ 0x0000000800000000ULL
+ },
+ [ PPC970_PME_PM_FPU1_SINGLE ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_FPU0_STALL3 ] = {
+ 0x0000000000002000ULL
+ },
+ [ PPC970_PME_PM_TB_BIT_TRANS ] = {
+ 0x0000000000080000ULL
+ },
+ [ PPC970_PME_PM_GPR_MAP_FULL_CYC ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_MRK_ST_CMPL ] = {
+ 0x0000000800000000ULL
+ },
+ [ PPC970_PME_PM_FPU0_STF ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_FPU1_FMA ] = {
+ 0x0000000000000400ULL
+ },
+ [ PPC970_PME_PM_LSU1_FLUSH_ULD ] = {
+ 0x0000000000008000ULL
+ },
+ [ PPC970_PME_PM_MRK_INST_FIN ] = {
+ 0x0000000200000000ULL
+ },
+ [ PPC970_PME_PM_MRK_LSU0_FLUSH_UST ] = {
+ 0x0000001000000000ULL
+ },
+ [ PPC970_PME_PM_LSU_LRQ_S0_ALLOC ] = {
+ 0x0000000010000000ULL
+ },
+ [ PPC970_PME_PM_FPU_FDIV ] = {
+ 0x0000000000900010ULL
+ },
+ [ PPC970_PME_PM_FPU0_FULL_CYC ] = {
+ 0x0000000000000080ULL
+ },
+ [ PPC970_PME_PM_FPU_SINGLE ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_FPU0_FMA ] = {
+ 0x0000000000000400ULL
+ },
+ [ PPC970_PME_PM_MRK_LSU1_FLUSH_ULD ] = {
+ 0x0000001000000000ULL
+ },
+ [ PPC970_PME_PM_LSU1_FLUSH_LRQ ] = {
+ 0x0000000000004000ULL
+ },
+ [ PPC970_PME_PM_DTLB_MISS ] = {
+ 0x0000000010600000ULL
+ },
+ [ PPC970_PME_PM_MRK_ST_MISS_L1 ] = {
+ 0x0000001000000000ULL
+ },
+ [ PPC970_PME_PM_EXT_INT ] = {
+ 0x0000000000000200ULL
+ },
+ [ PPC970_PME_PM_MRK_LSU1_FLUSH_LRQ ] = {
+ 0x0000002000000000ULL
+ },
+ [ PPC970_PME_PM_MRK_ST_GPS ] = {
+ 0x0000000800000000ULL
+ },
+ [ PPC970_PME_PM_GRP_DISP_SUCCESS ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_LSU1_LDF ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_LSU0_SRQ_STFWD ] = {
+ 0x0000000000020000ULL
+ },
+ [ PPC970_PME_PM_CR_MAP_FULL_CYC ] = {
+ 0x0000000000000040ULL
+ },
+ [ PPC970_PME_PM_MRK_LSU0_FLUSH_ULD ] = {
+ 0x0000001000000000ULL
+ },
+ [ PPC970_PME_PM_LSU_DERAT_MISS ] = {
+ 0x0000000100000000ULL
+ },
+ [ PPC970_PME_PM_FPU0_SINGLE ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_FPU1_FDIV ] = {
+ 0x0000000000000400ULL
+ },
+ [ PPC970_PME_PM_FPU1_FEST ] = {
+ 0x0000000000001000ULL
+ },
+ [ PPC970_PME_PM_FPU0_FRSP_FCONV ] = {
+ 0x0000000000000400ULL
+ },
+ [ PPC970_PME_PM_GCT_EMPTY_SRQ_FULL ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_MRK_ST_CMPL_INT ] = {
+ 0x0000000800000000ULL
+ },
+ [ PPC970_PME_PM_FLUSH_BR_MPRED ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_FXU_FIN ] = {
+ 0x0000004000100000ULL
+ },
+ [ PPC970_PME_PM_FPU_STF ] = {
+ 0x0000000000800020ULL
+ },
+ [ PPC970_PME_PM_DSLB_MISS ] = {
+ 0x0000000004000000ULL
+ },
+ [ PPC970_PME_PM_FXLS1_FULL_CYC ] = {
+ 0x0000008000000080ULL
+ },
+ [ PPC970_PME_PM_LSU_LMQ_LHR_MERGE ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_MRK_STCX_FAIL ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_FXU0_BUSY_FXU1_IDLE ] = {
+ 0x0000004000000000ULL
+ },
+ [ PPC970_PME_PM_MRK_DATA_FROM_L25_SHR ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_LSU_FLUSH_ULD ] = {
+ 0x0000000000000008ULL
+ },
+ [ PPC970_PME_PM_MRK_BRU_FIN ] = {
+ 0x0000000400000000ULL
+ },
+ [ PPC970_PME_PM_IERAT_XLATE_WR ] = {
+ 0x0000000080000000ULL
+ },
+ [ PPC970_PME_PM_DATA_FROM_MEM ] = {
+ 0x0000000008000000ULL
+ },
+ [ PPC970_PME_PM_FPR_MAP_FULL_CYC ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_FPU1_FULL_CYC ] = {
+ 0x0000000000000080ULL
+ },
+ [ PPC970_PME_PM_FPU0_FIN ] = {
+ 0x0000000000802800ULL
+ },
+ [ PPC970_PME_PM_GRP_BR_REDIR ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_THRESH_TIMEO ] = {
+ 0x0000000200000000ULL
+ },
+ [ PPC970_PME_PM_FPU_FSQRT ] = {
+ 0x0000000000100010ULL
+ },
+ [ PPC970_PME_PM_MRK_LSU0_FLUSH_LRQ ] = {
+ 0x0000002000000000ULL
+ },
+ [ PPC970_PME_PM_PMC1_OVERFLOW ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_FXLS0_FULL_CYC ] = {
+ 0x0000008000000080ULL
+ },
+ [ PPC970_PME_PM_FPU0_ALL ] = {
+ 0x0000000000000800ULL
+ },
+ [ PPC970_PME_PM_DATA_TABLEWALK_CYC ] = {
+ 0x0000000020000000ULL
+ },
+ [ PPC970_PME_PM_FPU0_FEST ] = {
+ 0x0000000000001000ULL
+ },
+ [ PPC970_PME_PM_DATA_FROM_L25_MOD ] = {
+ 0x0000000008000000ULL
+ },
+ [ PPC970_PME_PM_LSU0_REJECT_ERAT_MISS ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = {
+ 0x0000000000480000ULL
+ },
+ [ PPC970_PME_PM_LSU0_REJECT_RELOAD_CDF ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_FPU_FEST ] = {
+ 0x0000000000000010ULL
+ },
+ [ PPC970_PME_PM_0INST_FETCH ] = {
+ 0x0000030000000000ULL
+ },
+ [ PPC970_PME_PM_LD_MISS_L1_LSU0 ] = {
+ 0x0000000000008000ULL
+ },
+ [ PPC970_PME_PM_LSU1_REJECT_RELOAD_CDF ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_L1_PREF ] = {
+ 0x0000000010000000ULL
+ },
+ [ PPC970_PME_PM_FPU1_STALL3 ] = {
+ 0x0000000000002000ULL
+ },
+ [ PPC970_PME_PM_BRQ_FULL_CYC ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_PMC8_OVERFLOW ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_PMC7_OVERFLOW ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_WORK_HELD ] = {
+ 0x0000000000000200ULL
+ },
+ [ PPC970_PME_PM_MRK_LD_MISS_L1_LSU0 ] = {
+ 0x0000002000000000ULL
+ },
+ [ PPC970_PME_PM_FXU_IDLE ] = {
+ 0x000000c000000000ULL
+ },
+ [ PPC970_PME_PM_INST_CMPL ] = {
+ 0x000003fbffffffffULL
+ },
+ [ PPC970_PME_PM_LSU1_FLUSH_UST ] = {
+ 0x0000000000010000ULL
+ },
+ [ PPC970_PME_PM_LSU0_FLUSH_ULD ] = {
+ 0x0000000000008000ULL
+ },
+ [ PPC970_PME_PM_LSU_FLUSH ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_INST_FROM_L2 ] = {
+ 0x0000020020000000ULL
+ },
+ [ PPC970_PME_PM_LSU1_REJECT_LMQ_FULL ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_PMC2_OVERFLOW ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_FPU0_DENORM ] = {
+ 0x0000000000001000ULL
+ },
+ [ PPC970_PME_PM_FPU1_FMOV_FEST ] = {
+ 0x0000000000001000ULL
+ },
+ [ PPC970_PME_PM_GRP_DISP_REJECT ] = {
+ 0x0000000000000101ULL
+ },
+ [ PPC970_PME_PM_LSU_LDF ] = {
+ 0x0000000000800020ULL
+ },
+ [ PPC970_PME_PM_INST_DISP ] = {
+ 0x0000000100000146ULL
+ },
+ [ PPC970_PME_PM_DATA_FROM_L25_SHR ] = {
+ 0x0000000008000000ULL
+ },
+ [ PPC970_PME_PM_L1_DCACHE_RELOAD_VALID ] = {
+ 0x0000000100040000ULL
+ },
+ [ PPC970_PME_PM_MRK_GRP_ISSUED ] = {
+ 0x0000000200000000ULL
+ },
+ [ PPC970_PME_PM_FPU_FMA ] = {
+ 0x0000000000900010ULL
+ },
+ [ PPC970_PME_PM_MRK_CRU_FIN ] = {
+ 0x0000000400000000ULL
+ },
+ [ PPC970_PME_PM_MRK_LSU1_FLUSH_UST ] = {
+ 0x0000001000000000ULL
+ },
+ [ PPC970_PME_PM_MRK_FXU_FIN ] = {
+ 0x0000000400000000ULL
+ },
+ [ PPC970_PME_PM_LSU1_REJECT_ERAT_MISS ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_BR_ISSUED ] = {
+ 0x0000000007000000ULL
+ },
+ [ PPC970_PME_PM_PMC4_OVERFLOW ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_EE_OFF ] = {
+ 0x0000000000000200ULL
+ },
+ [ PPC970_PME_PM_INST_FROM_L25_MOD ] = {
+ 0x0000020000000000ULL
+ },
+ [ PPC970_PME_PM_ITLB_MISS ] = {
+ 0x0000000010200000ULL
+ },
+ [ PPC970_PME_PM_FXU1_BUSY_FXU0_IDLE ] = {
+ 0x0000004000000000ULL
+ },
+ [ PPC970_PME_PM_GRP_DISP_VALID ] = {
+ 0x0000000100000100ULL
+ },
+ [ PPC970_PME_PM_MRK_GRP_DISP ] = {
+ 0x0000000400000000ULL
+ },
+ [ PPC970_PME_PM_LSU_FLUSH_UST ] = {
+ 0x0000000000000008ULL
+ },
+ [ PPC970_PME_PM_FXU1_FIN ] = {
+ 0x0000008000000100ULL
+ },
+ [ PPC970_PME_PM_GRP_CMPL ] = {
+ 0x0000000020080001ULL
+ },
+ [ PPC970_PME_PM_FPU_FRSP_FCONV ] = {
+ 0x0000000000000020ULL
+ },
+ [ PPC970_PME_PM_MRK_LSU0_FLUSH_SRQ ] = {
+ 0x0000002000000000ULL
+ },
+ [ PPC970_PME_PM_LSU_LMQ_FULL_CYC ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_ST_REF_L1_LSU0 ] = {
+ 0x0000000000030000ULL
+ },
+ [ PPC970_PME_PM_LSU0_DERAT_MISS ] = {
+ 0x0000000000040000ULL
+ },
+ [ PPC970_PME_PM_LSU_SRQ_SYNC_CYC ] = {
+ 0x0000000040000000ULL
+ },
+ [ PPC970_PME_PM_FPU_STALL3 ] = {
+ 0x0000000000000020ULL
+ },
+ [ PPC970_PME_PM_LSU_REJECT_ERAT_MISS ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_MRK_DATA_FROM_L2 ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_LSU0_FLUSH_SRQ ] = {
+ 0x0000000000004000ULL
+ },
+ [ PPC970_PME_PM_FPU0_FMOV_FEST ] = {
+ 0x0000000000001000ULL
+ },
+ [ PPC970_PME_PM_LD_REF_L1_LSU0 ] = {
+ 0x0000000000008000ULL
+ },
+ [ PPC970_PME_PM_LSU1_FLUSH_SRQ ] = {
+ 0x0000000000004000ULL
+ },
+ [ PPC970_PME_PM_GRP_BR_MPRED ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_LSU_LMQ_S0_ALLOC ] = {
+ 0x0000000008000000ULL
+ },
+ [ PPC970_PME_PM_LSU0_REJECT_LMQ_FULL ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_ST_REF_L1 ] = {
+ 0x000000010260000eULL
+ },
+ [ PPC970_PME_PM_MRK_VMX_FIN ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_LSU_SRQ_EMPTY_CYC ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_FPU1_STF ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_RUN_CYC ] = {
+ 0x0000000004000001ULL
+ },
+ [ PPC970_PME_PM_LSU_LMQ_S0_VALID ] = {
+ 0x0000000008000000ULL
+ },
+ [ PPC970_PME_PM_LSU0_LDF ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_LSU_LRQ_S0_VALID ] = {
+ 0x0000000010000000ULL
+ },
+ [ PPC970_PME_PM_PMC3_OVERFLOW ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_MRK_IMR_RELOAD ] = {
+ 0x0000001000000000ULL
+ },
+ [ PPC970_PME_PM_MRK_GRP_TIMEO ] = {
+ 0x0000000800000000ULL
+ },
+ [ PPC970_PME_PM_FPU_FMOV_FEST ] = {
+ 0x0000000000100010ULL
+ },
+ [ PPC970_PME_PM_GRP_DISP_BLK_SB_CYC ] = {
+ 0x0000000000000040ULL
+ },
+ [ PPC970_PME_PM_XER_MAP_FULL_CYC ] = {
+ 0x0000000000000040ULL
+ },
+ [ PPC970_PME_PM_ST_MISS_L1 ] = {
+ 0x0000000003630000ULL
+ },
+ [ PPC970_PME_PM_STOP_COMPLETION ] = {
+ 0x0000000000000201ULL
+ },
+ [ PPC970_PME_PM_MRK_GRP_CMPL ] = {
+ 0x0000000a00000000ULL
+ },
+ [ PPC970_PME_PM_ISLB_MISS ] = {
+ 0x0000000004000000ULL
+ },
+ [ PPC970_PME_PM_SUSPENDED ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_CYC ] = {
+ 0x000003ffffffffffULL
+ },
+ [ PPC970_PME_PM_LD_MISS_L1_LSU1 ] = {
+ 0x0000000000008000ULL
+ },
+ [ PPC970_PME_PM_STCX_FAIL ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_LSU1_SRQ_STFWD ] = {
+ 0x0000000000020000ULL
+ },
+ [ PPC970_PME_PM_GRP_DISP ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_L2_PREF ] = {
+ 0x0000000010000000ULL
+ },
+ [ PPC970_PME_PM_FPU1_DENORM ] = {
+ 0x0000000000001000ULL
+ },
+ [ PPC970_PME_PM_DATA_FROM_L2 ] = {
+ 0x0000000008000000ULL
+ },
+ [ PPC970_PME_PM_FPU0_FPSCR ] = {
+ 0x0000000000002000ULL
+ },
+ [ PPC970_PME_PM_MRK_DATA_FROM_L25_MOD ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_FPU0_FSQRT ] = {
+ 0x0000000000000800ULL
+ },
+ [ PPC970_PME_PM_LD_REF_L1 ] = {
+ 0x000000004260000eULL
+ },
+ [ PPC970_PME_PM_MRK_L1_RELOAD_VALID ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_1PLUS_PPC_CMPL ] = {
+ 0x0000000000080001ULL
+ },
+ [ PPC970_PME_PM_INST_FROM_L1 ] = {
+ 0x0000010080000000ULL
+ },
+ [ PPC970_PME_PM_EE_OFF_EXT_INT ] = {
+ 0x0000000000000200ULL
+ },
+ [ PPC970_PME_PM_PMC6_OVERFLOW ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_LSU_LRQ_FULL_CYC ] = {
+ 0x0000000000000080ULL
+ },
+ [ PPC970_PME_PM_IC_PREF_INSTALL ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_DC_PREF_OUT_OF_STREAMS ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_MRK_LSU1_FLUSH_SRQ ] = {
+ 0x0000002000000000ULL
+ },
+ [ PPC970_PME_PM_GCT_FULL_CYC ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_INST_FROM_MEM ] = {
+ 0x0000030020000000ULL
+ },
+ [ PPC970_PME_PM_FLUSH_LSU_BR_MPRED ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_FXU_BUSY ] = {
+ 0x000000c000000000ULL
+ },
+ [ PPC970_PME_PM_ST_REF_L1_LSU1 ] = {
+ 0x0000000000030000ULL
+ },
+ [ PPC970_PME_PM_MRK_LD_MISS_L1 ] = {
+ 0x0000000200000000ULL
+ },
+ [ PPC970_PME_PM_L1_WRITE_CYC ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_LSU_REJECT_LMQ_FULL ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_FPU_ALL ] = {
+ 0x0000000000000020ULL
+ },
+ [ PPC970_PME_PM_LSU_SRQ_S0_ALLOC ] = {
+ 0x0000000040000000ULL
+ },
+ [ PPC970_PME_PM_INST_FROM_L25_SHR ] = {
+ 0x0000020000000000ULL
+ },
+ [ PPC970_PME_PM_GRP_MRK ] = {
+ 0x0000000600000000ULL
+ },
+ [ PPC970_PME_PM_BR_MPRED_CR ] = {
+ 0x0000000005000000ULL
+ },
+ [ PPC970_PME_PM_DC_PREF_STREAM_ALLOC ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_FPU1_FIN ] = {
+ 0x0000000000802800ULL
+ },
+ [ PPC970_PME_PM_LSU_REJECT_SRQ ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_BR_MPRED_TA ] = {
+ 0x0000000005000000ULL
+ },
+ [ PPC970_PME_PM_CRQ_FULL_CYC ] = {
+ 0x0000000000000040ULL
+ },
+ [ PPC970_PME_PM_LD_MISS_L1 ] = {
+ 0x0000000043600006ULL
+ },
+ [ PPC970_PME_PM_INST_FROM_PREF ] = {
+ 0x0000030000000000ULL
+ },
+ [ PPC970_PME_PM_STCX_PASS ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_DC_INV_L2 ] = {
+ 0x0000000020010006ULL
+ },
+ [ PPC970_PME_PM_LSU_SRQ_FULL_CYC ] = {
+ 0x0000000000000080ULL
+ },
+ [ PPC970_PME_PM_LSU0_FLUSH_LRQ ] = {
+ 0x0000000000004000ULL
+ },
+ [ PPC970_PME_PM_LSU_SRQ_S0_VALID ] = {
+ 0x0000000040000000ULL
+ },
+ [ PPC970_PME_PM_LARX_LSU0 ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_GCT_EMPTY_CYC ] = {
+ 0x0000000100080200ULL
+ },
+ [ PPC970_PME_PM_FPU1_ALL ] = {
+ 0x0000000000000800ULL
+ },
+ [ PPC970_PME_PM_FPU1_FSQRT ] = {
+ 0x0000000000000800ULL
+ },
+ [ PPC970_PME_PM_FPU_FIN ] = {
+ 0x0000000000100010ULL
+ },
+ [ PPC970_PME_PM_LSU_SRQ_STFWD ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_MRK_LD_MISS_L1_LSU1 ] = {
+ 0x0000002000000000ULL
+ },
+ [ PPC970_PME_PM_FXU0_FIN ] = {
+ 0x0000008000000100ULL
+ },
+ [ PPC970_PME_PM_MRK_FPU_FIN ] = {
+ 0x0000000400000000ULL
+ },
+ [ PPC970_PME_PM_PMC5_OVERFLOW ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_SNOOP_TLBIE ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_FPU1_FRSP_FCONV ] = {
+ 0x0000000000000400ULL
+ },
+ [ PPC970_PME_PM_FPU0_FDIV ] = {
+ 0x0000000000000400ULL
+ },
+ [ PPC970_PME_PM_LD_REF_L1_LSU1 ] = {
+ 0x0000000000008000ULL
+ },
+ [ PPC970_PME_PM_HV_CYC ] = {
+ 0x0000000020080000ULL
+ },
+ [ PPC970_PME_PM_LR_CTR_MAP_FULL_CYC ] = {
+ 0x0000000000000040ULL
+ },
+ [ PPC970_PME_PM_FPU_DENORM ] = {
+ 0x0000000000000020ULL
+ },
+ [ PPC970_PME_PM_LSU0_REJECT_SRQ ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_LSU1_REJECT_SRQ ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_LSU1_DERAT_MISS ] = {
+ 0x0000000000040000ULL
+ },
+ [ PPC970_PME_PM_IC_PREF_REQ ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_MRK_LSU_FIN ] = {
+ 0x0000000400000000ULL
+ },
+ [ PPC970_PME_PM_MRK_DATA_FROM_MEM ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970_PME_PM_LSU0_FLUSH_UST ] = {
+ 0x0000000000010000ULL
+ },
+ [ PPC970_PME_PM_LSU_FLUSH_LRQ ] = {
+ 0x0000000000000008ULL
+ },
+ [ PPC970_PME_PM_LSU_FLUSH_SRQ ] = {
+ 0x0000000000000008ULL
+ }
+};
+
+static const pme_power_entry_t ppc970_pe[] = {
[ PPC970_PME_PM_LSU_REJECT_RELOAD_CDF ] = {
.pme_name = "PM_LSU_REJECT_RELOAD_CDF",
+ .pme_code = 0x6920,
.pme_short_desc = "LSU reject due to reload CDF or tag update collision",
.pme_long_desc = "LSU reject due to reload CDF or tag update collision",
- .pme_event_ids = { -1, -1, -1, -1, -1, 68, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_REJECT_RELOAD_CDF],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_REJECT_RELOAD_CDF]
},
-#define PPC970_PME_PM_MRK_LSU_SRQ_INST_VALID 1
[ PPC970_PME_PM_MRK_LSU_SRQ_INST_VALID ] = {
.pme_name = "PM_MRK_LSU_SRQ_INST_VALID",
+ .pme_code = 0x936,
.pme_short_desc = "Marked instruction valid in SRQ",
.pme_long_desc = "This signal is asserted every cycle when a marked request is resident in the Store Request Queue",
- .pme_event_ids = { -1, -1, 63, 61, -1, -1, 60, 61 },
- .pme_group_vector = {
- 0x0000000800000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LSU_SRQ_INST_VALID],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LSU_SRQ_INST_VALID]
},
-#define PPC970_PME_PM_FPU1_SINGLE 2
[ PPC970_PME_PM_FPU1_SINGLE ] = {
.pme_name = "PM_FPU1_SINGLE",
+ .pme_code = 0x127,
.pme_short_desc = "FPU1 executed single precision instruction",
.pme_long_desc = "This signal is active for one cycle when fp1 is executing single precision instruction.",
- .pme_event_ids = { 23, 22, -1, -1, 24, 23, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_SINGLE],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_SINGLE]
},
-#define PPC970_PME_PM_FPU0_STALL3 3
[ PPC970_PME_PM_FPU0_STALL3 ] = {
.pme_name = "PM_FPU0_STALL3",
+ .pme_code = 0x121,
.pme_short_desc = "FPU0 stalled in pipe3",
.pme_long_desc = "This signal indicates that fp0 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. ",
- .pme_event_ids = { 15, 14, -1, -1, 16, 15, -1, -1 },
- .pme_group_vector = {
- 0x0000000000002000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_STALL3],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_STALL3]
},
-#define PPC970_PME_PM_TB_BIT_TRANS 4
[ PPC970_PME_PM_TB_BIT_TRANS ] = {
.pme_name = "PM_TB_BIT_TRANS",
+ .pme_code = 0x8005,
.pme_short_desc = "Time Base bit transition",
.pme_long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 ",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 67 },
- .pme_group_vector = {
- 0x0000000000080000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_TB_BIT_TRANS],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_TB_BIT_TRANS]
},
-#define PPC970_PME_PM_GPR_MAP_FULL_CYC 5
[ PPC970_PME_PM_GPR_MAP_FULL_CYC ] = {
.pme_name = "PM_GPR_MAP_FULL_CYC",
+ .pme_code = 0x335,
.pme_short_desc = "Cycles GPR mapper full",
.pme_long_desc = "The ISU sends a signal indicating that the gpr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.",
- .pme_event_ids = { -1, -1, 28, 28, -1, -1, 27, 27 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GPR_MAP_FULL_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GPR_MAP_FULL_CYC]
},
-#define PPC970_PME_PM_MRK_ST_CMPL 6
[ PPC970_PME_PM_MRK_ST_CMPL ] = {
.pme_name = "PM_MRK_ST_CMPL",
+ .pme_code = 0x1003,
.pme_short_desc = "Marked store instruction completed",
.pme_long_desc = "A sampled store has completed (data home)",
- .pme_event_ids = { 79, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_ST_CMPL],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_ST_CMPL]
},
-#define PPC970_PME_PM_FPU0_STF 7
[ PPC970_PME_PM_FPU0_STF ] = {
.pme_name = "PM_FPU0_STF",
+ .pme_code = 0x122,
.pme_short_desc = "FPU0 executed store instruction",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing a store instruction.",
- .pme_event_ids = { 16, 15, -1, -1, 17, 16, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_STF],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_STF]
},
-#define PPC970_PME_PM_FPU1_FMA 8
[ PPC970_PME_PM_FPU1_FMA ] = {
.pme_name = "PM_FPU1_FMA",
+ .pme_code = 0x105,
.pme_short_desc = "FPU1 executed multiply-add instruction",
.pme_long_desc = "This signal is active for one cycle when fp1 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 20, 19, -1, -1, 21, 20, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000400ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_FMA],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_FMA]
},
-#define PPC970_PME_PM_LSU1_FLUSH_ULD 9
[ PPC970_PME_PM_LSU1_FLUSH_ULD ] = {
.pme_name = "PM_LSU1_FLUSH_ULD",
+ .pme_code = 0x804,
.pme_short_desc = "LSU1 unaligned load flushes",
.pme_long_desc = "A load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { 58, 57, -1, -1, 60, 57, -1, -1 },
- .pme_group_vector = {
- 0x0000000000008000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU1_FLUSH_ULD],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU1_FLUSH_ULD]
},
-#define PPC970_PME_PM_MRK_INST_FIN 10
[ PPC970_PME_PM_MRK_INST_FIN ] = {
.pme_name = "PM_MRK_INST_FIN",
+ .pme_code = 0x7005,
.pme_short_desc = "Marked instruction finished",
.pme_long_desc = "One of the execution units finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 50, -1 },
- .pme_group_vector = {
- 0x0000000200000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_INST_FIN],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_INST_FIN]
},
-#define PPC970_PME_PM_MRK_LSU0_FLUSH_UST 11
[ PPC970_PME_PM_MRK_LSU0_FLUSH_UST ] = {
.pme_name = "PM_MRK_LSU0_FLUSH_UST",
+ .pme_code = 0x711,
.pme_short_desc = "LSU0 marked unaligned store flushes",
.pme_long_desc = "A marked store was flushed from unit 0 because it was unaligned",
- .pme_event_ids = { -1, -1, 58, 56, -1, -1, 55, 55 },
- .pme_group_vector = {
- 0x0000001000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LSU0_FLUSH_UST],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LSU0_FLUSH_UST]
},
-#define PPC970_PME_PM_LSU_LRQ_S0_ALLOC 12
[ PPC970_PME_PM_LSU_LRQ_S0_ALLOC ] = {
.pme_name = "PM_LSU_LRQ_S0_ALLOC",
+ .pme_code = 0x826,
.pme_short_desc = "LRQ slot 0 allocated",
.pme_long_desc = "LRQ slot zero was allocated",
- .pme_event_ids = { 66, 66, -1, -1, 68, 66, -1, -1 },
- .pme_group_vector = {
- 0x0000000010000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_LRQ_S0_ALLOC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_LRQ_S0_ALLOC]
},
-#define PPC970_PME_PM_FPU_FDIV 13
[ PPC970_PME_PM_FPU_FDIV ] = {
.pme_name = "PM_FPU_FDIV",
+ .pme_code = 0x1100,
.pme_short_desc = "FPU executed FDIV instruction",
.pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when FPU is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs. Combined Unit 0 + Unit 1",
- .pme_event_ids = { 27, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000900010ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_FDIV],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_FDIV]
},
-#define PPC970_PME_PM_FPU0_FULL_CYC 14
[ PPC970_PME_PM_FPU0_FULL_CYC ] = {
.pme_name = "PM_FPU0_FULL_CYC",
+ .pme_code = 0x303,
.pme_short_desc = "Cycles FPU0 issue queue full",
.pme_long_desc = "The issue queue for FPU unit 0 cannot accept any more instructions. Issue is stopped",
- .pme_event_ids = { 13, 12, -1, -1, 14, 13, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000080ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_FULL_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_FULL_CYC]
},
-#define PPC970_PME_PM_FPU_SINGLE 15
[ PPC970_PME_PM_FPU_SINGLE ] = {
.pme_name = "PM_FPU_SINGLE",
+ .pme_code = 0x5120,
.pme_short_desc = "FPU executed single precision instruction",
.pme_long_desc = "FPU is executing single precision instruction. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, -1, -1, 28, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_SINGLE],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_SINGLE]
},
-#define PPC970_PME_PM_FPU0_FMA 16
[ PPC970_PME_PM_FPU0_FMA ] = {
.pme_name = "PM_FPU0_FMA",
+ .pme_code = 0x101,
.pme_short_desc = "FPU0 executed multiply-add instruction",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 11, 10, -1, -1, 12, 11, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000400ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_FMA],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_FMA]
},
-#define PPC970_PME_PM_MRK_LSU1_FLUSH_ULD 17
[ PPC970_PME_PM_MRK_LSU1_FLUSH_ULD ] = {
.pme_name = "PM_MRK_LSU1_FLUSH_ULD",
+ .pme_code = 0x714,
.pme_short_desc = "LSU1 marked unaligned load flushes",
.pme_long_desc = "A marked load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { -1, -1, 61, 59, -1, -1, 58, 58 },
- .pme_group_vector = {
- 0x0000001000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LSU1_FLUSH_ULD],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LSU1_FLUSH_ULD]
},
-#define PPC970_PME_PM_LSU1_FLUSH_LRQ 18
[ PPC970_PME_PM_LSU1_FLUSH_LRQ ] = {
.pme_name = "PM_LSU1_FLUSH_LRQ",
+ .pme_code = 0x806,
.pme_short_desc = "LSU1 LRQ flushes",
.pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { 56, 55, -1, -1, 58, 55, -1, -1 },
- .pme_group_vector = {
- 0x0000000000004000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU1_FLUSH_LRQ],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU1_FLUSH_LRQ]
},
-#define PPC970_PME_PM_DTLB_MISS 19
[ PPC970_PME_PM_DTLB_MISS ] = {
.pme_name = "PM_DTLB_MISS",
+ .pme_code = 0x704,
.pme_short_desc = "Data TLB misses",
.pme_long_desc = "A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.",
- .pme_event_ids = { 6, 5, -1, -1, 7, 6, -1, -1 },
- .pme_group_vector = {
- 0x0000000010600000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_DTLB_MISS],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_DTLB_MISS]
},
-#define PPC970_PME_PM_MRK_ST_MISS_L1 20
[ PPC970_PME_PM_MRK_ST_MISS_L1 ] = {
.pme_name = "PM_MRK_ST_MISS_L1",
+ .pme_code = 0x723,
.pme_short_desc = "Marked L1 D cache store misses",
.pme_long_desc = "A marked store missed the dcache",
- .pme_event_ids = { 80, 76, -1, -1, 79, 79, -1, -1 },
- .pme_group_vector = {
- 0x0000001000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_ST_MISS_L1],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_ST_MISS_L1]
},
-#define PPC970_PME_PM_EXT_INT 21
[ PPC970_PME_PM_EXT_INT ] = {
.pme_name = "PM_EXT_INT",
+ .pme_code = 0x8002,
.pme_short_desc = "External interrupts",
.pme_long_desc = "An external interrupt occurred",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 10 },
- .pme_group_vector = {
- 0x0000000000000200ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_EXT_INT],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_EXT_INT]
},
-#define PPC970_PME_PM_MRK_LSU1_FLUSH_LRQ 22
[ PPC970_PME_PM_MRK_LSU1_FLUSH_LRQ ] = {
.pme_name = "PM_MRK_LSU1_FLUSH_LRQ",
+ .pme_code = 0x716,
.pme_short_desc = "LSU1 marked LRQ flushes",
.pme_long_desc = "A marked load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { -1, -1, 59, 57, -1, -1, 56, 56 },
- .pme_group_vector = {
- 0x0000002000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LSU1_FLUSH_LRQ],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LSU1_FLUSH_LRQ]
},
-#define PPC970_PME_PM_MRK_ST_GPS 23
[ PPC970_PME_PM_MRK_ST_GPS ] = {
.pme_name = "PM_MRK_ST_GPS",
+ .pme_code = 0x6003,
.pme_short_desc = "Marked store sent to GPS",
.pme_long_desc = "A sampled store has been sent to the memory subsystem",
- .pme_event_ids = { -1, -1, -1, -1, -1, 78, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_ST_GPS],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_ST_GPS]
},
-#define PPC970_PME_PM_GRP_DISP_SUCCESS 24
[ PPC970_PME_PM_GRP_DISP_SUCCESS ] = {
.pme_name = "PM_GRP_DISP_SUCCESS",
+ .pme_code = 0x5001,
.pme_short_desc = "Group dispatch success",
.pme_long_desc = "Number of groups sucessfully dispatched (not rejected)",
- .pme_event_ids = { -1, -1, -1, -1, 34, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GRP_DISP_SUCCESS],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GRP_DISP_SUCCESS]
},
-#define PPC970_PME_PM_LSU1_LDF 25
[ PPC970_PME_PM_LSU1_LDF ] = {
.pme_name = "PM_LSU1_LDF",
+ .pme_code = 0x734,
.pme_short_desc = "LSU1 executed Floating Point load instruction",
.pme_long_desc = "A floating point load was executed from LSU unit 1",
- .pme_event_ids = { -1, -1, 43, 40, -1, -1, 40, 41 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU1_LDF],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU1_LDF]
},
-#define PPC970_PME_PM_LSU0_SRQ_STFWD 26
[ PPC970_PME_PM_LSU0_SRQ_STFWD ] = {
.pme_name = "PM_LSU0_SRQ_STFWD",
+ .pme_code = 0x820,
.pme_short_desc = "LSU0 SRQ store forwarded",
.pme_long_desc = "Data from a store instruction was forwarded to a load on unit 0",
- .pme_event_ids = { 54, 53, -1, -1, 56, 53, -1, -1 },
- .pme_group_vector = {
- 0x0000000000020000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU0_SRQ_STFWD],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU0_SRQ_STFWD]
},
-#define PPC970_PME_PM_CR_MAP_FULL_CYC 27
[ PPC970_PME_PM_CR_MAP_FULL_CYC ] = {
.pme_name = "PM_CR_MAP_FULL_CYC",
+ .pme_code = 0x304,
.pme_short_desc = "Cycles CR logical operation mapper full",
.pme_long_desc = "The ISU sends a signal indicating that the cr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.",
- .pme_event_ids = { 1, 1, -1, -1, 2, 1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000040ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_CR_MAP_FULL_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_CR_MAP_FULL_CYC]
},
-#define PPC970_PME_PM_MRK_LSU0_FLUSH_ULD 28
[ PPC970_PME_PM_MRK_LSU0_FLUSH_ULD ] = {
.pme_name = "PM_MRK_LSU0_FLUSH_ULD",
+ .pme_code = 0x710,
.pme_short_desc = "LSU0 marked unaligned load flushes",
.pme_long_desc = "A marked load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { -1, -1, 57, 55, -1, -1, 54, 54 },
- .pme_group_vector = {
- 0x0000001000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LSU0_FLUSH_ULD],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LSU0_FLUSH_ULD]
},
-#define PPC970_PME_PM_LSU_DERAT_MISS 29
[ PPC970_PME_PM_LSU_DERAT_MISS ] = {
.pme_name = "PM_LSU_DERAT_MISS",
+ .pme_code = 0x6700,
.pme_short_desc = "DERAT misses",
.pme_long_desc = "Total D-ERAT Misses (Unit 0 + Unit 1). Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.",
- .pme_event_ids = { -1, -1, -1, -1, -1, 64, -1, -1 },
- .pme_group_vector = {
- 0x0000000100000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_DERAT_MISS],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_DERAT_MISS]
},
-#define PPC970_PME_PM_FPU0_SINGLE 30
[ PPC970_PME_PM_FPU0_SINGLE ] = {
.pme_name = "PM_FPU0_SINGLE",
+ .pme_code = 0x123,
.pme_short_desc = "FPU0 executed single precision instruction",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing single precision instruction.",
- .pme_event_ids = { 14, 13, -1, -1, 15, 14, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_SINGLE],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_SINGLE]
},
-#define PPC970_PME_PM_FPU1_FDIV 31
[ PPC970_PME_PM_FPU1_FDIV ] = {
.pme_name = "PM_FPU1_FDIV",
+ .pme_code = 0x104,
.pme_short_desc = "FPU1 executed FDIV instruction",
.pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp1 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.",
- .pme_event_ids = { 19, 18, -1, -1, 20, 19, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000400ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_FDIV],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_FDIV]
},
-#define PPC970_PME_PM_FPU1_FEST 32
[ PPC970_PME_PM_FPU1_FEST ] = {
.pme_name = "PM_FPU1_FEST",
+ .pme_code = 0x116,
.pme_short_desc = "FPU1 executed FEST instruction",
.pme_long_desc = "This signal is active for one cycle when fp1 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ",
- .pme_event_ids = { -1, -1, 18, 18, -1, -1, 17, 18 },
- .pme_group_vector = {
- 0x0000000000001000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_FEST],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_FEST]
},
-#define PPC970_PME_PM_FPU0_FRSP_FCONV 33
[ PPC970_PME_PM_FPU0_FRSP_FCONV ] = {
.pme_name = "PM_FPU0_FRSP_FCONV",
+ .pme_code = 0x111,
.pme_short_desc = "FPU0 executed FRSP or FCONV instructions",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { -1, -1, 17, 17, -1, -1, 16, 17 },
- .pme_group_vector = {
- 0x0000000000000400ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_FRSP_FCONV],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_FRSP_FCONV]
},
-#define PPC970_PME_PM_GCT_EMPTY_SRQ_FULL 34
[ PPC970_PME_PM_GCT_EMPTY_SRQ_FULL ] = {
.pme_name = "PM_GCT_EMPTY_SRQ_FULL",
+ .pme_code = 0x200b,
.pme_short_desc = "GCT empty caused by SRQ full",
.pme_long_desc = "GCT empty caused by SRQ full",
- .pme_event_ids = { -1, 27, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GCT_EMPTY_SRQ_FULL],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GCT_EMPTY_SRQ_FULL]
},
-#define PPC970_PME_PM_MRK_ST_CMPL_INT 35
[ PPC970_PME_PM_MRK_ST_CMPL_INT ] = {
.pme_name = "PM_MRK_ST_CMPL_INT",
+ .pme_code = 0x3003,
.pme_short_desc = "Marked store completed with intervention",
.pme_long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention",
- .pme_event_ids = { -1, -1, 64, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_ST_CMPL_INT],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_ST_CMPL_INT]
},
-#define PPC970_PME_PM_FLUSH_BR_MPRED 36
[ PPC970_PME_PM_FLUSH_BR_MPRED ] = {
.pme_name = "PM_FLUSH_BR_MPRED",
+ .pme_code = 0x316,
.pme_short_desc = "Flush caused by branch mispredict",
.pme_long_desc = "Flush caused by branch mispredict",
- .pme_event_ids = { -1, -1, 11, 11, -1, -1, 10, 11 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FLUSH_BR_MPRED],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FLUSH_BR_MPRED]
},
-#define PPC970_PME_PM_FXU_FIN 37
[ PPC970_PME_PM_FXU_FIN ] = {
.pme_name = "PM_FXU_FIN",
+ .pme_code = 0x3330,
.pme_short_desc = "FXU produced a result",
.pme_long_desc = "The fixed point unit (Unit 0 + Unit 1) finished a marked instruction. Instructions that finish may not necessary complete.",
- .pme_event_ids = { -1, -1, 27, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000004000100000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FXU_FIN],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FXU_FIN]
},
-#define PPC970_PME_PM_FPU_STF 38
[ PPC970_PME_PM_FPU_STF ] = {
.pme_name = "PM_FPU_STF",
+ .pme_code = 0x6120,
.pme_short_desc = "FPU executed store instruction",
.pme_long_desc = "FPU is executing a store instruction. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, -1, -1, -1, 27, -1, -1 },
- .pme_group_vector = {
- 0x0000000000800020ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_STF],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_STF]
},
-#define PPC970_PME_PM_DSLB_MISS 39
[ PPC970_PME_PM_DSLB_MISS ] = {
.pme_name = "PM_DSLB_MISS",
+ .pme_code = 0x705,
.pme_short_desc = "Data SLB misses",
.pme_long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve",
- .pme_event_ids = { 5, 4, -1, -1, 6, 5, -1, -1 },
- .pme_group_vector = {
- 0x0000000004000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_DSLB_MISS],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_DSLB_MISS]
},
-#define PPC970_PME_PM_FXLS1_FULL_CYC 40
[ PPC970_PME_PM_FXLS1_FULL_CYC ] = {
.pme_name = "PM_FXLS1_FULL_CYC",
+ .pme_code = 0x314,
.pme_short_desc = "Cycles FXU1/LS1 queue full",
.pme_long_desc = "The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped",
- .pme_event_ids = { -1, -1, 24, 24, -1, -1, 23, 24 },
- .pme_group_vector = {
- 0x0000008000000080ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FXLS1_FULL_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FXLS1_FULL_CYC]
},
-#define PPC970_PME_PM_LSU_LMQ_LHR_MERGE 41
[ PPC970_PME_PM_LSU_LMQ_LHR_MERGE ] = {
.pme_name = "PM_LSU_LMQ_LHR_MERGE",
+ .pme_code = 0x935,
.pme_short_desc = "LMQ LHR merges",
.pme_long_desc = "A dcache miss occured for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.",
- .pme_event_ids = { -1, -1, 46, 43, -1, -1, 43, 45 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_LMQ_LHR_MERGE],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_LMQ_LHR_MERGE]
},
-#define PPC970_PME_PM_MRK_STCX_FAIL 42
[ PPC970_PME_PM_MRK_STCX_FAIL ] = {
.pme_name = "PM_MRK_STCX_FAIL",
+ .pme_code = 0x726,
.pme_short_desc = "Marked STCX failed",
.pme_long_desc = "A marked stcx (stwcx or stdcx) failed",
- .pme_event_ids = { 78, 75, -1, -1, 78, 77, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_STCX_FAIL],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_STCX_FAIL]
},
-#define PPC970_PME_PM_FXU0_BUSY_FXU1_IDLE 43
[ PPC970_PME_PM_FXU0_BUSY_FXU1_IDLE ] = {
.pme_name = "PM_FXU0_BUSY_FXU1_IDLE",
+ .pme_code = 0x7002,
.pme_short_desc = "FXU0 busy FXU1 idle",
.pme_long_desc = "FXU0 is busy while FXU1 was idle",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 24, -1 },
- .pme_group_vector = {
- 0x0000004000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FXU0_BUSY_FXU1_IDLE],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FXU0_BUSY_FXU1_IDLE]
},
-#define PPC970_PME_PM_MRK_DATA_FROM_L25_SHR 44
[ PPC970_PME_PM_MRK_DATA_FROM_L25_SHR ] = {
.pme_name = "PM_MRK_DATA_FROM_L25_SHR",
+ .pme_code = 0x193d,
.pme_short_desc = "Marked data loaded from L2.5 shared",
.pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a marked demand load",
- .pme_event_ids = { -1, -1, -1, -1, 73, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_DATA_FROM_L25_SHR],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_DATA_FROM_L25_SHR]
},
-#define PPC970_PME_PM_LSU_FLUSH_ULD 45
[ PPC970_PME_PM_LSU_FLUSH_ULD ] = {
.pme_name = "PM_LSU_FLUSH_ULD",
+ .pme_code = 0x1800,
.pme_short_desc = "LRQ unaligned load flushes",
.pme_long_desc = "A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { 65, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000008ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_FLUSH_ULD],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_FLUSH_ULD]
},
-#define PPC970_PME_PM_MRK_BRU_FIN 46
[ PPC970_PME_PM_MRK_BRU_FIN ] = {
.pme_name = "PM_MRK_BRU_FIN",
+ .pme_code = 0x2005,
.pme_short_desc = "Marked instruction BRU processing finished",
.pme_long_desc = "The branch unit finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, 71, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000400000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_BRU_FIN],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_BRU_FIN]
},
-#define PPC970_PME_PM_IERAT_XLATE_WR 47
[ PPC970_PME_PM_IERAT_XLATE_WR ] = {
.pme_name = "PM_IERAT_XLATE_WR",
+ .pme_code = 0x430,
.pme_short_desc = "Translation written to ierat",
.pme_long_desc = "This signal will be asserted each time the I-ERAT is written. This indicates that an ERAT miss has been serviced. ERAT misses will initiate a sequence resulting in the ERAT being written. ERAT misses that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed, This should be a fairly accurate count of ERAT missed (best available).",
- .pme_event_ids = { 36, 36, -1, -1, 39, 36, -1, -1 },
- .pme_group_vector = {
- 0x0000000080000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_IERAT_XLATE_WR],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_IERAT_XLATE_WR]
},
-#define PPC970_PME_PM_DATA_FROM_MEM 48
[ PPC970_PME_PM_DATA_FROM_MEM ] = {
.pme_name = "PM_DATA_FROM_MEM",
+ .pme_code = 0x3837,
.pme_short_desc = "Data loaded from memory",
.pme_long_desc = "Data loaded from memory",
- .pme_event_ids = { -1, -1, 5, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000008000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_DATA_FROM_MEM],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_DATA_FROM_MEM]
},
-#define PPC970_PME_PM_FPR_MAP_FULL_CYC 49
[ PPC970_PME_PM_FPR_MAP_FULL_CYC ] = {
.pme_name = "PM_FPR_MAP_FULL_CYC",
+ .pme_code = 0x301,
.pme_short_desc = "Cycles FPR mapper full",
.pme_long_desc = "The ISU sends a signal indicating that the FPR mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.",
- .pme_event_ids = { 7, 6, -1, -1, 8, 7, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPR_MAP_FULL_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPR_MAP_FULL_CYC]
},
-#define PPC970_PME_PM_FPU1_FULL_CYC 50
[ PPC970_PME_PM_FPU1_FULL_CYC ] = {
.pme_name = "PM_FPU1_FULL_CYC",
+ .pme_code = 0x307,
.pme_short_desc = "Cycles FPU1 issue queue full",
.pme_long_desc = "The issue queue for FPU unit 1 cannot accept any more instructions. Issue is stopped",
- .pme_event_ids = { 22, 21, -1, -1, 23, 22, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000080ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_FULL_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_FULL_CYC]
},
-#define PPC970_PME_PM_FPU0_FIN 51
[ PPC970_PME_PM_FPU0_FIN ] = {
.pme_name = "PM_FPU0_FIN",
+ .pme_code = 0x113,
.pme_short_desc = "FPU0 produced a result",
.pme_long_desc = "fp0 finished, produced a result This only indicates finish, not completion. ",
- .pme_event_ids = { -1, -1, 14, 14, -1, -1, 13, 14 },
- .pme_group_vector = {
- 0x0000000000802800ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_FIN],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_FIN]
},
-#define PPC970_PME_PM_GRP_BR_REDIR 52
[ PPC970_PME_PM_GRP_BR_REDIR ] = {
.pme_name = "PM_GRP_BR_REDIR",
+ .pme_code = 0x326,
.pme_short_desc = "Group experienced branch redirect",
.pme_long_desc = "Group experienced branch redirect",
- .pme_event_ids = { 31, 30, -1, -1, 32, 31, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GRP_BR_REDIR],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GRP_BR_REDIR]
},
-#define PPC970_PME_PM_THRESH_TIMEO 53
[ PPC970_PME_PM_THRESH_TIMEO ] = {
.pme_name = "PM_THRESH_TIMEO",
+ .pme_code = 0x2003,
.pme_short_desc = "Threshold timeout",
.pme_long_desc = "The threshold timer expired",
- .pme_event_ids = { -1, 83, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000200000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_THRESH_TIMEO],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_THRESH_TIMEO]
},
-#define PPC970_PME_PM_FPU_FSQRT 54
[ PPC970_PME_PM_FPU_FSQRT ] = {
.pme_name = "PM_FPU_FSQRT",
+ .pme_code = 0x6100,
.pme_short_desc = "FPU executed FSQRT instruction",
.pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when FPU is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, -1, -1, -1, 26, -1, -1 },
- .pme_group_vector = {
- 0x0000000000100010ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_FSQRT],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_FSQRT]
},
-#define PPC970_PME_PM_MRK_LSU0_FLUSH_LRQ 55
[ PPC970_PME_PM_MRK_LSU0_FLUSH_LRQ ] = {
.pme_name = "PM_MRK_LSU0_FLUSH_LRQ",
+ .pme_code = 0x712,
.pme_short_desc = "LSU0 marked LRQ flushes",
.pme_long_desc = "A marked load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { -1, -1, 55, 53, -1, -1, 52, 52 },
- .pme_group_vector = {
- 0x0000002000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LSU0_FLUSH_LRQ],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LSU0_FLUSH_LRQ]
},
-#define PPC970_PME_PM_PMC1_OVERFLOW 56
[ PPC970_PME_PM_PMC1_OVERFLOW ] = {
.pme_name = "PM_PMC1_OVERFLOW",
+ .pme_code = 0x200a,
.pme_short_desc = "PMC1 Overflow",
.pme_long_desc = "PMC1 Overflow",
- .pme_event_ids = { -1, 77, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_PMC1_OVERFLOW],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_PMC1_OVERFLOW]
},
-#define PPC970_PME_PM_FXLS0_FULL_CYC 57
[ PPC970_PME_PM_FXLS0_FULL_CYC ] = {
.pme_name = "PM_FXLS0_FULL_CYC",
+ .pme_code = 0x310,
.pme_short_desc = "Cycles FXU0/LS0 queue full",
.pme_long_desc = "The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped",
- .pme_event_ids = { -1, -1, 23, 23, -1, -1, 22, 23 },
- .pme_group_vector = {
- 0x0000008000000080ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FXLS0_FULL_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FXLS0_FULL_CYC]
},
-#define PPC970_PME_PM_FPU0_ALL 58
[ PPC970_PME_PM_FPU0_ALL ] = {
.pme_name = "PM_FPU0_ALL",
+ .pme_code = 0x103,
.pme_short_desc = "FPU0 executed add",
.pme_long_desc = " mult",
- .pme_event_ids = { 8, 7, -1, -1, 9, 8, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000800ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_ALL],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_ALL]
},
-#define PPC970_PME_PM_DATA_TABLEWALK_CYC 59
[ PPC970_PME_PM_DATA_TABLEWALK_CYC ] = {
.pme_name = "PM_DATA_TABLEWALK_CYC",
+ .pme_code = 0x707,
.pme_short_desc = "Cycles doing data tablewalks",
.pme_long_desc = "This signal is asserted every cycle when a tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.",
- .pme_event_ids = { 4, 3, -1, -1, 5, 4, -1, -1 },
- .pme_group_vector = {
- 0x0000000020000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_DATA_TABLEWALK_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_DATA_TABLEWALK_CYC]
},
-#define PPC970_PME_PM_FPU0_FEST 60
[ PPC970_PME_PM_FPU0_FEST ] = {
.pme_name = "PM_FPU0_FEST",
+ .pme_code = 0x112,
.pme_short_desc = "FPU0 executed FEST instruction",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ",
- .pme_event_ids = { -1, -1, 13, 13, -1, -1, 12, 13 },
- .pme_group_vector = {
- 0x0000000000001000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_FEST],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_FEST]
},
-#define PPC970_PME_PM_DATA_FROM_L25_MOD 61
[ PPC970_PME_PM_DATA_FROM_L25_MOD ] = {
.pme_name = "PM_DATA_FROM_L25_MOD",
+ .pme_code = 0x383d,
.pme_short_desc = "Data loaded from L2.5 modified",
.pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a demand load",
- .pme_event_ids = { -1, -1, -1, -1, -1, 3, -1, -1 },
- .pme_group_vector = {
- 0x0000000008000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_DATA_FROM_L25_MOD],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_DATA_FROM_L25_MOD]
},
-#define PPC970_PME_PM_LSU0_REJECT_ERAT_MISS 62
[ PPC970_PME_PM_LSU0_REJECT_ERAT_MISS ] = {
.pme_name = "PM_LSU0_REJECT_ERAT_MISS",
+ .pme_code = 0x923,
.pme_short_desc = "LSU0 reject due to ERAT miss",
.pme_long_desc = "LSU0 reject due to ERAT miss",
- .pme_event_ids = { 50, 49, -1, -1, 52, 49, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU0_REJECT_ERAT_MISS],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU0_REJECT_ERAT_MISS]
},
-#define PPC970_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 63
[ PPC970_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = {
.pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC",
+ .pme_code = 0x2002,
.pme_short_desc = "Cycles LMQ and SRQ empty",
.pme_long_desc = "Cycles when both the LMQ and SRQ are empty (LSU is idle)",
- .pme_event_ids = { -1, 65, 49, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000480000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC]
},
-#define PPC970_PME_PM_LSU0_REJECT_RELOAD_CDF 64
[ PPC970_PME_PM_LSU0_REJECT_RELOAD_CDF ] = {
.pme_name = "PM_LSU0_REJECT_RELOAD_CDF",
+ .pme_code = 0x922,
.pme_short_desc = "LSU0 reject due to reload CDF or tag update collision",
.pme_long_desc = "LSU0 reject due to reload CDF or tag update collision",
- .pme_event_ids = { 52, 51, -1, -1, 54, 51, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU0_REJECT_RELOAD_CDF],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU0_REJECT_RELOAD_CDF]
},
-#define PPC970_PME_PM_FPU_FEST 65
[ PPC970_PME_PM_FPU_FEST ] = {
.pme_name = "PM_FPU_FEST",
+ .pme_code = 0x3110,
.pme_short_desc = "FPU executed FEST instruction",
.pme_long_desc = "This signal is active for one cycle when executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. Combined Unit 0 + Unit 1.",
- .pme_event_ids = { -1, -1, 22, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000010ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_FEST],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_FEST]
},
-#define PPC970_PME_PM_0INST_FETCH 66
[ PPC970_PME_PM_0INST_FETCH ] = {
.pme_name = "PM_0INST_FETCH",
+ .pme_code = 0x442d,
.pme_short_desc = "No instructions fetched",
.pme_long_desc = "No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)",
- .pme_event_ids = { -1, -1, -1, 0, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000030000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_0INST_FETCH],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_0INST_FETCH]
},
-#define PPC970_PME_PM_LD_MISS_L1_LSU0 67
[ PPC970_PME_PM_LD_MISS_L1_LSU0 ] = {
.pme_name = "PM_LD_MISS_L1_LSU0",
+ .pme_code = 0x812,
.pme_short_desc = "LSU0 L1 D cache load misses",
.pme_long_desc = "A load, executing on unit 0, missed the dcache",
- .pme_event_ids = { -1, -1, 38, 35, -1, -1, 35, 35 },
- .pme_group_vector = {
- 0x0000000000008000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LD_MISS_L1_LSU0],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LD_MISS_L1_LSU0]
},
-#define PPC970_PME_PM_LSU1_REJECT_RELOAD_CDF 68
[ PPC970_PME_PM_LSU1_REJECT_RELOAD_CDF ] = {
.pme_name = "PM_LSU1_REJECT_RELOAD_CDF",
+ .pme_code = 0x926,
.pme_short_desc = "LSU1 reject due to reload CDF or tag update collision",
.pme_long_desc = "LSU1 reject due to reload CDF or tag update collision",
- .pme_event_ids = { 62, 61, -1, -1, 64, 61, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU1_REJECT_RELOAD_CDF],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU1_REJECT_RELOAD_CDF]
},
-#define PPC970_PME_PM_L1_PREF 69
[ PPC970_PME_PM_L1_PREF ] = {
.pme_name = "PM_L1_PREF",
+ .pme_code = 0x731,
.pme_short_desc = "L1 cache data prefetches",
.pme_long_desc = "A request to prefetch data into the L1 was made",
- .pme_event_ids = { -1, -1, 34, 32, -1, -1, 32, 32 },
- .pme_group_vector = {
- 0x0000000010000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_L1_PREF],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_L1_PREF]
},
-#define PPC970_PME_PM_FPU1_STALL3 70
[ PPC970_PME_PM_FPU1_STALL3 ] = {
.pme_name = "PM_FPU1_STALL3",
+ .pme_code = 0x125,
.pme_short_desc = "FPU1 stalled in pipe3",
.pme_long_desc = "This signal indicates that fp1 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. ",
- .pme_event_ids = { 24, 23, -1, -1, 25, 24, -1, -1 },
- .pme_group_vector = {
- 0x0000000000002000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_STALL3],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_STALL3]
},
-#define PPC970_PME_PM_BRQ_FULL_CYC 71
[ PPC970_PME_PM_BRQ_FULL_CYC ] = {
.pme_name = "PM_BRQ_FULL_CYC",
+ .pme_code = 0x305,
.pme_short_desc = "Cycles branch queue full",
.pme_long_desc = "The ISU sends a signal indicating that the issue queue that feeds the ifu br unit cannot accept any more group (queue is full of groups).",
- .pme_event_ids = { 0, 0, -1, -1, 1, 0, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_BRQ_FULL_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_BRQ_FULL_CYC]
},
-#define PPC970_PME_PM_PMC8_OVERFLOW 72
[ PPC970_PME_PM_PMC8_OVERFLOW ] = {
.pme_name = "PM_PMC8_OVERFLOW",
+ .pme_code = 0x100a,
.pme_short_desc = "PMC8 Overflow",
.pme_long_desc = "PMC8 Overflow",
- .pme_event_ids = { 81, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_PMC8_OVERFLOW],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_PMC8_OVERFLOW]
},
-#define PPC970_PME_PM_PMC7_OVERFLOW 73
[ PPC970_PME_PM_PMC7_OVERFLOW ] = {
.pme_name = "PM_PMC7_OVERFLOW",
+ .pme_code = 0x800a,
.pme_short_desc = "PMC7 Overflow",
.pme_long_desc = "PMC7 Overflow",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 62 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_PMC7_OVERFLOW],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_PMC7_OVERFLOW]
},
-#define PPC970_PME_PM_WORK_HELD 74
[ PPC970_PME_PM_WORK_HELD ] = {
.pme_name = "PM_WORK_HELD",
+ .pme_code = 0x2001,
.pme_short_desc = "Work held",
.pme_long_desc = "RAS Unit has signaled completion to stop and there are groups waiting to complete",
- .pme_event_ids = { -1, 84, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000200ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_WORK_HELD],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_WORK_HELD]
},
-#define PPC970_PME_PM_MRK_LD_MISS_L1_LSU0 75
[ PPC970_PME_PM_MRK_LD_MISS_L1_LSU0 ] = {
.pme_name = "PM_MRK_LD_MISS_L1_LSU0",
+ .pme_code = 0x720,
.pme_short_desc = "LSU0 L1 D cache load misses",
.pme_long_desc = "A marked load, executing on unit 0, missed the dcache",
- .pme_event_ids = { 76, 73, -1, -1, 76, 75, -1, -1 },
- .pme_group_vector = {
- 0x0000002000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LD_MISS_L1_LSU0],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LD_MISS_L1_LSU0]
},
-#define PPC970_PME_PM_FXU_IDLE 76
[ PPC970_PME_PM_FXU_IDLE ] = {
.pme_name = "PM_FXU_IDLE",
+ .pme_code = 0x5002,
.pme_short_desc = "FXU idle",
.pme_long_desc = "FXU0 and FXU1 are both idle",
- .pme_event_ids = { -1, -1, -1, -1, 29, -1, -1, -1 },
- .pme_group_vector = {
- 0x000000c000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FXU_IDLE],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FXU_IDLE]
},
-#define PPC970_PME_PM_INST_CMPL 77
[ PPC970_PME_PM_INST_CMPL ] = {
.pme_name = "PM_INST_CMPL",
+ .pme_code = 0x1,
.pme_short_desc = "Instructions completed",
.pme_long_desc = "Number of Eligible Instructions that completed. ",
- .pme_event_ids = { 37, 37, 31, 30, 40, 37, 30, 30 },
- .pme_group_vector = {
- 0x000003fbffffffffULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_INST_CMPL],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_INST_CMPL]
},
-#define PPC970_PME_PM_LSU1_FLUSH_UST 78
[ PPC970_PME_PM_LSU1_FLUSH_UST ] = {
.pme_name = "PM_LSU1_FLUSH_UST",
+ .pme_code = 0x805,
.pme_short_desc = "LSU1 unaligned store flushes",
.pme_long_desc = "A store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)",
- .pme_event_ids = { 59, 58, -1, -1, 61, 58, -1, -1 },
- .pme_group_vector = {
- 0x0000000000010000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU1_FLUSH_UST],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU1_FLUSH_UST]
},
-#define PPC970_PME_PM_LSU0_FLUSH_ULD 79
[ PPC970_PME_PM_LSU0_FLUSH_ULD ] = {
.pme_name = "PM_LSU0_FLUSH_ULD",
+ .pme_code = 0x800,
.pme_short_desc = "LSU0 unaligned load flushes",
.pme_long_desc = "A load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { 48, 47, -1, -1, 50, 47, -1, -1 },
- .pme_group_vector = {
- 0x0000000000008000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU0_FLUSH_ULD],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU0_FLUSH_ULD]
},
-#define PPC970_PME_PM_LSU_FLUSH 80
[ PPC970_PME_PM_LSU_FLUSH ] = {
.pme_name = "PM_LSU_FLUSH",
+ .pme_code = 0x315,
.pme_short_desc = "Flush initiated by LSU",
.pme_long_desc = "Flush initiated by LSU",
- .pme_event_ids = { -1, -1, 44, 41, -1, -1, 41, 42 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_FLUSH],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_FLUSH]
},
-#define PPC970_PME_PM_INST_FROM_L2 81
[ PPC970_PME_PM_INST_FROM_L2 ] = {
.pme_name = "PM_INST_FROM_L2",
+ .pme_code = 0x1426,
.pme_short_desc = "Instructions fetched from L2",
.pme_long_desc = "An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions",
- .pme_event_ids = { 40, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000020020000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_INST_FROM_L2],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_INST_FROM_L2]
},
-#define PPC970_PME_PM_LSU1_REJECT_LMQ_FULL 82
[ PPC970_PME_PM_LSU1_REJECT_LMQ_FULL ] = {
.pme_name = "PM_LSU1_REJECT_LMQ_FULL",
+ .pme_code = 0x925,
.pme_short_desc = "LSU1 reject due to LMQ full or missed data coming",
.pme_long_desc = "LSU1 reject due to LMQ full or missed data coming",
- .pme_event_ids = { 61, 60, -1, -1, 63, 60, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU1_REJECT_LMQ_FULL],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU1_REJECT_LMQ_FULL]
},
-#define PPC970_PME_PM_PMC2_OVERFLOW 83
[ PPC970_PME_PM_PMC2_OVERFLOW ] = {
.pme_name = "PM_PMC2_OVERFLOW",
+ .pme_code = 0x300a,
.pme_short_desc = "PMC2 Overflow",
.pme_long_desc = "PMC2 Overflow",
- .pme_event_ids = { -1, -1, 66, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_PMC2_OVERFLOW],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_PMC2_OVERFLOW]
},
-#define PPC970_PME_PM_FPU0_DENORM 84
[ PPC970_PME_PM_FPU0_DENORM ] = {
.pme_name = "PM_FPU0_DENORM",
+ .pme_code = 0x120,
.pme_short_desc = "FPU0 received denormalized data",
.pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.",
- .pme_event_ids = { 9, 8, -1, -1, 10, 9, -1, -1 },
- .pme_group_vector = {
- 0x0000000000001000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_DENORM],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_DENORM]
},
-#define PPC970_PME_PM_FPU1_FMOV_FEST 85
[ PPC970_PME_PM_FPU1_FMOV_FEST ] = {
.pme_name = "PM_FPU1_FMOV_FEST",
+ .pme_code = 0x114,
.pme_short_desc = "FPU1 executing FMOV or FEST instructions",
.pme_long_desc = "This signal is active for one cycle when fp1 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ",
- .pme_event_ids = { -1, -1, 20, 20, -1, -1, 19, 20 },
- .pme_group_vector = {
- 0x0000000000001000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_FMOV_FEST],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_FMOV_FEST]
},
-#define PPC970_PME_PM_GRP_DISP_REJECT 86
[ PPC970_PME_PM_GRP_DISP_REJECT ] = {
.pme_name = "PM_GRP_DISP_REJECT",
+ .pme_code = 0x324,
.pme_short_desc = "Group dispatch rejected",
.pme_long_desc = "A group that previously attempted dispatch was rejected.",
- .pme_event_ids = { 32, 32, -1, -1, 33, 32, -1, 29 },
- .pme_group_vector = {
- 0x0000000000000101ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GRP_DISP_REJECT],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GRP_DISP_REJECT]
},
-#define PPC970_PME_PM_LSU_LDF 87
[ PPC970_PME_PM_LSU_LDF ] = {
.pme_name = "PM_LSU_LDF",
+ .pme_code = 0x8730,
.pme_short_desc = "LSU executed Floating Point load instruction",
.pme_long_desc = "LSU executed Floating Point load instruction",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 43 },
- .pme_group_vector = {
- 0x0000000000800020ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_LDF],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_LDF]
},
-#define PPC970_PME_PM_INST_DISP 88
[ PPC970_PME_PM_INST_DISP ] = {
.pme_name = "PM_INST_DISP",
+ .pme_code = 0x320,
.pme_short_desc = "Instructions dispatched",
.pme_long_desc = "The ISU sends the number of instructions dispatched.",
- .pme_event_ids = { 38, 38, -1, -1, 41, 38, -1, -1 },
- .pme_group_vector = {
- 0x0000000100000146ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_INST_DISP],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_INST_DISP]
},
-#define PPC970_PME_PM_DATA_FROM_L25_SHR 89
[ PPC970_PME_PM_DATA_FROM_L25_SHR ] = {
.pme_name = "PM_DATA_FROM_L25_SHR",
+ .pme_code = 0x183d,
.pme_short_desc = "Data loaded from L2.5 shared",
.pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a demand load",
- .pme_event_ids = { -1, -1, -1, -1, 4, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000008000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_DATA_FROM_L25_SHR],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_DATA_FROM_L25_SHR]
},
-#define PPC970_PME_PM_L1_DCACHE_RELOAD_VALID 90
[ PPC970_PME_PM_L1_DCACHE_RELOAD_VALID ] = {
.pme_name = "PM_L1_DCACHE_RELOAD_VALID",
+ .pme_code = 0x834,
.pme_short_desc = "L1 reload data source valid",
.pme_long_desc = "The data source information is valid",
- .pme_event_ids = { -1, -1, 33, 31, -1, -1, 31, 31 },
- .pme_group_vector = {
- 0x0000000100040000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_L1_DCACHE_RELOAD_VALID],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_L1_DCACHE_RELOAD_VALID]
},
-#define PPC970_PME_PM_MRK_GRP_ISSUED 91
[ PPC970_PME_PM_MRK_GRP_ISSUED ] = {
.pme_name = "PM_MRK_GRP_ISSUED",
+ .pme_code = 0x6005,
.pme_short_desc = "Marked group issued",
.pme_long_desc = "A sampled instruction was issued",
- .pme_event_ids = { -1, -1, -1, -1, -1, 73, -1, -1 },
- .pme_group_vector = {
- 0x0000000200000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_GRP_ISSUED],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_GRP_ISSUED]
},
-#define PPC970_PME_PM_FPU_FMA 92
[ PPC970_PME_PM_FPU_FMA ] = {
.pme_name = "PM_FPU_FMA",
+ .pme_code = 0x2100,
.pme_short_desc = "FPU executed multiply-add instruction",
.pme_long_desc = "This signal is active for one cycle when FPU is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, 25, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000900010ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_FMA],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_FMA]
},
-#define PPC970_PME_PM_MRK_CRU_FIN 93
[ PPC970_PME_PM_MRK_CRU_FIN ] = {
.pme_name = "PM_MRK_CRU_FIN",
+ .pme_code = 0x4005,
.pme_short_desc = "Marked instruction CRU processing finished",
.pme_long_desc = "The Condition Register Unit finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, -1, -1, 50, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000400000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_CRU_FIN],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_CRU_FIN]
},
-#define PPC970_PME_PM_MRK_LSU1_FLUSH_UST 94
[ PPC970_PME_PM_MRK_LSU1_FLUSH_UST ] = {
.pme_name = "PM_MRK_LSU1_FLUSH_UST",
+ .pme_code = 0x715,
.pme_short_desc = "LSU1 marked unaligned store flushes",
.pme_long_desc = "A marked store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)",
- .pme_event_ids = { -1, -1, 62, 60, -1, -1, 59, 59 },
- .pme_group_vector = {
- 0x0000001000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LSU1_FLUSH_UST],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LSU1_FLUSH_UST]
},
-#define PPC970_PME_PM_MRK_FXU_FIN 95
[ PPC970_PME_PM_MRK_FXU_FIN ] = {
.pme_name = "PM_MRK_FXU_FIN",
+ .pme_code = 0x6004,
.pme_short_desc = "Marked instruction FXU processing finished",
.pme_long_desc = "Marked instruction FXU processing finished",
- .pme_event_ids = { -1, -1, -1, -1, -1, 72, -1, -1 },
- .pme_group_vector = {
- 0x0000000400000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_FXU_FIN],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_FXU_FIN]
},
-#define PPC970_PME_PM_LSU1_REJECT_ERAT_MISS 96
[ PPC970_PME_PM_LSU1_REJECT_ERAT_MISS ] = {
.pme_name = "PM_LSU1_REJECT_ERAT_MISS",
+ .pme_code = 0x927,
.pme_short_desc = "LSU1 reject due to ERAT miss",
.pme_long_desc = "LSU1 reject due to ERAT miss",
- .pme_event_ids = { 60, 59, -1, -1, 62, 59, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU1_REJECT_ERAT_MISS],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU1_REJECT_ERAT_MISS]
},
-#define PPC970_PME_PM_BR_ISSUED 97
[ PPC970_PME_PM_BR_ISSUED ] = {
.pme_name = "PM_BR_ISSUED",
+ .pme_code = 0x431,
.pme_short_desc = "Branches issued",
.pme_long_desc = "This signal will be asserted each time the ISU issues a branch instruction. This signal will be asserted each time the ISU selects a branch instruction to issue.",
- .pme_event_ids = { -1, -1, 0, 1, -1, -1, 0, 0 },
- .pme_group_vector = {
- 0x0000000007000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_BR_ISSUED],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_BR_ISSUED]
},
-#define PPC970_PME_PM_PMC4_OVERFLOW 98
[ PPC970_PME_PM_PMC4_OVERFLOW ] = {
.pme_name = "PM_PMC4_OVERFLOW",
+ .pme_code = 0x500a,
.pme_short_desc = "PMC4 Overflow",
.pme_long_desc = "PMC4 Overflow",
- .pme_event_ids = { -1, -1, -1, -1, 80, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_PMC4_OVERFLOW],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_PMC4_OVERFLOW]
},
-#define PPC970_PME_PM_EE_OFF 99
[ PPC970_PME_PM_EE_OFF ] = {
.pme_name = "PM_EE_OFF",
+ .pme_code = 0x333,
.pme_short_desc = "Cycles MSR(EE) bit off",
.pme_long_desc = "The number of Cycles MSR(EE) bit was off.",
- .pme_event_ids = { -1, -1, 9, 9, -1, -1, 8, 8 },
- .pme_group_vector = {
- 0x0000000000000200ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_EE_OFF],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_EE_OFF]
},
-#define PPC970_PME_PM_INST_FROM_L25_MOD 100
[ PPC970_PME_PM_INST_FROM_L25_MOD ] = {
.pme_name = "PM_INST_FROM_L25_MOD",
+ .pme_code = 0x6426,
.pme_short_desc = "Instruction fetched from L2.5 modified",
.pme_long_desc = "Instruction fetched from L2.5 modified",
- .pme_event_ids = { -1, -1, -1, -1, -1, 39, -1, -1 },
- .pme_group_vector = {
- 0x0000020000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_INST_FROM_L25_MOD],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_INST_FROM_L25_MOD]
},
-#define PPC970_PME_PM_ITLB_MISS 101
[ PPC970_PME_PM_ITLB_MISS ] = {
.pme_name = "PM_ITLB_MISS",
+ .pme_code = 0x700,
.pme_short_desc = "Instruction TLB misses",
.pme_long_desc = "A TLB miss for an Instruction Fetch has occurred",
- .pme_event_ids = { 42, 41, -1, -1, 44, 41, -1, -1 },
- .pme_group_vector = {
- 0x0000000010200000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_ITLB_MISS],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_ITLB_MISS]
},
-#define PPC970_PME_PM_FXU1_BUSY_FXU0_IDLE 102
[ PPC970_PME_PM_FXU1_BUSY_FXU0_IDLE ] = {
.pme_name = "PM_FXU1_BUSY_FXU0_IDLE",
+ .pme_code = 0x4002,
.pme_short_desc = "FXU1 busy FXU0 idle",
.pme_long_desc = "FXU0 was idle while FXU1 was busy",
- .pme_event_ids = { -1, -1, -1, 26, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000004000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FXU1_BUSY_FXU0_IDLE],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FXU1_BUSY_FXU0_IDLE]
},
-#define PPC970_PME_PM_GRP_DISP_VALID 103
[ PPC970_PME_PM_GRP_DISP_VALID ] = {
.pme_name = "PM_GRP_DISP_VALID",
+ .pme_code = 0x323,
.pme_short_desc = "Group dispatch valid",
.pme_long_desc = "Dispatch has been attempted for a valid group. Some groups may be rejected. The total number of successful dispatches is the number of dispatch valid minus dispatch reject.",
- .pme_event_ids = { 33, 33, -1, -1, 35, 33, -1, -1 },
- .pme_group_vector = {
- 0x0000000100000100ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GRP_DISP_VALID],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GRP_DISP_VALID]
},
-#define PPC970_PME_PM_MRK_GRP_DISP 104
[ PPC970_PME_PM_MRK_GRP_DISP ] = {
.pme_name = "PM_MRK_GRP_DISP",
+ .pme_code = 0x1002,
.pme_short_desc = "Marked group dispatched",
.pme_long_desc = "A group containing a sampled instruction was dispatched",
- .pme_event_ids = { 73, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000400000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_GRP_DISP],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_GRP_DISP]
},
-#define PPC970_PME_PM_LSU_FLUSH_UST 105
[ PPC970_PME_PM_LSU_FLUSH_UST ] = {
.pme_name = "PM_LSU_FLUSH_UST",
+ .pme_code = 0x2800,
.pme_short_desc = "SRQ unaligned store flushes",
.pme_long_desc = "A store was flushed because it was unaligned",
- .pme_event_ids = { -1, 64, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000008ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_FLUSH_UST],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_FLUSH_UST]
},
-#define PPC970_PME_PM_FXU1_FIN 106
[ PPC970_PME_PM_FXU1_FIN ] = {
.pme_name = "PM_FXU1_FIN",
+ .pme_code = 0x336,
.pme_short_desc = "FXU1 produced a result",
.pme_long_desc = "The Fixed Point unit 1 finished an instruction and produced a result",
- .pme_event_ids = { -1, -1, 26, 27, -1, -1, 26, 26 },
- .pme_group_vector = {
- 0x0000008000000100ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FXU1_FIN],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FXU1_FIN]
},
-#define PPC970_PME_PM_GRP_CMPL 107
[ PPC970_PME_PM_GRP_CMPL ] = {
.pme_name = "PM_GRP_CMPL",
+ .pme_code = 0x7003,
.pme_short_desc = "Group completed",
.pme_long_desc = "A group completed. Microcoded instructions that span multiple groups will generate this event once per group.",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 28, -1 },
- .pme_group_vector = {
- 0x0000000020080001ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GRP_CMPL],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GRP_CMPL]
},
-#define PPC970_PME_PM_FPU_FRSP_FCONV 108
[ PPC970_PME_PM_FPU_FRSP_FCONV ] = {
.pme_name = "PM_FPU_FRSP_FCONV",
+ .pme_code = 0x7110,
.pme_short_desc = "FPU executed FRSP or FCONV instructions",
.pme_long_desc = "This signal is active for one cycle when executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 21, -1 },
- .pme_group_vector = {
- 0x0000000000000020ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_FRSP_FCONV],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_FRSP_FCONV]
},
-#define PPC970_PME_PM_MRK_LSU0_FLUSH_SRQ 109
[ PPC970_PME_PM_MRK_LSU0_FLUSH_SRQ ] = {
.pme_name = "PM_MRK_LSU0_FLUSH_SRQ",
+ .pme_code = 0x713,
.pme_short_desc = "LSU0 marked SRQ flushes",
.pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { -1, -1, 56, 54, -1, -1, 53, 53 },
- .pme_group_vector = {
- 0x0000002000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LSU0_FLUSH_SRQ],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LSU0_FLUSH_SRQ]
},
-#define PPC970_PME_PM_LSU_LMQ_FULL_CYC 110
[ PPC970_PME_PM_LSU_LMQ_FULL_CYC ] = {
.pme_name = "PM_LSU_LMQ_FULL_CYC",
+ .pme_code = 0x837,
.pme_short_desc = "Cycles LMQ full",
.pme_long_desc = "The LMQ was full",
- .pme_event_ids = { -1, -1, 45, 42, -1, -1, 42, 44 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_LMQ_FULL_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_LMQ_FULL_CYC]
},
-#define PPC970_PME_PM_ST_REF_L1_LSU0 111
[ PPC970_PME_PM_ST_REF_L1_LSU0 ] = {
.pme_name = "PM_ST_REF_L1_LSU0",
+ .pme_code = 0x811,
.pme_short_desc = "LSU0 L1 D cache store references",
.pme_long_desc = "A store executed on unit 0",
- .pme_event_ids = { -1, -1, 69, 64, -1, -1, 64, 64 },
- .pme_group_vector = {
- 0x0000000000030000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_ST_REF_L1_LSU0],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_ST_REF_L1_LSU0]
},
-#define PPC970_PME_PM_LSU0_DERAT_MISS 112
[ PPC970_PME_PM_LSU0_DERAT_MISS ] = {
.pme_name = "PM_LSU0_DERAT_MISS",
+ .pme_code = 0x702,
.pme_short_desc = "LSU0 DERAT misses",
.pme_long_desc = "A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.",
- .pme_event_ids = { 45, 44, -1, -1, 47, 44, -1, -1 },
- .pme_group_vector = {
- 0x0000000000040000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU0_DERAT_MISS],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU0_DERAT_MISS]
},
-#define PPC970_PME_PM_LSU_SRQ_SYNC_CYC 113
[ PPC970_PME_PM_LSU_SRQ_SYNC_CYC ] = {
.pme_name = "PM_LSU_SRQ_SYNC_CYC",
+ .pme_code = 0x735,
.pme_short_desc = "SRQ sync duration",
.pme_long_desc = "This signal is asserted every cycle when a sync is in the SRQ.",
- .pme_event_ids = { -1, -1, 52, 49, -1, -1, 48, 50 },
- .pme_group_vector = {
- 0x0000000040000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_SRQ_SYNC_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_SRQ_SYNC_CYC]
},
-#define PPC970_PME_PM_FPU_STALL3 114
[ PPC970_PME_PM_FPU_STALL3 ] = {
.pme_name = "PM_FPU_STALL3",
+ .pme_code = 0x2120,
.pme_short_desc = "FPU stalled in pipe3",
.pme_long_desc = "FPU has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, 26, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000020ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_STALL3],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_STALL3]
},
-#define PPC970_PME_PM_LSU_REJECT_ERAT_MISS 115
[ PPC970_PME_PM_LSU_REJECT_ERAT_MISS ] = {
.pme_name = "PM_LSU_REJECT_ERAT_MISS",
+ .pme_code = 0x5920,
.pme_short_desc = "LSU reject due to ERAT miss",
.pme_long_desc = "LSU reject due to ERAT miss",
- .pme_event_ids = { -1, -1, -1, -1, 70, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_REJECT_ERAT_MISS],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_REJECT_ERAT_MISS]
},
-#define PPC970_PME_PM_MRK_DATA_FROM_L2 116
[ PPC970_PME_PM_MRK_DATA_FROM_L2 ] = {
.pme_name = "PM_MRK_DATA_FROM_L2",
+ .pme_code = 0x1937,
.pme_short_desc = "Marked data loaded from L2",
.pme_long_desc = "DL1 was reloaded from the local L2 due to a marked demand load",
- .pme_event_ids = { 72, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_DATA_FROM_L2],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_DATA_FROM_L2]
},
-#define PPC970_PME_PM_LSU0_FLUSH_SRQ 117
[ PPC970_PME_PM_LSU0_FLUSH_SRQ ] = {
.pme_name = "PM_LSU0_FLUSH_SRQ",
+ .pme_code = 0x803,
.pme_short_desc = "LSU0 SRQ flushes",
.pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { 47, 46, -1, -1, 49, 46, -1, -1 },
- .pme_group_vector = {
- 0x0000000000004000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU0_FLUSH_SRQ],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU0_FLUSH_SRQ]
},
-#define PPC970_PME_PM_FPU0_FMOV_FEST 118
[ PPC970_PME_PM_FPU0_FMOV_FEST ] = {
.pme_name = "PM_FPU0_FMOV_FEST",
+ .pme_code = 0x110,
.pme_short_desc = "FPU0 executed FMOV or FEST instructions",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ",
- .pme_event_ids = { -1, -1, 15, 15, -1, -1, 14, 15 },
- .pme_group_vector = {
- 0x0000000000001000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_FMOV_FEST],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_FMOV_FEST]
},
-#define PPC970_PME_PM_LD_REF_L1_LSU0 119
[ PPC970_PME_PM_LD_REF_L1_LSU0 ] = {
.pme_name = "PM_LD_REF_L1_LSU0",
+ .pme_code = 0x810,
.pme_short_desc = "LSU0 L1 D cache load references",
.pme_long_desc = "A load executed on unit 0",
- .pme_event_ids = { -1, -1, 40, 37, -1, -1, 37, 38 },
- .pme_group_vector = {
- 0x0000000000008000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LD_REF_L1_LSU0],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LD_REF_L1_LSU0]
},
-#define PPC970_PME_PM_LSU1_FLUSH_SRQ 120
[ PPC970_PME_PM_LSU1_FLUSH_SRQ ] = {
.pme_name = "PM_LSU1_FLUSH_SRQ",
+ .pme_code = 0x807,
.pme_short_desc = "LSU1 SRQ flushes",
.pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. ",
- .pme_event_ids = { 57, 56, -1, -1, 59, 56, -1, -1 },
- .pme_group_vector = {
- 0x0000000000004000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU1_FLUSH_SRQ],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU1_FLUSH_SRQ]
},
-#define PPC970_PME_PM_GRP_BR_MPRED 121
[ PPC970_PME_PM_GRP_BR_MPRED ] = {
.pme_name = "PM_GRP_BR_MPRED",
+ .pme_code = 0x327,
.pme_short_desc = "Group experienced a branch mispredict",
.pme_long_desc = "Group experienced a branch mispredict",
- .pme_event_ids = { 30, 29, -1, -1, 31, 30, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GRP_BR_MPRED],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GRP_BR_MPRED]
},
-#define PPC970_PME_PM_LSU_LMQ_S0_ALLOC 122
[ PPC970_PME_PM_LSU_LMQ_S0_ALLOC ] = {
.pme_name = "PM_LSU_LMQ_S0_ALLOC",
+ .pme_code = 0x836,
.pme_short_desc = "LMQ slot 0 allocated",
.pme_long_desc = "The first entry in the LMQ was allocated.",
- .pme_event_ids = { -1, -1, 47, 44, -1, -1, 44, 46 },
- .pme_group_vector = {
- 0x0000000008000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_LMQ_S0_ALLOC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_LMQ_S0_ALLOC]
},
-#define PPC970_PME_PM_LSU0_REJECT_LMQ_FULL 123
[ PPC970_PME_PM_LSU0_REJECT_LMQ_FULL ] = {
.pme_name = "PM_LSU0_REJECT_LMQ_FULL",
+ .pme_code = 0x921,
.pme_short_desc = "LSU0 reject due to LMQ full or missed data coming",
.pme_long_desc = "LSU0 reject due to LMQ full or missed data coming",
- .pme_event_ids = { 51, 50, -1, -1, 53, 50, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU0_REJECT_LMQ_FULL],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU0_REJECT_LMQ_FULL]
},
-#define PPC970_PME_PM_ST_REF_L1 124
[ PPC970_PME_PM_ST_REF_L1 ] = {
.pme_name = "PM_ST_REF_L1",
+ .pme_code = 0x7810,
.pme_short_desc = "L1 D cache store references",
.pme_long_desc = "Total DL1 Store references",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 63, -1 },
- .pme_group_vector = {
- 0x000000010260000eULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_ST_REF_L1],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_ST_REF_L1]
},
-#define PPC970_PME_PM_MRK_VMX_FIN 125
[ PPC970_PME_PM_MRK_VMX_FIN ] = {
.pme_name = "PM_MRK_VMX_FIN",
+ .pme_code = 0x3005,
.pme_short_desc = "Marked instruction VMX processing finished",
.pme_long_desc = "Marked instruction VMX processing finished",
- .pme_event_ids = { -1, -1, 65, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_VMX_FIN],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_VMX_FIN]
},
-#define PPC970_PME_PM_LSU_SRQ_EMPTY_CYC 126
[ PPC970_PME_PM_LSU_SRQ_EMPTY_CYC ] = {
.pme_name = "PM_LSU_SRQ_EMPTY_CYC",
+ .pme_code = 0x4003,
.pme_short_desc = "Cycles SRQ empty",
.pme_long_desc = "The Store Request Queue is empty",
- .pme_event_ids = { -1, -1, -1, 47, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_SRQ_EMPTY_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_SRQ_EMPTY_CYC]
},
-#define PPC970_PME_PM_FPU1_STF 127
[ PPC970_PME_PM_FPU1_STF ] = {
.pme_name = "PM_FPU1_STF",
+ .pme_code = 0x126,
.pme_short_desc = "FPU1 executed store instruction",
.pme_long_desc = "This signal is active for one cycle when fp1 is executing a store instruction.",
- .pme_event_ids = { 25, 24, -1, -1, 26, 25, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_STF],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_STF]
},
-#define PPC970_PME_PM_RUN_CYC 128
[ PPC970_PME_PM_RUN_CYC ] = {
.pme_name = "PM_RUN_CYC",
+ .pme_code = 0x1005,
.pme_short_desc = "Run cycles",
.pme_long_desc = "Processor Cycles gated by the run latch",
- .pme_event_ids = { 82, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000004000001ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_RUN_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_RUN_CYC]
},
-#define PPC970_PME_PM_LSU_LMQ_S0_VALID 129
[ PPC970_PME_PM_LSU_LMQ_S0_VALID ] = {
.pme_name = "PM_LSU_LMQ_S0_VALID",
+ .pme_code = 0x835,
.pme_short_desc = "LMQ slot 0 valid",
.pme_long_desc = "This signal is asserted every cycle when the first entry in the LMQ is valid. The LMQ had eight entries that are allocated FIFO",
- .pme_event_ids = { -1, -1, 48, 45, -1, -1, 45, 47 },
- .pme_group_vector = {
- 0x0000000008000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_LMQ_S0_VALID],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_LMQ_S0_VALID]
},
-#define PPC970_PME_PM_LSU0_LDF 130
[ PPC970_PME_PM_LSU0_LDF ] = {
.pme_name = "PM_LSU0_LDF",
+ .pme_code = 0x730,
.pme_short_desc = "LSU0 executed Floating Point load instruction",
.pme_long_desc = "A floating point load was executed from LSU unit 0",
- .pme_event_ids = { -1, -1, 42, 39, -1, -1, 39, 40 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU0_LDF],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU0_LDF]
},
-#define PPC970_PME_PM_LSU_LRQ_S0_VALID 131
[ PPC970_PME_PM_LSU_LRQ_S0_VALID ] = {
.pme_name = "PM_LSU_LRQ_S0_VALID",
+ .pme_code = 0x822,
.pme_short_desc = "LRQ slot 0 valid",
.pme_long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.",
- .pme_event_ids = { 67, 67, -1, -1, 69, 67, -1, -1 },
- .pme_group_vector = {
- 0x0000000010000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_LRQ_S0_VALID],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_LRQ_S0_VALID]
},
-#define PPC970_PME_PM_PMC3_OVERFLOW 132
[ PPC970_PME_PM_PMC3_OVERFLOW ] = {
.pme_name = "PM_PMC3_OVERFLOW",
+ .pme_code = 0x400a,
.pme_short_desc = "PMC3 Overflow",
.pme_long_desc = "PMC3 Overflow",
- .pme_event_ids = { -1, -1, -1, 62, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_PMC3_OVERFLOW],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_PMC3_OVERFLOW]
},
-#define PPC970_PME_PM_MRK_IMR_RELOAD 133
[ PPC970_PME_PM_MRK_IMR_RELOAD ] = {
.pme_name = "PM_MRK_IMR_RELOAD",
+ .pme_code = 0x722,
.pme_short_desc = "Marked IMR reloaded",
.pme_long_desc = "A DL1 reload occured due to marked load",
- .pme_event_ids = { 74, 72, -1, -1, 75, 74, -1, -1 },
- .pme_group_vector = {
- 0x0000001000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_IMR_RELOAD],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_IMR_RELOAD]
},
-#define PPC970_PME_PM_MRK_GRP_TIMEO 134
[ PPC970_PME_PM_MRK_GRP_TIMEO ] = {
.pme_name = "PM_MRK_GRP_TIMEO",
+ .pme_code = 0x5005,
.pme_short_desc = "Marked group completion timeout",
.pme_long_desc = "The sampling timeout expired indicating that the previously sampled instruction is no longer in the processor",
- .pme_event_ids = { -1, -1, -1, -1, 74, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_GRP_TIMEO],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_GRP_TIMEO]
},
-#define PPC970_PME_PM_FPU_FMOV_FEST 135
[ PPC970_PME_PM_FPU_FMOV_FEST ] = {
.pme_name = "PM_FPU_FMOV_FEST",
+ .pme_code = 0x8110,
.pme_short_desc = "FPU executing FMOV or FEST instructions",
.pme_long_desc = "This signal is active for one cycle when executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ . Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 22 },
- .pme_group_vector = {
- 0x0000000000100010ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_FMOV_FEST],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_FMOV_FEST]
},
-#define PPC970_PME_PM_GRP_DISP_BLK_SB_CYC 136
[ PPC970_PME_PM_GRP_DISP_BLK_SB_CYC ] = {
.pme_name = "PM_GRP_DISP_BLK_SB_CYC",
+ .pme_code = 0x331,
.pme_short_desc = "Cycles group dispatch blocked by scoreboard",
.pme_long_desc = "The ISU sends a signal indicating that dispatch is blocked by scoreboard.",
- .pme_event_ids = { -1, -1, 29, 29, -1, -1, 29, 28 },
- .pme_group_vector = {
- 0x0000000000000040ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GRP_DISP_BLK_SB_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GRP_DISP_BLK_SB_CYC]
},
-#define PPC970_PME_PM_XER_MAP_FULL_CYC 137
[ PPC970_PME_PM_XER_MAP_FULL_CYC ] = {
.pme_name = "PM_XER_MAP_FULL_CYC",
+ .pme_code = 0x302,
.pme_short_desc = "Cycles XER mapper full",
.pme_long_desc = "The ISU sends a signal indicating that the xer mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.",
- .pme_event_ids = { 88, 85, -1, -1, 86, 86, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000040ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_XER_MAP_FULL_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_XER_MAP_FULL_CYC]
},
-#define PPC970_PME_PM_ST_MISS_L1 138
[ PPC970_PME_PM_ST_MISS_L1 ] = {
.pme_name = "PM_ST_MISS_L1",
+ .pme_code = 0x813,
.pme_short_desc = "L1 D cache store misses",
.pme_long_desc = "A store missed the dcache",
- .pme_event_ids = { 86, 81, 68, 63, 84, 84, 62, 63 },
- .pme_group_vector = {
- 0x0000000003630000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_ST_MISS_L1],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_ST_MISS_L1]
},
-#define PPC970_PME_PM_STOP_COMPLETION 139
[ PPC970_PME_PM_STOP_COMPLETION ] = {
.pme_name = "PM_STOP_COMPLETION",
+ .pme_code = 0x3001,
.pme_short_desc = "Completion stopped",
.pme_long_desc = "RAS Unit has signaled completion to stop",
- .pme_event_ids = { -1, -1, 67, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000201ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_STOP_COMPLETION],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_STOP_COMPLETION]
},
-#define PPC970_PME_PM_MRK_GRP_CMPL 140
[ PPC970_PME_PM_MRK_GRP_CMPL ] = {
.pme_name = "PM_MRK_GRP_CMPL",
+ .pme_code = 0x4004,
.pme_short_desc = "Marked group completed",
.pme_long_desc = "A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group.",
- .pme_event_ids = { -1, -1, -1, 51, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000a00000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_GRP_CMPL],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_GRP_CMPL]
},
-#define PPC970_PME_PM_ISLB_MISS 141
[ PPC970_PME_PM_ISLB_MISS ] = {
.pme_name = "PM_ISLB_MISS",
+ .pme_code = 0x701,
.pme_short_desc = "Instruction SLB misses",
.pme_long_desc = "A SLB miss for an instruction fetch as occurred",
- .pme_event_ids = { 41, 40, -1, -1, 43, 40, -1, -1 },
- .pme_group_vector = {
- 0x0000000004000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_ISLB_MISS],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_ISLB_MISS]
},
-#define PPC970_PME_PM_SUSPENDED 142
[ PPC970_PME_PM_SUSPENDED ] = {
.pme_name = "PM_SUSPENDED",
+ .pme_code = 0x0,
.pme_short_desc = "Suspended",
.pme_long_desc = "Suspended",
- .pme_event_ids = { 87, 82, 71, 66, 85, 85, 66, 66 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_SUSPENDED],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_SUSPENDED]
},
-#define PPC970_PME_PM_CYC 143
[ PPC970_PME_PM_CYC ] = {
.pme_name = "PM_CYC",
+ .pme_code = 0x7,
.pme_short_desc = "Processor cycles",
.pme_long_desc = "Processor cycles",
- .pme_event_ids = { 2, 2, 4, 5, 3, 2, 4, 4 },
- .pme_group_vector = {
- 0x000003ffffffffffULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_CYC]
},
-#define PPC970_PME_PM_LD_MISS_L1_LSU1 144
[ PPC970_PME_PM_LD_MISS_L1_LSU1 ] = {
.pme_name = "PM_LD_MISS_L1_LSU1",
+ .pme_code = 0x816,
.pme_short_desc = "LSU1 L1 D cache load misses",
.pme_long_desc = "A load, executing on unit 1, missed the dcache",
- .pme_event_ids = { -1, -1, 39, 36, -1, -1, 36, 36 },
- .pme_group_vector = {
- 0x0000000000008000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LD_MISS_L1_LSU1],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LD_MISS_L1_LSU1]
},
-#define PPC970_PME_PM_STCX_FAIL 145
[ PPC970_PME_PM_STCX_FAIL ] = {
.pme_name = "PM_STCX_FAIL",
+ .pme_code = 0x721,
.pme_short_desc = "STCX failed",
.pme_long_desc = "A stcx (stwcx or stdcx) failed",
- .pme_event_ids = { 84, 79, -1, -1, 82, 82, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_STCX_FAIL],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_STCX_FAIL]
},
-#define PPC970_PME_PM_LSU1_SRQ_STFWD 146
[ PPC970_PME_PM_LSU1_SRQ_STFWD ] = {
.pme_name = "PM_LSU1_SRQ_STFWD",
+ .pme_code = 0x824,
.pme_short_desc = "LSU1 SRQ store forwarded",
.pme_long_desc = "Data from a store instruction was forwarded to a load on unit 1",
- .pme_event_ids = { 64, 63, -1, -1, 66, 63, -1, -1 },
- .pme_group_vector = {
- 0x0000000000020000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU1_SRQ_STFWD],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU1_SRQ_STFWD]
},
-#define PPC970_PME_PM_GRP_DISP 147
[ PPC970_PME_PM_GRP_DISP ] = {
.pme_name = "PM_GRP_DISP",
+ .pme_code = 0x2004,
.pme_short_desc = "Group dispatches",
.pme_long_desc = "A group was dispatched",
- .pme_event_ids = { -1, 31, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GRP_DISP],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GRP_DISP]
},
-#define PPC970_PME_PM_L2_PREF 148
[ PPC970_PME_PM_L2_PREF ] = {
.pme_name = "PM_L2_PREF",
+ .pme_code = 0x733,
.pme_short_desc = "L2 cache prefetches",
.pme_long_desc = "A request to prefetch data into L2 was made",
- .pme_event_ids = { -1, -1, 36, 34, -1, -1, 34, 34 },
- .pme_group_vector = {
- 0x0000000010000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_L2_PREF],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_L2_PREF]
},
-#define PPC970_PME_PM_FPU1_DENORM 149
[ PPC970_PME_PM_FPU1_DENORM ] = {
.pme_name = "PM_FPU1_DENORM",
+ .pme_code = 0x124,
.pme_short_desc = "FPU1 received denormalized data",
.pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.",
- .pme_event_ids = { 18, 17, -1, -1, 19, 18, -1, -1 },
- .pme_group_vector = {
- 0x0000000000001000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_DENORM],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_DENORM]
},
-#define PPC970_PME_PM_DATA_FROM_L2 150
[ PPC970_PME_PM_DATA_FROM_L2 ] = {
.pme_name = "PM_DATA_FROM_L2",
+ .pme_code = 0x1837,
.pme_short_desc = "Data loaded from L2",
.pme_long_desc = "DL1 was reloaded from the local L2 due to a demand load",
- .pme_event_ids = { 3, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000008000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_DATA_FROM_L2],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_DATA_FROM_L2]
},
-#define PPC970_PME_PM_FPU0_FPSCR 151
[ PPC970_PME_PM_FPU0_FPSCR ] = {
.pme_name = "PM_FPU0_FPSCR",
+ .pme_code = 0x130,
.pme_short_desc = "FPU0 executed FPSCR instruction",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing fpscr move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*. mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs",
- .pme_event_ids = { -1, -1, 16, 16, -1, -1, 15, 16 },
- .pme_group_vector = {
- 0x0000000000002000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_FPSCR],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_FPSCR]
},
-#define PPC970_PME_PM_MRK_DATA_FROM_L25_MOD 152
[ PPC970_PME_PM_MRK_DATA_FROM_L25_MOD ] = {
.pme_name = "PM_MRK_DATA_FROM_L25_MOD",
+ .pme_code = 0x393d,
.pme_short_desc = "Marked data loaded from L2.5 modified",
.pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a marked demand load",
- .pme_event_ids = { -1, -1, -1, -1, -1, 71, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_DATA_FROM_L25_MOD],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_DATA_FROM_L25_MOD]
},
-#define PPC970_PME_PM_FPU0_FSQRT 153
[ PPC970_PME_PM_FPU0_FSQRT ] = {
.pme_name = "PM_FPU0_FSQRT",
+ .pme_code = 0x102,
.pme_short_desc = "FPU0 executed FSQRT instruction",
.pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp0 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 12, 11, -1, -1, 13, 12, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000800ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_FSQRT],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_FSQRT]
},
-#define PPC970_PME_PM_LD_REF_L1 154
[ PPC970_PME_PM_LD_REF_L1 ] = {
.pme_name = "PM_LD_REF_L1",
+ .pme_code = 0x8810,
.pme_short_desc = "L1 D cache load references",
.pme_long_desc = "Total DL1 Load references",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 37 },
- .pme_group_vector = {
- 0x000000004260000eULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LD_REF_L1],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LD_REF_L1]
},
-#define PPC970_PME_PM_MRK_L1_RELOAD_VALID 155
[ PPC970_PME_PM_MRK_L1_RELOAD_VALID ] = {
.pme_name = "PM_MRK_L1_RELOAD_VALID",
+ .pme_code = 0x934,
.pme_short_desc = "Marked L1 reload data source valid",
.pme_long_desc = "The source information is valid and is for a marked load",
- .pme_event_ids = { -1, -1, 54, 52, -1, -1, 51, 51 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_L1_RELOAD_VALID],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_L1_RELOAD_VALID]
},
-#define PPC970_PME_PM_1PLUS_PPC_CMPL 156
[ PPC970_PME_PM_1PLUS_PPC_CMPL ] = {
.pme_name = "PM_1PLUS_PPC_CMPL",
+ .pme_code = 0x5003,
.pme_short_desc = "One or more PPC instruction completed",
.pme_long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.",
- .pme_event_ids = { -1, -1, -1, -1, 0, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000080001ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_1PLUS_PPC_CMPL],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_1PLUS_PPC_CMPL]
},
-#define PPC970_PME_PM_INST_FROM_L1 157
[ PPC970_PME_PM_INST_FROM_L1 ] = {
.pme_name = "PM_INST_FROM_L1",
+ .pme_code = 0x142d,
.pme_short_desc = "Instruction fetched from L1",
.pme_long_desc = "An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions",
- .pme_event_ids = { 39, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000010080000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_INST_FROM_L1],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_INST_FROM_L1]
},
-#define PPC970_PME_PM_EE_OFF_EXT_INT 158
[ PPC970_PME_PM_EE_OFF_EXT_INT ] = {
.pme_name = "PM_EE_OFF_EXT_INT",
+ .pme_code = 0x337,
.pme_short_desc = "Cycles MSR(EE) bit off and external interrupt pending",
.pme_long_desc = "Cycles MSR(EE) bit off and external interrupt pending",
- .pme_event_ids = { -1, -1, 10, 10, -1, -1, 9, 9 },
- .pme_group_vector = {
- 0x0000000000000200ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_EE_OFF_EXT_INT],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_EE_OFF_EXT_INT]
},
-#define PPC970_PME_PM_PMC6_OVERFLOW 159
[ PPC970_PME_PM_PMC6_OVERFLOW ] = {
.pme_name = "PM_PMC6_OVERFLOW",
+ .pme_code = 0x700a,
.pme_short_desc = "PMC6 Overflow",
.pme_long_desc = "PMC6 Overflow",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 61, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_PMC6_OVERFLOW],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_PMC6_OVERFLOW]
},
-#define PPC970_PME_PM_LSU_LRQ_FULL_CYC 160
[ PPC970_PME_PM_LSU_LRQ_FULL_CYC ] = {
.pme_name = "PM_LSU_LRQ_FULL_CYC",
+ .pme_code = 0x312,
.pme_short_desc = "Cycles LRQ full",
.pme_long_desc = "The ISU sends this signal when the LRQ is full.",
- .pme_event_ids = { -1, -1, 50, 46, -1, -1, 46, 48 },
- .pme_group_vector = {
- 0x0000000000000080ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_LRQ_FULL_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_LRQ_FULL_CYC]
},
-#define PPC970_PME_PM_IC_PREF_INSTALL 161
[ PPC970_PME_PM_IC_PREF_INSTALL ] = {
.pme_name = "PM_IC_PREF_INSTALL",
+ .pme_code = 0x427,
.pme_short_desc = "Instruction prefetched installed in prefetch",
.pme_long_desc = "New line coming into the prefetch buffer",
- .pme_event_ids = { 34, 34, -1, -1, 37, 34, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_IC_PREF_INSTALL],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_IC_PREF_INSTALL]
},
-#define PPC970_PME_PM_DC_PREF_OUT_OF_STREAMS 162
[ PPC970_PME_PM_DC_PREF_OUT_OF_STREAMS ] = {
.pme_name = "PM_DC_PREF_OUT_OF_STREAMS",
+ .pme_code = 0x732,
.pme_short_desc = "D cache out of streams",
.pme_long_desc = "out of streams",
- .pme_event_ids = { -1, -1, 7, 7, -1, -1, 6, 6 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_DC_PREF_OUT_OF_STREAMS],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_DC_PREF_OUT_OF_STREAMS]
},
-#define PPC970_PME_PM_MRK_LSU1_FLUSH_SRQ 163
[ PPC970_PME_PM_MRK_LSU1_FLUSH_SRQ ] = {
.pme_name = "PM_MRK_LSU1_FLUSH_SRQ",
+ .pme_code = 0x717,
.pme_short_desc = "LSU1 marked SRQ flushes",
.pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { -1, -1, 60, 58, -1, -1, 57, 57 },
- .pme_group_vector = {
- 0x0000002000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LSU1_FLUSH_SRQ],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LSU1_FLUSH_SRQ]
},
-#define PPC970_PME_PM_GCT_FULL_CYC 164
[ PPC970_PME_PM_GCT_FULL_CYC ] = {
.pme_name = "PM_GCT_FULL_CYC",
+ .pme_code = 0x300,
.pme_short_desc = "Cycles GCT full",
.pme_long_desc = "The ISU sends a signal indicating the gct is full. ",
- .pme_event_ids = { 29, 28, -1, -1, 30, 29, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GCT_FULL_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GCT_FULL_CYC]
},
-#define PPC970_PME_PM_INST_FROM_MEM 165
[ PPC970_PME_PM_INST_FROM_MEM ] = {
.pme_name = "PM_INST_FROM_MEM",
+ .pme_code = 0x2426,
.pme_short_desc = "Instruction fetched from memory",
.pme_long_desc = "Instruction fetched from memory",
- .pme_event_ids = { -1, 39, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000030020000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_INST_FROM_MEM],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_INST_FROM_MEM]
},
-#define PPC970_PME_PM_FLUSH_LSU_BR_MPRED 166
[ PPC970_PME_PM_FLUSH_LSU_BR_MPRED ] = {
.pme_name = "PM_FLUSH_LSU_BR_MPRED",
+ .pme_code = 0x317,
.pme_short_desc = "Flush caused by LSU or branch mispredict",
.pme_long_desc = "Flush caused by LSU or branch mispredict",
- .pme_event_ids = { -1, -1, 12, 12, -1, -1, 11, 12 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FLUSH_LSU_BR_MPRED],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FLUSH_LSU_BR_MPRED]
},
-#define PPC970_PME_PM_FXU_BUSY 167
[ PPC970_PME_PM_FXU_BUSY ] = {
.pme_name = "PM_FXU_BUSY",
+ .pme_code = 0x6002,
.pme_short_desc = "FXU busy",
.pme_long_desc = "FXU0 and FXU1 are both busy",
- .pme_event_ids = { -1, -1, -1, -1, -1, 28, -1, -1 },
- .pme_group_vector = {
- 0x000000c000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FXU_BUSY],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FXU_BUSY]
},
-#define PPC970_PME_PM_ST_REF_L1_LSU1 168
[ PPC970_PME_PM_ST_REF_L1_LSU1 ] = {
.pme_name = "PM_ST_REF_L1_LSU1",
+ .pme_code = 0x815,
.pme_short_desc = "LSU1 L1 D cache store references",
.pme_long_desc = "A store executed on unit 1",
- .pme_event_ids = { -1, -1, 70, 65, -1, -1, 65, 65 },
- .pme_group_vector = {
- 0x0000000000030000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_ST_REF_L1_LSU1],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_ST_REF_L1_LSU1]
},
-#define PPC970_PME_PM_MRK_LD_MISS_L1 169
[ PPC970_PME_PM_MRK_LD_MISS_L1 ] = {
.pme_name = "PM_MRK_LD_MISS_L1",
+ .pme_code = 0x1720,
.pme_short_desc = "Marked L1 D cache load misses",
.pme_long_desc = "Marked L1 D cache load misses",
- .pme_event_ids = { 75, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000200000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LD_MISS_L1],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LD_MISS_L1]
},
-#define PPC970_PME_PM_L1_WRITE_CYC 170
[ PPC970_PME_PM_L1_WRITE_CYC ] = {
.pme_name = "PM_L1_WRITE_CYC",
+ .pme_code = 0x434,
.pme_short_desc = "Cycles writing to instruction L1",
.pme_long_desc = "This signal is asserted each cycle a cache write is active.",
- .pme_event_ids = { -1, -1, 35, 33, -1, -1, 33, 33 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_L1_WRITE_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_L1_WRITE_CYC]
},
-#define PPC970_PME_PM_LSU_REJECT_LMQ_FULL 171
[ PPC970_PME_PM_LSU_REJECT_LMQ_FULL ] = {
.pme_name = "PM_LSU_REJECT_LMQ_FULL",
+ .pme_code = 0x2920,
.pme_short_desc = "LSU reject due to LMQ full or missed data coming",
.pme_long_desc = "LSU reject due to LMQ full or missed data coming",
- .pme_event_ids = { -1, 68, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_REJECT_LMQ_FULL],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_REJECT_LMQ_FULL]
},
-#define PPC970_PME_PM_FPU_ALL 172
[ PPC970_PME_PM_FPU_ALL ] = {
.pme_name = "PM_FPU_ALL",
+ .pme_code = 0x5100,
.pme_short_desc = "FPU executed add",
.pme_long_desc = " mult",
- .pme_event_ids = { -1, -1, -1, -1, 27, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000020ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_ALL],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_ALL]
},
-#define PPC970_PME_PM_LSU_SRQ_S0_ALLOC 173
[ PPC970_PME_PM_LSU_SRQ_S0_ALLOC ] = {
.pme_name = "PM_LSU_SRQ_S0_ALLOC",
+ .pme_code = 0x825,
.pme_short_desc = "SRQ slot 0 allocated",
.pme_long_desc = "SRQ Slot zero was allocated",
- .pme_event_ids = { 69, 69, -1, -1, 71, 69, -1, -1 },
- .pme_group_vector = {
- 0x0000000040000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_SRQ_S0_ALLOC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_SRQ_S0_ALLOC]
},
-#define PPC970_PME_PM_INST_FROM_L25_SHR 174
[ PPC970_PME_PM_INST_FROM_L25_SHR ] = {
.pme_name = "PM_INST_FROM_L25_SHR",
+ .pme_code = 0x5426,
.pme_short_desc = "Instruction fetched from L2.5 shared",
.pme_long_desc = "Instruction fetched from L2.5 shared",
- .pme_event_ids = { -1, -1, -1, -1, 42, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000020000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_INST_FROM_L25_SHR],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_INST_FROM_L25_SHR]
},
-#define PPC970_PME_PM_GRP_MRK 175
[ PPC970_PME_PM_GRP_MRK ] = {
.pme_name = "PM_GRP_MRK",
+ .pme_code = 0x5004,
.pme_short_desc = "Group marked in IDU",
.pme_long_desc = "A group was sampled (marked)",
- .pme_event_ids = { -1, -1, -1, -1, 36, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000600000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GRP_MRK],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GRP_MRK]
},
-#define PPC970_PME_PM_BR_MPRED_CR 176
[ PPC970_PME_PM_BR_MPRED_CR ] = {
.pme_name = "PM_BR_MPRED_CR",
+ .pme_code = 0x432,
.pme_short_desc = "Branch mispredictions due to CR bit setting",
.pme_long_desc = "This signal is asserted when the branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This signal is asserted after a branch issue event and will result in a branch redirect flush if not overridden by a flush of an older instruction.",
- .pme_event_ids = { -1, -1, 1, 2, -1, -1, 1, 1 },
- .pme_group_vector = {
- 0x0000000005000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_BR_MPRED_CR],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_BR_MPRED_CR]
},
-#define PPC970_PME_PM_DC_PREF_STREAM_ALLOC 177
[ PPC970_PME_PM_DC_PREF_STREAM_ALLOC ] = {
.pme_name = "PM_DC_PREF_STREAM_ALLOC",
+ .pme_code = 0x737,
.pme_short_desc = "D cache new prefetch stream allocated",
.pme_long_desc = "A new Prefetch Stream was allocated",
- .pme_event_ids = { -1, -1, 8, 8, -1, -1, 7, 7 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_DC_PREF_STREAM_ALLOC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_DC_PREF_STREAM_ALLOC]
},
-#define PPC970_PME_PM_FPU1_FIN 178
[ PPC970_PME_PM_FPU1_FIN ] = {
.pme_name = "PM_FPU1_FIN",
+ .pme_code = 0x117,
.pme_short_desc = "FPU1 produced a result",
.pme_long_desc = "fp1 finished, produced a result. This only indicates finish, not completion. ",
- .pme_event_ids = { -1, -1, 19, 19, -1, -1, 18, 19 },
- .pme_group_vector = {
- 0x0000000000802800ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_FIN],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_FIN]
},
-#define PPC970_PME_PM_LSU_REJECT_SRQ 179
[ PPC970_PME_PM_LSU_REJECT_SRQ ] = {
.pme_name = "PM_LSU_REJECT_SRQ",
+ .pme_code = 0x1920,
.pme_short_desc = "LSU SRQ rejects",
.pme_long_desc = "LSU SRQ rejects",
- .pme_event_ids = { 68, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_REJECT_SRQ],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_REJECT_SRQ]
},
-#define PPC970_PME_PM_BR_MPRED_TA 180
[ PPC970_PME_PM_BR_MPRED_TA ] = {
.pme_name = "PM_BR_MPRED_TA",
+ .pme_code = 0x433,
.pme_short_desc = "Branch mispredictions due to target address",
.pme_long_desc = "branch miss predict due to a target address prediction. This signal will be asserted each time the branch execution unit detects an incorrect target address prediction. This signal will be asserted after a valid branch execution unit issue and will cause a branch mispredict flush unless a flush is detected from an older instruction.",
- .pme_event_ids = { -1, -1, 2, 3, -1, -1, 2, 2 },
- .pme_group_vector = {
- 0x0000000005000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_BR_MPRED_TA],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_BR_MPRED_TA]
},
-#define PPC970_PME_PM_CRQ_FULL_CYC 181
[ PPC970_PME_PM_CRQ_FULL_CYC ] = {
.pme_name = "PM_CRQ_FULL_CYC",
+ .pme_code = 0x311,
.pme_short_desc = "Cycles CR issue queue full",
.pme_long_desc = "The ISU sends a signal indicating that the issue queue that feeds the ifu cr unit cannot accept any more group (queue is full of groups).",
- .pme_event_ids = { -1, -1, 3, 4, -1, -1, 3, 3 },
- .pme_group_vector = {
- 0x0000000000000040ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_CRQ_FULL_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_CRQ_FULL_CYC]
},
-#define PPC970_PME_PM_LD_MISS_L1 182
[ PPC970_PME_PM_LD_MISS_L1 ] = {
.pme_name = "PM_LD_MISS_L1",
+ .pme_code = 0x3810,
.pme_short_desc = "L1 D cache load misses",
.pme_long_desc = "Total DL1 Load references that miss the DL1",
- .pme_event_ids = { -1, -1, 37, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000043600006ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LD_MISS_L1],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LD_MISS_L1]
},
-#define PPC970_PME_PM_INST_FROM_PREF 183
[ PPC970_PME_PM_INST_FROM_PREF ] = {
.pme_name = "PM_INST_FROM_PREF",
+ .pme_code = 0x342d,
.pme_short_desc = "Instructions fetched from prefetch",
.pme_long_desc = "An instruction fetch group was fetched from the prefetch buffer. Fetch Groups can contain up to 8 instructions",
- .pme_event_ids = { -1, -1, 32, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000030000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_INST_FROM_PREF],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_INST_FROM_PREF]
},
-#define PPC970_PME_PM_STCX_PASS 184
[ PPC970_PME_PM_STCX_PASS ] = {
.pme_name = "PM_STCX_PASS",
+ .pme_code = 0x725,
.pme_short_desc = "Stcx passes",
.pme_long_desc = "A stcx (stwcx or stdcx) instruction was successful",
- .pme_event_ids = { 85, 80, -1, -1, 83, 83, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_STCX_PASS],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_STCX_PASS]
},
-#define PPC970_PME_PM_DC_INV_L2 185
[ PPC970_PME_PM_DC_INV_L2 ] = {
.pme_name = "PM_DC_INV_L2",
+ .pme_code = 0x817,
.pme_short_desc = "L1 D cache entries invalidated from L2",
.pme_long_desc = "A dcache invalidated was received from the L2 because a line in L2 was castout.",
- .pme_event_ids = { -1, -1, 6, 6, -1, -1, 5, 5 },
- .pme_group_vector = {
- 0x0000000020010006ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_DC_INV_L2],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_DC_INV_L2]
},
-#define PPC970_PME_PM_LSU_SRQ_FULL_CYC 186
[ PPC970_PME_PM_LSU_SRQ_FULL_CYC ] = {
.pme_name = "PM_LSU_SRQ_FULL_CYC",
+ .pme_code = 0x313,
.pme_short_desc = "Cycles SRQ full",
.pme_long_desc = "The ISU sends this signal when the srq is full.",
- .pme_event_ids = { -1, -1, 51, 48, -1, -1, 47, 49 },
- .pme_group_vector = {
- 0x0000000000000080ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_SRQ_FULL_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_SRQ_FULL_CYC]
},
-#define PPC970_PME_PM_LSU0_FLUSH_LRQ 187
[ PPC970_PME_PM_LSU0_FLUSH_LRQ ] = {
.pme_name = "PM_LSU0_FLUSH_LRQ",
+ .pme_code = 0x802,
.pme_short_desc = "LSU0 LRQ flushes",
.pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { 46, 45, -1, -1, 48, 45, -1, -1 },
- .pme_group_vector = {
- 0x0000000000004000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU0_FLUSH_LRQ],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU0_FLUSH_LRQ]
},
-#define PPC970_PME_PM_LSU_SRQ_S0_VALID 188
[ PPC970_PME_PM_LSU_SRQ_S0_VALID ] = {
.pme_name = "PM_LSU_SRQ_S0_VALID",
+ .pme_code = 0x821,
.pme_short_desc = "SRQ slot 0 valid",
.pme_long_desc = "This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.",
- .pme_event_ids = { 70, 70, -1, -1, 72, 70, -1, -1 },
- .pme_group_vector = {
- 0x0000000040000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_SRQ_S0_VALID],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_SRQ_S0_VALID]
},
-#define PPC970_PME_PM_LARX_LSU0 189
[ PPC970_PME_PM_LARX_LSU0 ] = {
.pme_name = "PM_LARX_LSU0",
+ .pme_code = 0x727,
.pme_short_desc = "Larx executed on LSU0",
.pme_long_desc = "A larx (lwarx or ldarx) was executed on side 0 (there is no coresponding unit 1 event since larx instructions can only execute on unit 0)",
- .pme_event_ids = { 43, 42, -1, -1, 45, 42, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LARX_LSU0],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LARX_LSU0]
},
-#define PPC970_PME_PM_GCT_EMPTY_CYC 190
[ PPC970_PME_PM_GCT_EMPTY_CYC ] = {
.pme_name = "PM_GCT_EMPTY_CYC",
+ .pme_code = 0x1004,
.pme_short_desc = "Cycles GCT empty",
.pme_long_desc = "The Global Completion Table is completely empty",
- .pme_event_ids = { 28, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000100080200ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GCT_EMPTY_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GCT_EMPTY_CYC]
},
-#define PPC970_PME_PM_FPU1_ALL 191
[ PPC970_PME_PM_FPU1_ALL ] = {
.pme_name = "PM_FPU1_ALL",
+ .pme_code = 0x107,
.pme_short_desc = "FPU1 executed add",
.pme_long_desc = " mult",
- .pme_event_ids = { 17, 16, -1, -1, 18, 17, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000800ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_ALL],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_ALL]
},
-#define PPC970_PME_PM_FPU1_FSQRT 192
[ PPC970_PME_PM_FPU1_FSQRT ] = {
.pme_name = "PM_FPU1_FSQRT",
+ .pme_code = 0x106,
.pme_short_desc = "FPU1 executed FSQRT instruction",
.pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp1 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 21, 20, -1, -1, 22, 21, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000800ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_FSQRT],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_FSQRT]
},
-#define PPC970_PME_PM_FPU_FIN 193
[ PPC970_PME_PM_FPU_FIN ] = {
.pme_name = "PM_FPU_FIN",
+ .pme_code = 0x4110,
.pme_short_desc = "FPU produced a result",
.pme_long_desc = "FPU finished, produced a result This only indicates finish, not completion. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, -1, 22, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000100010ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_FIN],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_FIN]
},
-#define PPC970_PME_PM_LSU_SRQ_STFWD 194
[ PPC970_PME_PM_LSU_SRQ_STFWD ] = {
.pme_name = "PM_LSU_SRQ_STFWD",
+ .pme_code = 0x1820,
.pme_short_desc = "SRQ store forwarded",
.pme_long_desc = "Data from a store instruction was forwarded to a load",
- .pme_event_ids = { 71, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_SRQ_STFWD],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_SRQ_STFWD]
},
-#define PPC970_PME_PM_MRK_LD_MISS_L1_LSU1 195
[ PPC970_PME_PM_MRK_LD_MISS_L1_LSU1 ] = {
.pme_name = "PM_MRK_LD_MISS_L1_LSU1",
+ .pme_code = 0x724,
.pme_short_desc = "LSU1 L1 D cache load misses",
.pme_long_desc = "A marked load, executing on unit 1, missed the dcache",
- .pme_event_ids = { 77, 74, -1, -1, 77, 76, -1, -1 },
- .pme_group_vector = {
- 0x0000002000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LD_MISS_L1_LSU1],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LD_MISS_L1_LSU1]
},
-#define PPC970_PME_PM_FXU0_FIN 196
[ PPC970_PME_PM_FXU0_FIN ] = {
.pme_name = "PM_FXU0_FIN",
+ .pme_code = 0x332,
.pme_short_desc = "FXU0 produced a result",
.pme_long_desc = "The Fixed Point unit 0 finished an instruction and produced a result",
- .pme_event_ids = { -1, -1, 25, 25, -1, -1, 25, 25 },
- .pme_group_vector = {
- 0x0000008000000100ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FXU0_FIN],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FXU0_FIN]
},
-#define PPC970_PME_PM_MRK_FPU_FIN 197
[ PPC970_PME_PM_MRK_FPU_FIN ] = {
.pme_name = "PM_MRK_FPU_FIN",
+ .pme_code = 0x7004,
.pme_short_desc = "Marked instruction FPU processing finished",
.pme_long_desc = "One of the Floating Point Units finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 49, -1 },
- .pme_group_vector = {
- 0x0000000400000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_FPU_FIN],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_FPU_FIN]
},
-#define PPC970_PME_PM_PMC5_OVERFLOW 198
[ PPC970_PME_PM_PMC5_OVERFLOW ] = {
.pme_name = "PM_PMC5_OVERFLOW",
+ .pme_code = 0x600a,
.pme_short_desc = "PMC5 Overflow",
.pme_long_desc = "PMC5 Overflow",
- .pme_event_ids = { -1, -1, -1, -1, -1, 80, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_PMC5_OVERFLOW],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_PMC5_OVERFLOW]
},
-#define PPC970_PME_PM_SNOOP_TLBIE 199
[ PPC970_PME_PM_SNOOP_TLBIE ] = {
.pme_name = "PM_SNOOP_TLBIE",
+ .pme_code = 0x703,
.pme_short_desc = "Snoop TLBIE",
.pme_long_desc = "A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.",
- .pme_event_ids = { 83, 78, -1, -1, 81, 81, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_SNOOP_TLBIE],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_SNOOP_TLBIE]
},
-#define PPC970_PME_PM_FPU1_FRSP_FCONV 200
[ PPC970_PME_PM_FPU1_FRSP_FCONV ] = {
.pme_name = "PM_FPU1_FRSP_FCONV",
+ .pme_code = 0x115,
.pme_short_desc = "FPU1 executed FRSP or FCONV instructions",
.pme_long_desc = "This signal is active for one cycle when fp1 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { -1, -1, 21, 21, -1, -1, 20, 21 },
- .pme_group_vector = {
- 0x0000000000000400ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_FRSP_FCONV],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_FRSP_FCONV]
},
-#define PPC970_PME_PM_FPU0_FDIV 201
[ PPC970_PME_PM_FPU0_FDIV ] = {
.pme_name = "PM_FPU0_FDIV",
+ .pme_code = 0x100,
.pme_short_desc = "FPU0 executed FDIV instruction",
.pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp0 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.",
- .pme_event_ids = { 10, 9, -1, -1, 11, 10, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000400ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_FDIV],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_FDIV]
},
-#define PPC970_PME_PM_LD_REF_L1_LSU1 202
[ PPC970_PME_PM_LD_REF_L1_LSU1 ] = {
.pme_name = "PM_LD_REF_L1_LSU1",
+ .pme_code = 0x814,
.pme_short_desc = "LSU1 L1 D cache load references",
.pme_long_desc = "A load executed on unit 1",
- .pme_event_ids = { -1, -1, 41, 38, -1, -1, 38, 39 },
- .pme_group_vector = {
- 0x0000000000008000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LD_REF_L1_LSU1],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LD_REF_L1_LSU1]
},
-#define PPC970_PME_PM_HV_CYC 203
[ PPC970_PME_PM_HV_CYC ] = {
.pme_name = "PM_HV_CYC",
+ .pme_code = 0x3004,
.pme_short_desc = "Hypervisor Cycles",
.pme_long_desc = "Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)",
- .pme_event_ids = { -1, -1, 30, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000020080000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_HV_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_HV_CYC]
},
-#define PPC970_PME_PM_LR_CTR_MAP_FULL_CYC 204
[ PPC970_PME_PM_LR_CTR_MAP_FULL_CYC ] = {
.pme_name = "PM_LR_CTR_MAP_FULL_CYC",
+ .pme_code = 0x306,
.pme_short_desc = "Cycles LR/CTR mapper full",
.pme_long_desc = "The ISU sends a signal indicating that the lr/ctr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.",
- .pme_event_ids = { 44, 43, -1, -1, 46, 43, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000040ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LR_CTR_MAP_FULL_CYC],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LR_CTR_MAP_FULL_CYC]
},
-#define PPC970_PME_PM_FPU_DENORM 205
[ PPC970_PME_PM_FPU_DENORM ] = {
.pme_name = "PM_FPU_DENORM",
+ .pme_code = 0x1120,
.pme_short_desc = "FPU received denormalized data",
.pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized. Combined Unit 0 + Unit 1",
- .pme_event_ids = { 26, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000020ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_DENORM],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_DENORM]
},
-#define PPC970_PME_PM_LSU0_REJECT_SRQ 206
[ PPC970_PME_PM_LSU0_REJECT_SRQ ] = {
.pme_name = "PM_LSU0_REJECT_SRQ",
+ .pme_code = 0x920,
.pme_short_desc = "LSU0 SRQ rejects",
.pme_long_desc = "LSU0 SRQ rejects",
- .pme_event_ids = { 53, 52, -1, -1, 55, 52, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU0_REJECT_SRQ],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU0_REJECT_SRQ]
},
-#define PPC970_PME_PM_LSU1_REJECT_SRQ 207
[ PPC970_PME_PM_LSU1_REJECT_SRQ ] = {
.pme_name = "PM_LSU1_REJECT_SRQ",
+ .pme_code = 0x924,
.pme_short_desc = "LSU1 SRQ rejects",
.pme_long_desc = "LSU1 SRQ rejects",
- .pme_event_ids = { 63, 62, -1, -1, 65, 62, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU1_REJECT_SRQ],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU1_REJECT_SRQ]
},
-#define PPC970_PME_PM_LSU1_DERAT_MISS 208
[ PPC970_PME_PM_LSU1_DERAT_MISS ] = {
.pme_name = "PM_LSU1_DERAT_MISS",
+ .pme_code = 0x706,
.pme_short_desc = "LSU1 DERAT misses",
.pme_long_desc = "A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.",
- .pme_event_ids = { 55, 54, -1, -1, 57, 54, -1, -1 },
- .pme_group_vector = {
- 0x0000000000040000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU1_DERAT_MISS],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU1_DERAT_MISS]
},
-#define PPC970_PME_PM_IC_PREF_REQ 209
[ PPC970_PME_PM_IC_PREF_REQ ] = {
.pme_name = "PM_IC_PREF_REQ",
+ .pme_code = 0x426,
.pme_short_desc = "Instruction prefetch requests",
.pme_long_desc = "Asserted when a non-canceled prefetch is made to the cache interface unit (CIU).",
- .pme_event_ids = { 35, 35, -1, -1, 38, 35, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_IC_PREF_REQ],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_IC_PREF_REQ]
},
-#define PPC970_PME_PM_MRK_LSU_FIN 210
[ PPC970_PME_PM_MRK_LSU_FIN ] = {
.pme_name = "PM_MRK_LSU_FIN",
+ .pme_code = 0x8004,
.pme_short_desc = "Marked instruction LSU processing finished",
.pme_long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 60 },
- .pme_group_vector = {
- 0x0000000400000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LSU_FIN],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LSU_FIN]
},
-#define PPC970_PME_PM_MRK_DATA_FROM_MEM 211
[ PPC970_PME_PM_MRK_DATA_FROM_MEM ] = {
.pme_name = "PM_MRK_DATA_FROM_MEM",
+ .pme_code = 0x3937,
.pme_short_desc = "Marked data loaded from memory",
.pme_long_desc = "Marked data loaded from memory",
- .pme_event_ids = { -1, -1, 53, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_DATA_FROM_MEM],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_DATA_FROM_MEM]
},
-#define PPC970_PME_PM_LSU0_FLUSH_UST 212
[ PPC970_PME_PM_LSU0_FLUSH_UST ] = {
.pme_name = "PM_LSU0_FLUSH_UST",
+ .pme_code = 0x801,
.pme_short_desc = "LSU0 unaligned store flushes",
.pme_long_desc = "A store was flushed from unit 0 because it was unaligned (crossed a 4k boundary)",
- .pme_event_ids = { 49, 48, -1, -1, 51, 48, -1, -1 },
- .pme_group_vector = {
- 0x0000000000010000ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU0_FLUSH_UST],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU0_FLUSH_UST]
},
-#define PPC970_PME_PM_LSU_FLUSH_LRQ 213
[ PPC970_PME_PM_LSU_FLUSH_LRQ ] = {
.pme_name = "PM_LSU_FLUSH_LRQ",
+ .pme_code = 0x6800,
.pme_short_desc = "LRQ flushes",
.pme_long_desc = "A load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { -1, -1, -1, -1, -1, 65, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000008ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_FLUSH_LRQ],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_FLUSH_LRQ]
},
-#define PPC970_PME_PM_LSU_FLUSH_SRQ 214
[ PPC970_PME_PM_LSU_FLUSH_SRQ ] = {
.pme_name = "PM_LSU_FLUSH_SRQ",
+ .pme_code = 0x5800,
.pme_short_desc = "SRQ flushes",
.pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { -1, -1, -1, -1, 67, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000008ULL }
+ .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_FLUSH_SRQ],
+ .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_FLUSH_SRQ]
}
};
#define PPC970_PME_EVENT_COUNT 215
-static pmg_ppc970_group_t ppc970_groups[] = {
+static const int ppc970_group_event_ids[][PPC970_NUM_EVENT_COUNTERS] = {
+ [ 0 ] = { 82, 2, 67, 30, 0, 2, 28, 29 },
+ [ 1 ] = { 2, 2, 37, 6, 41, 37, 63, 37 },
+ [ 2 ] = { 37, 2, 37, 6, 41, 37, 63, 37 },
+ [ 3 ] = { 65, 64, 4, 30, 67, 65, 63, 37 },
+ [ 4 ] = { 27, 25, 22, 22, 3, 26, 30, 22 },
+ [ 5 ] = { 26, 26, 4, 30, 27, 27, 21, 43 },
+ [ 6 ] = { 88, 1, 3, 29, 46, 38, 30, 4 },
+ [ 7 ] = { 13, 21, 23, 24, 3, 37, 46, 49 },
+ [ 8 ] = { 38, 2, 25, 27, 35, 32, 30, 4 },
+ [ 9 ] = { 28, 84, 67, 10, 3, 37, 8, 10 },
+ [ 10 ] = { 10, 18, 17, 21, 12, 20, 30, 4 },
+ [ 11 ] = { 12, 20, 14, 19, 9, 17, 30, 4 },
+ [ 12 ] = { 9, 17, 15, 20, 3, 37, 12, 18 },
+ [ 13 ] = { 15, 23, 14, 19, 3, 37, 4, 16 },
+ [ 14 ] = { 46, 55, 4, 5, 49, 56, 30, 4 },
+ [ 15 ] = { 48, 57, 40, 38, 3, 37, 35, 36 },
+ [ 16 ] = { 49, 58, 69, 65, 3, 37, 62, 5 },
+ [ 17 ] = { 54, 63, 69, 65, 84, 2, 30, 4 },
+ [ 18 ] = { 45, 54, 4, 5, 40, 2, 31, 4 },
+ [ 19 ] = { 28, 65, 30, 5, 0, 37, 28, 67 },
+ [ 20 ] = { 27, 25, 27, 22, 3, 26, 30, 22 },
+ [ 21 ] = { 6, 41, 37, 63, 3, 37, 63, 37 },
+ [ 22 ] = { 6, 65, 37, 63, 3, 37, 63, 37 },
+ [ 23 ] = { 27, 25, 14, 19, 3, 27, 30, 43 },
+ [ 24 ] = { 37, 2, 37, 1, 84, 2, 1, 2 },
+ [ 25 ] = { 37, 2, 37, 1, 3, 84, 63, 37 },
+ [ 26 ] = { 82, 4, 0, 2, 43, 2, 30, 2 },
+ [ 27 ] = { 3, 37, 5, 5, 4, 3, 44, 47 },
+ [ 28 ] = { 6, 41, 31, 5, 68, 67, 32, 34 },
+ [ 29 ] = { 40, 39, 30, 30, 5, 2, 28, 5 },
+ [ 30 ] = { 69, 70, 37, 49, 40, 37, 4, 37 },
+ [ 31 ] = { 39, 36, 31, 5, 40, 2, 30, 4 },
+ [ 32 ] = { 28, 33, 33, 30, 41, 64, 63, 4 },
+ [ 33 ] = { 75, 83, 4, 51, 36, 73, 50, 30 },
+ [ 34 ] = { 73, 71, 4, 50, 36, 72, 49, 60 },
+ [ 35 ] = { 79, 2, 64, 51, 74, 78, 60, 30 },
+ [ 36 ] = { 80, 72, 58, 60, 3, 37, 54, 58 },
+ [ 37 ] = { 76, 74, 55, 57, 3, 37, 53, 57 },
+ [ 38 ] = { 37, 37, 27, 26, 29, 28, 24, 4 },
+ [ 39 ] = { 37, 2, 24, 23, 29, 28, 25, 26 },
+ [ 40 ] = { 39, 39, 32, 0, 40, 2, 4, 30 },
+ [ 41 ] = { 40, 39, 32, 0, 42, 39, 4, 30 }
+};
+
+static const pmg_power_group_t ppc970_groups[] = {
[ 0 ] = {
.pmg_name = "pm_slice0",
.pmg_desc = "Time Slice 0",
- .pmg_event_ids = { 82, 2, 67, 30, 0, 2, 28, 29 },
+ .pmg_event_ids = ppc970_group_event_ids[0],
.pmg_mmcr0 = 0x000000000000051eULL,
.pmg_mmcr1 = 0x000000000a46f18cULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -1971,7 +2884,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 1 ] = {
.pmg_name = "pm_eprof",
.pmg_desc = "Group for use with eprof",
- .pmg_event_ids = { 2, 2, 37, 6, 41, 37, 63, 37 },
+ .pmg_event_ids = ppc970_group_event_ids[1],
.pmg_mmcr0 = 0x0000000000000f1eULL,
.pmg_mmcr1 = 0x4003001005f09000ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -1979,7 +2892,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 2 ] = {
.pmg_name = "pm_basic",
.pmg_desc = "Basic performance indicators",
- .pmg_event_ids = { 37, 2, 37, 6, 41, 37, 63, 37 },
+ .pmg_event_ids = ppc970_group_event_ids[2],
.pmg_mmcr0 = 0x000000000000091eULL,
.pmg_mmcr1 = 0x4003001005f09000ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -1987,7 +2900,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 3 ] = {
.pmg_name = "pm_lsu",
.pmg_desc = "Information on the Load Store Unit",
- .pmg_event_ids = { 65, 64, 4, 30, 67, 65, 63, 37 },
+ .pmg_event_ids = ppc970_group_event_ids[3],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000f00007a400000ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -1995,7 +2908,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 4 ] = {
.pmg_name = "pm_fpu1",
.pmg_desc = "Floating Point events",
- .pmg_event_ids = { 27, 25, 22, 22, 3, 26, 30, 22 },
+ .pmg_event_ids = ppc970_group_event_ids[4],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00000000001e0480ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2003,7 +2916,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 5 ] = {
.pmg_name = "pm_fpu2",
.pmg_desc = "Floating Point events",
- .pmg_event_ids = { 26, 26, 4, 30, 27, 27, 21, 43 },
+ .pmg_event_ids = ppc970_group_event_ids[5],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000020e87a400000ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2011,7 +2924,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 6 ] = {
.pmg_name = "pm_isu_rename",
.pmg_desc = "ISU Rename Pool Events",
- .pmg_event_ids = { 88, 1, 3, 29, 46, 38, 30, 4 },
+ .pmg_event_ids = ppc970_group_event_ids[6],
.pmg_mmcr0 = 0x0000000000001228ULL,
.pmg_mmcr1 = 0x400000218e6d84bcULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2019,7 +2932,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 7 ] = {
.pmg_name = "pm_isu_queues1",
.pmg_desc = "ISU Rename Pool Events",
- .pmg_event_ids = { 13, 21, 23, 24, 3, 37, 46, 49 },
+ .pmg_event_ids = ppc970_group_event_ids[7],
.pmg_mmcr0 = 0x000000000000132eULL,
.pmg_mmcr1 = 0x40000000851e994cULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2027,7 +2940,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 8 ] = {
.pmg_name = "pm_isu_flow",
.pmg_desc = "ISU Instruction Flow Events",
- .pmg_event_ids = { 38, 2, 25, 27, 35, 32, 30, 4 },
+ .pmg_event_ids = ppc970_group_event_ids[8],
.pmg_mmcr0 = 0x000000000000181eULL,
.pmg_mmcr1 = 0x400000b3d7b7c4bcULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2035,7 +2948,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 9 ] = {
.pmg_name = "pm_isu_work",
.pmg_desc = "ISU Indicators of Work Blockage",
- .pmg_event_ids = { 28, 84, 67, 10, 3, 37, 8, 10 },
+ .pmg_event_ids = ppc970_group_event_ids[9],
.pmg_mmcr0 = 0x0000000000000402ULL,
.pmg_mmcr1 = 0x400000050fde9d88ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2043,7 +2956,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 10 ] = {
.pmg_name = "pm_fpu3",
.pmg_desc = "Floating Point events by unit",
- .pmg_event_ids = { 10, 18, 17, 21, 12, 20, 30, 4 },
+ .pmg_event_ids = ppc970_group_event_ids[10],
.pmg_mmcr0 = 0x0000000000001028ULL,
.pmg_mmcr1 = 0x000000008d6354bcULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2051,7 +2964,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 11 ] = {
.pmg_name = "pm_fpu4",
.pmg_desc = "Floating Point events by unit",
- .pmg_event_ids = { 12, 20, 14, 19, 9, 17, 30, 4 },
+ .pmg_event_ids = ppc970_group_event_ids[11],
.pmg_mmcr0 = 0x000000000000122cULL,
.pmg_mmcr1 = 0x000000009de774bcULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2059,7 +2972,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 12 ] = {
.pmg_name = "pm_fpu5",
.pmg_desc = "Floating Point events by unit",
- .pmg_event_ids = { 9, 17, 15, 20, 3, 37, 12, 18 },
+ .pmg_event_ids = ppc970_group_event_ids[12],
.pmg_mmcr0 = 0x0000000000001838ULL,
.pmg_mmcr1 = 0x000000c0851e9958ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2067,7 +2980,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 13 ] = {
.pmg_name = "pm_fpu7",
.pmg_desc = "Floating Point events by unit",
- .pmg_event_ids = { 15, 23, 14, 19, 3, 37, 4, 16 },
+ .pmg_event_ids = ppc970_group_event_ids[13],
.pmg_mmcr0 = 0x000000000000193aULL,
.pmg_mmcr1 = 0x000000c89dde97e0ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2075,7 +2988,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 14 ] = {
.pmg_name = "pm_lsu_flush",
.pmg_desc = "LSU Flush Events",
- .pmg_event_ids = { 46, 55, 4, 5, 49, 56, 30, 4 },
+ .pmg_event_ids = ppc970_group_event_ids[14],
.pmg_mmcr0 = 0x000000000000122cULL,
.pmg_mmcr1 = 0x000c00007be774bcULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2083,7 +2996,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 15 ] = {
.pmg_name = "pm_lsu_load1",
.pmg_desc = "LSU Load Events",
- .pmg_event_ids = { 48, 57, 40, 38, 3, 37, 35, 36 },
+ .pmg_event_ids = ppc970_group_event_ids[15],
.pmg_mmcr0 = 0x0000000000001028ULL,
.pmg_mmcr1 = 0x000f0000851e9958ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2091,7 +3004,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 16 ] = {
.pmg_name = "pm_lsu_store1",
.pmg_desc = "LSU Store Events",
- .pmg_event_ids = { 49, 58, 69, 65, 3, 37, 62, 5 },
+ .pmg_event_ids = ppc970_group_event_ids[16],
.pmg_mmcr0 = 0x000000000000112aULL,
.pmg_mmcr1 = 0x000f00008d5e99dcULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2099,7 +3012,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 17 ] = {
.pmg_name = "pm_lsu_store2",
.pmg_desc = "LSU Store Events",
- .pmg_event_ids = { 54, 63, 69, 65, 84, 2, 30, 4 },
+ .pmg_event_ids = ppc970_group_event_ids[17],
.pmg_mmcr0 = 0x0000000000001838ULL,
.pmg_mmcr1 = 0x0003c0d08d76f4bcULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2107,7 +3020,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 18 ] = {
.pmg_name = "pm_lsu7",
.pmg_desc = "Information on the Load Store Unit",
- .pmg_event_ids = { 45, 54, 4, 5, 40, 2, 31, 4 },
+ .pmg_event_ids = ppc970_group_event_ids[18],
.pmg_mmcr0 = 0x000000000000122cULL,
.pmg_mmcr1 = 0x000830047bd2fe3cULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2115,7 +3028,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 19 ] = {
.pmg_name = "pm_misc",
.pmg_desc = "Misc Events for testing",
- .pmg_event_ids = { 28, 65, 30, 5, 0, 37, 28, 67 },
+ .pmg_event_ids = ppc970_group_event_ids[19],
.pmg_mmcr0 = 0x0000000000000404ULL,
.pmg_mmcr1 = 0x0000000023c69194ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2123,7 +3036,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 20 ] = {
.pmg_name = "pm_pe_bench1",
.pmg_desc = "PE Benchmarker group for FP analysis",
- .pmg_event_ids = { 27, 25, 27, 22, 3, 26, 30, 22 },
+ .pmg_event_ids = ppc970_group_event_ids[20],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x10001002001e0480ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2131,7 +3044,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 21 ] = {
.pmg_name = "pm_pe_bench4",
.pmg_desc = "PE Benchmarker group for L1 and TLB",
- .pmg_event_ids = { 6, 41, 37, 63, 3, 37, 63, 37 },
+ .pmg_event_ids = ppc970_group_event_ids[21],
.pmg_mmcr0 = 0x0000000000001420ULL,
.pmg_mmcr1 = 0x000b000004de9000ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2139,7 +3052,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 22 ] = {
.pmg_name = "pm_hpmcount1",
.pmg_desc = "Hpmcount group for L1 and TLB behavior",
- .pmg_event_ids = { 6, 65, 37, 63, 3, 37, 63, 37 },
+ .pmg_event_ids = ppc970_group_event_ids[22],
.pmg_mmcr0 = 0x0000000000001404ULL,
.pmg_mmcr1 = 0x000b000004de9000ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2147,7 +3060,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 23 ] = {
.pmg_name = "pm_hpmcount2",
.pmg_desc = "Hpmcount group for computation",
- .pmg_event_ids = { 27, 25, 14, 19, 3, 27, 30, 43 },
+ .pmg_event_ids = ppc970_group_event_ids[23],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000020289dde0480ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2155,7 +3068,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 24 ] = {
.pmg_name = "pm_l1andbr",
.pmg_desc = "L1 misses and branch misspredict analysis",
- .pmg_event_ids = { 37, 2, 37, 1, 84, 2, 1, 2 },
+ .pmg_event_ids = ppc970_group_event_ids[24],
.pmg_mmcr0 = 0x000000000000091eULL,
.pmg_mmcr1 = 0x8003c01d0636fce8ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2163,7 +3076,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 25 ] = {
.pmg_name = "Instruction mix: loads",
.pmg_desc = " stores and branches",
- .pmg_event_ids = { 37, 2, 37, 1, 3, 84, 63, 37 },
+ .pmg_event_ids = ppc970_group_event_ids[25],
.pmg_mmcr0 = 0x000000000000091eULL,
.pmg_mmcr1 = 0x8003c021061fb000ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2171,7 +3084,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 26 ] = {
.pmg_name = "pm_branch",
.pmg_desc = "SLB and branch misspredict analysis",
- .pmg_event_ids = { 82, 4, 0, 2, 43, 2, 30, 2 },
+ .pmg_event_ids = ppc970_group_event_ids[26],
.pmg_mmcr0 = 0x000000000000052aULL,
.pmg_mmcr1 = 0x8008000bc662f4e8ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2179,7 +3092,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 27 ] = {
.pmg_name = "pm_data",
.pmg_desc = "data source and LMQ",
- .pmg_event_ids = { 3, 37, 5, 5, 4, 3, 44, 47 },
+ .pmg_event_ids = ppc970_group_event_ids[27],
.pmg_mmcr0 = 0x0000000000000712ULL,
.pmg_mmcr1 = 0x0000300e3bce7f74ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2187,7 +3100,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 28 ] = {
.pmg_name = "pm_tlb",
.pmg_desc = "TLB and LRQ plus data prefetch",
- .pmg_event_ids = { 6, 41, 31, 5, 68, 67, 32, 34 },
+ .pmg_event_ids = ppc970_group_event_ids[28],
.pmg_mmcr0 = 0x0000000000001420ULL,
.pmg_mmcr1 = 0x0008e03c4bfdacecULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2195,7 +3108,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 29 ] = {
.pmg_name = "pm_isource",
.pmg_desc = "inst source and tablewalk",
- .pmg_event_ids = { 40, 39, 30, 30, 5, 2, 28, 5 },
+ .pmg_event_ids = ppc970_group_event_ids[29],
.pmg_mmcr0 = 0x000000000000060cULL,
.pmg_mmcr1 = 0x800b00c0226ef1dcULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2203,7 +3116,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 30 ] = {
.pmg_name = "pm_sync",
.pmg_desc = "Sync and SRQ",
- .pmg_event_ids = { 69, 70, 37, 49, 40, 37, 4, 37 },
+ .pmg_event_ids = ppc970_group_event_ids[30],
.pmg_mmcr0 = 0x0000000000001d32ULL,
.pmg_mmcr1 = 0x0003e0c107529780ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2211,7 +3124,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 31 ] = {
.pmg_name = "pm_ierat",
.pmg_desc = "IERAT",
- .pmg_event_ids = { 39, 36, 31, 5, 40, 2, 30, 4 },
+ .pmg_event_ids = ppc970_group_event_ids[31],
.pmg_mmcr0 = 0x0000000000000d3eULL,
.pmg_mmcr1 = 0x800000c04bd2f4bcULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2219,7 +3132,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 32 ] = {
.pmg_name = "pm_derat",
.pmg_desc = "DERAT",
- .pmg_event_ids = { 28, 33, 33, 30, 41, 64, 63, 4 },
+ .pmg_event_ids = ppc970_group_event_ids[32],
.pmg_mmcr0 = 0x0000000000000436ULL,
.pmg_mmcr1 = 0x100b7052e274003cULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2227,7 +3140,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 33 ] = {
.pmg_name = "pm_mark1",
.pmg_desc = "Information on marked instructions",
- .pmg_event_ids = { 75, 83, 4, 51, 36, 73, 50, 30 },
+ .pmg_event_ids = ppc970_group_event_ids[33],
.pmg_mmcr0 = 0x0000000000000006ULL,
.pmg_mmcr1 = 0x00008080790852a4ULL,
.pmg_mmcra = 0x0000000000002001ULL
@@ -2235,7 +3148,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 34 ] = {
.pmg_name = "pm_mark2",
.pmg_desc = "Marked Instructions Processing Flow",
- .pmg_event_ids = { 73, 71, 4, 50, 36, 72, 49, 60 },
+ .pmg_event_ids = ppc970_group_event_ids[34],
.pmg_mmcr0 = 0x000000000000020aULL,
.pmg_mmcr1 = 0x0000000079484210ULL,
.pmg_mmcra = 0x0000000000002001ULL
@@ -2243,7 +3156,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 35 ] = {
.pmg_name = "pm_mark3",
.pmg_desc = "Marked Stores Processing Flow",
- .pmg_event_ids = { 79, 2, 64, 51, 74, 78, 60, 30 },
+ .pmg_event_ids = ppc970_group_event_ids[35],
.pmg_mmcr0 = 0x000000000000031eULL,
.pmg_mmcr1 = 0x00203004190a3f24ULL,
.pmg_mmcra = 0x0000000000002001ULL
@@ -2251,7 +3164,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 36 ] = {
.pmg_name = "pm_lsu_mark1",
.pmg_desc = "Load Store Unit Marked Events",
- .pmg_event_ids = { 80, 72, 58, 60, 3, 37, 54, 58 },
+ .pmg_event_ids = ppc970_group_event_ids[36],
.pmg_mmcr0 = 0x0000000000001b34ULL,
.pmg_mmcr1 = 0x000280c08d5e9850ULL,
.pmg_mmcra = 0x0000000000002001ULL
@@ -2259,7 +3172,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 37 ] = {
.pmg_name = "pm_lsu_mark2",
.pmg_desc = "Load Store Unit Marked Events",
- .pmg_event_ids = { 76, 74, 55, 57, 3, 37, 53, 57 },
+ .pmg_event_ids = ppc970_group_event_ids[37],
.pmg_mmcr0 = 0x0000000000001838ULL,
.pmg_mmcr1 = 0x000280c0959e99dcULL,
.pmg_mmcra = 0x0000000000002001ULL
@@ -2267,7 +3180,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 38 ] = {
.pmg_name = "pm_fxu1",
.pmg_desc = "Fixed Point events by unit",
- .pmg_event_ids = { 37, 37, 27, 26, 29, 28, 24, 4 },
+ .pmg_event_ids = ppc970_group_event_ids[38],
.pmg_mmcr0 = 0x0000000000000912ULL,
.pmg_mmcr1 = 0x100010020084213cULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2275,7 +3188,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 39 ] = {
.pmg_name = "pm_fxu2",
.pmg_desc = "Fixed Point events by unit",
- .pmg_event_ids = { 37, 2, 24, 23, 29, 28, 25, 26 },
+ .pmg_event_ids = ppc970_group_event_ids[39],
.pmg_mmcr0 = 0x000000000000091eULL,
.pmg_mmcr1 = 0x4000000ca4042d78ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2283,7 +3196,7 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 40 ] = {
.pmg_name = "pm_ifu",
.pmg_desc = "Instruction Fetch Unit events",
- .pmg_event_ids = { 39, 39, 32, 0, 40, 2, 4, 30 },
+ .pmg_event_ids = ppc970_group_event_ids[40],
.pmg_mmcr0 = 0x0000000000000d0cULL,
.pmg_mmcr1 = 0x800000c06b52f7a4ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2291,11 +3204,12 @@ static pmg_ppc970_group_t ppc970_groups[] = {
[ 41 ] = {
.pmg_name = "pm_L1_icm",
.pmg_desc = " Level 1 instruction cache misses",
- .pmg_event_ids = { 40, 39, 32, 0, 42, 39, 4, 30 },
+ .pmg_event_ids = ppc970_group_event_ids[41],
.pmg_mmcr0 = 0x000000000000060cULL,
.pmg_mmcr1 = 0x800000f06b4c67a4ULL,
.pmg_mmcra = 0x0000000000002000ULL
}
};
+
#endif
diff --git a/src/libpfm-3.y/lib/ppc970mp_events.h b/src/libpfm-3.y/lib/ppc970mp_events.h
index 7beae0e94c8b8b5bde1544c5d4b1b5fa3cad70b4..bc4abf5839da2e96e95148daabcf71d6f8ce73af 100644
--- a/src/libpfm-3.y/lib/ppc970mp_events.h
+++ b/src/libpfm-3.y/lib/ppc970mp_events.h
@@ -20,2085 +20,3067 @@
* hand.
*
*/
-static pme_ppc970mp_entry_t ppc970mp_pe[] = {
#define PPC970MP_PME_PM_LSU_REJECT_RELOAD_CDF 0
+#define PPC970MP_PME_PM_MRK_LSU_SRQ_INST_VALID 1
+#define PPC970MP_PME_PM_FPU1_SINGLE 2
+#define PPC970MP_PME_PM_FPU0_STALL3 3
+#define PPC970MP_PME_PM_TB_BIT_TRANS 4
+#define PPC970MP_PME_PM_GPR_MAP_FULL_CYC 5
+#define PPC970MP_PME_PM_MRK_ST_CMPL 6
+#define PPC970MP_PME_PM_FPU0_STF 7
+#define PPC970MP_PME_PM_FPU1_FMA 8
+#define PPC970MP_PME_PM_LSU1_FLUSH_ULD 9
+#define PPC970MP_PME_PM_MRK_INST_FIN 10
+#define PPC970MP_PME_PM_MRK_LSU0_FLUSH_UST 11
+#define PPC970MP_PME_PM_LSU_LRQ_S0_ALLOC 12
+#define PPC970MP_PME_PM_FPU_FDIV 13
+#define PPC970MP_PME_PM_FPU0_FULL_CYC 14
+#define PPC970MP_PME_PM_FPU_SINGLE 15
+#define PPC970MP_PME_PM_FPU0_FMA 16
+#define PPC970MP_PME_PM_MRK_LSU1_FLUSH_ULD 17
+#define PPC970MP_PME_PM_LSU1_FLUSH_LRQ 18
+#define PPC970MP_PME_PM_DTLB_MISS 19
+#define PPC970MP_PME_PM_CMPLU_STALL_FXU 20
+#define PPC970MP_PME_PM_MRK_ST_MISS_L1 21
+#define PPC970MP_PME_PM_EXT_INT 22
+#define PPC970MP_PME_PM_MRK_LSU1_FLUSH_LRQ 23
+#define PPC970MP_PME_PM_MRK_ST_GPS 24
+#define PPC970MP_PME_PM_GRP_DISP_SUCCESS 25
+#define PPC970MP_PME_PM_LSU1_LDF 26
+#define PPC970MP_PME_PM_LSU0_SRQ_STFWD 27
+#define PPC970MP_PME_PM_CR_MAP_FULL_CYC 28
+#define PPC970MP_PME_PM_MRK_LSU0_FLUSH_ULD 29
+#define PPC970MP_PME_PM_LSU_DERAT_MISS 30
+#define PPC970MP_PME_PM_FPU0_SINGLE 31
+#define PPC970MP_PME_PM_FPU1_FDIV 32
+#define PPC970MP_PME_PM_FPU1_FEST 33
+#define PPC970MP_PME_PM_FPU0_FRSP_FCONV 34
+#define PPC970MP_PME_PM_GCT_EMPTY_SRQ_FULL 35
+#define PPC970MP_PME_PM_MRK_ST_CMPL_INT 36
+#define PPC970MP_PME_PM_FLUSH_BR_MPRED 37
+#define PPC970MP_PME_PM_FXU_FIN 38
+#define PPC970MP_PME_PM_FPU_STF 39
+#define PPC970MP_PME_PM_DSLB_MISS 40
+#define PPC970MP_PME_PM_FXLS1_FULL_CYC 41
+#define PPC970MP_PME_PM_CMPLU_STALL_FPU 42
+#define PPC970MP_PME_PM_LSU_LMQ_LHR_MERGE 43
+#define PPC970MP_PME_PM_MRK_STCX_FAIL 44
+#define PPC970MP_PME_PM_FXU0_BUSY_FXU1_IDLE 45
+#define PPC970MP_PME_PM_CMPLU_STALL_LSU 46
+#define PPC970MP_PME_PM_MRK_DATA_FROM_L25_SHR 47
+#define PPC970MP_PME_PM_LSU_FLUSH_ULD 48
+#define PPC970MP_PME_PM_MRK_BRU_FIN 49
+#define PPC970MP_PME_PM_IERAT_XLATE_WR 50
+#define PPC970MP_PME_PM_GCT_EMPTY_BR_MPRED 51
+#define PPC970MP_PME_PM_LSU0_BUSY 52
+#define PPC970MP_PME_PM_DATA_FROM_MEM 53
+#define PPC970MP_PME_PM_FPR_MAP_FULL_CYC 54
+#define PPC970MP_PME_PM_FPU1_FULL_CYC 55
+#define PPC970MP_PME_PM_FPU0_FIN 56
+#define PPC970MP_PME_PM_GRP_BR_REDIR 57
+#define PPC970MP_PME_PM_GCT_EMPTY_IC_MISS 58
+#define PPC970MP_PME_PM_THRESH_TIMEO 59
+#define PPC970MP_PME_PM_FPU_FSQRT 60
+#define PPC970MP_PME_PM_MRK_LSU0_FLUSH_LRQ 61
+#define PPC970MP_PME_PM_PMC1_OVERFLOW 62
+#define PPC970MP_PME_PM_FXLS0_FULL_CYC 63
+#define PPC970MP_PME_PM_FPU0_ALL 64
+#define PPC970MP_PME_PM_DATA_TABLEWALK_CYC 65
+#define PPC970MP_PME_PM_FPU0_FEST 66
+#define PPC970MP_PME_PM_DATA_FROM_L25_MOD 67
+#define PPC970MP_PME_PM_LSU0_REJECT_ERAT_MISS 68
+#define PPC970MP_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 69
+#define PPC970MP_PME_PM_LSU0_REJECT_RELOAD_CDF 70
+#define PPC970MP_PME_PM_FPU_FEST 71
+#define PPC970MP_PME_PM_0INST_FETCH 72
+#define PPC970MP_PME_PM_LD_MISS_L1_LSU0 73
+#define PPC970MP_PME_PM_LSU1_REJECT_RELOAD_CDF 74
+#define PPC970MP_PME_PM_L1_PREF 75
+#define PPC970MP_PME_PM_FPU1_STALL3 76
+#define PPC970MP_PME_PM_BRQ_FULL_CYC 77
+#define PPC970MP_PME_PM_PMC8_OVERFLOW 78
+#define PPC970MP_PME_PM_PMC7_OVERFLOW 79
+#define PPC970MP_PME_PM_WORK_HELD 80
+#define PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU0 81
+#define PPC970MP_PME_PM_FXU_IDLE 82
+#define PPC970MP_PME_PM_INST_CMPL 83
+#define PPC970MP_PME_PM_LSU1_FLUSH_UST 84
+#define PPC970MP_PME_PM_LSU0_FLUSH_ULD 85
+#define PPC970MP_PME_PM_LSU_FLUSH 86
+#define PPC970MP_PME_PM_INST_FROM_L2 87
+#define PPC970MP_PME_PM_LSU1_REJECT_LMQ_FULL 88
+#define PPC970MP_PME_PM_PMC2_OVERFLOW 89
+#define PPC970MP_PME_PM_FPU0_DENORM 90
+#define PPC970MP_PME_PM_FPU1_FMOV_FEST 91
+#define PPC970MP_PME_PM_INST_FETCH_CYC 92
+#define PPC970MP_PME_PM_GRP_DISP_REJECT 93
+#define PPC970MP_PME_PM_LSU_LDF 94
+#define PPC970MP_PME_PM_INST_DISP 95
+#define PPC970MP_PME_PM_DATA_FROM_L25_SHR 96
+#define PPC970MP_PME_PM_L1_DCACHE_RELOAD_VALID 97
+#define PPC970MP_PME_PM_MRK_GRP_ISSUED 98
+#define PPC970MP_PME_PM_FPU_FMA 99
+#define PPC970MP_PME_PM_MRK_CRU_FIN 100
+#define PPC970MP_PME_PM_CMPLU_STALL_REJECT 101
+#define PPC970MP_PME_PM_MRK_LSU1_FLUSH_UST 102
+#define PPC970MP_PME_PM_MRK_FXU_FIN 103
+#define PPC970MP_PME_PM_LSU1_REJECT_ERAT_MISS 104
+#define PPC970MP_PME_PM_BR_ISSUED 105
+#define PPC970MP_PME_PM_PMC4_OVERFLOW 106
+#define PPC970MP_PME_PM_EE_OFF 107
+#define PPC970MP_PME_PM_INST_FROM_L25_MOD 108
+#define PPC970MP_PME_PM_CMPLU_STALL_ERAT_MISS 109
+#define PPC970MP_PME_PM_ITLB_MISS 110
+#define PPC970MP_PME_PM_FXU1_BUSY_FXU0_IDLE 111
+#define PPC970MP_PME_PM_GRP_DISP_VALID 112
+#define PPC970MP_PME_PM_MRK_GRP_DISP 113
+#define PPC970MP_PME_PM_LSU_FLUSH_UST 114
+#define PPC970MP_PME_PM_FXU1_FIN 115
+#define PPC970MP_PME_PM_GRP_CMPL 116
+#define PPC970MP_PME_PM_FPU_FRSP_FCONV 117
+#define PPC970MP_PME_PM_MRK_LSU0_FLUSH_SRQ 118
+#define PPC970MP_PME_PM_CMPLU_STALL_OTHER 119
+#define PPC970MP_PME_PM_LSU_LMQ_FULL_CYC 120
+#define PPC970MP_PME_PM_ST_REF_L1_LSU0 121
+#define PPC970MP_PME_PM_LSU0_DERAT_MISS 122
+#define PPC970MP_PME_PM_LSU_SRQ_SYNC_CYC 123
+#define PPC970MP_PME_PM_FPU_STALL3 124
+#define PPC970MP_PME_PM_LSU_REJECT_ERAT_MISS 125
+#define PPC970MP_PME_PM_MRK_DATA_FROM_L2 126
+#define PPC970MP_PME_PM_LSU0_FLUSH_SRQ 127
+#define PPC970MP_PME_PM_FPU0_FMOV_FEST 128
+#define PPC970MP_PME_PM_IOPS_CMPL 129
+#define PPC970MP_PME_PM_LD_REF_L1_LSU0 130
+#define PPC970MP_PME_PM_LSU1_FLUSH_SRQ 131
+#define PPC970MP_PME_PM_CMPLU_STALL_DIV 132
+#define PPC970MP_PME_PM_GRP_BR_MPRED 133
+#define PPC970MP_PME_PM_LSU_LMQ_S0_ALLOC 134
+#define PPC970MP_PME_PM_LSU0_REJECT_LMQ_FULL 135
+#define PPC970MP_PME_PM_ST_REF_L1 136
+#define PPC970MP_PME_PM_MRK_VMX_FIN 137
+#define PPC970MP_PME_PM_LSU_SRQ_EMPTY_CYC 138
+#define PPC970MP_PME_PM_FPU1_STF 139
+#define PPC970MP_PME_PM_RUN_CYC 140
+#define PPC970MP_PME_PM_LSU_LMQ_S0_VALID 141
+#define PPC970MP_PME_PM_LSU0_LDF 142
+#define PPC970MP_PME_PM_LSU_LRQ_S0_VALID 143
+#define PPC970MP_PME_PM_PMC3_OVERFLOW 144
+#define PPC970MP_PME_PM_MRK_IMR_RELOAD 145
+#define PPC970MP_PME_PM_MRK_GRP_TIMEO 146
+#define PPC970MP_PME_PM_FPU_FMOV_FEST 147
+#define PPC970MP_PME_PM_GRP_DISP_BLK_SB_CYC 148
+#define PPC970MP_PME_PM_XER_MAP_FULL_CYC 149
+#define PPC970MP_PME_PM_ST_MISS_L1 150
+#define PPC970MP_PME_PM_STOP_COMPLETION 151
+#define PPC970MP_PME_PM_MRK_GRP_CMPL 152
+#define PPC970MP_PME_PM_ISLB_MISS 153
+#define PPC970MP_PME_PM_SUSPENDED 154
+#define PPC970MP_PME_PM_CYC 155
+#define PPC970MP_PME_PM_LD_MISS_L1_LSU1 156
+#define PPC970MP_PME_PM_STCX_FAIL 157
+#define PPC970MP_PME_PM_LSU1_SRQ_STFWD 158
+#define PPC970MP_PME_PM_GRP_DISP 159
+#define PPC970MP_PME_PM_L2_PREF 160
+#define PPC970MP_PME_PM_FPU1_DENORM 161
+#define PPC970MP_PME_PM_DATA_FROM_L2 162
+#define PPC970MP_PME_PM_FPU0_FPSCR 163
+#define PPC970MP_PME_PM_MRK_DATA_FROM_L25_MOD 164
+#define PPC970MP_PME_PM_FPU0_FSQRT 165
+#define PPC970MP_PME_PM_LD_REF_L1 166
+#define PPC970MP_PME_PM_MRK_L1_RELOAD_VALID 167
+#define PPC970MP_PME_PM_1PLUS_PPC_CMPL 168
+#define PPC970MP_PME_PM_INST_FROM_L1 169
+#define PPC970MP_PME_PM_EE_OFF_EXT_INT 170
+#define PPC970MP_PME_PM_PMC6_OVERFLOW 171
+#define PPC970MP_PME_PM_LSU_LRQ_FULL_CYC 172
+#define PPC970MP_PME_PM_IC_PREF_INSTALL 173
+#define PPC970MP_PME_PM_DC_PREF_OUT_OF_STREAMS 174
+#define PPC970MP_PME_PM_MRK_LSU1_FLUSH_SRQ 175
+#define PPC970MP_PME_PM_GCT_FULL_CYC 176
+#define PPC970MP_PME_PM_INST_FROM_MEM 177
+#define PPC970MP_PME_PM_FLUSH_LSU_BR_MPRED 178
+#define PPC970MP_PME_PM_FXU_BUSY 179
+#define PPC970MP_PME_PM_ST_REF_L1_LSU1 180
+#define PPC970MP_PME_PM_MRK_LD_MISS_L1 181
+#define PPC970MP_PME_PM_L1_WRITE_CYC 182
+#define PPC970MP_PME_PM_LSU1_BUSY 183
+#define PPC970MP_PME_PM_LSU_REJECT_LMQ_FULL 184
+#define PPC970MP_PME_PM_CMPLU_STALL_FDIV 185
+#define PPC970MP_PME_PM_FPU_ALL 186
+#define PPC970MP_PME_PM_LSU_SRQ_S0_ALLOC 187
+#define PPC970MP_PME_PM_INST_FROM_L25_SHR 188
+#define PPC970MP_PME_PM_GRP_MRK 189
+#define PPC970MP_PME_PM_BR_MPRED_CR 190
+#define PPC970MP_PME_PM_DC_PREF_STREAM_ALLOC 191
+#define PPC970MP_PME_PM_FPU1_FIN 192
+#define PPC970MP_PME_PM_LSU_REJECT_SRQ 193
+#define PPC970MP_PME_PM_BR_MPRED_TA 194
+#define PPC970MP_PME_PM_CRQ_FULL_CYC 195
+#define PPC970MP_PME_PM_LD_MISS_L1 196
+#define PPC970MP_PME_PM_INST_FROM_PREF 197
+#define PPC970MP_PME_PM_STCX_PASS 198
+#define PPC970MP_PME_PM_DC_INV_L2 199
+#define PPC970MP_PME_PM_LSU_SRQ_FULL_CYC 200
+#define PPC970MP_PME_PM_LSU0_FLUSH_LRQ 201
+#define PPC970MP_PME_PM_LSU_SRQ_S0_VALID 202
+#define PPC970MP_PME_PM_LARX_LSU0 203
+#define PPC970MP_PME_PM_GCT_EMPTY_CYC 204
+#define PPC970MP_PME_PM_FPU1_ALL 205
+#define PPC970MP_PME_PM_FPU1_FSQRT 206
+#define PPC970MP_PME_PM_FPU_FIN 207
+#define PPC970MP_PME_PM_LSU_SRQ_STFWD 208
+#define PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU1 209
+#define PPC970MP_PME_PM_FXU0_FIN 210
+#define PPC970MP_PME_PM_MRK_FPU_FIN 211
+#define PPC970MP_PME_PM_PMC5_OVERFLOW 212
+#define PPC970MP_PME_PM_SNOOP_TLBIE 213
+#define PPC970MP_PME_PM_FPU1_FRSP_FCONV 214
+#define PPC970MP_PME_PM_FPU0_FDIV 215
+#define PPC970MP_PME_PM_LD_REF_L1_LSU1 216
+#define PPC970MP_PME_PM_HV_CYC 217
+#define PPC970MP_PME_PM_LR_CTR_MAP_FULL_CYC 218
+#define PPC970MP_PME_PM_FPU_DENORM 219
+#define PPC970MP_PME_PM_LSU0_REJECT_SRQ 220
+#define PPC970MP_PME_PM_LSU1_REJECT_SRQ 221
+#define PPC970MP_PME_PM_LSU1_DERAT_MISS 222
+#define PPC970MP_PME_PM_IC_PREF_REQ 223
+#define PPC970MP_PME_PM_MRK_LSU_FIN 224
+#define PPC970MP_PME_PM_MRK_DATA_FROM_MEM 225
+#define PPC970MP_PME_PM_CMPLU_STALL_DCACHE_MISS 226
+#define PPC970MP_PME_PM_LSU0_FLUSH_UST 227
+#define PPC970MP_PME_PM_LSU_FLUSH_LRQ 228
+#define PPC970MP_PME_PM_LSU_FLUSH_SRQ 229
+
+
+static const int ppc970mp_event_ids[][PPC970MP_NUM_EVENT_COUNTERS] = {
+ [ PPC970MP_PME_PM_LSU_REJECT_RELOAD_CDF ] = { -1, -1, -1, -1, -1, 66, -1, -1 },
+ [ PPC970MP_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { -1, -1, 61, 61, -1, -1, 60, 61 },
+ [ PPC970MP_PME_PM_FPU1_SINGLE ] = { 23, 22, -1, -1, 23, 22, -1, -1 },
+ [ PPC970MP_PME_PM_FPU0_STALL3 ] = { 15, 14, -1, -1, 15, 14, -1, -1 },
+ [ PPC970MP_PME_PM_TB_BIT_TRANS ] = { -1, -1, -1, -1, -1, -1, -1, 67 },
+ [ PPC970MP_PME_PM_GPR_MAP_FULL_CYC ] = { -1, -1, 27, 28, -1, -1, 27, 27 },
+ [ PPC970MP_PME_PM_MRK_ST_CMPL ] = { 78, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_FPU0_STF ] = { 16, 15, -1, -1, 16, 15, -1, -1 },
+ [ PPC970MP_PME_PM_FPU1_FMA ] = { 20, 19, -1, -1, 20, 19, -1, -1 },
+ [ PPC970MP_PME_PM_LSU1_FLUSH_ULD ] = { 57, 56, -1, -1, 58, 55, -1, -1 },
+ [ PPC970MP_PME_PM_MRK_INST_FIN ] = { -1, -1, -1, -1, -1, -1, 50, -1 },
+ [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_UST ] = { -1, -1, 56, 56, -1, -1, 55, 55 },
+ [ PPC970MP_PME_PM_LSU_LRQ_S0_ALLOC ] = { 65, 65, -1, -1, 66, 64, -1, -1 },
+ [ PPC970MP_PME_PM_FPU_FDIV ] = { 27, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_FPU0_FULL_CYC ] = { 13, 12, -1, -1, 13, 12, -1, -1 },
+ [ PPC970MP_PME_PM_FPU_SINGLE ] = { -1, -1, -1, -1, 27, -1, -1, -1 },
+ [ PPC970MP_PME_PM_FPU0_FMA ] = { 11, 10, -1, -1, 11, 10, -1, -1 },
+ [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_ULD ] = { -1, -1, 59, 59, -1, -1, 58, 58 },
+ [ PPC970MP_PME_PM_LSU1_FLUSH_LRQ ] = { 55, 54, -1, -1, 56, 53, -1, -1 },
+ [ PPC970MP_PME_PM_DTLB_MISS ] = { 6, 5, -1, -1, 6, 5, -1, -1 },
+ [ PPC970MP_PME_PM_CMPLU_STALL_FXU ] = { -1, -1, -1, -1, 85, -1, -1, -1 },
+ [ PPC970MP_PME_PM_MRK_ST_MISS_L1 ] = { 79, 75, -1, -1, 76, 76, -1, -1 },
+ [ PPC970MP_PME_PM_EXT_INT ] = { -1, -1, -1, -1, -1, -1, -1, 10 },
+ [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { -1, -1, 57, 57, -1, -1, 56, 56 },
+ [ PPC970MP_PME_PM_MRK_ST_GPS ] = { -1, -1, -1, -1, -1, 75, -1, -1 },
+ [ PPC970MP_PME_PM_GRP_DISP_SUCCESS ] = { -1, -1, -1, -1, 33, -1, -1, -1 },
+ [ PPC970MP_PME_PM_LSU1_LDF ] = { -1, -1, 42, 40, -1, -1, 40, 41 },
+ [ PPC970MP_PME_PM_LSU0_SRQ_STFWD ] = { 53, 52, -1, -1, 54, 51, -1, -1 },
+ [ PPC970MP_PME_PM_CR_MAP_FULL_CYC ] = { 1, 1, -1, -1, 2, 1, -1, -1 },
+ [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_ULD ] = { -1, -1, 55, 55, -1, -1, 54, 54 },
+ [ PPC970MP_PME_PM_LSU_DERAT_MISS ] = { -1, -1, -1, -1, -1, 62, -1, -1 },
+ [ PPC970MP_PME_PM_FPU0_SINGLE ] = { 14, 13, -1, -1, 14, 13, -1, -1 },
+ [ PPC970MP_PME_PM_FPU1_FDIV ] = { 19, 18, -1, -1, 19, 18, -1, -1 },
+ [ PPC970MP_PME_PM_FPU1_FEST ] = { -1, -1, 17, 18, -1, -1, 17, 18 },
+ [ PPC970MP_PME_PM_FPU0_FRSP_FCONV ] = { -1, -1, 16, 17, -1, -1, 16, 17 },
+ [ PPC970MP_PME_PM_GCT_EMPTY_SRQ_FULL ] = { -1, 27, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_MRK_ST_CMPL_INT ] = { -1, -1, 62, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_FLUSH_BR_MPRED ] = { -1, -1, 10, 11, -1, -1, 10, 11 },
+ [ PPC970MP_PME_PM_FXU_FIN ] = { -1, -1, 26, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_FPU_STF ] = { -1, -1, -1, -1, -1, 26, -1, -1 },
+ [ PPC970MP_PME_PM_DSLB_MISS ] = { 5, 4, -1, -1, 5, 4, -1, -1 },
+ [ PPC970MP_PME_PM_FXLS1_FULL_CYC ] = { -1, -1, 23, 24, -1, -1, 23, 24 },
+ [ PPC970MP_PME_PM_CMPLU_STALL_FPU ] = { -1, -1, -1, -1, -1, -1, 67, -1 },
+ [ PPC970MP_PME_PM_LSU_LMQ_LHR_MERGE ] = { -1, -1, 45, 43, -1, -1, 43, 45 },
+ [ PPC970MP_PME_PM_MRK_STCX_FAIL ] = { 77, 74, -1, -1, 75, 74, -1, -1 },
+ [ PPC970MP_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { -1, -1, -1, -1, -1, -1, 24, -1 },
+ [ PPC970MP_PME_PM_CMPLU_STALL_LSU ] = { -1, -1, -1, -1, 84, -1, -1, -1 },
+ [ PPC970MP_PME_PM_MRK_DATA_FROM_L25_SHR ] = { -1, -1, -1, -1, 92, -1, -1, -1 },
+ [ PPC970MP_PME_PM_LSU_FLUSH_ULD ] = { 64, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_MRK_BRU_FIN ] = { -1, 70, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_IERAT_XLATE_WR ] = { -1, -1, 70, 67, -1, -1, 72, 68 },
+ [ PPC970MP_PME_PM_GCT_EMPTY_BR_MPRED ] = { -1, -1, -1, -1, -1, -1, 71, -1 },
+ [ PPC970MP_PME_PM_LSU0_BUSY ] = { 85, 80, -1, -1, 81, 81, -1, -1 },
+ [ PPC970MP_PME_PM_DATA_FROM_MEM ] = { -1, 87, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_FPR_MAP_FULL_CYC ] = { 7, 6, -1, -1, 7, 6, -1, -1 },
+ [ PPC970MP_PME_PM_FPU1_FULL_CYC ] = { 22, 21, -1, -1, 22, 21, -1, -1 },
+ [ PPC970MP_PME_PM_FPU0_FIN ] = { -1, -1, 13, 14, -1, -1, 13, 14 },
+ [ PPC970MP_PME_PM_GRP_BR_REDIR ] = { 31, 30, -1, -1, 31, 30, -1, -1 },
+ [ PPC970MP_PME_PM_GCT_EMPTY_IC_MISS ] = { -1, -1, -1, -1, 88, -1, -1, -1 },
+ [ PPC970MP_PME_PM_THRESH_TIMEO ] = { -1, 82, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_FPU_FSQRT ] = { -1, -1, -1, -1, -1, 25, -1, -1 },
+ [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { -1, -1, 53, 53, -1, -1, 52, 52 },
+ [ PPC970MP_PME_PM_PMC1_OVERFLOW ] = { -1, 76, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_FXLS0_FULL_CYC ] = { -1, -1, 22, 23, -1, -1, 22, 23 },
+ [ PPC970MP_PME_PM_FPU0_ALL ] = { 8, 7, -1, -1, 8, 7, -1, -1 },
+ [ PPC970MP_PME_PM_DATA_TABLEWALK_CYC ] = { 4, 3, -1, -1, 4, 3, -1, -1 },
+ [ PPC970MP_PME_PM_FPU0_FEST ] = { -1, -1, 12, 13, -1, -1, 12, 13 },
+ [ PPC970MP_PME_PM_DATA_FROM_L25_MOD ] = { -1, -1, -1, -1, -1, 87, -1, -1 },
+ [ PPC970MP_PME_PM_LSU0_REJECT_ERAT_MISS ] = { 49, 48, -1, -1, 50, 47, -1, -1 },
+ [ PPC970MP_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { -1, 64, 48, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_LSU0_REJECT_RELOAD_CDF ] = { 51, 50, -1, -1, 52, 49, -1, -1 },
+ [ PPC970MP_PME_PM_FPU_FEST ] = { -1, -1, 21, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_0INST_FETCH ] = { -1, -1, -1, 0, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_LD_MISS_L1_LSU0 ] = { -1, -1, 37, 35, -1, -1, 35, 35 },
+ [ PPC970MP_PME_PM_LSU1_REJECT_RELOAD_CDF ] = { 61, 60, -1, -1, 62, 59, -1, -1 },
+ [ PPC970MP_PME_PM_L1_PREF ] = { -1, -1, 33, 32, -1, -1, 32, 32 },
+ [ PPC970MP_PME_PM_FPU1_STALL3 ] = { 24, 23, -1, -1, 24, 23, -1, -1 },
+ [ PPC970MP_PME_PM_BRQ_FULL_CYC ] = { 0, 0, -1, -1, 1, 0, -1, -1 },
+ [ PPC970MP_PME_PM_PMC8_OVERFLOW ] = { 80, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_PMC7_OVERFLOW ] = { -1, -1, -1, -1, -1, -1, -1, 62 },
+ [ PPC970MP_PME_PM_WORK_HELD ] = { -1, 83, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { 75, 72, -1, -1, 73, 72, -1, -1 },
+ [ PPC970MP_PME_PM_FXU_IDLE ] = { -1, -1, -1, -1, 28, -1, -1, -1 },
+ [ PPC970MP_PME_PM_INST_CMPL ] = { 36, 36, 30, 30, 38, 35, 30, 30 },
+ [ PPC970MP_PME_PM_LSU1_FLUSH_UST ] = { 58, 57, -1, -1, 59, 56, -1, -1 },
+ [ PPC970MP_PME_PM_LSU0_FLUSH_ULD ] = { 47, 46, -1, -1, 48, 45, -1, -1 },
+ [ PPC970MP_PME_PM_LSU_FLUSH ] = { -1, -1, 43, 41, -1, -1, 41, 42 },
+ [ PPC970MP_PME_PM_INST_FROM_L2 ] = { 39, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_LSU1_REJECT_LMQ_FULL ] = { 60, 59, -1, -1, 61, 58, -1, -1 },
+ [ PPC970MP_PME_PM_PMC2_OVERFLOW ] = { -1, -1, 64, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_FPU0_DENORM ] = { 9, 8, -1, -1, 9, 8, -1, -1 },
+ [ PPC970MP_PME_PM_FPU1_FMOV_FEST ] = { -1, -1, 19, 20, -1, -1, 19, 20 },
+ [ PPC970MP_PME_PM_INST_FETCH_CYC ] = { 90, 86, -1, -1, 90, 85, -1, -1 },
+ [ PPC970MP_PME_PM_GRP_DISP_REJECT ] = { 32, 32, -1, -1, 32, 31, -1, 29 },
+ [ PPC970MP_PME_PM_LSU_LDF ] = { -1, -1, -1, -1, -1, -1, -1, 43 },
+ [ PPC970MP_PME_PM_INST_DISP ] = { 37, 37, -1, -1, 39, 36, -1, -1 },
+ [ PPC970MP_PME_PM_DATA_FROM_L25_SHR ] = { -1, -1, -1, -1, 91, -1, -1, -1 },
+ [ PPC970MP_PME_PM_L1_DCACHE_RELOAD_VALID ] = { -1, -1, 32, 31, -1, -1, 31, 31 },
+ [ PPC970MP_PME_PM_MRK_GRP_ISSUED ] = { -1, -1, -1, -1, -1, 70, -1, -1 },
+ [ PPC970MP_PME_PM_FPU_FMA ] = { -1, 25, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_MRK_CRU_FIN ] = { -1, -1, -1, 50, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_CMPLU_STALL_REJECT ] = { -1, -1, -1, -1, -1, -1, 69, -1 },
+ [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_UST ] = { -1, -1, 60, 60, -1, -1, 59, 59 },
+ [ PPC970MP_PME_PM_MRK_FXU_FIN ] = { -1, -1, -1, -1, -1, 69, -1, -1 },
+ [ PPC970MP_PME_PM_LSU1_REJECT_ERAT_MISS ] = { 59, 58, -1, -1, 60, 57, -1, -1 },
+ [ PPC970MP_PME_PM_BR_ISSUED ] = { -1, -1, 0, 1, -1, -1, 0, 0 },
+ [ PPC970MP_PME_PM_PMC4_OVERFLOW ] = { -1, -1, -1, -1, 77, -1, -1, -1 },
+ [ PPC970MP_PME_PM_EE_OFF ] = { -1, -1, 8, 9, -1, -1, 8, 8 },
+ [ PPC970MP_PME_PM_INST_FROM_L25_MOD ] = { -1, -1, -1, -1, -1, 37, -1, -1 },
+ [ PPC970MP_PME_PM_CMPLU_STALL_ERAT_MISS ] = { -1, -1, -1, -1, -1, -1, 70, -1 },
+ [ PPC970MP_PME_PM_ITLB_MISS ] = { 41, 40, -1, -1, 42, 39, -1, -1 },
+ [ PPC970MP_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { -1, -1, -1, 26, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_GRP_DISP_VALID ] = { 33, 33, -1, -1, 34, 32, -1, -1 },
+ [ PPC970MP_PME_PM_MRK_GRP_DISP ] = { 72, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_LSU_FLUSH_UST ] = { -1, 63, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_FXU1_FIN ] = { -1, -1, 25, 27, -1, -1, 26, 26 },
+ [ PPC970MP_PME_PM_GRP_CMPL ] = { -1, -1, -1, -1, -1, -1, 28, -1 },
+ [ PPC970MP_PME_PM_FPU_FRSP_FCONV ] = { -1, -1, -1, -1, -1, -1, 21, -1 },
+ [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { -1, -1, 54, 54, -1, -1, 53, 53 },
+ [ PPC970MP_PME_PM_CMPLU_STALL_OTHER ] = { 88, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_LSU_LMQ_FULL_CYC ] = { -1, -1, 44, 42, -1, -1, 42, 44 },
+ [ PPC970MP_PME_PM_ST_REF_L1_LSU0 ] = { -1, -1, 67, 64, -1, -1, 64, 64 },
+ [ PPC970MP_PME_PM_LSU0_DERAT_MISS ] = { 44, 43, -1, -1, 45, 42, -1, -1 },
+ [ PPC970MP_PME_PM_LSU_SRQ_SYNC_CYC ] = { -1, -1, 51, 49, -1, -1, 48, 50 },
+ [ PPC970MP_PME_PM_FPU_STALL3 ] = { -1, 26, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_LSU_REJECT_ERAT_MISS ] = { -1, -1, -1, -1, 68, -1, -1, -1 },
+ [ PPC970MP_PME_PM_MRK_DATA_FROM_L2 ] = { 71, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_LSU0_FLUSH_SRQ ] = { 46, 45, -1, -1, 47, 44, -1, -1 },
+ [ PPC970MP_PME_PM_FPU0_FMOV_FEST ] = { -1, -1, 14, 15, -1, -1, 14, 15 },
+ [ PPC970MP_PME_PM_IOPS_CMPL ] = { 91, -1, -1, 68, -1, 86, 73, 69 },
+ [ PPC970MP_PME_PM_LD_REF_L1_LSU0 ] = { -1, -1, 39, 37, -1, -1, 37, 38 },
+ [ PPC970MP_PME_PM_LSU1_FLUSH_SRQ ] = { 56, 55, -1, -1, 57, 54, -1, -1 },
+ [ PPC970MP_PME_PM_CMPLU_STALL_DIV ] = { -1, -1, -1, -1, -1, -1, 68, -1 },
+ [ PPC970MP_PME_PM_GRP_BR_MPRED ] = { 30, 29, -1, -1, 30, 29, -1, -1 },
+ [ PPC970MP_PME_PM_LSU_LMQ_S0_ALLOC ] = { -1, -1, 46, 44, -1, -1, 44, 46 },
+ [ PPC970MP_PME_PM_LSU0_REJECT_LMQ_FULL ] = { 50, 49, -1, -1, 51, 48, -1, -1 },
+ [ PPC970MP_PME_PM_ST_REF_L1 ] = { -1, -1, -1, -1, -1, -1, 63, -1 },
+ [ PPC970MP_PME_PM_MRK_VMX_FIN ] = { -1, -1, 63, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_LSU_SRQ_EMPTY_CYC ] = { -1, -1, -1, 47, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_FPU1_STF ] = { 25, 24, -1, -1, 25, 24, -1, -1 },
+ [ PPC970MP_PME_PM_RUN_CYC ] = { 81, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_LSU_LMQ_S0_VALID ] = { -1, -1, 47, 45, -1, -1, 45, 47 },
+ [ PPC970MP_PME_PM_LSU0_LDF ] = { -1, -1, 41, 39, -1, -1, 39, 40 },
+ [ PPC970MP_PME_PM_LSU_LRQ_S0_VALID ] = { 66, 66, -1, -1, 67, 65, -1, -1 },
+ [ PPC970MP_PME_PM_PMC3_OVERFLOW ] = { -1, -1, -1, 62, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_MRK_IMR_RELOAD ] = { 73, 71, -1, -1, 72, 71, -1, -1 },
+ [ PPC970MP_PME_PM_MRK_GRP_TIMEO ] = { -1, -1, -1, -1, 71, -1, -1, -1 },
+ [ PPC970MP_PME_PM_FPU_FMOV_FEST ] = { -1, -1, -1, -1, -1, -1, -1, 22 },
+ [ PPC970MP_PME_PM_GRP_DISP_BLK_SB_CYC ] = { -1, -1, 28, 29, -1, -1, 29, 28 },
+ [ PPC970MP_PME_PM_XER_MAP_FULL_CYC ] = { 87, 84, -1, -1, 83, 83, -1, -1 },
+ [ PPC970MP_PME_PM_ST_MISS_L1 ] = { -1, -1, 66, 63, -1, -1, 62, 63 },
+ [ PPC970MP_PME_PM_STOP_COMPLETION ] = { -1, -1, 65, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_MRK_GRP_CMPL ] = { -1, -1, -1, 51, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_ISLB_MISS ] = { 40, 39, -1, -1, 41, 38, -1, -1 },
+ [ PPC970MP_PME_PM_SUSPENDED ] = { 86, 81, 69, 66, 82, 82, 66, 66 },
+ [ PPC970MP_PME_PM_CYC ] = { 2, 2, 4, 5, 3, 2, 4, 4 },
+ [ PPC970MP_PME_PM_LD_MISS_L1_LSU1 ] = { -1, -1, 38, 36, -1, -1, 36, 36 },
+ [ PPC970MP_PME_PM_STCX_FAIL ] = { 83, 78, -1, -1, 79, 79, -1, -1 },
+ [ PPC970MP_PME_PM_LSU1_SRQ_STFWD ] = { 63, 62, -1, -1, 64, 61, -1, -1 },
+ [ PPC970MP_PME_PM_GRP_DISP ] = { -1, 31, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_L2_PREF ] = { -1, -1, 35, 34, -1, -1, 34, 34 },
+ [ PPC970MP_PME_PM_FPU1_DENORM ] = { 18, 17, -1, -1, 18, 17, -1, -1 },
+ [ PPC970MP_PME_PM_DATA_FROM_L2 ] = { 3, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_FPU0_FPSCR ] = { -1, -1, 15, 16, -1, -1, 15, 16 },
+ [ PPC970MP_PME_PM_MRK_DATA_FROM_L25_MOD ] = { -1, -1, -1, -1, -1, 88, -1, -1 },
+ [ PPC970MP_PME_PM_FPU0_FSQRT ] = { 12, 11, -1, -1, 12, 11, -1, -1 },
+ [ PPC970MP_PME_PM_LD_REF_L1 ] = { -1, -1, -1, -1, -1, -1, -1, 37 },
+ [ PPC970MP_PME_PM_MRK_L1_RELOAD_VALID ] = { -1, -1, 52, 52, -1, -1, 51, 51 },
+ [ PPC970MP_PME_PM_1PLUS_PPC_CMPL ] = { -1, -1, -1, -1, 0, -1, -1, -1 },
+ [ PPC970MP_PME_PM_INST_FROM_L1 ] = { 38, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_EE_OFF_EXT_INT ] = { -1, -1, 9, 10, -1, -1, 9, 9 },
+ [ PPC970MP_PME_PM_PMC6_OVERFLOW ] = { -1, -1, -1, -1, -1, -1, 61, -1 },
+ [ PPC970MP_PME_PM_LSU_LRQ_FULL_CYC ] = { -1, -1, 49, 46, -1, -1, 46, 48 },
+ [ PPC970MP_PME_PM_IC_PREF_INSTALL ] = { 34, 34, -1, -1, 36, 33, -1, -1 },
+ [ PPC970MP_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { -1, -1, 6, 7, -1, -1, 6, 6 },
+ [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { -1, -1, 58, 58, -1, -1, 57, 57 },
+ [ PPC970MP_PME_PM_GCT_FULL_CYC ] = { 29, 28, -1, -1, 29, 28, -1, -1 },
+ [ PPC970MP_PME_PM_INST_FROM_MEM ] = { -1, 38, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_FLUSH_LSU_BR_MPRED ] = { -1, -1, 11, 12, -1, -1, 11, 12 },
+ [ PPC970MP_PME_PM_FXU_BUSY ] = { -1, -1, -1, -1, -1, 27, -1, -1 },
+ [ PPC970MP_PME_PM_ST_REF_L1_LSU1 ] = { -1, -1, 68, 65, -1, -1, 65, 65 },
+ [ PPC970MP_PME_PM_MRK_LD_MISS_L1 ] = { 74, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_L1_WRITE_CYC ] = { -1, -1, 34, 33, -1, -1, 33, 33 },
+ [ PPC970MP_PME_PM_LSU1_BUSY ] = { 89, 85, -1, -1, 89, 84, -1, -1 },
+ [ PPC970MP_PME_PM_LSU_REJECT_LMQ_FULL ] = { -1, 67, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_CMPLU_STALL_FDIV ] = { -1, -1, -1, -1, 87, -1, -1, -1 },
+ [ PPC970MP_PME_PM_FPU_ALL ] = { -1, -1, -1, -1, 26, -1, -1, -1 },
+ [ PPC970MP_PME_PM_LSU_SRQ_S0_ALLOC ] = { 68, 68, -1, -1, 69, 67, -1, -1 },
+ [ PPC970MP_PME_PM_INST_FROM_L25_SHR ] = { -1, -1, -1, -1, 40, -1, -1, -1 },
+ [ PPC970MP_PME_PM_GRP_MRK ] = { -1, -1, -1, -1, 35, -1, -1, -1 },
+ [ PPC970MP_PME_PM_BR_MPRED_CR ] = { -1, -1, 1, 2, -1, -1, 1, 1 },
+ [ PPC970MP_PME_PM_DC_PREF_STREAM_ALLOC ] = { -1, -1, 7, 8, -1, -1, 7, 7 },
+ [ PPC970MP_PME_PM_FPU1_FIN ] = { -1, -1, 18, 19, -1, -1, 18, 19 },
+ [ PPC970MP_PME_PM_LSU_REJECT_SRQ ] = { 67, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_BR_MPRED_TA ] = { -1, -1, 2, 3, -1, -1, 2, 2 },
+ [ PPC970MP_PME_PM_CRQ_FULL_CYC ] = { -1, -1, 3, 4, -1, -1, 3, 3 },
+ [ PPC970MP_PME_PM_LD_MISS_L1 ] = { -1, -1, 36, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_INST_FROM_PREF ] = { -1, -1, 31, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_STCX_PASS ] = { 84, 79, -1, -1, 80, 80, -1, -1 },
+ [ PPC970MP_PME_PM_DC_INV_L2 ] = { -1, -1, 5, 6, -1, -1, 5, 5 },
+ [ PPC970MP_PME_PM_LSU_SRQ_FULL_CYC ] = { -1, -1, 50, 48, -1, -1, 47, 49 },
+ [ PPC970MP_PME_PM_LSU0_FLUSH_LRQ ] = { 45, 44, -1, -1, 46, 43, -1, -1 },
+ [ PPC970MP_PME_PM_LSU_SRQ_S0_VALID ] = { 69, 69, -1, -1, 70, 68, -1, -1 },
+ [ PPC970MP_PME_PM_LARX_LSU0 ] = { 42, 41, -1, -1, 43, 40, -1, -1 },
+ [ PPC970MP_PME_PM_GCT_EMPTY_CYC ] = { 28, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_FPU1_ALL ] = { 17, 16, -1, -1, 17, 16, -1, -1 },
+ [ PPC970MP_PME_PM_FPU1_FSQRT ] = { 21, 20, -1, -1, 21, 20, -1, -1 },
+ [ PPC970MP_PME_PM_FPU_FIN ] = { -1, -1, -1, 22, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_LSU_SRQ_STFWD ] = { 70, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { 76, 73, -1, -1, 74, 73, -1, -1 },
+ [ PPC970MP_PME_PM_FXU0_FIN ] = { -1, -1, 24, 25, -1, -1, 25, 25 },
+ [ PPC970MP_PME_PM_MRK_FPU_FIN ] = { -1, -1, -1, -1, -1, -1, 49, -1 },
+ [ PPC970MP_PME_PM_PMC5_OVERFLOW ] = { -1, -1, -1, -1, -1, 77, -1, -1 },
+ [ PPC970MP_PME_PM_SNOOP_TLBIE ] = { 82, 77, -1, -1, 78, 78, -1, -1 },
+ [ PPC970MP_PME_PM_FPU1_FRSP_FCONV ] = { -1, -1, 20, 21, -1, -1, 20, 21 },
+ [ PPC970MP_PME_PM_FPU0_FDIV ] = { 10, 9, -1, -1, 10, 9, -1, -1 },
+ [ PPC970MP_PME_PM_LD_REF_L1_LSU1 ] = { -1, -1, 40, 38, -1, -1, 38, 39 },
+ [ PPC970MP_PME_PM_HV_CYC ] = { -1, -1, 29, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_LR_CTR_MAP_FULL_CYC ] = { 43, 42, -1, -1, 44, 41, -1, -1 },
+ [ PPC970MP_PME_PM_FPU_DENORM ] = { 26, -1, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_LSU0_REJECT_SRQ ] = { 52, 51, -1, -1, 53, 50, -1, -1 },
+ [ PPC970MP_PME_PM_LSU1_REJECT_SRQ ] = { 62, 61, -1, -1, 63, 60, -1, -1 },
+ [ PPC970MP_PME_PM_LSU1_DERAT_MISS ] = { 54, 53, -1, -1, 55, 52, -1, -1 },
+ [ PPC970MP_PME_PM_IC_PREF_REQ ] = { 35, 35, -1, -1, 37, 34, -1, -1 },
+ [ PPC970MP_PME_PM_MRK_LSU_FIN ] = { -1, -1, -1, -1, -1, -1, -1, 60 },
+ [ PPC970MP_PME_PM_MRK_DATA_FROM_MEM ] = { -1, 88, -1, -1, -1, -1, -1, -1 },
+ [ PPC970MP_PME_PM_CMPLU_STALL_DCACHE_MISS ] = { -1, -1, -1, -1, 86, -1, -1, -1 },
+ [ PPC970MP_PME_PM_LSU0_FLUSH_UST ] = { 48, 47, -1, -1, 49, 46, -1, -1 },
+ [ PPC970MP_PME_PM_LSU_FLUSH_LRQ ] = { -1, -1, -1, -1, -1, 63, -1, -1 },
+ [ PPC970MP_PME_PM_LSU_FLUSH_SRQ ] = { -1, -1, -1, -1, 65, -1, -1, -1 }
+};
+
+static const unsigned long long ppc970mp_group_vecs[][PPC970MP_NUM_GROUP_VEC] = {
+ [ PPC970MP_PME_PM_LSU_REJECT_RELOAD_CDF ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_MRK_LSU_SRQ_INST_VALID ] = {
+ 0x0000000800000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU1_SINGLE ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU0_STALL3 ] = {
+ 0x0000000000002000ULL
+ },
+ [ PPC970MP_PME_PM_TB_BIT_TRANS ] = {
+ 0x0000000000080000ULL
+ },
+ [ PPC970MP_PME_PM_GPR_MAP_FULL_CYC ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_MRK_ST_CMPL ] = {
+ 0x0000000800000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU0_STF ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU1_FMA ] = {
+ 0x0000000000000400ULL
+ },
+ [ PPC970MP_PME_PM_LSU1_FLUSH_ULD ] = {
+ 0x0000000000008000ULL
+ },
+ [ PPC970MP_PME_PM_MRK_INST_FIN ] = {
+ 0x0004000200000000ULL
+ },
+ [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_UST ] = {
+ 0x0000001000000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU_LRQ_S0_ALLOC ] = {
+ 0x0000000010000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU_FDIV ] = {
+ 0x0000100000900010ULL
+ },
+ [ PPC970MP_PME_PM_FPU0_FULL_CYC ] = {
+ 0x0000000000000080ULL
+ },
+ [ PPC970MP_PME_PM_FPU_SINGLE ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU0_FMA ] = {
+ 0x0000000000000400ULL
+ },
+ [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_ULD ] = {
+ 0x0000001000000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU1_FLUSH_LRQ ] = {
+ 0x0000000000004000ULL
+ },
+ [ PPC970MP_PME_PM_DTLB_MISS ] = {
+ 0x0000000010600000ULL
+ },
+ [ PPC970MP_PME_PM_CMPLU_STALL_FXU ] = {
+ 0x0000080000000000ULL
+ },
+ [ PPC970MP_PME_PM_MRK_ST_MISS_L1 ] = {
+ 0x0000001000000000ULL
+ },
+ [ PPC970MP_PME_PM_EXT_INT ] = {
+ 0x0000000000000200ULL
+ },
+ [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_LRQ ] = {
+ 0x0000002000000000ULL
+ },
+ [ PPC970MP_PME_PM_MRK_ST_GPS ] = {
+ 0x0000000800000000ULL
+ },
+ [ PPC970MP_PME_PM_GRP_DISP_SUCCESS ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU1_LDF ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU0_SRQ_STFWD ] = {
+ 0x0000000000020000ULL
+ },
+ [ PPC970MP_PME_PM_CR_MAP_FULL_CYC ] = {
+ 0x0000000000000040ULL
+ },
+ [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_ULD ] = {
+ 0x0000001000000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU_DERAT_MISS ] = {
+ 0x0000040100000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU0_SINGLE ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU1_FDIV ] = {
+ 0x0000000000000400ULL
+ },
+ [ PPC970MP_PME_PM_FPU1_FEST ] = {
+ 0x0000000000001000ULL
+ },
+ [ PPC970MP_PME_PM_FPU0_FRSP_FCONV ] = {
+ 0x0000000000000400ULL
+ },
+ [ PPC970MP_PME_PM_GCT_EMPTY_SRQ_FULL ] = {
+ 0x0000080000000000ULL
+ },
+ [ PPC970MP_PME_PM_MRK_ST_CMPL_INT ] = {
+ 0x0000000800000000ULL
+ },
+ [ PPC970MP_PME_PM_FLUSH_BR_MPRED ] = {
+ 0x0000200000000000ULL
+ },
+ [ PPC970MP_PME_PM_FXU_FIN ] = {
+ 0x0000084000100000ULL
+ },
+ [ PPC970MP_PME_PM_FPU_STF ] = {
+ 0x0000000000800020ULL
+ },
+ [ PPC970MP_PME_PM_DSLB_MISS ] = {
+ 0x0000000004000000ULL
+ },
+ [ PPC970MP_PME_PM_FXLS1_FULL_CYC ] = {
+ 0x0000008000000080ULL
+ },
+ [ PPC970MP_PME_PM_CMPLU_STALL_FPU ] = {
+ 0x0000100000000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU_LMQ_LHR_MERGE ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_MRK_STCX_FAIL ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_FXU0_BUSY_FXU1_IDLE ] = {
+ 0x0000004000000000ULL
+ },
+ [ PPC970MP_PME_PM_CMPLU_STALL_LSU ] = {
+ 0x0000020000000000ULL
+ },
+ [ PPC970MP_PME_PM_MRK_DATA_FROM_L25_SHR ] = {
+ 0x0004000000000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU_FLUSH_ULD ] = {
+ 0x0000000000000008ULL
+ },
+ [ PPC970MP_PME_PM_MRK_BRU_FIN ] = {
+ 0x0000000400000000ULL
+ },
+ [ PPC970MP_PME_PM_IERAT_XLATE_WR ] = {
+ 0x0000000080000000ULL
+ },
+ [ PPC970MP_PME_PM_GCT_EMPTY_BR_MPRED ] = {
+ 0x0000200000000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU0_BUSY ] = {
+ 0x0000020003020000ULL
+ },
+ [ PPC970MP_PME_PM_DATA_FROM_MEM ] = {
+ 0x0003000008000000ULL
+ },
+ [ PPC970MP_PME_PM_FPR_MAP_FULL_CYC ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU1_FULL_CYC ] = {
+ 0x0000000000000080ULL
+ },
+ [ PPC970MP_PME_PM_FPU0_FIN ] = {
+ 0x0000000000802800ULL
+ },
+ [ PPC970MP_PME_PM_GRP_BR_REDIR ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_GCT_EMPTY_IC_MISS ] = {
+ 0x0000200000000000ULL
+ },
+ [ PPC970MP_PME_PM_THRESH_TIMEO ] = {
+ 0x0000000200000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU_FSQRT ] = {
+ 0x0000100000100010ULL
+ },
+ [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_LRQ ] = {
+ 0x0000002000000000ULL
+ },
+ [ PPC970MP_PME_PM_PMC1_OVERFLOW ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_FXLS0_FULL_CYC ] = {
+ 0x0000008000000080ULL
+ },
+ [ PPC970MP_PME_PM_FPU0_ALL ] = {
+ 0x0000000000000800ULL
+ },
+ [ PPC970MP_PME_PM_DATA_TABLEWALK_CYC ] = {
+ 0x0000000020000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU0_FEST ] = {
+ 0x0000000000001000ULL
+ },
+ [ PPC970MP_PME_PM_DATA_FROM_L25_MOD ] = {
+ 0x0002400000000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU0_REJECT_ERAT_MISS ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = {
+ 0x0000000000480000ULL
+ },
+ [ PPC970MP_PME_PM_LSU0_REJECT_RELOAD_CDF ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU_FEST ] = {
+ 0x0000000000000010ULL
+ },
+ [ PPC970MP_PME_PM_0INST_FETCH ] = {
+ 0x0000010000000000ULL
+ },
+ [ PPC970MP_PME_PM_LD_MISS_L1_LSU0 ] = {
+ 0x0001000000008000ULL
+ },
+ [ PPC970MP_PME_PM_LSU1_REJECT_RELOAD_CDF ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_L1_PREF ] = {
+ 0x0000000010000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU1_STALL3 ] = {
+ 0x0000000000002000ULL
+ },
+ [ PPC970MP_PME_PM_BRQ_FULL_CYC ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_PMC8_OVERFLOW ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_PMC7_OVERFLOW ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_WORK_HELD ] = {
+ 0x0000000000000200ULL
+ },
+ [ PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU0 ] = {
+ 0x0000002000000000ULL
+ },
+ [ PPC970MP_PME_PM_FXU_IDLE ] = {
+ 0x000000c000000000ULL
+ },
+ [ PPC970MP_PME_PM_INST_CMPL ] = {
+ 0x0007fffbffffffffULL
+ },
+ [ PPC970MP_PME_PM_LSU1_FLUSH_UST ] = {
+ 0x0000000000010000ULL
+ },
+ [ PPC970MP_PME_PM_LSU0_FLUSH_ULD ] = {
+ 0x0000000000008000ULL
+ },
+ [ PPC970MP_PME_PM_LSU_FLUSH ] = {
+ 0x0000020000000000ULL
+ },
+ [ PPC970MP_PME_PM_INST_FROM_L2 ] = {
+ 0x0000800020000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU1_REJECT_LMQ_FULL ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_PMC2_OVERFLOW ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU0_DENORM ] = {
+ 0x0000000000001000ULL
+ },
+ [ PPC970MP_PME_PM_FPU1_FMOV_FEST ] = {
+ 0x0000000000001000ULL
+ },
+ [ PPC970MP_PME_PM_INST_FETCH_CYC ] = {
+ 0x0000010000000000ULL
+ },
+ [ PPC970MP_PME_PM_GRP_DISP_REJECT ] = {
+ 0x0000000000000101ULL
+ },
+ [ PPC970MP_PME_PM_LSU_LDF ] = {
+ 0x0000000000800020ULL
+ },
+ [ PPC970MP_PME_PM_INST_DISP ] = {
+ 0x0000000100000146ULL
+ },
+ [ PPC970MP_PME_PM_DATA_FROM_L25_SHR ] = {
+ 0x0002400000000000ULL
+ },
+ [ PPC970MP_PME_PM_L1_DCACHE_RELOAD_VALID ] = {
+ 0x0000000100040000ULL
+ },
+ [ PPC970MP_PME_PM_MRK_GRP_ISSUED ] = {
+ 0x0000000200000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU_FMA ] = {
+ 0x0000100000900010ULL
+ },
+ [ PPC970MP_PME_PM_MRK_CRU_FIN ] = {
+ 0x0000000400000000ULL
+ },
+ [ PPC970MP_PME_PM_CMPLU_STALL_REJECT ] = {
+ 0x0000040000000000ULL
+ },
+ [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_UST ] = {
+ 0x0000001000000000ULL
+ },
+ [ PPC970MP_PME_PM_MRK_FXU_FIN ] = {
+ 0x0000000400000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU1_REJECT_ERAT_MISS ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_BR_ISSUED ] = {
+ 0x0000800007000000ULL
+ },
+ [ PPC970MP_PME_PM_PMC4_OVERFLOW ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_EE_OFF ] = {
+ 0x0000000000000200ULL
+ },
+ [ PPC970MP_PME_PM_INST_FROM_L25_MOD ] = {
+ 0x0000010000000000ULL
+ },
+ [ PPC970MP_PME_PM_CMPLU_STALL_ERAT_MISS ] = {
+ 0x0000020000000000ULL
+ },
+ [ PPC970MP_PME_PM_ITLB_MISS ] = {
+ 0x0000000010200000ULL
+ },
+ [ PPC970MP_PME_PM_FXU1_BUSY_FXU0_IDLE ] = {
+ 0x0000004000000000ULL
+ },
+ [ PPC970MP_PME_PM_GRP_DISP_VALID ] = {
+ 0x0000000100000100ULL
+ },
+ [ PPC970MP_PME_PM_MRK_GRP_DISP ] = {
+ 0x0000000400000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU_FLUSH_UST ] = {
+ 0x0000000000000008ULL
+ },
+ [ PPC970MP_PME_PM_FXU1_FIN ] = {
+ 0x0000008000000100ULL
+ },
+ [ PPC970MP_PME_PM_GRP_CMPL ] = {
+ 0x0000000020080001ULL
+ },
+ [ PPC970MP_PME_PM_FPU_FRSP_FCONV ] = {
+ 0x0000000000000020ULL
+ },
+ [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_SRQ ] = {
+ 0x0000002000000000ULL
+ },
+ [ PPC970MP_PME_PM_CMPLU_STALL_OTHER ] = {
+ 0x0000040000000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU_LMQ_FULL_CYC ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_ST_REF_L1_LSU0 ] = {
+ 0x0000000000030000ULL
+ },
+ [ PPC970MP_PME_PM_LSU0_DERAT_MISS ] = {
+ 0x0000000000040000ULL
+ },
+ [ PPC970MP_PME_PM_LSU_SRQ_SYNC_CYC ] = {
+ 0x0000000040000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU_STALL3 ] = {
+ 0x0000000000000020ULL
+ },
+ [ PPC970MP_PME_PM_LSU_REJECT_ERAT_MISS ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_MRK_DATA_FROM_L2 ] = {
+ 0x0004000000000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU0_FLUSH_SRQ ] = {
+ 0x0000000000004000ULL
+ },
+ [ PPC970MP_PME_PM_FPU0_FMOV_FEST ] = {
+ 0x0000000000001000ULL
+ },
+ [ PPC970MP_PME_PM_IOPS_CMPL ] = {
+ 0x0000100000000000ULL
+ },
+ [ PPC970MP_PME_PM_LD_REF_L1_LSU0 ] = {
+ 0x0000000000008000ULL
+ },
+ [ PPC970MP_PME_PM_LSU1_FLUSH_SRQ ] = {
+ 0x0000000000004000ULL
+ },
+ [ PPC970MP_PME_PM_CMPLU_STALL_DIV ] = {
+ 0x0000080000000000ULL
+ },
+ [ PPC970MP_PME_PM_GRP_BR_MPRED ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU_LMQ_S0_ALLOC ] = {
+ 0x0000400008000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU0_REJECT_LMQ_FULL ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_ST_REF_L1 ] = {
+ 0x000000010260000eULL
+ },
+ [ PPC970MP_PME_PM_MRK_VMX_FIN ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU_SRQ_EMPTY_CYC ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU1_STF ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_RUN_CYC ] = {
+ 0x0000000004000001ULL
+ },
+ [ PPC970MP_PME_PM_LSU_LMQ_S0_VALID ] = {
+ 0x0000400008000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU0_LDF ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU_LRQ_S0_VALID ] = {
+ 0x0000000010000000ULL
+ },
+ [ PPC970MP_PME_PM_PMC3_OVERFLOW ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_MRK_IMR_RELOAD ] = {
+ 0x0000001000000000ULL
+ },
+ [ PPC970MP_PME_PM_MRK_GRP_TIMEO ] = {
+ 0x0000000800000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU_FMOV_FEST ] = {
+ 0x0000000000100010ULL
+ },
+ [ PPC970MP_PME_PM_GRP_DISP_BLK_SB_CYC ] = {
+ 0x0000000000000040ULL
+ },
+ [ PPC970MP_PME_PM_XER_MAP_FULL_CYC ] = {
+ 0x0000000000000040ULL
+ },
+ [ PPC970MP_PME_PM_ST_MISS_L1 ] = {
+ 0x0000000000610000ULL
+ },
+ [ PPC970MP_PME_PM_STOP_COMPLETION ] = {
+ 0x0000000000000201ULL
+ },
+ [ PPC970MP_PME_PM_MRK_GRP_CMPL ] = {
+ 0x0000000a00000000ULL
+ },
+ [ PPC970MP_PME_PM_ISLB_MISS ] = {
+ 0x0000000004000000ULL
+ },
+ [ PPC970MP_PME_PM_SUSPENDED ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_CYC ] = {
+ 0x0007ffffffffffffULL
+ },
+ [ PPC970MP_PME_PM_LD_MISS_L1_LSU1 ] = {
+ 0x0003000000008000ULL
+ },
+ [ PPC970MP_PME_PM_STCX_FAIL ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU1_SRQ_STFWD ] = {
+ 0x0000000000020000ULL
+ },
+ [ PPC970MP_PME_PM_GRP_DISP ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_L2_PREF ] = {
+ 0x0000000010000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU1_DENORM ] = {
+ 0x0000000000001000ULL
+ },
+ [ PPC970MP_PME_PM_DATA_FROM_L2 ] = {
+ 0x0003000008000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU0_FPSCR ] = {
+ 0x0000000000002000ULL
+ },
+ [ PPC970MP_PME_PM_MRK_DATA_FROM_L25_MOD ] = {
+ 0x0004000000000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU0_FSQRT ] = {
+ 0x0000000000000800ULL
+ },
+ [ PPC970MP_PME_PM_LD_REF_L1 ] = {
+ 0x000304004260000eULL
+ },
+ [ PPC970MP_PME_PM_MRK_L1_RELOAD_VALID ] = {
+ 0x0004000000000000ULL
+ },
+ [ PPC970MP_PME_PM_1PLUS_PPC_CMPL ] = {
+ 0x0001000000080001ULL
+ },
+ [ PPC970MP_PME_PM_INST_FROM_L1 ] = {
+ 0x0000010080000000ULL
+ },
+ [ PPC970MP_PME_PM_EE_OFF_EXT_INT ] = {
+ 0x0000000000000200ULL
+ },
+ [ PPC970MP_PME_PM_PMC6_OVERFLOW ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU_LRQ_FULL_CYC ] = {
+ 0x0000000000000080ULL
+ },
+ [ PPC970MP_PME_PM_IC_PREF_INSTALL ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_DC_PREF_OUT_OF_STREAMS ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_SRQ ] = {
+ 0x0000002000000000ULL
+ },
+ [ PPC970MP_PME_PM_GCT_FULL_CYC ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_INST_FROM_MEM ] = {
+ 0x0000810020000000ULL
+ },
+ [ PPC970MP_PME_PM_FLUSH_LSU_BR_MPRED ] = {
+ 0x0000020000000000ULL
+ },
+ [ PPC970MP_PME_PM_FXU_BUSY ] = {
+ 0x000008c000000000ULL
+ },
+ [ PPC970MP_PME_PM_ST_REF_L1_LSU1 ] = {
+ 0x0000000000030000ULL
+ },
+ [ PPC970MP_PME_PM_MRK_LD_MISS_L1 ] = {
+ 0x0000000200000000ULL
+ },
+ [ PPC970MP_PME_PM_L1_WRITE_CYC ] = {
+ 0x0000200000000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU1_BUSY ] = {
+ 0x0000020000000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU_REJECT_LMQ_FULL ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_CMPLU_STALL_FDIV ] = {
+ 0x0000100000000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU_ALL ] = {
+ 0x0000000000000020ULL
+ },
+ [ PPC970MP_PME_PM_LSU_SRQ_S0_ALLOC ] = {
+ 0x0000000040000000ULL
+ },
+ [ PPC970MP_PME_PM_INST_FROM_L25_SHR ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_GRP_MRK ] = {
+ 0x0000000600000000ULL
+ },
+ [ PPC970MP_PME_PM_BR_MPRED_CR ] = {
+ 0x0000800005000000ULL
+ },
+ [ PPC970MP_PME_PM_DC_PREF_STREAM_ALLOC ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU1_FIN ] = {
+ 0x0000000000802800ULL
+ },
+ [ PPC970MP_PME_PM_LSU_REJECT_SRQ ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_BR_MPRED_TA ] = {
+ 0x0000a00005000000ULL
+ },
+ [ PPC970MP_PME_PM_CRQ_FULL_CYC ] = {
+ 0x0000000000000040ULL
+ },
+ [ PPC970MP_PME_PM_LD_MISS_L1 ] = {
+ 0x0000040043600006ULL
+ },
+ [ PPC970MP_PME_PM_INST_FROM_PREF ] = {
+ 0x0000810000000000ULL
+ },
+ [ PPC970MP_PME_PM_STCX_PASS ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_DC_INV_L2 ] = {
+ 0x0000000020010006ULL
+ },
+ [ PPC970MP_PME_PM_LSU_SRQ_FULL_CYC ] = {
+ 0x0000000000000080ULL
+ },
+ [ PPC970MP_PME_PM_LSU0_FLUSH_LRQ ] = {
+ 0x0000000000004000ULL
+ },
+ [ PPC970MP_PME_PM_LSU_SRQ_S0_VALID ] = {
+ 0x0000000040000000ULL
+ },
+ [ PPC970MP_PME_PM_LARX_LSU0 ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_GCT_EMPTY_CYC ] = {
+ 0x0000200100080200ULL
+ },
+ [ PPC970MP_PME_PM_FPU1_ALL ] = {
+ 0x0000000000000800ULL
+ },
+ [ PPC970MP_PME_PM_FPU1_FSQRT ] = {
+ 0x0000000000000800ULL
+ },
+ [ PPC970MP_PME_PM_FPU_FIN ] = {
+ 0x0000080000100010ULL
+ },
+ [ PPC970MP_PME_PM_LSU_SRQ_STFWD ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU1 ] = {
+ 0x0000002000000000ULL
+ },
+ [ PPC970MP_PME_PM_FXU0_FIN ] = {
+ 0x0000008000000100ULL
+ },
+ [ PPC970MP_PME_PM_MRK_FPU_FIN ] = {
+ 0x0000000400000000ULL
+ },
+ [ PPC970MP_PME_PM_PMC5_OVERFLOW ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_SNOOP_TLBIE ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_FPU1_FRSP_FCONV ] = {
+ 0x0000000000000400ULL
+ },
+ [ PPC970MP_PME_PM_FPU0_FDIV ] = {
+ 0x0000000000000400ULL
+ },
+ [ PPC970MP_PME_PM_LD_REF_L1_LSU1 ] = {
+ 0x0000000000008000ULL
+ },
+ [ PPC970MP_PME_PM_HV_CYC ] = {
+ 0x0000000020080000ULL
+ },
+ [ PPC970MP_PME_PM_LR_CTR_MAP_FULL_CYC ] = {
+ 0x0000000000000040ULL
+ },
+ [ PPC970MP_PME_PM_FPU_DENORM ] = {
+ 0x0000000000000020ULL
+ },
+ [ PPC970MP_PME_PM_LSU0_REJECT_SRQ ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU1_REJECT_SRQ ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU1_DERAT_MISS ] = {
+ 0x0000000000040000ULL
+ },
+ [ PPC970MP_PME_PM_IC_PREF_REQ ] = {
+ 0x0000000000000000ULL
+ },
+ [ PPC970MP_PME_PM_MRK_LSU_FIN ] = {
+ 0x0000000400000000ULL
+ },
+ [ PPC970MP_PME_PM_MRK_DATA_FROM_MEM ] = {
+ 0x0004000000000000ULL
+ },
+ [ PPC970MP_PME_PM_CMPLU_STALL_DCACHE_MISS ] = {
+ 0x0000040000000000ULL
+ },
+ [ PPC970MP_PME_PM_LSU0_FLUSH_UST ] = {
+ 0x0000000000010000ULL
+ },
+ [ PPC970MP_PME_PM_LSU_FLUSH_LRQ ] = {
+ 0x0000000000000008ULL
+ },
+ [ PPC970MP_PME_PM_LSU_FLUSH_SRQ ] = {
+ 0x0000000000000008ULL
+ }
+};
+
+static const pme_power_entry_t ppc970mp_pe[] = {
[ PPC970MP_PME_PM_LSU_REJECT_RELOAD_CDF ] = {
.pme_name = "PM_LSU_REJECT_RELOAD_CDF",
+ .pme_code = 0x6920,
.pme_short_desc = "LSU reject due to reload CDF or tag update collision",
.pme_long_desc = "LSU reject due to reload CDF or tag update collision",
- .pme_event_ids = { -1, -1, -1, -1, -1, 66, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_REJECT_RELOAD_CDF],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_REJECT_RELOAD_CDF]
},
-#define PPC970MP_PME_PM_MRK_LSU_SRQ_INST_VALID 1
[ PPC970MP_PME_PM_MRK_LSU_SRQ_INST_VALID ] = {
.pme_name = "PM_MRK_LSU_SRQ_INST_VALID",
+ .pme_code = 0x936,
.pme_short_desc = "Marked instruction valid in SRQ",
.pme_long_desc = "This signal is asserted every cycle when a marked request is resident in the Store Request Queue",
- .pme_event_ids = { -1, -1, 61, 61, -1, -1, 60, 61 },
- .pme_group_vector = {
- 0x0000000800000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LSU_SRQ_INST_VALID],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LSU_SRQ_INST_VALID]
},
-#define PPC970MP_PME_PM_FPU1_SINGLE 2
[ PPC970MP_PME_PM_FPU1_SINGLE ] = {
.pme_name = "PM_FPU1_SINGLE",
+ .pme_code = 0x127,
.pme_short_desc = "FPU1 executed single precision instruction",
.pme_long_desc = "This signal is active for one cycle when fp1 is executing single precision instruction.",
- .pme_event_ids = { 23, 22, -1, -1, 23, 22, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_SINGLE],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_SINGLE]
},
-#define PPC970MP_PME_PM_FPU0_STALL3 3
[ PPC970MP_PME_PM_FPU0_STALL3 ] = {
.pme_name = "PM_FPU0_STALL3",
+ .pme_code = 0x121,
.pme_short_desc = "FPU0 stalled in pipe3",
.pme_long_desc = "This signal indicates that fp0 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. ",
- .pme_event_ids = { 15, 14, -1, -1, 15, 14, -1, -1 },
- .pme_group_vector = {
- 0x0000000000002000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_STALL3],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_STALL3]
},
-#define PPC970MP_PME_PM_TB_BIT_TRANS 4
[ PPC970MP_PME_PM_TB_BIT_TRANS ] = {
.pme_name = "PM_TB_BIT_TRANS",
+ .pme_code = 0x8005,
.pme_short_desc = "Time Base bit transition",
.pme_long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 ",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 67 },
- .pme_group_vector = {
- 0x0000000000080000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_TB_BIT_TRANS],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_TB_BIT_TRANS]
},
-#define PPC970MP_PME_PM_GPR_MAP_FULL_CYC 5
[ PPC970MP_PME_PM_GPR_MAP_FULL_CYC ] = {
.pme_name = "PM_GPR_MAP_FULL_CYC",
+ .pme_code = 0x335,
.pme_short_desc = "Cycles GPR mapper full",
.pme_long_desc = "The ISU sends a signal indicating that the gpr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.",
- .pme_event_ids = { -1, -1, 27, 28, -1, -1, 27, 27 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GPR_MAP_FULL_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GPR_MAP_FULL_CYC]
},
-#define PPC970MP_PME_PM_MRK_ST_CMPL 6
[ PPC970MP_PME_PM_MRK_ST_CMPL ] = {
.pme_name = "PM_MRK_ST_CMPL",
+ .pme_code = 0x1003,
.pme_short_desc = "Marked store instruction completed",
.pme_long_desc = "A sampled store has completed (data home)",
- .pme_event_ids = { 78, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_ST_CMPL],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_ST_CMPL]
},
-#define PPC970MP_PME_PM_FPU0_STF 7
[ PPC970MP_PME_PM_FPU0_STF ] = {
.pme_name = "PM_FPU0_STF",
+ .pme_code = 0x122,
.pme_short_desc = "FPU0 executed store instruction",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing a store instruction.",
- .pme_event_ids = { 16, 15, -1, -1, 16, 15, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_STF],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_STF]
},
-#define PPC970MP_PME_PM_FPU1_FMA 8
[ PPC970MP_PME_PM_FPU1_FMA ] = {
.pme_name = "PM_FPU1_FMA",
+ .pme_code = 0x105,
.pme_short_desc = "FPU1 executed multiply-add instruction",
.pme_long_desc = "This signal is active for one cycle when fp1 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 20, 19, -1, -1, 20, 19, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000400ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_FMA],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_FMA]
},
-#define PPC970MP_PME_PM_LSU1_FLUSH_ULD 9
[ PPC970MP_PME_PM_LSU1_FLUSH_ULD ] = {
.pme_name = "PM_LSU1_FLUSH_ULD",
+ .pme_code = 0x804,
.pme_short_desc = "LSU1 unaligned load flushes",
.pme_long_desc = "A load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { 57, 56, -1, -1, 58, 55, -1, -1 },
- .pme_group_vector = {
- 0x0000000000008000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_FLUSH_ULD],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_FLUSH_ULD]
},
-#define PPC970MP_PME_PM_MRK_INST_FIN 10
[ PPC970MP_PME_PM_MRK_INST_FIN ] = {
.pme_name = "PM_MRK_INST_FIN",
+ .pme_code = 0x7005,
.pme_short_desc = "Marked instruction finished",
.pme_long_desc = "One of the execution units finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 50, -1 },
- .pme_group_vector = {
- 0x0004000200000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_INST_FIN],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_INST_FIN]
},
-#define PPC970MP_PME_PM_MRK_LSU0_FLUSH_UST 11
[ PPC970MP_PME_PM_MRK_LSU0_FLUSH_UST ] = {
.pme_name = "PM_MRK_LSU0_FLUSH_UST",
+ .pme_code = 0x711,
.pme_short_desc = "LSU0 marked unaligned store flushes",
.pme_long_desc = "A marked store was flushed from unit 0 because it was unaligned",
- .pme_event_ids = { -1, -1, 56, 56, -1, -1, 55, 55 },
- .pme_group_vector = {
- 0x0000001000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LSU0_FLUSH_UST],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LSU0_FLUSH_UST]
},
-#define PPC970MP_PME_PM_LSU_LRQ_S0_ALLOC 12
[ PPC970MP_PME_PM_LSU_LRQ_S0_ALLOC ] = {
.pme_name = "PM_LSU_LRQ_S0_ALLOC",
+ .pme_code = 0x826,
.pme_short_desc = "LRQ slot 0 allocated",
.pme_long_desc = "LRQ slot zero was allocated",
- .pme_event_ids = { 65, 65, -1, -1, 66, 64, -1, -1 },
- .pme_group_vector = {
- 0x0000000010000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_LRQ_S0_ALLOC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_LRQ_S0_ALLOC]
},
-#define PPC970MP_PME_PM_FPU_FDIV 13
[ PPC970MP_PME_PM_FPU_FDIV ] = {
.pme_name = "PM_FPU_FDIV",
+ .pme_code = 0x1100,
.pme_short_desc = "FPU executed FDIV instruction",
.pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when FPU is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs. Combined Unit 0 + Unit 1",
- .pme_event_ids = { 27, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000100000900010ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_FDIV],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_FDIV]
},
-#define PPC970MP_PME_PM_FPU0_FULL_CYC 14
[ PPC970MP_PME_PM_FPU0_FULL_CYC ] = {
.pme_name = "PM_FPU0_FULL_CYC",
+ .pme_code = 0x303,
.pme_short_desc = "Cycles FPU0 issue queue full",
.pme_long_desc = "The issue queue for FPU unit 0 cannot accept any more instructions. Issue is stopped",
- .pme_event_ids = { 13, 12, -1, -1, 13, 12, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000080ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_FULL_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_FULL_CYC]
},
-#define PPC970MP_PME_PM_FPU_SINGLE 15
[ PPC970MP_PME_PM_FPU_SINGLE ] = {
.pme_name = "PM_FPU_SINGLE",
+ .pme_code = 0x5120,
.pme_short_desc = "FPU executed single precision instruction",
.pme_long_desc = "FPU is executing single precision instruction. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, -1, -1, 27, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_SINGLE],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_SINGLE]
},
-#define PPC970MP_PME_PM_FPU0_FMA 16
[ PPC970MP_PME_PM_FPU0_FMA ] = {
.pme_name = "PM_FPU0_FMA",
+ .pme_code = 0x101,
.pme_short_desc = "FPU0 executed multiply-add instruction",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 11, 10, -1, -1, 11, 10, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000400ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_FMA],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_FMA]
},
-#define PPC970MP_PME_PM_MRK_LSU1_FLUSH_ULD 17
[ PPC970MP_PME_PM_MRK_LSU1_FLUSH_ULD ] = {
.pme_name = "PM_MRK_LSU1_FLUSH_ULD",
+ .pme_code = 0x714,
.pme_short_desc = "LSU1 marked unaligned load flushes",
.pme_long_desc = "A marked load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { -1, -1, 59, 59, -1, -1, 58, 58 },
- .pme_group_vector = {
- 0x0000001000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LSU1_FLUSH_ULD],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LSU1_FLUSH_ULD]
},
-#define PPC970MP_PME_PM_LSU1_FLUSH_LRQ 18
[ PPC970MP_PME_PM_LSU1_FLUSH_LRQ ] = {
.pme_name = "PM_LSU1_FLUSH_LRQ",
+ .pme_code = 0x806,
.pme_short_desc = "LSU1 LRQ flushes",
.pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { 55, 54, -1, -1, 56, 53, -1, -1 },
- .pme_group_vector = {
- 0x0000000000004000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_FLUSH_LRQ],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_FLUSH_LRQ]
},
-#define PPC970MP_PME_PM_DTLB_MISS 19
[ PPC970MP_PME_PM_DTLB_MISS ] = {
.pme_name = "PM_DTLB_MISS",
+ .pme_code = 0x704,
.pme_short_desc = "Data TLB misses",
.pme_long_desc = "A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.",
- .pme_event_ids = { 6, 5, -1, -1, 6, 5, -1, -1 },
- .pme_group_vector = {
- 0x0000000010600000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_DTLB_MISS],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_DTLB_MISS]
},
-#define PPC970MP_PME_PM_CMPLU_STALL_FXU 20
[ PPC970MP_PME_PM_CMPLU_STALL_FXU ] = {
.pme_name = "PM_CMPLU_STALL_FXU",
+ .pme_code = 0x508b,
.pme_short_desc = "Completion stall caused by FXU instruction",
.pme_long_desc = "Completion stall caused by FXU instruction",
- .pme_event_ids = { -1, -1, -1, -1, 85, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000080000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CMPLU_STALL_FXU],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CMPLU_STALL_FXU]
},
-#define PPC970MP_PME_PM_MRK_ST_MISS_L1 21
[ PPC970MP_PME_PM_MRK_ST_MISS_L1 ] = {
.pme_name = "PM_MRK_ST_MISS_L1",
+ .pme_code = 0x723,
.pme_short_desc = "Marked L1 D cache store misses",
.pme_long_desc = "A marked store missed the dcache",
- .pme_event_ids = { 79, 75, -1, -1, 76, 76, -1, -1 },
- .pme_group_vector = {
- 0x0000001000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_ST_MISS_L1],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_ST_MISS_L1]
},
-#define PPC970MP_PME_PM_EXT_INT 22
[ PPC970MP_PME_PM_EXT_INT ] = {
.pme_name = "PM_EXT_INT",
+ .pme_code = 0x8002,
.pme_short_desc = "External interrupts",
.pme_long_desc = "An external interrupt occurred",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 10 },
- .pme_group_vector = {
- 0x0000000000000200ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_EXT_INT],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_EXT_INT]
},
-#define PPC970MP_PME_PM_MRK_LSU1_FLUSH_LRQ 23
[ PPC970MP_PME_PM_MRK_LSU1_FLUSH_LRQ ] = {
.pme_name = "PM_MRK_LSU1_FLUSH_LRQ",
+ .pme_code = 0x716,
.pme_short_desc = "LSU1 marked LRQ flushes",
.pme_long_desc = "A marked load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { -1, -1, 57, 57, -1, -1, 56, 56 },
- .pme_group_vector = {
- 0x0000002000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LSU1_FLUSH_LRQ],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LSU1_FLUSH_LRQ]
},
-#define PPC970MP_PME_PM_MRK_ST_GPS 24
[ PPC970MP_PME_PM_MRK_ST_GPS ] = {
.pme_name = "PM_MRK_ST_GPS",
+ .pme_code = 0x6003,
.pme_short_desc = "Marked store sent to GPS",
.pme_long_desc = "A sampled store has been sent to the memory subsystem",
- .pme_event_ids = { -1, -1, -1, -1, -1, 75, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_ST_GPS],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_ST_GPS]
},
-#define PPC970MP_PME_PM_GRP_DISP_SUCCESS 25
[ PPC970MP_PME_PM_GRP_DISP_SUCCESS ] = {
.pme_name = "PM_GRP_DISP_SUCCESS",
+ .pme_code = 0x5001,
.pme_short_desc = "Group dispatch success",
.pme_long_desc = "Number of groups sucessfully dispatched (not rejected)",
- .pme_event_ids = { -1, -1, -1, -1, 33, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GRP_DISP_SUCCESS],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GRP_DISP_SUCCESS]
},
-#define PPC970MP_PME_PM_LSU1_LDF 26
[ PPC970MP_PME_PM_LSU1_LDF ] = {
.pme_name = "PM_LSU1_LDF",
+ .pme_code = 0x734,
.pme_short_desc = "LSU1 executed Floating Point load instruction",
.pme_long_desc = "A floating point load was executed from LSU unit 1",
- .pme_event_ids = { -1, -1, 42, 40, -1, -1, 40, 41 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_LDF],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_LDF]
},
-#define PPC970MP_PME_PM_LSU0_SRQ_STFWD 27
[ PPC970MP_PME_PM_LSU0_SRQ_STFWD ] = {
.pme_name = "PM_LSU0_SRQ_STFWD",
+ .pme_code = 0x820,
.pme_short_desc = "LSU0 SRQ store forwarded",
.pme_long_desc = "Data from a store instruction was forwarded to a load on unit 0",
- .pme_event_ids = { 53, 52, -1, -1, 54, 51, -1, -1 },
- .pme_group_vector = {
- 0x0000000000020000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_SRQ_STFWD],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_SRQ_STFWD]
},
-#define PPC970MP_PME_PM_CR_MAP_FULL_CYC 28
[ PPC970MP_PME_PM_CR_MAP_FULL_CYC ] = {
.pme_name = "PM_CR_MAP_FULL_CYC",
+ .pme_code = 0x304,
.pme_short_desc = "Cycles CR logical operation mapper full",
.pme_long_desc = "The ISU sends a signal indicating that the cr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.",
- .pme_event_ids = { 1, 1, -1, -1, 2, 1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000040ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CR_MAP_FULL_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CR_MAP_FULL_CYC]
},
-#define PPC970MP_PME_PM_MRK_LSU0_FLUSH_ULD 29
[ PPC970MP_PME_PM_MRK_LSU0_FLUSH_ULD ] = {
.pme_name = "PM_MRK_LSU0_FLUSH_ULD",
+ .pme_code = 0x710,
.pme_short_desc = "LSU0 marked unaligned load flushes",
.pme_long_desc = "A marked load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { -1, -1, 55, 55, -1, -1, 54, 54 },
- .pme_group_vector = {
- 0x0000001000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LSU0_FLUSH_ULD],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LSU0_FLUSH_ULD]
},
-#define PPC970MP_PME_PM_LSU_DERAT_MISS 30
[ PPC970MP_PME_PM_LSU_DERAT_MISS ] = {
.pme_name = "PM_LSU_DERAT_MISS",
+ .pme_code = 0x6700,
.pme_short_desc = "DERAT misses",
.pme_long_desc = "Total D-ERAT Misses (Unit 0 + Unit 1). Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.",
- .pme_event_ids = { -1, -1, -1, -1, -1, 62, -1, -1 },
- .pme_group_vector = {
- 0x0000040100000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_DERAT_MISS],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_DERAT_MISS]
},
-#define PPC970MP_PME_PM_FPU0_SINGLE 31
[ PPC970MP_PME_PM_FPU0_SINGLE ] = {
.pme_name = "PM_FPU0_SINGLE",
+ .pme_code = 0x123,
.pme_short_desc = "FPU0 executed single precision instruction",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing single precision instruction.",
- .pme_event_ids = { 14, 13, -1, -1, 14, 13, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_SINGLE],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_SINGLE]
},
-#define PPC970MP_PME_PM_FPU1_FDIV 32
[ PPC970MP_PME_PM_FPU1_FDIV ] = {
.pme_name = "PM_FPU1_FDIV",
+ .pme_code = 0x104,
.pme_short_desc = "FPU1 executed FDIV instruction",
.pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp1 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.",
- .pme_event_ids = { 19, 18, -1, -1, 19, 18, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000400ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_FDIV],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_FDIV]
},
-#define PPC970MP_PME_PM_FPU1_FEST 33
[ PPC970MP_PME_PM_FPU1_FEST ] = {
.pme_name = "PM_FPU1_FEST",
+ .pme_code = 0x116,
.pme_short_desc = "FPU1 executed FEST instruction",
.pme_long_desc = "This signal is active for one cycle when fp1 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ",
- .pme_event_ids = { -1, -1, 17, 18, -1, -1, 17, 18 },
- .pme_group_vector = {
- 0x0000000000001000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_FEST],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_FEST]
},
-#define PPC970MP_PME_PM_FPU0_FRSP_FCONV 34
[ PPC970MP_PME_PM_FPU0_FRSP_FCONV ] = {
.pme_name = "PM_FPU0_FRSP_FCONV",
+ .pme_code = 0x111,
.pme_short_desc = "FPU0 executed FRSP or FCONV instructions",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { -1, -1, 16, 17, -1, -1, 16, 17 },
- .pme_group_vector = {
- 0x0000000000000400ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_FRSP_FCONV],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_FRSP_FCONV]
},
-#define PPC970MP_PME_PM_GCT_EMPTY_SRQ_FULL 35
[ PPC970MP_PME_PM_GCT_EMPTY_SRQ_FULL ] = {
.pme_name = "PM_GCT_EMPTY_SRQ_FULL",
+ .pme_code = 0x200b,
.pme_short_desc = "GCT empty caused by SRQ full",
.pme_long_desc = "GCT empty caused by SRQ full",
- .pme_event_ids = { -1, 27, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000080000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GCT_EMPTY_SRQ_FULL],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GCT_EMPTY_SRQ_FULL]
},
-#define PPC970MP_PME_PM_MRK_ST_CMPL_INT 36
[ PPC970MP_PME_PM_MRK_ST_CMPL_INT ] = {
.pme_name = "PM_MRK_ST_CMPL_INT",
+ .pme_code = 0x3003,
.pme_short_desc = "Marked store completed with intervention",
.pme_long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention",
- .pme_event_ids = { -1, -1, 62, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_ST_CMPL_INT],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_ST_CMPL_INT]
},
-#define PPC970MP_PME_PM_FLUSH_BR_MPRED 37
[ PPC970MP_PME_PM_FLUSH_BR_MPRED ] = {
.pme_name = "PM_FLUSH_BR_MPRED",
+ .pme_code = 0x316,
.pme_short_desc = "Flush caused by branch mispredict",
.pme_long_desc = "Flush caused by branch mispredict",
- .pme_event_ids = { -1, -1, 10, 11, -1, -1, 10, 11 },
- .pme_group_vector = {
- 0x0000200000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FLUSH_BR_MPRED],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FLUSH_BR_MPRED]
},
-#define PPC970MP_PME_PM_FXU_FIN 38
[ PPC970MP_PME_PM_FXU_FIN ] = {
.pme_name = "PM_FXU_FIN",
+ .pme_code = 0x3330,
.pme_short_desc = "FXU produced a result",
.pme_long_desc = "The fixed point unit (Unit 0 + Unit 1) finished an instruction. Instructions that finish may not necessary complete.",
- .pme_event_ids = { -1, -1, 26, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000084000100000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FXU_FIN],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FXU_FIN]
},
-#define PPC970MP_PME_PM_FPU_STF 39
[ PPC970MP_PME_PM_FPU_STF ] = {
.pme_name = "PM_FPU_STF",
+ .pme_code = 0x6120,
.pme_short_desc = "FPU executed store instruction",
.pme_long_desc = "FPU is executing a store instruction. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, -1, -1, -1, 26, -1, -1 },
- .pme_group_vector = {
- 0x0000000000800020ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_STF],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_STF]
},
-#define PPC970MP_PME_PM_DSLB_MISS 40
[ PPC970MP_PME_PM_DSLB_MISS ] = {
.pme_name = "PM_DSLB_MISS",
+ .pme_code = 0x705,
.pme_short_desc = "Data SLB misses",
.pme_long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve",
- .pme_event_ids = { 5, 4, -1, -1, 5, 4, -1, -1 },
- .pme_group_vector = {
- 0x0000000004000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_DSLB_MISS],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_DSLB_MISS]
},
-#define PPC970MP_PME_PM_FXLS1_FULL_CYC 41
[ PPC970MP_PME_PM_FXLS1_FULL_CYC ] = {
.pme_name = "PM_FXLS1_FULL_CYC",
+ .pme_code = 0x314,
.pme_short_desc = "Cycles FXU1/LS1 queue full",
.pme_long_desc = "The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped",
- .pme_event_ids = { -1, -1, 23, 24, -1, -1, 23, 24 },
- .pme_group_vector = {
- 0x0000008000000080ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FXLS1_FULL_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FXLS1_FULL_CYC]
},
-#define PPC970MP_PME_PM_CMPLU_STALL_FPU 42
[ PPC970MP_PME_PM_CMPLU_STALL_FPU ] = {
.pme_name = "PM_CMPLU_STALL_FPU",
+ .pme_code = 0x704b,
.pme_short_desc = "Completion stall caused by FPU instruction",
.pme_long_desc = "Completion stall caused by FPU instruction",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 67, -1 },
- .pme_group_vector = {
- 0x0000100000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CMPLU_STALL_FPU],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CMPLU_STALL_FPU]
},
-#define PPC970MP_PME_PM_LSU_LMQ_LHR_MERGE 43
[ PPC970MP_PME_PM_LSU_LMQ_LHR_MERGE ] = {
.pme_name = "PM_LSU_LMQ_LHR_MERGE",
+ .pme_code = 0x935,
.pme_short_desc = "LMQ LHR merges",
.pme_long_desc = "A dcache miss occured for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.",
- .pme_event_ids = { -1, -1, 45, 43, -1, -1, 43, 45 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_LMQ_LHR_MERGE],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_LMQ_LHR_MERGE]
},
-#define PPC970MP_PME_PM_MRK_STCX_FAIL 44
[ PPC970MP_PME_PM_MRK_STCX_FAIL ] = {
.pme_name = "PM_MRK_STCX_FAIL",
+ .pme_code = 0x726,
.pme_short_desc = "Marked STCX failed",
.pme_long_desc = "A marked stcx (stwcx or stdcx) failed",
- .pme_event_ids = { 77, 74, -1, -1, 75, 74, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_STCX_FAIL],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_STCX_FAIL]
},
-#define PPC970MP_PME_PM_FXU0_BUSY_FXU1_IDLE 45
[ PPC970MP_PME_PM_FXU0_BUSY_FXU1_IDLE ] = {
.pme_name = "PM_FXU0_BUSY_FXU1_IDLE",
+ .pme_code = 0x7002,
.pme_short_desc = "FXU0 busy FXU1 idle",
.pme_long_desc = "FXU0 is busy while FXU1 was idle",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 24, -1 },
- .pme_group_vector = {
- 0x0000004000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FXU0_BUSY_FXU1_IDLE],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FXU0_BUSY_FXU1_IDLE]
},
-#define PPC970MP_PME_PM_CMPLU_STALL_LSU 46
[ PPC970MP_PME_PM_CMPLU_STALL_LSU ] = {
.pme_name = "PM_CMPLU_STALL_LSU",
+ .pme_code = 0x504b,
.pme_short_desc = "Completion stall caused by LSU instruction",
.pme_long_desc = "Completion stall caused by LSU instruction",
- .pme_event_ids = { -1, -1, -1, -1, 84, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000020000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CMPLU_STALL_LSU],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CMPLU_STALL_LSU]
},
-#define PPC970MP_PME_PM_MRK_DATA_FROM_L25_SHR 47
[ PPC970MP_PME_PM_MRK_DATA_FROM_L25_SHR ] = {
.pme_name = "PM_MRK_DATA_FROM_L25_SHR",
+ .pme_code = 0x5937,
.pme_short_desc = "Marked data loaded from L2.5 shared",
.pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a marked demand load",
- .pme_event_ids = { -1, -1, -1, -1, 92, -1, -1, -1 },
- .pme_group_vector = {
- 0x0004000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_DATA_FROM_L25_SHR],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_DATA_FROM_L25_SHR]
},
-#define PPC970MP_PME_PM_LSU_FLUSH_ULD 48
[ PPC970MP_PME_PM_LSU_FLUSH_ULD ] = {
.pme_name = "PM_LSU_FLUSH_ULD",
+ .pme_code = 0x1800,
.pme_short_desc = "LRQ unaligned load flushes",
.pme_long_desc = "A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { 64, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000008ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_FLUSH_ULD],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_FLUSH_ULD]
},
-#define PPC970MP_PME_PM_MRK_BRU_FIN 49
[ PPC970MP_PME_PM_MRK_BRU_FIN ] = {
.pme_name = "PM_MRK_BRU_FIN",
+ .pme_code = 0x2005,
.pme_short_desc = "Marked instruction BRU processing finished",
.pme_long_desc = "The branch unit finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, 70, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000400000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_BRU_FIN],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_BRU_FIN]
},
-#define PPC970MP_PME_PM_IERAT_XLATE_WR 50
[ PPC970MP_PME_PM_IERAT_XLATE_WR ] = {
.pme_name = "PM_IERAT_XLATE_WR",
+ .pme_code = 0x430,
.pme_short_desc = "Translation written to ierat",
.pme_long_desc = "This signal will be asserted each time the I-ERAT is written. This indicates that an ERAT miss has been serviced. ERAT misses will initiate a sequence resulting in the ERAT being written. ERAT misses that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed, This should be a fairly accurate count of ERAT missed (best available).",
- .pme_event_ids = { -1, -1, 70, 67, -1, -1, 72, 68 },
- .pme_group_vector = {
- 0x0000000080000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_IERAT_XLATE_WR],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_IERAT_XLATE_WR]
},
-#define PPC970MP_PME_PM_GCT_EMPTY_BR_MPRED 51
[ PPC970MP_PME_PM_GCT_EMPTY_BR_MPRED ] = {
.pme_name = "PM_GCT_EMPTY_BR_MPRED",
+ .pme_code = 0x708c,
.pme_short_desc = "GCT empty due to branch mispredict",
.pme_long_desc = "GCT empty due to branch mispredict",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 71, -1 },
- .pme_group_vector = {
- 0x0000200000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GCT_EMPTY_BR_MPRED],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GCT_EMPTY_BR_MPRED]
},
-#define PPC970MP_PME_PM_LSU0_BUSY 52
[ PPC970MP_PME_PM_LSU0_BUSY ] = {
.pme_name = "PM_LSU0_BUSY",
+ .pme_code = 0x823,
.pme_short_desc = "LSU0 busy",
.pme_long_desc = "LSU unit 0 is busy rejecting instructions",
- .pme_event_ids = { 85, 80, -1, -1, 81, 81, -1, -1 },
- .pme_group_vector = {
- 0x0000020003020000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_BUSY],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_BUSY]
},
-#define PPC970MP_PME_PM_DATA_FROM_MEM 53
[ PPC970MP_PME_PM_DATA_FROM_MEM ] = {
.pme_name = "PM_DATA_FROM_MEM",
+ .pme_code = 0x2837,
.pme_short_desc = "Data loaded from memory",
.pme_long_desc = "Data loaded from memory",
- .pme_event_ids = { -1, 87, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0003000008000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_DATA_FROM_MEM],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_DATA_FROM_MEM]
},
-#define PPC970MP_PME_PM_FPR_MAP_FULL_CYC 54
[ PPC970MP_PME_PM_FPR_MAP_FULL_CYC ] = {
.pme_name = "PM_FPR_MAP_FULL_CYC",
+ .pme_code = 0x301,
.pme_short_desc = "Cycles FPR mapper full",
.pme_long_desc = "The ISU sends a signal indicating that the FPR mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.",
- .pme_event_ids = { 7, 6, -1, -1, 7, 6, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPR_MAP_FULL_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPR_MAP_FULL_CYC]
},
-#define PPC970MP_PME_PM_FPU1_FULL_CYC 55
[ PPC970MP_PME_PM_FPU1_FULL_CYC ] = {
.pme_name = "PM_FPU1_FULL_CYC",
+ .pme_code = 0x307,
.pme_short_desc = "Cycles FPU1 issue queue full",
.pme_long_desc = "The issue queue for FPU unit 1 cannot accept any more instructions. Issue is stopped",
- .pme_event_ids = { 22, 21, -1, -1, 22, 21, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000080ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_FULL_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_FULL_CYC]
},
-#define PPC970MP_PME_PM_FPU0_FIN 56
[ PPC970MP_PME_PM_FPU0_FIN ] = {
.pme_name = "PM_FPU0_FIN",
+ .pme_code = 0x113,
.pme_short_desc = "FPU0 produced a result",
.pme_long_desc = "fp0 finished, produced a result This only indicates finish, not completion. ",
- .pme_event_ids = { -1, -1, 13, 14, -1, -1, 13, 14 },
- .pme_group_vector = {
- 0x0000000000802800ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_FIN],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_FIN]
},
-#define PPC970MP_PME_PM_GRP_BR_REDIR 57
[ PPC970MP_PME_PM_GRP_BR_REDIR ] = {
.pme_name = "PM_GRP_BR_REDIR",
+ .pme_code = 0x326,
.pme_short_desc = "Group experienced branch redirect",
.pme_long_desc = "Group experienced branch redirect",
- .pme_event_ids = { 31, 30, -1, -1, 31, 30, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GRP_BR_REDIR],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GRP_BR_REDIR]
},
-#define PPC970MP_PME_PM_GCT_EMPTY_IC_MISS 58
[ PPC970MP_PME_PM_GCT_EMPTY_IC_MISS ] = {
.pme_name = "PM_GCT_EMPTY_IC_MISS",
+ .pme_code = 0x508c,
.pme_short_desc = "GCT empty due to I cache miss",
.pme_long_desc = "GCT empty due to I cache miss",
- .pme_event_ids = { -1, -1, -1, -1, 88, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000200000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GCT_EMPTY_IC_MISS],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GCT_EMPTY_IC_MISS]
},
-#define PPC970MP_PME_PM_THRESH_TIMEO 59
[ PPC970MP_PME_PM_THRESH_TIMEO ] = {
.pme_name = "PM_THRESH_TIMEO",
+ .pme_code = 0x2003,
.pme_short_desc = "Threshold timeout",
.pme_long_desc = "The threshold timer expired",
- .pme_event_ids = { -1, 82, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000200000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_THRESH_TIMEO],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_THRESH_TIMEO]
},
-#define PPC970MP_PME_PM_FPU_FSQRT 60
[ PPC970MP_PME_PM_FPU_FSQRT ] = {
.pme_name = "PM_FPU_FSQRT",
+ .pme_code = 0x6100,
.pme_short_desc = "FPU executed FSQRT instruction",
.pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when FPU is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, -1, -1, -1, 25, -1, -1 },
- .pme_group_vector = {
- 0x0000100000100010ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_FSQRT],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_FSQRT]
},
-#define PPC970MP_PME_PM_MRK_LSU0_FLUSH_LRQ 61
[ PPC970MP_PME_PM_MRK_LSU0_FLUSH_LRQ ] = {
.pme_name = "PM_MRK_LSU0_FLUSH_LRQ",
+ .pme_code = 0x712,
.pme_short_desc = "LSU0 marked LRQ flushes",
.pme_long_desc = "A marked load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { -1, -1, 53, 53, -1, -1, 52, 52 },
- .pme_group_vector = {
- 0x0000002000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LSU0_FLUSH_LRQ],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LSU0_FLUSH_LRQ]
},
-#define PPC970MP_PME_PM_PMC1_OVERFLOW 62
[ PPC970MP_PME_PM_PMC1_OVERFLOW ] = {
.pme_name = "PM_PMC1_OVERFLOW",
+ .pme_code = 0x200a,
.pme_short_desc = "PMC1 Overflow",
.pme_long_desc = "PMC1 Overflow",
- .pme_event_ids = { -1, 76, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_PMC1_OVERFLOW],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_PMC1_OVERFLOW]
},
-#define PPC970MP_PME_PM_FXLS0_FULL_CYC 63
[ PPC970MP_PME_PM_FXLS0_FULL_CYC ] = {
.pme_name = "PM_FXLS0_FULL_CYC",
+ .pme_code = 0x310,
.pme_short_desc = "Cycles FXU0/LS0 queue full",
.pme_long_desc = "The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped",
- .pme_event_ids = { -1, -1, 22, 23, -1, -1, 22, 23 },
- .pme_group_vector = {
- 0x0000008000000080ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FXLS0_FULL_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FXLS0_FULL_CYC]
},
-#define PPC970MP_PME_PM_FPU0_ALL 64
[ PPC970MP_PME_PM_FPU0_ALL ] = {
.pme_name = "PM_FPU0_ALL",
+ .pme_code = 0x103,
.pme_short_desc = "FPU0 executed add",
.pme_long_desc = " mult",
- .pme_event_ids = { 8, 7, -1, -1, 8, 7, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000800ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_ALL],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_ALL]
},
-#define PPC970MP_PME_PM_DATA_TABLEWALK_CYC 65
[ PPC970MP_PME_PM_DATA_TABLEWALK_CYC ] = {
.pme_name = "PM_DATA_TABLEWALK_CYC",
+ .pme_code = 0x707,
.pme_short_desc = "Cycles doing data tablewalks",
.pme_long_desc = "This signal is asserted every cycle when a tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.",
- .pme_event_ids = { 4, 3, -1, -1, 4, 3, -1, -1 },
- .pme_group_vector = {
- 0x0000000020000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_DATA_TABLEWALK_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_DATA_TABLEWALK_CYC]
},
-#define PPC970MP_PME_PM_FPU0_FEST 66
[ PPC970MP_PME_PM_FPU0_FEST ] = {
.pme_name = "PM_FPU0_FEST",
+ .pme_code = 0x112,
.pme_short_desc = "FPU0 executed FEST instruction",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ",
- .pme_event_ids = { -1, -1, 12, 13, -1, -1, 12, 13 },
- .pme_group_vector = {
- 0x0000000000001000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_FEST],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_FEST]
},
-#define PPC970MP_PME_PM_DATA_FROM_L25_MOD 67
[ PPC970MP_PME_PM_DATA_FROM_L25_MOD ] = {
.pme_name = "PM_DATA_FROM_L25_MOD",
+ .pme_code = 0x6837,
.pme_short_desc = "Data loaded from L2.5 modified",
.pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a demand load",
- .pme_event_ids = { -1, -1, -1, -1, -1, 87, -1, -1 },
- .pme_group_vector = {
- 0x0002400000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_DATA_FROM_L25_MOD],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_DATA_FROM_L25_MOD]
},
-#define PPC970MP_PME_PM_LSU0_REJECT_ERAT_MISS 68
[ PPC970MP_PME_PM_LSU0_REJECT_ERAT_MISS ] = {
.pme_name = "PM_LSU0_REJECT_ERAT_MISS",
+ .pme_code = 0x923,
.pme_short_desc = "LSU0 reject due to ERAT miss",
.pme_long_desc = "LSU0 reject due to ERAT miss",
- .pme_event_ids = { 49, 48, -1, -1, 50, 47, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_REJECT_ERAT_MISS],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_REJECT_ERAT_MISS]
},
-#define PPC970MP_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 69
[ PPC970MP_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = {
.pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC",
+ .pme_code = 0x2002,
.pme_short_desc = "Cycles LMQ and SRQ empty",
.pme_long_desc = "Cycles when both the LMQ and SRQ are empty (LSU is idle)",
- .pme_event_ids = { -1, 64, 48, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000480000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC]
},
-#define PPC970MP_PME_PM_LSU0_REJECT_RELOAD_CDF 70
[ PPC970MP_PME_PM_LSU0_REJECT_RELOAD_CDF ] = {
.pme_name = "PM_LSU0_REJECT_RELOAD_CDF",
+ .pme_code = 0x922,
.pme_short_desc = "LSU0 reject due to reload CDF or tag update collision",
.pme_long_desc = "LSU0 reject due to reload CDF or tag update collision",
- .pme_event_ids = { 51, 50, -1, -1, 52, 49, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_REJECT_RELOAD_CDF],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_REJECT_RELOAD_CDF]
},
-#define PPC970MP_PME_PM_FPU_FEST 71
[ PPC970MP_PME_PM_FPU_FEST ] = {
.pme_name = "PM_FPU_FEST",
+ .pme_code = 0x3110,
.pme_short_desc = "FPU executed FEST instruction",
.pme_long_desc = "This signal is active for one cycle when executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. Combined Unit 0 + Unit 1.",
- .pme_event_ids = { -1, -1, 21, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000010ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_FEST],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_FEST]
},
-#define PPC970MP_PME_PM_0INST_FETCH 72
[ PPC970MP_PME_PM_0INST_FETCH ] = {
.pme_name = "PM_0INST_FETCH",
+ .pme_code = 0x442d,
.pme_short_desc = "No instructions fetched",
.pme_long_desc = "No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)",
- .pme_event_ids = { -1, -1, -1, 0, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000010000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_0INST_FETCH],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_0INST_FETCH]
},
-#define PPC970MP_PME_PM_LD_MISS_L1_LSU0 73
[ PPC970MP_PME_PM_LD_MISS_L1_LSU0 ] = {
.pme_name = "PM_LD_MISS_L1_LSU0",
+ .pme_code = 0x812,
.pme_short_desc = "LSU0 L1 D cache load misses",
.pme_long_desc = "A load, executing on unit 0, missed the dcache",
- .pme_event_ids = { -1, -1, 37, 35, -1, -1, 35, 35 },
- .pme_group_vector = {
- 0x0001000000008000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LD_MISS_L1_LSU0],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LD_MISS_L1_LSU0]
},
-#define PPC970MP_PME_PM_LSU1_REJECT_RELOAD_CDF 74
[ PPC970MP_PME_PM_LSU1_REJECT_RELOAD_CDF ] = {
.pme_name = "PM_LSU1_REJECT_RELOAD_CDF",
+ .pme_code = 0x926,
.pme_short_desc = "LSU1 reject due to reload CDF or tag update collision",
.pme_long_desc = "LSU1 reject due to reload CDF or tag update collision",
- .pme_event_ids = { 61, 60, -1, -1, 62, 59, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_REJECT_RELOAD_CDF],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_REJECT_RELOAD_CDF]
},
-#define PPC970MP_PME_PM_L1_PREF 75
[ PPC970MP_PME_PM_L1_PREF ] = {
.pme_name = "PM_L1_PREF",
+ .pme_code = 0x731,
.pme_short_desc = "L1 cache data prefetches",
.pme_long_desc = "A request to prefetch data into the L1 was made",
- .pme_event_ids = { -1, -1, 33, 32, -1, -1, 32, 32 },
- .pme_group_vector = {
- 0x0000000010000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_L1_PREF],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_L1_PREF]
},
-#define PPC970MP_PME_PM_FPU1_STALL3 76
[ PPC970MP_PME_PM_FPU1_STALL3 ] = {
.pme_name = "PM_FPU1_STALL3",
+ .pme_code = 0x125,
.pme_short_desc = "FPU1 stalled in pipe3",
.pme_long_desc = "This signal indicates that fp1 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. ",
- .pme_event_ids = { 24, 23, -1, -1, 24, 23, -1, -1 },
- .pme_group_vector = {
- 0x0000000000002000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_STALL3],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_STALL3]
},
-#define PPC970MP_PME_PM_BRQ_FULL_CYC 77
[ PPC970MP_PME_PM_BRQ_FULL_CYC ] = {
.pme_name = "PM_BRQ_FULL_CYC",
+ .pme_code = 0x305,
.pme_short_desc = "Cycles branch queue full",
.pme_long_desc = "The ISU sends a signal indicating that the issue queue that feeds the ifu br unit cannot accept any more group (queue is full of groups).",
- .pme_event_ids = { 0, 0, -1, -1, 1, 0, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_BRQ_FULL_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_BRQ_FULL_CYC]
},
-#define PPC970MP_PME_PM_PMC8_OVERFLOW 78
[ PPC970MP_PME_PM_PMC8_OVERFLOW ] = {
.pme_name = "PM_PMC8_OVERFLOW",
+ .pme_code = 0x100a,
.pme_short_desc = "PMC8 Overflow",
.pme_long_desc = "PMC8 Overflow",
- .pme_event_ids = { 80, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_PMC8_OVERFLOW],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_PMC8_OVERFLOW]
},
-#define PPC970MP_PME_PM_PMC7_OVERFLOW 79
[ PPC970MP_PME_PM_PMC7_OVERFLOW ] = {
.pme_name = "PM_PMC7_OVERFLOW",
+ .pme_code = 0x800a,
.pme_short_desc = "PMC7 Overflow",
.pme_long_desc = "PMC7 Overflow",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 62 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_PMC7_OVERFLOW],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_PMC7_OVERFLOW]
},
-#define PPC970MP_PME_PM_WORK_HELD 80
[ PPC970MP_PME_PM_WORK_HELD ] = {
.pme_name = "PM_WORK_HELD",
+ .pme_code = 0x2001,
.pme_short_desc = "Work held",
.pme_long_desc = "RAS Unit has signaled completion to stop and there are groups waiting to complete",
- .pme_event_ids = { -1, 83, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000200ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_WORK_HELD],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_WORK_HELD]
},
-#define PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU0 81
[ PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU0 ] = {
.pme_name = "PM_MRK_LD_MISS_L1_LSU0",
+ .pme_code = 0x720,
.pme_short_desc = "LSU0 L1 D cache load misses",
.pme_long_desc = "A marked load, executing on unit 0, missed the dcache",
- .pme_event_ids = { 75, 72, -1, -1, 73, 72, -1, -1 },
- .pme_group_vector = {
- 0x0000002000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU0],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU0]
},
-#define PPC970MP_PME_PM_FXU_IDLE 82
[ PPC970MP_PME_PM_FXU_IDLE ] = {
.pme_name = "PM_FXU_IDLE",
+ .pme_code = 0x5002,
.pme_short_desc = "FXU idle",
.pme_long_desc = "FXU0 and FXU1 are both idle",
- .pme_event_ids = { -1, -1, -1, -1, 28, -1, -1, -1 },
- .pme_group_vector = {
- 0x000000c000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FXU_IDLE],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FXU_IDLE]
},
-#define PPC970MP_PME_PM_INST_CMPL 83
[ PPC970MP_PME_PM_INST_CMPL ] = {
.pme_name = "PM_INST_CMPL",
+ .pme_code = 0x1,
.pme_short_desc = "Instructions completed",
.pme_long_desc = "Number of Eligible Instructions that completed. ",
- .pme_event_ids = { 36, 36, 30, 30, 38, 35, 30, 30 },
- .pme_group_vector = {
- 0x0007fffbffffffffULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_INST_CMPL],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_INST_CMPL]
},
-#define PPC970MP_PME_PM_LSU1_FLUSH_UST 84
[ PPC970MP_PME_PM_LSU1_FLUSH_UST ] = {
.pme_name = "PM_LSU1_FLUSH_UST",
+ .pme_code = 0x805,
.pme_short_desc = "LSU1 unaligned store flushes",
.pme_long_desc = "A store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)",
- .pme_event_ids = { 58, 57, -1, -1, 59, 56, -1, -1 },
- .pme_group_vector = {
- 0x0000000000010000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_FLUSH_UST],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_FLUSH_UST]
},
-#define PPC970MP_PME_PM_LSU0_FLUSH_ULD 85
[ PPC970MP_PME_PM_LSU0_FLUSH_ULD ] = {
.pme_name = "PM_LSU0_FLUSH_ULD",
+ .pme_code = 0x800,
.pme_short_desc = "LSU0 unaligned load flushes",
.pme_long_desc = "A load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
- .pme_event_ids = { 47, 46, -1, -1, 48, 45, -1, -1 },
- .pme_group_vector = {
- 0x0000000000008000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_FLUSH_ULD],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_FLUSH_ULD]
},
-#define PPC970MP_PME_PM_LSU_FLUSH 86
[ PPC970MP_PME_PM_LSU_FLUSH ] = {
.pme_name = "PM_LSU_FLUSH",
+ .pme_code = 0x315,
.pme_short_desc = "Flush initiated by LSU",
.pme_long_desc = "Flush initiated by LSU",
- .pme_event_ids = { -1, -1, 43, 41, -1, -1, 41, 42 },
- .pme_group_vector = {
- 0x0000020000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_FLUSH],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_FLUSH]
},
-#define PPC970MP_PME_PM_INST_FROM_L2 87
[ PPC970MP_PME_PM_INST_FROM_L2 ] = {
.pme_name = "PM_INST_FROM_L2",
+ .pme_code = 0x1426,
.pme_short_desc = "Instructions fetched from L2",
.pme_long_desc = "An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions",
- .pme_event_ids = { 39, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000800020000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_INST_FROM_L2],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_INST_FROM_L2]
},
-#define PPC970MP_PME_PM_LSU1_REJECT_LMQ_FULL 88
[ PPC970MP_PME_PM_LSU1_REJECT_LMQ_FULL ] = {
.pme_name = "PM_LSU1_REJECT_LMQ_FULL",
+ .pme_code = 0x925,
.pme_short_desc = "LSU1 reject due to LMQ full or missed data coming",
.pme_long_desc = "LSU1 reject due to LMQ full or missed data coming",
- .pme_event_ids = { 60, 59, -1, -1, 61, 58, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_REJECT_LMQ_FULL],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_REJECT_LMQ_FULL]
},
-#define PPC970MP_PME_PM_PMC2_OVERFLOW 89
[ PPC970MP_PME_PM_PMC2_OVERFLOW ] = {
.pme_name = "PM_PMC2_OVERFLOW",
+ .pme_code = 0x300a,
.pme_short_desc = "PMC2 Overflow",
.pme_long_desc = "PMC2 Overflow",
- .pme_event_ids = { -1, -1, 64, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_PMC2_OVERFLOW],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_PMC2_OVERFLOW]
},
-#define PPC970MP_PME_PM_FPU0_DENORM 90
[ PPC970MP_PME_PM_FPU0_DENORM ] = {
.pme_name = "PM_FPU0_DENORM",
+ .pme_code = 0x120,
.pme_short_desc = "FPU0 received denormalized data",
.pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.",
- .pme_event_ids = { 9, 8, -1, -1, 9, 8, -1, -1 },
- .pme_group_vector = {
- 0x0000000000001000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_DENORM],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_DENORM]
},
-#define PPC970MP_PME_PM_FPU1_FMOV_FEST 91
[ PPC970MP_PME_PM_FPU1_FMOV_FEST ] = {
.pme_name = "PM_FPU1_FMOV_FEST",
+ .pme_code = 0x114,
.pme_short_desc = "FPU1 executing FMOV or FEST instructions",
.pme_long_desc = "This signal is active for one cycle when fp1 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ",
- .pme_event_ids = { -1, -1, 19, 20, -1, -1, 19, 20 },
- .pme_group_vector = {
- 0x0000000000001000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_FMOV_FEST],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_FMOV_FEST]
},
-#define PPC970MP_PME_PM_INST_FETCH_CYC 92
[ PPC970MP_PME_PM_INST_FETCH_CYC ] = {
.pme_name = "PM_INST_FETCH_CYC",
+ .pme_code = 0x424,
.pme_short_desc = "Cycles at least 1 instruction fetched",
.pme_long_desc = "Asserted each cycle when the IFU sends at least one instruction to the IDU. ",
- .pme_event_ids = { 90, 86, -1, -1, 90, 85, -1, -1 },
- .pme_group_vector = {
- 0x0000010000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_INST_FETCH_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_INST_FETCH_CYC]
},
-#define PPC970MP_PME_PM_GRP_DISP_REJECT 93
[ PPC970MP_PME_PM_GRP_DISP_REJECT ] = {
.pme_name = "PM_GRP_DISP_REJECT",
+ .pme_code = 0x324,
.pme_short_desc = "Group dispatch rejected",
.pme_long_desc = "A group that previously attempted dispatch was rejected.",
- .pme_event_ids = { 32, 32, -1, -1, 32, 31, -1, 29 },
- .pme_group_vector = {
- 0x0000000000000101ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GRP_DISP_REJECT],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GRP_DISP_REJECT]
},
-#define PPC970MP_PME_PM_LSU_LDF 94
[ PPC970MP_PME_PM_LSU_LDF ] = {
.pme_name = "PM_LSU_LDF",
+ .pme_code = 0x8730,
.pme_short_desc = "LSU executed Floating Point load instruction",
.pme_long_desc = "LSU executed Floating Point load instruction",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 43 },
- .pme_group_vector = {
- 0x0000000000800020ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_LDF],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_LDF]
},
-#define PPC970MP_PME_PM_INST_DISP 95
[ PPC970MP_PME_PM_INST_DISP ] = {
.pme_name = "PM_INST_DISP",
+ .pme_code = 0x320,
.pme_short_desc = "Instructions dispatched",
.pme_long_desc = "The ISU sends the number of instructions dispatched.",
- .pme_event_ids = { 37, 37, -1, -1, 39, 36, -1, -1 },
- .pme_group_vector = {
- 0x0000000100000146ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_INST_DISP],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_INST_DISP]
},
-#define PPC970MP_PME_PM_DATA_FROM_L25_SHR 96
[ PPC970MP_PME_PM_DATA_FROM_L25_SHR ] = {
.pme_name = "PM_DATA_FROM_L25_SHR",
+ .pme_code = 0x5837,
.pme_short_desc = "Data loaded from L2.5 shared",
.pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a demand load",
- .pme_event_ids = { -1, -1, -1, -1, 91, -1, -1, -1 },
- .pme_group_vector = {
- 0x0002400000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_DATA_FROM_L25_SHR],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_DATA_FROM_L25_SHR]
},
-#define PPC970MP_PME_PM_L1_DCACHE_RELOAD_VALID 97
[ PPC970MP_PME_PM_L1_DCACHE_RELOAD_VALID ] = {
.pme_name = "PM_L1_DCACHE_RELOAD_VALID",
+ .pme_code = 0x834,
.pme_short_desc = "L1 reload data source valid",
.pme_long_desc = "The data source information is valid",
- .pme_event_ids = { -1, -1, 32, 31, -1, -1, 31, 31 },
- .pme_group_vector = {
- 0x0000000100040000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_L1_DCACHE_RELOAD_VALID],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_L1_DCACHE_RELOAD_VALID]
},
-#define PPC970MP_PME_PM_MRK_GRP_ISSUED 98
[ PPC970MP_PME_PM_MRK_GRP_ISSUED ] = {
.pme_name = "PM_MRK_GRP_ISSUED",
+ .pme_code = 0x6005,
.pme_short_desc = "Marked group issued",
.pme_long_desc = "A sampled instruction was issued",
- .pme_event_ids = { -1, -1, -1, -1, -1, 70, -1, -1 },
- .pme_group_vector = {
- 0x0000000200000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_GRP_ISSUED],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_GRP_ISSUED]
},
-#define PPC970MP_PME_PM_FPU_FMA 99
[ PPC970MP_PME_PM_FPU_FMA ] = {
.pme_name = "PM_FPU_FMA",
+ .pme_code = 0x2100,
.pme_short_desc = "FPU executed multiply-add instruction",
.pme_long_desc = "This signal is active for one cycle when FPU is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, 25, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000100000900010ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_FMA],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_FMA]
},
-#define PPC970MP_PME_PM_MRK_CRU_FIN 100
[ PPC970MP_PME_PM_MRK_CRU_FIN ] = {
.pme_name = "PM_MRK_CRU_FIN",
+ .pme_code = 0x4005,
.pme_short_desc = "Marked instruction CRU processing finished",
.pme_long_desc = "The Condition Register Unit finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, -1, -1, 50, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000400000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_CRU_FIN],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_CRU_FIN]
},
-#define PPC970MP_PME_PM_CMPLU_STALL_REJECT 101
[ PPC970MP_PME_PM_CMPLU_STALL_REJECT ] = {
.pme_name = "PM_CMPLU_STALL_REJECT",
+ .pme_code = 0x70cb,
.pme_short_desc = "Completion stall caused by reject",
.pme_long_desc = "Completion stall caused by reject",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 69, -1 },
- .pme_group_vector = {
- 0x0000040000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CMPLU_STALL_REJECT],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CMPLU_STALL_REJECT]
},
-#define PPC970MP_PME_PM_MRK_LSU1_FLUSH_UST 102
[ PPC970MP_PME_PM_MRK_LSU1_FLUSH_UST ] = {
.pme_name = "PM_MRK_LSU1_FLUSH_UST",
+ .pme_code = 0x715,
.pme_short_desc = "LSU1 marked unaligned store flushes",
.pme_long_desc = "A marked store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)",
- .pme_event_ids = { -1, -1, 60, 60, -1, -1, 59, 59 },
- .pme_group_vector = {
- 0x0000001000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LSU1_FLUSH_UST],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LSU1_FLUSH_UST]
},
-#define PPC970MP_PME_PM_MRK_FXU_FIN 103
[ PPC970MP_PME_PM_MRK_FXU_FIN ] = {
.pme_name = "PM_MRK_FXU_FIN",
+ .pme_code = 0x6004,
.pme_short_desc = "Marked instruction FXU processing finished",
.pme_long_desc = "Marked instruction FXU processing finished",
- .pme_event_ids = { -1, -1, -1, -1, -1, 69, -1, -1 },
- .pme_group_vector = {
- 0x0000000400000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_FXU_FIN],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_FXU_FIN]
},
-#define PPC970MP_PME_PM_LSU1_REJECT_ERAT_MISS 104
[ PPC970MP_PME_PM_LSU1_REJECT_ERAT_MISS ] = {
.pme_name = "PM_LSU1_REJECT_ERAT_MISS",
+ .pme_code = 0x927,
.pme_short_desc = "LSU1 reject due to ERAT miss",
.pme_long_desc = "LSU1 reject due to ERAT miss",
- .pme_event_ids = { 59, 58, -1, -1, 60, 57, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_REJECT_ERAT_MISS],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_REJECT_ERAT_MISS]
},
-#define PPC970MP_PME_PM_BR_ISSUED 105
[ PPC970MP_PME_PM_BR_ISSUED ] = {
.pme_name = "PM_BR_ISSUED",
+ .pme_code = 0x431,
.pme_short_desc = "Branches issued",
.pme_long_desc = "This signal will be asserted each time the ISU issues a branch instruction. This signal will be asserted each time the ISU selects a branch instruction to issue.",
- .pme_event_ids = { -1, -1, 0, 1, -1, -1, 0, 0 },
- .pme_group_vector = {
- 0x0000800007000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_BR_ISSUED],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_BR_ISSUED]
},
-#define PPC970MP_PME_PM_PMC4_OVERFLOW 106
[ PPC970MP_PME_PM_PMC4_OVERFLOW ] = {
.pme_name = "PM_PMC4_OVERFLOW",
+ .pme_code = 0x500a,
.pme_short_desc = "PMC4 Overflow",
.pme_long_desc = "PMC4 Overflow",
- .pme_event_ids = { -1, -1, -1, -1, 77, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_PMC4_OVERFLOW],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_PMC4_OVERFLOW]
},
-#define PPC970MP_PME_PM_EE_OFF 107
[ PPC970MP_PME_PM_EE_OFF ] = {
.pme_name = "PM_EE_OFF",
+ .pme_code = 0x333,
.pme_short_desc = "Cycles MSR(EE) bit off",
.pme_long_desc = "The number of Cycles MSR(EE) bit was off.",
- .pme_event_ids = { -1, -1, 8, 9, -1, -1, 8, 8 },
- .pme_group_vector = {
- 0x0000000000000200ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_EE_OFF],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_EE_OFF]
},
-#define PPC970MP_PME_PM_INST_FROM_L25_MOD 108
[ PPC970MP_PME_PM_INST_FROM_L25_MOD ] = {
.pme_name = "PM_INST_FROM_L25_MOD",
+ .pme_code = 0x6426,
.pme_short_desc = "Instruction fetched from L2.5 modified",
.pme_long_desc = "Instruction fetched from L2.5 modified",
- .pme_event_ids = { -1, -1, -1, -1, -1, 37, -1, -1 },
- .pme_group_vector = {
- 0x0000010000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_INST_FROM_L25_MOD],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_INST_FROM_L25_MOD]
},
-#define PPC970MP_PME_PM_CMPLU_STALL_ERAT_MISS 109
[ PPC970MP_PME_PM_CMPLU_STALL_ERAT_MISS ] = {
.pme_name = "PM_CMPLU_STALL_ERAT_MISS",
+ .pme_code = 0x704c,
.pme_short_desc = "Completion stall caused by ERAT miss",
.pme_long_desc = "Completion stall caused by ERAT miss",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 70, -1 },
- .pme_group_vector = {
- 0x0000020000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CMPLU_STALL_ERAT_MISS],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CMPLU_STALL_ERAT_MISS]
},
-#define PPC970MP_PME_PM_ITLB_MISS 110
[ PPC970MP_PME_PM_ITLB_MISS ] = {
.pme_name = "PM_ITLB_MISS",
+ .pme_code = 0x700,
.pme_short_desc = "Instruction TLB misses",
.pme_long_desc = "A TLB miss for an Instruction Fetch has occurred",
- .pme_event_ids = { 41, 40, -1, -1, 42, 39, -1, -1 },
- .pme_group_vector = {
- 0x0000000010200000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_ITLB_MISS],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_ITLB_MISS]
},
-#define PPC970MP_PME_PM_FXU1_BUSY_FXU0_IDLE 111
[ PPC970MP_PME_PM_FXU1_BUSY_FXU0_IDLE ] = {
.pme_name = "PM_FXU1_BUSY_FXU0_IDLE",
+ .pme_code = 0x4002,
.pme_short_desc = "FXU1 busy FXU0 idle",
.pme_long_desc = "FXU0 was idle while FXU1 was busy",
- .pme_event_ids = { -1, -1, -1, 26, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000004000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FXU1_BUSY_FXU0_IDLE],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FXU1_BUSY_FXU0_IDLE]
},
-#define PPC970MP_PME_PM_GRP_DISP_VALID 112
[ PPC970MP_PME_PM_GRP_DISP_VALID ] = {
.pme_name = "PM_GRP_DISP_VALID",
+ .pme_code = 0x323,
.pme_short_desc = "Group dispatch valid",
.pme_long_desc = "Dispatch has been attempted for a valid group. Some groups may be rejected. The total number of successful dispatches is the number of dispatch valid minus dispatch reject.",
- .pme_event_ids = { 33, 33, -1, -1, 34, 32, -1, -1 },
- .pme_group_vector = {
- 0x0000000100000100ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GRP_DISP_VALID],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GRP_DISP_VALID]
},
-#define PPC970MP_PME_PM_MRK_GRP_DISP 113
[ PPC970MP_PME_PM_MRK_GRP_DISP ] = {
.pme_name = "PM_MRK_GRP_DISP",
+ .pme_code = 0x1002,
.pme_short_desc = "Marked group dispatched",
.pme_long_desc = "A group containing a sampled instruction was dispatched",
- .pme_event_ids = { 72, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000400000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_GRP_DISP],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_GRP_DISP]
},
-#define PPC970MP_PME_PM_LSU_FLUSH_UST 114
[ PPC970MP_PME_PM_LSU_FLUSH_UST ] = {
.pme_name = "PM_LSU_FLUSH_UST",
+ .pme_code = 0x2800,
.pme_short_desc = "SRQ unaligned store flushes",
.pme_long_desc = "A store was flushed because it was unaligned",
- .pme_event_ids = { -1, 63, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000008ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_FLUSH_UST],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_FLUSH_UST]
},
-#define PPC970MP_PME_PM_FXU1_FIN 115
[ PPC970MP_PME_PM_FXU1_FIN ] = {
.pme_name = "PM_FXU1_FIN",
+ .pme_code = 0x336,
.pme_short_desc = "FXU1 produced a result",
.pme_long_desc = "The Fixed Point unit 1 finished an instruction and produced a result",
- .pme_event_ids = { -1, -1, 25, 27, -1, -1, 26, 26 },
- .pme_group_vector = {
- 0x0000008000000100ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FXU1_FIN],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FXU1_FIN]
},
-#define PPC970MP_PME_PM_GRP_CMPL 116
[ PPC970MP_PME_PM_GRP_CMPL ] = {
.pme_name = "PM_GRP_CMPL",
+ .pme_code = 0x7003,
.pme_short_desc = "Group completed",
.pme_long_desc = "A group completed. Microcoded instructions that span multiple groups will generate this event once per group.",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 28, -1 },
- .pme_group_vector = {
- 0x0000000020080001ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GRP_CMPL],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GRP_CMPL]
},
-#define PPC970MP_PME_PM_FPU_FRSP_FCONV 117
[ PPC970MP_PME_PM_FPU_FRSP_FCONV ] = {
.pme_name = "PM_FPU_FRSP_FCONV",
+ .pme_code = 0x7110,
.pme_short_desc = "FPU executed FRSP or FCONV instructions",
.pme_long_desc = "This signal is active for one cycle when executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 21, -1 },
- .pme_group_vector = {
- 0x0000000000000020ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_FRSP_FCONV],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_FRSP_FCONV]
},
-#define PPC970MP_PME_PM_MRK_LSU0_FLUSH_SRQ 118
[ PPC970MP_PME_PM_MRK_LSU0_FLUSH_SRQ ] = {
.pme_name = "PM_MRK_LSU0_FLUSH_SRQ",
+ .pme_code = 0x713,
.pme_short_desc = "LSU0 marked SRQ flushes",
.pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { -1, -1, 54, 54, -1, -1, 53, 53 },
- .pme_group_vector = {
- 0x0000002000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LSU0_FLUSH_SRQ],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LSU0_FLUSH_SRQ]
},
-#define PPC970MP_PME_PM_CMPLU_STALL_OTHER 119
[ PPC970MP_PME_PM_CMPLU_STALL_OTHER ] = {
.pme_name = "PM_CMPLU_STALL_OTHER",
+ .pme_code = 0x100b,
.pme_short_desc = "Completion stall caused by other reason",
.pme_long_desc = "Completion stall caused by other reason",
- .pme_event_ids = { 88, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000040000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CMPLU_STALL_OTHER],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CMPLU_STALL_OTHER]
},
-#define PPC970MP_PME_PM_LSU_LMQ_FULL_CYC 120
[ PPC970MP_PME_PM_LSU_LMQ_FULL_CYC ] = {
.pme_name = "PM_LSU_LMQ_FULL_CYC",
+ .pme_code = 0x837,
.pme_short_desc = "Cycles LMQ full",
.pme_long_desc = "The LMQ was full",
- .pme_event_ids = { -1, -1, 44, 42, -1, -1, 42, 44 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_LMQ_FULL_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_LMQ_FULL_CYC]
},
-#define PPC970MP_PME_PM_ST_REF_L1_LSU0 121
[ PPC970MP_PME_PM_ST_REF_L1_LSU0 ] = {
.pme_name = "PM_ST_REF_L1_LSU0",
+ .pme_code = 0x811,
.pme_short_desc = "LSU0 L1 D cache store references",
.pme_long_desc = "A store executed on unit 0",
- .pme_event_ids = { -1, -1, 67, 64, -1, -1, 64, 64 },
- .pme_group_vector = {
- 0x0000000000030000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_ST_REF_L1_LSU0],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_ST_REF_L1_LSU0]
},
-#define PPC970MP_PME_PM_LSU0_DERAT_MISS 122
[ PPC970MP_PME_PM_LSU0_DERAT_MISS ] = {
.pme_name = "PM_LSU0_DERAT_MISS",
+ .pme_code = 0x702,
.pme_short_desc = "LSU0 DERAT misses",
.pme_long_desc = "A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.",
- .pme_event_ids = { 44, 43, -1, -1, 45, 42, -1, -1 },
- .pme_group_vector = {
- 0x0000000000040000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_DERAT_MISS],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_DERAT_MISS]
},
-#define PPC970MP_PME_PM_LSU_SRQ_SYNC_CYC 123
[ PPC970MP_PME_PM_LSU_SRQ_SYNC_CYC ] = {
.pme_name = "PM_LSU_SRQ_SYNC_CYC",
+ .pme_code = 0x735,
.pme_short_desc = "SRQ sync duration",
.pme_long_desc = "This signal is asserted every cycle when a sync is in the SRQ.",
- .pme_event_ids = { -1, -1, 51, 49, -1, -1, 48, 50 },
- .pme_group_vector = {
- 0x0000000040000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_SRQ_SYNC_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_SRQ_SYNC_CYC]
},
-#define PPC970MP_PME_PM_FPU_STALL3 124
[ PPC970MP_PME_PM_FPU_STALL3 ] = {
.pme_name = "PM_FPU_STALL3",
+ .pme_code = 0x2120,
.pme_short_desc = "FPU stalled in pipe3",
.pme_long_desc = "FPU has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, 26, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000020ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_STALL3],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_STALL3]
},
-#define PPC970MP_PME_PM_LSU_REJECT_ERAT_MISS 125
[ PPC970MP_PME_PM_LSU_REJECT_ERAT_MISS ] = {
.pme_name = "PM_LSU_REJECT_ERAT_MISS",
+ .pme_code = 0x5920,
.pme_short_desc = "LSU reject due to ERAT miss",
.pme_long_desc = "LSU reject due to ERAT miss",
- .pme_event_ids = { -1, -1, -1, -1, 68, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_REJECT_ERAT_MISS],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_REJECT_ERAT_MISS]
},
-#define PPC970MP_PME_PM_MRK_DATA_FROM_L2 126
[ PPC970MP_PME_PM_MRK_DATA_FROM_L2 ] = {
.pme_name = "PM_MRK_DATA_FROM_L2",
+ .pme_code = 0x1937,
.pme_short_desc = "Marked data loaded from L2",
.pme_long_desc = "DL1 was reloaded from the local L2 due to a marked demand load",
- .pme_event_ids = { 71, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0004000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_DATA_FROM_L2],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_DATA_FROM_L2]
},
-#define PPC970MP_PME_PM_LSU0_FLUSH_SRQ 127
[ PPC970MP_PME_PM_LSU0_FLUSH_SRQ ] = {
.pme_name = "PM_LSU0_FLUSH_SRQ",
+ .pme_code = 0x803,
.pme_short_desc = "LSU0 SRQ flushes",
.pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { 46, 45, -1, -1, 47, 44, -1, -1 },
- .pme_group_vector = {
- 0x0000000000004000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_FLUSH_SRQ],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_FLUSH_SRQ]
},
-#define PPC970MP_PME_PM_FPU0_FMOV_FEST 128
[ PPC970MP_PME_PM_FPU0_FMOV_FEST ] = {
.pme_name = "PM_FPU0_FMOV_FEST",
+ .pme_code = 0x110,
.pme_short_desc = "FPU0 executed FMOV or FEST instructions",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ",
- .pme_event_ids = { -1, -1, 14, 15, -1, -1, 14, 15 },
- .pme_group_vector = {
- 0x0000000000001000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_FMOV_FEST],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_FMOV_FEST]
},
-#define PPC970MP_PME_PM_IOPS_CMPL 129
[ PPC970MP_PME_PM_IOPS_CMPL ] = {
.pme_name = "PM_IOPS_CMPL",
+ .pme_code = 0x1001,
.pme_short_desc = "IOPS instructions completed",
.pme_long_desc = "Number of IOPS Instructions that completed.",
- .pme_event_ids = { 91, -1, -1, 68, -1, 86, 73, 69 },
- .pme_group_vector = {
- 0x0000100000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_IOPS_CMPL],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_IOPS_CMPL]
},
-#define PPC970MP_PME_PM_LD_REF_L1_LSU0 130
[ PPC970MP_PME_PM_LD_REF_L1_LSU0 ] = {
.pme_name = "PM_LD_REF_L1_LSU0",
+ .pme_code = 0x810,
.pme_short_desc = "LSU0 L1 D cache load references",
.pme_long_desc = "A load executed on unit 0",
- .pme_event_ids = { -1, -1, 39, 37, -1, -1, 37, 38 },
- .pme_group_vector = {
- 0x0000000000008000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LD_REF_L1_LSU0],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LD_REF_L1_LSU0]
},
-#define PPC970MP_PME_PM_LSU1_FLUSH_SRQ 131
[ PPC970MP_PME_PM_LSU1_FLUSH_SRQ ] = {
.pme_name = "PM_LSU1_FLUSH_SRQ",
+ .pme_code = 0x807,
.pme_short_desc = "LSU1 SRQ flushes",
.pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. ",
- .pme_event_ids = { 56, 55, -1, -1, 57, 54, -1, -1 },
- .pme_group_vector = {
- 0x0000000000004000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_FLUSH_SRQ],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_FLUSH_SRQ]
},
-#define PPC970MP_PME_PM_CMPLU_STALL_DIV 132
[ PPC970MP_PME_PM_CMPLU_STALL_DIV ] = {
.pme_name = "PM_CMPLU_STALL_DIV",
+ .pme_code = 0x708b,
.pme_short_desc = "Completion stall caused by DIV instruction",
.pme_long_desc = "Completion stall caused by DIV instruction",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 68, -1 },
- .pme_group_vector = {
- 0x0000080000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CMPLU_STALL_DIV],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CMPLU_STALL_DIV]
},
-#define PPC970MP_PME_PM_GRP_BR_MPRED 133
[ PPC970MP_PME_PM_GRP_BR_MPRED ] = {
.pme_name = "PM_GRP_BR_MPRED",
+ .pme_code = 0x327,
.pme_short_desc = "Group experienced a branch mispredict",
.pme_long_desc = "Group experienced a branch mispredict",
- .pme_event_ids = { 30, 29, -1, -1, 30, 29, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GRP_BR_MPRED],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GRP_BR_MPRED]
},
-#define PPC970MP_PME_PM_LSU_LMQ_S0_ALLOC 134
[ PPC970MP_PME_PM_LSU_LMQ_S0_ALLOC ] = {
.pme_name = "PM_LSU_LMQ_S0_ALLOC",
+ .pme_code = 0x836,
.pme_short_desc = "LMQ slot 0 allocated",
.pme_long_desc = "The first entry in the LMQ was allocated.",
- .pme_event_ids = { -1, -1, 46, 44, -1, -1, 44, 46 },
- .pme_group_vector = {
- 0x0000400008000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_LMQ_S0_ALLOC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_LMQ_S0_ALLOC]
},
-#define PPC970MP_PME_PM_LSU0_REJECT_LMQ_FULL 135
[ PPC970MP_PME_PM_LSU0_REJECT_LMQ_FULL ] = {
.pme_name = "PM_LSU0_REJECT_LMQ_FULL",
+ .pme_code = 0x921,
.pme_short_desc = "LSU0 reject due to LMQ full or missed data coming",
.pme_long_desc = "LSU0 reject due to LMQ full or missed data coming",
- .pme_event_ids = { 50, 49, -1, -1, 51, 48, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_REJECT_LMQ_FULL],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_REJECT_LMQ_FULL]
},
-#define PPC970MP_PME_PM_ST_REF_L1 136
[ PPC970MP_PME_PM_ST_REF_L1 ] = {
.pme_name = "PM_ST_REF_L1",
+ .pme_code = 0x7810,
.pme_short_desc = "L1 D cache store references",
.pme_long_desc = "Total DL1 Store references",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 63, -1 },
- .pme_group_vector = {
- 0x000000010260000eULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_ST_REF_L1],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_ST_REF_L1]
},
-#define PPC970MP_PME_PM_MRK_VMX_FIN 137
[ PPC970MP_PME_PM_MRK_VMX_FIN ] = {
.pme_name = "PM_MRK_VMX_FIN",
+ .pme_code = 0x3005,
.pme_short_desc = "Marked instruction VMX processing finished",
.pme_long_desc = "Marked instruction VMX processing finished",
- .pme_event_ids = { -1, -1, 63, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_VMX_FIN],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_VMX_FIN]
},
-#define PPC970MP_PME_PM_LSU_SRQ_EMPTY_CYC 138
[ PPC970MP_PME_PM_LSU_SRQ_EMPTY_CYC ] = {
.pme_name = "PM_LSU_SRQ_EMPTY_CYC",
+ .pme_code = 0x4003,
.pme_short_desc = "Cycles SRQ empty",
.pme_long_desc = "The Store Request Queue is empty",
- .pme_event_ids = { -1, -1, -1, 47, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_SRQ_EMPTY_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_SRQ_EMPTY_CYC]
},
-#define PPC970MP_PME_PM_FPU1_STF 139
[ PPC970MP_PME_PM_FPU1_STF ] = {
.pme_name = "PM_FPU1_STF",
+ .pme_code = 0x126,
.pme_short_desc = "FPU1 executed store instruction",
.pme_long_desc = "This signal is active for one cycle when fp1 is executing a store instruction.",
- .pme_event_ids = { 25, 24, -1, -1, 25, 24, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_STF],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_STF]
},
-#define PPC970MP_PME_PM_RUN_CYC 140
[ PPC970MP_PME_PM_RUN_CYC ] = {
.pme_name = "PM_RUN_CYC",
+ .pme_code = 0x1005,
.pme_short_desc = "Run cycles",
.pme_long_desc = "Processor Cycles gated by the run latch",
- .pme_event_ids = { 81, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000004000001ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_RUN_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_RUN_CYC]
},
-#define PPC970MP_PME_PM_LSU_LMQ_S0_VALID 141
[ PPC970MP_PME_PM_LSU_LMQ_S0_VALID ] = {
.pme_name = "PM_LSU_LMQ_S0_VALID",
+ .pme_code = 0x835,
.pme_short_desc = "LMQ slot 0 valid",
.pme_long_desc = "This signal is asserted every cycle when the first entry in the LMQ is valid. The LMQ had eight entries that are allocated FIFO",
- .pme_event_ids = { -1, -1, 47, 45, -1, -1, 45, 47 },
- .pme_group_vector = {
- 0x0000400008000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_LMQ_S0_VALID],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_LMQ_S0_VALID]
},
-#define PPC970MP_PME_PM_LSU0_LDF 142
[ PPC970MP_PME_PM_LSU0_LDF ] = {
.pme_name = "PM_LSU0_LDF",
+ .pme_code = 0x730,
.pme_short_desc = "LSU0 executed Floating Point load instruction",
.pme_long_desc = "A floating point load was executed from LSU unit 0",
- .pme_event_ids = { -1, -1, 41, 39, -1, -1, 39, 40 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_LDF],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_LDF]
},
-#define PPC970MP_PME_PM_LSU_LRQ_S0_VALID 143
[ PPC970MP_PME_PM_LSU_LRQ_S0_VALID ] = {
.pme_name = "PM_LSU_LRQ_S0_VALID",
+ .pme_code = 0x822,
.pme_short_desc = "LRQ slot 0 valid",
.pme_long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.",
- .pme_event_ids = { 66, 66, -1, -1, 67, 65, -1, -1 },
- .pme_group_vector = {
- 0x0000000010000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_LRQ_S0_VALID],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_LRQ_S0_VALID]
},
-#define PPC970MP_PME_PM_PMC3_OVERFLOW 144
[ PPC970MP_PME_PM_PMC3_OVERFLOW ] = {
.pme_name = "PM_PMC3_OVERFLOW",
+ .pme_code = 0x400a,
.pme_short_desc = "PMC3 Overflow",
.pme_long_desc = "PMC3 Overflow",
- .pme_event_ids = { -1, -1, -1, 62, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_PMC3_OVERFLOW],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_PMC3_OVERFLOW]
},
-#define PPC970MP_PME_PM_MRK_IMR_RELOAD 145
[ PPC970MP_PME_PM_MRK_IMR_RELOAD ] = {
.pme_name = "PM_MRK_IMR_RELOAD",
+ .pme_code = 0x722,
.pme_short_desc = "Marked IMR reloaded",
.pme_long_desc = "A DL1 reload occured due to marked load",
- .pme_event_ids = { 73, 71, -1, -1, 72, 71, -1, -1 },
- .pme_group_vector = {
- 0x0000001000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_IMR_RELOAD],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_IMR_RELOAD]
},
-#define PPC970MP_PME_PM_MRK_GRP_TIMEO 146
[ PPC970MP_PME_PM_MRK_GRP_TIMEO ] = {
.pme_name = "PM_MRK_GRP_TIMEO",
+ .pme_code = 0x5005,
.pme_short_desc = "Marked group completion timeout",
.pme_long_desc = "The sampling timeout expired indicating that the previously sampled instruction is no longer in the processor",
- .pme_event_ids = { -1, -1, -1, -1, 71, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000800000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_GRP_TIMEO],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_GRP_TIMEO]
},
-#define PPC970MP_PME_PM_FPU_FMOV_FEST 147
[ PPC970MP_PME_PM_FPU_FMOV_FEST ] = {
.pme_name = "PM_FPU_FMOV_FEST",
+ .pme_code = 0x8110,
.pme_short_desc = "FPU executing FMOV or FEST instructions",
.pme_long_desc = "This signal is active for one cycle when executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ . Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 22 },
- .pme_group_vector = {
- 0x0000000000100010ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_FMOV_FEST],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_FMOV_FEST]
},
-#define PPC970MP_PME_PM_GRP_DISP_BLK_SB_CYC 148
[ PPC970MP_PME_PM_GRP_DISP_BLK_SB_CYC ] = {
.pme_name = "PM_GRP_DISP_BLK_SB_CYC",
+ .pme_code = 0x331,
.pme_short_desc = "Cycles group dispatch blocked by scoreboard",
.pme_long_desc = "The ISU sends a signal indicating that dispatch is blocked by scoreboard.",
- .pme_event_ids = { -1, -1, 28, 29, -1, -1, 29, 28 },
- .pme_group_vector = {
- 0x0000000000000040ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GRP_DISP_BLK_SB_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GRP_DISP_BLK_SB_CYC]
},
-#define PPC970MP_PME_PM_XER_MAP_FULL_CYC 149
[ PPC970MP_PME_PM_XER_MAP_FULL_CYC ] = {
.pme_name = "PM_XER_MAP_FULL_CYC",
+ .pme_code = 0x302,
.pme_short_desc = "Cycles XER mapper full",
.pme_long_desc = "The ISU sends a signal indicating that the xer mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.",
- .pme_event_ids = { 87, 84, -1, -1, 83, 83, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000040ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_XER_MAP_FULL_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_XER_MAP_FULL_CYC]
},
-#define PPC970MP_PME_PM_ST_MISS_L1 150
[ PPC970MP_PME_PM_ST_MISS_L1 ] = {
.pme_name = "PM_ST_MISS_L1",
+ .pme_code = 0x813,
.pme_short_desc = "L1 D cache store misses",
.pme_long_desc = "A store missed the dcache",
- .pme_event_ids = { -1, -1, 66, 63, -1, -1, 62, 63 },
- .pme_group_vector = {
- 0x0000000000610000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_ST_MISS_L1],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_ST_MISS_L1]
},
-#define PPC970MP_PME_PM_STOP_COMPLETION 151
[ PPC970MP_PME_PM_STOP_COMPLETION ] = {
.pme_name = "PM_STOP_COMPLETION",
+ .pme_code = 0x3001,
.pme_short_desc = "Completion stopped",
.pme_long_desc = "RAS Unit has signaled completion to stop",
- .pme_event_ids = { -1, -1, 65, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000201ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_STOP_COMPLETION],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_STOP_COMPLETION]
},
-#define PPC970MP_PME_PM_MRK_GRP_CMPL 152
[ PPC970MP_PME_PM_MRK_GRP_CMPL ] = {
.pme_name = "PM_MRK_GRP_CMPL",
+ .pme_code = 0x4004,
.pme_short_desc = "Marked group completed",
.pme_long_desc = "A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group.",
- .pme_event_ids = { -1, -1, -1, 51, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000a00000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_GRP_CMPL],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_GRP_CMPL]
},
-#define PPC970MP_PME_PM_ISLB_MISS 153
[ PPC970MP_PME_PM_ISLB_MISS ] = {
.pme_name = "PM_ISLB_MISS",
+ .pme_code = 0x701,
.pme_short_desc = "Instruction SLB misses",
.pme_long_desc = "A SLB miss for an instruction fetch as occurred",
- .pme_event_ids = { 40, 39, -1, -1, 41, 38, -1, -1 },
- .pme_group_vector = {
- 0x0000000004000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_ISLB_MISS],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_ISLB_MISS]
},
-#define PPC970MP_PME_PM_SUSPENDED 154
[ PPC970MP_PME_PM_SUSPENDED ] = {
.pme_name = "PM_SUSPENDED",
+ .pme_code = 0x0,
.pme_short_desc = "Suspended",
.pme_long_desc = "Suspended",
- .pme_event_ids = { 86, 81, 69, 66, 82, 82, 66, 66 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_SUSPENDED],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_SUSPENDED]
},
-#define PPC970MP_PME_PM_CYC 155
[ PPC970MP_PME_PM_CYC ] = {
.pme_name = "PM_CYC",
+ .pme_code = 0x7,
.pme_short_desc = "Processor cycles",
.pme_long_desc = "Processor cycles",
- .pme_event_ids = { 2, 2, 4, 5, 3, 2, 4, 4 },
- .pme_group_vector = {
- 0x0007ffffffffffffULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CYC]
},
-#define PPC970MP_PME_PM_LD_MISS_L1_LSU1 156
[ PPC970MP_PME_PM_LD_MISS_L1_LSU1 ] = {
.pme_name = "PM_LD_MISS_L1_LSU1",
+ .pme_code = 0x816,
.pme_short_desc = "LSU1 L1 D cache load misses",
.pme_long_desc = "A load, executing on unit 1, missed the dcache",
- .pme_event_ids = { -1, -1, 38, 36, -1, -1, 36, 36 },
- .pme_group_vector = {
- 0x0003000000008000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LD_MISS_L1_LSU1],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LD_MISS_L1_LSU1]
},
-#define PPC970MP_PME_PM_STCX_FAIL 157
[ PPC970MP_PME_PM_STCX_FAIL ] = {
.pme_name = "PM_STCX_FAIL",
+ .pme_code = 0x721,
.pme_short_desc = "STCX failed",
.pme_long_desc = "A stcx (stwcx or stdcx) failed",
- .pme_event_ids = { 83, 78, -1, -1, 79, 79, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_STCX_FAIL],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_STCX_FAIL]
},
-#define PPC970MP_PME_PM_LSU1_SRQ_STFWD 158
[ PPC970MP_PME_PM_LSU1_SRQ_STFWD ] = {
.pme_name = "PM_LSU1_SRQ_STFWD",
+ .pme_code = 0x824,
.pme_short_desc = "LSU1 SRQ store forwarded",
.pme_long_desc = "Data from a store instruction was forwarded to a load on unit 1",
- .pme_event_ids = { 63, 62, -1, -1, 64, 61, -1, -1 },
- .pme_group_vector = {
- 0x0000000000020000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_SRQ_STFWD],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_SRQ_STFWD]
},
-#define PPC970MP_PME_PM_GRP_DISP 159
[ PPC970MP_PME_PM_GRP_DISP ] = {
.pme_name = "PM_GRP_DISP",
+ .pme_code = 0x2004,
.pme_short_desc = "Group dispatches",
.pme_long_desc = "A group was dispatched",
- .pme_event_ids = { -1, 31, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GRP_DISP],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GRP_DISP]
},
-#define PPC970MP_PME_PM_L2_PREF 160
[ PPC970MP_PME_PM_L2_PREF ] = {
.pme_name = "PM_L2_PREF",
+ .pme_code = 0x733,
.pme_short_desc = "L2 cache prefetches",
.pme_long_desc = "A request to prefetch data into L2 was made",
- .pme_event_ids = { -1, -1, 35, 34, -1, -1, 34, 34 },
- .pme_group_vector = {
- 0x0000000010000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_L2_PREF],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_L2_PREF]
},
-#define PPC970MP_PME_PM_FPU1_DENORM 161
[ PPC970MP_PME_PM_FPU1_DENORM ] = {
.pme_name = "PM_FPU1_DENORM",
+ .pme_code = 0x124,
.pme_short_desc = "FPU1 received denormalized data",
.pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.",
- .pme_event_ids = { 18, 17, -1, -1, 18, 17, -1, -1 },
- .pme_group_vector = {
- 0x0000000000001000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_DENORM],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_DENORM]
},
-#define PPC970MP_PME_PM_DATA_FROM_L2 162
[ PPC970MP_PME_PM_DATA_FROM_L2 ] = {
.pme_name = "PM_DATA_FROM_L2",
+ .pme_code = 0x1837,
.pme_short_desc = "Data loaded from L2",
.pme_long_desc = "DL1 was reloaded from the local L2 due to a demand load",
- .pme_event_ids = { 3, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0003000008000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_DATA_FROM_L2],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_DATA_FROM_L2]
},
-#define PPC970MP_PME_PM_FPU0_FPSCR 163
[ PPC970MP_PME_PM_FPU0_FPSCR ] = {
.pme_name = "PM_FPU0_FPSCR",
+ .pme_code = 0x130,
.pme_short_desc = "FPU0 executed FPSCR instruction",
.pme_long_desc = "This signal is active for one cycle when fp0 is executing fpscr move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*. mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs",
- .pme_event_ids = { -1, -1, 15, 16, -1, -1, 15, 16 },
- .pme_group_vector = {
- 0x0000000000002000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_FPSCR],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_FPSCR]
},
-#define PPC970MP_PME_PM_MRK_DATA_FROM_L25_MOD 164
[ PPC970MP_PME_PM_MRK_DATA_FROM_L25_MOD ] = {
.pme_name = "PM_MRK_DATA_FROM_L25_MOD",
+ .pme_code = 0x6937,
.pme_short_desc = "Marked data loaded from L2.5 modified",
.pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a marked demand load",
- .pme_event_ids = { -1, -1, -1, -1, -1, 88, -1, -1 },
- .pme_group_vector = {
- 0x0004000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_DATA_FROM_L25_MOD],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_DATA_FROM_L25_MOD]
},
-#define PPC970MP_PME_PM_FPU0_FSQRT 165
[ PPC970MP_PME_PM_FPU0_FSQRT ] = {
.pme_name = "PM_FPU0_FSQRT",
+ .pme_code = 0x102,
.pme_short_desc = "FPU0 executed FSQRT instruction",
.pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp0 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 12, 11, -1, -1, 12, 11, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000800ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_FSQRT],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_FSQRT]
},
-#define PPC970MP_PME_PM_LD_REF_L1 166
[ PPC970MP_PME_PM_LD_REF_L1 ] = {
.pme_name = "PM_LD_REF_L1",
+ .pme_code = 0x8810,
.pme_short_desc = "L1 D cache load references",
.pme_long_desc = "Total DL1 Load references",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 37 },
- .pme_group_vector = {
- 0x000304004260000eULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LD_REF_L1],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LD_REF_L1]
},
-#define PPC970MP_PME_PM_MRK_L1_RELOAD_VALID 167
[ PPC970MP_PME_PM_MRK_L1_RELOAD_VALID ] = {
.pme_name = "PM_MRK_L1_RELOAD_VALID",
+ .pme_code = 0x934,
.pme_short_desc = "Marked L1 reload data source valid",
.pme_long_desc = "The source information is valid and is for a marked load",
- .pme_event_ids = { -1, -1, 52, 52, -1, -1, 51, 51 },
- .pme_group_vector = {
- 0x0004000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_L1_RELOAD_VALID],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_L1_RELOAD_VALID]
},
-#define PPC970MP_PME_PM_1PLUS_PPC_CMPL 168
[ PPC970MP_PME_PM_1PLUS_PPC_CMPL ] = {
.pme_name = "PM_1PLUS_PPC_CMPL",
+ .pme_code = 0x5003,
.pme_short_desc = "One or more PPC instruction completed",
.pme_long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.",
- .pme_event_ids = { -1, -1, -1, -1, 0, -1, -1, -1 },
- .pme_group_vector = {
- 0x0001000000080001ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_1PLUS_PPC_CMPL],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_1PLUS_PPC_CMPL]
},
-#define PPC970MP_PME_PM_INST_FROM_L1 169
[ PPC970MP_PME_PM_INST_FROM_L1 ] = {
.pme_name = "PM_INST_FROM_L1",
+ .pme_code = 0x142d,
.pme_short_desc = "Instruction fetched from L1",
.pme_long_desc = "An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions",
- .pme_event_ids = { 38, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000010080000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_INST_FROM_L1],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_INST_FROM_L1]
},
-#define PPC970MP_PME_PM_EE_OFF_EXT_INT 170
[ PPC970MP_PME_PM_EE_OFF_EXT_INT ] = {
.pme_name = "PM_EE_OFF_EXT_INT",
+ .pme_code = 0x337,
.pme_short_desc = "Cycles MSR(EE) bit off and external interrupt pending",
.pme_long_desc = "Cycles MSR(EE) bit off and external interrupt pending",
- .pme_event_ids = { -1, -1, 9, 10, -1, -1, 9, 9 },
- .pme_group_vector = {
- 0x0000000000000200ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_EE_OFF_EXT_INT],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_EE_OFF_EXT_INT]
},
-#define PPC970MP_PME_PM_PMC6_OVERFLOW 171
[ PPC970MP_PME_PM_PMC6_OVERFLOW ] = {
.pme_name = "PM_PMC6_OVERFLOW",
+ .pme_code = 0x700a,
.pme_short_desc = "PMC6 Overflow",
.pme_long_desc = "PMC6 Overflow",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 61, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_PMC6_OVERFLOW],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_PMC6_OVERFLOW]
},
-#define PPC970MP_PME_PM_LSU_LRQ_FULL_CYC 172
[ PPC970MP_PME_PM_LSU_LRQ_FULL_CYC ] = {
.pme_name = "PM_LSU_LRQ_FULL_CYC",
+ .pme_code = 0x312,
.pme_short_desc = "Cycles LRQ full",
.pme_long_desc = "The ISU sends this signal when the LRQ is full.",
- .pme_event_ids = { -1, -1, 49, 46, -1, -1, 46, 48 },
- .pme_group_vector = {
- 0x0000000000000080ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_LRQ_FULL_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_LRQ_FULL_CYC]
},
-#define PPC970MP_PME_PM_IC_PREF_INSTALL 173
[ PPC970MP_PME_PM_IC_PREF_INSTALL ] = {
.pme_name = "PM_IC_PREF_INSTALL",
+ .pme_code = 0x427,
.pme_short_desc = "Instruction prefetched installed in prefetch",
.pme_long_desc = "New line coming into the prefetch buffer",
- .pme_event_ids = { 34, 34, -1, -1, 36, 33, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_IC_PREF_INSTALL],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_IC_PREF_INSTALL]
},
-#define PPC970MP_PME_PM_DC_PREF_OUT_OF_STREAMS 174
[ PPC970MP_PME_PM_DC_PREF_OUT_OF_STREAMS ] = {
.pme_name = "PM_DC_PREF_OUT_OF_STREAMS",
+ .pme_code = 0x732,
.pme_short_desc = "D cache out of streams",
.pme_long_desc = "out of streams",
- .pme_event_ids = { -1, -1, 6, 7, -1, -1, 6, 6 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_DC_PREF_OUT_OF_STREAMS],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_DC_PREF_OUT_OF_STREAMS]
},
-#define PPC970MP_PME_PM_MRK_LSU1_FLUSH_SRQ 175
[ PPC970MP_PME_PM_MRK_LSU1_FLUSH_SRQ ] = {
.pme_name = "PM_MRK_LSU1_FLUSH_SRQ",
+ .pme_code = 0x717,
.pme_short_desc = "LSU1 marked SRQ flushes",
.pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { -1, -1, 58, 58, -1, -1, 57, 57 },
- .pme_group_vector = {
- 0x0000002000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LSU1_FLUSH_SRQ],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LSU1_FLUSH_SRQ]
},
-#define PPC970MP_PME_PM_GCT_FULL_CYC 176
[ PPC970MP_PME_PM_GCT_FULL_CYC ] = {
.pme_name = "PM_GCT_FULL_CYC",
+ .pme_code = 0x300,
.pme_short_desc = "Cycles GCT full",
.pme_long_desc = "The ISU sends a signal indicating the gct is full. ",
- .pme_event_ids = { 29, 28, -1, -1, 29, 28, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GCT_FULL_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GCT_FULL_CYC]
},
-#define PPC970MP_PME_PM_INST_FROM_MEM 177
[ PPC970MP_PME_PM_INST_FROM_MEM ] = {
.pme_name = "PM_INST_FROM_MEM",
+ .pme_code = 0x2426,
.pme_short_desc = "Instruction fetched from memory",
.pme_long_desc = "Instruction fetched from memory",
- .pme_event_ids = { -1, 38, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000810020000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_INST_FROM_MEM],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_INST_FROM_MEM]
},
-#define PPC970MP_PME_PM_FLUSH_LSU_BR_MPRED 178
[ PPC970MP_PME_PM_FLUSH_LSU_BR_MPRED ] = {
.pme_name = "PM_FLUSH_LSU_BR_MPRED",
+ .pme_code = 0x317,
.pme_short_desc = "Flush caused by LSU or branch mispredict",
.pme_long_desc = "Flush caused by LSU or branch mispredict",
- .pme_event_ids = { -1, -1, 11, 12, -1, -1, 11, 12 },
- .pme_group_vector = {
- 0x0000020000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FLUSH_LSU_BR_MPRED],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FLUSH_LSU_BR_MPRED]
},
-#define PPC970MP_PME_PM_FXU_BUSY 179
[ PPC970MP_PME_PM_FXU_BUSY ] = {
.pme_name = "PM_FXU_BUSY",
+ .pme_code = 0x6002,
.pme_short_desc = "FXU busy",
.pme_long_desc = "FXU0 and FXU1 are both busy",
- .pme_event_ids = { -1, -1, -1, -1, -1, 27, -1, -1 },
- .pme_group_vector = {
- 0x000008c000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FXU_BUSY],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FXU_BUSY]
},
-#define PPC970MP_PME_PM_ST_REF_L1_LSU1 180
[ PPC970MP_PME_PM_ST_REF_L1_LSU1 ] = {
.pme_name = "PM_ST_REF_L1_LSU1",
+ .pme_code = 0x815,
.pme_short_desc = "LSU1 L1 D cache store references",
.pme_long_desc = "A store executed on unit 1",
- .pme_event_ids = { -1, -1, 68, 65, -1, -1, 65, 65 },
- .pme_group_vector = {
- 0x0000000000030000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_ST_REF_L1_LSU1],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_ST_REF_L1_LSU1]
},
-#define PPC970MP_PME_PM_MRK_LD_MISS_L1 181
[ PPC970MP_PME_PM_MRK_LD_MISS_L1 ] = {
.pme_name = "PM_MRK_LD_MISS_L1",
+ .pme_code = 0x1720,
.pme_short_desc = "Marked L1 D cache load misses",
.pme_long_desc = "Marked L1 D cache load misses",
- .pme_event_ids = { 74, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000200000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LD_MISS_L1],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LD_MISS_L1]
},
-#define PPC970MP_PME_PM_L1_WRITE_CYC 182
[ PPC970MP_PME_PM_L1_WRITE_CYC ] = {
.pme_name = "PM_L1_WRITE_CYC",
+ .pme_code = 0x434,
.pme_short_desc = "Cycles writing to instruction L1",
.pme_long_desc = "This signal is asserted each cycle a cache write is active.",
- .pme_event_ids = { -1, -1, 34, 33, -1, -1, 33, 33 },
- .pme_group_vector = {
- 0x0000200000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_L1_WRITE_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_L1_WRITE_CYC]
},
-#define PPC970MP_PME_PM_LSU1_BUSY 183
[ PPC970MP_PME_PM_LSU1_BUSY ] = {
.pme_name = "PM_LSU1_BUSY",
+ .pme_code = 0x827,
.pme_short_desc = "LSU1 busy",
.pme_long_desc = "LSU unit 0 is busy rejecting instructions ",
- .pme_event_ids = { 89, 85, -1, -1, 89, 84, -1, -1 },
- .pme_group_vector = {
- 0x0000020000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_BUSY],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_BUSY]
},
-#define PPC970MP_PME_PM_LSU_REJECT_LMQ_FULL 184
[ PPC970MP_PME_PM_LSU_REJECT_LMQ_FULL ] = {
.pme_name = "PM_LSU_REJECT_LMQ_FULL",
+ .pme_code = 0x2920,
.pme_short_desc = "LSU reject due to LMQ full or missed data coming",
.pme_long_desc = "LSU reject due to LMQ full or missed data coming",
- .pme_event_ids = { -1, 67, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_REJECT_LMQ_FULL],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_REJECT_LMQ_FULL]
},
-#define PPC970MP_PME_PM_CMPLU_STALL_FDIV 185
[ PPC970MP_PME_PM_CMPLU_STALL_FDIV ] = {
.pme_name = "PM_CMPLU_STALL_FDIV",
+ .pme_code = 0x504c,
.pme_short_desc = "Completion stall caused by FDIV or FQRT instruction",
.pme_long_desc = "Completion stall caused by FDIV or FQRT instruction",
- .pme_event_ids = { -1, -1, -1, -1, 87, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000100000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CMPLU_STALL_FDIV],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CMPLU_STALL_FDIV]
},
-#define PPC970MP_PME_PM_FPU_ALL 186
[ PPC970MP_PME_PM_FPU_ALL ] = {
.pme_name = "PM_FPU_ALL",
+ .pme_code = 0x5100,
.pme_short_desc = "FPU executed add",
.pme_long_desc = " mult",
- .pme_event_ids = { -1, -1, -1, -1, 26, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000020ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_ALL],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_ALL]
},
-#define PPC970MP_PME_PM_LSU_SRQ_S0_ALLOC 187
[ PPC970MP_PME_PM_LSU_SRQ_S0_ALLOC ] = {
.pme_name = "PM_LSU_SRQ_S0_ALLOC",
+ .pme_code = 0x825,
.pme_short_desc = "SRQ slot 0 allocated",
.pme_long_desc = "SRQ Slot zero was allocated",
- .pme_event_ids = { 68, 68, -1, -1, 69, 67, -1, -1 },
- .pme_group_vector = {
- 0x0000000040000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_SRQ_S0_ALLOC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_SRQ_S0_ALLOC]
},
-#define PPC970MP_PME_PM_INST_FROM_L25_SHR 188
[ PPC970MP_PME_PM_INST_FROM_L25_SHR ] = {
.pme_name = "PM_INST_FROM_L25_SHR",
+ .pme_code = 0x5426,
.pme_short_desc = "Instruction fetched from L2.5 shared",
.pme_long_desc = "Instruction fetched from L2.5 shared",
- .pme_event_ids = { -1, -1, -1, -1, 40, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_INST_FROM_L25_SHR],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_INST_FROM_L25_SHR]
},
-#define PPC970MP_PME_PM_GRP_MRK 189
[ PPC970MP_PME_PM_GRP_MRK ] = {
.pme_name = "PM_GRP_MRK",
+ .pme_code = 0x5004,
.pme_short_desc = "Group marked in IDU",
.pme_long_desc = "A group was sampled (marked)",
- .pme_event_ids = { -1, -1, -1, -1, 35, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000600000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GRP_MRK],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GRP_MRK]
},
-#define PPC970MP_PME_PM_BR_MPRED_CR 190
[ PPC970MP_PME_PM_BR_MPRED_CR ] = {
.pme_name = "PM_BR_MPRED_CR",
+ .pme_code = 0x432,
.pme_short_desc = "Branch mispredictions due to CR bit setting",
.pme_long_desc = "This signal is asserted when the branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This signal is asserted after a branch issue event and will result in a branch redirect flush if not overridden by a flush of an older instruction.",
- .pme_event_ids = { -1, -1, 1, 2, -1, -1, 1, 1 },
- .pme_group_vector = {
- 0x0000800005000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_BR_MPRED_CR],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_BR_MPRED_CR]
},
-#define PPC970MP_PME_PM_DC_PREF_STREAM_ALLOC 191
[ PPC970MP_PME_PM_DC_PREF_STREAM_ALLOC ] = {
.pme_name = "PM_DC_PREF_STREAM_ALLOC",
+ .pme_code = 0x737,
.pme_short_desc = "D cache new prefetch stream allocated",
.pme_long_desc = "A new Prefetch Stream was allocated",
- .pme_event_ids = { -1, -1, 7, 8, -1, -1, 7, 7 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_DC_PREF_STREAM_ALLOC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_DC_PREF_STREAM_ALLOC]
},
-#define PPC970MP_PME_PM_FPU1_FIN 192
[ PPC970MP_PME_PM_FPU1_FIN ] = {
.pme_name = "PM_FPU1_FIN",
+ .pme_code = 0x117,
.pme_short_desc = "FPU1 produced a result",
.pme_long_desc = "fp1 finished, produced a result. This only indicates finish, not completion. ",
- .pme_event_ids = { -1, -1, 18, 19, -1, -1, 18, 19 },
- .pme_group_vector = {
- 0x0000000000802800ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_FIN],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_FIN]
},
-#define PPC970MP_PME_PM_LSU_REJECT_SRQ 193
[ PPC970MP_PME_PM_LSU_REJECT_SRQ ] = {
.pme_name = "PM_LSU_REJECT_SRQ",
+ .pme_code = 0x1920,
.pme_short_desc = "LSU SRQ rejects",
.pme_long_desc = "LSU SRQ rejects",
- .pme_event_ids = { 67, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_REJECT_SRQ],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_REJECT_SRQ]
},
-#define PPC970MP_PME_PM_BR_MPRED_TA 194
[ PPC970MP_PME_PM_BR_MPRED_TA ] = {
.pme_name = "PM_BR_MPRED_TA",
+ .pme_code = 0x433,
.pme_short_desc = "Branch mispredictions due to target address",
.pme_long_desc = "branch miss predict due to a target address prediction. This signal will be asserted each time the branch execution unit detects an incorrect target address prediction. This signal will be asserted after a valid branch execution unit issue and will cause a branch mispredict flush unless a flush is detected from an older instruction.",
- .pme_event_ids = { -1, -1, 2, 3, -1, -1, 2, 2 },
- .pme_group_vector = {
- 0x0000a00005000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_BR_MPRED_TA],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_BR_MPRED_TA]
},
-#define PPC970MP_PME_PM_CRQ_FULL_CYC 195
[ PPC970MP_PME_PM_CRQ_FULL_CYC ] = {
.pme_name = "PM_CRQ_FULL_CYC",
+ .pme_code = 0x311,
.pme_short_desc = "Cycles CR issue queue full",
.pme_long_desc = "The ISU sends a signal indicating that the issue queue that feeds the ifu cr unit cannot accept any more group (queue is full of groups).",
- .pme_event_ids = { -1, -1, 3, 4, -1, -1, 3, 3 },
- .pme_group_vector = {
- 0x0000000000000040ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CRQ_FULL_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CRQ_FULL_CYC]
},
-#define PPC970MP_PME_PM_LD_MISS_L1 196
[ PPC970MP_PME_PM_LD_MISS_L1 ] = {
.pme_name = "PM_LD_MISS_L1",
+ .pme_code = 0x3810,
.pme_short_desc = "L1 D cache load misses",
.pme_long_desc = "Total DL1 Load references that miss the DL1",
- .pme_event_ids = { -1, -1, 36, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000040043600006ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LD_MISS_L1],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LD_MISS_L1]
},
-#define PPC970MP_PME_PM_INST_FROM_PREF 197
[ PPC970MP_PME_PM_INST_FROM_PREF ] = {
.pme_name = "PM_INST_FROM_PREF",
+ .pme_code = 0x342d,
.pme_short_desc = "Instructions fetched from prefetch",
.pme_long_desc = "An instruction fetch group was fetched from the prefetch buffer. Fetch Groups can contain up to 8 instructions",
- .pme_event_ids = { -1, -1, 31, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000810000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_INST_FROM_PREF],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_INST_FROM_PREF]
},
-#define PPC970MP_PME_PM_STCX_PASS 198
[ PPC970MP_PME_PM_STCX_PASS ] = {
.pme_name = "PM_STCX_PASS",
+ .pme_code = 0x725,
.pme_short_desc = "Stcx passes",
.pme_long_desc = "A stcx (stwcx or stdcx) instruction was successful",
- .pme_event_ids = { 84, 79, -1, -1, 80, 80, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_STCX_PASS],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_STCX_PASS]
},
-#define PPC970MP_PME_PM_DC_INV_L2 199
[ PPC970MP_PME_PM_DC_INV_L2 ] = {
.pme_name = "PM_DC_INV_L2",
+ .pme_code = 0x817,
.pme_short_desc = "L1 D cache entries invalidated from L2",
.pme_long_desc = "A dcache invalidated was received from the L2 because a line in L2 was castout.",
- .pme_event_ids = { -1, -1, 5, 6, -1, -1, 5, 5 },
- .pme_group_vector = {
- 0x0000000020010006ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_DC_INV_L2],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_DC_INV_L2]
},
-#define PPC970MP_PME_PM_LSU_SRQ_FULL_CYC 200
[ PPC970MP_PME_PM_LSU_SRQ_FULL_CYC ] = {
.pme_name = "PM_LSU_SRQ_FULL_CYC",
+ .pme_code = 0x313,
.pme_short_desc = "Cycles SRQ full",
.pme_long_desc = "The ISU sends this signal when the srq is full.",
- .pme_event_ids = { -1, -1, 50, 48, -1, -1, 47, 49 },
- .pme_group_vector = {
- 0x0000000000000080ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_SRQ_FULL_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_SRQ_FULL_CYC]
},
-#define PPC970MP_PME_PM_LSU0_FLUSH_LRQ 201
[ PPC970MP_PME_PM_LSU0_FLUSH_LRQ ] = {
.pme_name = "PM_LSU0_FLUSH_LRQ",
+ .pme_code = 0x802,
.pme_short_desc = "LSU0 LRQ flushes",
.pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { 45, 44, -1, -1, 46, 43, -1, -1 },
- .pme_group_vector = {
- 0x0000000000004000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_FLUSH_LRQ],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_FLUSH_LRQ]
},
-#define PPC970MP_PME_PM_LSU_SRQ_S0_VALID 202
[ PPC970MP_PME_PM_LSU_SRQ_S0_VALID ] = {
.pme_name = "PM_LSU_SRQ_S0_VALID",
+ .pme_code = 0x821,
.pme_short_desc = "SRQ slot 0 valid",
.pme_long_desc = "This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.",
- .pme_event_ids = { 69, 69, -1, -1, 70, 68, -1, -1 },
- .pme_group_vector = {
- 0x0000000040000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_SRQ_S0_VALID],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_SRQ_S0_VALID]
},
-#define PPC970MP_PME_PM_LARX_LSU0 203
[ PPC970MP_PME_PM_LARX_LSU0 ] = {
.pme_name = "PM_LARX_LSU0",
+ .pme_code = 0x727,
.pme_short_desc = "Larx executed on LSU0",
.pme_long_desc = "A larx (lwarx or ldarx) was executed on side 0 (there is no coresponding unit 1 event since larx instructions can only execute on unit 0)",
- .pme_event_ids = { 42, 41, -1, -1, 43, 40, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LARX_LSU0],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LARX_LSU0]
},
-#define PPC970MP_PME_PM_GCT_EMPTY_CYC 204
[ PPC970MP_PME_PM_GCT_EMPTY_CYC ] = {
.pme_name = "PM_GCT_EMPTY_CYC",
+ .pme_code = 0x1004,
.pme_short_desc = "Cycles GCT empty",
.pme_long_desc = "The Global Completion Table is completely empty",
- .pme_event_ids = { 28, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000200100080200ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GCT_EMPTY_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GCT_EMPTY_CYC]
},
-#define PPC970MP_PME_PM_FPU1_ALL 205
[ PPC970MP_PME_PM_FPU1_ALL ] = {
.pme_name = "PM_FPU1_ALL",
+ .pme_code = 0x107,
.pme_short_desc = "FPU1 executed add",
.pme_long_desc = " mult",
- .pme_event_ids = { 17, 16, -1, -1, 17, 16, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000800ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_ALL],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_ALL]
},
-#define PPC970MP_PME_PM_FPU1_FSQRT 206
[ PPC970MP_PME_PM_FPU1_FSQRT ] = {
.pme_name = "PM_FPU1_FSQRT",
+ .pme_code = 0x106,
.pme_short_desc = "FPU1 executed FSQRT instruction",
.pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp1 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { 21, 20, -1, -1, 21, 20, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000800ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_FSQRT],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_FSQRT]
},
-#define PPC970MP_PME_PM_FPU_FIN 207
[ PPC970MP_PME_PM_FPU_FIN ] = {
.pme_name = "PM_FPU_FIN",
+ .pme_code = 0x4110,
.pme_short_desc = "FPU produced a result",
.pme_long_desc = "FPU finished, produced a result This only indicates finish, not completion. Combined Unit 0 + Unit 1",
- .pme_event_ids = { -1, -1, -1, 22, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000080000100010ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_FIN],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_FIN]
},
-#define PPC970MP_PME_PM_LSU_SRQ_STFWD 208
[ PPC970MP_PME_PM_LSU_SRQ_STFWD ] = {
.pme_name = "PM_LSU_SRQ_STFWD",
+ .pme_code = 0x1820,
.pme_short_desc = "SRQ store forwarded",
.pme_long_desc = "Data from a store instruction was forwarded to a load",
- .pme_event_ids = { 70, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_SRQ_STFWD],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_SRQ_STFWD]
},
-#define PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU1 209
[ PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU1 ] = {
.pme_name = "PM_MRK_LD_MISS_L1_LSU1",
+ .pme_code = 0x724,
.pme_short_desc = "LSU1 L1 D cache load misses",
.pme_long_desc = "A marked load, executing on unit 1, missed the dcache",
- .pme_event_ids = { 76, 73, -1, -1, 74, 73, -1, -1 },
- .pme_group_vector = {
- 0x0000002000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU1],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU1]
},
-#define PPC970MP_PME_PM_FXU0_FIN 210
[ PPC970MP_PME_PM_FXU0_FIN ] = {
.pme_name = "PM_FXU0_FIN",
+ .pme_code = 0x332,
.pme_short_desc = "FXU0 produced a result",
.pme_long_desc = "The Fixed Point unit 0 finished an instruction and produced a result",
- .pme_event_ids = { -1, -1, 24, 25, -1, -1, 25, 25 },
- .pme_group_vector = {
- 0x0000008000000100ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FXU0_FIN],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FXU0_FIN]
},
-#define PPC970MP_PME_PM_MRK_FPU_FIN 211
[ PPC970MP_PME_PM_MRK_FPU_FIN ] = {
.pme_name = "PM_MRK_FPU_FIN",
+ .pme_code = 0x7004,
.pme_short_desc = "Marked instruction FPU processing finished",
.pme_long_desc = "One of the Floating Point Units finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, 49, -1 },
- .pme_group_vector = {
- 0x0000000400000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_FPU_FIN],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_FPU_FIN]
},
-#define PPC970MP_PME_PM_PMC5_OVERFLOW 212
[ PPC970MP_PME_PM_PMC5_OVERFLOW ] = {
.pme_name = "PM_PMC5_OVERFLOW",
+ .pme_code = 0x600a,
.pme_short_desc = "PMC5 Overflow",
.pme_long_desc = "PMC5 Overflow",
- .pme_event_ids = { -1, -1, -1, -1, -1, 77, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_PMC5_OVERFLOW],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_PMC5_OVERFLOW]
},
-#define PPC970MP_PME_PM_SNOOP_TLBIE 213
[ PPC970MP_PME_PM_SNOOP_TLBIE ] = {
.pme_name = "PM_SNOOP_TLBIE",
+ .pme_code = 0x703,
.pme_short_desc = "Snoop TLBIE",
.pme_long_desc = "A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.",
- .pme_event_ids = { 82, 77, -1, -1, 78, 78, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_SNOOP_TLBIE],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_SNOOP_TLBIE]
},
-#define PPC970MP_PME_PM_FPU1_FRSP_FCONV 214
[ PPC970MP_PME_PM_FPU1_FRSP_FCONV ] = {
.pme_name = "PM_FPU1_FRSP_FCONV",
+ .pme_code = 0x115,
.pme_short_desc = "FPU1 executed FRSP or FCONV instructions",
.pme_long_desc = "This signal is active for one cycle when fp1 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.",
- .pme_event_ids = { -1, -1, 20, 21, -1, -1, 20, 21 },
- .pme_group_vector = {
- 0x0000000000000400ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_FRSP_FCONV],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_FRSP_FCONV]
},
-#define PPC970MP_PME_PM_FPU0_FDIV 215
[ PPC970MP_PME_PM_FPU0_FDIV ] = {
.pme_name = "PM_FPU0_FDIV",
+ .pme_code = 0x100,
.pme_short_desc = "FPU0 executed FDIV instruction",
.pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp0 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.",
- .pme_event_ids = { 10, 9, -1, -1, 10, 9, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000400ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_FDIV],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_FDIV]
},
-#define PPC970MP_PME_PM_LD_REF_L1_LSU1 216
[ PPC970MP_PME_PM_LD_REF_L1_LSU1 ] = {
.pme_name = "PM_LD_REF_L1_LSU1",
+ .pme_code = 0x814,
.pme_short_desc = "LSU1 L1 D cache load references",
.pme_long_desc = "A load executed on unit 1",
- .pme_event_ids = { -1, -1, 40, 38, -1, -1, 38, 39 },
- .pme_group_vector = {
- 0x0000000000008000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LD_REF_L1_LSU1],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LD_REF_L1_LSU1]
},
-#define PPC970MP_PME_PM_HV_CYC 217
[ PPC970MP_PME_PM_HV_CYC ] = {
.pme_name = "PM_HV_CYC",
+ .pme_code = 0x3004,
.pme_short_desc = "Hypervisor Cycles",
.pme_long_desc = "Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)",
- .pme_event_ids = { -1, -1, 29, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000020080000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_HV_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_HV_CYC]
},
-#define PPC970MP_PME_PM_LR_CTR_MAP_FULL_CYC 218
[ PPC970MP_PME_PM_LR_CTR_MAP_FULL_CYC ] = {
.pme_name = "PM_LR_CTR_MAP_FULL_CYC",
+ .pme_code = 0x306,
.pme_short_desc = "Cycles LR/CTR mapper full",
.pme_long_desc = "The ISU sends a signal indicating that the lr/ctr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.",
- .pme_event_ids = { 43, 42, -1, -1, 44, 41, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000040ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LR_CTR_MAP_FULL_CYC],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LR_CTR_MAP_FULL_CYC]
},
-#define PPC970MP_PME_PM_FPU_DENORM 219
[ PPC970MP_PME_PM_FPU_DENORM ] = {
.pme_name = "PM_FPU_DENORM",
+ .pme_code = 0x1120,
.pme_short_desc = "FPU received denormalized data",
.pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized. Combined Unit 0 + Unit 1",
- .pme_event_ids = { 26, -1, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000020ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_DENORM],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_DENORM]
},
-#define PPC970MP_PME_PM_LSU0_REJECT_SRQ 220
[ PPC970MP_PME_PM_LSU0_REJECT_SRQ ] = {
.pme_name = "PM_LSU0_REJECT_SRQ",
+ .pme_code = 0x920,
.pme_short_desc = "LSU0 SRQ rejects",
.pme_long_desc = "LSU0 SRQ rejects",
- .pme_event_ids = { 52, 51, -1, -1, 53, 50, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_REJECT_SRQ],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_REJECT_SRQ]
},
-#define PPC970MP_PME_PM_LSU1_REJECT_SRQ 221
[ PPC970MP_PME_PM_LSU1_REJECT_SRQ ] = {
.pme_name = "PM_LSU1_REJECT_SRQ",
+ .pme_code = 0x924,
.pme_short_desc = "LSU1 SRQ rejects",
.pme_long_desc = "LSU1 SRQ rejects",
- .pme_event_ids = { 62, 61, -1, -1, 63, 60, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_REJECT_SRQ],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_REJECT_SRQ]
},
-#define PPC970MP_PME_PM_LSU1_DERAT_MISS 222
[ PPC970MP_PME_PM_LSU1_DERAT_MISS ] = {
.pme_name = "PM_LSU1_DERAT_MISS",
+ .pme_code = 0x706,
.pme_short_desc = "LSU1 DERAT misses",
.pme_long_desc = "A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.",
- .pme_event_ids = { 54, 53, -1, -1, 55, 52, -1, -1 },
- .pme_group_vector = {
- 0x0000000000040000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_DERAT_MISS],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_DERAT_MISS]
},
-#define PPC970MP_PME_PM_IC_PREF_REQ 223
[ PPC970MP_PME_PM_IC_PREF_REQ ] = {
.pme_name = "PM_IC_PREF_REQ",
+ .pme_code = 0x426,
.pme_short_desc = "Instruction prefetch requests",
.pme_long_desc = "Asserted when a non-canceled prefetch is made to the cache interface unit (CIU).",
- .pme_event_ids = { 35, 35, -1, -1, 37, 34, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_IC_PREF_REQ],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_IC_PREF_REQ]
},
-#define PPC970MP_PME_PM_MRK_LSU_FIN 224
[ PPC970MP_PME_PM_MRK_LSU_FIN ] = {
.pme_name = "PM_MRK_LSU_FIN",
+ .pme_code = 0x8004,
.pme_short_desc = "Marked instruction LSU processing finished",
.pme_long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete",
- .pme_event_ids = { -1, -1, -1, -1, -1, -1, -1, 60 },
- .pme_group_vector = {
- 0x0000000400000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LSU_FIN],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LSU_FIN]
},
-#define PPC970MP_PME_PM_MRK_DATA_FROM_MEM 225
[ PPC970MP_PME_PM_MRK_DATA_FROM_MEM ] = {
.pme_name = "PM_MRK_DATA_FROM_MEM",
+ .pme_code = 0x2937,
.pme_short_desc = "Marked data loaded from memory",
.pme_long_desc = "Marked data loaded from memory",
- .pme_event_ids = { -1, 88, -1, -1, -1, -1, -1, -1 },
- .pme_group_vector = {
- 0x0004000000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_DATA_FROM_MEM],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_DATA_FROM_MEM]
},
-#define PPC970MP_PME_PM_CMPLU_STALL_DCACHE_MISS 226
[ PPC970MP_PME_PM_CMPLU_STALL_DCACHE_MISS ] = {
.pme_name = "PM_CMPLU_STALL_DCACHE_MISS",
+ .pme_code = 0x50cb,
.pme_short_desc = "Completion stall caused by D cache miss",
.pme_long_desc = "Completion stall caused by D cache miss",
- .pme_event_ids = { -1, -1, -1, -1, 86, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000040000000000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CMPLU_STALL_DCACHE_MISS],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CMPLU_STALL_DCACHE_MISS]
},
-#define PPC970MP_PME_PM_LSU0_FLUSH_UST 227
[ PPC970MP_PME_PM_LSU0_FLUSH_UST ] = {
.pme_name = "PM_LSU0_FLUSH_UST",
+ .pme_code = 0x801,
.pme_short_desc = "LSU0 unaligned store flushes",
.pme_long_desc = "A store was flushed from unit 0 because it was unaligned (crossed a 4k boundary)",
- .pme_event_ids = { 48, 47, -1, -1, 49, 46, -1, -1 },
- .pme_group_vector = {
- 0x0000000000010000ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_FLUSH_UST],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_FLUSH_UST]
},
-#define PPC970MP_PME_PM_LSU_FLUSH_LRQ 228
[ PPC970MP_PME_PM_LSU_FLUSH_LRQ ] = {
.pme_name = "PM_LSU_FLUSH_LRQ",
+ .pme_code = 0x6800,
.pme_short_desc = "LRQ flushes",
.pme_long_desc = "A load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
- .pme_event_ids = { -1, -1, -1, -1, -1, 63, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000008ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_FLUSH_LRQ],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_FLUSH_LRQ]
},
-#define PPC970MP_PME_PM_LSU_FLUSH_SRQ 229
[ PPC970MP_PME_PM_LSU_FLUSH_SRQ ] = {
.pme_name = "PM_LSU_FLUSH_SRQ",
+ .pme_code = 0x5800,
.pme_short_desc = "SRQ flushes",
.pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.",
- .pme_event_ids = { -1, -1, -1, -1, 65, -1, -1, -1 },
- .pme_group_vector = {
- 0x0000000000000008ULL }
+ .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_FLUSH_SRQ],
+ .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_FLUSH_SRQ]
}
};
#define PPC970MP_PME_EVENT_COUNT 230
-static pmg_ppc970mp_group_t ppc970mp_groups[] = {
+static const int ppc970mp_group_event_ids[][PPC970MP_NUM_EVENT_COUNTERS] = {
+ [ 0 ] = { 81, 2, 65, 30, 0, 2, 28, 29 },
+ [ 1 ] = { 2, 2, 36, 6, 39, 35, 63, 37 },
+ [ 2 ] = { 36, 2, 36, 6, 39, 35, 63, 37 },
+ [ 3 ] = { 64, 63, 4, 30, 65, 63, 63, 37 },
+ [ 4 ] = { 27, 25, 21, 22, 3, 25, 30, 22 },
+ [ 5 ] = { 26, 26, 4, 30, 26, 26, 21, 43 },
+ [ 6 ] = { 87, 1, 3, 29, 44, 36, 30, 4 },
+ [ 7 ] = { 13, 21, 22, 24, 3, 35, 46, 49 },
+ [ 8 ] = { 37, 2, 24, 27, 34, 31, 30, 4 },
+ [ 9 ] = { 28, 83, 65, 10, 3, 35, 8, 10 },
+ [ 10 ] = { 10, 18, 16, 21, 11, 19, 30, 4 },
+ [ 11 ] = { 12, 20, 13, 19, 8, 16, 30, 4 },
+ [ 12 ] = { 9, 17, 14, 20, 3, 35, 12, 18 },
+ [ 13 ] = { 15, 23, 13, 19, 3, 35, 4, 16 },
+ [ 14 ] = { 45, 54, 4, 5, 47, 54, 30, 4 },
+ [ 15 ] = { 47, 56, 39, 38, 3, 35, 35, 36 },
+ [ 16 ] = { 48, 57, 67, 65, 3, 35, 62, 5 },
+ [ 17 ] = { 53, 62, 67, 65, 81, 2, 30, 4 },
+ [ 18 ] = { 44, 53, 4, 5, 38, 2, 31, 4 },
+ [ 19 ] = { 28, 64, 29, 5, 0, 35, 28, 67 },
+ [ 20 ] = { 27, 25, 26, 22, 3, 25, 30, 22 },
+ [ 21 ] = { 6, 40, 36, 63, 3, 35, 63, 37 },
+ [ 22 ] = { 6, 64, 36, 63, 3, 35, 63, 37 },
+ [ 23 ] = { 27, 25, 13, 19, 3, 26, 30, 43 },
+ [ 24 ] = { 36, 2, 36, 1, 81, 2, 1, 2 },
+ [ 25 ] = { 36, 2, 36, 1, 3, 81, 63, 37 },
+ [ 26 ] = { 81, 4, 0, 2, 41, 2, 30, 2 },
+ [ 27 ] = { 3, 87, 30, 5, 38, 2, 44, 47 },
+ [ 28 ] = { 6, 40, 30, 5, 66, 65, 32, 34 },
+ [ 29 ] = { 39, 38, 29, 30, 4, 2, 28, 5 },
+ [ 30 ] = { 68, 69, 36, 49, 38, 35, 4, 37 },
+ [ 31 ] = { 38, 36, 70, 5, 38, 2, 30, 4 },
+ [ 32 ] = { 28, 33, 32, 30, 39, 62, 63, 4 },
+ [ 33 ] = { 74, 82, 4, 51, 35, 70, 50, 30 },
+ [ 34 ] = { 72, 70, 4, 50, 35, 69, 49, 60 },
+ [ 35 ] = { 78, 2, 62, 51, 71, 75, 60, 30 },
+ [ 36 ] = { 79, 71, 56, 60, 3, 35, 54, 58 },
+ [ 37 ] = { 75, 73, 53, 57, 3, 35, 53, 57 },
+ [ 38 ] = { 36, 36, 26, 26, 28, 27, 24, 4 },
+ [ 39 ] = { 36, 2, 23, 23, 28, 27, 25, 26 },
+ [ 40 ] = { 38, 38, 31, 0, 90, 37, 4, 30 },
+ [ 41 ] = { 85, 85, 43, 12, 84, 35, 70, 4 },
+ [ 42 ] = { 88, 36, 36, 5, 86, 62, 69, 37 },
+ [ 43 ] = { 36, 27, 26, 22, 85, 27, 68, 4 },
+ [ 44 ] = { 27, 25, 30, 68, 87, 25, 67, 4 },
+ [ 45 ] = { 28, 36, 10, 3, 88, 2, 71, 33 },
+ [ 46 ] = { 36, 36, 4, 5, 91, 87, 44, 47 },
+ [ 47 ] = { 39, 38, 31, 1, 3, 35, 1, 2 },
+ [ 48 ] = { 3, 87, 30, 35, 0, 2, 36, 37 },
+ [ 49 ] = { 3, 87, 30, 5, 91, 87, 36, 37 },
+ [ 50 ] = { 71, 88, 30, 5, 92, 88, 50, 51 }
+};
+
+static const pmg_power_group_t ppc970mp_groups[] = {
[ 0 ] = {
.pmg_name = "pm_slice0",
.pmg_desc = "Time Slice 0",
- .pmg_event_ids = { 81, 2, 65, 30, 0, 2, 28, 29 },
+ .pmg_event_ids = ppc970mp_group_event_ids[0],
.pmg_mmcr0 = 0x000000000000051eULL,
.pmg_mmcr1 = 0x000000000a46f18cULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2106,7 +3088,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 1 ] = {
.pmg_name = "pm_eprof",
.pmg_desc = "Group for use with eprof",
- .pmg_event_ids = { 2, 2, 36, 6, 39, 35, 63, 37 },
+ .pmg_event_ids = ppc970mp_group_event_ids[1],
.pmg_mmcr0 = 0x0000000000000f1eULL,
.pmg_mmcr1 = 0x4003001005f09000ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2114,7 +3096,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 2 ] = {
.pmg_name = "pm_basic",
.pmg_desc = "Basic performance indicators",
- .pmg_event_ids = { 36, 2, 36, 6, 39, 35, 63, 37 },
+ .pmg_event_ids = ppc970mp_group_event_ids[2],
.pmg_mmcr0 = 0x000000000000091eULL,
.pmg_mmcr1 = 0x4003001005f09000ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2122,7 +3104,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 3 ] = {
.pmg_name = "pm_lsu",
.pmg_desc = "Information on the Load Store Unit",
- .pmg_event_ids = { 64, 63, 4, 30, 65, 63, 63, 37 },
+ .pmg_event_ids = ppc970mp_group_event_ids[3],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000f00007a400000ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2130,7 +3112,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 4 ] = {
.pmg_name = "pm_fpu1",
.pmg_desc = "Floating Point events",
- .pmg_event_ids = { 27, 25, 21, 22, 3, 25, 30, 22 },
+ .pmg_event_ids = ppc970mp_group_event_ids[4],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00000000001e0480ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2138,7 +3120,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 5 ] = {
.pmg_name = "pm_fpu2",
.pmg_desc = "Floating Point events",
- .pmg_event_ids = { 26, 26, 4, 30, 26, 26, 21, 43 },
+ .pmg_event_ids = ppc970mp_group_event_ids[5],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000020e87a400000ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2146,7 +3128,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 6 ] = {
.pmg_name = "pm_isu_rename",
.pmg_desc = "ISU Rename Pool Events",
- .pmg_event_ids = { 87, 1, 3, 29, 44, 36, 30, 4 },
+ .pmg_event_ids = ppc970mp_group_event_ids[6],
.pmg_mmcr0 = 0x0000000000001228ULL,
.pmg_mmcr1 = 0x400000218e6d84bcULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2154,7 +3136,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 7 ] = {
.pmg_name = "pm_isu_queues1",
.pmg_desc = "ISU Rename Pool Events",
- .pmg_event_ids = { 13, 21, 22, 24, 3, 35, 46, 49 },
+ .pmg_event_ids = ppc970mp_group_event_ids[7],
.pmg_mmcr0 = 0x000000000000132eULL,
.pmg_mmcr1 = 0x40000000851e994cULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2162,7 +3144,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 8 ] = {
.pmg_name = "pm_isu_flow",
.pmg_desc = "ISU Instruction Flow Events",
- .pmg_event_ids = { 37, 2, 24, 27, 34, 31, 30, 4 },
+ .pmg_event_ids = ppc970mp_group_event_ids[8],
.pmg_mmcr0 = 0x000000000000181eULL,
.pmg_mmcr1 = 0x400000b3d7b7c4bcULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2170,7 +3152,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 9 ] = {
.pmg_name = "pm_isu_work",
.pmg_desc = "ISU Indicators of Work Blockage",
- .pmg_event_ids = { 28, 83, 65, 10, 3, 35, 8, 10 },
+ .pmg_event_ids = ppc970mp_group_event_ids[9],
.pmg_mmcr0 = 0x0000000000000402ULL,
.pmg_mmcr1 = 0x400000050fde9d88ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2178,7 +3160,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 10 ] = {
.pmg_name = "pm_fpu3",
.pmg_desc = "Floating Point events by unit",
- .pmg_event_ids = { 10, 18, 16, 21, 11, 19, 30, 4 },
+ .pmg_event_ids = ppc970mp_group_event_ids[10],
.pmg_mmcr0 = 0x0000000000001028ULL,
.pmg_mmcr1 = 0x000000008d6354bcULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2186,7 +3168,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 11 ] = {
.pmg_name = "pm_fpu4",
.pmg_desc = "Floating Point events by unit",
- .pmg_event_ids = { 12, 20, 13, 19, 8, 16, 30, 4 },
+ .pmg_event_ids = ppc970mp_group_event_ids[11],
.pmg_mmcr0 = 0x000000000000122cULL,
.pmg_mmcr1 = 0x000000009de774bcULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2194,7 +3176,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 12 ] = {
.pmg_name = "pm_fpu5",
.pmg_desc = "Floating Point events by unit",
- .pmg_event_ids = { 9, 17, 14, 20, 3, 35, 12, 18 },
+ .pmg_event_ids = ppc970mp_group_event_ids[12],
.pmg_mmcr0 = 0x0000000000001838ULL,
.pmg_mmcr1 = 0x000000c0851e9958ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2202,7 +3184,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 13 ] = {
.pmg_name = "pm_fpu7",
.pmg_desc = "Floating Point events by unit",
- .pmg_event_ids = { 15, 23, 13, 19, 3, 35, 4, 16 },
+ .pmg_event_ids = ppc970mp_group_event_ids[13],
.pmg_mmcr0 = 0x000000000000193aULL,
.pmg_mmcr1 = 0x000000c89dde97e0ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2210,7 +3192,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 14 ] = {
.pmg_name = "pm_lsu_flush",
.pmg_desc = "LSU Flush Events",
- .pmg_event_ids = { 45, 54, 4, 5, 47, 54, 30, 4 },
+ .pmg_event_ids = ppc970mp_group_event_ids[14],
.pmg_mmcr0 = 0x000000000000122cULL,
.pmg_mmcr1 = 0x000c00007be774bcULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2218,7 +3200,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 15 ] = {
.pmg_name = "pm_lsu_load1",
.pmg_desc = "LSU Load Events",
- .pmg_event_ids = { 47, 56, 39, 38, 3, 35, 35, 36 },
+ .pmg_event_ids = ppc970mp_group_event_ids[15],
.pmg_mmcr0 = 0x0000000000001028ULL,
.pmg_mmcr1 = 0x000f0000851e9958ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2226,7 +3208,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 16 ] = {
.pmg_name = "pm_lsu_store1",
.pmg_desc = "LSU Store Events",
- .pmg_event_ids = { 48, 57, 67, 65, 3, 35, 62, 5 },
+ .pmg_event_ids = ppc970mp_group_event_ids[16],
.pmg_mmcr0 = 0x000000000000112aULL,
.pmg_mmcr1 = 0x000f00008d5e99dcULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2234,7 +3216,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 17 ] = {
.pmg_name = "pm_lsu_store2",
.pmg_desc = "LSU Store Events",
- .pmg_event_ids = { 53, 62, 67, 65, 81, 2, 30, 4 },
+ .pmg_event_ids = ppc970mp_group_event_ids[17],
.pmg_mmcr0 = 0x0000000000001838ULL,
.pmg_mmcr1 = 0x0003c0d08d76f4bcULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2242,7 +3224,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 18 ] = {
.pmg_name = "pm_lsu7",
.pmg_desc = "Information on the Load Store Unit",
- .pmg_event_ids = { 44, 53, 4, 5, 38, 2, 31, 4 },
+ .pmg_event_ids = ppc970mp_group_event_ids[18],
.pmg_mmcr0 = 0x000000000000122cULL,
.pmg_mmcr1 = 0x000830047bd2fe3cULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2250,7 +3232,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 19 ] = {
.pmg_name = "pm_misc",
.pmg_desc = "Misc Events for testing",
- .pmg_event_ids = { 28, 64, 29, 5, 0, 35, 28, 67 },
+ .pmg_event_ids = ppc970mp_group_event_ids[19],
.pmg_mmcr0 = 0x0000000000000404ULL,
.pmg_mmcr1 = 0x0000000023c69194ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2258,7 +3240,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 20 ] = {
.pmg_name = "pm_pe_bench1",
.pmg_desc = "PE Benchmarker group for FP analysis",
- .pmg_event_ids = { 27, 25, 26, 22, 3, 25, 30, 22 },
+ .pmg_event_ids = ppc970mp_group_event_ids[20],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x10001002001e0480ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2266,7 +3248,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 21 ] = {
.pmg_name = "pm_pe_bench4",
.pmg_desc = "PE Benchmarker group for L1 and TLB",
- .pmg_event_ids = { 6, 40, 36, 63, 3, 35, 63, 37 },
+ .pmg_event_ids = ppc970mp_group_event_ids[21],
.pmg_mmcr0 = 0x0000000000001420ULL,
.pmg_mmcr1 = 0x000b000004de9000ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2274,7 +3256,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 22 ] = {
.pmg_name = "pm_hpmcount1",
.pmg_desc = "Hpmcount group for L1 and TLB behavior",
- .pmg_event_ids = { 6, 64, 36, 63, 3, 35, 63, 37 },
+ .pmg_event_ids = ppc970mp_group_event_ids[22],
.pmg_mmcr0 = 0x0000000000001404ULL,
.pmg_mmcr1 = 0x000b000004de9000ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2282,7 +3264,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 23 ] = {
.pmg_name = "pm_hpmcount2",
.pmg_desc = "Hpmcount group for computation",
- .pmg_event_ids = { 27, 25, 13, 19, 3, 26, 30, 43 },
+ .pmg_event_ids = ppc970mp_group_event_ids[23],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x000020289dde0480ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2290,7 +3272,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 24 ] = {
.pmg_name = "pm_l1andbr",
.pmg_desc = "L1 misses and branch misspredict analysis",
- .pmg_event_ids = { 36, 2, 36, 1, 81, 2, 1, 2 },
+ .pmg_event_ids = ppc970mp_group_event_ids[24],
.pmg_mmcr0 = 0x000000000000091eULL,
.pmg_mmcr1 = 0x8003c01d0676fd6cULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2298,7 +3280,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 25 ] = {
.pmg_name = "Instruction mix: loads",
.pmg_desc = " stores and branches",
- .pmg_event_ids = { 36, 2, 36, 1, 3, 81, 63, 37 },
+ .pmg_event_ids = ppc970mp_group_event_ids[25],
.pmg_mmcr0 = 0x000000000000091eULL,
.pmg_mmcr1 = 0x8003c021065fb000ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2306,7 +3288,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 26 ] = {
.pmg_name = "pm_branch",
.pmg_desc = "SLB and branch misspredict analysis",
- .pmg_event_ids = { 81, 4, 0, 2, 41, 2, 30, 2 },
+ .pmg_event_ids = ppc970mp_group_event_ids[26],
.pmg_mmcr0 = 0x000000000000052aULL,
.pmg_mmcr1 = 0x8008000bcea2f4ecULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2314,7 +3296,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 27 ] = {
.pmg_name = "pm_data",
.pmg_desc = "data source and LMQ",
- .pmg_event_ids = { 3, 87, 30, 5, 38, 2, 44, 47 },
+ .pmg_event_ids = ppc970mp_group_event_ids[27],
.pmg_mmcr0 = 0x000000000000070eULL,
.pmg_mmcr1 = 0x0000300c4bd2ff74ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2322,7 +3304,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 28 ] = {
.pmg_name = "pm_tlb",
.pmg_desc = "TLB and LRQ plus data prefetch",
- .pmg_event_ids = { 6, 40, 30, 5, 66, 65, 32, 34 },
+ .pmg_event_ids = ppc970mp_group_event_ids[28],
.pmg_mmcr0 = 0x0000000000001420ULL,
.pmg_mmcr1 = 0x0008e03c4bfdacecULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2330,7 +3312,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 29 ] = {
.pmg_name = "pm_isource",
.pmg_desc = "inst source and tablewalk",
- .pmg_event_ids = { 39, 38, 29, 30, 4, 2, 28, 5 },
+ .pmg_event_ids = ppc970mp_group_event_ids[29],
.pmg_mmcr0 = 0x000000000000060cULL,
.pmg_mmcr1 = 0x800b00c0226ef1dcULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2338,7 +3320,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 30 ] = {
.pmg_name = "pm_sync",
.pmg_desc = "Sync and SRQ",
- .pmg_event_ids = { 68, 69, 36, 49, 38, 35, 4, 37 },
+ .pmg_event_ids = ppc970mp_group_event_ids[30],
.pmg_mmcr0 = 0x0000000000001d32ULL,
.pmg_mmcr1 = 0x0003e0c107529780ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2346,7 +3328,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 31 ] = {
.pmg_name = "pm_ierat",
.pmg_desc = "IERAT",
- .pmg_event_ids = { 38, 36, 70, 5, 38, 2, 30, 4 },
+ .pmg_event_ids = ppc970mp_group_event_ids[31],
.pmg_mmcr0 = 0x0000000000000d12ULL,
.pmg_mmcr1 = 0x80000082c3d2f4bcULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2354,7 +3336,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 32 ] = {
.pmg_name = "pm_derat",
.pmg_desc = "DERAT",
- .pmg_event_ids = { 28, 33, 32, 30, 39, 62, 63, 4 },
+ .pmg_event_ids = ppc970mp_group_event_ids[32],
.pmg_mmcr0 = 0x0000000000000436ULL,
.pmg_mmcr1 = 0x100b7052e274003cULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2362,7 +3344,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 33 ] = {
.pmg_name = "pm_mark1",
.pmg_desc = "Information on marked instructions",
- .pmg_event_ids = { 74, 82, 4, 51, 35, 70, 50, 30 },
+ .pmg_event_ids = ppc970mp_group_event_ids[33],
.pmg_mmcr0 = 0x0000000000000006ULL,
.pmg_mmcr1 = 0x00008080790852a4ULL,
.pmg_mmcra = 0x0000000000002001ULL
@@ -2370,7 +3352,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 34 ] = {
.pmg_name = "pm_mark2",
.pmg_desc = "Marked Instructions Processing Flow",
- .pmg_event_ids = { 72, 70, 4, 50, 35, 69, 49, 60 },
+ .pmg_event_ids = ppc970mp_group_event_ids[34],
.pmg_mmcr0 = 0x000000000000020aULL,
.pmg_mmcr1 = 0x0000000079484210ULL,
.pmg_mmcra = 0x0000000000002001ULL
@@ -2378,7 +3360,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 35 ] = {
.pmg_name = "pm_mark3",
.pmg_desc = "Marked Stores Processing Flow",
- .pmg_event_ids = { 78, 2, 62, 51, 71, 75, 60, 30 },
+ .pmg_event_ids = ppc970mp_group_event_ids[35],
.pmg_mmcr0 = 0x000000000000031eULL,
.pmg_mmcr1 = 0x00203004190a3f24ULL,
.pmg_mmcra = 0x0000000000002001ULL
@@ -2386,7 +3368,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 36 ] = {
.pmg_name = "pm_lsu_mark1",
.pmg_desc = "Load Store Unit Marked Events",
- .pmg_event_ids = { 79, 71, 56, 60, 3, 35, 54, 58 },
+ .pmg_event_ids = ppc970mp_group_event_ids[36],
.pmg_mmcr0 = 0x0000000000001b34ULL,
.pmg_mmcr1 = 0x000280c08d5e9850ULL,
.pmg_mmcra = 0x0000000000002001ULL
@@ -2394,7 +3376,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 37 ] = {
.pmg_name = "pm_lsu_mark2",
.pmg_desc = "Load Store Unit Marked Events",
- .pmg_event_ids = { 75, 73, 53, 57, 3, 35, 53, 57 },
+ .pmg_event_ids = ppc970mp_group_event_ids[37],
.pmg_mmcr0 = 0x0000000000001838ULL,
.pmg_mmcr1 = 0x000280c0959e99dcULL,
.pmg_mmcra = 0x0000000000002001ULL
@@ -2402,7 +3384,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 38 ] = {
.pmg_name = "pm_fxu1",
.pmg_desc = "Fixed Point events by unit",
- .pmg_event_ids = { 36, 36, 26, 26, 28, 27, 24, 4 },
+ .pmg_event_ids = ppc970mp_group_event_ids[38],
.pmg_mmcr0 = 0x0000000000000912ULL,
.pmg_mmcr1 = 0x100010020084213cULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2410,7 +3392,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 39 ] = {
.pmg_name = "pm_fxu2",
.pmg_desc = "Fixed Point events by unit",
- .pmg_event_ids = { 36, 2, 23, 23, 28, 27, 25, 26 },
+ .pmg_event_ids = ppc970mp_group_event_ids[39],
.pmg_mmcr0 = 0x000000000000091eULL,
.pmg_mmcr1 = 0x4000000ca4042d78ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2418,7 +3400,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 40 ] = {
.pmg_name = "pm_ifu",
.pmg_desc = "pm_ifu",
- .pmg_event_ids = { 38, 38, 31, 0, 90, 37, 4, 30 },
+ .pmg_event_ids = ppc970mp_group_event_ids[40],
.pmg_mmcr0 = 0x0000000000000d0cULL,
.pmg_mmcr1 = 0x800000f06b7867a4ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2426,7 +3408,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 41 ] = {
.pmg_name = "pm_cpi_stack1",
.pmg_desc = "CPI stack analysis",
- .pmg_event_ids = { 85, 85, 43, 12, 84, 35, 70, 4 },
+ .pmg_event_ids = ppc970mp_group_event_ids[41],
.pmg_mmcr0 = 0x0000000000001b3eULL,
.pmg_mmcr1 = 0x4000c0c0add6963dULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2434,7 +3416,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 42 ] = {
.pmg_name = "pm_cpi_stack2",
.pmg_desc = "CPI stack analysis",
- .pmg_event_ids = { 88, 36, 36, 5, 86, 62, 69, 37 },
+ .pmg_event_ids = ppc970mp_group_event_ids[42],
.pmg_mmcr0 = 0x0000000000000b12ULL,
.pmg_mmcr1 = 0x000b000003d60583ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2442,7 +3424,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 43 ] = {
.pmg_name = "pm_cpi_stack3",
.pmg_desc = "CPI stack analysis",
- .pmg_event_ids = { 36, 27, 26, 22, 85, 27, 68, 4 },
+ .pmg_event_ids = ppc970mp_group_event_ids[43],
.pmg_mmcr0 = 0x0000000000000916ULL,
.pmg_mmcr1 = 0x10001002001625beULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2450,7 +3432,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 44 ] = {
.pmg_name = "pm_cpi_stack4",
.pmg_desc = "CPI stack analysis",
- .pmg_event_ids = { 27, 25, 30, 68, 87, 25, 67, 4 },
+ .pmg_event_ids = ppc970mp_group_event_ids[44],
.pmg_mmcr0 = 0x0000000000000000ULL,
.pmg_mmcr1 = 0x00000000485805bdULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2458,7 +3440,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 45 ] = {
.pmg_name = "pm_cpi_stack5",
.pmg_desc = "CPI stack analysis",
- .pmg_event_ids = { 28, 36, 10, 3, 88, 2, 71, 33 },
+ .pmg_event_ids = ppc970mp_group_event_ids[45],
.pmg_mmcr0 = 0x0000000000000412ULL,
.pmg_mmcr1 = 0x90014009b6d8f672ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2466,7 +3448,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 46 ] = {
.pmg_name = "pm_data2",
.pmg_desc = "data source and LMQ",
- .pmg_event_ids = { 36, 36, 4, 5, 91, 87, 44, 47 },
+ .pmg_event_ids = ppc970mp_group_event_ids[46],
.pmg_mmcr0 = 0x0000000000000912ULL,
.pmg_mmcr1 = 0x0000300c7bce7f74ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2474,7 +3456,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 47 ] = {
.pmg_name = "pm_fetch_branch",
.pmg_desc = "Instruction fetch and branch events",
- .pmg_event_ids = { 39, 38, 31, 1, 3, 35, 1, 2 },
+ .pmg_event_ids = ppc970mp_group_event_ids[47],
.pmg_mmcr0 = 0x000000000000060cULL,
.pmg_mmcr1 = 0x800000cd6e5e9d6cULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2482,7 +3464,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 48 ] = {
.pmg_name = "pm_l1l2_miss",
.pmg_desc = "L1 and L2 miss events",
- .pmg_event_ids = { 3, 87, 30, 35, 0, 2, 36, 37 },
+ .pmg_event_ids = ppc970mp_group_event_ids[48],
.pmg_mmcr0 = 0x000000000000070eULL,
.pmg_mmcr1 = 0x000330004c86fb00ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2490,7 +3472,7 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 49 ] = {
.pmg_name = "pm_data_from",
.pmg_desc = "Data From L2 instructions",
- .pmg_event_ids = { 3, 87, 30, 5, 91, 87, 36, 37 },
+ .pmg_event_ids = ppc970mp_group_event_ids[49],
.pmg_mmcr0 = 0x000000000000070eULL,
.pmg_mmcr1 = 0x000330004bce7b00ULL,
.pmg_mmcra = 0x0000000000002000ULL
@@ -2498,11 +3480,12 @@ static pmg_ppc970mp_group_t ppc970mp_groups[] = {
[ 50 ] = {
.pmg_name = "pm_mark_data_from",
.pmg_desc = "Marked Data From L2 instructions",
- .pmg_event_ids = { 71, 88, 30, 5, 92, 88, 50, 51 },
+ .pmg_event_ids = ppc970mp_group_event_ids[50],
.pmg_mmcr0 = 0x000000000000070eULL,
.pmg_mmcr1 = 0x002030084bce72f0ULL,
.pmg_mmcra = 0x0000000000002001ULL
}
};
+
#endif
diff --git a/src/libpfm-3.y/libpfms/Makefile b/src/libpfm-3.y/libpfms/Makefile
index c8a7445de73b8fcdc9770f75f5ce0c7f981fd70f..30588fd5b87e0171c7a22f7056034f1645793e62 100644
--- a/src/libpfm-3.y/libpfms/Makefile
+++ b/src/libpfm-3.y/libpfms/Makefile
@@ -27,15 +27,14 @@ include $(TOPDIR)/rules.mk
DIRS=lib
CFLAGS+= -pthread -D_GNU_SOURCE -I./include
-LDFLAGS+=-static
-LIBS += -L./lib -lpfms -lpfm -lm
+LIBS += -L$(TOPDIR)/libpfms/lib -lpfms $(PFMLIB) -lm
TARGETS=syst_smp
all: $(TARGETS)
syst_smp: ./lib/libpfms.a syst_smp.o
- $(CC) $(LDFLAGS) -o $@ syst_smp.o $(LIBS) -lpthread
+ $(CC) $(CFLAGS) $(LDFLAGS) -o $@ syst_smp.o $(LIBS) -lpthread
clean:
@set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done
@@ -43,7 +42,13 @@ clean:
distclean: clean
-./lib/libpfms.a subdirs:
- @set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d all ; done
+.FORCE: lib/libpfms.a
+lib/libpfms.a:
+ @set -e ; $(MAKE) -C lib all
-.PHONY: install depend
+install depend: $(TARGETS)
+
+install depend:
+ifeq ($(CONFIG_PFMLIB_ARCH_SICORTEX),y)
+ @set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done
+endif
diff --git a/src/libpfm-3.y/libpfms/lib/Makefile b/src/libpfm-3.y/libpfms/lib/Makefile
index 2978f75d8e87cf154c44d8875d03aafa7d8805fc..2efc2bd9f90aa6a3279d37cced550275af9e7238 100644
--- a/src/libpfm-3.y/libpfms/lib/Makefile
+++ b/src/libpfm-3.y/libpfms/lib/Makefile
@@ -38,27 +38,45 @@ REVISION=1
AGE=0
SRCS=libpfms.c
+HEADERS=../include/libpfms.h
+ALIBPFM=libpfms.a
+TARGETS=$(ALIBPFM)
ifneq ($(CONFIG_PFMLIB_ARCH_CRAYX2),y)
SLIBPFM=libpfms.so.$(VERSION).$(REVISION).$(AGE)
+VLIBPFM=libpfms.so.$(VERSION)
endif
-TARGETS=libpfms.a $(SLIBPFM)
+
OBJS=$(SRCS:.c=.o)
SOBJS=$(OBJS:.o=.lo)
+
+#
+# assume that if llibpfm built static, libpfms should
+# also be static, i.e., likely platform does not support
+# shared libraries.
+#
+ifeq ($(CONFIG_PFMLIB_SHARED),y)
+TARGETS += $(SLIBPFM)
+endif
+
+ifeq ($(SYS),Linux)
+SLDFLAGS=-shared -Wl,-soname -Wl,libpfms.so.$(VERSION)
+endif
+
CFLAGS+=-I$(PFMSINCDIR)
all: $(TARGETS)
-$(OBJS) $(SOBJS): $(TOPDIR)/config.mk $(TOPDIR)/rules.mk Makefile
+$(OBJS) $(SOBJS): $(HEADERS) $(TOPDIR)/config.mk $(TOPDIR)/rules.mk Makefile
-libpfms.a: $(OBJS)
+libpfms.a: $(OBJS)
$(RM) $@
$(AR) cru $@ $(OBJS)
-$(SLIBPFM): $(SOBJS)
- $(CC) -shared -Wl,-soname -Wl,libpfms.so.$(VERSION) -o $@ $(SOBJS)
+$(SLIBPFM): $(SOBJS)
+ $(CC) $(CFLAGS) $(SLDFLAGS) -o $@ $(SOBJS)
$(LN) -sf $@ libpfms.so.$(VERSION)
clean:
@@ -66,4 +84,13 @@ clean:
distclean: clean
-.PHONY: install depend
+install: $(TARGETS)
+
+install:
+ -mkdir -p $(DESTDIR)$(LIBDIR)
+ $(INSTALL) -m 644 $(ALIBPFM) $(DESTDIR)$(LIBDIR)
+ $(INSTALL) $(SLIBPFM) $(DESTDIR)$(LIBDIR)
+ cd $(DESTDIR)$(LIBDIR); $(LN) $(SLIBPFM) $(VLIBPFM)
+ cd $(DESTDIR)$(LIBDIR); $(LN) $(SLIBPFM) libpfms.so
+ -mkdir -p $(DESTDIR)$(INCDIR)/perfmon
+ $(INSTALL) -m 644 $(HEADERS) $(DESTDIR)$(INCDIR)/perfmon
diff --git a/src/libpfm-3.y/rules.mk b/src/libpfm-3.y/rules.mk
index 67ee1e042e285be2058cc6ef5c0dfee30782d36b..49cd6fd385e852a2eb4a2ab1f2fbdbd88e33fa14 100644
--- a/src/libpfm-3.y/rules.mk
+++ b/src/libpfm-3.y/rules.mk
@@ -24,6 +24,8 @@
#
.SUFFIXES: .c .S .o .lo .cpp
+.PHONY: all clean distclean depend install install_examples
+
.S.o:
$(CC) $(CFLAGS) -c $*.S
.c.o:
diff --git a/src/perfctr-2.6.x/CHANGES b/src/perfctr-2.6.x/CHANGES
index 5e369e2cd1067edeccd498a084675ad94eda03bf..5f5212b38a2ee69e9d58341cf6a4ddcb4e22fd33 100755
--- a/src/perfctr-2.6.x/CHANGES
+++ b/src/perfctr-2.6.x/CHANGES
@@ -1,4 +1,4 @@
-$Id$
+$Id: CHANGES,v 1.142.2.72 2010/11/07 19:48:14 mikpe Exp $
CHANGES
=======
@@ -6,6 +6,478 @@ $Id$
[High-level changes in reverse chronological order. Detailed
driver changes are in linux/drivers/perfctr/RELEASE-NOTES.]
+Version 2.6.42, 2010-11-07
+- Classify Westmere processors as Westmere not Nehalem.
+- Update update-kernel to install arch-specific header files
+ in arch/$arch/include/asm/ for newer kernels. Also make
+ update-kernel --test trace file installation steps.
+- Update usr.src/Makefile to use the LD make variable rather
+ than plain 'ld' if set. Useful for cross-compilation and
+ builds with non-default target options.
+- Updated kernel support: 2.6.18-194.17.4.el5 (RHEL5).
+
+Version 2.6.41, 2010-06-08
+- Extend examples/perfex/ to allow users to set up values for
+ the OFFCORE_RSP MSRs on Nehalem-based processors.
+- Add driver support for OFFCORE_RSP MSRs on Nehalem-based processors.
+- Recognise more Nehalem-based processors (models 30, 37).
+- Renamed PERFCTR_X86_INTEL_COREI7 symbolic CPU/PMU type constant
+ to PERFCTR_X86_INTEL_NHLM, since it denotes the entire Nehalem
+ family not just the (original) Core i7. The old constant is
+ also defined for now, to not break source code compatibility.
+- Correct Core i7 event setup in examples/global/ to actually
+ work. It was rejected by the driver due to a copy-paste error.
+- Rewrite the missing event list message in `perfex -l/-L' to
+ indicate that this is a user-space library omission, not an
+ issue with the driver or the hardware.
+- Updated kernel support: 2.6.18-194.3.1.el5, 2.6.18-194.el5,
+ 2.6.18-164.15.1.el5 (RHEL5).
+
+Version 2.6.40, 2010-01-30
+- Preliminary support for Intel Xeon 7500 (Nehalem-based) processors.
+- Preliminary support for Intel i7-980X Gulftown processors.
+- Added support for AMD Family 11h processors (compatible with fam 10h).
+- Updated kernel support: 2.6.32, 2.6.31, 2.6.18-164.11.1.el5 and
+ 2.6.18-164.el5 (RHEL5), 2.6.9-89.0.19.EL (RHEL4).
+
+Version 2.6.39, 2009-06-11
+- Updated driver's AMD multicore detection code to actually work.
+ Tested on Istanbul and Shanghai Opterons.
+- Updated driver to allow per-thread counting of Northbridge events
+ on multicore AMD processors. Since the NB is shared between cores,
+ threads counting NB events will be forced via their CPU affinity
+ mask to core0 of the available processors. On early K8 RevE processors
+ NB events remain limited to global-mode counting, due to an erratum.
+- Updated kernel support: 2.6.30, 2.6.29, 2.6.18-128.1.10.el5 (RHEL5),
+ 2.6.18-92.1.26.el5 (RHEL5), 2.6.9-89.EL (RHEL4), 2.6.9-78.0.22.EL (RHEL4).
+
+Version 2.6.38, 2009-01-23
+- Added rvperfctr_iresume() procedure to the user-space library.
+ This allows a monitor process to resume overflow counters in a
+ target process after the target has received an overflow signal.
+- Updated kernel support: 2.6.29-rc2, 2.6.28, 2.6.18-128.el5
+ (RHEL5.3), 2.6.9-78.0.13.EL (RHEL4).
+- Removed support for 2.4 kernels. 2.4 kernels have effectively
+ been unsupported since early 2007, this change makes it official
+ by removing all 2.4-specific files and #ifdefs.
+
+Version 2.6.37, 2008-11-30
+- Preliminary support for Intel Core i7 (Nehalem) processors
+ (family 6 model 26). They are currently treated like Core 2s
+ but with four general-purpose counters, and with different
+ events and a new symbolic CPU type. The AnyThread evntsel flag
+ and "uncore" event monitoring are not yet supported.
+- Updated x86 driver to recognise Xeon 7400 (family 6 model 29)
+ as a member of the Core 2 family.
+- Extended x86 driver's CPU initialisation on Intel Core 2 and
+ newer CPUs to work around vtune leaving the performance monitor
+ unit in a "very" disabled state. Thanks to Mark Krentel for
+ reporting the problem and for facilitating tests that allowed
+ the cause of the problem to be identified.
+- Updated kernel support: 2.6.28-rc6, 2.6.18-120.el5 (RHEL5.3 beta),
+ 2.6.18-92.1.18.el5 (RHEL5), 2.6.9-78.0.8.EL (RHEL4).
+
+Version 2.6.36, 2008-10-19
+- Fixed a driver error which caused Intel Family 6 Model 23
+ processors to crash kernels with general protection faults
+ if the fixed-function counters ran in interrupt-on-overflow
+ mode. Older Intel Family 6 Model 15 processors tolerate the
+ error which is why it was not detected before. Thanks to
+ Mark Krentel for reporting the problem and for facilitating
+ tests that allowed the cause of the problem to be identified.
+- Updated kernel support: 2.6.27, 2.6.26, 2.6.18-92.1.13.el5
+ (RHEL5), 2.6.9-78.0.5.EL (RHEL4).
+
+Version 2.6.35, 2008-06-30
+- Preliminary support for Intel Atom processors added.
+ These processors are very poorly documented, but they are
+ known to be family 6 model 28, and to support Intel's
+ "architectural performance monitor". Current models seem
+ to have two general-purpose counters, one fixed-function
+ counter, and to support the seven architectural events.
+ Thanks to Steve Blackburn for running tests on his Atom.
+- Updated x86 driver to recognise the Celeron model 16h
+ as a member of the Core2 family.
+- Corrected an error in the x86 driver's control validation
+ procedure. The error was introduced in perfctr-2.6.29 when
+ support for the Core2's fixed-function counters was added.
+ The error made the driver accept some invalid controls
+ (on Core2 processors only), which could result in kernel
+ hangs due to exceptions from invalid register accesses.
+ Thanks to Anton Ertl for reporting the initial problem.
+- Updated README to add Atom and AMD Family 10h to list of
+ supported processors.
+- Updated kernel support: 2.6.26-rc8, 2.6.18-92.1.6.el5 (RHEL5),
+ 2.6.18-92.1.1.el5 (RHEL5), 2.6.9-67.0.20.EL (RHEL4).
+
+Version 2.6.35-pre1, 2008-06-23
+- Added optional close-on-exec feature for per-process perfctrs.
+ To enable it, set control.flags |= VPERFCTR_CONTROL_CLOEXEC
+ in a struct vperfctr_control object before passing it to
+ vperfctr_control(). If the flag is set when a thread executes
+ an execve() system call, then its perfctr state is detached
+ from the thread as if a call to vperfctr_unlink() had occurred.
+ If the flag is clear then the state survives execve() just like
+ it always did before.
+- The vperfctr_open() library function now sets close-on-exec
+ on the file descriptor embedded in the returned vperfctr handle.
+- Removed library support for the ancient /proc/<pid>/perfctr
+ kernel interface which hasn't worked since perfctr-2.6.0.
+
+Version 2.6.34, 2008-05-29
+- Updated kernel support: 2.6.26-rc4, 2.6.18-92.el5 (RHEL5U2),
+ 2.6.18-53.1.21.el5 (RHEL5), 2.6.16.42-0.12 (SuSE).
+- Corrected the kernel driver's version number: perfctr-2.6.33
+ forgot to increment it.
+
+Version 2.6.33, 2008-05-18
+- x86: The support for Intel Family 6 Model 23 processors added in
+ perfctr-2.6.32 was incomplete, causing overflow interrupts to not
+ work properly on those processors. This has been fixed. (Thanks
+ to Mark Krentel for reporting the issue and testing patches.)
+- Updated kernel support: 2.6.26-rc2, 2.6.18-53.1.19.el5 (RHEL5),
+ 2.6.9-67.0.15.EL (RHEL4).
+
+Version 2.6.32, 2008-04-20
+- Library: add experimental vperfctr_open_mode(mode) procedure.
+ The plain vperfctr_open() always opens the perfctr state in
+ O_CREAT|O_EXCL mode, which means that it will fail if the
+ invoking thread already has a perfctr state. The mode parameter
+ to vperfctr_open_mode() can be used to avoid this behaviour:
+ with mode == 0 no state will be created and a handle to the
+ thread's existing state (if any) is returned; to select the
+ current behaviour pass mode == VPERFCTR_OPEN_CREAT_EXCL to
+ vperfctr_open_mode(). For example:
+
+ the_state_is_shared = 0;
+ vperfctr = vperfctr_open_mode(VPERFCTR_OPEN_CREAT_EXCL);
+ if (vperfctr == NULL && errno == EEXIST) {
+ // error out due to the resource conflict, or:
+ vperfctr = vperfctr_open_mode(0);
+ the_state_is_shared = 1;
+ }
+ ...
+
+ The purpose of this API extension is to hopefully allow PAPI
+ to handle some use cases that currently cause it to error out.
+- Fix 'make install' to select the correct file to install
+ as <asm/perfctr.h>. Fixes regression caused by i386/x86_64
+ arch unification in perfctr-2.6.30. ppc32 also needed fixing.
+- x86: Recognize Intel Family 6 Model 23 as Core2.
+- Updated kernel support: 2.6.25, 2.6.18-53.1.14.el5 (RHEL5),
+ 2.6.9-67.0.7.EL (RHEL4).
+
+Version 2.6.31, 2008-01-26
+- x86: Barcelona (AMD Family 10h) updates:
+ * Correct CPU type constant to read FAM10H with trailing H.
+ The old spelling also remains, for now.
+ * Barcelona event selectors are 64-bit, not 32-bit as in K8.
+ Add evntsel_high[] array to struct perfctr_cpu_control to
+ allow passing high 32 bits of evntsels to the driver.
+ This array overlaps the p4 control sub-struct. (Uses a GCC
+ anonymous union, to avoid source-incompatible changes.)
+ Currently only some Northbridge events need the high bits.
+ * Update driver to accept and check high evntsel bits on
+ Barcelona, and to maintain all 64 evntsel bits in PMU
+ context switches.
+ * Update examples/perfex/ to indicate how to also set up
+ the high 32 evntsel bits for Barcelona (run perfex -h).
+- Minor coding style (mostly obsolete whitespace style) fixes.
+- Updated kernel support: 2.6.24, 2.6.18-53.1.6.el5 (RHEL5),
+ 2.6.9-67.0.1.EL (RHEL4).
+
+Version 2.6.30, 2007-10-28
+- Kernel 2.6.24-rc1 replaced the previously separate i386
+ and x86_64 source code directories with new shared x86
+ directories. Updated the linux/include/ hierarchy and the
+ update-kernel script to handle new and old source layouts.
+- Several driver updates to handle kernel 2.6.24-rc1 changes
+ on both x86 and ppc32.
+- Fixed a problem which could break RHEL5 kernel builds in
+ some configurations.
+- Updated kernel support: 2.6.24-rc1, 2.6.23, 2.6.18-8.1.14.el5
+ (RHEL5), and 2.6.9-55.0.6.EL (RHEL4).
+
+Version 2.6.29, 2007-10-07
+- Added support for the fixed-function counters in Intel Core 2
+ processors. To user-space they look like ordinary P6 counters,
+ except their PMC numbers are 0x40000000..0x40000002, and their
+ evntsels only need Enable, INT, and CPL fields set.
+- Preliminary support for AMD Family 10h processors.
+ Currently only events that do not need to use the high 32 bits
+ of the event select control registers are expected to work.
+- Fixed driver compilation warnings caused by perfctr needing
+ its own definitions of macros/constants that may or may not
+ be defined in the specific kernel version used.
+- Updated kernel support: 2.6.23-rc9, 2.6.5-7.276 (SuSE).
+
+Version 2.6.28, 2007-07-18
+- Fixed path to udev rules file (/etc/udev.d/ -> /etc/udev/).
+- Updated to handle changes in the 2.6.22 kernel on ppc32.
+- Updated to handle changes in the 2.6.22 kernel on x86.
+- Updated kernel support: 2.6.22, 2.6.21, 2.6.18-8.1.8.el5 (RHEL5),
+ 2.6.9-55.0.2.EL (RHEL4), and 2.6.9-55.EL (RHEL4).
+
+Version 2.6.27, 2007-04-09
+- Updated INSTALL with instructions for making /dev/perfctr
+ creation and perfctr module autoloading work with udev.
+ These instructions are known to work on Fedora Core 4.
+ Also updated the rpm package accordingly.
+- Updated for the RHEL5 2.6.18-8.1.1.el5 kernel. This kernel
+ removed a ptrace-related function that is used for perfctr's
+ remote-control API. For now, remote-control is disabled in
+ the RHEL5 kernel, but everything else should work.
+- Updated kernel support: 2.6.21-rc6, 2.6.18.2-34 (SuSE),
+ 2.6.9-42.0.10.EL (RHEL4).
+
+Version 2.6.26, 2007-02-11
+- My old @csd.uu.se email address no longer works. Updated
+ documentation and kernel messages to show my @it.uu.se address.
+- Added driver support for ARM/XScale processors. Overflow
+ interrupts are not yet supported, in part due to conflicts
+ with Intel's ixp400_eth driver. Plain event counting works.
+- Updated kernel support: 2.6.20, 2.6.19, 2.6.9-42.0.8.EL (RHEL4),
+ 2.4.34, 2.4.21-47.0.1.EL (RHEL3), 2.6.16.21 (SLES10).
+
+Version 2.6.25, 2006-10-15
+- The Intel Core 2 processors are substantially different from
+ the old Core processors. Core 2 processors are now mapped to a
+ new cpu_type PERFCTR_X86_INTEL_CORE2, and must be programmed
+ so that every EVNTSEL used has its Enable flag set. This is
+ consistent with Intel's documentation and observations made by
+ others on later steppings of the Core 2. Early steppings may
+ be more P6-like (master Enable in EVNTSEL0), but as long as a
+ control setup includes EVNTSEL0 it should work on any stepping.
+- Major x86 driver updates for changes in kernel 2.6.19-rc1.
+- Updated kernel support: 2.6.19-rc2, 2.6.18, 2.6.9-42.0.3.EL (RHEL4),
+ and 2.4.34-pre4.
+- Fixed perfex -l/-L to handle unavailability of event set data
+ gracefully and not signal an error in those cases.
+
+Version 2.6.24, 2006-09-17
+- Fixed a driver linkage failure in 64-bit x86 kernels when
+ CONFIG_PERFCTR_INIT_TESTS was enabled, caused by an omission
+ in the perfctr-2.6.23 changes to support Intel Core 2 CPUs.
+- Updated kernel support: 2.6.18-rc7, 2.6.9-42.0.2.EL (RHEL4),
+ and 2.4.34-pre2.
+
+Version 2.6.23, 2006-08-20
+- Intel Core 2 fixes: detect Core2 processors (Model 15) and
+ allow them to be used in 64-bit builds.
+- Updated kernel support: 2.6.18-rc4, 2.6.17, 2.6.9-34.0.2.EL (RHEL4),
+ 2.4.33, 2.4.34-pre1, and 2.4.21-47.EL (RHEL3).
+- The update-kernel script is now able to automatically identify
+ SuSE Linux kernel versions. A SuSE kernel MUST be configured
+ (".config" exists) for the identification to work.
+
+Version 2.6.22, 2006-06-02
+- Preliminary support for Intel Core (family 6 model 14) processors.
+- A serious error in the x86 driver's code to identify hyper-threads
+ was fixed. The driver logic is correct but it used a kernel function
+ which does not provide the required behaviour in 64-bit kernels or
+ older 32-bit kernels. As a result bogus data could be input to the
+ hyper-thread detection code, leading to various failures.
+- A change in the 2.6.16 32-bit x86 kernel caused a compilation error
+ when CONFIG_PERFCTR_INIT_TESTS was enabled. Fixed this.
+- Updated kernel support: 2.6.9-34.0.1 (RHEL4), 2.6.17-rc5, and
+ 2.4.33-pre3.
+
+Version 2.6.21, 2006-04-03
+- Updated kernel support: 2.4.21-40.EL (RHEL3), 2.6.16, and
+ 2.6.17-rc1.
+- Updates for internal changes in kernels 2.6.16 and 2.6.17-rc1.
+- Corrected a mistake in perfctr-2.6.20 which caused compilation
+ errors with RHEL3 kernels.
+
+Version 2.6.20, 2006-03-12
+- Updated kernel support: 2.6.9-34 (RHEL4), 2.6.16-rc6, and
+ 2.4.33-pre2.
+
+Version 2.6.19, 2006-01-22
+- Updated ppc32 driver for ppc32/ppc64 kernel merging changes
+ in the 2.6.16-rc1 kernel. The driver now dynamically claims
+ and release the hardware, allowing it to coexist with other
+ PMU drivers such as oprofile.
+- Updated kernel support: 2.6.16-rc1, 2.6.9-22.0.2 (RHEL4).
+
+Version 2.6.18, 2006-01-03
+- Added perfctr_get_info() library API procedure, which allows
+ users to acquire information about the system without needing
+ a handle to an open perfctr (per-process or global) state.
+- Rearranged structure marshalling descriptor declarations to
+ increase code sharing for all supported architectures.
+- Updated kernel support: 2.6.15, 2.6.14, 2.6.9-22.0.1 (RHEL4),
+ 2.6.5-7.201 (SuSE), 2.4.33-pre1, 2.4.32.
+
+Version 2.6.17, 2005-10-02
+- The x86 kernel driver has been updated to work correctly
+ on dual-core P4 processors. Previous versions would fail
+ during CPU detection (on HT DC P4s) or would erroneously
+ restrict access for one of the cores (non-HT DC P4s).
+- Updated kernel support: 2.4.21-37.EL (RHEL3), 2.4.32-rc1,
+ and 2.6.14-rc3.
+
+Version 2.6.16, 2005-09-04
+- The ppc32 driver will now compile in kernels that lack Open
+ Firmware support, which is needed for some embedded systems.
+- Updated kernel support: 2.6.9-11.EL (RHEL4), 2.4.21-32.0.1.EL
+ (RHEL3), 2.6.12, 2.6.13, 2.4.31, and 2.4.32-pre3.
+
+Version 2.6.15, 2005-05-06
+- Preliminary code in the x86/x86-64 low-level driver to detect
+ multicore AMD K8 processors, and to prevent resource conflicts
+ and an erratum related to northbridge events. On multicore K8s,
+ northbridge events are only allowed when using the global-mode
+ counters API.
+- Updated kernel support: 2.6.9-5.0.5.EL (RHEL4), 2.4.21-27.0.4.EL
+ (RHEL3), 2.4.31-pre1, and 2.6.12-rc3.
+
+Version 2.6.14, 2005-04-09
+- Changed vperfctr_open() so that if the thread already has
+ an attached perfctr state, then the call fails with EEXIST.
+ This allows self-monitoring code to detect if it is under
+ the control of an external monitoring agent, before it
+ changes the counters' control setup.
+- Reverted the workaround in perfctr-2.6.13 for the problem
+ that gcc-4.0 snapshots broke the x86/x86-64 low-level driver,
+ as recent gcc-4.0 prereleases seem to work correctly.
+- Updated kernel support: 2.4.30, 2.6.12-rc2, and 2.6.9-5.0.3
+ (RHEL4).
+
+Version 2.6.13, 2005-02-13
+- Changed the global-mode counters to allow user-space to
+ disable the in-kernel sampling timer and to move the sampling
+ points into the read system calls. This may improve sampling
+ precision in some scenarios.
+- gcc-4.0 snapshots broke the x86/x86-64 low-level driver.
+ Changed the driver to prevent those problems.
+- Updated kernel support: 2.6.11-rc4, 2.4.30-pre1, and
+ 2.4.21-27.0.2 (RHEL3).
+
+Version 2.6.12, 2004-12-19
+- PPC32 driver updated to be more robust in its detection of
+ timebase and core clock frequencies. Some information sources
+ can give wrong values for those frequencies, so the driver
+ now tries other more reliable methods first.
+- On x86/x86-64, perfctr_event_codes.h now includes P4 events.
+- On x86-64 libraries will now be installed in PREFIX/lib64/,
+ as per current standards, unless overridden by LIBDIR.
+- Perfex had a bug in which it interpreted all numbers as hex,
+ even those without "0x" prefixes. Perfex now emits warnings
+ for ambiguous numbers. To silence the warnings, (a) prefix
+ hex numbers with "0x" (preferred), or (b) use the "-d" option
+ to enable decimal numbers, which requires "0x" prefixes on
+ hex numbers, or (c) use the "-x" option to force all numbers
+ to be interpreted as hex (deprecated). The "-d" option should
+ be the default, but unfortunately that would break user-level
+ scripts that assumed that "0x"-less numbers are still hex.
+- Changes in examples/signal/ to handle glibc-2.3.3 on PPC32.
+
+Version 2.6.11, 2004-11-14
+- Workarounds for a hardware quirk on x86 and x86-64, where
+ interrupts can be delivered some time after the counters have
+ been stopped. Due to scheduling, an interrupt could be taken
+ in the context of an unrelated process, which would prematurely
+ terminate interrupt reporting for the original process.
+- Fixed a bug in the x86 and x86-64 kernels where the context-switch
+ path suspended the previous process' performance counters too late.
+ This could allow an overflow interrupt to be taken in the context
+ of an unrelated process, with effects similar to the hardware quirk
+ described above.
+- PPC32 updates: Enable overflow interrupts on all G4 processors
+ starting with the 7410 Rev 1.3, and all IBM G3 processors starting
+ with the 750FX DD2.3. Add support for MPC7447A and MPC7448.
+- Removed patches for obsolete kernels.
+
+Version 2.6.10.3, 2004-10-24
+- Driver modifications to handle two significant changes in
+ the 2.6.10-rc1 kernel.
+- PPC32: added MPC7447A and MPC7448 support.
+- Cleanups to bring the driver closer to the development version.
+
+Version 2.6.10.2, 2004-10-19
+- Updated kernel support: 2.6.9, 2.4.28-pre4.
+- Corrected the PPC32 driver's handling of MMCR0 changes due
+ to use of the FCECE or TRIGGER control flags.
+- Fixed a synchronisation error in the interface between
+ the per-process counters driver and the low-level drivers.
+ The error triggered warnings in DEBUG_SPINLOCK_SLEEP-
+ enabled kernels.
+
+Version 2.6.10.1, 2004-09-18
+- Fixed a problem causing an incomplete "wrapper" file to be
+ installed as /usr/include/asm/perfctr.h on x86_64 systems.
+
+Version 2.6.10, 2004-09-14
+- Eliminated a potential kernel crash on P4 model 3 Prescott
+ processors, due to the driver initialising two control
+ registers that have been removed from P4M3. The P4M3 Nocona
+ does not appear to have been affected by this error.
+- Fixed install procedure to not fail to install the shared
+ library's symbolic links when updating an older installation.
+- Updated kernel support: 2.4.21-20 (RHEL3), 2.4.28-pre3, 2.6.9-rc2.
+
+Version 2.6.10-pre1, 2004-08-03
+- x86-64 now uses the same driver and data structures as x86.
+ Intel's 64-bit P4 Xeon should work in the x86-64 kernel.
+ x86-64 application-level data structures have changed.
+- Updated library and example applications to include P4
+ support on x86-64.
+- Fixed update-kernel script to use 'head' in a POSIX
+ compliant way.
+- Added kernel support for the Model 13 Pentium-M.
+- Many code cleanups in the x86 driver.
+- Event 0x76 is now officially CPU_CLK_UNHALTED on AMD64.
+- Updated kernel support: 2.4.27-rc4.
+
+Version 2.6.9, 2004-07-27
+- Updated kernel support: 2.4.27-rc3, 2.6.7, 2.6.8-rc2,
+ 2.4.21-15.0.3 (RHEL3), 2.6.5-7.95 (SuSE).
+- x86: enforce -fno-unit-at-a-time with gcc-3.4, to prevent
+ kernel crashes due to stack overflow in 2.6 kernels < 2.6.6.
+- x86: do sync_core() before rdtsc() in the internal micro-
+ benchmarking code, to avoid bogus data on K8 processors.
+- x86: prevent stray WRMSR at driver init time, which could
+ disable the NMI watchdog or Oprofile.
+- x86: prevent inlining from breaking code backpatching mechanism.
+- x86: fix CONFIG_X86_LOCAL_APIC=n linkage error in init tests.
+- PPC32: fix to allow 7400/7410 to specify MMCR2[THRESHMULT].
+- PPC32: add support for generic processors using only the
+ timebase register for high-resolution time measurements.
+
+Version 2.6.8, 2004-05-29
+- Added support for the IBM PowerPC 750GX processor.
+- Updated kernel support: 2.4.27-pre3, 2.6.7-rc1, 2.6.7-rc1-mm1,
+ 2.4.21-15.EL (RHEL3), 2.6.5-1.358 (FC2).
+- Fixed an error in the 2.4.21-193 SuSE kernel patch file which
+ broke compilation on x86-64.
+- Perfctr and Oprofile can now coexist safely in newer kernels,
+ thanks to changes in kernel 2.6.6. Backported support for
+ those changes from perfctr-2.7.1.
+
+Version 2.6.7, 2004-05-04
+- Merged several x86_64-specific driver files with their x86
+ counterparts, reducing the amount of duplicated code.
+- Added textual descriptions to the library's P6 event sets.
+ From Bryan O'Sullivan.
+- Changed examples/signal/signal to count retired instructions
+ instead of retired micro-operations on AMD K7. Needed to avoid
+ a loop with the same instruction overflowing indefinitely.
+- Updated kernel support: 2.6.6-rc3, 2.4.27-pre1, 2.4.22-1.2188.nptl
+ (FC1), 2.4.21-9.0.1 (RHEL3), 2.4.20-31.9 (RH9).
+
+Version 2.6.6, 2004-02-21
+- Pentium-M has an undocumented local APIC quirk which can stop
+ perfctr interrupt delivery. Added workaround to prevent this.
+- Fixed a bug in x86-64's perfctr interrupt entry code in 2.4 kernels.
+ Luckily, the bug turned out to be harmless (a bogus "rip" value was
+ retrieved, but never used by the higher-level interrupt handler).
+- Added support for Pentium 4 Model 3 processors, which have slight
+ event set changes from earlier models.
+- Updated kernel support: 2.6.3, 2.4.25, 2.4.22-1.2174.nptl (FC1),
+ 2.4.20-30.9 (RH9), and 2.4.21-193 (SuSE). Removed support for some
+ obsolete FC1 and RH update kernels.
+
Version 2.6.5, 2004-01-26
- Relaxed and corrected control checks on Pentium 4:
* Allow ESCR.CPL_T1 to be non-zero when using global-mode
diff --git a/src/perfctr-2.6.x/INSTALL b/src/perfctr-2.6.x/INSTALL
index fbf0bd7f3933ee89018b007711c48539a115e842..61730ea1f55ee657cbde9755f8cfd1be3bfe2707 100755
--- a/src/perfctr-2.6.x/INSTALL
+++ b/src/perfctr-2.6.x/INSTALL
@@ -1,4 +1,4 @@
-$Id$
+$Id: INSTALL,v 1.19.2.3 2009/01/23 18:37:41 mikpe Exp $
INSTALLATION INSTRUCTIONS
=========================
@@ -59,10 +59,10 @@ The recommended kernel build and installation procedure is as follows:
$PDIR/update-kernel --test --patch=$V2
This applies the patch in testing mode, without actually altering
- any files. If the patch applies cleanly without any rejects, then
- you can force the use of this patch simply by removing the --test
- option to update-kernel. This usage mode is intended for experienced
- kernel builders only.
+ any files. If the patch applies cleanly without any rejects or large
+ offsets, then you can force the use of this patch simply by removing
+ the --test option to update-kernel. This usage mode is intended for
+ experienced kernel builders only.
Finally, edit $KDIR/Makefile and change EXTRAVERSION to include
something unique for THIS kernel, for example by appending "-perfctr"
@@ -109,7 +109,32 @@ The recommended kernel build and installation procedure is as follows:
DEVICE FILE
-----------
The kernel-side of this package is implemented as a character device
-driver, which has been assigned major number 10 and minor number 182.
+driver, which has been assigned /dev/perfctr with major number 10 and
+minor number 182. This device file must exist in order for user-space
+to be able to access the perfctr extensions. How the device file is
+created depends on whether /dev/ is static or dynamic.
+
+Dynamic /dev (udev)
+-------------------
+These instructions are known to work on Fedora Core 4, but may need
+adjustments for other Linux distributions. As root, execute:
+
+ cp etc/perfctr.rules /etc/udev/rules.d/99-perfctr.rules
+ cp etc/perfctr.rc /etc/rc.d/init.d/perfctr
+ chmod 755 /etc/rc.d/init.d/perfctr
+ /sbin/chkconfig --add perfctr
+
+The first step adds a udev rule so that when the perfctr driver is
+loaded into the kernel, udev will create /dev/perfctr with permissions
+that allows all users to access it.
+
+The following steps add a startup script which creates /dev/perfctr
+if the driver module is not yet loaded into the kernel. This enables
+the kernel to automatically load the perfctr module the first time the
+device file is opened.
+
+Static /dev (no udev)
+---------------------
The first time you install the package, a special file representing
this device must be created. As root, execute:
@@ -119,10 +144,7 @@ this device must be created. As root, execute:
If the driver was built as a module, it will be have to be loaded
into the kernel before it can be used. This will happen automatically
if the kernel was built with support for the kernel module loader
-(CONFIG_KMOD=y). For 2.6 kernels no further action is needed. For
-2.4 kernels, the following should be added to /etc/modules.conf:
-
- alias char-major-10-182 perfctr
+(CONFIG_KMOD=y).
LIBRARY
diff --git a/src/perfctr-2.6.x/Makefile b/src/perfctr-2.6.x/Makefile
index 1b347b7d1fc59c4679a6b2e76e4d487f043e6955..5c5f83fb5c7309e826bc65c331cfbeb563b60935 100755
--- a/src/perfctr-2.6.x/Makefile
+++ b/src/perfctr-2.6.x/Makefile
@@ -1,6 +1,6 @@
SHELL=/bin/sh
ARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/)
-SUBDIRS=usr.lib examples
+SUBDIRS=usr.lib etc examples
default: linux/include/asm/perfctr.h
$(MAKE) MAKETARGET=default all-subdirs
@@ -15,10 +15,10 @@ linux/include/asm/perfctr.h config configure:
ln -s asm-${ARCH} linux/include/asm
install: default
- etc/install.sh "$(PREFIX)" "$(BINDIR)" "$(LIBDIR)" "$(INCLDIR)"
+ etc/install.sh "$(PREFIX)" "$(BINDIR)" "$(LIBDIR)" "$(INCLDIR)" "$(ETCDIR)" "$(ARCH)"
install2:
- $(MAKE) MAKEARGS="BINDIR=$(BINDIR) LIBDIR=$(LIBDIR) INCLDIR=$(INCLDIR)" MAKETARGET=install all-subdirs
+ $(MAKE) MAKEARGS="BINDIR=$(BINDIR) LIBDIR=$(LIBDIR) INCLDIR=$(INCLDIR) ETCDIR=$(ETCDIR)" MAKETARGET=install all-subdirs
distclean realclean mrproper: clean
rm -f linux/include/asm
diff --git a/src/perfctr-2.6.x/README b/src/perfctr-2.6.x/README
index 2171dd258dda4a13e32cb544ff7c480b53a42070..428e797e6c6ba2c6d2a6241c79dd61604d9ec1ca 100755
--- a/src/perfctr-2.6.x/README
+++ b/src/perfctr-2.6.x/README
@@ -1,23 +1,24 @@
-$Id$
+$Id: README,v 1.46.2.7 2010/01/30 11:50:30 mikpe Exp $
Linux Performance-Monitoring Counters Driver
- Mikael Pettersson <mikpe@csd.uu.se>
+ Mikael Pettersson <mikpe@it.uu.se>
========================================================================
Overview
--------
-This package adds support to the Linux kernel (2.4.16 or newer)
+This package adds support to the Linux kernel (2.6.0 or newer)
for using the Performance-Monitoring Counters (PMCs) found in
many modern processors. Supported processors are:
-- All Intel Pentium processors, i.e., Pentium, Pentium MMX,
- Pentium Pro, Pentium II, Pentium III, Pentium M and Pentium 4,
- including Celeron and Xeon versions.
-- The AMD K7 and K8 processor families.
+- All Intel x86 family 5, 6, and 15 processors, i.e., Pentium,
+ Pentium MMX, Pentium Pro, Pentium II, Pentium III, Pentium M,
+ Pentium 4, Core, Core 2, Atom, and Core i7, including Celeron and Xeon versions.
+- The AMD K7, K8, Family 10h, and Family 11h processor families.
- Cyrix 6x86MX, MII, and III.
- VIA C3 (Cyrix III).
- Centaur WinChip C6/2/3.
- PowerPC 604, 7xx, and 74xx processors.
+- Intel XScale 1 and 2 processors (ARM).
PMCs are "event counters" capable of recording any of a large
number of performance-related events during execution.
@@ -62,26 +63,13 @@ The user-space library is accompanied by several example programs
that illustrate how the driver and the library can be used.
Support for performance-counter overflow interrupts is provided
-for Intel P4 and P6, and AMD K7 and K8 processors.
+where such support exists in the processors.
Limitations
-----------
-- Kernels older than 2.4.16 are not supported since perfctr-2.6.
- You can use the previous stable series, perfctr-2.4, if you
- must use an older kernel, but this has several limitations:
- * Older kernels do not support AMD64 (x86-64).
- * The performance counters in hyper-threaded P4s/Xeons cannot
- be used with kernels older than 2.4.15. You'd have to disable
- hyper-threading or SMP, or restrict yourself to TSC sampling.
- * No profiling using counter overflow interrupts, except in 2.4.10
- and newer kernels, and some early 2.4-ac/redhat kernels.
- * Application code compiled for perfctr-2.4 is not compatible
- with perfctr-2.6, and vice versa.
- * The perfctr-2.4 series does not support 2.6 kernels.
- Some of these limitations may be fixable. Contact the author if
- you are willing to fund development in this direction.
-- The performance counter interrupt facility requires SMP or
+- Kernels older than 2.6.0 are not supported.
+- The performance counter interrupt facility on x86 requires SMP or
uniprocessor APIC support. In the latter case, the BIOS must be
reasonably non-buggy. Unfortunately, this is often not the case.
- Almost no documentation. "Use the source, Luke."
@@ -101,7 +89,7 @@ Limitations
Availability
------------
This and future versions of this package can be downloaded from
-<http://www.csd.uu.se/~mikpe/linux/perfctr/>.
+<http://user.it.uu.se/~mikpe/linux/perfctr/>.
The perfctr-devel mailing list is an open forum for driver update
announcements and general discussions about the perfctr driver
@@ -111,7 +99,7 @@ and its usage. To subscribe to perfctr-devel, visit
Licensing
---------
-Copyright (C) 1999-2004 Mikael Pettersson <mikpe@csd.uu.se>
+Copyright (C) 1999-2010 Mikael Pettersson <mikpe@it.uu.se>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
diff --git a/src/perfctr-2.6.x/TODO b/src/perfctr-2.6.x/TODO
index d4b7d78e6f1d40c6c9c9b84578babda242f77ded..18db9b7e3ef58be163f4072e537c743cbdc1786b 100755
--- a/src/perfctr-2.6.x/TODO
+++ b/src/perfctr-2.6.x/TODO
@@ -6,10 +6,6 @@ Changes after perfctr-2.6.0:
Assuming 32-bit sampling precision and max sustained rate of
one event per core clock, then set the sampling timer to a
value N such that N < (2^32 * HZ) / (cpu_khz * 1000).
-- Add kernel resource manager to avoid oprofile/perfctr conflicts.
-- Move x86_setup.c's interrupt handler code to the kernel patch.
- Then try to make x86-64 use x86_setup.c instead of x86_64_setup.c.
-- Try to make x86-64 use x86_tests.c instead of x86_64_tests.c.
- Convert NR_CPUS arrays to per_cpu().
Changes after perfctr-2.7:
diff --git a/src/perfctr-2.6.x/etc/Makefile b/src/perfctr-2.6.x/etc/Makefile
index d8ba6a0d891cf8042853cc50d3b3d0dbaf14f94d..7f31f3450870e7984199218881447a103713cd76 100644
--- a/src/perfctr-2.6.x/etc/Makefile
+++ b/src/perfctr-2.6.x/etc/Makefile
@@ -1,4 +1,4 @@
-# $Id$
+# $Id: Makefile,v 1.1.2.2 2007/07/17 22:54:10 mikpe Exp $
SHELL=/bin/sh
diff --git a/src/perfctr-2.6.x/etc/costs/Athlon-1000 b/src/perfctr-2.6.x/etc/costs/Athlon-1000
index f90f585cb477d90dfbd3d1d1e42ace21e704042c..2f1127f606ac610d797b80f3310633f76d86d4cd 100755
--- a/src/perfctr-2.6.x/etc/costs/Athlon-1000
+++ b/src/perfctr-2.6.x/etc/costs/Athlon-1000
@@ -1,5 +1,19 @@
[data from a 1.0 GHz Athlon]
+PERFCTR INIT: vendor 2, family 6, model 6, stepping 2, clock 1050288 kHz
+PERFCTR INIT: NITER == 64
+PERFCTR INIT: loop overhead is 159 cycles
+PERFCTR INIT: rdtsc cost is 13.5 cycles (1025 total)
+PERFCTR INIT: rdpmc cost is 13.3 cycles (1016 total)
+PERFCTR INIT: rdmsr (counter) cost is 51.7 cycles (3474 total)
+PERFCTR INIT: rdmsr (evntsel) cost is 52.7 cycles (3538 total)
+PERFCTR INIT: wrmsr (counter) cost is 82.5 cycles (5441 total)
+PERFCTR INIT: wrmsr (evntsel) cost is 231.4 cycles (14973 total)
+PERFCTR INIT: read cr4 cost is 2.1 cycles (294 total)
+PERFCTR INIT: write cr4 cost is 62.8 cycles (4181 total)
+PERFCTR INIT: sync_core cost is 76.3 cycles (5047 total)
+perfctr: driver 2.6.11, cpu type AMD K7/K8 at 1050288 kHz
+
PERFCTR INIT: vendor 2, family 6, model 4
PERFCTR INIT: NITER == 64
PERFCTR INIT: rdpmc ticks == 1679
diff --git a/src/perfctr-2.6.x/etc/costs/Athlon64-2.0 b/src/perfctr-2.6.x/etc/costs/Athlon64-2.0
index c1e6738a76ff77209d68cfbd11c3110c7194cc90..48881dce39ae4573825d9e11ee55fd852bc37e8c 100755
--- a/src/perfctr-2.6.x/etc/costs/Athlon64-2.0
+++ b/src/perfctr-2.6.x/etc/costs/Athlon64-2.0
@@ -1,15 +1,33 @@
-[data from a 2.0 GHz Athlon64]
+[data from a 2.0 GHz Athlon64 in 32-bit mode]
-PERFCTR INIT: vendor 2, family 15, model 4, stepping 8, clock 2000139 kHz
+PERFCTR INIT: vendor 2, family 15, model 4, stepping 8, clock 2000097 kHz
PERFCTR INIT: NITER == 64
-PERFCTR INIT: loop overhead is 79 cycles
-PERFCTR INIT: rdtsc cost is 6.2 cycles (479 total)
-PERFCTR INIT: rdpmc cost is 13.3 cycles (936 total)
-PERFCTR INIT: rdmsr (counter) cost is 50.9 cycles (3342 total)
-PERFCTR INIT: rdmsr (evntsel) cost is 56.6 cycles (3703 total)
-PERFCTR INIT: wrmsr (counter) cost is 72.7 cycles (4737 total)
-PERFCTR INIT: wrmsr (evntsel) cost is 333.0 cycles (21396 total)
-PERFCTR INIT: read cr4 cost is 5.9 cycles (462 total)
-PERFCTR INIT: write cr4 cost is 67.1 cycles (4375 total)
-perfctr: disabled lapic_nmi_watchdog
-perfctr: driver 2.6.2, cpu type AMD K8C at 2000139 kHz
+PERFCTR INIT: loop overhead is 244 cycles
+PERFCTR INIT: rdtsc cost is 19.8 cycles (1513 total)
+PERFCTR INIT: rdpmc cost is 20.6 cycles (1565 total)
+PERFCTR INIT: rdmsr (counter) cost is 52.3 cycles (3597 total)
+PERFCTR INIT: rdmsr (evntsel) cost is 57.6 cycles (3932 total)
+PERFCTR INIT: wrmsr (counter) cost is 74.8 cycles (5035 total)
+PERFCTR INIT: wrmsr (evntsel) cost is 331.7 cycles (21473 total)
+PERFCTR INIT: read cr4 cost is 9.2 cycles (835 total)
+PERFCTR INIT: write cr4 cost is 69.9 cycles (4723 total)
+PERFCTR INIT: write LVTPC cost is 24.5 cycles (1816 total)
+PERFCTR INIT: sync_core cost is 167.3 cycles (10955 total)
+perfctr: driver 2.6.9, cpu type AMD K8C at 2000097 kHz
+
+[data from a 2.0 GHz Athlon64 in 64-bit mode]
+
+PERFCTR INIT: vendor 2, family 15, model 4, stepping 8, clock 2000119 kHz
+PERFCTR INIT: NITER == 64
+PERFCTR INIT: loop overhead is 244 cycles
+PERFCTR INIT: rdtsc cost is 12.6 cycles (1052 total)
+PERFCTR INIT: rdpmc cost is 18.2 cycles (1412 total)
+PERFCTR INIT: rdmsr (counter) cost is 55.1 cycles (3776 total)
+PERFCTR INIT: rdmsr (evntsel) cost is 57.2 cycles (3907 total)
+PERFCTR INIT: wrmsr (counter) cost is 73.5 cycles (4952 total)
+PERFCTR INIT: wrmsr (evntsel) cost is 332.3 cycles (21512 total)
+PERFCTR INIT: read cr4 cost is 6.0 cycles (629 total)
+PERFCTR INIT: write cr4 cost is 68.7 cycles (4642 total)
+PERFCTR INIT: write LVTPC cost is 24.7 cycles (1831 total)
+PERFCTR INIT: sync_core cost is 163.9 cycles (10739 total)
+perfctr: driver 2.6.9, cpu type AMD K8C at 2000119 kHz
diff --git a/src/perfctr-2.6.x/etc/install.sh b/src/perfctr-2.6.x/etc/install.sh
index 3f8a4e837c7ac13d53e32b8ff1bbaa4f503a7d3f..9a53ca389720dbb24b86869b728ad46aa860caed 100755
--- a/src/perfctr-2.6.x/etc/install.sh
+++ b/src/perfctr-2.6.x/etc/install.sh
@@ -1,13 +1,24 @@
#!/bin/sh
-# $Id$
-# usage: etc/install.sh PREFIX BINDIR LIBDIR INCLDIR
+# $Id: install.sh,v 1.1.2.2 2007/04/09 12:50:36 mikpe Exp $
+# usage: etc/install.sh PREFIX BINDIR LIBDIR INCLDIR ETCDIR ARCH
# If unset, {BIN,LIB,INCL}DIR are given default values from PREFIX.
-# Then make install2 is invoked with the final {BIN,LIB,INCL}DIR.
+# Then make install2 is invoked with the final {BIN,LIB,INCL,ETC}DIR.
PREFIX=$1
BINDIR=$2
LIBDIR=$3
INCLDIR=$4
+ETCDIR=$5
+ARCH=$6
+
+case "$ARCH" in
+ x86_64)
+ LIBSUFFIX=lib64
+ ;;
+ *)
+ LIBSUFFIX=lib
+ ;;
+esac
fix_var() {
if [ -z "$1" ]; then
@@ -20,7 +31,7 @@ fix_var() {
}
fix_var "$BINDIR" BINDIR bin
-fix_var "$LIBDIR" LIBDIR lib
+fix_var "$LIBDIR" LIBDIR $LIBSUFFIX
fix_var "$INCLDIR" INCLDIR include
-exec make "BINDIR=$BINDIR" "LIBDIR=$LIBDIR" "INCLDIR=$INCLDIR" install2
+exec make "BINDIR=$BINDIR" "LIBDIR=$LIBDIR" "INCLDIR=$INCLDIR" "ETCDIR=$ETCDIR" install2
diff --git a/src/perfctr-2.6.x/etc/p4.c b/src/perfctr-2.6.x/etc/p4.c
index eb3e467cd29506b5d6544833811906610fe726a9..6b3f8ed211eb351eec441b5a39ce06e8b0951357 100755
--- a/src/perfctr-2.6.x/etc/p4.c
+++ b/src/perfctr-2.6.x/etc/p4.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: p4.c,v 1.7 2004/02/20 21:33:25 mikpe Exp $
*
* pipe stdout through 'sort -u' to see:
* - which ESCRs are usable, and the events they support
@@ -123,8 +123,8 @@ enum escr_num {
IS_ESCR1, /* UNUSED */
ITLB_ESCR0, /* ITLB_reference */
ITLB_ESCR1, /* ITLB_reference */
- CRU_ESCR0, /* instr_retired, mispred_branch_retired, uops_retired */
- CRU_ESCR1, /* instr_retired, mispred_branch_retired, uops_retired */
+ CRU_ESCR0, /* instr_retired, mispred_branch_retired, uops_retired, instr_completed */
+ CRU_ESCR1, /* instr_retired, mispred_branch_retired, uops_retired, instr_completed */
IQ_ESCR0, /* UNUSED; available in family 0x0F models 1 and 2, removed from later models */
IQ_ESCR1, /* UNUSED; available in family 0x0F models 1 and 2, removed from later models */
RAT_ESCR0, /* uop_type */
@@ -134,8 +134,8 @@ enum escr_num {
MS_ESCR1, /* tc_ms_xfer, uop_queue_writes */
TBPU_ESCR0, /* retired_branch_type, retired_mispred_branch_type */
TBPU_ESCR1, /* retired_branch_type, retired_mispred_branch_type */
- TC_ESCR0, /* TC_deliver_mode */
- TC_ESCR1, /* TC_deliver_mode */
+ TC_ESCR0, /* TC_deliver_mode, TC_misc */
+ TC_ESCR1, /* TC_deliver_mode, TC_misc */
IX_ESCR0, /* UNUSED */
IX_ESCR1, /* UNUSED */
ALF_ESCR0, /* resource_stall */
@@ -437,6 +437,7 @@ static const struct event events[] = {
{ "128bit_MMX_uop", 0x1A, FIRM_ESCR0, FIRM_ESCR1 },
{ "x87_FP_uop", 0x04, FIRM_ESCR0, FIRM_ESCR1 },
{ "x87_SIMD_moves_uop", 0x2E, FIRM_ESCR0, FIRM_ESCR1 },
+ { "TC_misc", 0x06, TC_ESCR0, TC_ESCR1 },
{ "global_power_events", 0x13, FSB_ESCR0, FSB_ESCR1 },
{ "tc_ms_xfer", 0x05, MS_ESCR0, MS_ESCR1 },
{ "uop_queue_writes", 0x09, MS_ESCR0, MS_ESCR1 },
@@ -459,6 +460,8 @@ static const struct event events[] = {
{ "mispred_branch_retired", 0x03, CRU_ESCR0, CRU_ESCR1 },
{ "x87_assist", 0x03, CRU_ESCR2, CRU_ESCR3 },
{ "machine_clear", 0x02, CRU_ESCR2, CRU_ESCR3 },
+ /* Model 3 only */
+ { "instr_completed", 0x07, CRU_ESCR0, CRU_ESCR1 },
};
static void do_escr(unsigned int escr_num)
diff --git a/src/perfctr-2.6.x/examples/global/Makefile b/src/perfctr-2.6.x/examples/global/Makefile
index 92a4e44a408373b1c0596cbe36086ab328e4ed91..7c41f6b3d066711aa5260873a0dbd05529af6450 100755
--- a/src/perfctr-2.6.x/examples/global/Makefile
+++ b/src/perfctr-2.6.x/examples/global/Makefile
@@ -1,4 +1,4 @@
-# $Id$
+# $Id: Makefile,v 1.8.2.1 2007/02/11 20:14:31 mikpe Exp $
SHELL=/bin/sh
ARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/)
@@ -10,6 +10,7 @@ TARGET=global
i386_OBJS=x86.o
x86_64_OBJS=x86.o
ppc_OBJS=ppc.o
+arm_OBJS=arm.o
ARCH_OBJS=$($(ARCH)_OBJS)
OBJS=global.o $(ARCH_OBJS)
diff --git a/src/perfctr-2.6.x/examples/global/arch.h b/src/perfctr-2.6.x/examples/global/arch.h
index 7935e9d81856484079df5d1670146a4e03c7a049..345748c163ee030907b310f21b86b48cd462ddc6 100755
--- a/src/perfctr-2.6.x/examples/global/arch.h
+++ b/src/perfctr-2.6.x/examples/global/arch.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: arch.h,v 1.1 2004/01/11 22:07:12 mikpe Exp $
* Architecture-specific support code.
*
* Copyright (C) 2004 Mikael Pettersson
diff --git a/src/perfctr-2.6.x/examples/global/arm.c b/src/perfctr-2.6.x/examples/global/arm.c
index d480fe65daf40b2e92197cf36c7b043844cb4276..e552402212bb66ef3d9f4bf403e052a2bd1305ef 100644
--- a/src/perfctr-2.6.x/examples/global/arm.c
+++ b/src/perfctr-2.6.x/examples/global/arm.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: arm.c,v 1.1.2.1 2007/02/11 20:14:31 mikpe Exp $
* ARM-specific code.
*
* Copyright (C) 2005-2007 Mikael Pettersson
diff --git a/src/perfctr-2.6.x/examples/global/global.c b/src/perfctr-2.6.x/examples/global/global.c
index 286b2eda1af38eadf4abde73cdf7f70be6dc591f..782746502548f006bc1e7d9fe7dc0118d176f785 100755
--- a/src/perfctr-2.6.x/examples/global/global.c
+++ b/src/perfctr-2.6.x/examples/global/global.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: global.c,v 1.37 2004/01/12 14:25:40 mikpe Exp $
*
* usage: ./global [sampling_interval_usec [sleep_interval_sec]]
*
diff --git a/src/perfctr-2.6.x/examples/global/ppc.c b/src/perfctr-2.6.x/examples/global/ppc.c
index 8d01c6ff93d9456dbac8a3de70471dc6b7c19ce5..4a6190b9fe95ea4a0a4fce3a48c87b9cb4d762df 100755
--- a/src/perfctr-2.6.x/examples/global/ppc.c
+++ b/src/perfctr-2.6.x/examples/global/ppc.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: ppc.c,v 1.1.2.1 2004/06/21 22:41:44 mikpe Exp $
* PPC32-specific code.
*
* Copyright (C) 2004 Mikael Pettersson
@@ -14,8 +14,10 @@ void setup_control(const struct perfctr_info *info,
{
memset(control, 0, sizeof *control);
control->tsc_on = 1;
- control->nractrs = 1;
- control->pmc_map[0] = 0;
- control->evntsel[0] = 0x02; /* INSTRUCTIONS_COMPLETED */
- counting_mips = 1;
+ if (info->cpu_type > PERFCTR_PPC_GENERIC) {
+ control->nractrs = 1;
+ control->pmc_map[0] = 0;
+ control->evntsel[0] = 0x02; /* INSTRUCTIONS_COMPLETED */
+ counting_mips = 1;
+ }
}
diff --git a/src/perfctr-2.6.x/examples/global/x86.c b/src/perfctr-2.6.x/examples/global/x86.c
index a5de9e207ceda597c92dabac5ba1fe6b0f4c7ca2..e36b90a1c7dc1f027fb169ed26b4ccfdd5d84d11 100755
--- a/src/perfctr-2.6.x/examples/global/x86.c
+++ b/src/perfctr-2.6.x/examples/global/x86.c
@@ -1,7 +1,7 @@
-/* $Id$
+/* $Id: x86.c,v 1.2.2.11 2010/11/07 19:46:06 mikpe Exp $
* x86-specific code.
*
- * Copyright (C) 2000-2004 Mikael Pettersson
+ * Copyright (C) 2000-2010 Mikael Pettersson
*/
#include <stdio.h>
#include <stdlib.h>
@@ -21,12 +21,13 @@ void setup_control(const struct perfctr_info *info,
/* Attempt to set up control to count clocks via the TSC
and FLOPS via PMC0. */
- switch( info->cpu_type ) {
+ switch (info->cpu_type) {
case PERFCTR_X86_GENERIC:
nractrs = 0; /* no PMCs available */
break;
case PERFCTR_X86_AMD_K8:
case PERFCTR_X86_AMD_K8C:
+ case PERFCTR_X86_AMD_FAM10H:
/* RETIRED_FPU_INSTRS, Unit Mask "x87 instrs", any CPL, Enable */
evntsel0 = 0xCB | (0x01 << 8) | (3 << 16) | (1 << 22);
break;
@@ -41,10 +42,28 @@ void setup_control(const struct perfctr_info *info,
case PERFCTR_X86_INTEL_PII:
case PERFCTR_X86_INTEL_PIII:
case PERFCTR_X86_INTEL_PENTM:
+ case PERFCTR_X86_INTEL_CORE:
/* note: FLOPS is only available in PERFCTR0 */
/* event 0xC1 (FLOPS), any CPL, Enable */
evntsel0 = 0xC1 | (3 << 16) | (1 << 22);
break;
+#endif
+ case PERFCTR_X86_INTEL_CORE2:
+ /* event 0xC1 umask 0xFE (X87_OPS_RETIRED_ANY), any CPL, Enable */
+ evntsel0 = 0xC1 | (0xFE << 8) | (3 << 16) | (1 << 22);
+ break;
+ case PERFCTR_X86_INTEL_ATOM:
+ /* Atom's architectural events don't include FLOPS */
+ counting_mips = 1;
+ /* event 0xC0 (RETIRED_INSTRUCTIONS), any CPL, Enable */
+ evntsel0 = 0xC0 | (3 << 16) | (1 << 22);
+ break;
+ case PERFCTR_X86_INTEL_NHLM:
+ case PERFCTR_X86_INTEL_WSTMR:
+ /* FP_COMP_OPS_EXE.ANY, any CPL, Enable */
+ evntsel0 = 0x10 | (0xFF << 8) | (3 << 16) | (1 << 22);
+ break;
+#if !defined(__x86_64__)
case PERFCTR_X86_AMD_K7:
/* K7 apparently can't count FLOPS. */
counting_mips = 1;
@@ -68,6 +87,8 @@ void setup_control(const struct perfctr_info *info,
break;
case PERFCTR_X86_INTEL_P4:
case PERFCTR_X86_INTEL_P4M2:
+#endif
+ case PERFCTR_X86_INTEL_P4M3:
nractrs = 2;
/* set up PMC(1) to produce tagged x87_FP_uop:s */
control->pmc_map[1] = 0x8 | (1 << 31);
@@ -78,7 +99,6 @@ void setup_control(const struct perfctr_info *info,
evntsel0 = (0x3 << 16) | (5 << 13) | (1 << 12);
control->p4.escr[0] = (0xC << 25) | (1 << 9) | (1 << 2);
break;
-#endif
default:
fprintf(stderr, "cpu_type %u (%s) not supported\n",
info->cpu_type, perfctr_info_cpu_name(info));
diff --git a/src/perfctr-2.6.x/examples/perfex/Makefile b/src/perfctr-2.6.x/examples/perfex/Makefile
index 31cde535d3833c80dc48730bf80781fc90c97a38..b31a187b832332b6b6de74104d06467d48621a13 100755
--- a/src/perfctr-2.6.x/examples/perfex/Makefile
+++ b/src/perfctr-2.6.x/examples/perfex/Makefile
@@ -1,4 +1,4 @@
-# $Id$
+# $Id: Makefile,v 1.5.2.1 2007/02/11 20:14:31 mikpe Exp $
SHELL=/bin/sh
ARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/)
@@ -10,6 +10,7 @@ TARGET=perfex
i386_OBJS=x86.o
x86_64_OBJS=x86.o
ppc_OBJS=ppc.o
+arm_OBJS=arm.o
ARCH_OBJS=$($(ARCH)_OBJS)
OBJS=perfex.o $(ARCH_OBJS)
diff --git a/src/perfctr-2.6.x/examples/perfex/arch.h b/src/perfctr-2.6.x/examples/perfex/arch.h
index 657db0c505a015d1c036bbccfa74549910ce6e28..dfa1c8c5f2b061721adc30779fb86eed98c14a82 100755
--- a/src/perfctr-2.6.x/examples/perfex/arch.h
+++ b/src/perfctr-2.6.x/examples/perfex/arch.h
@@ -1,17 +1,21 @@
-/* $Id$
+/* $Id: arch.h,v 1.2.2.3 2010/06/08 20:48:55 mikpe Exp $
* Architecture-specific support code.
*
- * Copyright (C) 2004 Mikael Pettersson
+ * Copyright (C) 2004-2010 Mikael Pettersson
*/
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
extern void do_print(FILE *resfile,
+ const struct perfctr_info *info,
const struct perfctr_cpu_control *cpu_control,
const struct perfctr_sum_ctrs *sum);
extern void do_arch_usage(void);
+/* Hack while phasing out an old number parsing bug. */
+extern unsigned long my_strtoul(const char *nptr, char **endptr);
+
extern unsigned int do_event_spec(unsigned int n,
const char *arg,
struct perfctr_cpu_control *cpu_control);
@@ -24,4 +28,6 @@ extern int do_arch_option(int ch,
#include "x86.h"
#elif defined(__powerpc__)
#include "ppc.h"
+#elif defined(__arm__)
+#include "arm.h"
#endif
diff --git a/src/perfctr-2.6.x/examples/perfex/arm.c b/src/perfctr-2.6.x/examples/perfex/arm.c
index 3d3923bcb3de2a248f898fe17d41ff3ca06cad99..c4b1d3312333fb4816ae814a7c2bfb13d1c95363 100644
--- a/src/perfctr-2.6.x/examples/perfex/arm.c
+++ b/src/perfctr-2.6.x/examples/perfex/arm.c
@@ -1,7 +1,7 @@
-/* $Id$
+/* $Id: arm.c,v 1.1.2.2 2010/06/08 20:48:56 mikpe Exp $
* ARM-specific code.
*
- * Copyright (C) 2005-2007 Mikael Pettersson
+ * Copyright (C) 2005-2010 Mikael Pettersson
*/
#include <stdio.h>
#include <stdlib.h>
@@ -9,6 +9,7 @@
#include "arch.h"
void do_print(FILE *resfile,
+ const struct perfctr_info *info,
const struct perfctr_cpu_control *cpu_control,
const struct perfctr_sum_ctrs *sum)
{
diff --git a/src/perfctr-2.6.x/examples/perfex/arm.h b/src/perfctr-2.6.x/examples/perfex/arm.h
index fdc47f228e98f6fb216b4f925641d17cd5f32bed..92efd6da426645ff68f4d2fb603b66f484bda6bd 100644
--- a/src/perfctr-2.6.x/examples/perfex/arm.h
+++ b/src/perfctr-2.6.x/examples/perfex/arm.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: arm.h,v 1.1.2.1 2007/02/11 20:14:31 mikpe Exp $
* ARM-specific declarations.
*
* Copyright (C) 2005-2007 Mikael Pettersson
diff --git a/src/perfctr-2.6.x/examples/perfex/perfex.c b/src/perfctr-2.6.x/examples/perfex/perfex.c
index 4de982373210ae790fdd697572e9868990831bd5..b4a2eda50adfaca732d24a997028ca9c60a81214 100755
--- a/src/perfctr-2.6.x/examples/perfex/perfex.c
+++ b/src/perfctr-2.6.x/examples/perfex/perfex.c
@@ -1,10 +1,10 @@
-/* $Id$
+/* $Id: perfex.c,v 1.33.2.8 2010/06/08 20:48:56 mikpe Exp $
*
* NAME
- * perfex - a command-line interface to x86 performance counters
+ * perfex - a command-line interface to processor performance counters
*
* SYNOPSIS
- * perfex [-e event] .. [--p4pe=value] [--p4pmv=value] [-o file] command
+ * perfex [-e event] .. [--nhlm_offcore_rsp_{0,1}=value] [--p4{pe,pmv}=value] [-o file] command
* perfex { -i | -l | -L }
*
* DESCRIPTION
@@ -17,28 +17,35 @@
* Multiple event specifiers may be given, limited by the
* number of available performance counters in the processor.
*
- * The full syntax of an event specifier is "evntsel/escr@pmc".
+ * The full syntax of an event specifier is "evntsel/evntsel2@pmc".
* All three components are 32-bit processor-specific numbers,
* written in decimal or hexadecimal notation.
*
* "evntsel" is the primary processor-specific event selection
* code to use for this event. This field is mandatory.
*
- * "/escr" is used to specify additional event selection data
- * for Pentium 4 processors. "evntsel" is put in the counter's
- * CCCR register, and "escr" is put in the associated ESCR
- * register.
+ * "/evntsel2" provides auxiliary event selection data for this
+ * event. On a Pentium 4, "evntsel" is put in the counter's
+ * CCCR register, and "evntsel2" is put in the associated ESCR
+ * register. On an AMD Family 10h processor, "evntsel2" is put
+ * in the high 32 bits of the counter's 64-bit EVNTSEL register.
+ * On other processors "/evntsel2" should be omitted.
*
* "@pmc" describes which CPU counter number to assign this
* event to. When omitted, the events are assigned in the
* order listed, starting from 0. Either all or none of the
* event specifiers should use the "@pmc" notation.
* Explicit counter assignment via "@pmc" is required on
- * Pentium 4 and VIA C3 processors.
+ * Pentium 4 and VIA C3 processors. It is also required for the
+ * fixed-function counters on Core 2 and Atom processors.
*
* The counts, together with an event description are written
* to the result file (default is stderr).
*
+ * --nhlm_offcore_rsp_{0,1}=value
+ * Specify the value to be stored in the auxiliary control
+ * registers OFFCORE_RSP_{0,1} on Nehalem processors.
+ *
* --p4pe=value | --p4_pebs_enable=value
* --p4pmv=value | --p4_pebs_matrix_vert=value
* Specify the value to be stored in the auxiliary control
@@ -90,15 +97,15 @@
* metric. Note that bit 25 is NOT set in PEBS_ENABLE.
*
* DEPENDENCIES
- * perfex only works on Linux/x86 systems which have been modified
- * to include the perfctr driver. This driver is available at
- * http://www.csd.uu.se/~mikpe/linux/perfctr/.
+ * perfex only works on Linux systems which have been modified
+ * to include the perfctr kernel extension. Perfctr is available at
+ * http://user.it.uu.se/~mikpe/linux/perfctr/.
*
* NOTES
* perfex is superficially similar to IRIX' perfex(1).
* The -a, -mp, -s, and -x options are not yet implemented.
*
- * Copyright (C) 1999-2004 Mikael Pettersson
+ * Copyright (C) 1999-2010 Mikael Pettersson
*/
/*
@@ -163,7 +170,7 @@ static int my_send(int sock, int fd, int status)
msg.msg_iov = &iov;
msg.msg_iovlen = 1;
- if( status != 0 ) { /* errno, don't send fd */
+ if (status != 0) { /* errno, don't send fd */
msg.msg_control = 0;
msg.msg_controllen = 0;
} else {
@@ -208,21 +215,21 @@ static int my_receive(int sock, int *fd)
msg.msg_control = &cmsg_fd;
msg.msg_controllen = CMSG_FD_TRUE_SIZE;
- if( recvmsg(sock, &msg, 0) != sizeof buf )
+ if (recvmsg(sock, &msg, 0) != sizeof buf)
return -1;
- if( buf[0] == 0 &&
+ if (buf[0] == 0 &&
msg.msg_control == &cmsg_fd &&
msg.msg_controllen == CMSG_FD_PADDED_SIZE &&
cmsg_fd.hdr.cmsg_type == SCM_RIGHTS &&
cmsg_fd.hdr.cmsg_level == SOL_SOCKET &&
cmsg_fd.hdr.cmsg_len == CMSG_FD_TRUE_SIZE &&
- cmsg_fd.fd >= 0 ) {
+ cmsg_fd.fd >= 0) {
*fd = cmsg_fd.fd;
return 0;
}
- if( msg.msg_controllen == 0 && buf[0] != 0 )
+ if (msg.msg_controllen == 0 && buf[0] != 0)
errno = buf[0];
else
errno = EPROTO;
@@ -234,7 +241,7 @@ static int do_open_self(int creat)
int fd;
fd = _vperfctr_open(creat);
- if( fd >= 0 && perfctr_abi_check_fd(fd) < 0 ) {
+ if (fd >= 0 && perfctr_abi_check_fd(fd) < 0) {
close(fd);
return -1;
}
@@ -246,15 +253,15 @@ static int do_child(int sock, const struct vperfctr_control *control, char **arg
int fd;
fd = do_open_self(1);
- if( fd < 0 ) {
+ if (fd < 0) {
my_send_err(sock);
return 1;
}
- if( _vperfctr_control(fd, control) < 0 ) {
+ if (_vperfctr_control(fd, control) < 0) {
my_send_err(sock);
return 1;
}
- if( my_send_fd(sock, fd) < 0 ) {
+ if (my_send_fd(sock, fd) < 0) {
my_send_err(sock); /* well, we can try.. */
return 1;
}
@@ -265,7 +272,7 @@ static int do_child(int sock, const struct vperfctr_control *control, char **arg
return 1;
}
-static int do_parent(int sock, int child_pid, FILE *resfile)
+static int do_parent(int sock, int child_pid, FILE *resfile, const struct perfctr_info *info)
{
int child_status;
int fd;
@@ -273,55 +280,56 @@ static int do_parent(int sock, int child_pid, FILE *resfile)
struct vperfctr_control control;
/* this can be done before or after the recvmsg() */
- if( waitpid(child_pid, &child_status, 0) < 0 ) {
+ if (waitpid(child_pid, &child_status, 0) < 0) {
perror("perfex: waitpid");
return 1;
}
- if( !WIFEXITED(child_status) ) {
+ if (!WIFEXITED(child_status)) {
fprintf(stderr, "perfex: child did not exit normally\n");
return 1;
}
- if( my_receive(sock, &fd) < 0 ) {
+ if (my_receive(sock, &fd) < 0) {
perror("perfex: receiving fd/status");
return 1;
}
close(sock);
/* XXX: surely we don't need to repeat the ABI check here? */
- if( _vperfctr_read_sum(fd, &sum) < 0 ) {
+ if (_vperfctr_read_sum(fd, &sum) < 0) {
perror("perfex: read_sum");
return 1;
}
- if( _vperfctr_read_control(fd, &control) < 0 ) {
+ if (_vperfctr_read_control(fd, &control) < 0) {
perror("perfex: read_control");
return 1;
}
close(fd);
- do_print(resfile, &control.cpu_control, &sum);
+ do_print(resfile, info, &control.cpu_control, &sum);
return WEXITSTATUS(child_status);
}
-static int do_perfex(const struct vperfctr_control *control, char **argv, FILE *resfile)
+static int do_perfex(
+ const struct vperfctr_control *control, char **argv, FILE *resfile, const struct perfctr_info *info)
{
int pid;
int sv[2];
- if( socketpair(AF_UNIX, SOCK_DGRAM, 0, sv) < 0 ) {
+ if (socketpair(AF_UNIX, SOCK_DGRAM, 0, sv) < 0) {
perror("perfex: socketpair");
return 1;
}
pid = fork();
- if( pid < 0 ) {
+ if (pid < 0) {
perror("perfex: fork");
return 1;
}
- if( pid == 0 ) {
+ if (pid == 0) {
close(sv[0]);
return do_child(sv[1], control, argv);
} else {
close(sv[1]);
- return do_parent(sv[0], pid, resfile);
+ return do_parent(sv[0], pid, resfile, info);
}
}
@@ -330,11 +338,11 @@ static int get_info(struct perfctr_info *info)
int fd;
fd = do_open_self(0);
- if( fd < 0 ) {
+ if (fd < 0) {
perror("perfex: open perfctrs");
return -1;
}
- if( perfctr_info(fd, info) < 0 ) {
+ if (perfctr_info(fd, info) < 0) {
perror("perfex: perfctr_info");
close(fd);
return -1;
@@ -349,12 +357,12 @@ static struct perfctr_cpus_info *get_cpus_info(void)
struct perfctr_cpus_info *cpus_info;
fd = do_open_self(0);
- if( fd < 0 ) {
+ if (fd < 0) {
perror("perfex: open perfctrs");
return NULL;
}
cpus_info = perfctr_cpus_info(fd);
- if( !cpus_info )
+ if (!cpus_info)
perror("perfex: perfctr_cpus_info");
close(fd);
return cpus_info;
@@ -367,7 +375,7 @@ static int do_info(const struct perfctr_info *info)
cpus_info = get_cpus_info();
printf("PerfCtr Info:\n");
perfctr_info_print(info);
- if( cpus_info ) {
+ if (cpus_info) {
perfctr_cpus_info_print(cpus_info);
free(cpus_info);
}
@@ -378,7 +386,7 @@ static void do_print_event(const struct perfctr_event *event, int long_format,
const char *event_prefix)
{
printf("%s%s", event_prefix, event->name);
- if( long_format )
+ if (long_format)
printf(":0x%02X:0x%X:0x%X",
event->evntsel,
event->counters_set,
@@ -391,13 +399,13 @@ static void do_print_event_set(const struct perfctr_event_set *event_set,
{
unsigned int i;
- if( event_set->include )
+ if (event_set->include)
do_print_event_set(event_set->include, long_format);
for(i = 0; i < event_set->nevents; ++i)
do_print_event(&event_set->events[i], long_format, event_set->event_prefix);
}
-static int do_list(const struct perfctr_info *info, int long_format)
+static void do_list(const struct perfctr_info *info, int long_format)
{
const struct perfctr_event_set *event_set;
unsigned int nrctrs;
@@ -412,23 +420,41 @@ static int do_list(const struct perfctr_info *info, int long_format)
(info->cpu_features & PERFCTR_FEATURE_PCINT) ? "" : " not");
event_set = perfctr_cpu_event_set(info->cpu_type);
- if( !event_set ) {
- fprintf(stderr, "perfex: perfctr_cpu_event_set(%u) failed\n",
- info->cpu_type);
- return 1;
+ if (!event_set || !event_set->nevents) {
+ printf("\nThe user-space library does not include an event list for this CPU type (this is not an error)\n");
+ return;
}
- if( !event_set->nevents ) /* the 'generic' CPU type */
- return 0;
printf("\nEvents Available:\n");
- if( long_format )
+ if (long_format)
printf("Name:EvntSel:CounterSet:DefaultUnitMask\n");
do_print_event_set(event_set, long_format);
- return 0;
+ return;
+}
+
+/* Hack while phasing out an old number parsing bug. */
+static unsigned int strtoul_base = 16;
+static unsigned int quiet;
+
+unsigned long my_strtoul(const char *nptr, char **endptr)
+{
+ unsigned long val1;
+
+ val1 = strtoul(nptr, endptr, strtoul_base);
+ if (strtoul_base == 16 && !quiet) {
+ unsigned long val2 = strtoul(nptr, NULL, 0);
+ if (val1 != val2)
+ fprintf(stderr, "perfex: warning: string '%s' is base-dependent, assuming base 16."
+ " Please prefix hexadecimal numbers with '0x'.\n",
+ nptr);
+ }
+ return val1;
}
static const struct option long_options[] = {
+ { "decimal", 0, NULL, 'd' },
{ "event", 1, NULL, 'e' },
{ "help", 0, NULL, 'h' },
+ { "hex", 0, NULL, 'x' },
{ "info", 0, NULL, 'i' },
{ "list", 0, NULL, 'l' },
{ "long-list", 0, NULL, 'L' },
@@ -450,6 +476,8 @@ static void do_usage(void)
fprintf(stderr, "\t-i | --info\t\t\tPrint PerfCtr driver information\n");
fprintf(stderr, "\t-l | --list\t\t\tList available events\n");
fprintf(stderr, "\t-L | --long-list\t\tList available events in long format\n");
+ fprintf(stderr, "\t-d | --decimal\t\t\tAllow decimal numbers in event specifications\n");
+ fprintf(stderr, "\t-x | --hex\t\t\tOnly accept hexadecimal numbers in event specifications\n");
do_arch_usage();
}
@@ -461,21 +489,22 @@ int main(int argc, char **argv)
FILE *resfile;
/* prime info, as we'll need it in most cases */
- if( get_info(&info) )
+ if (get_info(&info))
return 1;
+ /* this deliberately also clears CLOEXEC in control.flags */
memset(&control, 0, sizeof control);
- if( info.cpu_features & PERFCTR_FEATURE_RDTSC )
+ if (info.cpu_features & PERFCTR_FEATURE_RDTSC)
control.cpu_control.tsc_on = 1;
n = 0;
resfile = stderr;
for(;;) {
/* the '+' is there to prevent permutation of argv[] */
- int ch = getopt_long(argc, argv, "+e:hilLo:", long_options, NULL);
- switch( ch ) {
+ int ch = getopt_long(argc, argv, "+de:hilLo:x", long_options, NULL);
+ switch (ch) {
case -1: /* no more options */
- if( optind >= argc ) {
+ if (optind >= argc) {
fprintf(stderr, "perfex: command missing\n");
return 1;
}
@@ -487,20 +516,29 @@ int main(int argc, char **argv)
case 'i':
return do_info(&info);
case 'l':
- return do_list(&info, 0);
+ do_list(&info, 0);
+ return 0;
case 'L':
- return do_list(&info, 1);
+ do_list(&info, 1);
+ return 0;
case 'o':
- if( (resfile = fopen(optarg, "w")) == NULL ) {
+ if ((resfile = fopen(optarg, "w")) == NULL) {
fprintf(stderr, "perfex: %s: %s\n", optarg, strerror(errno));
return 1;
}
continue;
+ case 'd':
+ strtoul_base = 0;
+ continue;
+ case 'x':
+ strtoul_base = 16;
+ quiet = 1;
+ continue;
case 'e':
n = do_event_spec(n, optarg, &control.cpu_control);
continue;
default:
- if( do_arch_option(ch, optarg, &control.cpu_control) < 0 ) {
+ if (do_arch_option(ch, optarg, &control.cpu_control) < 0) {
do_usage();
return 1;
}
@@ -509,5 +547,5 @@ int main(int argc, char **argv)
break;
}
- return do_perfex(&control, argv, resfile);
+ return do_perfex(&control, argv, resfile, &info);
}
diff --git a/src/perfctr-2.6.x/examples/perfex/ppc.c b/src/perfctr-2.6.x/examples/perfex/ppc.c
index 07750cd921c298f56188fd8949314f1370c6f98d..17586c20b4650e328095ad2cd96d33e7a43f703e 100755
--- a/src/perfctr-2.6.x/examples/perfex/ppc.c
+++ b/src/perfctr-2.6.x/examples/perfex/ppc.c
@@ -1,7 +1,7 @@
-/* $Id$
+/* $Id: ppc.c,v 1.1.2.2 2010/06/08 20:48:56 mikpe Exp $
* PPC32-specific code.
*
- * Copyright (C) 2004 Mikael Pettersson
+ * Copyright (C) 2004-2010 Mikael Pettersson
*/
#include <stdio.h>
#include <stdlib.h>
@@ -9,6 +9,7 @@
#include "arch.h"
void do_print(FILE *resfile,
+ const struct perfctr_info *info,
const struct perfctr_cpu_control *cpu_control,
const struct perfctr_sum_ctrs *sum)
{
@@ -53,12 +54,12 @@ static int parse_event_spec(const char *arg, unsigned int *evntsel,
{
char *endp;
- *evntsel = strtoul(arg, &endp, 16);
+ *evntsel = my_strtoul(arg, &endp);
if( endp[0] != '@' ) {
*pmc = (unsigned int)-1;
} else {
arg = endp + 1;
- *pmc = strtoul(arg, &endp, 16);
+ *pmc = my_strtoul(arg, &endp);
}
return endp[0] != '\0';
}
@@ -89,7 +90,7 @@ static int parse_value(const char *arg, unsigned int *value)
{
char *endp;
- *value = strtoul(arg, &endp, 16);
+ *value = my_strtoul(arg, &endp);
return endp[0] != '\0';
}
diff --git a/src/perfctr-2.6.x/examples/perfex/ppc.h b/src/perfctr-2.6.x/examples/perfex/ppc.h
index 1b492bd951d92e83b89d35b3c6e0c83cf7cb30d4..064e688619607553d98a0c09ff9c99f23880bef4 100755
--- a/src/perfctr-2.6.x/examples/perfex/ppc.h
+++ b/src/perfctr-2.6.x/examples/perfex/ppc.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: ppc.h,v 1.1 2004/01/12 01:56:15 mikpe Exp $
* PPC32-specific declarations.
*
* Copyright (C) 2004 Mikael Pettersson
diff --git a/src/perfctr-2.6.x/examples/perfex/x86.c b/src/perfctr-2.6.x/examples/perfex/x86.c
index e3c87fa7c244cfc7d6de16fb434b61235a744b38..c5d1f38738332e7c3089d076fb60d470dd2f7681 100755
--- a/src/perfctr-2.6.x/examples/perfex/x86.c
+++ b/src/perfctr-2.6.x/examples/perfex/x86.c
@@ -1,66 +1,112 @@
-/* $Id$
+/* $Id: x86.c,v 1.1.2.6 2010/06/08 20:48:56 mikpe Exp $
* x86-specific code.
*
- * Copyright (C) 1999-2004 Mikael Pettersson
+ * Copyright (C) 1999-2010 Mikael Pettersson
*/
#include <stdio.h>
#include <stdlib.h>
#include "libperfctr.h"
#include "arch.h"
+static int info_is_p4(const struct perfctr_info *info)
+{
+ switch (info->cpu_type) {
+#if !defined(__x86_64__)
+ case PERFCTR_X86_INTEL_P4:
+ case PERFCTR_X86_INTEL_P4M2:
+#endif
+ case PERFCTR_X86_INTEL_P4M3:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
void do_print(FILE *resfile,
+ const struct perfctr_info *info,
const struct perfctr_cpu_control *cpu_control,
const struct perfctr_sum_ctrs *sum)
{
unsigned int nrctrs, i;
+ int is_p4;
- if( cpu_control->tsc_on )
- fprintf(resfile, "tsc\t\t\t%19lld\n", sum->tsc);
+ is_p4 = info_is_p4(info);
+ if (cpu_control->tsc_on)
+ fprintf(resfile, "tsc\t\t\t\t%19lld\n", sum->tsc);
nrctrs = cpu_control->nractrs;
for(i = 0; i < nrctrs; ++i) {
fprintf(resfile, "event 0x%08X",
cpu_control->evntsel[i]);
-#if !defined(__x86_64__)
- if( cpu_control->p4.escr[i] )
+ /* p4.escr[] overlaps evntsel_high[], but the output syntax
+ is the same regardless of whether is_p4 is true or not */
+ if (cpu_control->p4.escr[i])
fprintf(resfile, "/0x%08X",
cpu_control->p4.escr[i]);
-#endif
- fprintf(resfile, "\t%19lld\n", sum->pmc[i]);
+ if (cpu_control->pmc_map[i] >= 18)
+ fprintf(resfile, "@0x%08x\t", cpu_control->pmc_map[i]);
+ else
+ fprintf(resfile, "@%u\t\t", cpu_control->pmc_map[i]);
+ fprintf(resfile, "%19lld\n", sum->pmc[i]);
}
-#if !defined(__x86_64__)
- if( cpu_control->p4.pebs_enable )
- fprintf(resfile, "PEBS_ENABLE 0x%08X\n",
+ /* p4.pebs_{enable,matrix_vert} overlap nhlm.offcore_rsp[],
+ and we want to adjust the output based on is_p4 */
+ if (cpu_control->p4.pebs_enable)
+ fprintf(resfile, "%s 0x%08X\n",
+ is_p4 ? "PEBS_ENABLE" : "NHLM_OFFCORE_RSP_0",
cpu_control->p4.pebs_enable);
- if( cpu_control->p4.pebs_matrix_vert )
- fprintf(resfile, "PEBS_MATRIX_VERT 0x%08X\n",
+ if (cpu_control->p4.pebs_matrix_vert)
+ fprintf(resfile, "%s 0x%08X\n",
+ is_p4 ? "PEBS_MATRIX_VERT" : "NHLM_OFFCORE_RSP_1",
cpu_control->p4.pebs_matrix_vert);
-#endif
}
void do_arch_usage(void)
{
+ fprintf(stderr, "\t--nhlm_offcore_rsp_0=<value>\tValue for OFFCORE_RSP_0 (Nehalem only)\n");
+ fprintf(stderr, "\t--nhlm_offcore_rsp_1=<value>\tValue for OFFCORE_RSP_1 (Nehalem only)\n");
fprintf(stderr, "\t--p4pe=<value>\t\t\tValue for PEBS_ENABLE (P4 only)\n");
fprintf(stderr, "\t--p4_pebs_enable=<value>\tSame as --p4pe=<value>\n");
fprintf(stderr, "\t--p4pmv=<value>\t\t\tValue for PEBS_MATRIX_VERT (P4 only)\n");
fprintf(stderr, "\t--p4_pebs_matrix_vert=<value>\tSame as --p4pmv=<value>\n");
fprintf(stderr, "\n");
fprintf(stderr, "Syntax of event specifiers:\n");
- fprintf(stderr, "\tevent ::= evntsel[/escr][@pmc]\n");
+ fprintf(stderr, "\tevent ::= evntsel[/evntsel2][@pmc]\n");
fprintf(stderr, "\n");
- fprintf(stderr, "\tevntsel, escr, and pmc are decimal or hexadecimal numbers.\n");
+ fprintf(stderr, "\tevntsel, evntsel2, and pmc are decimal or hexadecimal numbers.\n");
+ fprintf(stderr, "\t/ and @ are literal characters. [...] denotes an optional field.\n");
fprintf(stderr, "\n");
fprintf(stderr, "\tevntsel is the primary processor-specific event selection code\n");
fprintf(stderr, "\tto use for this counter. This field is mandatory.\n");
- fprintf(stderr, "\tOn a P4, evntsel is written to the counter's CCCR register.\n");
fprintf(stderr, "\n");
- fprintf(stderr, "\tescr describes the additional event selection data written to\n");
- fprintf(stderr, "\tthe counter's associated ESCR register. (P4 only)\n");
+ fprintf(stderr, "\tevntsel2 provides auxiliary event selection code to use for this\n");
+ fprintf(stderr, "\tcounter. Currently only used for P4 and AMD Family 10h, on other\n");
+ fprintf(stderr, "\tprocessors this field should be omitted.\n");
fprintf(stderr, "\n");
fprintf(stderr, "\tpmc describes which CPU counter to use for this event.\n");
fprintf(stderr, "\tBy default the events use counters 0 and up in the order listed.\n");
+ fprintf(stderr, "\n");
+ fprintf(stderr, "\tOn Core2, the fixed-function performance counters are numbered\n");
+ fprintf(stderr, "\t0x40000000 to 0x40000002. To use them, explicit counter assignment\n");
+ fprintf(stderr, "\tvia the @pmc notation is mandatory.\n");
+ fprintf(stderr, "\tOn Core2, a fixed-function performance counter has an evntsel\n");
+ fprintf(stderr, "\tjust like a programmable performance counter has, but only the\n");
+ fprintf(stderr, "\tCPL (bits 16 and 17) and Enable (bit 22) fields are relevant.\n");
+ fprintf(stderr, "\t(The INT field (bit 20) is also honoured, but perfex cannot set\n");
+ fprintf(stderr, "\tup interrupt-mode counting, so it should not be specified.)\n");
+ fprintf(stderr, "\n");
+ fprintf(stderr, "\tAtom is similar to Core2, but appears to only support a single\n");
+ fprintf(stderr, "\t(the first) fixed-function counter.\n");
+ fprintf(stderr, "\n");
+ fprintf(stderr, "\tOn AMD Family 10h, evntsel is written to the low 32 bits of the\n");
+ fprintf(stderr, "\tcounter's EVNTSEL register, and evntsel2 is written to the high\n");
+ fprintf(stderr, "\t32 bits of that register. Only a few events require evntsel2.\n");
+ fprintf(stderr, "\n");
+ fprintf(stderr, "\tOn a P4, evntsel is written to the counter's CCCR register.\n");
+ fprintf(stderr, "\tOn a P4, evntsel2 is written to the counter's ESCR register.\n");
fprintf(stderr, "\tOn P4, each event is compatible with only a small subset of the\n");
- fprintf(stderr, "\tcounters, and explicit counter assignment is mandatory. Also,\n");
- fprintf(stderr, "\ton P4 bit 31 should be set in pmc to enable 'fast rdpmc'.\n");
+ fprintf(stderr, "\tcounters, and explicit counter assignment via @pmc is mandatory.\n");
+ fprintf(stderr, "\tOn P4, bit 31 should be set in pmc to enable 'fast rdpmc'.\n");
+ fprintf(stderr, "\n");
fprintf(stderr, "\tVIA C3 accepts a single event only, but it must use counter 1.\n");
}
@@ -69,18 +115,18 @@ static int parse_event_spec(const char *arg, unsigned int *evntsel,
{
char *endp;
- *evntsel = strtoul(arg, &endp, 16);
- if( endp[0] != '/' ) {
+ *evntsel = my_strtoul(arg, &endp);
+ if (endp[0] != '/') {
*escr = 0;
} else {
arg = endp + 1;
- *escr = strtoul(arg, &endp, 16);
+ *escr = my_strtoul(arg, &endp);
}
- if( endp[0] != '@' ) {
+ if (endp[0] != '@') {
*pmc = (unsigned int)-1;
} else {
arg = endp + 1;
- *pmc = strtoul(arg, &endp, 16);
+ *pmc = my_strtoul(arg, &endp);
}
return endp[0] != '\0';
}
@@ -91,58 +137,52 @@ unsigned int do_event_spec(unsigned int n,
{
unsigned int spec_evntsel, spec_escr, spec_pmc;
- if( parse_event_spec(arg, &spec_evntsel, &spec_escr, &spec_pmc) ) {
+ if (parse_event_spec(arg, &spec_evntsel, &spec_escr, &spec_pmc)) {
fprintf(stderr, "perfex: invalid event specifier: '%s'\n", arg);
exit(1);
}
- if( n >= ARRAY_SIZE(cpu_control->evntsel) ) {
+ if (n >= ARRAY_SIZE(cpu_control->evntsel)) {
fprintf(stderr, "perfex: too many event specifiers\n");
exit(1);
}
- if( spec_pmc == (unsigned int)-1 )
+ if (spec_pmc == (unsigned int)-1)
spec_pmc = n;
cpu_control->evntsel[n] = spec_evntsel;
-#if !defined(__x86_64__)
cpu_control->p4.escr[n] = spec_escr;
-#endif
cpu_control->pmc_map[n] = spec_pmc;
cpu_control->nractrs = ++n;
return n;
}
-#if !defined(__x86_64__)
static int parse_value(const char *arg, unsigned int *value)
{
char *endp;
- *value = strtoul(arg, &endp, 16);
+ *value = my_strtoul(arg, &endp);
return endp[0] != '\0';
}
-#endif
int do_arch_option(int ch,
const char *arg,
struct perfctr_cpu_control *cpu_control)
{
-#if !defined(__x86_64__)
unsigned int spec_value;
- switch( ch ) {
+ switch (ch) {
case 1:
- if( parse_value(arg, &spec_value) ) {
+ if (parse_value(arg, &spec_value)) {
fprintf(stderr, "perfex: invalid value: '%s'\n", arg);
exit(1);
}
cpu_control->p4.pebs_enable = spec_value;
return 0;
case 2:
- if( parse_value(arg, &spec_value) ) {
+ if (parse_value(arg, &spec_value)) {
fprintf(stderr, "perfex: invalid value: '%s'\n", arg);
exit(1);
}
cpu_control->p4.pebs_matrix_vert = spec_value;
return 0;
}
-#endif
return -1;
}
diff --git a/src/perfctr-2.6.x/examples/perfex/x86.h b/src/perfctr-2.6.x/examples/perfex/x86.h
index 9dda42308f07a2c481d5d1dd0d954e44d60cc4ff..6419edd7ca395b39797b090b199657e4acb7de36 100755
--- a/src/perfctr-2.6.x/examples/perfex/x86.h
+++ b/src/perfctr-2.6.x/examples/perfex/x86.h
@@ -1,9 +1,11 @@
-/* $Id$
+/* $Id: x86.h,v 1.1.2.1 2010/06/08 20:48:56 mikpe Exp $
* x86-specific declarations.
*
- * Copyright (C) 1999-2004 Mikael Pettersson
+ * Copyright (C) 1999-2010 Mikael Pettersson
*/
#define ARCH_LONG_OPTIONS \
+ { "nhlm_offcore_rsp_0", 1, NULL, 1 }, \
+ { "nhlm_offcore_rsp_1", 1, NULL, 2 }, \
{ "p4pe", 1, NULL, 1 }, { "p4_pebs_enable", 1, NULL, 1 }, \
{ "p4pmv", 1, NULL, 2 }, { "p4_pebs_matrix_vert", 1, NULL, 2 },
diff --git a/src/perfctr-2.6.x/examples/self/Makefile b/src/perfctr-2.6.x/examples/self/Makefile
index cd22ee78693190ed7363f7f510c465288bee5018..cf8b999d749227b48677f5fef9f7cca38e6b1f0f 100755
--- a/src/perfctr-2.6.x/examples/self/Makefile
+++ b/src/perfctr-2.6.x/examples/self/Makefile
@@ -1,4 +1,4 @@
-# $Id$
+# $Id: Makefile,v 1.6.2.1 2007/02/11 20:14:31 mikpe Exp $
SHELL=/bin/sh
ARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/)
@@ -10,6 +10,7 @@ TARGET=self
i386_OBJS=x86.o
x86_64_OBJS=x86.o
ppc_OBJS=ppc.o
+arm_OBJS=arm.o
ARCH_OBJS=$($(ARCH)_OBJS)
OBJS=self.o $(ARCH_OBJS)
diff --git a/src/perfctr-2.6.x/examples/self/arch.h b/src/perfctr-2.6.x/examples/self/arch.h
index a1e663a0e09e590bce01793a7b15dbcb62b26558..9bf92805b32c09b4bd13cf859413930fca9be3d2 100755
--- a/src/perfctr-2.6.x/examples/self/arch.h
+++ b/src/perfctr-2.6.x/examples/self/arch.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: arch.h,v 1.1 2004/01/11 22:07:12 mikpe Exp $
* Architecture-specific support code.
*
* Copyright (C) 2004 Mikael Pettersson
diff --git a/src/perfctr-2.6.x/examples/self/arm.c b/src/perfctr-2.6.x/examples/self/arm.c
index a9dffced8b3849e7ac8f1b26978d786f323f3ef7..2ea9def0f9be5589e74bfb5de023a3bfdfa6f371 100644
--- a/src/perfctr-2.6.x/examples/self/arm.c
+++ b/src/perfctr-2.6.x/examples/self/arm.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: arm.c,v 1.1.2.1 2007/02/11 20:14:31 mikpe Exp $
* ARM-specific code.
*
* Copyright (C) 2005-2007 Mikael Pettersson
diff --git a/src/perfctr-2.6.x/examples/self/ppc.c b/src/perfctr-2.6.x/examples/self/ppc.c
index 8e6b348be4c69c3953425f35ce4f15f1538eeddb..f3ab91b7b17c5e2be51acde642e0390033f5b179 100755
--- a/src/perfctr-2.6.x/examples/self/ppc.c
+++ b/src/perfctr-2.6.x/examples/self/ppc.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: ppc.c,v 1.1.2.1 2004/06/21 22:41:44 mikpe Exp $
* PPC32-specific code.
*
* Copyright (C) 2004 Mikael Pettersson
@@ -14,8 +14,10 @@ void do_setup(const struct perfctr_info *info,
{
memset(cpu_control, 0, sizeof *cpu_control);
cpu_control->tsc_on = 1;
- cpu_control->nractrs = 1;
- cpu_control->pmc_map[0] = 0;
- cpu_control->evntsel[0] = 0x02; /* INSTRUCTIONS_COMPLETED */
- cpu_control->ppc.mmcr0 = (1 << (31-1)); /* don't count in kernel mode */
+ if (info->cpu_type > PERFCTR_PPC_GENERIC) {
+ cpu_control->nractrs = 1;
+ cpu_control->pmc_map[0] = 0;
+ cpu_control->evntsel[0] = 0x02; /* INSTRUCTIONS_COMPLETED */
+ cpu_control->ppc.mmcr0 = (1 << (31-1)); /* don't count in kernel mode */
+ }
}
diff --git a/src/perfctr-2.6.x/examples/self/self.c b/src/perfctr-2.6.x/examples/self/self.c
index 678a5bcf3d2a65f7267f5694695c73f25d9c704a..35acd6cbeee4fb5919c3a1d2106f42c8f5a391a0 100755
--- a/src/perfctr-2.6.x/examples/self/self.c
+++ b/src/perfctr-2.6.x/examples/self/self.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: self.c,v 1.32 2004/01/11 22:07:12 mikpe Exp $
*
* This test program illustrates how a process may use the
* Linux x86 Performance-Monitoring Counters interface to
diff --git a/src/perfctr-2.6.x/examples/self/x86.c b/src/perfctr-2.6.x/examples/self/x86.c
index f8d9c87dffa24012a99d57c6061dec2f4417ea7a..106f2eb32b2941cdfb1b919c93aa7bf3baac63ae 100755
--- a/src/perfctr-2.6.x/examples/self/x86.c
+++ b/src/perfctr-2.6.x/examples/self/x86.c
@@ -1,7 +1,7 @@
-/* $Id$
+/* $Id: x86.c,v 1.2.2.9 2010/11/07 19:46:06 mikpe Exp $
* x86-specific code.
*
- * Copyright (C) 1999-2004 Mikael Pettersson
+ * Copyright (C) 1999-2010 Mikael Pettersson
*/
#include <stdio.h>
#include <stdlib.h>
@@ -21,7 +21,7 @@ void do_setup(const struct perfctr_info *info,
/* Attempt to set up control to count clocks via the TSC
and retired instructions via PMC0. */
- switch( info->cpu_type ) {
+ switch (info->cpu_type) {
case PERFCTR_X86_GENERIC:
nractrs = 0; /* no PMCs available */
break;
@@ -37,9 +37,15 @@ void do_setup(const struct perfctr_info *info,
case PERFCTR_X86_INTEL_PIII:
case PERFCTR_X86_INTEL_PENTM:
case PERFCTR_X86_AMD_K7:
+ case PERFCTR_X86_INTEL_CORE:
#endif
+ case PERFCTR_X86_INTEL_CORE2:
+ case PERFCTR_X86_INTEL_ATOM:
+ case PERFCTR_X86_INTEL_NHLM:
+ case PERFCTR_X86_INTEL_WSTMR:
case PERFCTR_X86_AMD_K8:
case PERFCTR_X86_AMD_K8C:
+ case PERFCTR_X86_AMD_FAM10H:
/* event 0xC0 (INST_RETIRED), count at CPL > 0, Enable */
evntsel0 = 0xC0 | (1 << 16) | (1 << 22);
break;
@@ -58,6 +64,8 @@ void do_setup(const struct perfctr_info *info,
break;
case PERFCTR_X86_INTEL_P4:
case PERFCTR_X86_INTEL_P4M2:
+#endif
+ case PERFCTR_X86_INTEL_P4M3:
/* PMC0: IQ_COUNTER0 with fast RDPMC */
pmc_map0 = 0x0C | (1 << 31);
/* IQ_CCCR0: required flags, ESCR 4 (CRU_ESCR0), Enable */
@@ -65,7 +73,6 @@ void do_setup(const struct perfctr_info *info,
/* CRU_ESCR0: event 2 (instr_retired), NBOGUSNTAG, CPL>0 */
cpu_control->p4.escr[0] = (2 << 25) | (1 << 9) | (1 << 2);
break;
-#endif
default:
fprintf(stderr, "cpu type %u (%s) not supported\n",
info->cpu_type, perfctr_info_cpu_name(info));
diff --git a/src/perfctr-2.6.x/examples/signal/Makefile b/src/perfctr-2.6.x/examples/signal/Makefile
index 3c9c1eee8f76a15777029ec6cca7eb531e4de04a..a42f3e9f4584b389a85d65bb264f7d057cf0d8ef 100755
--- a/src/perfctr-2.6.x/examples/signal/Makefile
+++ b/src/perfctr-2.6.x/examples/signal/Makefile
@@ -1,4 +1,4 @@
-# $Id$
+# $Id: Makefile,v 1.5 2004/01/12 01:56:15 mikpe Exp $
SHELL=/bin/sh
ARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/)
diff --git a/src/perfctr-2.6.x/examples/signal/arch.h b/src/perfctr-2.6.x/examples/signal/arch.h
index ca2fc67643b51d858c87c6f2a3062e5f6c052043..d5276580a16b88f2dcd4908d2497d76f73a16d7f 100755
--- a/src/perfctr-2.6.x/examples/signal/arch.h
+++ b/src/perfctr-2.6.x/examples/signal/arch.h
@@ -1,10 +1,10 @@
-/* $Id$
+/* $Id: arch.h,v 1.1.2.1 2004/11/28 22:40:31 mikpe Exp $
* Architecture-specific support code.
*
* Copyright (C) 2004 Mikael Pettersson
*/
-extern unsigned long mcontext_pc(const mcontext_t *mc);
+extern unsigned long ucontext_pc(const struct ucontext *uc);
extern void do_setup(const struct perfctr_info *info,
struct perfctr_cpu_control *cpu_control);
diff --git a/src/perfctr-2.6.x/examples/signal/ppc.c b/src/perfctr-2.6.x/examples/signal/ppc.c
index b99e8fce9a9565dbd13ad555b5aaada032bb5e30..7fe7ccc8ccd8f82a20eb5088d84e6744252c2e3d 100755
--- a/src/perfctr-2.6.x/examples/signal/ppc.c
+++ b/src/perfctr-2.6.x/examples/signal/ppc.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: ppc.c,v 1.1.2.2 2004/12/19 13:53:11 mikpe Exp $
* PPC32-specific code.
*
* Copyright (C) 2004 Mikael Pettersson
@@ -10,9 +10,14 @@
#include "libperfctr.h"
#include "arch.h"
-unsigned long mcontext_pc(const mcontext_t *mc)
+unsigned long ucontext_pc(const struct ucontext *uc)
{
- return mc->regs->nip;
+ /* glibc-2.3.3 (YDL4) changed the type of uc->uc_mcontext,
+ * breaking code which worked in glibc-2.3.1 (YDL3.0.1).
+ * This formulation works with both, and is cleaner than
+ * selecting glibc-2.3.3 specific code with "#ifdef NGREG".
+ */
+ return uc->uc_mcontext.regs->nip;
}
void do_setup(const struct perfctr_info *info,
diff --git a/src/perfctr-2.6.x/examples/signal/signal.c b/src/perfctr-2.6.x/examples/signal/signal.c
index c7f68aae84d8167909c9277317473ea9ce6b8379..8924b7e30716131917a1e7827f460277f7ceb680 100755
--- a/src/perfctr-2.6.x/examples/signal/signal.c
+++ b/src/perfctr-2.6.x/examples/signal/signal.c
@@ -1,13 +1,13 @@
-/* $Id$
+/* $Id: signal.c,v 1.18.2.3 2009/01/23 18:37:41 mikpe Exp $
*
* This test program illustrates how performance counter overflow
* can be caught and sent to the process as a user-specified signal.
*
* Limitations:
- * - Requires a 2.4 or newer kernel with local APIC support.
- * - Requires a CPU with a local APIC (P4, P6, K8, K7).
+ * - x86 requires a kernel with local APIC support.
+ * - x86 requires a CPU with a local APIC.
*
- * Copyright (C) 2001-2004 Mikael Pettersson
+ * Copyright (C) 2001-2004, 2009 Mikael Pettersson
*/
#define __USE_GNU /* enable symbolic names for gregset_t[] indices */
#include <sys/ucontext.h>
@@ -36,10 +36,18 @@ static void do_open(void)
printf("PCINT not supported -- expect failure\n");
}
+#if defined(__powerpc__)
+/* It seems that the PPC32 Linux kernels do not clear the high
+ bits of the si_code when copying the siginfo_t to user-space.
+ This works around that. */
+#define get_si_code(SI) ((SI) & 0xFFFF)
+#else
+#define get_si_code(SI) ((SI))
+#endif
+
static void on_sigio(int sig, siginfo_t *si, void *puc)
{
struct ucontext *uc;
- mcontext_t *mc;
unsigned long pc;
unsigned int pmc_mask;
@@ -47,7 +55,7 @@ static void on_sigio(int sig, siginfo_t *si, void *puc)
printf("%s: unexpected signal %d\n", __FUNCTION__, sig);
return;
}
- if( si->si_code != SI_PMC_OVF ) {
+ if( get_si_code(si->si_code) != get_si_code(SI_PMC_OVF) ) {
printf("%s: unexpected si_code #%x\n", __FUNCTION__, si->si_code);
return;
}
@@ -56,8 +64,7 @@ static void on_sigio(int sig, siginfo_t *si, void *puc)
return;
}
uc = puc;
- mc = &uc->uc_mcontext;
- pc = mcontext_pc(mc);
+ pc = ucontext_pc(uc);
if( !vperfctr_is_running(vperfctr) ) {
/*
* My theory is that this happens if a perfctr overflowed
diff --git a/src/perfctr-2.6.x/examples/signal/x86.c b/src/perfctr-2.6.x/examples/signal/x86.c
index 42cf9761cc5d1b259f95f3f24dd2277e06951fd0..b44c7f930fe74fdd914e2d738430a02da4b6af53 100755
--- a/src/perfctr-2.6.x/examples/signal/x86.c
+++ b/src/perfctr-2.6.x/examples/signal/x86.c
@@ -1,7 +1,7 @@
-/* $Id$
+/* $Id: x86.c,v 1.3.2.11 2010/11/07 19:46:06 mikpe Exp $
* x86-specific code.
*
- * Copyright (C) 2001-2004 Mikael Pettersson
+ * Copyright (C) 2001-2010 Mikael Pettersson
*/
#define __USE_GNU /* enable symbolic names for gregset_t[] indices */
#include <sys/ucontext.h>
@@ -23,11 +23,16 @@
#define REG_PC REG_EIP
#endif
-unsigned long mcontext_pc(const mcontext_t *mc)
+static inline unsigned long mcontext_pc(const mcontext_t *mc)
{
return mc->gregs[REG_PC];
}
+unsigned long ucontext_pc(const struct ucontext *uc)
+{
+ return mcontext_pc(&uc->uc_mcontext);
+}
+
void do_setup(const struct perfctr_info *info,
struct perfctr_cpu_control *cpu_control)
{
@@ -37,25 +42,50 @@ void do_setup(const struct perfctr_info *info,
memset(cpu_control, 0, sizeof *cpu_control);
- switch( info->cpu_type ) {
+ switch (info->cpu_type) {
#if !defined(__x86_64__)
case PERFCTR_X86_INTEL_P6:
case PERFCTR_X86_INTEL_PII:
case PERFCTR_X86_INTEL_PIII:
case PERFCTR_X86_INTEL_PENTM:
+ case PERFCTR_X86_INTEL_CORE:
/* FLOPS, USR, ENable, INT */
evntsel0 = 0xC1 | (1 << 16) | (1 << 22) | (1 << 20);
/* BR_TAKEN_RETIRED, USR, INT */
evntsel1 = 0xC9 | (1 << 16) | (1 << 20);
break;
+#endif
+ case PERFCTR_X86_INTEL_CORE2:
+ /* X87_OPS_RETIRED_ANY, USR, Enable, INT */
+ evntsel0 = 0xC1 | (0xFE << 8) | (1 << 16) | (1 << 22) | (1 << 20);
+ /* BR_INST_RETIRED_TAKEN, USR, Enable, INT */
+ evntsel1 = 0xC4 | (0x0C << 8) | (1 << 16) | (1 << 22) | (1 << 20);
+ break;
+ case PERFCTR_X86_INTEL_ATOM:
+ /* Atom's architectural events don't include FLOPS */
+ /* INST_RETIRED_ANY, USR, Enable, INT */
+ evntsel0 = 0xC0 | (1 << 16) | (1 << 22) | (1 << 20);
+ /* BR_INST_RETIRED_ANY, USR, Enable, INT */
+ evntsel1 = 0xC4 | (1 << 16) | (1 << 22) | (1 << 20);
+ break;
+ case PERFCTR_X86_INTEL_NHLM:
+ case PERFCTR_X86_INTEL_WSTMR:
+ /* FP_COMP_OPS_EXE.ANY, USR, Enable, INT */
+ evntsel0 = 0x10 | (0xFF << 8) | (1 << 16) | (1 << 22) | (1 << 20);
+ /* BR_INST_RETIRED.ALL, USR, Enable, INT */
+ evntsel1 = 0xC4 | (1 << 16) | (1 << 22) | (1 << 20);
+ break;
+#if !defined(__x86_64__)
case PERFCTR_X86_AMD_K7:
- /* K7 can't count FLOPS. Count RETIRED_OPS instead. */
- evntsel0 = 0xC1 | (1 << 16) | (1 << 22) | (1 << 20);
+ /* K7 can't count FLOPS. Count RETIRED_INSTRUCTIONS instead. */
+ evntsel0 = 0xC0 | (1 << 16) | (1 << 22) | (1 << 20);
/* RETIRED_TAKEN_BRANCHES, USR, INT */
evntsel1 = 0xC4 | (1 << 16) | (1 << 22) | (1 << 20);
break;
case PERFCTR_X86_INTEL_P4:
case PERFCTR_X86_INTEL_P4M2:
+#endif
+ case PERFCTR_X86_INTEL_P4M3:
nractrs = 1;
/* PMC(0) produces tagged x87_FP_uop:s (FLAME_CCCR0, FIRM_ESCR0) */
cpu_control->pmc_map[0] = 0x8 | (1 << 31);
@@ -70,9 +100,9 @@ void do_setup(const struct perfctr_info *info,
evntsel1 = (1 << 26) | (0x3 << 16) | (5 << 13) | (1 << 12);
cpu_control->p4.escr[2] = (6 << 25) | (((1 << 3)|(1 << 2)) << 9) | (1 << 2);
break;
-#endif
case PERFCTR_X86_AMD_K8:
case PERFCTR_X86_AMD_K8C:
+ case PERFCTR_X86_AMD_FAM10H:
/* RETIRED_FPU_INSTRS, Unit Mask "x87 instrs", any CPL, Enable, INT */
evntsel0 = 0xCB | (0x01 << 8) | (3 << 16) | (1 << 22) | (1 << 20);
/* RETIRED_TAKEN_BRANCHES, USR, Enable, INT */
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/Kconfig b/src/perfctr-2.6.x/linux/drivers/perfctr/Kconfig
index 65b5bdfc1b908be82f3ec551c984af16d87b623c..487485af49d30ff84b0248aa9b650a09935d76f6 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/Kconfig
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/Kconfig
@@ -1,4 +1,4 @@
-# $Id$
+# $Id: Kconfig,v 1.7.2.2 2004/11/13 16:32:05 mikpe Exp $
# Performance-monitoring counters driver configuration
#
@@ -76,4 +76,16 @@ config PERFCTR_GLOBAL
is currently using virtual-mode performance counters, and vice versa.
Say Y.
+
+config PERFCTR_INTERRUPT_SUPPORT
+ prompt "Performance counter overflow interrupt support" if PPC
+ bool
+ depends on PERFCTR
+ default y if X86_LOCAL_APIC
+
+config PERFCTR_CPUS_FORBIDDEN_MASK
+ bool
+ depends on PERFCTR
+ default y if X86 && SMP
+
endmenu
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/Makefile b/src/perfctr-2.6.x/linux/drivers/perfctr/Makefile
index e76b1e22f3260676d22e4849e72dcdc908e35748..bfc67e1ff909a0316c2e3fdd47cd2d2bb222be3a 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/Makefile
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/Makefile
@@ -1,29 +1,32 @@
-# $Id$
+# $Id: Makefile,v 1.20.2.4 2009/01/23 17:25:39 mikpe Exp $
# Makefile for the Performance-monitoring counters driver.
-ifeq ($(VERSION)$(PATCHLEVEL),24)
-include Makefile24
-else
+# We need -fno-unit-at-a-time with gcc-3.4 on x86 to avoid stack overflow.
+# Kernels >= 2.6.6 do that automatically but older ones do not, so we
+# unconditionally add that option here just in case.
+my_check_gcc = $(shell if $(CC) $(CFLAGS) $(1) -S -o /dev/null -xc /dev/null > /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi ;)
+EXTRA_CFLAGS_$(CONFIG_X86) := $(call my_check_gcc,-fno-unit-at-a-time,)
+EXTRA_CFLAGS_$(CONFIG_X86_64) :=
+EXTRA_CFLAGS_$(CONFIG_PPC32) :=
+EXTRA_CFLAGS := $(EXTRA_CFLAGS_y)
# construct various object file lists:
# kernel-objs-y kernel objects
# m-objs-m perfctr.o if driver is module, empty otherwise
# driver-objs-y objects for perfctr.o module, or empty
+# This also covers x86_64.
driver-objs-$(CONFIG_X86) := x86.o
tests-objs-$(CONFIG_X86) := x86_tests.o
kernel-objs-$(CONFIG_X86) := x86_setup.o
-# Braindamage alert! x86_64 defines _both_ CONFIG_X86_64 and CONFIG_X86.
-# These assignments need to override those above.
-driver-objs-$(CONFIG_X86_64) := x86_64.o
-tests-objs-$(CONFIG_X86_64) := x86_64_tests.o
-kernel-objs-$(CONFIG_X86_64) := x86_64_setup.o
-
driver-objs-$(CONFIG_PPC32) := ppc.o
tests-objs-$(CONFIG_PPC32) := ppc_tests.o
kernel-objs-$(CONFIG_PPC32) := ppc_setup.o
+driver-objs-$(CONFIG_ARM) := arm.o
+kernel-objs-$(CONFIG_ARM) := arm_setup.o
+
driver-objs-y += init.o marshal.o
driver-objs-$(CONFIG_PERFCTR_INIT_TESTS) += $(tests-objs-y)
driver-objs-$(CONFIG_PERFCTR_VIRTUAL) += virtual.o
@@ -38,5 +41,3 @@ obj-m += $(m-objs-m)
obj-$(CONFIG_KPERFCTR) += kperfctr.o
kperfctr-objs := $(kernel-objs-y)
-
-endif # ifeq 24
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/RELEASE-NOTES b/src/perfctr-2.6.x/linux/drivers/perfctr/RELEASE-NOTES
index 1f87230a72e215e30578c8125f91e65a0ea95cd3..cd64c1050d63509950fd8deff42d071b01894148 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/RELEASE-NOTES
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/RELEASE-NOTES
@@ -1,8 +1,492 @@
-$Id$
+$Id: RELEASE-NOTES,v 1.234.2.166 2010/11/07 19:48:14 mikpe Exp $
RELEASE NOTES
=============
+Version 2.6.42, 2010-11-07
+- x86.c: identify Intel Family 6 Models 37 and 44 as Westmere not Nehalem.
+- x86.c: do_init_tests() calls perfctr_x86_init_tests() which is __init,
+ therefore mark do_init_tests() also as __init.
+
+Version 2.6.41, 2010-06-08
+- x86: Add support for OFFCORE_RSP_{0,1} on Nehalem/Westmere.
+- x86: Recognise Intel family 6 models 30 and 37 as Nehalems.
+ Update comments mapping product lines to model numbers.
+- x86: Rename PERFCTR_X86_INTEL_COREI7 CPU/PMU type constant to
+ PERFCTR_X86_INTEL_NHLM. Update driver to print "Nehalem" rather
+ than "Core i7" when a CPU of this type is detected.
+
+Version 2.6.40, 2010-01-30
+- x86: add comment after #endif terminating big kernel >= 2.6.19 block
+- x86: handle cpumask API change in kernel 2.6.32
+- x86: recognize Intel Family 6 Model 2Eh processors (Nehalem Xeon 7500).
+- x86: recognize Intel Family 6 Model 2Ch processors (i7-980X, Gulftown).
+- x86: recognize AMD Family 11h processors, support them as 10h ones.
+
+Version 2.6.39, 2009-06-11
+- ppc and arm: updates to match perfctr_cpu_update_control() changes,
+ add missing #include <asm/cputype.h> to arm.c
+- global.c: coding style fixups
+- x86.c: update AMD multicore detection to match the documentation
+ and actually work on current processors, set up cpumask of all
+ core0 CPUs, detect RevE processors, update p6_like_check_control()
+ to allow per-thread sessions to use AMD NB events on post-RevE
+ processors but limit them to core0 CPUs
+- x86.c: replace is_global parameter to perfctr_cpu_update_control()
+ with a cpumask_t pointer, make P4 update this cpumask instead of
+ hard-coding the use of perfctr_cpus_forbidden_mask in virtual.c,
+ add cpumask to struct vperfctr, update virtual.c to use the cpumask
+ from perfctr_cpu_update_control() not perfctr_cpus_forbidden_mask
+ to derive the task's new cpumask, update set_cpus_allowed() callback
+ to validate new cpumask against the vperfctr's private one, update
+ global.c to pass a NULL cpumask_t pointer
+- virtual.c: rearrange sys_vperfctr_control() so that set_cpus_allowed()
+ comes after perfctr_cpu_update_control(), record updater's ->tgid so
+ races with concurrent updaters can be detected and handled
+- virtual.c: make vperfctrfs_dentry_operations 'const' in 2.6.30 and
+ later kernels.
+- x86.c: silence MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL redefinition warning.
+
+Version 2.6.38, 2009-01-23
+- Remove 2.4 kernel support from <linux/perfctr.h> (cpumask_t workaround).
+- Remove 2.4 kernel support from build system.
+- Remove 2.4 kernel support from .c files.
+- Remove 2.4 kernel support from .h files.
+- Kernel 2.6.29-rc1 changed remap_pfn_range() to WARN_ON when applied
+ to plain RAM. Update virtual.c to use vm_insert_page() instead.
+- Kernel 2.6.29-rc1 moved a task's fsuid/fsgid field to the ->cred
+ struct. Update virtual.c to use current_fsuid() and current_fsgid().
+ Update compat.h to supply these macros for older kernels.
+
+Version 2.6.37, 2008-11-30
+- x86: Preliminary Intel Core i7 support, limited to handling it
+ as a Core2-like processor with four PMCs. The AnyThread evntsel
+ flag and off-core/uncore monitoring are not yet supported.
+- x86: Recognise Intel Family 6 Model 29 (Xeon 7400) as Core 2.
+- x86: Make core2_clear_counters() also clear the FREEZE_PERFMON_ON_PMI
+ bit in DEBUGCTLMSR. vtune leaves this bit set, which breaks perfctr.
+- x86: Make perfctr_clear_counters() initialise MSR_CORE_PERF_GLOBAL_CTRL
+ during initialisation. This fixes compatibility issues with drivers
+ that may leave this register cleared == all counters disabled. vtune
+ is reported to do this. Add ->clear_counters() op to perfctr_pmu_msrs
+ to handle this cleanly. Convert Via C3 to use this mechanism instead
+ of being a special case.
+
+Version 2.6.36, 2008-10-19
+- x86: Limit the value written to a fixed-function counter's MSR
+ to 40 bits. Extraneous high bits cause GP faults on Model 23
+ Core2s, while earlier processors would just ignore them.
+- Kernel 2.6.27-rc1 dropped the retry parameter to on_each_cpu()
+ and smp_call_function(). Adjust accordingly. Add compatibility
+ wrappers for older kernels.
+- Kernel 2.6.27-rc1 removed find_task_by_pid(). Migrate to new
+ find_task_by_vpid(). Add compatibility wrapper for older kernels.
+- Starting with kernel 2.6.27-rc1 one should use alloc_intr_gate()
+ not set_intr_gate() on x86 when binding a specific vector, as this
+ also marks the vector as allocated. Adjust <asm-x86/perfctr.h>.
+
+Version 2.6.35, 2008-06-30
+- x86: Preliminary Intel Atom support:
+ * add Atom CPU type, it differs from all previous models
+ * Atom is poorly documented, so query cpuid leaf 0xA for
+ its architectural PMU capabilities; initial Atoms appear
+ to have APM V3, 2 40-bit general-purpose counters, 7
+ architectural events, and 1 40-bit fixed-function counter
+- x86: Replace the p6_is_core2 flag with separate variables
+ indicating (a) having per-evntsel enable bits, and (b) the
+ number of fixed-function counters available.
+- x86: intel_p6_init(): recognise Celeron model 16h and
+ treat it as a Core 2.
+- x86: Clean up intel_p6_init(): replace complex if conditions
+ with explicit switches on x86_model, explicitly enumerate
+ accepted model numbers.
+- x86: Correct p6_like_check_control() to reject regular
+ pmcs >= 2 on Core2 before mapping fixed-function counters
+ 0x40000000+N to pmcs 2+N for duplicate counter checking.
+ The failure to reject those invalid pmcs made it possible
+ for users to cause the driver to perform invalid wrmsr and
+ rdpmc accesses with kernel hangs as the result.
+
+Version 2.6.35-pre1, 2008-06-23
+- Add optional close-on-exec feature for per-process perfctrs:
+ * reassign _reserved1 as flags in vperfctr_control
+ * add VPERFCTR_CONTROL_CLOEXEC flag
+ * add perfctr_flush_thread() hook to exec() path
+ * map perfctr_flush_thread() to __vperfctr_flush() via
+ inline functions and virtual_stub.c
+ * in __virtual_flush(), if CLOEXEC is set then unlink the state
+ * bump API version to 5.2
+
+Version 2.6.34, 2008-05-29
+- Reorder kernel version and HAVE_EXPORT___put_task_struct
+ tests in compat.h to handle the SuSE 2.6.16.42-0.12 kernel
+ exporting __put_task_struct_cb().
+- Fix warning about DONT_HAVE_i_blksize being undefined in
+ the SuSE 2.6.16.42-0.12 kernel.
+
+Version 2.6.33, 2008-05-18
+- x86: Intel Family 6 Model 23 support missed that it needs
+ to trigger LVTPC reinit. Fix that.
+
+Version 2.6.32, 2008-04-20
+- x86: Recognize Intel Family 6 Model 23 as Core2.
+- x86: Update perfctr_sysclass definition for kernel 2.6.25.
+
+Version 2.6.31, 2008-01-26
+- x86: Correct Barcelona CPU type to read FAM10H not FAM10
+ w/o the trailing H. In struct perfctr_cpu_control, place
+ p4 struct in a union and alias p4.escr[] with envtsel_high[]:
+ this allows passing high 32 evntsel bits for Barcelona.
+ Update driver to also manage high 32 evntsel bits on Barcelona,
+ on other processors those bits are forced to zero.
+
+Version 2.6.30, 2007-10-28
+- x86: Kernel 2.6.24-rc1 changed the calling convention for
+ the cpu_data macro. Updated accordingly, and added compat
+ code providing the new behaviour in older kernels.
+- ppc32: Kernel 2.6.24-rc1 removed the get_property() compat
+ macro. Use of_get_property() with kernels >= 2.6.22.
+- The workaround for RHEL5 removing ptrace_check_attach()
+ only works when perfctr is built as a module. Fix it to
+ also work in the non-modular case.
+
+Version 2.6.29, 2007-10-07
+- Add new cpu_type for AMD Family 10h, to reduce confusion.
+- Very preliminary support for AMD Family 10h processors.
+ They will need a new cpu_type and support for 64-bit evntsels.
+ For now pretend they are K8C processors.
+- Silence compilation warnings on ppc32.
+- Intel has finally documented how to read the Core 2's
+ fixed-function performance counters in user-space:
+ rdpmc 0x4000000N for N=0,1,2. Support them from user-space
+ by pretending they have P6-like evntsels, and extract the
+ useful controls (CPL+INT) into the fixed-function counters
+ control register. Update the P6 driver methods to handle the
+ fact that a fixed-function counter has no private evntsel MSR.
+ Update x86_tests to measure the cost of reading these counters
+ and writing their shared control register.
+- More Intel CPU detection cleanup: separate detection needed
+ by the driver from that done to supply cpu_type to user-space.
+- Clean up Intel CPU detection by moving family 5, 6, and 15
+ detection code to separate procedures.
+- Use #undef to silence macro redefinition warnings on x86.
+- Kernel 2.6.22 removed the rdtsc() macro from i386. Unbreak
+ and clean up x86_tests.c by using our own rdtsc_low() macro.
+
+Version 2.6.28, 2007-07-18
+- x86: The kernel's perfctr/nmi management system changed again
+ in 2.6.22-rc5. Call {disable,enable}_lapic_nmi_watchdog() not
+ {stop,setup}_apic_nmi_watchdog() in kernels >= 2.6.22.
+- ppc.c: kernel 2.6.22-rc1 removed find_type_devices(),
+ use of_find_node_by_type() and of_node_put() instead
+- compat.h: fix warnings in CONFIG_UTRACE check
+
+Version 2.6.27, 2007-04-09
+- Bumped copyright years on recently updated files.
+- RHEL5 2.6.18-8.1.1.el5 added export of __put_task_struct.
+ Patched <linux/config.h> to signal this.
+- RHEL5 2.6.18-8.1.1.el5 removed i_blksize. Patched
+ <linux/config.h> to signal this. Check this in virtual.c.
+- RHEL5 2.6.18-8.1.1.el5 replaced ptrace with utrace, breaking
+ the remote control API which needs ptrace_check_attach().
+ For now, stub ptrace_check_attach() so that things build.
+- The {reserve,release}_{perfctr,evntsel}_nmi() API changed
+ in kernel 2.6.21-rc6, from being CPU-local to being global.
+ Updated x86.c to handle this change.
+
+Version 2.6.26, 2007-02-11
+- Updates to show my @it.uu.se email address in some messages,
+ as the old @csd.uu.se address now is /dev/null.
+- Added driver support for ARM/XScale processors. Overflow
+ interrupts are not yet supported, in part due to conflicts
+ with Intel's ixp400_eth driver. Plain event counting works.
+- Kernel 2.6.20-rc1 moved filp->f_dentry and filp->f_vfsmnt into
+ the filp->fpath substructure. Added compat macros to handle this.
+- Kernel 2.6.20-rc1 changed how pipefs handles its dentries.
+ Adapted those changes to vperfctrfs.
+
+Version 2.6.25, 2006-10-15
+- x86.c: Intel Core 2 is substantially different from Intel Core.
+ Add new cpu_type for Core 2, map family 6 model 15 to Core 2,
+ and require Core 2 to set Enable in all EVNTSELs.
+- x86.c: kernel 2.6.19-rc1 removed the {reserve,release}_lapic_nmi()
+ API, and added a {reserve,release}_{perfctr,evntsel}_nmi() API.
+ Reimplement {reserve,release}_lapic_nmi(). Add data to describe
+ the set of perfctr, evntsel, and other MSRs used by a CPU type.
+ Add procedures to reserve and release all of the MSRs. Replace
+ the CPU-specific clear_counters() procedures with a generic one
+ that uses the MSR description data object. Add EXPORT_SYMBOL of
+ {setup,stop}_apic_nmi_watchdog() to x86_setup.c for 2.6.19+ kernels.
+- virtual.c: kernel 2.6.18 dropped EXPORT_SYMBOL(tasklist_lock),
+ so starting with 2.6.18 we must use rcu_read_{lock,unlock}()
+ around find_task_by_pid().
+- virtual.c: kernel 2.6.19-rc1 dropped the inode->i_blksize field.
+- Only #include <linux/config.h> for kernels older than 2.6.19,
+ since 2.6.19-rc1 marks it deprecated. The test is ugly: perhaps
+ this should be handled in the Makefile instead.
+
+Version 2.6.24, 2006-09-17
+- x86_tests: fixed linkage error caused by p6_init_tests()
+ not being compiled in 64-bit builds.
+
+Version 2.6.23, 2006-08-20
+- Testing done by the PAPI folks indicate that Intel Core 2 has
+ a single master Enable bit in EVNTSEL0, just like previous P6s.
+ Restore Intel Core to the classic P6 rule: EVNTSEL0 must be
+ enabled, EVNTSEL1 must not be enabled.
+- Intel Core updates: each EVNTSEL has its own Enable bit like
+ AMD and P4, recognise Model 15 (Core2), Core2 is 64-bit so
+ make P6 testing code available in both 32- and 64-bit builds.
+- ppc32: correct PMC1SEL and PMC4SEL definitions.
+- virtual: new vperfctrfs_get_sb() for kernel 2.6.18-rc1 and
+ later: ->get_sb() and get_sb_pseudo() changed prototype.
+- x86: #include <asm/nmi.h> to get lapic NMI declarations in
+ kernel 2.6.18-rc1 and later. Do not do this if we're going
+ to stub them because !CONFIG_X86_LOCAL_APIC.
+
+Version 2.6.22, 2006-06-02
+- Preliminary support for Intel Core (family 6 model 14) processors.
+- x86: The code to extract max_cores_per_package from CPUID(4):EAX
+ needs cpuid() to put zero in ecx, but it only does that in fairly
+ new 32-bit kernels, not in 64-bit kernels or older 32-bit kernels.
+ This badly broke the SMT_ID detection on a dual-processor dual-core
+ hyper-threaded 64-bit Xeon machine. Fixed by using cpuid_count()
+ instead. Added compatibility definition of it for kernels < 2.6.12.
+- Fixed x86_tests.c compilation error in the i386 2.6.16 kernel
+ by moving sync_core() definition from x86_tests.c to x86_compat.h
+ and only defining it in i386 kernels older than 2.6.16.
+
+Version 2.6.21, 2006-04-03
+- Converted mutex-like semaphores to the new mutex type
+ introduced in kernel 2.6.16. Added simulation of the
+ new API in terms of semaphores to compat.h and compat24.h.
+- put_task_struct() uses __put_task_struct() again starting
+ with the 2.6.17-rc1 kernel. Updated compat.h, compat24.h,
+ and virtual_stub.c accordingly.
+- Corrected a botched cleanup of compat24.h in perfctr-2.6.20
+ which broke support for RHEL3 2.4.21 kernels.
+
+Version 2.6.20, 2006-03-12
+- Starting with 2.6.16-rc1, put_task_struct() uses an RCU callback
+ __put_task_struct_cb() instead of the old __put_task_struct().
+ 2.6.16-rc6 dropped the EXPORT_SYMBOL() of __put_task_struct_cb().
+ Updated compat.h, compat24.h, and virtual_stub.c accordingly.
+
+Version 2.6.19, 2006-01-22
+- Updated ppc32 driver for kernel 2.6.16-rc1: dynamically
+ claim the HW and register our interrupt handler via
+ {reserve,release}_pmc_hardware(); simulate these primitives
+ in older kernels; fully migrate patch kit from arch/ppc/
+ to arch/powerpc/.
+
+Version 2.6.18, 2006-01-03
+- 2.6.5-7.201-suse added EXPORT_SYMBOL_GPL(__put_task_struct).
+ Added feature #define to the kernel patch, and modified compat.h
+ to disable our export of __put_task_struct in this case.
+- Merged the structure descriptor declarations in marshal.c
+ to avoid duplicating the parts that are identical across
+ all supported platforms.
+
+Version 2.6.17, 2005-10-02
+- The dual-core P4s changed the layout rules for the initial
+ APIC ID, which broke the x86 driver on DC P4s. Updated the
+ HT thread ID detection code to match current IA32 SDM Vol3.
+- Kernel 2.4.21-37.EL added EXPORT_SYMBOL_GPL(__put_task_struct).
+ Added new feature #define to the kernel-specific patch for this
+ case. compat24.h now disables our export of __put_task_struct
+ when that feature #define is set.
+- Kernel 2.6.14-rc1 changed the state parameter to ->suspend()
+ methods to be of type 'pm_message_t'. Adjusted x86.c for this,
+ to eliminate a compile-time type mismatch warning.
+
+Version 2.6.16, 2005-09-04
+- cpu_khz changed type in kernel 2.6.13. Adjusted x86_setup.c
+ accordingly, to avoid a compile-time error.
+- The ppc32 driver will now compile in kernels that lack Open
+ Firmware support, which is needed for some embedded systems.
+
+Version 2.6.15, 2005-05-06
+- Added code to detect multicore K8s and prevent threads in the
+ thread-centric API from using northbridge events. This avoids
+ resource conflicts, and an erratum in Revision E chips.
+- #undef MMCR0_PMXE in ppc_compat.h, to avoid macro redefinition
+ complaints in 2.6 kernels.
+
+Version 2.6.14, 2005-04-09
+- x86: Reverted the workaround in perfctr-2.6.13 for the problem
+ that gcc-4.0 snapshots appeared to ignore 'noinline' on static
+ functions, as recent gcc-4.0 prereleases seem to work correctly.
+
+Version 2.6.13, 2005-02-13
+- global.c: Allow user-space to disable the in-kernel sampling
+ timer by setting interval_usec == 0 in the START command.
+ In this case sampling is done by the READ command.
+- Modified x86 call backpatching code to avoid breaking with
+ gcc-4.0 snapshots:
+ * gcc-4.0 may clone control flows, resulting in more sites
+ with backpatchable calls. finalise_backpatching() now sets
+ things up to exercise all affected control flow paths.
+ * gcc-4.0 appears to ignore 'noinline' on static functions
+ that are only called from one place, at least on x86-64.
+ This broke perfctr_cpu_{write_control,isuspend,iresume}().
+ Things work again if they are made non-static.
+- Only define our own version of get_sb_pseudo() in kernels older
+ than 2.6.11, since 2.6.11-rc1 added EXPORT_SYMBOL(get_sb_pseudo).
+- In 2.6.11-rc2 and newer kernels, bind ioctls to ->unlocked_ioctl
+ and ->compat_ioctl, and don't use register_ioctl32_conversion().
+- Remove unused inode parameter to gperfctr_ioctl().
+- Define static spinlocks with DEFINE_SPINLOCK(), following new
+ coding style in 2.6.11-rc1. Add compat macros for older kernels.
+
+Version 2.6.12, 2004-12-19
+- PPC32 driver updated to be more robust in its detection of
+ timebase and core clock frequencies. Some information sources
+ can give wrong values for those frequencies, so the driver
+ now tries other more reliable methods first.
+
+Version 2.6.11, 2004-11-14
+- Compat stuff updated for tsk->sighand->siglock,
+ recalc_sigpending(), and preempt_enable_no_resched().
+- Silence compiler warning from compat.h:remap_pfn_range().
+- PPC32 overflow interrupt support backported from perfctr-2.7.
+- Backported inheritance handling calls from perfctr-2.7
+ to kernel patch kit. They are currently stubs, but can be
+ implemented later without having to update the patch kit.
+- Overflow interrupts fixes backported from perfctr-2.7.7:
+ * x86/x86-64: move perfctr_suspend_thread() call from
+ __switch_to() to the start of switch_to()
+ * x86/x86-64: mask interrupts at suspend and record if
+ any overflows are pending; unmask interrupts at resume
+ * virtual: handle pending overflows in resume path
+ * ppc32: provide dummy pending overflow checking function
+
+Version 2.6.10.3, 2004-10-24
+- virtual.c, linux/perfctr.h: reformatted "if( x )" to "if (x)"
+ and similarly for while and switch statements.
+- PPC32: Add support for MPC7447A. Add support for MPC7448,
+ except for decoding its PLL_CFG.
+- Move x86 cpu_type definitions from <linux/perfctr.h>
+ to <asm-i386/perfctr.h>.
+- Make PERFCTR_INTERRUPT_SUPPORT a Kconfig-derived option.
+ Ditto PERFCTR_CPUS_FORBIDDEN_MASK_NEEDED.
+ Also implement this in Config.in for 2.4 kernels.
+- Kernel 2.6.10-rc1 removed the export of put_filp().
+ Reordered the allocations in vperfctr_get_filp() to
+ avoid the need to use put_filp().
+- remap_page_range() was replaced with remap_pfn_range() in
+ kernel 2.6.10-rc1. Updated virtual.c accordingly, and added
+ remap_pfn_range() emulations for older kernels.
+
+Version 2.6.10.2, 2004-10-19
+- virtual.c: replace nrctrs_lock with a mutex. Avoids illegal
+ may-sleep-while-holding-lock, caused by mutex operations in
+ perfctr_cpu_{reserve,release}().
+ Backport from perfctr-2.7.6.
+- PPC32: Correct MMCR0 handling for FCECE/TRIGGER. Read
+ MMCR0 at suspend and then freeze the counters. Move
+ this code from read_counters() to suspend(). At resume,
+ reload MMCR0 to unfreeze the counters. Clean up the
+ cstatus checks controlling this behaviour.
+ Backport from perfctr-2.7.6.
+
+Version 2.6.10, 2004-09-14
+- Fixed p4_clear_counters() to not access IQ_ESCR{0,1}
+ on P4 models >= 3.
+
+Version 2.6.10-pre1, 2004-08-03
+- Changed x86-64 to use the x86 include file and driver.
+ Intel's 64-bit P4 should now work in the x86-64 kernel.
+- Replaced PERFCTR_INTERRUPT_SUPPORT and NMI_LOCAL_APIC
+ #if:s in x86 code by #ifdef:s on CONFIG_X86_LOCAL_APIC.
+- Use macros to clean up x86 per-cpu cache accesses.
+- Recognize model 13 Pentium-Ms.
+- Changed isuspend_cpu on x86 to be like x86-64's: it
+ now stores a CPU number instead of a cache pointer.
+- x86: make perfctr_cpu_name more approximate.
+- The x86 driver records a simplified CPU type for x86_tests,
+ but this only occurs if PERFCTR_INIT_TESTS is configured.
+ perfctr_info.cpu_type is now unused.
+- Changed P4 driver to set up and check an explicit flag
+ for EXTENDED_CASCADE availability. perfctr_info.cpu_type
+ is now unused except for perfctr_x86_init_tests().
+- x86: Reformatted "if( x )" to "if (x)" and similarly for while
+ and switch statements. Deleted #if 0 blocks.
+
+Version 2.6.9, 2004-07-27
+- Fix ppc_check_control() to allow 7400/7410 processors to
+ specify MMCR2[THRESHMULT].
+- PPC32 cleanups: make get_cpu_cache() return pointer not lvalue,
+ eliminate duplicated initialisation/cleanup code.
+- Makefile: enforce -fno-unit-at-a-time with gcc-3.4 on x86,
+ to prevent stack overflow in 2.6 kernels < 2.6.6.
+- Do sync_core() before rdtsc() in x86_tests, to avoid bogus
+ benchmarking data on K8. Add sync_core() implementation for
+ the 32-bit kernel. Add sync_core() benchmark.
+- Added __perfctr_mk_cstatus() to allow x86.c:finalise_backpatching()
+ to create a cstatus with i-mode counters marked as present, but
+ with zero actual counters. This prevents perfctr_cpu_isuspend()
+ from clearing the control register for counter #0 at init-time,
+ when the hardware doesn't belong to this driver. On AMD and P6
+ this would accidentally disable the NMI watchdog.
+- x86: Marked initial targets of backpatchable calls
+ 'noinline' to prevent gcc from inlining them, which
+ completely breaks the backpatching mechanism.
+- x86_tests: fix CONFIG_X86_LOCAL_APIC=n linkage error.
+- 2.6.8-rc1 no longer makes cpu_online_map a #define on UP,
+ breaking modules. Reintroduce the macro.
+- 2.6.8-rc1 changed cpus_complement() calling convention.
+ Replace cpus_complement();cpus_and() with cpus_andnot(),
+ and provide cpus_andnot() compat macro.
+- PPC32: support generic CPUs using only the TB.
+- PPC32: query OF for CPU/TB frequencies, drop /proc/cpuinfo
+ parsing code.
+- PPC32: avoid CPU re-detection in tests code.
+- PPC32: clean up and sync with current perfctr-2.7 code.
+
+Version 2.6.8, 2004-05-29
+- Added recognition of PowerPC 750GX.
+- Changes for the {reserve,release}_lapic_nmi() API added in
+ kernel 2.6.6 backported from perfctr-2.7.1:
+ * Starting with kernel 2.6.6 we no longer need access to
+ nmi_perfctr_msr, so removed EXPORT_SYMBOL() and <asm/apic.h>
+ patches related to this variable (except for older kernels).
+ * Updated x86.c to use the new API. Added simulation (without
+ the non-conflict guarantees) for older kernels.
+ * Moved hardware reservation to x86.c's "reserve" procedure.
+ The init code now only does read-only hardware detection.
+ * Added a mutex to the reserve/release procedures, eliminating
+ * a long-standing race possibility.
+ * Changed x86.c to reserve and release the hardware around its
+ call to perfctr_x86_init_tests().
+ * Similarly updated x86_64.c for the new API.
+
+Version 2.6.7, 2004-05-04
+- Replaced x86_64_tests.{c,h} with x86_tests.{c,h}.
+- sys_device_{,un}register() was renamed as sysdev_{,un}register()
+ in 2.6.4-rc2. Updated x86.c and x86_64.c accordingly, and
+ added a compatibility definition in compat.h.
+- Removed unnecessary '#include "compat.h"' from x86_tests.c.
+- Replaced x86_64_setup.c with x86_setup.c.
+- Replaced x86_64_compat.h with x86_compat.h.
+- Moved perfctr_interrupt entry point from x86_setup.c to patch kit,
+ for kernels older than 2.4.21. Cleanup to facilitate future merge
+ of x86_setup.c and x86_64_setup.c.
+
+Version 2.6.6, 2004-02-21
+- Fixed a bug in x86-64's perfctr interrupt entry code in 2.4 kernels,
+ causing it to pass the wrong value for "struct pt_regs*". This
+ was harmless since the retrieved "rip" was unused, but still wrong.
+ Renamed do_perfctr_interrupt to smp_perfctr_interrupt to allow
+ using the 2.4 kernel's standard BUILD_SMP_INTERRUPT macro.
+- Unmask LVTPC after interrupt on Pentium-M. An oprofile user
+ reports that P-M auto-masks LVTPC just like P4. Preliminary
+ measurements indicate a 40 to 60 cycle cost for the apic write
+ on P4s and P6s, so the unmask is not done unconditionally.
+- Measure LVTPC write overhead in x86{,_64}_tests.c.
+- Add Pentium 4 Model 3 detection.
+- The 2.4.21-193 SuSE kernel does EXPORT_SYMBOL(mmu_cr4_features).
+ Add compat24.h workaround for this.
+
Version 2.6.5, 2004-01-26
- Added perfctr_info.cpu_type constants to <asm-ppc/perfctr.h>.
- Init filp->f_mapping in virtual.c for 2.6.2-rc1+ kernels.
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/arm.c b/src/perfctr-2.6.x/linux/drivers/perfctr/arm.c
index 7c0f50e1477cebc7713709f6fe20a4dd2d836dac..ff7b7dd0ac056f15ae0bef7ef52273587bce1f4d 100644
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/arm.c
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/arm.c
@@ -1,7 +1,7 @@
-/* $Id$
+/* $Id: arm.c,v 1.1.2.3 2009/06/11 12:33:51 mikpe Exp $
* ARM/XScale performance-monitoring counters driver.
*
- * Copyright (C) 2005-2007 Mikael Pettersson
+ * Copyright (C) 2005-2009 Mikael Pettersson
*/
#include <linux/version.h>
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
@@ -12,6 +12,7 @@
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/perfctr.h>
+#include <asm/cputype.h>
#include "compat.h"
@@ -659,7 +660,7 @@ static int check_control(struct perfctr_cpu_state *state)
return xscale_check_control(state);
}
-int perfctr_cpu_update_control(struct perfctr_cpu_state *state, int is_global)
+int perfctr_cpu_update_control(struct perfctr_cpu_state *state, cpumask_t *cpumask)
{
int err;
@@ -796,7 +797,7 @@ static void perfctr_cpu_clear_one(void *ignore)
static void perfctr_cpu_reset(void)
{
- on_each_cpu(perfctr_cpu_clear_one, NULL, 1, 1);
+ on_each_cpu(perfctr_cpu_clear_one, NULL, 1);
perfctr_cpu_set_ihandler(NULL);
}
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/arm_setup.c b/src/perfctr-2.6.x/linux/drivers/perfctr/arm_setup.c
index 2d3bc395a54cf31f42c5e1e8780323457873423b..f2a532fc4910344a119533163744c61793223699 100644
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/arm_setup.c
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/arm_setup.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: arm_setup.c,v 1.1.2.1 2007/02/11 20:13:45 mikpe Exp $
* Performance-monitoring counters driver.
* ARM-specific kernel-resident code.
*
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/compat.h b/src/perfctr-2.6.x/linux/drivers/perfctr/compat.h
index d2d2c412cc76ad55a19b498194f4c93598598278..5841039ea3d4990f644ca0ef60d37c4c17fabfe2 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/compat.h
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/compat.h
@@ -1,18 +1,111 @@
-/* $Id$
+/* $Id: compat.h,v 1.42.2.17 2009/01/23 17:01:02 mikpe Exp $
* Performance-monitoring counters driver.
* Compatibility definitions for 2.6 kernels.
*
- * Copyright (C) 1999-2003 Mikael Pettersson
+ * Copyright (C) 1999-2009 Mikael Pettersson
*/
#include <linux/version.h>
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
-#include "compat24.h"
-#else
-
#include "cpumask.h"
#define EXPORT_SYMBOL_mmu_cr4_features EXPORT_SYMBOL(mmu_cr4_features)
+
+/* Starting with 2.6.16-rc1, put_task_struct() uses an RCU callback
+ __put_task_struct_cb() instead of the old __put_task_struct().
+ 2.6.16-rc6 dropped the EXPORT_SYMBOL() of __put_task_struct_cb().
+ 2.6.17-rc1 reverted to using __put_task_struct() again. */
+#if defined(HAVE_EXPORT___put_task_struct)
+/* 2.6.5-7.201-suse added EXPORT_SYMBOL_GPL(__put_task_struct) */
+/* 2.6.16.46-0.12-suse added EXPORT_SYMBOL(__put_task_struct_cb) */
+#define EXPORT_SYMBOL___put_task_struct /*empty*/
+#elif LINUX_VERSION_CODE == KERNEL_VERSION(2,6,16)
+#define EXPORT_SYMBOL___put_task_struct EXPORT_SYMBOL(__put_task_struct_cb)
+#else
#define EXPORT_SYMBOL___put_task_struct EXPORT_SYMBOL(__put_task_struct)
+#endif
+
+#define task_siglock(tsk) ((tsk)->sighand->siglock)
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) /* names changed in 2.6.4-rc2 */
+#define sysdev_register(dev) sys_device_register((dev))
+#define sysdev_unregister(dev) sys_device_unregister((dev))
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) /* remap_page_range() obsoleted in 2.6.10-rc1 */
+#include <linux/mm.h>
+static inline int
+remap_pfn_range(struct vm_area_struct *vma, unsigned long uvaddr,
+ unsigned long pfn, unsigned long size, pgprot_t prot)
+{
+ return remap_page_range(vma, uvaddr, pfn << PAGE_SHIFT, size, prot);
+}
+#endif
+
+#if !defined(DEFINE_SPINLOCK) /* added in 2.6.11-rc1 */
+#define DEFINE_SPINLOCK(x) spinlock_t x = SPIN_LOCK_UNLOCKED
+#endif
+
+/* 2.6.16 introduced a new mutex type, replacing mutex-like semaphores. */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16)
+#define DEFINE_MUTEX(mutex) DECLARE_MUTEX(mutex)
+#define mutex_lock(mutexp) down(mutexp)
+#define mutex_unlock(mutexp) up(mutexp)
+#endif
+
+/* 2.6.18-8.1.1.el5 replaced ptrace with utrace */
+#if defined(CONFIG_UTRACE)
+/* alas, I don't yet know how to convert this to utrace */
+static inline int ptrace_check_attach(struct task_struct *task, int kill) { return -ESRCH; }
+#endif
+
+/* 2.6.20-rc1 moved filp->f_dentry and filp->f_vfsmnt into filp->fpath */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
+#define filp_dentry(filp) ((filp)->f_path.dentry)
+#define filp_vfsmnt(filp) ((filp)->f_path.mnt)
+#else
+#define filp_dentry(filp) ((filp)->f_dentry)
+#define filp_vfsmnt(filp) ((filp)->f_vfsmnt)
+#endif
+
+/* 2.6.24 introduced find_task_by_vpid() and task_pid_vnr().
+ 2.6.26 deprecated find_task_by_pid() and 2.6.27-rc1 removed it.
+ We'll use 2.6.26 as the switch-over point. */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)
+static inline struct task_struct *perfctr_find_task_by_vpid(pid_t nr)
+{
+ return find_task_by_pid(nr);
+}
+#undef find_task_by_vpid
+#define find_task_by_vpid(nr) perfctr_find_task_by_vpid((nr))
+static inline pid_t perfctr_task_pid_vnr(const struct task_struct *tsk)
+{
+ return tsk->pid;
+}
+#undef task_pid_vnr
+#define task_pid_vnr(tsk) perfctr_task_pid_vnr((tsk))
+#endif
+
+/* 2.6.27-rc1 dropped the retry parameter from smp_call_function()
+ and on_each_cpu() -- we always called it with retry == 1 */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27)
+static inline int perfctr_smp_call_function(
+ void (*func)(void *info), void *info, int wait)
+{
+ return smp_call_function(func, info, 1, wait);
+}
+#undef smp_call_function
+#define smp_call_function(f,i,w) perfctr_smp_call_function((f),(i),(w))
+static inline int perfctr_on_each_cpu(
+ void (*func)(void *info), void *info, int wait)
+{
+ return on_each_cpu(func, info, 1, wait);
+}
+#undef on_each_cpu
+#define on_each_cpu(f,i,w) perfctr_on_each_cpu((f),(i),(w))
+#endif
+/* 2.6.29-rc1 changed how ->fsuid and ->fsgid are accessed */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29)) && !defined(current_fsuid)
+#define current_fsuid() (current->fsuid)
+#define current_fsgid() (current->fsgid)
#endif
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/cpumask.h b/src/perfctr-2.6.x/linux/drivers/perfctr/cpumask.h
index b23c55a547fc89caaa76b063bb6eb75060aab172..8e58fc4ff045ef5359e11f695ce46d0643da7e37 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/cpumask.h
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/cpumask.h
@@ -1,44 +1,13 @@
-/* $Id$
+/* $Id: cpumask.h,v 1.6.2.3 2009/01/23 17:01:02 mikpe Exp $
* Performance-monitoring counters driver.
* Partial simulation of cpumask_t on non-cpumask_t kernels.
* Extension to allow inspecting a cpumask_t as array of ulong.
* Appropriate definition of perfctr_cpus_forbidden_mask.
*
- * Copyright (C) 2003-2004 Mikael Pettersson
+ * Copyright (C) 2003-2004, 2009 Mikael Pettersson
*/
-/* 2.6.0-test4 changed set-of-CPUs values from ulong to cpumask_t */
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
-
-#if !defined(PERFCTR_HAVE_CPUMASK_T) && !defined(HAVE_CPUMASK_T)
-typedef unsigned long cpumask_t;
-#endif
-
-/* RH/FC1 kernel 2.4.22-1.2115.nptl added cpumask_t, but with
- an incomplete API and a broken cpus_and() [misspelled parameter
- in its body]. Sigh.
- Assume cpumask_t is unsigned long and use our own code. */
-#undef cpu_set
-#define cpu_set(cpu, map) atomic_set_mask((1UL << (cpu)), &(map))
-#undef cpu_isset
-#define cpu_isset(cpu, map) ((map) & (1UL << (cpu)))
-#undef cpus_and
-#define cpus_and(dst,src1,src2) do { (dst) = (src1) & (src2); } while(0)
-#undef cpus_clear
-#define cpus_clear(map) do { (map) = 0UL; } while(0)
-#undef cpus_complement
-#define cpus_complement(map) do { (map) = ~(map); } while(0)
-#undef cpus_empty
-#define cpus_empty(map) ((map) == 0UL)
-#undef cpus_equal
-#define cpus_equal(map1, map2) ((map1) == (map2))
-#undef cpus_addr
-#define cpus_addr(map) (&(map))
-
-#undef CPU_MASK_NONE
-#define CPU_MASK_NONE 0UL
-
-#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,1)
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,1)
/* 2.6.1-rc1 introduced cpus_addr() */
#ifdef CPU_ARRAY_SIZE
@@ -49,15 +18,31 @@ typedef unsigned long cpumask_t;
#endif
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) && !defined(cpus_andnot)
+#define cpus_andnot(dst, src1, src2) \
+do { \
+ cpumask_t _tmp2; \
+ _tmp2 = (src2); \
+ cpus_complement(_tmp2); \
+ cpus_and((dst), (src1), _tmp2); \
+} while(0)
+#endif
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,8) && !defined(CONFIG_SMP)
+#undef cpu_online_map
+#define cpu_online_map cpumask_of_cpu(0)
+#endif
+
#ifdef CPU_ARRAY_SIZE
#define PERFCTR_CPUMASK_NRLONGS CPU_ARRAY_SIZE
#else
#define PERFCTR_CPUMASK_NRLONGS 1
#endif
-/* `perfctr_cpus_forbidden_mask' used to be defined in <asm/perfctr.h>,
- but cpumask_t compatibility issues forced it to be moved here. */
-#if PERFCTR_CPUS_FORBIDDEN_MASK_NEEDED
+/* CPUs in `perfctr_cpus_forbidden_mask' must not use the
+ performance-monitoring counters. TSC use is unrestricted.
+ This is needed to prevent resource conflicts on hyper-threaded P4s. */
+#ifdef CONFIG_PERFCTR_CPUS_FORBIDDEN_MASK
extern cpumask_t perfctr_cpus_forbidden_mask;
#define perfctr_cpu_is_forbidden(cpu) cpu_isset((cpu), perfctr_cpus_forbidden_mask)
#else
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/global.c b/src/perfctr-2.6.x/linux/drivers/perfctr/global.c
index 635c8603932676647ae75faa1af26bf685dd2660..3a4bf1f6d4711bff4dbb5257be32ff2d69cf9ad4 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/global.c
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/global.c
@@ -1,12 +1,15 @@
-/* $Id$
+/* $Id: global.c,v 1.38.2.7 2009/06/11 08:11:31 mikpe Exp $
* Global-mode performance-monitoring counters via /dev/perfctr.
*
- * Copyright (C) 2000-2003 Mikael Pettersson
+ * Copyright (C) 2000-2006, 2008, 2009 Mikael Pettersson
*
* XXX: Doesn't do any authentication yet. Should we limit control
* to root, or base it on having write access to /dev/perfctr?
*/
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
#include <linux/config.h>
+#endif
#define __NO_VERSION__
#include <linux/module.h>
#include <linux/sched.h>
@@ -23,7 +26,7 @@
static const char this_service[] = __FILE__;
static int hardware_is_ours = 0;
static struct timer_list sampling_timer;
-static DECLARE_MUTEX(control_mutex);
+static DEFINE_MUTEX(control_mutex);
static unsigned int nr_active_cpus = 0;
struct gperfctr {
@@ -37,10 +40,10 @@ static int reserve_hardware(void)
{
const char *other;
- if( hardware_is_ours )
+ if (hardware_is_ours)
return 0;
other = perfctr_cpu_reserve(this_service);
- if( other ) {
+ if (other) {
printk(KERN_ERR __FILE__ ":%s: failed because hardware is taken by '%s'\n",
__FUNCTION__, other);
return -EBUSY;
@@ -55,9 +58,10 @@ static void release_hardware(void)
int i;
nr_active_cpus = 0;
- if( hardware_is_ours ) {
+ if (hardware_is_ours) {
hardware_is_ours = 0;
- del_timer(&sampling_timer);
+ if (sampling_timer.data)
+ del_timer(&sampling_timer);
sampling_timer.data = 0;
perfctr_cpu_release(this_service);
module_put(THIS_MODULE);
@@ -73,7 +77,7 @@ static void sample_this_cpu(void *unused)
struct gperfctr *perfctr;
perfctr = &per_cpu_gperfctr[smp_processor_id()];
- if( !perfctr_cstatus_enabled(perfctr->cpu_state.cstatus) )
+ if (!perfctr_cstatus_enabled(perfctr->cpu_state.cstatus))
return;
spin_lock(&perfctr->lock);
perfctr_cpu_sample(&perfctr->cpu_state);
@@ -82,7 +86,20 @@ static void sample_this_cpu(void *unused)
static void sample_all_cpus(void)
{
- on_each_cpu(sample_this_cpu, NULL, 1, 1);
+ on_each_cpu(sample_this_cpu, NULL, 1);
+}
+
+static void do_sample_one_cpu(void *info)
+{
+ unsigned int cpu = (unsigned long)info;
+
+ if (cpu == smp_processor_id())
+ sample_this_cpu(NULL);
+}
+
+static void sample_one_cpu(unsigned int cpu)
+{
+ on_each_cpu(do_sample_one_cpu, (void*)(unsigned long)cpu, 1);
}
static void sampling_timer_function(unsigned long interval)
@@ -101,7 +118,7 @@ static unsigned long usectojiffies(unsigned long usec)
static void start_sampling_timer(unsigned long interval_usec)
{
- if( interval_usec > 0 ) {
+ if (interval_usec > 0) {
unsigned long interval = usectojiffies(interval_usec);
init_timer(&sampling_timer);
sampling_timer.function = sampling_timer_function;
@@ -118,13 +135,13 @@ static void start_this_cpu(void *unused)
struct gperfctr *perfctr;
perfctr = &per_cpu_gperfctr[smp_processor_id()];
- if( perfctr_cstatus_enabled(perfctr->cpu_state.cstatus) )
+ if (perfctr_cstatus_enabled(perfctr->cpu_state.cstatus))
perfctr_cpu_resume(&perfctr->cpu_state);
}
static void start_all_cpus(void)
{
- on_each_cpu(start_this_cpu, NULL, 1, 1);
+ on_each_cpu(start_this_cpu, NULL, 1);
}
static int gperfctr_control(struct perfctr_struct_buf *argp)
@@ -134,34 +151,34 @@ static int gperfctr_control(struct perfctr_struct_buf *argp)
struct gperfctr_cpu_control cpu_control;
ret = perfctr_copy_from_user(&cpu_control, argp, &gperfctr_cpu_control_sdesc);
- if( ret )
+ if (ret)
return ret;
- if( cpu_control.cpu >= NR_CPUS ||
+ if (cpu_control.cpu >= NR_CPUS ||
!cpu_online(cpu_control.cpu) ||
- perfctr_cpu_is_forbidden(cpu_control.cpu) )
+ perfctr_cpu_is_forbidden(cpu_control.cpu))
return -EINVAL;
/* we don't permit i-mode counters */
- if( cpu_control.cpu_control.nrictrs != 0 )
+ if (cpu_control.cpu_control.nrictrs != 0)
return -EPERM;
- down(&control_mutex);
+ mutex_lock(&control_mutex);
ret = -EBUSY;
- if( hardware_is_ours )
- goto out_up; /* you have to stop them first */
+ if (hardware_is_ours)
+ goto out_unlock; /* you have to stop them first */
perfctr = &per_cpu_gperfctr[cpu_control.cpu];
spin_lock(&perfctr->lock);
perfctr->cpu_state.tsc_start = 0;
perfctr->cpu_state.tsc_sum = 0;
memset(&perfctr->cpu_state.pmc, 0, sizeof perfctr->cpu_state.pmc);
perfctr->cpu_state.control = cpu_control.cpu_control;
- ret = perfctr_cpu_update_control(&perfctr->cpu_state, 1);
+ ret = perfctr_cpu_update_control(&perfctr->cpu_state, NULL);
spin_unlock(&perfctr->lock);
- if( ret < 0 )
- goto out_up;
- if( perfctr_cstatus_enabled(perfctr->cpu_state.cstatus) )
+ if (ret < 0)
+ goto out_unlock;
+ if (perfctr_cstatus_enabled(perfctr->cpu_state.cstatus))
++nr_active_cpus;
ret = nr_active_cpus;
- out_up:
- up(&control_mutex);
+ out_unlock:
+ mutex_unlock(&control_mutex);
return ret;
}
@@ -169,27 +186,27 @@ static int gperfctr_start(unsigned int interval_usec)
{
int ret;
- if( interval_usec < 10000 )
+ if (interval_usec && interval_usec < 10000)
return -EINVAL;
- down(&control_mutex);
+ mutex_lock(&control_mutex);
ret = nr_active_cpus;
- if( ret > 0 ) {
- if( reserve_hardware() < 0 ) {
+ if (ret > 0) {
+ if (reserve_hardware() < 0) {
ret = -EBUSY;
} else {
start_all_cpus();
start_sampling_timer(interval_usec);
}
}
- up(&control_mutex);
+ mutex_unlock(&control_mutex);
return ret;
}
static int gperfctr_stop(void)
{
- down(&control_mutex);
+ mutex_lock(&control_mutex);
release_hardware();
- up(&control_mutex);
+ mutex_unlock(&control_mutex);
return 0;
}
@@ -199,12 +216,13 @@ static int gperfctr_read(struct perfctr_struct_buf *argp)
struct gperfctr_cpu_state state;
int err;
- // XXX: sample_all_cpus() ???
err = perfctr_copy_from_user(&state, argp, &gperfctr_cpu_state_only_cpu_sdesc);
- if( err )
+ if (err)
return err;
- if( state.cpu >= NR_CPUS || !cpu_online(state.cpu) )
+ if (state.cpu >= NR_CPUS || !cpu_online(state.cpu))
return -EINVAL;
+ if (!sampling_timer.data)
+ sample_one_cpu(state.cpu);
perfctr = &per_cpu_gperfctr[state.cpu];
spin_lock(&perfctr->lock);
state.cpu_control = perfctr->cpu_state.control;
@@ -219,10 +237,9 @@ static int gperfctr_read(struct perfctr_struct_buf *argp)
return perfctr_copy_to_user(argp, &state, &gperfctr_cpu_state_sdesc);
}
-int gperfctr_ioctl(struct inode *inode, struct file *filp,
- unsigned int cmd, unsigned long arg)
+int gperfctr_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
- switch( cmd ) {
+ switch (cmd) {
case GPERFCTR_CONTROL:
return gperfctr_control((struct perfctr_struct_buf*)arg);
case GPERFCTR_READ:
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/global.h b/src/perfctr-2.6.x/linux/drivers/perfctr/global.h
index 1533f29458456edb9e4cc610ee79e2239c7f5f28..8e4384218986ed7cbf0945f12b2e21c7ace368fc 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/global.h
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/global.h
@@ -1,15 +1,14 @@
-/* $Id$
+/* $Id: global.h,v 1.7.2.1 2005/01/22 14:04:03 mikpe Exp $
* Global-mode performance-monitoring counters.
*
- * Copyright (C) 2000-2003 Mikael Pettersson
+ * Copyright (C) 2000-2005 Mikael Pettersson
*/
#ifdef CONFIG_PERFCTR_GLOBAL
-extern int gperfctr_ioctl(struct inode*, struct file*, unsigned int, unsigned long);
+extern int gperfctr_ioctl(struct file*, unsigned int, unsigned long);
extern void gperfctr_init(void);
#else
-extern int gperfctr_ioctl(struct inode *inode, struct file *filp,
- unsigned int cmd, unsigned long arg)
+extern int gperfctr_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
return -EINVAL;
}
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/init.c b/src/perfctr-2.6.x/linux/drivers/perfctr/init.c
index a61c7485cbab678aec54fdb047dcc2dfba46e80b..05aae3b658c8c81c35dcf560ff0985dd1096a349 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/init.c
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/init.c
@@ -1,10 +1,13 @@
-/* $Id$
+/* $Id: init.c,v 1.68.2.5 2009/01/23 17:21:20 mikpe Exp $
* Performance-monitoring counters driver.
* Top-level initialisation code.
*
- * Copyright (C) 1999-2004 Mikael Pettersson
+ * Copyright (C) 1999-2007, 2009 Mikael Pettersson
*/
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
#include <linux/config.h>
+#endif
#include <linux/module.h>
#include <linux/fs.h>
#include <linux/init.h>
@@ -20,13 +23,10 @@
#include "version.h"
#include "marshal.h"
-MODULE_AUTHOR("Mikael Pettersson <mikpe@csd.uu.se>");
+MODULE_AUTHOR("Mikael Pettersson <mikpe@it.uu.se>");
MODULE_DESCRIPTION("Performance-monitoring counters driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("char-major-10-182");
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,63)
-EXPORT_NO_SYMBOLS;
-#endif
#ifdef CONFIG_PERFCTR_DEBUG
#define VERSION_DEBUG " DEBUG"
@@ -89,37 +89,28 @@ int sys_perfctr_cpus_forbidden(struct perfctr_cpu_mask *argp)
return cpus_copy_to_user(&cpus, argp);
}
-#ifdef CONFIG_IA32_EMULATION
+#if defined(CONFIG_IA32_EMULATION) && !HAVE_COMPAT_IOCTL
#include <asm/ioctl32.h>
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,23)
-static int perfctr_ioctl32_handler(unsigned int fd, unsigned int cmd, unsigned long arg, struct file *filp)
-{
- /* filp->f_op->ioctl is known to exist; see sys32_ioctl() */
- return filp->f_op->ioctl(filp->f_dentry->d_inode, filp, cmd, arg);
-}
-#else
-#define perfctr_ioctl32_handler 0
-#endif
static void __init perfctr_register_ioctl32_conversions(void)
{
int err;
- err = register_ioctl32_conversion(PERFCTR_ABI, perfctr_ioctl32_handler);
- err |= register_ioctl32_conversion(PERFCTR_INFO, perfctr_ioctl32_handler);
- err |= register_ioctl32_conversion(PERFCTR_CPUS, perfctr_ioctl32_handler);
- err |= register_ioctl32_conversion(PERFCTR_CPUS_FORBIDDEN, perfctr_ioctl32_handler);
- err |= register_ioctl32_conversion(VPERFCTR_CREAT, perfctr_ioctl32_handler);
- err |= register_ioctl32_conversion(VPERFCTR_OPEN, perfctr_ioctl32_handler);
- err |= register_ioctl32_conversion(VPERFCTR_READ_SUM, perfctr_ioctl32_handler);
- err |= register_ioctl32_conversion(VPERFCTR_UNLINK, perfctr_ioctl32_handler);
- err |= register_ioctl32_conversion(VPERFCTR_CONTROL, perfctr_ioctl32_handler);
- err |= register_ioctl32_conversion(VPERFCTR_IRESUME, perfctr_ioctl32_handler);
- err |= register_ioctl32_conversion(VPERFCTR_READ_CONTROL, perfctr_ioctl32_handler);
- err |= register_ioctl32_conversion(GPERFCTR_CONTROL, perfctr_ioctl32_handler);
- err |= register_ioctl32_conversion(GPERFCTR_READ, perfctr_ioctl32_handler);
- err |= register_ioctl32_conversion(GPERFCTR_STOP, perfctr_ioctl32_handler);
- err |= register_ioctl32_conversion(GPERFCTR_START, perfctr_ioctl32_handler);
+ err = register_ioctl32_conversion(PERFCTR_ABI, 0);
+ err |= register_ioctl32_conversion(PERFCTR_INFO, 0);
+ err |= register_ioctl32_conversion(PERFCTR_CPUS, 0);
+ err |= register_ioctl32_conversion(PERFCTR_CPUS_FORBIDDEN, 0);
+ err |= register_ioctl32_conversion(VPERFCTR_CREAT, 0);
+ err |= register_ioctl32_conversion(VPERFCTR_OPEN, 0);
+ err |= register_ioctl32_conversion(VPERFCTR_READ_SUM, 0);
+ err |= register_ioctl32_conversion(VPERFCTR_UNLINK, 0);
+ err |= register_ioctl32_conversion(VPERFCTR_CONTROL, 0);
+ err |= register_ioctl32_conversion(VPERFCTR_IRESUME, 0);
+ err |= register_ioctl32_conversion(VPERFCTR_READ_CONTROL, 0);
+ err |= register_ioctl32_conversion(GPERFCTR_CONTROL, 0);
+ err |= register_ioctl32_conversion(GPERFCTR_READ, 0);
+ err |= register_ioctl32_conversion(GPERFCTR_STOP, 0);
+ err |= register_ioctl32_conversion(GPERFCTR_START, 0);
if( err )
printk(KERN_ERR "perfctr: register_ioctl32_conversion() failed\n");
}
@@ -148,8 +139,7 @@ static void __exit perfctr_unregister_ioctl32_conversions(void)
#define perfctr_unregister_ioctl32_conversions() do{}while(0)
#endif
-static int dev_perfctr_ioctl(struct inode *inode, struct file *filp,
- unsigned int cmd, unsigned long arg)
+static long dev_perfctr_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
switch( cmd ) {
case PERFCTR_ABI:
@@ -165,14 +155,30 @@ static int dev_perfctr_ioctl(struct inode *inode, struct file *filp,
case VPERFCTR_OPEN:
return vperfctr_attach((int)arg, 0);
default:
- return gperfctr_ioctl(inode, filp, cmd, arg);
+ return gperfctr_ioctl(filp, cmd, arg);
}
return -EINVAL;
}
+#if !HAVE_UNLOCKED_IOCTL
+static int dev_perfctr_ioctl_oldstyle(struct inode *inode, struct file *filp,
+ unsigned int cmd, unsigned long arg)
+{
+ return dev_perfctr_ioctl(filp, cmd, arg);
+}
+#endif
+
static struct file_operations dev_perfctr_file_ops = {
.owner = THIS_MODULE,
- .ioctl = dev_perfctr_ioctl,
+ /* 2.6.11-rc2 introduced HAVE_UNLOCKED_IOCTL and HAVE_COMPAT_IOCTL */
+#if HAVE_UNLOCKED_IOCTL
+ .unlocked_ioctl = dev_perfctr_ioctl,
+#else
+ .ioctl = dev_perfctr_ioctl_oldstyle,
+#endif
+#if defined(CONFIG_IA32_EMULATION) && HAVE_COMPAT_IOCTL
+ .compat_ioctl = dev_perfctr_ioctl,
+#endif
};
static struct miscdevice dev_perfctr = {
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/marshal.c b/src/perfctr-2.6.x/linux/drivers/perfctr/marshal.c
index eea6fd3fab2b164d27f5e9809672dfd5c612d792..c7cfaedfb37e93fa36915ee60ea97e60376573d1 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/marshal.c
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/marshal.c
@@ -1,11 +1,14 @@
-/* $Id$
+/* $Id: marshal.c,v 1.6.2.7 2008/06/22 12:48:56 mikpe Exp $
* Performance-monitoring counters driver.
* Structure marshalling support.
*
- * Copyright (C) 2003-2004 Mikael Pettersson
+ * Copyright (C) 2003-2008 Mikael Pettersson
*/
#ifdef __KERNEL__
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
#include <linux/config.h>
+#endif
struct inode;
#include <linux/sched.h>
#include <linux/perfctr.h>
@@ -198,10 +201,11 @@ int perfctr_decode_struct(void *address,
* *
****************************************************************/
+#undef ARRAY_SIZE
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#define STRUCT_ARRAY_SIZE(TYPE, MEMBER) ARRAY_SIZE(((TYPE*)0)->MEMBER)
-#if defined(__i386__) || defined(__x86_64__)
+#if defined(__i386__) || defined(__x86_64__) || defined(__powerpc__) || defined(__arm__)
#define PERFCTR_TAG_CPU_CONTROL_TSC_ON 32
#define PERFCTR_TAG_CPU_CONTROL_NRACTRS 33
@@ -209,19 +213,31 @@ int perfctr_decode_struct(void *address,
#define PERFCTR_TAG_CPU_CONTROL_PMC_MAP 35
#define PERFCTR_TAG_CPU_CONTROL_EVNTSEL 36
#define PERFCTR_TAG_CPU_CONTROL_IRESET 37
-#define PERFCTR_TAG_CPU_CONTROL_P4_ESCR 38
-#define PERFCTR_TAG_CPU_CONTROL_P4_PE 39
-#define PERFCTR_TAG_CPU_CONTROL_P4_PMV 40
+/* 38-40 are arch-specific, see below */
#define PERFCTR_TAG_CPU_CONTROL_RSVD1 41
#define PERFCTR_TAG_CPU_CONTROL_RSVD2 42
#define PERFCTR_TAG_CPU_CONTROL_RSVD3 43
#define PERFCTR_TAG_CPU_CONTROL_RSVD4 44
#define PERFCTR_CPU_CONTROL_NRFIELDS_0 (7 + STRUCT_ARRAY_SIZE(struct perfctr_cpu_control, pmc_map) + STRUCT_ARRAY_SIZE(struct perfctr_cpu_control, evntsel) + STRUCT_ARRAY_SIZE(struct perfctr_cpu_control, ireset))
-#ifdef __x86_64__
-#define PERFCTR_CPU_CONTROL_NRFIELDS_1 0
-#else
+
+#if defined(__i386__) || defined(__x86_64__)
+#define PERFCTR_TAG_CPU_CONTROL_P4_ESCR 38
+#define PERFCTR_TAG_CPU_CONTROL_P4_PE 39
+#define PERFCTR_TAG_CPU_CONTROL_P4_PMV 40
#define PERFCTR_CPU_CONTROL_NRFIELDS_1 (2 + STRUCT_ARRAY_SIZE(struct perfctr_cpu_control, p4.escr))
+#endif /* __i386__ || __x86_64__ */
+
+#if defined(__powerpc__)
+#define PERFCTR_TAG_CPU_CONTROL_PPC_MMCR0 38
+#define PERFCTR_TAG_CPU_CONTROL_PPC_MMCR2 39
+/* 40: unused */
+#define PERFCTR_CPU_CONTROL_NRFIELDS_1 2
+#endif /* __powerpc__ */
+
+#if defined(__arm__)
+#define PERFCTR_CPU_CONTROL_NRFIELDS_1 0
#endif
+
#define PERFCTR_CPU_CONTROL_NRFIELDS (PERFCTR_CPU_CONTROL_NRFIELDS_0 + PERFCTR_CPU_CONTROL_NRFIELDS_1)
#define PERFCTR_TAG_SUM_CTRS_TSC 48
@@ -267,7 +283,7 @@ static const struct perfctr_field_desc perfctr_cpu_control_fields[] = {
.tag = PERFCTR_TAG_CPU_CONTROL_IRESET,
.type = PERFCTR_TYPE_ARRAY(STRUCT_ARRAY_SIZE(struct perfctr_cpu_control,ireset),
PERFCTR_TYPE_BYTES4) },
-#ifndef __x86_64__
+#if defined(__i386__) || defined(__x86_64__)
{ .offset = offsetof(struct perfctr_cpu_control, p4.escr),
.tag = PERFCTR_TAG_CPU_CONTROL_P4_ESCR,
.type = PERFCTR_TYPE_ARRAY(STRUCT_ARRAY_SIZE(struct perfctr_cpu_control,p4.escr),
@@ -278,95 +294,8 @@ static const struct perfctr_field_desc perfctr_cpu_control_fields[] = {
{ .offset = offsetof(struct perfctr_cpu_control, p4.pebs_matrix_vert),
.tag = PERFCTR_TAG_CPU_CONTROL_P4_PMV,
.type = PERFCTR_TYPE_BYTES4 },
-#endif /* __x86_64__ */
- { .offset = offsetof(struct perfctr_cpu_control, _reserved1),
- .tag = PERFCTR_TAG_CPU_CONTROL_RSVD1,
- .type = PERFCTR_TYPE_BYTES4 },
- { .offset = offsetof(struct perfctr_cpu_control, _reserved2),
- .tag = PERFCTR_TAG_CPU_CONTROL_RSVD2,
- .type = PERFCTR_TYPE_BYTES4 },
- { .offset = offsetof(struct perfctr_cpu_control, _reserved3),
- .tag = PERFCTR_TAG_CPU_CONTROL_RSVD3,
- .type = PERFCTR_TYPE_BYTES4 },
- { .offset = offsetof(struct perfctr_cpu_control, _reserved4),
- .tag = PERFCTR_TAG_CPU_CONTROL_RSVD4,
- .type = PERFCTR_TYPE_BYTES4 },
-};
-
-const struct perfctr_struct_desc perfctr_cpu_control_sdesc = {
- .total_sizeof = sizeof(struct perfctr_cpu_control),
- .total_nrfields = PERFCTR_CPU_CONTROL_NRFIELDS,
- .nrfields = ARRAY_SIZE(perfctr_cpu_control_fields),
- .fields = perfctr_cpu_control_fields,
-};
-
#endif /* __i386__ || __x86_64__ */
-
-#if defined(__powerpc__) /* XXX: can be merged with x86/amd64 */
-
-#define PERFCTR_TAG_CPU_CONTROL_TSC_ON 32
-#define PERFCTR_TAG_CPU_CONTROL_NRACTRS 33
-#define PERFCTR_TAG_CPU_CONTROL_NRICTRS 34
-#define PERFCTR_TAG_CPU_CONTROL_PMC_MAP 35
-#define PERFCTR_TAG_CPU_CONTROL_EVNTSEL 36
-#define PERFCTR_TAG_CPU_CONTROL_IRESET 37
-#define PERFCTR_TAG_CPU_CONTROL_PPC_MMCR0 38
-#define PERFCTR_TAG_CPU_CONTROL_PPC_MMCR2 39
-/* 40: unused */
-#define PERFCTR_TAG_CPU_CONTROL_RSVD1 41
-#define PERFCTR_TAG_CPU_CONTROL_RSVD2 42
-#define PERFCTR_TAG_CPU_CONTROL_RSVD3 43
-#define PERFCTR_TAG_CPU_CONTROL_RSVD4 44
-#define PERFCTR_CPU_CONTROL_NRFIELDS_0 (7 + STRUCT_ARRAY_SIZE(struct perfctr_cpu_control, pmc_map) + STRUCT_ARRAY_SIZE(struct perfctr_cpu_control, evntsel) + STRUCT_ARRAY_SIZE(struct perfctr_cpu_control, ireset))
-#ifdef __powerpc__
-#define PERFCTR_CPU_CONTROL_NRFIELDS_1 2
-#endif
-#define PERFCTR_CPU_CONTROL_NRFIELDS (PERFCTR_CPU_CONTROL_NRFIELDS_0 + PERFCTR_CPU_CONTROL_NRFIELDS_1)
-
-#define PERFCTR_TAG_SUM_CTRS_TSC 48
-#define PERFCTR_TAG_SUM_CTRS_PMC 49
-#define PERFCTR_SUM_CTRS_NRFIELDS (1 + STRUCT_ARRAY_SIZE(struct perfctr_sum_ctrs, pmc))
-
-static const struct perfctr_field_desc perfctr_sum_ctrs_fields[] = {
- { .offset = offsetof(struct perfctr_sum_ctrs, tsc),
- .tag = PERFCTR_TAG_SUM_CTRS_TSC,
- .type = PERFCTR_TYPE_UINT64 },
- { .offset = offsetof(struct perfctr_sum_ctrs, pmc),
- .tag = PERFCTR_TAG_SUM_CTRS_PMC,
- .type = PERFCTR_TYPE_ARRAY(STRUCT_ARRAY_SIZE(struct perfctr_sum_ctrs,pmc),
- PERFCTR_TYPE_UINT64) },
-};
-
-const struct perfctr_struct_desc perfctr_sum_ctrs_sdesc = {
- .total_sizeof = sizeof(struct perfctr_sum_ctrs),
- .total_nrfields = PERFCTR_SUM_CTRS_NRFIELDS,
- .nrfields = ARRAY_SIZE(perfctr_sum_ctrs_fields),
- .fields = perfctr_sum_ctrs_fields,
-};
-
-static const struct perfctr_field_desc perfctr_cpu_control_fields[] = {
- { .offset = offsetof(struct perfctr_cpu_control, tsc_on),
- .tag = PERFCTR_TAG_CPU_CONTROL_TSC_ON,
- .type = PERFCTR_TYPE_BYTES4 },
- { .offset = offsetof(struct perfctr_cpu_control, nractrs),
- .tag = PERFCTR_TAG_CPU_CONTROL_NRACTRS,
- .type = PERFCTR_TYPE_BYTES4 },
- { .offset = offsetof(struct perfctr_cpu_control, nrictrs),
- .tag = PERFCTR_TAG_CPU_CONTROL_NRICTRS,
- .type = PERFCTR_TYPE_BYTES4 },
- { .offset = offsetof(struct perfctr_cpu_control, pmc_map),
- .tag = PERFCTR_TAG_CPU_CONTROL_PMC_MAP,
- .type = PERFCTR_TYPE_ARRAY(STRUCT_ARRAY_SIZE(struct perfctr_cpu_control,pmc_map),
- PERFCTR_TYPE_BYTES4) },
- { .offset = offsetof(struct perfctr_cpu_control, evntsel),
- .tag = PERFCTR_TAG_CPU_CONTROL_EVNTSEL,
- .type = PERFCTR_TYPE_ARRAY(STRUCT_ARRAY_SIZE(struct perfctr_cpu_control,evntsel),
- PERFCTR_TYPE_BYTES4) },
- { .offset = offsetof(struct perfctr_cpu_control, ireset),
- .tag = PERFCTR_TAG_CPU_CONTROL_IRESET,
- .type = PERFCTR_TYPE_ARRAY(STRUCT_ARRAY_SIZE(struct perfctr_cpu_control,ireset),
- PERFCTR_TYPE_BYTES4) },
-#ifdef __powerpc__
+#if defined(__powerpc__)
{ .offset = offsetof(struct perfctr_cpu_control, ppc.mmcr0),
.tag = PERFCTR_TAG_CPU_CONTROL_PPC_MMCR0,
.type = PERFCTR_TYPE_BYTES4 },
@@ -395,7 +324,7 @@ const struct perfctr_struct_desc perfctr_cpu_control_sdesc = {
.fields = perfctr_cpu_control_fields,
};
-#endif /* __powerpc__ */
+#endif /* __i386__ || __x86_64__ || __powerpc__ */
#define PERFCTR_TAG_INFO_ABI_VERSION 0
#define PERFCTR_TAG_INFO_DRIVER_VERSION 1
@@ -410,7 +339,7 @@ const struct perfctr_struct_desc perfctr_cpu_control_sdesc = {
#define VPERFCTR_TAG_CONTROL_SIGNO 9
#define VPERFCTR_TAG_CONTROL_PRESERVE 10
-#define VPERFCTR_TAG_CONTROL_RSVD1 11
+#define VPERFCTR_TAG_CONTROL_FLAGS 11
#define VPERFCTR_TAG_CONTROL_RSVD2 12
#define VPERFCTR_TAG_CONTROL_RSVD3 13
#define VPERFCTR_TAG_CONTROL_RSVD4 14
@@ -476,8 +405,8 @@ static const struct perfctr_field_desc vperfctr_control_fields[] = {
{ .offset = offsetof(struct vperfctr_control, preserve),
.tag = VPERFCTR_TAG_CONTROL_PRESERVE,
.type = PERFCTR_TYPE_BYTES4 },
- { .offset = offsetof(struct vperfctr_control, _reserved1),
- .tag = VPERFCTR_TAG_CONTROL_RSVD1,
+ { .offset = offsetof(struct vperfctr_control, flags),
+ .tag = VPERFCTR_TAG_CONTROL_FLAGS,
.type = PERFCTR_TYPE_BYTES4 },
{ .offset = offsetof(struct vperfctr_control, _reserved2),
.tag = VPERFCTR_TAG_CONTROL_RSVD2,
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/marshal.h b/src/perfctr-2.6.x/linux/drivers/perfctr/marshal.h
index 5850afe34947f1e98e651c4fe504f944493a448d..7b33cb955a29b6828d1f81e65015b306c6549458 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/marshal.h
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/marshal.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: marshal.h,v 1.1 2003/08/19 13:37:07 mikpe Exp $
* Performance-monitoring counters driver.
* Structure marshalling support.
*
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/ppc.c b/src/perfctr-2.6.x/linux/drivers/perfctr/ppc.c
index 71e79725e1e837204db02460f64eac565ae41291..2a3e77b542c28d6e88c74ea81cbf9a0a1c959db4 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/ppc.c
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/ppc.c
@@ -1,17 +1,19 @@
-/* $Id$
+/* $Id: ppc.c,v 1.3.2.22 2009/06/11 12:33:51 mikpe Exp $
* PPC32 performance-monitoring counters driver.
*
- * Copyright (C) 2004 Mikael Pettersson
+ * Copyright (C) 2004-2009 Mikael Pettersson
*/
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
#include <linux/config.h>
+#endif
#define __NO_VERSION__
#include <linux/module.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/fs.h>
#include <linux/perfctr.h>
-#include <linux/seq_file.h>
-#include <asm/machdep.h>
+#include <asm/prom.h>
#include <asm/time.h> /* tb_ticks_per_jiffy, get_tbl() */
#include "compat.h"
@@ -27,6 +29,8 @@ struct per_cpu_cache { /* roughly a subset of perfctr_cpu_state */
unsigned int ppc_mmcr[3];
} ____cacheline_aligned;
static struct per_cpu_cache per_cpu_cache[NR_CPUS] __cacheline_aligned;
+#define __get_cpu_cache(cpu) (&per_cpu_cache[cpu])
+#define get_cpu_cache() (&per_cpu_cache[smp_processor_id()])
/* Structure for counter snapshots, as 32-bit values. */
struct perfctr_low_ctrs {
@@ -35,74 +39,23 @@ struct perfctr_low_ctrs {
};
enum pm_type {
- PM_604,
- PM_604e,
- PM_750, /* XXX: Minor event set diffs between IBM and Moto. */
- PM_7400,
- PM_7450,
+ PM_NONE,
+ PM_604,
+ PM_604e,
+ PM_750, /* XXX: Minor event set diffs between IBM and Moto. */
+ PM_7400,
+ PM_7450,
};
static enum pm_type pm_type;
-#define SPRN_MMCR0 0x3B8 /* 604 and up */
-#define SPRN_PMC1 0x3B9 /* 604 and up */
-#define SPRN_PMC2 0x3BA /* 604 and up */
-#define SPRN_SIA 0x3BB /* 604 and up */
-#define SPRN_MMCR1 0x3BC /* 604e and up */
-#define SPRN_PMC3 0x3BD /* 604e and up */
-#define SPRN_PMC4 0x3BE /* 604e and up */
-#define SPRN_MMCR2 0x3B0 /* 7400 and up */
-#define SPRN_BAMR 0x3B7 /* 7400 and up */
-#define SPRN_PMC5 0x3B1 /* 7450 and up */
-#define SPRN_PMC6 0x3B2 /* 7450 and up */
-
-/* MMCR0 layout (74xx terminology) */
-#define MMCR0_FC 0x80000000 /* Freeze counters unconditionally. */
-#define MMCR0_FCS 0x40000000 /* Freeze counters while MSR[PR]=0 (supervisor mode). */
-#define MMCR0_FCP 0x20000000 /* Freeze counters while MSR[PR]=1 (user mode). */
-#define MMCR0_FCM1 0x10000000 /* Freeze counters while MSR[PM]=1. */
-#define MMCR0_FCM0 0x08000000 /* Freeze counters while MSR[PM]=0. */
-#define MMCR0_PMXE 0x04000000 /* Enable performance monitor exceptions.
- * Cleared by hardware when a PM exception occurs.
- * 604: PMXE is not cleared by hardware.
- */
-#define MMCR0_FCECE 0x02000000 /* Freeze counters on enabled condition or event.
- * FCECE is treated as 0 if TRIGGER is 1.
- * 74xx: FC is set when the event occurs.
- * 604/750: ineffective when PMXE=0.
- */
-#define MMCR0_TBSEL 0x01800000 /* Time base lower (TBL) bit selector.
- * 00: bit 31, 01: bit 23, 10: bit 19, 11: bit 15.
- */
-#define MMCR0_TBEE 0x00400000 /* Enable event on TBL bit transition from 0 to 1. */
-#define MMCR0_THRESHOLD 0x003F0000 /* Threshold value for certain events. */
-#define MMCR0_PMC1CE 0x00008000 /* Enable event on PMC1 overflow. */
-#define MMCR0_PMCjCE 0x00004000 /* Enable event on PMC2-PMC6 overflow.
- * 604/750: Overrides FCECE (DISCOUNT).
- */
-#define MMCR0_TRIGGER 0x00002000 /* Disable PMC2-PMC6 until PMC1 overflow or other event.
- * 74xx: cleared by hardware when the event occurs.
- */
-#define MMCR0_PMC1SEL 0x00001FB0 /* PMC1 event selector, 7 bits. */
-#define MMCR0_PMC2SEL 0x0000003F /* PMC2 event selector, 6 bits. */
-#define MMCR0_RESERVED (MMCR0_PMXE | MMCR0_PMC1SEL | MMCR0_PMC2SEL)
-
-/* MMCR1 layout (604e-7457) */
-#define MMCR1_PMC3SEL 0xF8000000 /* PMC3 event selector, 5 bits. */
-#define MMCR1_PMC4SEL 0x07B00000 /* PMC4 event selector, 5 bits. */
-#define MMCR1_PMC5SEL 0x003E0000 /* PMC5 event selector, 5 bits. (745x only) */
-#define MMCR1_PMC6SEL 0x0001F800 /* PMC6 event selector, 6 bits. (745x only) */
-#define MMCR1__RESERVED 0x000007FF /* should be zero */
-
-/* MMCR2 layout (7400-7457) */
-#define MMCR2_THRESHMULT 0x80000000 /* MMCR0[THRESHOLD] multiplier. */
-#define MMCR2_SMCNTEN 0x40000000 /* 7400/7410 only, should be zero. */
-#define MMCR2_SMINTEN 0x20000000 /* 7400/7410 only, should be zero. */
-#define MMCR2__RESERVED 0x1FFFFFFF /* should be zero */
-#define MMCR2_RESERVED (MMCR2_SMCNTEN | MMCR2_SMINTEN | MMCR2__RESERVED)
+/* Bits users shouldn't set in control.ppc.mmcr0:
+ * - PMC1SEL/PMC2SEL because event selectors are in control.evntsel[]
+ */
+#define MMCR0_RESERVED (MMCR0_PMC1SEL | MMCR0_PMC2SEL)
static unsigned int new_id(void)
{
- static spinlock_t lock = SPIN_LOCK_UNLOCKED;
+ static DEFINE_SPINLOCK(lock);
static unsigned int counter;
int id;
@@ -112,37 +65,47 @@ static unsigned int new_id(void)
return id;
}
-#if !defined(PERFCTR_INTERRUPT_SUPPORT)
+#ifndef CONFIG_PERFCTR_INTERRUPT_SUPPORT
#define perfctr_cstatus_has_ictrs(cstatus) 0
#endif
-#if defined(CONFIG_SMP) && PERFCTR_INTERRUPT_SUPPORT
+#if defined(CONFIG_SMP) && defined(CONFIG_PERFCTR_INTERRUPT_SUPPORT)
-static inline void set_isuspend_cpu(struct perfctr_cpu_state *state,
- const struct per_cpu_cache *cache)
+static inline void
+set_isuspend_cpu(struct perfctr_cpu_state *state, int cpu)
{
- state->k1.isuspend_cpu = cache;
+ state->k1.isuspend_cpu = cpu;
}
-static inline int is_isuspend_cpu(const struct perfctr_cpu_state *state,
- const struct per_cpu_cache *cache)
+static inline int
+is_isuspend_cpu(const struct perfctr_cpu_state *state, int cpu)
{
- return state->k1.isuspend_cpu == cache;
+ return state->k1.isuspend_cpu == cpu;
}
static inline void clear_isuspend_cpu(struct perfctr_cpu_state *state)
{
- state->k1.isuspend_cpu = NULL;
+ state->k1.isuspend_cpu = NR_CPUS;
}
#else
-static inline void set_isuspend_cpu(struct perfctr_cpu_state *state,
- const struct per_cpu_cache *cache) { }
-static inline int is_isuspend_cpu(const struct perfctr_cpu_state *state,
- const struct per_cpu_cache *cache) { return 1; }
+static inline void set_isuspend_cpu(struct perfctr_cpu_state *state, int cpu) { }
+static inline int is_isuspend_cpu(const struct perfctr_cpu_state *state, int cpu) { return 1; }
static inline void clear_isuspend_cpu(struct perfctr_cpu_state *state) { }
#endif
+/* The ppc driver internally uses cstatus & (1<<30) to record that
+ a context has an asynchronously changing MMCR0. */
+static inline unsigned int perfctr_cstatus_set_mmcr0_quirk(unsigned int cstatus)
+{
+ return cstatus | (1 << 30);
+}
+
+static inline int perfctr_cstatus_has_mmcr0_quirk(unsigned int cstatus)
+{
+ return cstatus & (1 << 30);
+}
+
/****************************************************************
* *
* Driver procedures. *
@@ -174,14 +137,6 @@ static inline void clear_isuspend_cpu(struct perfctr_cpu_state *state) { }
* doing this (a) reserves one PMC, and (b) needs indirect accesses
* since the SPR number in general isn't known at compile-time.
*
- * Driver notes
- * ------------
- * - The driver currently does not support performance monitor interrupts,
- * mostly because of the 750/7400/7410 erratum. Working around it would
- * require disabling the decrementer interrupt, reserving a performance
- * counter and setting it up for TBL bit-flip events, and having the PMI
- * handler invoke the decrementer handler.
- *
* 604
* ---
* 604 has MMCR0, PMC1, PMC2, SIA, and SDA.
@@ -224,6 +179,8 @@ static inline void clear_isuspend_cpu(struct perfctr_cpu_state *state) { }
*
* 750FX adds dual-PLL support and programmable core frequency switching.
*
+ * 750FX DD2.3 fixed the DEC/PMI SRR0 corruption erratum.
+ *
* 74xx
* ----
* 7400 adds MMCR2 and BAMR.
@@ -248,7 +205,7 @@ static inline void clear_isuspend_cpu(struct perfctr_cpu_state *state) { }
static inline unsigned int read_pmc(unsigned int pmc)
{
- switch( pmc ) {
+ switch (pmc) {
default: /* impossible, but silences gcc warning */
case 0:
return mfspr(SPRN_PMC1);
@@ -265,30 +222,24 @@ static inline unsigned int read_pmc(unsigned int pmc)
}
}
-static void ppc_read_counters(/*const*/ struct perfctr_cpu_state *state,
+static void ppc_read_counters(struct perfctr_cpu_state *state,
struct perfctr_low_ctrs *ctrs)
{
unsigned int cstatus, nrctrs, i;
cstatus = state->cstatus;
- if( perfctr_cstatus_has_tsc(cstatus) )
+ if (perfctr_cstatus_has_tsc(cstatus))
ctrs->tsc = get_tbl();
nrctrs = perfctr_cstatus_nractrs(cstatus);
for(i = 0; i < nrctrs; ++i) {
unsigned int pmc = state->pmc[i].map;
ctrs->pmc[i] = read_pmc(pmc);
}
- /* handle MMCR0 changes due to FCECE or TRIGGER on 74xx */
- if( state->cstatus & (1<<30) ) {
- unsigned int mmcr0 = mfspr(SPRN_MMCR0);
- state->ppc_mmcr[0] = mmcr0;
- per_cpu_cache[smp_processor_id()].ppc_mmcr[0] = mmcr0;
- }
}
static unsigned int pmc_max_event(unsigned int pmc)
{
- switch( pmc ) {
+ switch (pmc) {
default: /* impossible, but silences gcc warning */
case 0:
return 127;
@@ -307,56 +258,71 @@ static unsigned int pmc_max_event(unsigned int pmc)
static unsigned int get_nr_pmcs(void)
{
- switch( pm_type ) {
+ switch (pm_type) {
case PM_7450:
return 6;
case PM_7400:
case PM_750:
case PM_604e:
return 4;
- default: /* impossible, but silences gcc warning */
case PM_604:
return 2;
+ default: /* PM_NONE, but silences gcc warning */
+ return 0;
}
}
static int ppc_check_control(struct perfctr_cpu_state *state)
{
- unsigned int i, nrctrs, pmc_mask, pmc;
+ unsigned int i, nractrs, nrctrs, pmc_mask, pmi_mask, pmc;
unsigned int nr_pmcs, evntsel[6];
nr_pmcs = get_nr_pmcs();
- nrctrs = state->control.nractrs;
- if( state->control.nrictrs || nrctrs > nr_pmcs )
+ nractrs = state->control.nractrs;
+ nrctrs = nractrs + state->control.nrictrs;
+ if (nrctrs < nractrs || nrctrs > nr_pmcs)
return -EINVAL;
pmc_mask = 0;
+ pmi_mask = 0;
memset(evntsel, 0, sizeof evntsel);
for(i = 0; i < nrctrs; ++i) {
pmc = state->control.pmc_map[i];
state->pmc[i].map = pmc;
- if( pmc >= nr_pmcs || (pmc_mask & (1<<pmc)) )
+ if (pmc >= nr_pmcs || (pmc_mask & (1<<pmc)))
return -EINVAL;
pmc_mask |= (1<<pmc);
+ if (i >= nractrs)
+ pmi_mask |= (1<<pmc);
+
evntsel[pmc] = state->control.evntsel[i];
- if( evntsel[pmc] > pmc_max_event(pmc) )
+ if (evntsel[pmc] > pmc_max_event(pmc))
return -EINVAL;
}
- switch( pm_type ) {
+ /* XXX: temporary limitation */
+ if ((pmi_mask & ~1) && (pmi_mask & ~1) != (pmc_mask & ~1))
+ return -EINVAL;
+
+ switch (pm_type) {
case PM_7450:
- if( state->control.ppc.mmcr2 & MMCR2_RESERVED )
+ case PM_7400:
+ if (state->control.ppc.mmcr2 & MMCR2_RESERVED)
return -EINVAL;
state->ppc_mmcr[2] = state->control.ppc.mmcr2;
break;
default:
- if( state->control.ppc.mmcr2 )
+ if (state->control.ppc.mmcr2)
return -EINVAL;
state->ppc_mmcr[2] = 0;
}
- if( state->control.ppc.mmcr0 & MMCR0_RESERVED )
+ /* We do not yet handle TBEE as the only exception cause,
+ so PMXE requires at least one interrupt-mode counter. */
+ if ((state->control.ppc.mmcr0 & MMCR0_PMXE) && !state->control.nrictrs)
+ return -EINVAL;
+ if (state->control.ppc.mmcr0 & MMCR0_RESERVED)
return -EINVAL;
state->ppc_mmcr[0] = (state->control.ppc.mmcr0
| (evntsel[0] << (31-25))
@@ -371,30 +337,99 @@ static int ppc_check_control(struct perfctr_cpu_state *state)
/*
* MMCR0[FC] and MMCR0[TRIGGER] may change on 74xx if FCECE or
- * TRIGGER is set. To avoid undoing those changes, we must read
- * MMCR0 back into state->ppc_mmcr[0] and the cache at suspends.
+ * TRIGGER is set. At suspends we must read MMCR0 back into
+ * the state and the cache and then freeze the counters, and
+ * at resumes we must unfreeze the counters and reload MMCR0.
*/
- switch( pm_type ) {
+ switch (pm_type) {
case PM_7450:
case PM_7400:
- if( state->ppc_mmcr[0] & (MMCR0_FCECE | MMCR0_TRIGGER) )
- state->cstatus |= (1<<30);
+ if (state->ppc_mmcr[0] & (MMCR0_FCECE | MMCR0_TRIGGER))
+ state->cstatus = perfctr_cstatus_set_mmcr0_quirk(state->cstatus);
default:
;
}
+ /* The MMCR0 handling for FCECE and TRIGGER is also needed for PMXE. */
+ if (state->ppc_mmcr[0] & (MMCR0_PMXE | MMCR0_FCECE | MMCR0_TRIGGER))
+ state->cstatus = perfctr_cstatus_set_mmcr0_quirk(state->cstatus);
+
return 0;
}
-#if PERFCTR_INTERRUPT_SUPPORT
+#ifdef CONFIG_PERFCTR_INTERRUPT_SUPPORT
+/* PRE: perfctr_cstatus_has_ictrs(state->cstatus) != 0 */
+/* PRE: counters frozen */
static void ppc_isuspend(struct perfctr_cpu_state *state)
{
- // XXX
+ struct per_cpu_cache *cache;
+ unsigned int cstatus, nrctrs, i;
+ int cpu;
+
+ cpu = smp_processor_id();
+ set_isuspend_cpu(state, cpu); /* early to limit cpu's live range */
+ cache = __get_cpu_cache(cpu);
+ cstatus = state->cstatus;
+ nrctrs = perfctr_cstatus_nrctrs(cstatus);
+ for(i = perfctr_cstatus_nractrs(cstatus); i < nrctrs; ++i) {
+ unsigned int pmc = state->pmc[i].map;
+ unsigned int now = read_pmc(pmc);
+ state->pmc[i].sum += now - state->pmc[i].start;
+ state->pmc[i].start = now;
+ }
+ /* cache->k1.id is still == state->k1.id */
}
static void ppc_iresume(const struct perfctr_cpu_state *state)
{
- // XXX
+ struct per_cpu_cache *cache;
+ unsigned int cstatus, nrctrs, i;
+ int cpu;
+ unsigned int pmc[6];
+
+ cpu = smp_processor_id();
+ cache = __get_cpu_cache(cpu);
+ if (cache->k1.id == state->k1.id) {
+ /* Clearing cache->k1.id to force write_control()
+ to unfreeze MMCR0 would be done here, but it
+ is subsumed by resume()'s MMCR0 reload logic. */
+ if (is_isuspend_cpu(state, cpu))
+ return; /* skip reload of PMCs */
+ }
+ /*
+ * The CPU state wasn't ours.
+ *
+ * The counters must be frozen before being reinitialised,
+ * to prevent unexpected increments and missed overflows.
+ *
+ * All unused counters must be reset to a non-overflow state.
+ */
+ if (!(cache->ppc_mmcr[0] & MMCR0_FC)) {
+ cache->ppc_mmcr[0] |= MMCR0_FC;
+ mtspr(SPRN_MMCR0, cache->ppc_mmcr[0]);
+ }
+ memset(&pmc[0], 0, sizeof pmc);
+ cstatus = state->cstatus;
+ nrctrs = perfctr_cstatus_nrctrs(cstatus);
+ for(i = perfctr_cstatus_nractrs(cstatus); i < nrctrs; ++i)
+ pmc[state->pmc[i].map] = state->pmc[i].start;
+
+ switch (pm_type) {
+ case PM_7450:
+ mtspr(SPRN_PMC6, pmc[6-1]);
+ mtspr(SPRN_PMC5, pmc[5-1]);
+ case PM_7400:
+ case PM_750:
+ case PM_604e:
+ mtspr(SPRN_PMC4, pmc[4-1]);
+ mtspr(SPRN_PMC3, pmc[3-1]);
+ case PM_604:
+ mtspr(SPRN_PMC2, pmc[2-1]);
+ mtspr(SPRN_PMC1, pmc[1-1]);
+ case PM_NONE:
+ ;
+ }
+ /* cache->k1.id remains != state->k1.id */
}
#endif
@@ -403,11 +438,9 @@ static void ppc_write_control(const struct perfctr_cpu_state *state)
struct per_cpu_cache *cache;
unsigned int value;
- cache = &per_cpu_cache[smp_processor_id()];
- if( cache->k1.id == state->k1.id ) {
- //debug_evntsel_cache(state, cache);
+ cache = get_cpu_cache();
+ if (cache->k1.id == state->k1.id)
return;
- }
/*
* Order matters here: update threshmult and event
* selectors before updating global control, which
@@ -422,17 +455,17 @@ static void ppc_write_control(const struct perfctr_cpu_state *state)
* preventing any actual mtspr to it. Ditto for MMCR1.
*/
value = state->ppc_mmcr[2];
- if( value != cache->ppc_mmcr[2] ) {
+ if (value != cache->ppc_mmcr[2]) {
cache->ppc_mmcr[2] = value;
mtspr(SPRN_MMCR2, value);
}
value = state->ppc_mmcr[1];
- if( value != cache->ppc_mmcr[1] ) {
+ if (value != cache->ppc_mmcr[1]) {
cache->ppc_mmcr[1] = value;
mtspr(SPRN_MMCR1, value);
}
value = state->ppc_mmcr[0];
- if( value != cache->ppc_mmcr[0] ) {
+ if (value != cache->ppc_mmcr[0]) {
cache->ppc_mmcr[0] = value;
mtspr(SPRN_MMCR0, value);
}
@@ -441,7 +474,7 @@ static void ppc_write_control(const struct perfctr_cpu_state *state)
static void ppc_clear_counters(void)
{
- switch( pm_type ) {
+ switch (pm_type) {
case PM_7450:
case PM_7400:
mtspr(SPRN_MMCR2, 0);
@@ -451,8 +484,10 @@ static void ppc_clear_counters(void)
mtspr(SPRN_MMCR1, 0);
case PM_604:
mtspr(SPRN_MMCR0, 0);
+ case PM_NONE:
+ ;
}
- switch( pm_type ) {
+ switch (pm_type) {
case PM_7450:
mtspr(SPRN_PMC6, 0);
mtspr(SPRN_PMC5, 0);
@@ -464,6 +499,8 @@ static void ppc_clear_counters(void)
case PM_604:
mtspr(SPRN_PMC2, 0);
mtspr(SPRN_PMC1, 0);
+ case PM_NONE:
+ ;
}
}
@@ -476,13 +513,13 @@ static void perfctr_cpu_write_control(const struct perfctr_cpu_state *state)
return ppc_write_control(state);
}
-static void perfctr_cpu_read_counters(/*const*/ struct perfctr_cpu_state *state,
+static void perfctr_cpu_read_counters(struct perfctr_cpu_state *state,
struct perfctr_low_ctrs *ctrs)
{
return ppc_read_counters(state, ctrs);
}
-#if PERFCTR_INTERRUPT_SUPPORT
+#ifdef CONFIG_PERFCTR_INTERRUPT_SUPPORT
static void perfctr_cpu_isuspend(struct perfctr_cpu_state *state)
{
return ppc_isuspend(state);
@@ -497,10 +534,11 @@ static void perfctr_cpu_iresume(const struct perfctr_cpu_state *state)
bypass internal caching and force a reload if the I-mode PMCs. */
void perfctr_cpu_ireload(struct perfctr_cpu_state *state)
{
+ state->ppc_mmcr[0] |= MMCR0_PMXE;
#ifdef CONFIG_SMP
clear_isuspend_cpu(state);
#else
- per_cpu_cache[smp_processor_id()].k1.id = 0;
+ get_cpu_cache()->k1.id = 0;
#endif
}
@@ -514,15 +552,14 @@ unsigned int perfctr_cpu_identify_overflow(struct perfctr_cpu_state *state)
nrctrs = perfctr_cstatus_nrctrs(cstatus);
for(pmc_mask = 0; pmc < nrctrs; ++pmc) {
- if( (int)state->pmc[pmc].start < 0 ) { /* PPC-specific */
+ if ((int)state->pmc[pmc].start < 0) { /* PPC-specific */
/* XXX: "+=" to correct for overshots */
state->pmc[pmc].start = state->control.ireset[pmc];
pmc_mask |= (1 << pmc);
}
}
- /* XXX: if pmc_mask == 0, then it must have been a TBL bit flip */
- /* XXX: HW cleared MMCR0[ENINT]. We presumably cleared the entire
- MMCR0, so the re-enable occurs automatically later, no? */
+ if (!pmc_mask && (state->ppc_mmcr[0] & MMCR0_TBEE))
+ pmc_mask = (1<<8); /* fake TB bit flip indicator */
return pmc_mask;
}
@@ -533,7 +570,7 @@ static inline int check_ireset(const struct perfctr_cpu_state *state)
i = state->control.nractrs;
nrctrs = i + state->control.nrictrs;
for(; i < nrctrs; ++i)
- if( state->control.ireset[i] < 0 ) /* PPC-specific */
+ if (state->control.ireset[i] < 0) /* PPC-specific */
return -EINVAL;
return 0;
}
@@ -548,49 +585,35 @@ static inline void setup_imode_start_values(struct perfctr_cpu_state *state)
state->pmc[i].start = state->control.ireset[i];
}
-static inline void debug_no_imode(const struct perfctr_cpu_state *state)
-{
-#ifdef CONFIG_PERFCTR_DEBUG
- if( perfctr_cstatus_has_ictrs(state->cstatus) )
- printk(KERN_ERR "perfctr/%s: BUG! updating control in"
- " perfctr %p on cpu %u while it has cstatus %x"
- " (pid %d, comm %s)\n",
- __FILE__, state, smp_processor_id(), state->cstatus,
- current->pid, current->comm);
-#endif
-}
-
-#else /* PERFCTR_INTERRUPT_SUPPORT */
+#else /* CONFIG_PERFCTR_INTERRUPT_SUPPORT */
static inline void perfctr_cpu_isuspend(struct perfctr_cpu_state *state) { }
static inline void perfctr_cpu_iresume(const struct perfctr_cpu_state *state) { }
static inline int check_ireset(const struct perfctr_cpu_state *state) { return 0; }
static inline void setup_imode_start_values(struct perfctr_cpu_state *state) { }
-static inline void debug_no_imode(const struct perfctr_cpu_state *state) { }
-#endif /* PERFCTR_INTERRUPT_SUPPORT */
+#endif /* CONFIG_PERFCTR_INTERRUPT_SUPPORT */
static int check_control(struct perfctr_cpu_state *state)
{
return ppc_check_control(state);
}
-int perfctr_cpu_update_control(struct perfctr_cpu_state *state, int is_global)
+int perfctr_cpu_update_control(struct perfctr_cpu_state *state, cpumask_t *cpumask)
{
int err;
- debug_no_imode(state);
clear_isuspend_cpu(state);
state->cstatus = 0;
/* disallow i-mode counters if we cannot catch the interrupts */
- if( !(perfctr_info.cpu_features & PERFCTR_FEATURE_PCINT)
- && state->control.nrictrs )
+ if (!(perfctr_info.cpu_features & PERFCTR_FEATURE_PCINT)
+ && state->control.nrictrs)
return -EPERM;
err = check_ireset(state);
- if( err < 0 )
+ if (err < 0)
return err;
err = check_control(state); /* may initialise state->cstatus */
- if( err < 0 )
+ if (err < 0)
return err;
state->cstatus |= perfctr_mk_cstatus(state->control.tsc_on,
state->control.nractrs,
@@ -604,11 +627,17 @@ void perfctr_cpu_suspend(struct perfctr_cpu_state *state)
unsigned int i, cstatus, nractrs;
struct perfctr_low_ctrs now;
- if( perfctr_cstatus_has_ictrs(state->cstatus) )
- perfctr_cpu_isuspend(state);
+ if (perfctr_cstatus_has_mmcr0_quirk(state->cstatus)) {
+ unsigned int mmcr0 = mfspr(SPRN_MMCR0);
+ mtspr(SPRN_MMCR0, mmcr0 | MMCR0_FC);
+ get_cpu_cache()->ppc_mmcr[0] = mmcr0 | MMCR0_FC;
+ state->ppc_mmcr[0] = mmcr0;
+ }
+ if (perfctr_cstatus_has_ictrs(state->cstatus))
+ perfctr_cpu_isuspend(state);
perfctr_cpu_read_counters(state, &now);
cstatus = state->cstatus;
- if( perfctr_cstatus_has_tsc(cstatus) )
+ if (perfctr_cstatus_has_tsc(cstatus))
state->tsc_sum += now.tsc - state->tsc_start;
nractrs = perfctr_cstatus_nractrs(cstatus);
for(i = 0; i < nractrs; ++i)
@@ -617,8 +646,10 @@ void perfctr_cpu_suspend(struct perfctr_cpu_state *state)
void perfctr_cpu_resume(struct perfctr_cpu_state *state)
{
- if( perfctr_cstatus_has_ictrs(state->cstatus) )
+ if (perfctr_cstatus_has_ictrs(state->cstatus))
perfctr_cpu_iresume(state);
+ if (perfctr_cstatus_has_mmcr0_quirk(state->cstatus))
+ get_cpu_cache()->k1.id = 0; /* force reload of MMCR0 */
perfctr_cpu_write_control(state);
//perfctr_cpu_read_counters(state, &state->start);
{
@@ -626,7 +657,7 @@ void perfctr_cpu_resume(struct perfctr_cpu_state *state)
unsigned int i, cstatus, nrctrs;
perfctr_cpu_read_counters(state, &now);
cstatus = state->cstatus;
- if( perfctr_cstatus_has_tsc(cstatus) )
+ if (perfctr_cstatus_has_tsc(cstatus))
state->tsc_start = now.tsc;
nrctrs = perfctr_cstatus_nractrs(cstatus);
for(i = 0; i < nrctrs; ++i)
@@ -642,7 +673,7 @@ void perfctr_cpu_sample(struct perfctr_cpu_state *state)
perfctr_cpu_read_counters(state, &now);
cstatus = state->cstatus;
- if( perfctr_cstatus_has_tsc(cstatus) ) {
+ if (perfctr_cstatus_has_tsc(cstatus)) {
state->tsc_sum += now.tsc - state->tsc_start;
state->tsc_start = now.tsc;
}
@@ -657,7 +688,7 @@ static void perfctr_cpu_clear_counters(void)
{
struct per_cpu_cache *cache;
- cache = &per_cpu_cache[smp_processor_id()];
+ cache = get_cpu_cache();
memset(cache, 0, sizeof *cache);
cache->k1.id = -1;
@@ -721,12 +752,12 @@ static unsigned char cfg_ratio_7457[32] __initdata = { // *2
16, 28, 12, 32, 27, 56, 0, 25
};
-static unsigned int __init tb_to_core_ratio(enum pll_type pll_type)
+static unsigned int __init pll_tb_to_core(enum pll_type pll_type)
{
unsigned char *cfg_ratio;
unsigned int shift = 28, mask = 0xF, hid1, pll_cfg, ratio;
- switch( pll_type ) {
+ switch (pll_type) {
case PLL_604e:
cfg_ratio = cfg_ratio_604e;
break;
@@ -736,7 +767,7 @@ static unsigned int __init tb_to_core_ratio(enum pll_type pll_type)
case PLL_750FX:
cfg_ratio = cfg_ratio_750FX;
hid1 = mfspr(SPRN_HID1);
- switch( (hid1 >> 16) & 0x3 ) { /* HID1[PI0,PS] */
+ switch ((hid1 >> 16) & 0x3) { /* HID1[PI0,PS] */
case 0: /* PLL0 with external config */
shift = 31-4; /* access HID1[PCE] */
break;
@@ -768,115 +799,191 @@ static unsigned int __init tb_to_core_ratio(enum pll_type pll_type)
hid1 = mfspr(SPRN_HID1);
pll_cfg = (hid1 >> shift) & mask;
ratio = cfg_ratio[pll_cfg];
- if( !ratio )
- printk(KERN_WARNING "perfctr/%s: unknown PLL_CFG 0x%x\n",
- __FILE__, pll_cfg);
+ if (!ratio)
+ printk(KERN_WARNING "perfctr: unknown PLL_CFG 0x%x\n", pll_cfg);
return (4/2) * ratio;
}
-static unsigned int __init pll_to_core_khz(enum pll_type pll_type)
+/* Extract core and timebase frequencies from Open Firmware. */
+
+#ifdef CONFIG_PPC_OF
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)
+static inline struct device_node *perfctr_of_find_node_by_type(struct device_node *from, const char *type)
+{
+ return of_find_node_by_type(from, type);
+}
+
+static inline void perfctr_of_node_put(struct device_node *node)
{
- unsigned int tb_to_core = tb_to_core_ratio(pll_type);
- perfctr_info.tsc_to_cpu_mult = tb_to_core;
- return tb_ticks_per_jiffy * tb_to_core * (HZ/10) / (1000/10);
+ of_node_put(node);
+}
+#else
+#define of_get_property(a, b, c) get_property((a), (b), (c))
+static inline struct device_node *perfctr_of_find_node_by_type(struct device_node *from, const char *type)
+{
+ return find_type_devices(type);
}
-/* Extract the CPU clock frequency from /proc/cpuinfo. */
+static inline void perfctr_of_node_put(struct device_node *node) { }
+#endif
-static unsigned int __init parse_clock_khz(struct seq_file *m)
+static unsigned int __init of_core_khz(void)
{
- /* "/proc/cpuinfo" formats:
- *
- * "core clock\t: %d MHz\n" // 8260 (show_percpuinfo)
- * "clock\t\t: %ldMHz\n" // 4xx (show_percpuinfo)
- * "clock\t\t: %dMHz\n" // oak (show_percpuinfo)
- * "clock\t\t: %ldMHz\n" // prep (show_percpuinfo)
- * "clock\t\t: %dMHz\n" // pmac (show_percpuinfo)
- * "clock\t\t: %dMHz\n" // gemini (show_cpuinfo!)
- */
- char *p;
- unsigned int mhz;
-
- p = m->buf;
- p[m->count] = '\0';
-
- for(;;) { /* for each line */
- if( strncmp(p, "core ", 5) == 0 )
- p += 5;
- do {
- if( strncmp(p, "clock\t", 6) != 0 )
- break;
- p += 6;
- while( *p == '\t' )
- ++p;
- if( *p != ':' )
- break;
- do {
- ++p;
- } while( *p == ' ' );
- mhz = simple_strtoul(p, 0, 10);
- if( mhz )
- return mhz * 1000;
- } while( 0 );
- for(;;) { /* skip to next line */
- switch( *p++ ) {
- case '\n':
- break;
- case '\0':
- return 0;
- default:
- continue;
- }
- break;
- }
- }
+ struct device_node *cpu;
+ unsigned int *fp, core;
+
+ cpu = perfctr_of_find_node_by_type(NULL, "cpu");
+ if (!cpu)
+ return 0;
+ fp = (unsigned int*)of_get_property(cpu, "clock-frequency", NULL);
+ core = 0;
+ if (fp)
+ core = *fp;
+ perfctr_of_node_put(cpu);
+ return core / 1000;
}
-static unsigned int __init detect_cpu_khz(enum pll_type pll_type)
+static unsigned int __init of_bus_khz(void)
{
- char buf[512];
- struct seq_file m;
- unsigned int khz;
+ struct device_node *cpu;
+ unsigned int *fp, bus;
- khz = pll_to_core_khz(pll_type);
- if( khz )
- return khz;
+ cpu = perfctr_of_find_node_by_type(NULL, "cpu");
+ if (!cpu)
+ return 0;
+ fp = (unsigned int*)of_get_property(cpu, "bus-frequency", NULL);
+ bus = 0;
+ if (!fp || !(bus = *fp)) {
+ fp = (unsigned int*)of_get_property(cpu, "config-bus-frequency", NULL);
+ if (fp)
+ bus = *fp;
+ }
+ perfctr_of_node_put(cpu);
+ return bus / 1000;
+}
- memset(&m, 0, sizeof m);
- m.buf = buf;
- m.size = (sizeof buf)-1;
+static unsigned int __init of_bus_to_core_x2(void)
+{
+ struct device_node *cpu;
+ unsigned int *fp, ratio;
- m.count = 0;
- if( ppc_md.show_percpuinfo != 0 &&
- ppc_md.show_percpuinfo(&m, 0) == 0 &&
- (khz = parse_clock_khz(&m)) != 0 )
- return khz;
+ cpu = perfctr_of_find_node_by_type(NULL, "cpu");
+ if (!cpu)
+ return 0;
+ fp = (unsigned int*)of_get_property(cpu, "processor-to-bus-ratio*2", NULL);
+ ratio = 0;
+ if (fp)
+ ratio = *fp;
+ perfctr_of_node_put(cpu);
+ return ratio;
+}
+#else
+static inline unsigned int of_core_khz(void) { return 0; }
+static inline unsigned int of_bus_khz(void) { return 0; }
+static inline unsigned int of_bus_to_core_x2(void) { return 0; }
+#endif
- m.count = 0;
- if( ppc_md.show_cpuinfo != 0 &&
- ppc_md.show_cpuinfo(&m) == 0 &&
- (khz = parse_clock_khz(&m)) != 0 )
- return khz;
+static unsigned int __init detect_tb_khz(unsigned int bus_khz, unsigned int tb_to_bus)
+{
+ unsigned int tb_khz, bus_tb_khz, diff;
+
+ tb_khz = tb_ticks_per_jiffy * (HZ/10) / (1000/10);
+ if (bus_khz && tb_to_bus) {
+ bus_tb_khz = bus_khz / tb_to_bus;
+ if (bus_tb_khz > tb_khz)
+ diff = bus_tb_khz - tb_khz;
+ else
+ diff = tb_khz - bus_tb_khz;
+ if (diff >= bus_tb_khz/20) {
+ printk(KERN_WARNING "perfctr: timebase frequency %u kHz seems"
+ " out of range, using %u kHz (bus/%u) instead\n",
+ tb_khz, bus_tb_khz, tb_to_bus);
+ return bus_tb_khz;
+ }
+ }
+ return tb_khz;
+}
- printk(KERN_WARNING "perfctr/%s: unable to determine CPU speed\n",
- __FILE__);
+static unsigned int __init detect_tb_to_core(enum pll_type pll_type, unsigned int tb_to_bus)
+{
+ unsigned int tb_to_core;
+ unsigned int bus_to_core_x2;
+
+ tb_to_core = pll_tb_to_core(pll_type);
+ if (tb_to_core)
+ return tb_to_core;
+ if (tb_to_bus) {
+ bus_to_core_x2 = of_bus_to_core_x2();
+ if (bus_to_core_x2)
+ return (tb_to_bus * bus_to_core_x2) / 2;
+ }
return 0;
}
-static int __init generic_init(void)
+static unsigned int __init detect_core_khz(unsigned int tb_khz, unsigned int tb_to_core)
+{
+ unsigned int core_khz;
+
+ if (tb_to_core) {
+ perfctr_info.tsc_to_cpu_mult = tb_to_core;
+ return tb_khz * tb_to_core;
+ }
+ core_khz = of_core_khz();
+ perfctr_info.tsc_to_cpu_mult = core_khz / tb_khz;
+ return core_khz;
+}
+
+/*
+ * Detect the timebase and core clock frequencies.
+ *
+ * Known issues:
+ * 1. The OF timebase-frequency property is sometimes way off, and
+ * similarly the ppc32 kernel's tb_ticks_per_jiffy variable.
+ * (Observed on a 7447A-based laptop.)
+ * Workaround: Compute the TB frequency from the bus frequency
+ * and the TB-to-bus ratio.
+ * 2. The OF clock-frequency property is sometimes wrong.
+ * (Observed on a Beige G3 with a 7455 upgrade processor.)
+ * Workaround: Compute the core frequency from the TB frequency
+ * and the TB-to-core ratio.
+ * 3. The PLL_CFG details may be unknown.
+ */
+static unsigned int __init detect_cpu_khz(enum pll_type pll_type, unsigned int tb_to_bus)
+{
+ unsigned int bus_khz;
+ unsigned int tb_khz;
+ unsigned int tb_to_core;
+ unsigned int core_khz;
+
+ bus_khz = of_bus_khz();
+ tb_khz = detect_tb_khz(bus_khz, tb_to_bus);
+ tb_to_core = detect_tb_to_core(pll_type, tb_to_bus);
+ core_khz = detect_core_khz(tb_khz, tb_to_core);
+ if (!core_khz)
+ printk(KERN_WARNING "perfctr: unable to determine CPU speed\n");
+ return core_khz;
+}
+
+static int __init known_init(void)
{
- static char generic_name[] __initdata = "PowerPC 60x/7xx/74xx";
+ static char known_name[] __initdata = "PowerPC 60x/7xx/74xx";
unsigned int features;
enum pll_type pll_type;
unsigned int pvr;
+ int have_mmcr1;
+ unsigned int tb_to_bus;
+ tb_to_bus = 4; /* default, overridden below if necessary */
features = PERFCTR_FEATURE_RDTSC | PERFCTR_FEATURE_RDPMC;
+ have_mmcr1 = 1;
pvr = mfspr(SPRN_PVR);
- switch( PVR_VER(pvr) ) {
+ switch (PVR_VER(pvr)) {
case 0x0004: /* 604 */
pm_type = PM_604;
pll_type = PLL_NONE;
features = PERFCTR_FEATURE_RDTSC;
+ have_mmcr1 = 0;
break;
case 0x0009: /* 604e; */
case 0x000A: /* 604ev */
@@ -889,6 +996,13 @@ static int __init generic_init(void)
pll_type = PLL_750;
break;
case 0x7000: case 0x7001: /* IBM750FX */
+ if ((pvr & 0xFF0F) >= 0x0203)
+ features |= PERFCTR_FEATURE_PCINT;
+ pm_type = PM_750;
+ pll_type = PLL_750FX;
+ break;
+ case 0x7002: /* IBM750GX */
+ features |= PERFCTR_FEATURE_PCINT;
pm_type = PM_750;
pll_type = PLL_750FX;
break;
@@ -897,75 +1011,91 @@ static int __init generic_init(void)
pll_type = PLL_7400;
break;
case 0x800C: /* 7410 */
+ if ((pvr & 0xFFFF) >= 0x1103)
+ features |= PERFCTR_FEATURE_PCINT;
pm_type = PM_7400;
pll_type = PLL_7400;
break;
case 0x8000: /* 7451/7441 */
+ features |= PERFCTR_FEATURE_PCINT;
pm_type = PM_7450;
pll_type = PLL_7450;
break;
case 0x8001: /* 7455/7445 */
+ features |= PERFCTR_FEATURE_PCINT;
pm_type = PM_7450;
pll_type = ((pvr & 0xFFFF) < 0x0303) ? PLL_7450 : PLL_7457;
break;
case 0x8002: /* 7457/7447 */
+ case 0x8003: /* 7447A */
+ features |= PERFCTR_FEATURE_PCINT;
pm_type = PM_7450;
pll_type = PLL_7457;
break;
+ case 0x8004: /* 7448 */
+ features |= PERFCTR_FEATURE_PCINT;
+ pm_type = PM_7450;
+ pll_type = PLL_NONE; /* known to differ from 7447A, no details yet */
+ break;
default:
- printk(KERN_WARNING "perfctr/%s: unknown PowerPC with "
- "PVR 0x%08x -- bailing out\n", __FILE__, pvr);
return -ENODEV;
}
perfctr_info.cpu_features = features;
perfctr_info.cpu_type = 0; /* user-space should inspect PVR */
- perfctr_cpu_name = generic_name;
- perfctr_info.cpu_khz = detect_cpu_khz(pll_type);
- perfctr_ppc_init_tests();
+ perfctr_cpu_name = known_name;
+ perfctr_info.cpu_khz = detect_cpu_khz(pll_type, tb_to_bus);
+ perfctr_ppc_init_tests(have_mmcr1);
return 0;
}
-static void __init perfctr_cpu_init_one(void *ignore)
+static int __init unknown_init(void)
{
- /* PREEMPT note: when called via smp_call_function(),
- this is in IRQ context with preemption disabled. */
- perfctr_cpu_clear_counters();
+ static char unknown_name[] __initdata = "Generic PowerPC with TB";
+ unsigned int khz;
+
+ khz = detect_cpu_khz(PLL_NONE, 0);
+ if (!khz)
+ return -ENODEV;
+ perfctr_info.cpu_features = PERFCTR_FEATURE_RDTSC;
+ perfctr_info.cpu_type = 0;
+ perfctr_cpu_name = unknown_name;
+ perfctr_info.cpu_khz = khz;
+ pm_type = PM_NONE;
+ return 0;
}
-static void __exit perfctr_cpu_exit_one(void *ignore)
+static void perfctr_cpu_clear_one(void *ignore)
{
- /* PREEMPT note: when called via smp_call_function(),
+ /* PREEMPT note: when called via on_each_cpu(),
this is in IRQ context with preemption disabled. */
perfctr_cpu_clear_counters();
}
+static void perfctr_cpu_reset(void)
+{
+ on_each_cpu(perfctr_cpu_clear_one, NULL, 1);
+ perfctr_cpu_set_ihandler(NULL);
+}
+
int __init perfctr_cpu_init(void)
{
int err;
- preempt_disable();
-
perfctr_info.cpu_features = 0;
- err = generic_init();
- if( err )
- goto out;
+ err = known_init();
+ if (err) {
+ err = unknown_init();
+ if (err)
+ goto out;
+ }
- perfctr_cpu_init_one(NULL);
- smp_call_function(perfctr_cpu_init_one, NULL, 1, 1);
- perfctr_cpu_set_ihandler(NULL);
out:
- preempt_enable();
return err;
}
void __exit perfctr_cpu_exit(void)
{
- preempt_disable();
- perfctr_cpu_exit_one(NULL);
- smp_call_function(perfctr_cpu_exit_one, NULL, 1, 1);
- perfctr_cpu_set_ihandler(NULL);
- preempt_enable();
}
/****************************************************************
@@ -974,34 +1104,41 @@ void __exit perfctr_cpu_exit(void)
* *
****************************************************************/
+static DEFINE_MUTEX(mutex);
static const char *current_service = 0;
const char *perfctr_cpu_reserve(const char *service)
{
- if( current_service )
- return current_service;
+ const char *ret;
+
+ mutex_lock(&mutex);
+ ret = current_service;
+ if (ret)
+ goto out_unlock;
+ ret = "unknown driver (oprofile?)";
+ if (perfctr_reserve_pmc_hardware() < 0)
+ goto out_unlock;
current_service = service;
__module_get(THIS_MODULE);
- return 0;
-}
-
-static void perfctr_cpu_clear_one(void *ignore)
-{
- /* PREEMPT note: when called via smp_call_function(),
- this is in IRQ context with preemption disabled. */
- perfctr_cpu_clear_counters();
+ perfctr_cpu_reset();
+ ret = NULL;
+ out_unlock:
+ mutex_unlock(&mutex);
+ return ret;
}
void perfctr_cpu_release(const char *service)
{
- if( service != current_service ) {
+ mutex_lock(&mutex);
+ if (service != current_service) {
printk(KERN_ERR "%s: attempt by %s to release while reserved by %s\n",
__FUNCTION__, service, current_service);
} else {
/* power down the counters */
- on_each_cpu(perfctr_cpu_clear_one, NULL, 1, 1);
- perfctr_cpu_set_ihandler(NULL);
+ perfctr_cpu_reset();
current_service = 0;
+ perfctr_release_pmc_hardware();
module_put(THIS_MODULE);
}
+ mutex_unlock(&mutex);
}
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/ppc_compat.h b/src/perfctr-2.6.x/linux/drivers/perfctr/ppc_compat.h
index 9b2e350de5ae7af458c5b6d417df033ae9369e02..360287bc3e3af8f6243f026ca8a28a36627fbd81 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/ppc_compat.h
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/ppc_compat.h
@@ -1,10 +1,101 @@
-/* $Id$
+/* $Id: ppc_compat.h,v 1.1.2.8 2009/01/23 17:01:02 mikpe Exp $
* Performance-monitoring counters driver.
- * PPC32-specific compatibility definitions for 2.4/2.6 kernels.
+ * PPC32-specific compatibility definitions for 2.6 kernels.
*
- * Copyright (C) 2004 Mikael Pettersson
+ * Copyright (C) 2004-2007, 2009 Mikael Pettersson
*/
-#if 0
-#include <linux/config.h>
#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
+#include <linux/config.h>
+#endif
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,16)
+#include <asm/pmc.h>
+#else
+static inline int reserve_pmc_hardware(void (*new_perf_irq)(struct pt_regs*)) { return 0; }
+static inline void release_pmc_hardware(void) { }
#endif
+extern int perfctr_reserve_pmc_hardware(void);
+static inline void perfctr_release_pmc_hardware(void) { release_pmc_hardware(); }
+
+#undef MMCR0_FC
+#undef MMCR0_FCECE
+#undef MMCR0_FCM0
+#undef MMCR0_FCM1
+#undef MMCR0_FCP
+#undef MMCR0_FCS
+#undef MMCR0_PMC1CE
+#undef MMCR0_PMC1SEL
+#undef MMCR0_PMC2SEL
+#undef MMCR0_PMXE
+#undef MMCR0_TBEE
+#undef MMCR0_TRIGGER
+#undef MMCR1_PMC3SEL
+#undef MMCR1_PMC4SEL
+#undef MMCR1_PMC5SEL
+#undef MMCR1_PMC6SEL
+#undef SPRN_MMCR0
+#undef SPRN_MMCR1
+#undef SPRN_MMCR2
+#undef SPRN_PMC1
+#undef SPRN_PMC2
+#undef SPRN_PMC3
+#undef SPRN_PMC4
+#undef SPRN_PMC5
+#undef SPRN_PMC6
+
+#define SPRN_MMCR0 0x3B8 /* 604 and up */
+#define SPRN_PMC1 0x3B9 /* 604 and up */
+#define SPRN_PMC2 0x3BA /* 604 and up */
+#define SPRN_SIA 0x3BB /* 604 and up */
+#define SPRN_MMCR1 0x3BC /* 604e and up */
+#define SPRN_PMC3 0x3BD /* 604e and up */
+#define SPRN_PMC4 0x3BE /* 604e and up */
+#define SPRN_MMCR2 0x3B0 /* 7400 and up */
+#define SPRN_BAMR 0x3B7 /* 7400 and up */
+#define SPRN_PMC5 0x3B1 /* 7450 and up */
+#define SPRN_PMC6 0x3B2 /* 7450 and up */
+
+/* MMCR0 layout (74xx terminology) */
+#define MMCR0_FC 0x80000000 /* Freeze counters unconditionally. */
+#define MMCR0_FCS 0x40000000 /* Freeze counters while MSR[PR]=0 (supervisor mode). */
+#define MMCR0_FCP 0x20000000 /* Freeze counters while MSR[PR]=1 (user mode). */
+#define MMCR0_FCM1 0x10000000 /* Freeze counters while MSR[PM]=1. */
+#define MMCR0_FCM0 0x08000000 /* Freeze counters while MSR[PM]=0. */
+#define MMCR0_PMXE 0x04000000 /* Enable performance monitor exceptions.
+ * Cleared by hardware when a PM exception occurs.
+ * 604: PMXE is not cleared by hardware.
+ */
+#define MMCR0_FCECE 0x02000000 /* Freeze counters on enabled condition or event.
+ * FCECE is treated as 0 if TRIGGER is 1.
+ * 74xx: FC is set when the event occurs.
+ * 604/750: ineffective when PMXE=0.
+ */
+#define MMCR0_TBSEL 0x01800000 /* Time base lower (TBL) bit selector.
+ * 00: bit 31, 01: bit 23, 10: bit 19, 11: bit 15.
+ */
+#define MMCR0_TBEE 0x00400000 /* Enable event on TBL bit transition from 0 to 1. */
+#define MMCR0_THRESHOLD 0x003F0000 /* Threshold value for certain events. */
+#define MMCR0_PMC1CE 0x00008000 /* Enable event on PMC1 overflow. */
+#define MMCR0_PMCjCE 0x00004000 /* Enable event on PMC2-PMC6 overflow.
+ * 604/750: Overrides FCECE (DISCOUNT).
+ */
+#define MMCR0_TRIGGER 0x00002000 /* Disable PMC2-PMC6 until PMC1 overflow or other event.
+ * 74xx: cleared by hardware when the event occurs.
+ */
+#define MMCR0_PMC1SEL 0x00001FC0 /* PMC1 event selector, 7 bits. */
+#define MMCR0_PMC2SEL 0x0000003F /* PMC2 event selector, 6 bits. */
+
+/* MMCR1 layout (604e-7457) */
+#define MMCR1_PMC3SEL 0xF8000000 /* PMC3 event selector, 5 bits. */
+#define MMCR1_PMC4SEL 0x07C00000 /* PMC4 event selector, 5 bits. */
+#define MMCR1_PMC5SEL 0x003E0000 /* PMC5 event selector, 5 bits. (745x only) */
+#define MMCR1_PMC6SEL 0x0001F800 /* PMC6 event selector, 6 bits. (745x only) */
+#define MMCR1__RESERVED 0x000007FF /* should be zero */
+
+/* MMCR2 layout (7400-7457) */
+#define MMCR2_THRESHMULT 0x80000000 /* MMCR0[THRESHOLD] multiplier. */
+#define MMCR2_SMCNTEN 0x40000000 /* 7400/7410 only, should be zero. */
+#define MMCR2_SMINTEN 0x20000000 /* 7400/7410 only, should be zero. */
+#define MMCR2__RESERVED 0x1FFFFFFF /* should be zero */
+#define MMCR2_RESERVED (MMCR2_SMCNTEN | MMCR2_SMINTEN | MMCR2__RESERVED)
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/ppc_setup.c b/src/perfctr-2.6.x/linux/drivers/perfctr/ppc_setup.c
index 78637874b23c8dd445cadb702984250e4eea649d..45b7fd19fc9bea6ec4c2639b0d7762b7ade8139c 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/ppc_setup.c
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/ppc_setup.c
@@ -1,10 +1,13 @@
-/* $Id$
+/* $Id: ppc_setup.c,v 1.1.2.4 2006/10/15 09:22:16 mikpe Exp $
* Performance-monitoring counters driver.
* PPC32-specific kernel-resident code.
*
- * Copyright (C) 2004 Mikael Pettersson
+ * Copyright (C) 2004-2006 Mikael Pettersson
*/
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
#include <linux/config.h>
+#endif
#include <linux/module.h>
#include <linux/init.h>
#include <linux/kernel.h>
@@ -15,7 +18,7 @@
#include "ppc_compat.h"
#include "compat.h"
-#if PERFCTR_INTERRUPT_SUPPORT
+#ifdef CONFIG_PERFCTR_INTERRUPT_SUPPORT
static void perfctr_default_ihandler(unsigned long pc)
{
}
@@ -25,16 +28,22 @@ static perfctr_ihandler_t perfctr_ihandler = perfctr_default_ihandler;
void do_perfctr_interrupt(struct pt_regs *regs)
{
preempt_disable();
- (*perfctr_ihandler)(regs->nip);
+ (*perfctr_ihandler)(instruction_pointer(regs));
preempt_enable_no_resched();
}
+int perfctr_reserve_pmc_hardware(void)
+{
+ return reserve_pmc_hardware(do_perfctr_interrupt);
+}
+
void perfctr_cpu_set_ihandler(perfctr_ihandler_t ihandler)
{
perfctr_ihandler = ihandler ? ihandler : perfctr_default_ihandler;
}
#ifdef CONFIG_PERFCTR_MODULE
+EXPORT_SYMBOL(perfctr_reserve_pmc_hardware);
EXPORT_SYMBOL(perfctr_cpu_set_ihandler);
#endif /* MODULE */
-#endif /* PERFCTR_INTERRUPT_SUPPORT */
+#endif /* CONFIG_PERFCTR_INTERRUPT_SUPPORT */
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/ppc_tests.c b/src/perfctr-2.6.x/linux/drivers/perfctr/ppc_tests.c
index c96d9075b469b282b8a019c21478b46e345ccfcd..b98318208aa80afda300c064c918bbebed6852c6 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/ppc_tests.c
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/ppc_tests.c
@@ -1,10 +1,13 @@
-/* $Id$
+/* $Id: ppc_tests.c,v 1.1.2.7 2007/10/07 17:18:52 mikpe Exp $
* Performance-monitoring counters driver.
* Optional PPC32-specific init-time tests.
*
- * Copyright (C) 2004 Mikael Pettersson
+ * Copyright (C) 2004-2007 Mikael Pettersson
*/
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
#include <linux/config.h>
+#endif
#define __NO_VERSION__
#include <linux/module.h>
#include <linux/init.h>
@@ -12,7 +15,7 @@
#include <linux/fs.h>
#include <linux/perfctr.h>
#include <asm/processor.h>
-#include <asm/time.h> /* for tb_ticks_per_jiffy */
+#include "compat.h"
#include "ppc_compat.h"
#include "ppc_tests.h"
@@ -124,13 +127,15 @@ static void __init init_tests_message(void)
{
unsigned int pvr = mfspr(SPRN_PVR);
printk(KERN_INFO "Please email the following PERFCTR INIT lines "
- "to mikpe@csd.uu.se\n"
+ "to mikpe@it.uu.se\n"
KERN_INFO "To remove this message, rebuild the driver "
"with CONFIG_PERFCTR_INIT_TESTS=n\n");
printk(KERN_INFO "PERFCTR INIT: PVR 0x%08x, CPU clock %u kHz, TB clock %u kHz\n",
pvr,
perfctr_info.cpu_khz,
- tb_ticks_per_jiffy*(HZ/10)/(1000/10));
+ perfctr_info.tsc_to_cpu_mult
+ ? (perfctr_info.cpu_khz / perfctr_info.tsc_to_cpu_mult)
+ : 0);
}
static void __init clear(int have_mmcr1)
@@ -138,11 +143,11 @@ static void __init clear(int have_mmcr1)
mtspr(SPRN_MMCR0, 0);
mtspr(SPRN_PMC1, 0);
mtspr(SPRN_PMC2, 0);
- if( have_mmcr1 ) {
+ if (have_mmcr1) {
mtspr(SPRN_MMCR1, 0);
mtspr(SPRN_PMC3, 0);
mtspr(SPRN_PMC4, 0);
- }
+ }
}
static void __init check_fcece(unsigned int pmc1ce)
@@ -168,14 +173,14 @@ static void __init check_fcece(unsigned int pmc1ce)
*/
mtspr(SPRN_PMC1, 0x80000000-100);
mmcr0 = (1<<(31-6)) | (0x01 << 6);
- if( pmc1ce )
+ if (pmc1ce)
mmcr0 |= (1<<(31-16));
mtspr(SPRN_MMCR0, mmcr0);
do {
do_empty_loop(0);
- } while( !(mfspr(SPRN_PMC1) & 0x80000000) );
+ } while (!(mfspr(SPRN_PMC1) & 0x80000000));
do_empty_loop(0);
- printk(KERN_INFO "PERFCTR INIT: %s(%u): MMCR0[FC] is %u, PMC1 is %#x\n",
+ printk(KERN_INFO "PERFCTR INIT: %s(%u): MMCR0[FC] is %u, PMC1 is %#lx\n",
__FUNCTION__, pmc1ce,
!!(mfspr(SPRN_MMCR0) & (1<<(31-0))), mfspr(SPRN_PMC1));
mtspr(SPRN_MMCR0, 0);
@@ -206,14 +211,14 @@ static void __init check_trigger(unsigned int pmc1ce)
mtspr(SPRN_PMC2, 0);
mtspr(SPRN_PMC1, 0x80000000-100);
mmcr0 = (1<<(31-18)) | (0x01 << 6) | (0x01 << 0);
- if( pmc1ce )
+ if (pmc1ce)
mmcr0 |= (1<<(31-16));
mtspr(SPRN_MMCR0, mmcr0);
do {
do_empty_loop(0);
- } while( !(mfspr(SPRN_PMC1) & 0x80000000) );
+ } while (!(mfspr(SPRN_PMC1) & 0x80000000));
do_empty_loop(0);
- printk(KERN_INFO "PERFCTR INIT: %s(%u): MMCR0[TRIGGER] is %u, PMC1 is %#x, PMC2 is %#x\n",
+ printk(KERN_INFO "PERFCTR INIT: %s(%u): MMCR0[TRIGGER] is %u, PMC1 is %#lx, PMC2 is %#lx\n",
__FUNCTION__, pmc1ce,
!!(mfspr(SPRN_MMCR0) & (1<<(31-18))), mfspr(SPRN_PMC1), mfspr(SPRN_PMC2));
mtspr(SPRN_MMCR0, 0);
@@ -271,7 +276,7 @@ measure_overheads(int have_mmcr1)
printk(KERN_INFO "PERFCTR INIT: loop overhead is %u cycles\n", loop);
for(i = 0; i < ARRAY_SIZE(ticks); ++i) {
unsigned int x;
- if( !ticks[i] )
+ if (!ticks[i])
continue;
x = ((ticks[i] - loop) * 10) / NITER;
printk(KERN_INFO "PERFCTR INIT: %s cost is %u.%u cycles (%u total)\n",
@@ -283,7 +288,9 @@ measure_overheads(int have_mmcr1)
check_trigger(1);
}
-void __init perfctr_ppc_init_tests(void)
+void __init perfctr_ppc_init_tests(int have_mmcr1)
{
- measure_overheads(PVR_VER(mfspr(SPRN_PVR)) != 0x0004);
+ preempt_disable();
+ measure_overheads(have_mmcr1);
+ preempt_enable();
}
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/ppc_tests.h b/src/perfctr-2.6.x/linux/drivers/perfctr/ppc_tests.h
index 17a9d173b9ce309aa29bc26bd07539ba2cfd8f27..bc9682d7035c373749063498b2aaa629f60c727a 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/ppc_tests.h
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/ppc_tests.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: ppc_tests.h,v 1.1.2.1 2004/06/21 22:33:35 mikpe Exp $
* Performance-monitoring counters driver.
* Optional PPC32-specific init-time tests.
*
@@ -6,7 +6,7 @@
*/
#ifdef CONFIG_PERFCTR_INIT_TESTS
-extern void perfctr_ppc_init_tests(void);
+extern void perfctr_ppc_init_tests(int have_mmcr1);
#else
-#define perfctr_ppc_init_tests()
+static inline void perfctr_ppc_init_tests(int have_mmcr1) { }
#endif
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/version.h b/src/perfctr-2.6.x/linux/drivers/perfctr/version.h
index 0e98a230c6f39f5db04648db41a98a0153afc96b..200d6023b6d7b0b34066194d2f7a23fd3063c97d 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/version.h
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/version.h
@@ -1 +1 @@
-#define VERSION "2.6.5"
+#define VERSION "2.6.41"
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/virtual.c b/src/perfctr-2.6.x/linux/drivers/perfctr/virtual.c
index a5bb0b25e6bed407f799c5a27a3a7aee26c274b2..7677cf3fe292a3a0f66fb68e3df171c25b41ae43 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/virtual.c
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/virtual.c
@@ -1,13 +1,16 @@
-/* $Id$
+/* $Id: virtual.c,v 1.88.2.28 2009/06/11 08:09:12 mikpe Exp $
* Virtual per-process performance counters.
*
- * Copyright (C) 1999-2003 Mikael Pettersson
+ * Copyright (C) 1999-2009 Mikael Pettersson
*/
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
#include <linux/config.h>
+#endif
#define __NO_VERSION__
#include <linux/module.h>
#include <linux/init.h>
-#include <linux/compiler.h> /* for unlikely() in 2.4.18 and older */
+#include <linux/compiler.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/ptrace.h>
@@ -39,16 +42,19 @@ struct vperfctr {
/* sampling_timer and bad_cpus_allowed are frequently
accessed, so they get to share a cache line */
unsigned int sampling_timer ____cacheline_aligned;
-#if PERFCTR_CPUS_FORBIDDEN_MASK_NEEDED
+#ifdef CONFIG_PERFCTR_CPUS_FORBIDDEN_MASK
atomic_t bad_cpus_allowed;
+ cpumask_t cpumask;
#endif
+ pid_t updater_tgid; /* to detect self vs remote vperfctr_control races */
#if 0 && defined(CONFIG_PERFCTR_DEBUG)
unsigned start_smp_id;
unsigned suspended;
#endif
-#if PERFCTR_INTERRUPT_SUPPORT
+#ifdef CONFIG_PERFCTR_INTERRUPT_SUPPORT
unsigned int iresume_cstatus;
#endif
+ unsigned int flags;
};
#define IS_RUNNING(perfctr) perfctr_cstatus_enabled((perfctr)->cpu_state.cstatus)
@@ -59,33 +65,33 @@ do { \
int i; \
for(i = 0; i < PAGE_SIZE/sizeof(int); ++i) \
((int*)(perfctr))[i] = 0xfedac0ed; \
-} while( 0 )
-#define debug_init(perfctr) do { (perfctr)->suspended = 1; } while( 0 )
+} while(0)
+#define debug_init(perfctr) do { (perfctr)->suspended = 1; } while(0)
#define debug_suspend(perfctr) \
do { \
- if( (perfctr)->suspended ) \
+ if ((perfctr)->suspended) \
printk(KERN_ERR "%s: BUG! suspending non-running perfctr (pid %d, comm %s)\n", \
__FUNCTION__, current->pid, current->comm); \
(perfctr)->suspended = 1; \
-} while( 0 )
+} while(0)
#define debug_resume(perfctr) \
do { \
- if( !(perfctr)->suspended ) \
+ if (!(perfctr)->suspended) \
printk(KERN_ERR "%s: BUG! resuming non-suspended perfctr (pid %d, comm %s)\n", \
__FUNCTION__, current->pid, current->comm); \
(perfctr)->suspended = 0; \
-} while( 0 )
+} while(0)
#define debug_check_smp_id(perfctr) \
do { \
- if( (perfctr)->start_smp_id != smp_processor_id() ) { \
+ if ((perfctr)->start_smp_id != smp_processor_id()) { \
printk(KERN_ERR "%s: BUG! current cpu %u differs from start cpu %u (pid %d, comm %s)\n", \
__FUNCTION__, smp_processor_id(), (perfctr)->start_smp_id, \
current->pid, current->comm); \
return; \
} \
-} while( 0 )
+} while(0)
#define debug_set_smp_id(perfctr) \
- do { (perfctr)->start_smp_id = smp_processor_id(); } while( 0 )
+ do { (perfctr)->start_smp_id = smp_processor_id(); } while(0)
#else /* CONFIG_PERFCTR_DEBUG */
#define debug_free(perfctr) do{}while(0)
#define debug_init(perfctr) do{}while(0)
@@ -95,9 +101,10 @@ do { \
#define debug_set_smp_id(perfctr) do{}while(0)
#endif /* CONFIG_PERFCTR_DEBUG */
-#if PERFCTR_INTERRUPT_SUPPORT
+#ifdef CONFIG_PERFCTR_INTERRUPT_SUPPORT
static void vperfctr_ihandler(unsigned long pc);
+static void vperfctr_handle_overflow(struct task_struct*, struct vperfctr*);
static inline void vperfctr_set_ihandler(void)
{
@@ -114,13 +121,18 @@ static inline void vperfctr_set_ihandler(void) { }
static inline void vperfctr_clear_iresume_cstatus(struct vperfctr *perfctr) { }
#endif
-#if PERFCTR_CPUS_FORBIDDEN_MASK_NEEDED
+#ifdef CONFIG_PERFCTR_CPUS_FORBIDDEN_MASK
static inline void vperfctr_init_bad_cpus_allowed(struct vperfctr *perfctr)
{
atomic_set(&perfctr->bad_cpus_allowed, 0);
}
+static inline void vperfctr_init_cpumask(struct vperfctr *perfctr)
+{
+ cpus_setall(perfctr->cpumask);
+}
+
/* Concurrent set_cpus_allowed() is possible. The only lock it
can take is the task lock, so we have to take it as well.
task_lock/unlock also disables/enables preemption. */
@@ -135,10 +147,12 @@ static inline void vperfctr_task_unlock(struct task_struct *p)
task_unlock(p);
}
-#else /* !PERFCTR_CPUS_FORBIDDEN_MASK_NEEDED */
+#else /* !CONFIG_PERFCTR_CPUS_FORBIDDEN_MASK */
static inline void vperfctr_init_bad_cpus_allowed(struct vperfctr *perfctr) { }
+static inline void vperfctr_init_cpumask(struct vperfctr *perfctr) { }
+
/* Concurrent set_cpus_allowed() is impossible or irrelevant.
Disabling and enabling preemption suffices for an atomic region. */
@@ -152,7 +166,32 @@ static inline void vperfctr_task_unlock(struct task_struct *p)
preempt_enable();
}
-#endif /* !PERFCTR_CPUS_FORBIDDEN_MASK_NEEDED */
+#endif /* !CONFIG_PERFCTR_CPUS_FORBIDDEN_MASK */
+
+/* How to lock around find_task_by_vpid(). The tasklist_lock always
+ works, but it's no longer exported starting with kernel 2.6.18.
+ For kernels 2.6.18 and newer use rcu_read_{lock,unlock}(). */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18)
+static inline void vperfctr_lock_find_task_by_vpid(void)
+{
+ rcu_read_lock();
+}
+
+static inline void vperfctr_unlock_find_task_by_vpid(void)
+{
+ rcu_read_unlock();
+}
+#else /* < 2.6.18 */
+static inline void vperfctr_lock_find_task_by_vpid(void)
+{
+ read_lock(&tasklist_lock);
+}
+
+static inline void vperfctr_unlock_find_task_by_vpid(void)
+{
+ read_unlock(&tasklist_lock);
+}
+#endif /* < 2.6.18 */
/****************************************************************
* *
@@ -161,7 +200,7 @@ static inline void vperfctr_task_unlock(struct task_struct *p)
****************************************************************/
/* XXX: perhaps relax this to number of _live_ perfctrs */
-static spinlock_t nrctrs_lock = SPIN_LOCK_UNLOCKED;
+static DEFINE_MUTEX(nrctrs_mutex);
static int nrctrs;
static const char this_service[] = __FILE__;
@@ -170,14 +209,14 @@ static int inc_nrctrs(void)
const char *other;
other = NULL;
- spin_lock(&nrctrs_lock);
- if( ++nrctrs == 1 ) {
+ mutex_lock(&nrctrs_mutex);
+ if (++nrctrs == 1) {
other = perfctr_cpu_reserve(this_service);
- if( other )
+ if (other)
nrctrs = 0;
}
- spin_unlock(&nrctrs_lock);
- if( other ) {
+ mutex_unlock(&nrctrs_mutex);
+ if (other) {
printk(KERN_ERR __FILE__
": cannot operate, perfctr hardware taken by '%s'\n",
other);
@@ -189,20 +228,20 @@ static int inc_nrctrs(void)
static void dec_nrctrs(void)
{
- spin_lock(&nrctrs_lock);
- if( --nrctrs == 0 )
+ mutex_lock(&nrctrs_mutex);
+ if (--nrctrs == 0)
perfctr_cpu_release(this_service);
- spin_unlock(&nrctrs_lock);
+ mutex_unlock(&nrctrs_mutex);
}
static struct vperfctr *vperfctr_alloc(void)
{
unsigned long page;
- if( inc_nrctrs() != 0 )
+ if (inc_nrctrs() != 0)
return ERR_PTR(-EBUSY);
page = get_zeroed_page(GFP_KERNEL);
- if( !page ) {
+ if (!page) {
dec_nrctrs();
return ERR_PTR(-ENOMEM);
}
@@ -221,9 +260,10 @@ static void vperfctr_free(struct vperfctr *perfctr)
static struct vperfctr *get_empty_vperfctr(void)
{
struct vperfctr *perfctr = vperfctr_alloc();
- if( !IS_ERR(perfctr) ) {
+ if (!IS_ERR(perfctr)) {
atomic_set(&perfctr->count, 1);
vperfctr_init_bad_cpus_allowed(perfctr);
+ vperfctr_init_cpumask(perfctr);
spin_lock_init(&perfctr->owner_lock);
debug_init(perfctr);
}
@@ -232,7 +272,7 @@ static struct vperfctr *get_empty_vperfctr(void)
static void put_vperfctr(struct vperfctr *perfctr)
{
- if( atomic_dec_and_test(&perfctr->count) )
+ if (atomic_dec_and_test(&perfctr->count))
vperfctr_free(perfctr);
}
@@ -246,8 +286,6 @@ static void put_vperfctr(struct vperfctr *perfctr)
/* PRE: IS_RUNNING(perfctr)
* Suspend the counters.
- * XXX: When called from switch_to(), perfctr belongs to 'prev'
- * but current is 'next'. Debug messages will refer to 'next'...
*/
static inline void vperfctr_suspend(struct vperfctr *perfctr)
{
@@ -273,40 +311,59 @@ static inline void vperfctr_resume(struct vperfctr *perfctr)
debug_set_smp_id(perfctr);
}
+static inline void vperfctr_resume_with_overflow_check(struct vperfctr *perfctr)
+{
+#ifdef CONFIG_PERFCTR_INTERRUPT_SUPPORT
+ if (perfctr_cpu_has_pending_interrupt(&perfctr->cpu_state)) {
+ vperfctr_handle_overflow(current, perfctr);
+ return;
+ }
+#endif
+ vperfctr_resume(perfctr);
+}
+
/* Sample the counters but do not suspend them. */
static void vperfctr_sample(struct vperfctr *perfctr)
{
- if( IS_RUNNING(perfctr) ) {
+ if (IS_RUNNING(perfctr)) {
debug_check_smp_id(perfctr);
perfctr_cpu_sample(&perfctr->cpu_state);
vperfctr_reset_sampling_timer(perfctr);
}
}
-#if PERFCTR_INTERRUPT_SUPPORT
+#ifdef CONFIG_PERFCTR_INTERRUPT_SUPPORT
/* vperfctr interrupt handler (XXX: add buffering support) */
/* PREEMPT note: called in IRQ context with preemption disabled. */
static void vperfctr_ihandler(unsigned long pc)
{
struct task_struct *tsk = current;
struct vperfctr *perfctr;
- unsigned int pmc_mask;
- siginfo_t si;
perfctr = tsk->thread.perfctr;
- if( !perfctr ) {
+ if (!perfctr) {
printk(KERN_ERR "%s: BUG! pid %d has no vperfctr\n",
__FUNCTION__, tsk->pid);
return;
}
- if( !perfctr_cstatus_has_ictrs(perfctr->cpu_state.cstatus) ) {
+ if (!perfctr_cstatus_has_ictrs(perfctr->cpu_state.cstatus)) {
printk(KERN_ERR "%s: BUG! vperfctr has cstatus %#x (pid %d, comm %s)\n",
__FUNCTION__, perfctr->cpu_state.cstatus, tsk->pid, tsk->comm);
return;
}
vperfctr_suspend(perfctr);
+ vperfctr_handle_overflow(tsk, perfctr);
+}
+
+static void vperfctr_handle_overflow(struct task_struct *tsk,
+ struct vperfctr *perfctr)
+{
+ unsigned int pmc_mask;
+ siginfo_t si;
+ sigset_t old_blocked;
+
pmc_mask = perfctr_cpu_identify_overflow(&perfctr->cpu_state);
- if( !pmc_mask ) {
+ if (!pmc_mask) {
printk(KERN_ERR "%s: BUG! pid %d has unidentifiable overflow source\n",
__FUNCTION__, tsk->pid);
return;
@@ -314,7 +371,7 @@ static void vperfctr_ihandler(unsigned long pc)
/* suspend a-mode and i-mode PMCs, leaving only TSC on */
/* XXX: some people also want to suspend the TSC */
perfctr->iresume_cstatus = perfctr->cpu_state.cstatus;
- if( perfctr_cstatus_has_tsc(perfctr->iresume_cstatus) ) {
+ if (perfctr_cstatus_has_tsc(perfctr->iresume_cstatus)) {
perfctr->cpu_state.cstatus = perfctr_mk_cstatus(1, 0, 0);
vperfctr_resume(perfctr);
} else
@@ -323,8 +380,20 @@ static void vperfctr_ihandler(unsigned long pc)
si.si_errno = 0;
si.si_code = SI_PMC_OVF;
si.si_pmc_ovf_mask = pmc_mask;
- if( !send_sig_info(si.si_signo, &si, tsk) )
+
+ /* deliver signal without waking up the receiver */
+ spin_lock_irq(&task_siglock(tsk));
+ old_blocked = tsk->blocked;
+ sigaddset(&tsk->blocked, si.si_signo);
+ spin_unlock_irq(&task_siglock(tsk));
+
+ if (!send_sig_info(si.si_signo, &si, tsk))
send_sig(si.si_signo, tsk, 1);
+
+ spin_lock_irq(&task_siglock(tsk));
+ tsk->blocked = old_blocked;
+ recalc_sigpending();
+ spin_unlock_irq(&task_siglock(tsk));
}
#endif
@@ -352,7 +421,7 @@ static void vperfctr_unlink(struct task_struct *owner, struct vperfctr *perfctr)
/* perfctr suspend+detach must be atomic wrt process suspend */
/* this also synchronises with perfctr_set_cpus_allowed() */
vperfctr_task_lock(owner);
- if( IS_RUNNING(perfctr) && owner == current )
+ if (IS_RUNNING(perfctr) && owner == current)
vperfctr_suspend(perfctr);
owner->thread.perfctr = NULL;
vperfctr_task_unlock(owner);
@@ -367,13 +436,23 @@ void __vperfctr_exit(struct vperfctr *perfctr)
vperfctr_unlink(current, perfctr);
}
+/* sys_execve() -> .. -> flush_old_exec() -> .. -> __vperfctr_flush().
+ * Unlink the thread's perfctr state, if the CLOEXEC control flag is set.
+ * PREEMPT note: flush_old_exec() does not run with preemption disabled.
+ */
+void __vperfctr_flush(struct vperfctr *perfctr)
+{
+ if (perfctr->flags & VPERFCTR_CONTROL_CLOEXEC)
+ __vperfctr_exit(perfctr);
+}
+
/* schedule() --> switch_to() --> .. --> __vperfctr_suspend().
* If the counters are running, suspend them.
* PREEMPT note: switch_to() runs with preemption disabled.
*/
void __vperfctr_suspend(struct vperfctr *perfctr)
{
- if( IS_RUNNING(perfctr) )
+ if (IS_RUNNING(perfctr))
vperfctr_suspend(perfctr);
}
@@ -384,10 +463,10 @@ void __vperfctr_suspend(struct vperfctr *perfctr)
*/
void __vperfctr_resume(struct vperfctr *perfctr)
{
- if( IS_RUNNING(perfctr) ) {
-#if PERFCTR_CPUS_FORBIDDEN_MASK_NEEDED
- if( unlikely(atomic_read(&perfctr->bad_cpus_allowed)) &&
- perfctr_cstatus_nrctrs(perfctr->cpu_state.cstatus) ) {
+ if (IS_RUNNING(perfctr)) {
+#ifdef CONFIG_PERFCTR_CPUS_FORBIDDEN_MASK
+ if (unlikely(atomic_read(&perfctr->bad_cpus_allowed)) &&
+ perfctr_cstatus_nrctrs(perfctr->cpu_state.cstatus)) {
perfctr->cpu_state.cstatus = 0;
vperfctr_clear_iresume_cstatus(perfctr);
BUG_ON(current->state != TASK_RUNNING);
@@ -395,7 +474,7 @@ void __vperfctr_resume(struct vperfctr *perfctr)
return;
}
#endif
- vperfctr_resume(perfctr);
+ vperfctr_resume_with_overflow_check(perfctr);
}
}
@@ -408,11 +487,11 @@ void __vperfctr_resume(struct vperfctr *perfctr)
*/
void __vperfctr_sample(struct vperfctr *perfctr)
{
- if( --perfctr->sampling_timer == 0 )
+ if (--perfctr->sampling_timer == 0)
vperfctr_sample(perfctr);
}
-#if PERFCTR_CPUS_FORBIDDEN_MASK_NEEDED
+#ifdef CONFIG_PERFCTR_CPUS_FORBIDDEN_MASK
/* Called from set_cpus_allowed().
* PRE: current holds task_lock(owner)
* PRE: owner->thread.perfctr == perfctr
@@ -421,10 +500,7 @@ void __vperfctr_set_cpus_allowed(struct task_struct *owner,
struct vperfctr *perfctr,
cpumask_t new_mask)
{
- cpumask_t tmp;
-
- cpus_and(tmp, new_mask, perfctr_cpus_forbidden_mask);
- if( !cpus_empty(tmp) ) {
+ if (!cpus_subset(new_mask, perfctr->cpumask)) {
atomic_set(&perfctr->bad_cpus_allowed, 1);
printk(KERN_WARNING "perfctr: process %d (comm %s) issued unsafe"
" set_cpus_allowed() on process %d (comm %s)\n",
@@ -452,82 +528,118 @@ static int sys_vperfctr_control(struct vperfctr *perfctr,
int err;
unsigned int next_cstatus;
unsigned int nrctrs, i;
+ cpumask_t cpumask;
- if( !tsk )
+ if (!tsk)
return -ESRCH; /* attempt to update unlinked perfctr */
err = perfctr_copy_from_user(&control, argp, &vperfctr_control_sdesc);
- if( err )
+ if (err)
+ return err;
+
+ /* Step 1: Update the control but keep the counters disabled.
+ PREEMPT note: Preemption is disabled since we're updating
+ an active perfctr. */
+ preempt_disable();
+ if (IS_RUNNING(perfctr)) {
+ if (tsk == current)
+ vperfctr_suspend(perfctr);
+ perfctr->cpu_state.cstatus = 0;
+ vperfctr_clear_iresume_cstatus(perfctr);
+ }
+ perfctr->cpu_state.control = control.cpu_control;
+ /* remote access note: perfctr_cpu_update_control() is ok */
+ cpus_setall(cpumask);
+#ifdef CONFIG_PERFCTR_CPUS_FORBIDDEN_MASK
+ /* make a stopped vperfctr have an unconstrained cpumask */
+ perfctr->cpumask = cpumask;
+#endif
+ err = perfctr_cpu_update_control(&perfctr->cpu_state, &cpumask);
+ if (err < 0) {
+ next_cstatus = 0;
+ } else {
+ next_cstatus = perfctr->cpu_state.cstatus;
+ perfctr->cpu_state.cstatus = 0;
+ perfctr->updater_tgid = current->tgid;
+#ifdef CONFIG_PERFCTR_CPUS_FORBIDDEN_MASK
+ perfctr->cpumask = cpumask;
+#endif
+ }
+ preempt_enable_no_resched();
+
+ if (!perfctr_cstatus_enabled(next_cstatus))
return err;
- if( control.cpu_control.nractrs || control.cpu_control.nrictrs ) {
- cpumask_t tmp, old_mask, new_mask;
+#ifdef CONFIG_PERFCTR_CPUS_FORBIDDEN_MASK
+ /* Step 2: Update the task's CPU affinity mask.
+ PREEMPT note: Preemption must be enabled for set_cpus_allowed(). */
+ if (control.cpu_control.nractrs || control.cpu_control.nrictrs) {
+ cpumask_t old_mask, new_mask;
- tmp = perfctr_cpus_forbidden_mask;
- cpus_complement(tmp);
old_mask = tsk->cpus_allowed;
- cpus_and(new_mask, old_mask, tmp);
+ cpus_and(new_mask, old_mask, cpumask);
- if( cpus_empty(new_mask) )
+ if (cpus_empty(new_mask))
return -EINVAL;
- if( !cpus_equal(new_mask, old_mask) )
+ if (!cpus_equal(new_mask, old_mask))
set_cpus_allowed(tsk, new_mask);
}
+#endif
- /* PREEMPT note: preemption is disabled over the entire
- region since we're updating an active perfctr. */
+ /* Step 3: Enable the counters with the new control and affinity.
+ PREEMPT note: Preemption is disabled since we're updating
+ an active perfctr. */
preempt_disable();
- if( IS_RUNNING(perfctr) ) {
- if( tsk == current )
- vperfctr_suspend(perfctr);
- perfctr->cpu_state.cstatus = 0;
- vperfctr_clear_iresume_cstatus(perfctr);
- }
- perfctr->cpu_state.control = control.cpu_control;
- /* remote access note: perfctr_cpu_update_control() is ok */
- err = perfctr_cpu_update_control(&perfctr->cpu_state, 0);
- if( err < 0 )
- goto out;
- next_cstatus = perfctr->cpu_state.cstatus;
- if( !perfctr_cstatus_enabled(next_cstatus) )
- goto out;
- /* XXX: validate si_signo? */
- perfctr->si_signo = control.si_signo;
+ /* We had to enable preemption above for set_cpus_allowed() so we may
+ have lost a race with a concurrent update via the remote control
+ interface. If so then we must abort our update of this perfctr. */
+ if (perfctr->updater_tgid != current->tgid) {
+ printk(KERN_WARNING "perfctr: control update by task %d"
+ " was lost due to race with update by task %d\n",
+ current->tgid, perfctr->updater_tgid);
+ err = -EBUSY;
+ } else {
+ /* XXX: validate si_signo? */
+ perfctr->si_signo = control.si_signo;
+
+ perfctr->cpu_state.cstatus = next_cstatus;
- if( !perfctr_cstatus_has_tsc(next_cstatus) )
- perfctr->cpu_state.tsc_sum = 0;
+ if (!perfctr_cstatus_has_tsc(next_cstatus))
+ perfctr->cpu_state.tsc_sum = 0;
- nrctrs = perfctr_cstatus_nrctrs(next_cstatus);
- for(i = 0; i < nrctrs; ++i)
- if( !(control.preserve & (1<<i)) )
- perfctr->cpu_state.pmc[i].sum = 0;
+ nrctrs = perfctr_cstatus_nrctrs(next_cstatus);
+ for(i = 0; i < nrctrs; ++i)
+ if (!(control.preserve & (1<<i)))
+ perfctr->cpu_state.pmc[i].sum = 0;
- if( tsk == current )
- vperfctr_resume(perfctr);
+ perfctr->flags = control.flags;
+
+ if (tsk == current)
+ vperfctr_resume(perfctr);
+ }
- out:
preempt_enable();
return err;
}
static int sys_vperfctr_iresume(struct vperfctr *perfctr, const struct task_struct *tsk)
{
-#if PERFCTR_INTERRUPT_SUPPORT
+#ifdef CONFIG_PERFCTR_INTERRUPT_SUPPORT
unsigned int iresume_cstatus;
- if( !tsk )
+ if (!tsk)
return -ESRCH; /* attempt to update unlinked perfctr */
iresume_cstatus = perfctr->iresume_cstatus;
- if( !perfctr_cstatus_has_ictrs(iresume_cstatus) )
+ if (!perfctr_cstatus_has_ictrs(iresume_cstatus))
return -EPERM;
/* PREEMPT note: preemption is disabled over the entire
region because we're updating an active perfctr. */
preempt_disable();
- if( IS_RUNNING(perfctr) && tsk == current )
+ if (IS_RUNNING(perfctr) && tsk == current)
vperfctr_suspend(perfctr);
perfctr->cpu_state.cstatus = iresume_cstatus;
@@ -536,7 +648,7 @@ static int sys_vperfctr_iresume(struct vperfctr *perfctr, const struct task_stru
/* remote access note: perfctr_cpu_ireload() is ok */
perfctr_cpu_ireload(&perfctr->cpu_state);
- if( tsk == current )
+ if (tsk == current)
vperfctr_resume(perfctr);
preempt_enable();
@@ -549,7 +661,7 @@ static int sys_vperfctr_iresume(struct vperfctr *perfctr, const struct task_stru
static int sys_vperfctr_unlink(struct vperfctr *perfctr, struct task_struct *tsk)
{
- if( tsk )
+ if (tsk)
vperfctr_unlink(tsk, perfctr);
return 0;
}
@@ -560,7 +672,7 @@ static int sys_vperfctr_read_sum(struct vperfctr *perfctr,
{
struct perfctr_sum_ctrs sum;
- if( tsk == current ) {
+ if (tsk == current) {
preempt_disable();
vperfctr_sample(perfctr);
}
@@ -571,7 +683,7 @@ static int sys_vperfctr_read_sum(struct vperfctr *perfctr,
for(j = 0; j < ARRAY_SIZE(sum.pmc); ++j)
sum.pmc[j] = perfctr->cpu_state.pmc[j].sum;
}
- if( tsk == current )
+ if (tsk == current)
preempt_enable();
return perfctr_copy_to_user(argp, &sum, &perfctr_sum_ctrs_sdesc);
}
@@ -587,11 +699,12 @@ static int sys_vperfctr_read_control(struct vperfctr *perfctr,
Disable preemption to ensure we get a consistent copy.
Not needed for other cases since the perfctr is either
unlinked or its owner is ptrace ATTACH suspended by us. */
- if( tsk == current )
+ if (tsk == current)
preempt_disable();
control.si_signo = perfctr->si_signo;
control.cpu_control = perfctr->cpu_state.control;
- if( tsk == current )
+ control.flags = perfctr->flags;
+ if (tsk == current)
preempt_enable();
control.preserve = 0;
return perfctr_copy_to_user(argp, &control, &vperfctr_control_sdesc);
@@ -607,36 +720,48 @@ static int vperfctr_mmap(struct file *filp, struct vm_area_struct *vma)
{
struct vperfctr *perfctr;
+#ifdef CONFIG_ARM
+#define _PAGE_RW L_PTE_WRITE
+#endif
/* Only allow read-only mapping of first page. */
- if( (vma->vm_end - vma->vm_start) != PAGE_SIZE ||
+ if ((vma->vm_end - vma->vm_start) != PAGE_SIZE ||
vma->vm_pgoff != 0 ||
(pgprot_val(vma->vm_page_prot) & _PAGE_RW) ||
- (vma->vm_flags & (VM_WRITE | VM_MAYWRITE)) )
+ (vma->vm_flags & (VM_WRITE | VM_MAYWRITE)))
return -EPERM;
perfctr = filp->private_data;
- if( !perfctr )
+ if (!perfctr)
return -EPERM;
- return remap_page_range(vma, vma->vm_start, virt_to_phys(perfctr),
- PAGE_SIZE, vma->vm_page_prot);
+ /* 2.6.29-rc1 changed arch/x86/mm/pat.c to WARN_ON when
+ remap_pfn_range() is applied to plain RAM pages.
+ Comments there indicate that one should set_memory_wc()
+ before the remap, but that doesn't silence the WARN_ON.
+ Luckily vm_insert_page() works without complaints. */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
+ return vm_insert_page(vma, vma->vm_start, virt_to_page((unsigned long)perfctr));
+#else
+ return remap_pfn_range(vma, vma->vm_start,
+ virt_to_phys(perfctr) >> PAGE_SHIFT,
+ PAGE_SIZE, vma->vm_page_prot);
+#endif
}
static int vperfctr_release(struct inode *inode, struct file *filp)
{
struct vperfctr *perfctr = filp->private_data;
filp->private_data = NULL;
- if( perfctr )
+ if (perfctr)
put_vperfctr(perfctr);
return 0;
}
-static int vperfctr_ioctl(struct inode *inode, struct file *filp,
- unsigned int cmd, unsigned long arg)
+static long vperfctr_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
struct vperfctr *perfctr;
struct task_struct *tsk;
int ret;
- switch( cmd ) {
+ switch (cmd) {
case PERFCTR_ABI:
return sys_perfctr_abi((unsigned int*)arg);
case PERFCTR_INFO:
@@ -647,23 +772,23 @@ static int vperfctr_ioctl(struct inode *inode, struct file *filp,
return sys_perfctr_cpus_forbidden((struct perfctr_cpu_mask*)arg);
}
perfctr = filp->private_data;
- if( !perfctr )
+ if (!perfctr)
return -EINVAL;
tsk = current;
- if( perfctr != current->thread.perfctr ) {
+ if (perfctr != current->thread.perfctr) {
/* this synchronises with vperfctr_unlink() and itself */
spin_lock(&perfctr->owner_lock);
tsk = perfctr->owner;
- if( tsk )
+ if (tsk)
get_task_struct(tsk);
spin_unlock(&perfctr->owner_lock);
- if( tsk ) {
+ if (tsk) {
ret = ptrace_check_attach(tsk, 0);
- if( ret < 0 )
+ if (ret < 0)
goto out;
}
}
- switch( cmd ) {
+ switch (cmd) {
case VPERFCTR_CONTROL:
ret = sys_vperfctr_control(perfctr, (struct perfctr_struct_buf*)arg, tsk);
break;
@@ -683,16 +808,36 @@ static int vperfctr_ioctl(struct inode *inode, struct file *filp,
ret = -EINVAL;
}
out:
- if( tsk && tsk != current )
+ if (tsk && tsk != current)
put_task_struct(tsk);
return ret;
}
-static struct file_operations vperfctr_file_ops = {
+#if !HAVE_UNLOCKED_IOCTL
+static int vperfctr_ioctl_oldstyle(struct inode *inode, struct file *filp,
+ unsigned int cmd, unsigned long arg)
+{
+ return vperfctr_ioctl(filp, cmd, arg);
+}
+#endif
+
+static
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
+const
+#endif
+struct file_operations vperfctr_file_ops = {
.owner = THIS_MODULE,
.mmap = vperfctr_mmap,
.release = vperfctr_release,
- .ioctl = vperfctr_ioctl,
+ /* 2.6.11-rc2 introduced HAVE_UNLOCKED_IOCTL and HAVE_COMPAT_IOCTL */
+#if HAVE_UNLOCKED_IOCTL
+ .unlocked_ioctl = vperfctr_ioctl,
+#else
+ .ioctl = vperfctr_ioctl_oldstyle,
+#endif
+#if defined(CONFIG_IA32_EMULATION) && HAVE_COMPAT_IOCTL
+ .compat_ioctl = vperfctr_ioctl,
+#endif
};
/****************************************************************
@@ -703,14 +848,11 @@ static struct file_operations vperfctr_file_ops = {
#define VPERFCTRFS_MAGIC (('V'<<24)|('P'<<16)|('M'<<8)|('C'))
-/* The code to set up a `struct file_system_type' for a pseudo fs
- is unfortunately not the same in 2.4 and 2.6. */
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
-#include <linux/mount.h> /* needed for 2.6, included by fs.h in 2.4 */
+#include <linux/mount.h>
-/* 2.6 doesn't EXPORT_SYMBOL() fs/libfs.c:get_sb_pseudo().
+/* 2.6 kernels prior to 2.6.11-rc1 don't EXPORT_SYMBOL() get_sb_pseudo().
This is a verbatim copy, only renamed. */
-#ifdef MODULE
+#if defined(MODULE) && LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
static
struct super_block *
perfctr_get_sb_pseudo(struct file_system_type *fs_type, char *name,
@@ -756,14 +898,24 @@ Enomem:
}
#undef get_sb_pseudo
#define get_sb_pseudo perfctr_get_sb_pseudo
-#endif /* MODULE */
+#endif /* MODULE && VERSION < 2.6.11 */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18)
+static int
+vperfctrfs_get_sb(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data,
+ struct vfsmount *mnt)
+{
+ return get_sb_pseudo(fs_type, "vperfctr:", NULL, VPERFCTRFS_MAGIC, mnt);
+}
+#else
static struct super_block *
vperfctrfs_get_sb(struct file_system_type *fs_type,
int flags, const char *dev_name, void *data)
{
return get_sb_pseudo(fs_type, "vperfctr:", NULL, VPERFCTRFS_MAGIC);
}
+#endif
static struct file_system_type vperfctrfs_type = {
.name = "vperfctrfs",
@@ -771,69 +923,15 @@ static struct file_system_type vperfctrfs_type = {
.kill_sb = kill_anon_super,
};
-#else /* 2.4 */
-
-static int vperfctrfs_statfs(struct super_block *sb, struct statfs *buf)
-{
- buf->f_type = VPERFCTRFS_MAGIC;
- buf->f_bsize = 1024;
- buf->f_namelen = 255;
- return 0;
-}
-
-static struct super_operations vperfctrfs_ops = {
- .statfs = vperfctrfs_statfs,
-};
-
-static struct super_block*
-vperfctrfs_read_super(struct super_block *sb, void *data, int silent)
-{
- static const struct qstr d_name = { "vperfctrfs:", 11, 0 };
- struct dentry *dentry;
- struct inode *root;
-
- root = new_inode(sb);
- if( !root )
- return NULL;
- root->i_mode = S_IFDIR | S_IRUSR | S_IWUSR;
- root->i_uid = root->i_gid = 0;
- root->i_atime = root->i_mtime = root->i_ctime = CURRENT_TIME;
- sb->s_blocksize = 1024;
- sb->s_blocksize_bits = 10;
- sb->s_magic = VPERFCTRFS_MAGIC;
- sb->s_op = &vperfctrfs_ops; /* XXX: check if 2.4 really needs this */
- sb->s_root = dentry = d_alloc(NULL, &d_name);
- if( !dentry ) {
- iput(root);
- return NULL;
- }
- dentry->d_sb = sb;
- dentry->d_parent = dentry;
- d_instantiate(dentry, root);
- return sb;
-}
-
-/* DECLARE_FSTYPE() hides 'owner: THIS_MODULE'. kern_mount() increments
- owner's use count, and since we're not unmountable from user-space,
- the module can't be unloaded because it's use count is >= 1.
- So we declare the file_system_type manually without the owner field. */
-static struct file_system_type vperfctrfs_type = {
- .name = "vperfctrfs",
- .read_super = vperfctrfs_read_super,
- .fs_flags = FS_NOMOUNT,
-};
-
-#endif /* 2.4 */
-
/* XXX: check if s/vperfctr_mnt/vperfctrfs_type.kern_mnt/ would work */
static struct vfsmount *vperfctr_mnt;
static int __init vperfctrfs_init(void)
{
int err = register_filesystem(&vperfctrfs_type);
- if( !err ) {
+ if (!err) {
vperfctr_mnt = kern_mount(&vperfctrfs_type);
- if( !IS_ERR(vperfctr_mnt) )
+ if (!IS_ERR(vperfctr_mnt))
return 0;
err = PTR_ERR(vperfctr_mnt);
unregister_filesystem(&vperfctrfs_type);
@@ -852,24 +950,41 @@ static struct inode *vperfctr_get_inode(void)
struct inode *inode;
inode = new_inode(vperfctr_mnt->mnt_sb);
- if( !inode )
+ if (!inode)
return NULL;
inode->i_fop = &vperfctr_file_ops;
inode->i_state = I_DIRTY;
inode->i_mode = S_IFCHR | S_IRUSR | S_IWUSR;
- inode->i_uid = current->fsuid;
- inode->i_gid = current->fsgid;
+ inode->i_uid = current_fsuid();
+ inode->i_gid = current_fsgid();
inode->i_atime = inode->i_mtime = inode->i_ctime = CURRENT_TIME;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) && !defined(DONT_HAVE_i_blksize)
inode->i_blksize = 0;
+#endif
return inode;
}
static int vperfctrfs_delete_dentry(struct dentry *dentry)
{
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
+ /*
+ * At creation time, we pretended this dentry was hashed
+ * (by clearing DCACHE_UNHASHED bit in d_flags)
+ * At delete time, we restore the truth : not hashed.
+ * (so that dput() can proceed correctly)
+ */
+ dentry->d_flags |= DCACHE_UNHASHED;
+ return 0;
+#else
return 1;
+#endif
}
-static struct dentry_operations vperfctrfs_dentry_operations = {
+static
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
+const
+#endif
+struct dentry_operations vperfctrfs_dentry_operations = {
.d_delete = vperfctrfs_delete_dentry,
};
@@ -882,11 +997,25 @@ static struct dentry *vperfctr_d_alloc_root(struct inode *inode)
sprintf(name, "[%lu]", inode->i_ino);
this.name = name;
this.len = strlen(name);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
+ this.hash = 0;
+#else
this.hash = inode->i_ino; /* will go */
+#endif
dentry = d_alloc(vperfctr_mnt->mnt_sb->s_root, &this);
- if( dentry ) {
+ if (dentry) {
dentry->d_op = &vperfctrfs_dentry_operations;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
+ /*
+ * We dont want to publish this dentry into global dentry hash table.
+ * We pretend dentry is already hashed, by unsetting DCACHE_UNHASHED
+ * This permits a working /proc/$pid/fd/XXX on vperfctrs
+ */
+ dentry->d_flags &= ~DCACHE_UNHASHED;
+ d_instantiate(dentry, inode);
+#else
d_add(dentry, inode);
+#endif
}
return dentry;
}
@@ -897,18 +1026,25 @@ static struct file *vperfctr_get_filp(void)
struct inode *inode;
struct dentry *dentry;
- filp = get_empty_filp();
- if( !filp )
- goto out;
inode = vperfctr_get_inode();
- if( !inode )
- goto out_filp;
+ if (!inode)
+ goto out;
dentry = vperfctr_d_alloc_root(inode);
- if( !dentry )
+ if (!dentry)
goto out_inode;
+ /*
+ * Create the filp _after_ the inode and dentry, to avoid
+ * needing access to put_filp(), which is no longer exported
+ * starting with kernel 2.6.10-rc1. fput() is available but
+ * doesn't work on incomplete files. We now need access to
+ * dput() instead, but that's Ok.
+ */
+ filp = get_empty_filp();
+ if (!filp)
+ goto out_dentry;
- filp->f_vfsmnt = mntget(vperfctr_mnt);
- filp->f_dentry = dentry;
+ filp_vfsmnt(filp) = mntget(vperfctr_mnt);
+ filp_dentry(filp) = dentry;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,2)
filp->f_mapping = dentry->d_inode->i_mapping;
#endif
@@ -921,10 +1057,11 @@ static struct file *vperfctr_get_filp(void)
return filp;
+ out_dentry:
+ dput(dentry);
+ goto out; /* dput() also does iput() */
out_inode:
iput(inode);
- out_filp:
- put_filp(filp); /* doesn't run ->release() like fput() does */
out:
return NULL;
}
@@ -940,44 +1077,44 @@ int vperfctr_attach(int tid, int creat)
int fd;
filp = vperfctr_get_filp();
- if( !filp )
+ if (!filp)
return -ENOMEM;
err = fd = get_unused_fd();
- if( err < 0 )
+ if (err < 0)
goto err_filp;
perfctr = NULL;
- if( creat ) {
+ if (creat) {
perfctr = get_empty_vperfctr(); /* may sleep */
- if( IS_ERR(perfctr) ) {
+ if (IS_ERR(perfctr)) {
err = PTR_ERR(perfctr);
goto err_fd;
}
}
tsk = current;
- if( tid != 0 && tid != tsk->pid ) { /* remote? */
- read_lock(&tasklist_lock);
- tsk = find_task_by_pid(tid);
- if( tsk )
+ if (tid != 0 && tid != task_pid_vnr(tsk)) { /* remote? */
+ vperfctr_lock_find_task_by_vpid();
+ tsk = find_task_by_vpid(tid);
+ if (tsk)
get_task_struct(tsk);
- read_unlock(&tasklist_lock);
+ vperfctr_unlock_find_task_by_vpid();
err = -ESRCH;
- if( !tsk )
+ if (!tsk)
goto err_perfctr;
err = ptrace_check_attach(tsk, 0);
- if( err < 0 )
+ if (err < 0)
goto err_tsk;
}
- if( creat ) {
+ if (creat) {
/* check+install must be atomic to prevent remote-control races */
vperfctr_task_lock(tsk);
- if( !tsk->thread.perfctr ) {
+ if (!tsk->thread.perfctr) {
perfctr->owner = tsk;
tsk->thread.perfctr = perfctr;
err = 0;
} else
err = -EEXIST;
vperfctr_task_unlock(tsk);
- if( err )
+ if (err)
goto err_tsk;
} else {
perfctr = tsk->thread.perfctr;
@@ -985,17 +1122,17 @@ int vperfctr_attach(int tid, int creat)
Hence no non-NULL check here. */
}
filp->private_data = perfctr;
- if( perfctr )
+ if (perfctr)
atomic_inc(&perfctr->count);
- if( tsk != current )
+ if (tsk != current)
put_task_struct(tsk);
fd_install(fd, filp);
return fd;
err_tsk:
- if( tsk != current )
+ if (tsk != current)
put_task_struct(tsk);
err_perfctr:
- if( perfctr ) /* can only occur if creat != 0 */
+ if (perfctr) /* can only occur if creat != 0 */
put_vperfctr(perfctr);
err_fd:
put_unused_fd(fd);
@@ -1018,10 +1155,11 @@ static void vperfctr_stub_init(void)
off = vperfctr_stub;
vperfctr_stub.owner = THIS_MODULE;
vperfctr_stub.exit = __vperfctr_exit;
+ vperfctr_stub.flush = __vperfctr_flush;
vperfctr_stub.suspend = __vperfctr_suspend;
vperfctr_stub.resume = __vperfctr_resume;
vperfctr_stub.sample = __vperfctr_sample;
-#if PERFCTR_CPUS_FORBIDDEN_MASK_NEEDED
+#ifdef CONFIG_PERFCTR_CPUS_FORBIDDEN_MASK
vperfctr_stub.set_cpus_allowed = __vperfctr_set_cpus_allowed;
#endif
}
@@ -1038,7 +1176,7 @@ static inline void vperfctr_stub_exit(void) { }
int __init vperfctr_init(void)
{
int err = vperfctrfs_init();
- if( err )
+ if (err)
return err;
vperfctr_stub_init();
return 0;
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/virtual.h b/src/perfctr-2.6.x/linux/drivers/perfctr/virtual.h
index 8885be8824df5990e962798a8f2d3d7510e99cdc..27de582552eeaf2db6e03b40cfa16c0cb4909174 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/virtual.h
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/virtual.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: virtual.h,v 1.11 2003/10/04 20:29:43 mikpe Exp $
* Virtual per-process performance counters.
*
* Copyright (C) 1999-2003 Mikael Pettersson
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/virtual_stub.c b/src/perfctr-2.6.x/linux/drivers/perfctr/virtual_stub.c
index 17f62fb680438cbecd2be066d0df0a73a2366b75..5036db590330c95e5eca83180fa7d0a2007ec752 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/virtual_stub.c
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/virtual_stub.c
@@ -1,10 +1,13 @@
-/* $Id$
+/* $Id: virtual_stub.c,v 1.26.2.9 2009/01/23 17:21:20 mikpe Exp $
* Kernel stub used to support virtual perfctrs when the
* perfctr driver is built as a module.
*
- * Copyright (C) 2000-2003 Mikael Pettersson
+ * Copyright (C) 2000-2009 Mikael Pettersson
*/
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
#include <linux/config.h>
+#endif
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
@@ -17,7 +20,7 @@ static void bug_void_perfctr(struct vperfctr *perfctr)
BUG();
}
-#if PERFCTR_CPUS_FORBIDDEN_MASK_NEEDED
+#ifdef CONFIG_PERFCTR_CPUS_FORBIDDEN_MASK
static void bug_set_cpus_allowed(struct task_struct *owner, struct vperfctr *perfctr, cpumask_t new_mask)
{
owner->thread.perfctr = NULL;
@@ -27,10 +30,11 @@ static void bug_set_cpus_allowed(struct task_struct *owner, struct vperfctr *per
struct vperfctr_stub vperfctr_stub = {
.exit = bug_void_perfctr,
+ .flush = bug_void_perfctr,
.suspend = bug_void_perfctr,
.resume = bug_void_perfctr,
.sample = bug_void_perfctr,
-#if PERFCTR_CPUS_FORBIDDEN_MASK_NEEDED
+#ifdef CONFIG_PERFCTR_CPUS_FORBIDDEN_MASK
.set_cpus_allowed = bug_set_cpus_allowed,
#endif
};
@@ -51,7 +55,7 @@ struct vperfctr_stub vperfctr_stub = {
* count before the call, and decrement it again afterwards. Thus,
* the final drop to zero occurs here and not in the module itself.
* (All other code paths that drop the use count do so via a file
- * object, and VFS in 2.4+ kernels also refcount the module.)
+ * object, and VFS also refcounts the module.)
*/
void _vperfctr_exit(struct vperfctr *perfctr)
{
@@ -60,9 +64,21 @@ void _vperfctr_exit(struct vperfctr *perfctr)
module_put(vperfctr_stub.owner);
}
+/* __vperfctr_flush() is a conditional __vperfctr_exit(),
+ * so it needs the same protection.
+ */
+void _vperfctr_flush(struct vperfctr *perfctr)
+{
+ __module_get(vperfctr_stub.owner);
+ vperfctr_stub.flush(perfctr);
+ module_put(vperfctr_stub.owner);
+}
+
EXPORT_SYMBOL(vperfctr_stub);
EXPORT_SYMBOL___put_task_struct;
-#include <linux/mm.h> /* for 2.4.15 and up, except 2.4.20-8-redhat */
-#include <linux/ptrace.h> /* for 2.5.32 and up, and 2.4.20-8-redhat */
+#if !defined(CONFIG_UTRACE)
+#include <linux/mm.h>
+#include <linux/ptrace.h>
EXPORT_SYMBOL(ptrace_check_attach);
+#endif
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/x86.c b/src/perfctr-2.6.x/linux/drivers/perfctr/x86.c
index f19ea18a53d7f8c19f3189820260d7b9092d1c93..9e2692ed5c3a19c1a03171d717320f6424568c64 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/x86.c
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/x86.c
@@ -1,9 +1,12 @@
-/* $Id$
- * x86 performance-monitoring counters driver.
+/* $Id: x86.c,v 1.127.2.70 2010/11/07 19:46:06 mikpe Exp $
+ * x86/x86_64 performance-monitoring counters driver.
*
- * Copyright (C) 1999-2004 Mikael Pettersson
+ * Copyright (C) 1999-2010 Mikael Pettersson
*/
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
#include <linux/config.h>
+#endif
#define __NO_VERSION__
#include <linux/module.h>
#include <linux/init.h>
@@ -13,11 +16,22 @@
#include <asm/msr.h>
#undef MSR_P6_PERFCTR0
+#undef MSR_P6_EVNTSEL0
+#undef MSR_K7_PERFCTR0
+#undef MSR_K7_EVNTSEL0
+#undef MSR_CORE_PERF_FIXED_CTR0
+#undef MSR_CORE_PERF_FIXED_CTR_CTRL
+#undef MSR_CORE_PERF_GLOBAL_CTRL
#undef MSR_IA32_MISC_ENABLE
+#undef MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
+#undef MSR_IA32_DEBUGCTLMSR
#include <asm/fixmap.h>
#include <asm/apic.h>
struct hw_interrupt_type;
#include <asm/hw_irq.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18) && defined(CONFIG_X86_LOCAL_APIC)
+#include <asm/nmi.h>
+#endif
#include "compat.h"
#include "x86_compat.h"
@@ -32,12 +46,19 @@ struct per_cpu_cache { /* roughly a subset of perfctr_cpu_state */
struct {
/* NOTE: these caches have physical indices, not virtual */
unsigned int evntsel[18];
- unsigned int escr[0x3E2-0x3A0];
+ union {
+ unsigned int escr[0x3E2-0x3A0];
+ unsigned int evntsel_high[18];
+ };
unsigned int pebs_enable;
unsigned int pebs_matrix_vert;
} control;
+ unsigned int core2_fixed_ctr_ctrl;
+ unsigned int nhlm_offcore_rsp[2];
} ____cacheline_aligned;
static struct per_cpu_cache per_cpu_cache[NR_CPUS] __cacheline_aligned;
+#define __get_cpu_cache(cpu) (&per_cpu_cache[cpu])
+#define get_cpu_cache() __get_cpu_cache(smp_processor_id())
/* Structure for counter snapshots, as 32-bit values. */
struct perfctr_low_ctrs {
@@ -45,6 +66,19 @@ struct perfctr_low_ctrs {
unsigned int pmc[18];
};
+/* Structures for describing the set of PMU MSRs. */
+struct perfctr_msr_range {
+ unsigned int first_msr;
+ unsigned int nr_msrs;
+};
+
+struct perfctr_pmu_msrs {
+ const struct perfctr_msr_range *perfctrs; /* for {reserve,release}_perfctr_nmi() */
+ const struct perfctr_msr_range *evntsels; /* for {reserve,release}_evntsel_nmi() */
+ const struct perfctr_msr_range *extras;
+ void (*clear_counters)(int init);
+};
+
/* Intel P5, Cyrix 6x86MX/MII/III, Centaur WinChip C6/2/3 */
#define MSR_P5_CESR 0x11
#define MSR_P5_CTR0 0x12 /* .. 0x13 */
@@ -54,19 +88,39 @@ struct perfctr_low_ctrs {
#define C6_CESR_RESERVED (~0x00FF)
/* Intel P6, VIA C3 */
-#define MSR_P6_PERFCTR0 0xC1 /* .. 0xC2 */
-#define MSR_P6_EVNTSEL0 0x186 /* .. 0x187 */
+#define MSR_P6_PERFCTR0 0xC1 /* .. 0xC4 */
+#define MSR_P6_EVNTSEL0 0x186 /* .. 0x189 */
#define P6_EVNTSEL_ENABLE 0x00400000
#define P6_EVNTSEL_INT 0x00100000
#define P6_EVNTSEL_CPL 0x00030000
#define P6_EVNTSEL_RESERVED 0x00280000
#define VC3_EVNTSEL1_RESERVED (~0x1FF)
+/* Intel Core */
+#define MSR_IA32_DEBUGCTLMSR 0x000001D9
+#define MSR_IA32_DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1<<12)
+#define MSR_CORE_PERF_FIXED_CTR0 0x309 /* .. 0x30B */
+#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38D
+#define MSR_CORE_PERF_FIXED_CTR_CTRL_PMIANY 0x00000888
+#define MSR_CORE_PERF_GLOBAL_CTRL 0x38F
+#define CORE2_PMC_FIXED_FLAG (1<<30)
+#define CORE2_PMC_FIXED_MASK 0x3
+
+/* Intel Nehalem */
+#define MSR_OFFCORE_RSP0 0x1A6 /* Westmere has another at 0x1A7 */
+#define OFFCORE_RSP_RESERVED (~0xF7FF)
+
/* AMD K7 */
#define MSR_K7_EVNTSEL0 0xC0010000 /* .. 0xC0010003 */
#define MSR_K7_PERFCTR0 0xC0010004 /* .. 0xC0010007 */
-/* Intel P4, Intel Pentium M */
+/* AMD K8 */
+#define IS_K8_NB_EVENT(EVNTSEL) ((((EVNTSEL) >> 5) & 0x7) == 0x7)
+
+/* AMD Family 10h */
+#define FAM10H_EVNTSEL_HIGH_RESERVED (~0x30F)
+
+/* Intel P4, Intel Pentium M, Intel Core */
#define MSR_IA32_MISC_ENABLE 0x1A0
#define MSR_IA32_MISC_ENABLE_PERF_AVAIL (1<<7) /* read-only status bit */
#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12) /* read-only status bit */
@@ -129,7 +183,7 @@ static inline void clear_in_cr4_local(unsigned int mask)
static unsigned int new_id(void)
{
- static spinlock_t lock = SPIN_LOCK_UNLOCKED;
+ static DEFINE_SPINLOCK(lock);
static unsigned int counter;
int id;
@@ -139,40 +193,50 @@ static unsigned int new_id(void)
return id;
}
-#if !defined(PERFCTR_INTERRUPT_SUPPORT)
+#if defined(CONFIG_X86_LOCAL_APIC)
+
+static inline void perfctr_cpu_mask_interrupts(const struct per_cpu_cache *cache)
+{
+ __perfctr_cpu_mask_interrupts();
+}
+
+static inline void perfctr_cpu_unmask_interrupts(const struct per_cpu_cache *cache)
+{
+ __perfctr_cpu_unmask_interrupts();
+}
+
+#else /* CONFIG_X86_LOCAL_APIC */
#define perfctr_cstatus_has_ictrs(cstatus) 0
#undef cpu_has_apic
#define cpu_has_apic 0
#undef apic_write
#define apic_write(reg,vector) do{}while(0)
-#endif
+#endif /* CONFIG_X86_LOCAL_APIC */
-#if defined(CONFIG_SMP) && PERFCTR_INTERRUPT_SUPPORT
+#if defined(CONFIG_SMP)
-static inline void set_isuspend_cpu(struct perfctr_cpu_state *state,
- const struct per_cpu_cache *cache)
+static inline void
+set_isuspend_cpu(struct perfctr_cpu_state *state, int cpu)
{
- state->k1.isuspend_cpu = cache;
+ state->k1.isuspend_cpu = cpu;
}
-static inline int is_isuspend_cpu(const struct perfctr_cpu_state *state,
- const struct per_cpu_cache *cache)
+static inline int
+is_isuspend_cpu(const struct perfctr_cpu_state *state, int cpu)
{
- return state->k1.isuspend_cpu == cache;
+ return state->k1.isuspend_cpu == cpu;
}
static inline void clear_isuspend_cpu(struct perfctr_cpu_state *state)
{
- state->k1.isuspend_cpu = NULL;
+ state->k1.isuspend_cpu = NR_CPUS;
}
-#else
-static inline void set_isuspend_cpu(struct perfctr_cpu_state *state,
- const struct per_cpu_cache *cache) { }
-static inline int is_isuspend_cpu(const struct perfctr_cpu_state *state,
- const struct per_cpu_cache *cache) { return 1; }
+#else /* CONFIG_SMP */
+static inline void set_isuspend_cpu(struct perfctr_cpu_state *state, int cpu) { }
+static inline int is_isuspend_cpu(const struct perfctr_cpu_state *state, int cpu) { return 1; }
static inline void clear_isuspend_cpu(struct perfctr_cpu_state *state) { }
-#endif
+#endif /* CONFIG_SMP */
/****************************************************************
* *
@@ -203,21 +267,21 @@ static int p5_like_check_control(struct perfctr_cpu_state *state,
unsigned short cesr_half[2];
unsigned int pmc, evntsel, i;
- if( state->control.nrictrs != 0 || state->control.nractrs > 2 )
+ if (state->control.nrictrs != 0 || state->control.nractrs > 2)
return -EINVAL;
cesr_half[0] = 0;
cesr_half[1] = 0;
for(i = 0; i < state->control.nractrs; ++i) {
pmc = state->control.pmc_map[i];
state->pmc[i].map = pmc;
- if( pmc > 1 || cesr_half[pmc] != 0 )
+ if (pmc > 1 || cesr_half[pmc] != 0)
return -EINVAL;
evntsel = state->control.evntsel[i];
/* protect reserved bits */
- if( (evntsel & reserved_bits) != 0 )
+ if ((evntsel & reserved_bits) != 0)
return -EPERM;
/* the CPL field (if defined) must be non-zero */
- if( !is_c6 && !(evntsel & P5_CESR_CPL) )
+ if (!is_c6 && !(evntsel & P5_CESR_CPL))
return -EINVAL;
cesr_half[pmc] = evntsel;
}
@@ -225,7 +289,7 @@ static int p5_like_check_control(struct perfctr_cpu_state *state,
return 0;
}
-static int p5_check_control(struct perfctr_cpu_state *state, int is_global)
+static int p5_check_control(struct perfctr_cpu_state *state, cpumask_t *cpumask)
{
return p5_like_check_control(state, P5_CESR_RESERVED, 0);
}
@@ -237,10 +301,10 @@ static void p5_write_control(const struct perfctr_cpu_state *state)
unsigned int cesr;
cesr = state->k1.id;
- if( !cesr ) /* no PMC is on (this test doesn't work on C6) */
+ if (!cesr) /* no PMC is on (this test doesn't work on C6) */
return;
- cache = &per_cpu_cache[smp_processor_id()];
- if( cache->k1.p5_cesr != cesr ) {
+ cache = get_cpu_cache();
+ if (cache->k1.p5_cesr != cesr) {
cache->k1.p5_cesr = cesr;
wrmsr(MSR_P5_CESR, cesr, 0);
}
@@ -257,7 +321,7 @@ static void p5_read_counters(const struct perfctr_cpu_state *state,
asm("" : : "r"(ctrs->tsc));
cstatus = state->cstatus;
- if( perfctr_cstatus_has_tsc(cstatus) )
+ if (perfctr_cstatus_has_tsc(cstatus))
rdtscl(ctrs->tsc);
nrctrs = perfctr_cstatus_nractrs(cstatus);
for(i = 0; i < nrctrs; ++i) {
@@ -273,7 +337,7 @@ static void rdpmc_read_counters(const struct perfctr_cpu_state *state,
unsigned int cstatus, nrctrs, i;
cstatus = state->cstatus;
- if( perfctr_cstatus_has_tsc(cstatus) )
+ if (perfctr_cstatus_has_tsc(cstatus))
rdtscl(ctrs->tsc);
nrctrs = perfctr_cstatus_nractrs(cstatus);
for(i = 0; i < nrctrs; ++i) {
@@ -283,10 +347,14 @@ static void rdpmc_read_counters(const struct perfctr_cpu_state *state,
}
/* shared with MII and C6 */
-static void p5_clear_counters(void)
-{
- clear_msr_range(MSR_P5_CESR, 1+2);
-}
+static const struct perfctr_msr_range p5_extras[] = {
+ { MSR_P5_CESR, 1+2 },
+ { 0, 0 },
+};
+
+static const struct perfctr_pmu_msrs p5_pmu_msrs = {
+ .extras = p5_extras,
+};
/*
* Cyrix 6x86/MII/III.
@@ -298,7 +366,7 @@ static void p5_clear_counters(void)
* (and CESR bit 26 for PMC1).
*/
-static int mii_check_control(struct perfctr_cpu_state *state, int is_global)
+static int mii_check_control(struct perfctr_cpu_state *state, cpumask_t *cpumask)
{
return p5_like_check_control(state, MII_CESR_RESERVED, 0);
}
@@ -324,9 +392,9 @@ static int mii_check_control(struct perfctr_cpu_state *state, int is_global)
*/
#if !defined(CONFIG_X86_TSC)
-static int c6_check_control(struct perfctr_cpu_state *state, int is_global)
+static int c6_check_control(struct perfctr_cpu_state *state, cpumask_t *cpumask)
{
- if( state->control.tsc_on )
+ if (state->control.tsc_on)
return -EINVAL;
return p5_like_check_control(state, C6_CESR_RESERVED, 1);
}
@@ -336,116 +404,167 @@ static void c6_write_control(const struct perfctr_cpu_state *state)
struct per_cpu_cache *cache;
unsigned int cesr;
- if( perfctr_cstatus_nractrs(state->cstatus) == 0 ) /* no PMC is on */
+ if (perfctr_cstatus_nractrs(state->cstatus) == 0) /* no PMC is on */
return;
- cache = &per_cpu_cache[smp_processor_id()];
+ cache = get_cpu_cache();
cesr = state->k1.id;
- if( cache->k1.p5_cesr != cesr ) {
+ if (cache->k1.p5_cesr != cesr) {
cache->k1.p5_cesr = cesr;
wrmsr(MSR_P5_CESR, cesr, 0);
}
}
-#endif
+#endif /* !CONFIG_X86_TSC */
/*
- * Intel P6 family (Pentium Pro, Pentium II, and Pentium III cores,
- * and Xeon and Celeron versions of Pentium II and III cores).
+ * Intel P6 family (Pentium Pro, Pentium II, Pentium III, Pentium M,
+ * Intel Core, Intel Core 2, Atom, and Core i7, including Xeon and Celeron versions.
* - One TSC and two 40-bit PMCs.
+ * Core i7 has four 48-bit PMCs.
* - One 32-bit EVNTSEL MSR for each PMC.
* - EVNTSEL0 contains a global enable/disable bit.
* That bit is reserved in EVNTSEL1.
+ * On Core 2, Atom, and Core i7 each EVNTSEL has its own enable/disable bit.
* - Each EVNTSEL contains a CPL field.
* - Overflow interrupts are possible, but requires that the
* local APIC is available. Some Mobile P6s have no local APIC.
* - The PMCs cannot be initialised with arbitrary values, since
* wrmsr fills the high bits by sign-extending from bit 31.
* - Most events are symmetric, but a few are not.
+ * - Core 2 adds three fixed-function counters. A single shared control
+ * register has the control bits (CPL:2 + PMI:1) for these counters.
+ * - Initial Atoms appear to have one fixed-function counter.
*/
+static int is_fam10h;
+static int amd_is_multicore; /* northbridge events need special care */
+static int amd_is_k8_mc_RevE;
+static cpumask_t amd_mc_core0_mask; /* only these may use NB events */
+static int p6_has_separate_enables; /* affects EVNTSEL.ENable rules */
+static unsigned int p6_nr_pmcs; /* number of general-purpose counters */
+static unsigned int p6_nr_ffcs; /* number of fixed-function counters */
+static unsigned int nhlm_nr_offcore_rsps; /* number of OFFCORE_RSP MSRs */
+
/* shared with K7 */
-static int p6_like_check_control(struct perfctr_cpu_state *state, int is_k7)
+static int p6_like_check_control(struct perfctr_cpu_state *state, int is_k7, cpumask_t *cpumask)
{
unsigned int evntsel, i, nractrs, nrctrs, pmc_mask, pmc;
+ unsigned int core2_fixed_ctr_ctrl;
+ unsigned int max_nrctrs;
+ unsigned int amd_mc_nb_event_seen;
+
+ max_nrctrs = is_k7 ? 4 : p6_nr_pmcs + p6_nr_ffcs;
nractrs = state->control.nractrs;
nrctrs = nractrs + state->control.nrictrs;
- if( nrctrs < nractrs || nrctrs > (is_k7 ? 4 : 2) )
+ if (nrctrs < nractrs || nrctrs > max_nrctrs)
return -EINVAL;
pmc_mask = 0;
+ core2_fixed_ctr_ctrl = 0; /* must be zero on CPUs != Core 2 */
+ amd_mc_nb_event_seen = 0;
for(i = 0; i < nrctrs; ++i) {
pmc = state->control.pmc_map[i];
state->pmc[i].map = pmc;
- if( pmc >= (is_k7 ? 4 : 2) || (pmc_mask & (1<<pmc)) )
+ /* pmc_map[i] is what we pass to RDPMC
+ * to check that pmc_map[] is well-defined on Core 2,
+ * we map FIXED_CTR 0x40000000+N to PMC p6_nr_pmcs+N
+ */
+ if (!is_k7 && p6_nr_ffcs != 0) {
+ if (pmc & CORE2_PMC_FIXED_FLAG)
+ pmc = p6_nr_pmcs + (pmc & ~CORE2_PMC_FIXED_FLAG);
+ else if (pmc >= p6_nr_pmcs)
+ return -EINVAL;
+ }
+ if (pmc >= max_nrctrs || (pmc_mask & (1<<pmc)))
return -EINVAL;
pmc_mask |= (1<<pmc);
+ /*
+ * check evntsel_high on AMD Fam10h
+ * on others we force it to zero (should return -EINVAL but
+ * having zeroes there has not been a requirement before)
+ */
+ if (is_fam10h) {
+ unsigned int evntsel_high = state->control.evntsel_high[i];
+ if (evntsel_high & FAM10H_EVNTSEL_HIGH_RESERVED)
+ return -EINVAL;
+ } else
+ state->control.evntsel_high[i] = 0;
+ /* check evntsel */
evntsel = state->control.evntsel[i];
+ /* handle per-thread counting of AMD multicore northbridge events */
+ if (cpumask != NULL && amd_is_multicore && IS_K8_NB_EVENT(evntsel)) {
+ /* K8 RevE NB event erratum is incompatible with per-thread counters */
+ if (amd_is_k8_mc_RevE)
+ return -EPERM;
+ /* remember to restrict this session to amd_mc_core0_mask */
+ amd_mc_nb_event_seen = 1;
+ }
/* protect reserved bits */
- if( evntsel & P6_EVNTSEL_RESERVED )
+ if (evntsel & P6_EVNTSEL_RESERVED)
return -EPERM;
/* check ENable bit */
- if( is_k7 ) {
+ if (is_k7 || p6_has_separate_enables) {
/* ENable bit must be set in each evntsel */
- if( !(evntsel & P6_EVNTSEL_ENABLE) )
+ if (!(evntsel & P6_EVNTSEL_ENABLE))
return -EINVAL;
} else {
/* only evntsel[0] has the ENable bit */
- if( evntsel & P6_EVNTSEL_ENABLE ) {
- if( pmc > 0 )
+ if (evntsel & P6_EVNTSEL_ENABLE) {
+ if (pmc > 0)
return -EPERM;
} else {
- if( pmc == 0 )
+ if (pmc == 0)
return -EINVAL;
}
}
/* the CPL field must be non-zero */
- if( !(evntsel & P6_EVNTSEL_CPL) )
+ if (!(evntsel & P6_EVNTSEL_CPL))
return -EINVAL;
/* INT bit must be off for a-mode and on for i-mode counters */
- if( evntsel & P6_EVNTSEL_INT ) {
- if( i < nractrs )
+ if (evntsel & P6_EVNTSEL_INT) {
+ if (i < nractrs)
return -EINVAL;
} else {
- if( i >= nractrs )
+ if (i >= nractrs)
return -EINVAL;
}
+ if (!is_k7 && p6_nr_ffcs != 0) {
+ pmc = state->control.pmc_map[i];
+ if (pmc & CORE2_PMC_FIXED_FLAG) {
+ unsigned int ctl = 0;
+ ctl |= ((evntsel >> 17) & 1) << 0; /* CPL.OS */
+ ctl |= ((evntsel >> 16) & 1) << 1; /* CPL.USR */
+ ctl |= ((evntsel >> 20) & 1) << 3; /* INT/PMI */
+ core2_fixed_ctr_ctrl |= ctl << (pmc & CORE2_PMC_FIXED_MASK) * 4;
+ }
+ }
+ }
+ /*
+ * check offcore_rsp[] on Intel Nehalem
+ * on others we force it to zero (should return -EINVAL but
+ * having zeroes there has not been a requirement before)
+ */
+ for (i = 0; i < 2; ++i) {
+ if (i < nhlm_nr_offcore_rsps) {
+ unsigned int offcore_rsp = state->control.nhlm.offcore_rsp[i];
+ if (offcore_rsp & OFFCORE_RSP_RESERVED)
+ return -EINVAL;
+ } else
+ state->control.nhlm.offcore_rsp[i] = 0;
}
+ state->core2_fixed_ctr_ctrl = core2_fixed_ctr_ctrl;
state->k1.id = new_id();
+ if (amd_mc_nb_event_seen)
+ *cpumask = amd_mc_core0_mask;
return 0;
}
-static int p6_check_control(struct perfctr_cpu_state *state, int is_global)
+static int p6_check_control(struct perfctr_cpu_state *state, cpumask_t *cpumask)
{
- return p6_like_check_control(state, 0);
+ return p6_like_check_control(state, 0, cpumask);
}
-/* XXX: disabled: called from switch_to() where printk() is disallowed */
-#if 0 && defined(CONFIG_PERFCTR_DEBUG)
-static void debug_evntsel_cache(const struct perfctr_cpu_state *state,
- const struct per_cpu_cache *cache)
-{
- unsigned int nrctrs, i;
-
- nrctrs = perfctr_cstatus_nrctrs(state->cstatus);
- for(i = 0; i < nrctrs; ++i) {
- unsigned int evntsel = state->control.evntsel[i];
- unsigned int pmc = state->control.pmc_map[i];
- if( evntsel != cache->control.evntsel[pmc] ) {
- printk(KERN_ERR "perfctr/x86.c: (pid %d, comm %s) "
- "evntsel[%u] is %#x, should be %#x\n",
- current->pid, current->comm,
- i, cache->control.evntsel[pmc], evntsel);
- return;
- }
- }
-}
-#else
-static inline void debug_evntsel_cache(const struct perfctr_cpu_state *s,
- const struct per_cpu_cache *c)
-{ }
-#endif
-
-#if PERFCTR_INTERRUPT_SUPPORT
+#ifdef CONFIG_X86_LOCAL_APIC
/* PRE: perfctr_cstatus_has_ictrs(state->cstatus) != 0 */
/* shared with K7 and P4 */
static void p6_like_isuspend(struct perfctr_cpu_state *state,
@@ -453,26 +572,40 @@ static void p6_like_isuspend(struct perfctr_cpu_state *state,
{
struct per_cpu_cache *cache;
unsigned int cstatus, nrctrs, i;
+ int cpu;
+ unsigned int pending = 0;
- cache = &per_cpu_cache[smp_processor_id()];
+ cpu = smp_processor_id();
+ set_isuspend_cpu(state, cpu); /* early to limit cpu's live range */
+ cache = __get_cpu_cache(cpu);
+ perfctr_cpu_mask_interrupts(cache);
cstatus = state->cstatus;
nrctrs = perfctr_cstatus_nrctrs(cstatus);
+ if (state->core2_fixed_ctr_ctrl & MSR_CORE_PERF_FIXED_CTR_CTRL_PMIANY) {
+ cache->core2_fixed_ctr_ctrl = 0;
+ wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, 0, 0);
+ }
for(i = perfctr_cstatus_nractrs(cstatus); i < nrctrs; ++i) {
unsigned int pmc_raw, pmc_idx, now;
pmc_raw = state->pmc[i].map;
- /* Note: P4_MASK_FAST_RDPMC is a no-op for P6 and K7.
- We don't need to make it into a parameter. */
- pmc_idx = pmc_raw & P4_MASK_FAST_RDPMC;
- cache->control.evntsel[pmc_idx] = 0;
- /* On P4 this intensionally also clears the CCCR.OVF flag. */
- wrmsr(msr_evntsel0+pmc_idx, 0, 0);
+ if (!(pmc_raw & CORE2_PMC_FIXED_FLAG)) {
+ /* Note: P4_MASK_FAST_RDPMC is a no-op for P6 and K7.
+ We don't need to make it into a parameter. */
+ pmc_idx = pmc_raw & P4_MASK_FAST_RDPMC;
+ cache->control.evntsel[pmc_idx] = 0;
+ cache->control.evntsel_high[pmc_idx] = 0;
+ /* On P4 this intensionally also clears the CCCR.OVF flag. */
+ wrmsr(msr_evntsel0+pmc_idx, 0, 0);
+ }
/* P4 erratum N17 does not apply since we read only low 32 bits. */
rdpmc_low(pmc_raw, now);
state->pmc[i].sum += now - state->pmc[i].start;
state->pmc[i].start = now;
+ if ((int)now >= 0)
+ ++pending;
}
+ state->pending_interrupt = pending;
/* cache->k1.id is still == state->k1.id */
- set_isuspend_cpu(state, cache);
}
/* PRE: perfctr_cstatus_has_ictrs(state->cstatus) != 0 */
@@ -483,28 +616,54 @@ static void p6_like_iresume(const struct perfctr_cpu_state *state,
{
struct per_cpu_cache *cache;
unsigned int cstatus, nrctrs, i;
+ int cpu;
- cache = &per_cpu_cache[smp_processor_id()];
- if( cache->k1.id == state->k1.id ) {
+ cpu = smp_processor_id();
+ cache = __get_cpu_cache(cpu);
+ perfctr_cpu_unmask_interrupts(cache);
+ if (cache->k1.id == state->k1.id) {
cache->k1.id = 0; /* force reload of cleared EVNTSELs */
- if( is_isuspend_cpu(state, cache) )
+ if (is_isuspend_cpu(state, cpu))
return; /* skip reload of PERFCTRs */
}
cstatus = state->cstatus;
nrctrs = perfctr_cstatus_nrctrs(cstatus);
+ /* If the control wasn't ours we must disable the
+ counters before reinitialising them. */
+ if ((state->core2_fixed_ctr_ctrl & MSR_CORE_PERF_FIXED_CTR_CTRL_PMIANY) &&
+ cache->core2_fixed_ctr_ctrl != 0) {
+ cache->core2_fixed_ctr_ctrl = 0;
+ wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, 0, 0);
+ }
for(i = perfctr_cstatus_nractrs(cstatus); i < nrctrs; ++i) {
- /* Note: P4_MASK_FAST_RDPMC is a no-op for P6 and K7.
- We don't need to make it into a parameter. */
- unsigned int pmc = state->pmc[i].map & P4_MASK_FAST_RDPMC;
- /* If the control wasn't ours we must disable the evntsels
- before reinitialising the counters, to prevent unexpected
- counter increments and missed overflow interrupts. */
- if( cache->control.evntsel[pmc] ) {
- cache->control.evntsel[pmc] = 0;
- wrmsr(msr_evntsel0+pmc, 0, 0);
+ unsigned int pmc_raw = state->pmc[i].map;
+ unsigned int msr_perfctr;
+ unsigned int pmc_value_hi;
+
+ if (pmc_raw & CORE2_PMC_FIXED_FLAG) {
+ msr_perfctr = MSR_CORE_PERF_FIXED_CTR0 + (pmc_raw & CORE2_PMC_FIXED_MASK);
+ /* Limit the value written to a fixed-function counter's MSR
+ * to 40 bits. Extraneous high bits cause GP faults on Model 23
+ * Core2s, while earlier processors would just ignore them.
+ */
+ pmc_value_hi = 0xff;
+ } else {
+ /* Note: P4_MASK_FAST_RDPMC is a no-op for P6 and K7.
+ We don't need to make it into a parameter. */
+ unsigned int pmc_idx = pmc_raw & P4_MASK_FAST_RDPMC;
+ /* If the control wasn't ours we must disable the evntsels
+ before reinitialising the counters, to prevent unexpected
+ counter increments and missed overflow interrupts. */
+ if (cache->control.evntsel[pmc_idx]) {
+ cache->control.evntsel[pmc_idx] = 0;
+ cache->control.evntsel_high[pmc_idx] = 0;
+ wrmsr(msr_evntsel0+pmc_idx, 0, 0);
+ }
+ msr_perfctr = msr_perfctr0 + pmc_idx;
+ pmc_value_hi = -1;
}
/* P4 erratum N15 does not apply since the CCCR is disabled. */
- wrmsr(msr_perfctr0+pmc, state->pmc[i].start, -1);
+ wrmsr(msr_perfctr, state->pmc[i].start, pmc_value_hi);
}
/* cache->k1.id remains != state->k1.id */
}
@@ -518,7 +677,7 @@ static void p6_iresume(const struct perfctr_cpu_state *state)
{
p6_like_iresume(state, MSR_P6_EVNTSEL0, MSR_P6_PERFCTR0);
}
-#endif /* PERFCTR_INTERRUPT_SUPPORT */
+#endif /* CONFIG_X86_LOCAL_APIC */
/* shared with K7 and VC3 */
static void p6_like_write_control(const struct perfctr_cpu_state *state,
@@ -527,18 +686,37 @@ static void p6_like_write_control(const struct perfctr_cpu_state *state,
struct per_cpu_cache *cache;
unsigned int nrctrs, i;
- cache = &per_cpu_cache[smp_processor_id()];
- if( cache->k1.id == state->k1.id ) {
- debug_evntsel_cache(state, cache);
+ cache = get_cpu_cache();
+ if (cache->k1.id == state->k1.id)
return;
- }
nrctrs = perfctr_cstatus_nrctrs(state->cstatus);
for(i = 0; i < nrctrs; ++i) {
- unsigned int evntsel = state->control.evntsel[i];
- unsigned int pmc = state->pmc[i].map;
- if( evntsel != cache->control.evntsel[pmc] ) {
+ unsigned int pmc, evntsel, evntsel_high;
+
+ pmc = state->pmc[i].map;
+ if (pmc & CORE2_PMC_FIXED_FLAG)
+ continue;
+ evntsel = state->control.evntsel[i];
+ evntsel_high = state->control.evntsel_high[i];
+ if (evntsel != cache->control.evntsel[pmc] ||
+ evntsel_high != cache->control.evntsel_high[pmc]) {
cache->control.evntsel[pmc] = evntsel;
- wrmsr(msr_evntsel0+pmc, evntsel, 0);
+ cache->control.evntsel_high[pmc] = evntsel_high;
+ wrmsr(msr_evntsel0+pmc, evntsel, evntsel_high);
+ }
+ }
+ if (state->core2_fixed_ctr_ctrl != 0 &&
+ state->core2_fixed_ctr_ctrl != cache->core2_fixed_ctr_ctrl) {
+ cache->core2_fixed_ctr_ctrl = state->core2_fixed_ctr_ctrl;
+ wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, state->core2_fixed_ctr_ctrl, 0);
+ }
+ for (i = 0; i < 2; ++i) {
+ unsigned int offcore_rsp;
+
+ offcore_rsp = state->control.nhlm.offcore_rsp[i];
+ if (offcore_rsp != cache->nhlm_offcore_rsp[i]) {
+ cache->nhlm_offcore_rsp[i] = offcore_rsp;
+ wrmsr(MSR_OFFCORE_RSP0+i, offcore_rsp, 0);
}
}
cache->k1.id = state->k1.id;
@@ -550,12 +728,46 @@ static void p6_write_control(const struct perfctr_cpu_state *state)
p6_like_write_control(state, MSR_P6_EVNTSEL0);
}
-static void p6_clear_counters(void)
+static struct perfctr_msr_range p6_perfctrs[] = {
+ { MSR_P6_PERFCTR0, 2 }, /* on Core i7 we'll update this count */
+ { 0, 0 },
+};
+
+static struct perfctr_msr_range p6_evntsels[] = {
+ { MSR_P6_EVNTSEL0, 2 }, /* on Core i7 we'll update this count */
+ { 0, 0 },
+};
+
+static const struct perfctr_pmu_msrs p6_pmu_msrs = {
+ .perfctrs = p6_perfctrs,
+ .evntsels = p6_evntsels,
+};
+
+static struct perfctr_msr_range core2_extras[] = {
+ { MSR_CORE_PERF_FIXED_CTR0, 3 }, /* on Atom we'll update this count */
+ { MSR_CORE_PERF_FIXED_CTR_CTRL, 1 },
+ { MSR_OFFCORE_RSP0, 0 }, /* on Nehalem we'll update this count */
+ { 0, 0 },
+};
+
+static void core2_clear_counters(int init)
{
- clear_msr_range(MSR_P6_EVNTSEL0, 2);
- clear_msr_range(MSR_P6_PERFCTR0, 2);
+ if (init) {
+ unsigned int low, high;
+ rdmsr(MSR_IA32_DEBUGCTLMSR, low, high);
+ low &= ~MSR_IA32_DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI;
+ wrmsr(MSR_IA32_DEBUGCTLMSR, low, high);
+ wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, (1 << p6_nr_pmcs) - 1, (1 << p6_nr_ffcs) - 1);
+ }
}
+static const struct perfctr_pmu_msrs core2_pmu_msrs = {
+ .perfctrs = p6_perfctrs,
+ .evntsels = p6_evntsels,
+ .extras = core2_extras,
+ .clear_counters = core2_clear_counters,
+};
+
/*
* AMD K7 family (Athlon, Duron).
* - Somewhat similar to the Intel P6 family.
@@ -566,17 +778,22 @@ static void p6_clear_counters(void)
* - The events appear to be completely symmetric.
* - The EVNTSEL MSRs are symmetric since each has its own enable bit.
* - Publicly available documentation is incomplete.
+ * - K7 model 1 does not have a local APIC. AMD Document #22007
+ * Revision J hints that it may use debug interrupts instead.
*
* The K8 has the same hardware layout as the K7. It also has
* better documentation and a different set of available events.
+ *
+ * AMD Family 10h is similar to the K7, but the EVNTSEL MSRs
+ * have been widened to 64 bits.
*/
-static int k7_check_control(struct perfctr_cpu_state *state, int is_global)
+static int k7_check_control(struct perfctr_cpu_state *state, cpumask_t *cpumask)
{
- return p6_like_check_control(state, 1);
+ return p6_like_check_control(state, 1, cpumask);
}
-#if PERFCTR_INTERRUPT_SUPPORT
+#ifdef CONFIG_X86_LOCAL_APIC
static void k7_isuspend(struct perfctr_cpu_state *state)
{
p6_like_isuspend(state, MSR_K7_EVNTSEL0);
@@ -586,17 +803,27 @@ static void k7_iresume(const struct perfctr_cpu_state *state)
{
p6_like_iresume(state, MSR_K7_EVNTSEL0, MSR_K7_PERFCTR0);
}
-#endif /* PERFCTR_INTERRUPT_SUPPORT */
+#endif /* CONFIG_X86_LOCAL_APIC */
static void k7_write_control(const struct perfctr_cpu_state *state)
{
p6_like_write_control(state, MSR_K7_EVNTSEL0);
}
-static void k7_clear_counters(void)
-{
- clear_msr_range(MSR_K7_EVNTSEL0, 4+4);
-}
+static const struct perfctr_msr_range k7_perfctrs[] = {
+ { MSR_K7_PERFCTR0, 4 },
+ { 0, 0 },
+};
+
+static const struct perfctr_msr_range k7_evntsels[] = {
+ { MSR_K7_EVNTSEL0, 4 },
+ { 0, 0 },
+};
+
+static const struct perfctr_pmu_msrs k7_pmu_msrs = {
+ .perfctrs = k7_perfctrs,
+ .evntsels = k7_evntsels,
+};
/*
* VIA C3 family.
@@ -611,15 +838,15 @@ static void k7_clear_counters(void)
* - No local APIC or interrupt-mode support.
* - pmc_map[0] must be 1, if nractrs == 1.
*/
-static int vc3_check_control(struct perfctr_cpu_state *state, int is_global)
+static int vc3_check_control(struct perfctr_cpu_state *state, cpumask_t *cpumask)
{
- if( state->control.nrictrs || state->control.nractrs > 1 )
+ if (state->control.nrictrs || state->control.nractrs > 1)
return -EINVAL;
- if( state->control.nractrs == 1 ) {
- if( state->control.pmc_map[0] != 1 )
+ if (state->control.nractrs == 1) {
+ if (state->control.pmc_map[0] != 1)
return -EINVAL;
state->pmc[0].map = 1;
- if( state->control.evntsel[0] & VC3_EVNTSEL1_RESERVED )
+ if (state->control.evntsel[0] & VC3_EVNTSEL1_RESERVED)
return -EPERM;
state->k1.id = state->control.evntsel[0];
} else
@@ -627,12 +854,16 @@ static int vc3_check_control(struct perfctr_cpu_state *state, int is_global)
return 0;
}
-static void vc3_clear_counters(void)
+static void vc3_clear_counters(int init)
{
/* Not documented, but seems to be default after boot. */
wrmsr(MSR_P6_EVNTSEL0+1, 0x00070079, 0);
}
+static const struct perfctr_pmu_msrs vc3_pmu_msrs = {
+ .clear_counters = vc3_clear_counters,
+};
+
/*
* Intel Pentium 4.
* Current implementation restrictions:
@@ -713,27 +944,28 @@ static unsigned int p4_escr_addr(unsigned int pmc, unsigned int cccr_val)
unsigned int escr_select, pair, escr_offset;
escr_select = P4_CCCR_ESCR_SELECT(cccr_val);
- if( pmc > 0x11 )
+ if (pmc > 0x11)
return 0; /* pmc range error */
- if( pmc > 0x0F )
+ if (pmc > 0x0F)
pmc -= 3; /* 0 <= pmc <= 0x0F */
pair = pmc / 2; /* 0 <= pair <= 7 */
escr_offset = p4_cccr_escr_map[pair / 2][escr_select];
- if( !escr_offset || (pair == 7 && escr_select == 3) )
+ if (!escr_offset || (pair == 7 && escr_select == 3))
return 0; /* ESCR SELECT range error */
return escr_offset + (pair & 1) + 0x300;
};
static int p4_IQ_ESCR_ok; /* only models <= 2 can use IQ_ESCR{0,1} */
static int p4_is_ht; /* affects several CCCR & ESCR fields */
+static int p4_extended_cascade_ok; /* only models >= 2 can use extended cascading */
-static int p4_check_control(struct perfctr_cpu_state *state, int is_global)
+static int p4_check_control(struct perfctr_cpu_state *state, cpumask_t *cpumask)
{
unsigned int i, nractrs, nrctrs, pmc_mask;
nractrs = state->control.nractrs;
nrctrs = nractrs + state->control.nrictrs;
- if( nrctrs < nractrs || nrctrs > 18 )
+ if (nrctrs < nractrs || nrctrs > 18)
return -EINVAL;
pmc_mask = 0;
@@ -744,71 +976,77 @@ static int p4_check_control(struct perfctr_cpu_state *state, int is_global)
is extracted by masking off the FAST_RDPMC flag */
pmc = state->control.pmc_map[i] & ~P4_FAST_RDPMC;
state->pmc[i].map = state->control.pmc_map[i];
- if( pmc >= 18 || (pmc_mask & (1<<pmc)) )
+ if (pmc >= 18 || (pmc_mask & (1<<pmc)))
return -EINVAL;
pmc_mask |= (1<<pmc);
/* check CCCR contents */
cccr_val = state->control.evntsel[i];
- if( cccr_val & P4_CCCR_RESERVED )
+ if (cccr_val & P4_CCCR_RESERVED)
return -EPERM;
- if( cccr_val & P4_CCCR_EXTENDED_CASCADE ) {
- if( perfctr_info.cpu_type != PERFCTR_X86_INTEL_P4M2 )
+ if (cccr_val & P4_CCCR_EXTENDED_CASCADE) {
+ if (!p4_extended_cascade_ok)
return -EPERM;
- if( !(pmc == 12 || pmc >= 15) )
+ if (!(pmc == 12 || pmc >= 15))
return -EPERM;
}
- if( (cccr_val & P4_CCCR_ACTIVE_THREAD) != P4_CCCR_ACTIVE_THREAD && !p4_is_ht )
+ if ((cccr_val & P4_CCCR_ACTIVE_THREAD) != P4_CCCR_ACTIVE_THREAD && !p4_is_ht)
return -EINVAL;
- if( !(cccr_val & (P4_CCCR_ENABLE | P4_CCCR_CASCADE | P4_CCCR_EXTENDED_CASCADE)) )
+ if (!(cccr_val & (P4_CCCR_ENABLE | P4_CCCR_CASCADE | P4_CCCR_EXTENDED_CASCADE)))
return -EINVAL;
- if( cccr_val & P4_CCCR_OVF_PMI_T0 ) {
- if( i < nractrs )
+ if (cccr_val & P4_CCCR_OVF_PMI_T0) {
+ if (i < nractrs)
return -EINVAL;
- if( (cccr_val & P4_CCCR_FORCE_OVF) &&
- state->control.ireset[i] != -1 )
+ if ((cccr_val & P4_CCCR_FORCE_OVF) &&
+ state->control.ireset[i] != -1)
return -EINVAL;
} else {
- if( i >= nractrs )
+ if (i >= nractrs)
return -EINVAL;
}
/* check ESCR contents */
escr_val = state->control.p4.escr[i];
- if( escr_val & P4_ESCR_RESERVED )
+ if (escr_val & P4_ESCR_RESERVED)
return -EPERM;
- if( (escr_val & P4_ESCR_CPL_T1) && (!p4_is_ht || !is_global) )
+ if ((escr_val & P4_ESCR_CPL_T1) && (!p4_is_ht || cpumask != NULL))
return -EINVAL;
/* compute and cache ESCR address */
escr_addr = p4_escr_addr(pmc, cccr_val);
- if( !escr_addr )
+ if (!escr_addr)
return -EINVAL; /* ESCR SELECT range error */
/* IQ_ESCR0 and IQ_ESCR1 only exist in models <= 2 */
- if( (escr_addr & ~0x001) == 0x3BA && !p4_IQ_ESCR_ok )
+ if ((escr_addr & ~0x001) == 0x3BA && !p4_IQ_ESCR_ok)
return -EINVAL;
/* XXX: Two counters could map to the same ESCR. Should we
check that they use the same ESCR value? */
state->p4_escr_map[i] = escr_addr - MSR_P4_ESCR0;
}
/* check ReplayTagging control (PEBS_ENABLE and PEBS_MATRIX_VERT) */
- if( state->control.p4.pebs_enable ) {
- if( !nrctrs )
+ if (state->control.p4.pebs_enable) {
+ if (!nrctrs)
return -EPERM;
- if( state->control.p4.pebs_enable & P4_PE_RESERVED )
+ if (state->control.p4.pebs_enable & P4_PE_RESERVED)
return -EPERM;
- if( !(state->control.p4.pebs_enable & P4_PE_UOP_TAG ) )
+ if (!(state->control.p4.pebs_enable & P4_PE_UOP_TAG))
return -EINVAL;
- if( !(state->control.p4.pebs_enable & P4_PE_REPLAY_TAG_BITS) )
+ if (!(state->control.p4.pebs_enable & P4_PE_REPLAY_TAG_BITS))
return -EINVAL;
- if( state->control.p4.pebs_matrix_vert & P4_PMV_RESERVED )
+ if (state->control.p4.pebs_matrix_vert & P4_PMV_RESERVED)
return -EPERM;
- if( !(state->control.p4.pebs_matrix_vert & P4_PMV_REPLAY_TAG_BITS) )
+ if (!(state->control.p4.pebs_matrix_vert & P4_PMV_REPLAY_TAG_BITS))
return -EINVAL;
- } else if( state->control.p4.pebs_matrix_vert )
+ } else if (state->control.p4.pebs_matrix_vert)
return -EPERM;
state->k1.id = new_id();
+ if (nrctrs != 0 && cpumask != NULL)
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32)
+ cpumask_complement(cpumask, &perfctr_cpus_forbidden_mask);
+#else
+ cpus_complement(*cpumask, perfctr_cpus_forbidden_mask);
+#endif
return 0;
}
-#if PERFCTR_INTERRUPT_SUPPORT
+#ifdef CONFIG_X86_LOCAL_APIC
static void p4_isuspend(struct perfctr_cpu_state *state)
{
return p6_like_isuspend(state, MSR_P4_CCCR0);
@@ -818,7 +1056,7 @@ static void p4_iresume(const struct perfctr_cpu_state *state)
{
return p6_like_iresume(state, MSR_P4_CCCR0, MSR_P4_PERFCTR0);
}
-#endif /* PERFCTR_INTERRUPT_SUPPORT */
+#endif /* CONFIG_X86_LOCAL_APIC */
static void p4_write_control(const struct perfctr_cpu_state *state)
{
@@ -826,72 +1064,88 @@ static void p4_write_control(const struct perfctr_cpu_state *state)
unsigned int nrctrs, i;
/* XXX: temporary debug check */
- if( cpu_isset(smp_processor_id(), perfctr_cpus_forbidden_mask) &&
- perfctr_cstatus_nrctrs(state->cstatus) )
+ if (cpu_isset(smp_processor_id(), perfctr_cpus_forbidden_mask) &&
+ perfctr_cstatus_nrctrs(state->cstatus))
printk(KERN_ERR "%s: BUG! CPU %u is in the forbidden set\n",
__FUNCTION__, smp_processor_id());
- cache = &per_cpu_cache[smp_processor_id()];
- if( cache->k1.id == state->k1.id ) {
- debug_evntsel_cache(state, cache);
+ cache = get_cpu_cache();
+ if (cache->k1.id == state->k1.id)
return;
- }
nrctrs = perfctr_cstatus_nrctrs(state->cstatus);
for(i = 0; i < nrctrs; ++i) {
unsigned int escr_val, escr_off, cccr_val, pmc;
escr_val = state->control.p4.escr[i];
escr_off = state->p4_escr_map[i];
- if( escr_val != cache->control.escr[escr_off] ) {
+ if (escr_val != cache->control.escr[escr_off]) {
cache->control.escr[escr_off] = escr_val;
wrmsr(MSR_P4_ESCR0+escr_off, escr_val, 0);
}
cccr_val = state->control.evntsel[i];
pmc = state->pmc[i].map & P4_MASK_FAST_RDPMC;
- if( cccr_val != cache->control.evntsel[pmc] ) {
+ if (cccr_val != cache->control.evntsel[pmc]) {
cache->control.evntsel[pmc] = cccr_val;
wrmsr(MSR_P4_CCCR0+pmc, cccr_val, 0);
}
}
- if( state->control.p4.pebs_enable != cache->control.pebs_enable ) {
+ if (state->control.p4.pebs_enable != cache->control.pebs_enable) {
cache->control.pebs_enable = state->control.p4.pebs_enable;
wrmsr(MSR_P4_PEBS_ENABLE, state->control.p4.pebs_enable, 0);
}
- if( state->control.p4.pebs_matrix_vert != cache->control.pebs_matrix_vert ) {
+ if (state->control.p4.pebs_matrix_vert != cache->control.pebs_matrix_vert) {
cache->control.pebs_matrix_vert = state->control.p4.pebs_matrix_vert;
wrmsr(MSR_P4_PEBS_MATRIX_VERT, state->control.p4.pebs_matrix_vert, 0);
}
cache->k1.id = state->k1.id;
}
-static void p4_clear_counters(void)
-{
+static const struct perfctr_msr_range p4_perfctrs[] = {
+ { MSR_P4_PERFCTR0, 18 },
+ { 0, 0 },
+};
+
+static const struct perfctr_msr_range p4_evntsels[] = {
+ { 0x3BA, 2 }, /* IQ_ESCR{0,1}: only models <= 2 have them */
+ { 0x3A0, 26 },
+ { 0x3BC, 3 },
+ { 0x3C0, 6 },
+ { 0x3C8, 6 },
+ { 0x3E0, 2 },
+ { 0, 0 },
+};
+
+static const struct perfctr_msr_range p4_extras[] = {
/* MSR 0x3F0 seems to have a default value of 0xFC00, but current
docs doesn't fully define it, so leave it alone for now. */
- /* clear PEBS_ENABLE and PEBS_MATRIX_VERT; they handle both PEBS
- and ReplayTagging, and should exist even if PEBS is disabled */
- clear_msr_range(0x3F1, 2);
- clear_msr_range(0x3A0, 31);
- clear_msr_range(0x3C0, 6);
- clear_msr_range(0x3C8, 6);
- clear_msr_range(0x3E0, 2);
- clear_msr_range(MSR_P4_CCCR0, 18);
- clear_msr_range(MSR_P4_PERFCTR0, 18);
-}
+ /* PEBS_ENABLE and PEBS_MATRIX_VERT handle both PEBS and
+ ReplayTagging, and should exist even if PEBS is disabled */
+ { 0x3F1, 2 },
+ { MSR_P4_CCCR0, 18 },
+ { 0, 0 },
+};
+
+static const struct perfctr_pmu_msrs p4_pmu_msrs_models_0to2 = {
+ .perfctrs = p4_perfctrs,
+ .evntsels = p4_evntsels,
+ .extras = p4_extras,
+};
+
+static const struct perfctr_pmu_msrs p4_pmu_msrs_models_3up = {
+ .perfctrs = p4_perfctrs,
+ .evntsels = p4_evntsels+1,
+ .extras = p4_extras,
+};
/*
* Generic driver for any x86 with a working TSC.
*/
-static int generic_check_control(struct perfctr_cpu_state *state, int is_global)
+static int generic_check_control(struct perfctr_cpu_state *state, cpumask_t *cpumask)
{
- if( state->control.nractrs || state->control.nrictrs )
+ if (state->control.nractrs || state->control.nrictrs)
return -EINVAL;
return 0;
}
-static void generic_clear_counters(void)
-{
-}
-
/*
* Driver methods, internal and exported.
*
@@ -905,18 +1159,22 @@ static void generic_clear_counters(void)
* modification doesn't work in multiprocessor systems, due to
* Intel P6 errata. Consequently, all backpatchable call sites
* must be known and local to this file.
+ *
+ * Backpatchable calls must initially be to 'noinline' stubs.
+ * Otherwise the compiler may inline the stubs, which breaks
+ * redirect_call() and finalise_backpatching().
*/
static int redirect_call_disable;
-static void redirect_call(void *ra, void *to)
+static noinline void redirect_call(void *ra, void *to)
{
/* XXX: make this function __init later */
- if( redirect_call_disable )
+ if (redirect_call_disable)
printk(KERN_ERR __FILE__ ":%s: unresolved call to %p at %p\n",
__FUNCTION__, to, ra);
/* we can only redirect `call near relative' instructions */
- if( *((unsigned char*)ra - 5) != 0xE8 ) {
+ if (*((unsigned char*)ra - 5) != 0xE8) {
printk(KERN_WARNING __FILE__ ":%s: unable to redirect caller %p to %p\n",
__FUNCTION__, ra, to);
return;
@@ -925,7 +1183,7 @@ static void redirect_call(void *ra, void *to)
}
static void (*write_control)(const struct perfctr_cpu_state*);
-static void perfctr_cpu_write_control(const struct perfctr_cpu_state *state)
+static noinline void perfctr_cpu_write_control(const struct perfctr_cpu_state *state)
{
redirect_call(__builtin_return_address(0), write_control);
return write_control(state);
@@ -933,23 +1191,23 @@ static void perfctr_cpu_write_control(const struct perfctr_cpu_state *state)
static void (*read_counters)(const struct perfctr_cpu_state*,
struct perfctr_low_ctrs*);
-static void perfctr_cpu_read_counters(const struct perfctr_cpu_state *state,
- struct perfctr_low_ctrs *ctrs)
+static noinline void perfctr_cpu_read_counters(const struct perfctr_cpu_state *state,
+ struct perfctr_low_ctrs *ctrs)
{
redirect_call(__builtin_return_address(0), read_counters);
return read_counters(state, ctrs);
}
-#if PERFCTR_INTERRUPT_SUPPORT
+#ifdef CONFIG_X86_LOCAL_APIC
static void (*cpu_isuspend)(struct perfctr_cpu_state*);
-static void perfctr_cpu_isuspend(struct perfctr_cpu_state *state)
+static noinline void perfctr_cpu_isuspend(struct perfctr_cpu_state *state)
{
redirect_call(__builtin_return_address(0), cpu_isuspend);
return cpu_isuspend(state);
}
static void (*cpu_iresume)(const struct perfctr_cpu_state*);
-static void perfctr_cpu_iresume(const struct perfctr_cpu_state *state)
+static noinline void perfctr_cpu_iresume(const struct perfctr_cpu_state *state)
{
redirect_call(__builtin_return_address(0), cpu_iresume);
return cpu_iresume(state);
@@ -962,12 +1220,12 @@ void perfctr_cpu_ireload(struct perfctr_cpu_state *state)
#ifdef CONFIG_SMP
clear_isuspend_cpu(state);
#else
- per_cpu_cache[smp_processor_id()].k1.id = 0;
+ get_cpu_cache()->k1.id = 0;
#endif
}
/* PRE: the counters have been suspended and sampled by perfctr_cpu_suspend() */
-static int is_p4;
+static int lvtpc_reinit_needed;
unsigned int perfctr_cpu_identify_overflow(struct perfctr_cpu_state *state)
{
unsigned int cstatus, nrctrs, pmc, pmc_mask;
@@ -976,8 +1234,9 @@ unsigned int perfctr_cpu_identify_overflow(struct perfctr_cpu_state *state)
pmc = perfctr_cstatus_nractrs(cstatus);
nrctrs = perfctr_cstatus_nrctrs(cstatus);
+ state->pending_interrupt = 0;
for(pmc_mask = 0; pmc < nrctrs; ++pmc) {
- if( (int)state->pmc[pmc].start >= 0 ) { /* XXX: ">" ? */
+ if ((int)state->pmc[pmc].start >= 0) { /* XXX: ">" ? */
/* XXX: "+=" to correct for overshots */
state->pmc[pmc].start = state->control.ireset[pmc];
pmc_mask |= (1 << pmc);
@@ -987,7 +1246,7 @@ unsigned int perfctr_cpu_identify_overflow(struct perfctr_cpu_state *state)
in order to stop the i-mode counters. */
}
}
- if( is_p4 )
+ if (lvtpc_reinit_needed)
apic_write(APIC_LVTPC, LOCAL_PERFCTR_VECTOR);
return pmc_mask;
}
@@ -999,7 +1258,7 @@ static inline int check_ireset(const struct perfctr_cpu_state *state)
i = state->control.nractrs;
nrctrs = i + state->control.nrictrs;
for(; i < nrctrs; ++i)
- if( state->control.ireset[i] >= 0 )
+ if (state->control.ireset[i] >= 0)
return -EINVAL;
return 0;
}
@@ -1017,7 +1276,7 @@ static inline void setup_imode_start_values(struct perfctr_cpu_state *state)
static inline void debug_no_imode(const struct perfctr_cpu_state *state)
{
#ifdef CONFIG_PERFCTR_DEBUG
- if( perfctr_cstatus_has_ictrs(state->cstatus) )
+ if (perfctr_cstatus_has_ictrs(state->cstatus))
printk(KERN_ERR "perfctr/x86.c: BUG! updating control in"
" perfctr %p on cpu %u while it has cstatus %x"
" (pid %d, comm %s)\n",
@@ -1026,16 +1285,16 @@ static inline void debug_no_imode(const struct perfctr_cpu_state *state)
#endif
}
-#else /* PERFCTR_INTERRUPT_SUPPORT */
+#else /* CONFIG_X86_LOCAL_APIC */
static inline void perfctr_cpu_isuspend(struct perfctr_cpu_state *state) { }
static inline void perfctr_cpu_iresume(const struct perfctr_cpu_state *state) { }
static inline int check_ireset(const struct perfctr_cpu_state *state) { return 0; }
static inline void setup_imode_start_values(struct perfctr_cpu_state *state) { }
static inline void debug_no_imode(const struct perfctr_cpu_state *state) { }
-#endif /* PERFCTR_INTERRUPT_SUPPORT */
+#endif /* CONFIG_X86_LOCAL_APIC */
-static int (*check_control)(struct perfctr_cpu_state*, int);
-int perfctr_cpu_update_control(struct perfctr_cpu_state *state, int is_global)
+static int (*check_control)(struct perfctr_cpu_state*, cpumask_t*);
+int perfctr_cpu_update_control(struct perfctr_cpu_state *state, cpumask_t *cpumask)
{
int err;
@@ -1044,15 +1303,15 @@ int perfctr_cpu_update_control(struct perfctr_cpu_state *state, int is_global)
state->cstatus = 0;
/* disallow i-mode counters if we cannot catch the interrupts */
- if( !(perfctr_info.cpu_features & PERFCTR_FEATURE_PCINT)
- && state->control.nrictrs )
+ if (!(perfctr_info.cpu_features & PERFCTR_FEATURE_PCINT)
+ && state->control.nrictrs)
return -EPERM;
- err = check_control(state, is_global);
- if( err < 0 )
+ err = check_control(state, cpumask);
+ if (err < 0)
return err;
err = check_ireset(state);
- if( err < 0 )
+ if (err < 0)
return err;
state->cstatus = perfctr_mk_cstatus(state->control.tsc_on,
state->control.nractrs,
@@ -1066,11 +1325,11 @@ void perfctr_cpu_suspend(struct perfctr_cpu_state *state)
unsigned int i, cstatus, nractrs;
struct perfctr_low_ctrs now;
- if( perfctr_cstatus_has_ictrs(state->cstatus) )
+ if (perfctr_cstatus_has_ictrs(state->cstatus))
perfctr_cpu_isuspend(state);
perfctr_cpu_read_counters(state, &now);
cstatus = state->cstatus;
- if( perfctr_cstatus_has_tsc(cstatus) )
+ if (perfctr_cstatus_has_tsc(cstatus))
state->tsc_sum += now.tsc - state->tsc_start;
nractrs = perfctr_cstatus_nractrs(cstatus);
for(i = 0; i < nractrs; ++i)
@@ -1080,7 +1339,7 @@ void perfctr_cpu_suspend(struct perfctr_cpu_state *state)
void perfctr_cpu_resume(struct perfctr_cpu_state *state)
{
- if( perfctr_cstatus_has_ictrs(state->cstatus) )
+ if (perfctr_cstatus_has_ictrs(state->cstatus))
perfctr_cpu_iresume(state);
/* perfctr_cpu_enable_rdpmc(); */ /* not for x86 or global-mode */
perfctr_cpu_write_control(state);
@@ -1090,7 +1349,7 @@ void perfctr_cpu_resume(struct perfctr_cpu_state *state)
unsigned int i, cstatus, nrctrs;
perfctr_cpu_read_counters(state, &now);
cstatus = state->cstatus;
- if( perfctr_cstatus_has_tsc(cstatus) )
+ if (perfctr_cstatus_has_tsc(cstatus))
state->tsc_start = now.tsc;
nrctrs = perfctr_cstatus_nractrs(cstatus);
for(i = 0; i < nrctrs; ++i)
@@ -1106,7 +1365,7 @@ void perfctr_cpu_sample(struct perfctr_cpu_state *state)
perfctr_cpu_read_counters(state, &now);
cstatus = state->cstatus;
- if( perfctr_cstatus_has_tsc(cstatus) ) {
+ if (perfctr_cstatus_has_tsc(cstatus)) {
state->tsc_sum += now.tsc - state->tsc_start;
state->tsc_start = now.tsc;
}
@@ -1117,10 +1376,34 @@ void perfctr_cpu_sample(struct perfctr_cpu_state *state)
}
}
-static void (*clear_counters)(void);
-static void perfctr_cpu_clear_counters(void)
+static const struct perfctr_pmu_msrs *pmu_msrs;
+
+static void perfctr_cpu_clear_counters(int init)
{
- return clear_counters();
+ const struct perfctr_pmu_msrs *pmu;
+ const struct perfctr_msr_range *msrs;
+ int i;
+
+ pmu = pmu_msrs;
+ if (!pmu)
+ return;
+
+ /* The order below is significant: evntsels must be cleared
+ before the perfctrs. */
+ msrs = pmu->evntsels;
+ if (msrs)
+ for(i = 0; msrs[i].first_msr; ++i)
+ clear_msr_range(msrs[i].first_msr, msrs[i].nr_msrs);
+ msrs = pmu->extras;
+ if (msrs)
+ for(i = 0; msrs[i].first_msr; ++i)
+ clear_msr_range(msrs[i].first_msr, msrs[i].nr_msrs);
+ msrs = pmu->perfctrs;
+ if (msrs)
+ for(i = 0; msrs[i].first_msr; ++i)
+ clear_msr_range(msrs[i].first_msr, msrs[i].nr_msrs);
+ if (pmu->clear_counters)
+ (*pmu->clear_counters)(init);
}
/****************************************************************
@@ -1153,13 +1436,16 @@ static void __init finalise_backpatching(void)
old_mask = perfctr_cpus_forbidden_mask;
clear_perfctr_cpus_forbidden_mask();
- cache = &per_cpu_cache[smp_processor_id()];
+ cache = get_cpu_cache();
memset(cache, 0, sizeof *cache);
memset(&state, 0, sizeof state);
- state.cstatus =
- (perfctr_info.cpu_features & PERFCTR_FEATURE_PCINT)
- ? perfctr_mk_cstatus(0, 0, 1)
- : 0;
+ if (perfctr_info.cpu_features & PERFCTR_FEATURE_PCINT) {
+ state.cstatus = __perfctr_mk_cstatus(0, 1, 0, 0);
+ perfctr_cpu_sample(&state);
+ perfctr_cpu_resume(&state);
+ perfctr_cpu_suspend(&state);
+ }
+ state.cstatus = 0;
perfctr_cpu_sample(&state);
perfctr_cpu_resume(&state);
perfctr_cpu_suspend(&state);
@@ -1173,13 +1459,98 @@ static void __init finalise_backpatching(void)
cpumask_t perfctr_cpus_forbidden_mask;
+static inline unsigned int find_mask(unsigned int nrvals)
+{
+ unsigned int tmp = nrvals;
+ unsigned int index_msb = 31;
+
+ if (!tmp)
+ return 0;
+ while (!(tmp & (1<<31))) {
+ tmp <<= 1;
+ --index_msb;
+ }
+ if (nrvals & (nrvals - 1))
+ ++index_msb;
+ return ~(~0 << index_msb);
+}
+
static void __init p4_ht_mask_setup_cpu(void *forbidden)
{
- unsigned int local_apic_physical_id = cpuid_ebx(1) >> 24;
- unsigned int logical_processor_id = local_apic_physical_id & 1;
- if( logical_processor_id != 0 )
+ int cpu = smp_processor_id();
+ unsigned int cpuid_maxlev;
+ unsigned int cpuid1_ebx, cpuid1_edx, cpuid4_eax;
+ unsigned int initial_APIC_ID;
+ unsigned int max_cores_per_package;
+ unsigned int max_lp_per_package;
+ unsigned int max_lp_per_core;
+ unsigned int smt_id;
+
+ /*
+ * The following big chunk of code detects the current logical processor's
+ * SMT ID (thread number). This is quite complicated, see AP-485 and Volume 3
+ * of Intel's IA-32 Manual (especially section 7.10) for details.
+ */
+
+ /* Ensure that CPUID reports all levels. */
+ if (cpu_data(cpu).x86_model == 3) { /* >= 3? */
+ unsigned int low, high;
+ rdmsr(MSR_IA32_MISC_ENABLE, low, high);
+ if (low & (1<<22)) { /* LIMIT_CPUID_MAXVAL */
+ low &= ~(1<<22);
+ wrmsr(MSR_IA32_MISC_ENABLE, low, high);
+ printk(KERN_INFO "perfctr/x86.c: CPU %d: removed CPUID level limitation\n",
+ cpu);
+ }
+ }
+
+ /* Find the highest standard CPUID level. */
+ cpuid_maxlev = cpuid_eax(0);
+ if (cpuid_maxlev < 1) {
+ printk(KERN_INFO "perfctr/x86: CPU %d: impossibly low # of CPUID levels: %u\n",
+ cpu, cpuid_maxlev);
+ return;
+ }
+ cpuid1_ebx = cpuid_ebx(1);
+ cpuid1_edx = cpuid_edx(1);
+
+ /* Find the initial (HW-assigned) APIC ID of this logical processor. */
+ initial_APIC_ID = cpuid1_ebx >> 24;
+
+ /* Find the max number of logical processors per physical processor package. */
+ if (cpuid1_edx & (1 << 28)) /* HT is supported */
+ max_lp_per_package = (cpuid1_ebx >> 16) & 0xFF;
+ else /* HT is not supported */
+ max_lp_per_package = 1;
+
+ /* Find the max number of processor cores per physical processor package. */
+ if (cpuid_maxlev >= 4) {
+ /* For CPUID level 4 we need a zero in ecx as input to CPUID, but
+ cpuid_eax() doesn't do that. So we resort to using cpuid_count()
+ with reference parameters and dummy outputs. */
+ unsigned int dummy;
+ cpuid_count(4, 0, &cpuid4_eax, &dummy, &dummy, &dummy);
+ max_cores_per_package = (cpuid4_eax >> 26) + 1;
+ } else {
+ cpuid4_eax = 0;
+ max_cores_per_package = 1;
+ }
+
+ max_lp_per_core = max_lp_per_package / max_cores_per_package;
+
+ smt_id = initial_APIC_ID & find_mask(max_lp_per_core);
+
+ printk(KERN_INFO "perfctr/x86.c: CPU %d: cpuid_ebx(1) 0x%08x, cpuid_edx(1) 0x%08x, cpuid_eax(4) 0x%08x, cpuid_maxlev %u, max_cores_per_package %u, SMT_ID %u\n",
+ cpu, cpuid1_ebx, cpuid1_edx, cpuid4_eax, cpuid_maxlev, max_cores_per_package, smt_id);
+
+ /*
+ * Now (finally!) check the SMT ID. The CPU numbers for non-zero SMT ID
+ * threads are recorded in the forbidden set, to allow performance counter
+ * hardware resource conflicts between sibling threads to be prevented.
+ */
+ if (smt_id != 0)
/* We rely on cpu_set() being atomic! */
- cpu_set(smp_processor_id(), *(cpumask_t*)forbidden);
+ cpu_set(cpu, *(cpumask_t*)forbidden);
}
static int __init p4_ht_smp_init(void)
@@ -1188,15 +1559,15 @@ static int __init p4_ht_smp_init(void)
unsigned int cpu;
cpus_clear(forbidden);
- smp_call_function(p4_ht_mask_setup_cpu, &forbidden, 1, 1);
+ smp_call_function(p4_ht_mask_setup_cpu, &forbidden, 1);
p4_ht_mask_setup_cpu(&forbidden);
- if( cpus_empty(forbidden) )
+ if (cpus_empty(forbidden))
return 0;
perfctr_cpus_forbidden_mask = forbidden;
printk(KERN_INFO "perfctr/x86.c: hyper-threaded P4s detected:"
" restricting access for CPUs");
for(cpu = 0; cpu < NR_CPUS; ++cpu)
- if( cpu_isset(cpu, forbidden) )
+ if (cpu_isset(cpu, forbidden))
printk(" %u", cpu);
printk("\n");
return 0;
@@ -1209,188 +1580,466 @@ static int __init p4_ht_init(void)
{
unsigned int nr_siblings;
- if( !cpu_has_ht )
+ if (!cpu_has_ht)
return 0;
nr_siblings = (cpuid_ebx(1) >> 16) & 0xFF;
- if( nr_siblings > 2 ) {
- printk(KERN_WARNING "perfctr/x86.c: hyper-threaded P4s detected:"
- " unsupported number of siblings: %u -- bailing out\n",
- nr_siblings);
- return -ENODEV;
- }
- if( nr_siblings < 2 )
+ if (nr_siblings < 2)
return 0;
p4_is_ht = 1; /* needed even in a UP kernel */
return p4_ht_smp_init();
}
-static int __init intel_init(void)
+static int __init intel_p4_init(void)
{
- static char p5_name[] __initdata = "Intel Pentium";
- static char p5mmx_name[] __initdata = "Intel Pentium MMX";
- static char ppro_name[] __initdata = "Intel Pentium Pro";
- static char pii_name[] __initdata = "Intel Pentium II";
- static char piii_name[] __initdata = "Intel Pentium III";
- static char p4_name[] __initdata = "Intel Pentium 4";
- static char p4m2_name[] __initdata = "Intel Pentium 4 Model 2";
- static char pentm_name[] __initdata = "Intel Pentium M";
+ static char p4_name[] __initdata = "Intel P4";
unsigned int misc_enable;
- if( !cpu_has_tsc )
+ /* Detect things that matter to the driver. */
+ rdmsr_low(MSR_IA32_MISC_ENABLE, misc_enable);
+ if (!(misc_enable & MSR_IA32_MISC_ENABLE_PERF_AVAIL))
return -ENODEV;
- switch( current_cpu_data.x86 ) {
- case 5:
- if( cpu_has_mmx ) {
- perfctr_info.cpu_type = PERFCTR_X86_INTEL_P5MMX;
- perfctr_cpu_name = p5mmx_name;
- read_counters = rdpmc_read_counters;
-
- /* Avoid Pentium Erratum 74. */
- if( current_cpu_data.x86_model == 4 &&
- (current_cpu_data.x86_mask == 4 ||
- (current_cpu_data.x86_mask == 3 &&
- ((cpuid_eax(1) >> 12) & 0x3) == 1)) )
- perfctr_info.cpu_features &= ~PERFCTR_FEATURE_RDPMC;
- } else {
- perfctr_info.cpu_type = PERFCTR_X86_INTEL_P5;
- perfctr_cpu_name = p5_name;
+ if (p4_ht_init() != 0)
+ return -ENODEV;
+ if (current_cpu_data.x86_model <= 2)
+ p4_IQ_ESCR_ok = 1;
+ if (current_cpu_data.x86_model >= 2)
+ p4_extended_cascade_ok = 1;
+ /* Detect and set up legacy cpu_type for user-space. */
+ if (current_cpu_data.x86_model >= 3) {
+ /* Model 3 removes IQ_ESCR{0,1} and adds one event. */
+ perfctr_info.cpu_type = PERFCTR_X86_INTEL_P4M3;
+ } else if (current_cpu_data.x86_model >= 2) {
+ /* Model 2 changed the ESCR Event Mask programming
+ details for several events. */
+ perfctr_info.cpu_type = PERFCTR_X86_INTEL_P4M2;
+ } else {
+ perfctr_info.cpu_type = PERFCTR_X86_INTEL_P4;
+ }
+ perfctr_set_tests_type(PTT_P4);
+ perfctr_cpu_name = p4_name;
+ read_counters = rdpmc_read_counters;
+ write_control = p4_write_control;
+ check_control = p4_check_control;
+ if (current_cpu_data.x86_model <= 2)
+ pmu_msrs = &p4_pmu_msrs_models_0to2;
+ else
+ pmu_msrs = &p4_pmu_msrs_models_3up;
+#ifdef CONFIG_X86_LOCAL_APIC
+ if (cpu_has_apic) {
+ perfctr_info.cpu_features |= PERFCTR_FEATURE_PCINT;
+ cpu_isuspend = p4_isuspend;
+ cpu_iresume = p4_iresume;
+ lvtpc_reinit_needed = 1;
+ }
+#endif
+ return 0;
+}
+
+static int __init intel_p5_init(void)
+{
+ static char p5_name[] __initdata = "Intel P5";
+
+ /* Detect things that matter to the driver. */
+ if (cpu_has_mmx) {
+ read_counters = rdpmc_read_counters;
+
+ /* Avoid Pentium Erratum 74. */
+ if (current_cpu_data.x86_model == 4 &&
+ (current_cpu_data.x86_mask == 4 ||
+ (current_cpu_data.x86_mask == 3 &&
+ ((cpuid_eax(1) >> 12) & 0x3) == 1)))
perfctr_info.cpu_features &= ~PERFCTR_FEATURE_RDPMC;
- read_counters = p5_read_counters;
- }
- write_control = p5_write_control;
- check_control = p5_check_control;
- clear_counters = p5_clear_counters;
- perfctr_p5_init_tests();
- return 0;
- case 6:
- if( current_cpu_data.x86_model == 9 ) { /* Pentium M */
- /* Pentium M added the MISC_ENABLE MSR from P4. */
- rdmsr_low(MSR_IA32_MISC_ENABLE, misc_enable);
- if( !(misc_enable & MSR_IA32_MISC_ENABLE_PERF_AVAIL) )
- break;
- /* Erratum Y3 probably does not apply since we
- read only the low 32 bits. */
- perfctr_info.cpu_type = PERFCTR_X86_INTEL_PENTM;
- perfctr_cpu_name = pentm_name;
- } else if( current_cpu_data.x86_model >= 7 ) { /* PIII */
- perfctr_info.cpu_type = PERFCTR_X86_INTEL_PIII;
- perfctr_cpu_name = piii_name;
- } else if( current_cpu_data.x86_model >= 3 ) { /* PII or Celeron */
- perfctr_info.cpu_type = PERFCTR_X86_INTEL_PII;
- perfctr_cpu_name = pii_name;
- } else {
- perfctr_info.cpu_type = PERFCTR_X86_INTEL_P6;
- perfctr_cpu_name = ppro_name;
+ } else {
+ perfctr_info.cpu_features &= ~PERFCTR_FEATURE_RDPMC;
+ read_counters = p5_read_counters;
+ }
+ /* Detect and set up legacy cpu_type for user-space. */
+ if (cpu_has_mmx) {
+ perfctr_info.cpu_type = PERFCTR_X86_INTEL_P5MMX;
+ } else {
+ perfctr_info.cpu_type = PERFCTR_X86_INTEL_P5;
+ }
+ perfctr_set_tests_type(PTT_P5);
+ perfctr_cpu_name = p5_name;
+ write_control = p5_write_control;
+ check_control = p5_check_control;
+ pmu_msrs = &p5_pmu_msrs;
+ return 0;
+}
+
+static int __init intel_p6_init(void)
+{
+ static char p6_name[] __initdata = "Intel P6";
+ static char core2_name[] __initdata = "Intel Core 2";
+ static char atom_name[] __initdata = "Intel Atom";
+ static char nhlm_name[] __initdata = "Intel Nehalem";
+ static char wstmr_name[] __initdata = "Intel Westmere";
+ unsigned int misc_enable;
+
+ /*
+ * Post P4 family 6 models (Pentium M, Core, Core 2, Atom)
+ * have MISC_ENABLE.PERF_AVAIL like the P4.
+ */
+ switch (current_cpu_data.x86_model) {
+ case 9: /* Pentium M */
+ case 13: /* Pentium M */
+ case 14: /* Core */
+ case 15: /* Core 2 */
+ case 22: /* Core 2 based Celeron model 16h */
+ case 23: /* Core 2 */
+ case 26: /* Nehalem: Core i7-900, Xeon 5500, Xeon 3500 */
+ case 28: /* Atom */
+ case 29: /* Core 2 based Xeon 7400 */
+ case 30: /* Nehalem: Core i7-800/i5-700, i7-900XM/i7-800M/i7-700M, Xeon 3400 */
+ case 37: /* Westmere: Core i5-600/i3-500/Pentium-G6950, i7-600M/i5-500M/i5-400M/i3-300M, Xeno L3406 */
+ case 44: /* Westmere: Core i7-980X (Gulftown), Xeon 5600, Xeon 3600 */
+ case 46: /* Nehalem: Xeon 7500 */
+ rdmsr_low(MSR_IA32_MISC_ENABLE, misc_enable);
+ if (!(misc_enable & MSR_IA32_MISC_ENABLE_PERF_AVAIL))
+ return -ENODEV;
+ }
+
+ /*
+ * Core 2 made each EVNTSEL have its own ENable bit,
+ * and added three fixed-function counters.
+ * On Atom cpuid tells us the number of fixed-function counters.
+ * Core i7 extended the number of PMCs to four.
+ */
+ p6_nr_pmcs = 2;
+ switch (current_cpu_data.x86_model) {
+ case 15: /* Core 2 */
+ case 22: /* Core 2 based Celeron model 16h */
+ case 23: /* Core 2 */
+ case 29: /* Core 2 based Xeon 7400 */
+ perfctr_cpu_name = core2_name;
+ p6_has_separate_enables = 1;
+ p6_nr_ffcs = 3;
+ break;
+ case 26: /* Nehalem: Core i7-900, Xeon 5500, Xeon 3500 */
+ case 30: /* Nehalem: Core i7-800/i5-700, i7-900XM/i7-800M/i7-700M, Xeon 3400 */
+ case 46: /* Nehalem: Xeon 7500 */
+ perfctr_cpu_name = nhlm_name;
+ p6_has_separate_enables = 1;
+ p6_nr_ffcs = 3;
+ p6_nr_pmcs = 4;
+ nhlm_nr_offcore_rsps = 1;
+ break;
+ case 37: /* Westmere: Core i5-600/i3-500/Pentium-G6950, i7-600M/i5-500M/i5-400M/i3-300M, Xeon L3406 */
+ case 44: /* Westmere: Core i7-980X (Gulftown), Xeon 5600, Xeon 3600 */
+ perfctr_cpu_name = wstmr_name;
+ p6_has_separate_enables = 1;
+ p6_nr_ffcs = 3;
+ p6_nr_pmcs = 4;
+ /* Westmere adds MSR_OFFCORE_RSP1 and drops some events */
+ nhlm_nr_offcore_rsps = 2;
+ break;
+ case 28: { /* Atom */
+ unsigned int maxlev, eax, ebx, dummy, edx;
+
+ perfctr_cpu_name = atom_name;
+ p6_has_separate_enables = 1;
- /* Avoid Pentium Pro Erratum 26. */
- if( current_cpu_data.x86_mask < 9 )
- perfctr_info.cpu_features &= ~PERFCTR_FEATURE_RDPMC;
+ maxlev = cpuid_eax(0);
+ if (maxlev < 0xA) {
+ printk(KERN_WARNING "%s: cpuid[0].eax == %u, unable to query 0xA leaf\n",
+ __FUNCTION__, maxlev);
+ return -EINVAL;
}
- read_counters = rdpmc_read_counters;
- write_control = p6_write_control;
- check_control = p6_check_control;
- clear_counters = p6_clear_counters;
-#if PERFCTR_INTERRUPT_SUPPORT
- if( cpu_has_apic ) {
- perfctr_info.cpu_features |= PERFCTR_FEATURE_PCINT;
- cpu_isuspend = p6_isuspend;
- cpu_iresume = p6_iresume;
+ cpuid(0xA, &eax, &ebx, &dummy, &edx);
+ /* ensure we have at least APM V2 with 2 40-bit general-purpose counters */
+ if ((eax & 0xff) < 2 ||
+ ((eax >> 8) & 0xff) != 2 ||
+ ((eax >> 16) & 0xff) < 40) {
+ printk(KERN_WARNING "%s: cpuid[0xA].eax == 0x%08x appears bogus\n",
+ __FUNCTION__, eax);
+ return -EINVAL;
}
-#endif
- perfctr_p6_init_tests();
- return 0;
- case 15: /* Pentium 4 */
- rdmsr_low(MSR_IA32_MISC_ENABLE, misc_enable);
- if( !(misc_enable & MSR_IA32_MISC_ENABLE_PERF_AVAIL) )
- break;
- if( p4_ht_init() != 0 )
- break;
- if( current_cpu_data.x86_model <= 2 )
- p4_IQ_ESCR_ok = 1;
- if( current_cpu_data.x86_model >= 2 ) {
- /* Model 2 changed the ESCR Event Mask programming
- details for several events. */
- perfctr_info.cpu_type = PERFCTR_X86_INTEL_P4M2;
- perfctr_cpu_name = p4m2_name;
- } else {
- perfctr_info.cpu_type = PERFCTR_X86_INTEL_P4;
- perfctr_cpu_name = p4_name;
+ /* extract the number of fixed-function counters: Core2 has 3,
+ and initial Atoms appear to have 1; play it safe and reject
+ excessive values */
+ p6_nr_ffcs = edx & 0x1f;
+ if (p6_nr_ffcs > 3) {
+ printk(KERN_WARNING "%s: cpuid[0xA] == { edx == 0x%08x, "
+ "eax == 0x%08x } appears bogus\n",
+ __FUNCTION__, edx, eax);
+ p6_nr_ffcs = 0;
}
- read_counters = rdpmc_read_counters;
- write_control = p4_write_control;
- check_control = p4_check_control;
- clear_counters = p4_clear_counters;
-#if PERFCTR_INTERRUPT_SUPPORT
- if( cpu_has_apic ) {
- perfctr_info.cpu_features |= PERFCTR_FEATURE_PCINT;
- cpu_isuspend = p4_isuspend;
- cpu_iresume = p4_iresume;
- is_p4 = 1;
+ break;
+ }
+ default:
+ perfctr_cpu_name = p6_name;
+ break;
+ }
+
+ /*
+ * Avoid Pentium Pro Erratum 26.
+ */
+ if (current_cpu_data.x86_model < 3) { /* Pentium Pro */
+ if (current_cpu_data.x86_mask < 9)
+ perfctr_info.cpu_features &= ~PERFCTR_FEATURE_RDPMC;
+ }
+
+ /*
+ * Detect and set up legacy cpu_type for user-space.
+ */
+ switch (current_cpu_data.x86_model) {
+ default:
+ printk(KERN_WARNING __FILE__ "%s: unknown model %u processor, "
+ "please report this to perfctr-devel or mikpe@it.uu.se\n",
+ __FUNCTION__, current_cpu_data.x86_model);
+ /*FALLTHROUGH*/
+ case 0: /* Pentium Pro A-step */
+ case 1: /* Pentium Pro */
+ case 4: /* Pentium Pro based P55CT overdrive for P54 */
+ perfctr_info.cpu_type = PERFCTR_X86_INTEL_P6;
+ break;
+ case 3: /* Pentium II or PII-based overdrive for PPro */
+ case 5: /* Pentium II */
+ case 6: /* Pentium II */
+ perfctr_info.cpu_type = PERFCTR_X86_INTEL_PII;
+ break;
+ case 7: /* Pentium III */
+ case 8: /* Pentium III */
+ case 10: /* Pentium III Xeon model A */
+ case 11: /* Pentium III */
+ perfctr_info.cpu_type = PERFCTR_X86_INTEL_PIII;
+ break;
+ case 9: /* Pentium M */
+ case 13: /* Pentium M */
+ /* Erratum Y3 probably does not apply since we
+ read only the low 32 bits. */
+ perfctr_info.cpu_type = PERFCTR_X86_INTEL_PENTM;
+ break;
+ case 14: /* Core */
+ /* XXX: what about erratum AE19? */
+ perfctr_info.cpu_type = PERFCTR_X86_INTEL_CORE;
+ break;
+ case 15: /* Core 2 */
+ case 22: /* Core 2 based Celeron model 16h */
+ case 23: /* Core 2 */
+ case 29: /* Core 2 based Xeon 7400 */
+ perfctr_info.cpu_type = PERFCTR_X86_INTEL_CORE2;
+ break;
+ case 26: /* Nehalem: Core i7-900, Xeon 5500, Xeon 3500 */
+ case 30: /* Nehalem: Core i7-800/i5-700, i7-900XM/i7-800M/i7-700M, Xeon 3400 */
+ case 46: /* Nehalem: Xeon 7500 */
+ perfctr_info.cpu_type = PERFCTR_X86_INTEL_NHLM;
+ break;
+ case 37: /* Westmere: Core i5-600/i3-500/Pentium-G6950, i7-600M/i5-500M/i5-400M/i3-300M, Xeon L3406 */
+ case 44: /* Westmere: Core i7-980X (Gulftown), Xeon 5600, Xeon 3600 */
+ perfctr_info.cpu_type = PERFCTR_X86_INTEL_WSTMR;
+ break;
+ case 28: /* Atom */
+ perfctr_info.cpu_type = PERFCTR_X86_INTEL_ATOM;
+ break;
+ }
+
+ perfctr_set_tests_type(p6_nr_ffcs != 0 ? PTT_CORE2 : PTT_P6);
+ read_counters = rdpmc_read_counters;
+ write_control = p6_write_control;
+ check_control = p6_check_control;
+ p6_perfctrs[0].nr_msrs = p6_nr_pmcs;
+ p6_evntsels[0].nr_msrs = p6_nr_pmcs;
+ core2_extras[0].nr_msrs = p6_nr_ffcs;
+ core2_extras[2].nr_msrs = nhlm_nr_offcore_rsps;
+ pmu_msrs = p6_nr_ffcs != 0 ? &core2_pmu_msrs : &p6_pmu_msrs;
+
+#ifdef CONFIG_X86_LOCAL_APIC
+ if (cpu_has_apic) {
+ perfctr_info.cpu_features |= PERFCTR_FEATURE_PCINT;
+ cpu_isuspend = p6_isuspend;
+ cpu_iresume = p6_iresume;
+ /*
+ * Post P4 family 6 models (Pentium M, Core, Core 2, Atom)
+ * have LVTPC auto-masking like the P4.
+ */
+ switch (current_cpu_data.x86_model) {
+ case 9: /* Pentium M */
+ case 13: /* Pentium M */
+ case 14: /* Core */
+ case 15: /* Core 2 */
+ case 22: /* Core 2 based Celeron model 16h */
+ case 23: /* Core 2 */
+ case 26: /* Nehalem: Core i7-900, Xeon 5500, Xeon 3500 */
+ case 28: /* Atom */
+ case 29: /* Core 2 based Xeon 7400 */
+ case 30: /* Nehalem: Core i7-800/i5-700, i7-900XM/i7-800M/i7-700M, Xeon 3400 */
+ case 37: /* Westmere: Core i5-600/i3-500/Pentium-G6950, i7-600M/i5-500M/i5-400M/i3-300M, Xeon L3406 */
+ case 44: /* Westmere: Core i7-980X (Gulftown), Xeon 5600, Xeon 3600 */
+ case 46: /* Nehalem: Xeon 7500 */
+ lvtpc_reinit_needed = 1;
}
+ }
#endif
- perfctr_p4_init_tests();
- return 0;
+
+ return 0;
+}
+
+static int __init intel_init(void)
+{
+ if (!cpu_has_tsc)
+ return -ENODEV;
+ switch (current_cpu_data.x86) {
+ case 5:
+ return intel_p5_init();
+ case 6:
+ return intel_p6_init();
+ case 15:
+ return intel_p4_init();
}
return -ENODEV;
}
+/*
+ * Multicore K8s have issues with northbridge events:
+ * 1. The NB is shared between the cores, so two different cores
+ * in the same node cannot count NB events simultaneously.
+ * This is handled by using a cpumask to restrict NB-using
+ * threads to core0 of all processors.
+ * 2. The initial multicore chips (Revision E) have an erratum
+ * which causes the NB counters to be reset when either core
+ * reprograms its evntsels (even for non-NB events).
+ * This is only an issue because of scheduling of threads, so
+ * we restrict NB events to the non thread-centric API.
+ */
+#ifdef CONFIG_SMP
+struct amd_mc_init_data {
+ atomic_t non0core_seen;
+ cpumask_t core0_mask;
+};
+
+static void __init amd_mc_init_cpu(void *data)
+{
+ int cpu = smp_processor_id();
+ unsigned int apic_core_id_size, core_id;
+ struct amd_mc_init_data *amd_mc_init_data = data;
+
+ if ((cpuid_edx(1) & (1<<28)) == 0 || /* HTT is off */
+ cpuid_eax(0x80000000) < 0x80000008) { /* no Core Count info */
+ /* each processor is single-core */
+ apic_core_id_size = 0;
+ } else {
+ unsigned int ecx = cpuid_ecx(0x80000008);
+
+ apic_core_id_size = (ecx >> 12) & 0xF; /* XXX: resvd in early CPUs */
+ if (apic_core_id_size == 0) {
+ unsigned int max_cores = (ecx & 0xFF) + 1;
+
+ while ((1 << apic_core_id_size) < max_cores)
+ ++apic_core_id_size;
+ }
+ }
+
+ core_id = (cpuid_ebx(1) >> 24) & ((1 << apic_core_id_size) - 1);
+ printk(KERN_INFO "%s: cpu %d core_id %u\n", __FUNCTION__, cpu, core_id);
+
+ if (core_id != 0) {
+ atomic_set(&amd_mc_init_data->non0core_seen, 1);
+ } else {
+ /* We rely on cpu_set() being atomic! */
+ cpu_set(cpu, amd_mc_init_data->core0_mask);
+ }
+}
+
+static int __init amd_multicore_init(void)
+{
+ struct amd_mc_init_data amd_mc_init_data;
+
+ atomic_set(&amd_mc_init_data.non0core_seen, 0);
+ cpus_clear(amd_mc_init_data.core0_mask);
+
+ smp_call_function(amd_mc_init_cpu, &amd_mc_init_data, 1);
+ amd_mc_init_cpu(&amd_mc_init_data);
+
+ if (atomic_read(&amd_mc_init_data.non0core_seen) == 0) {
+ printk(KERN_INFO "%s: !non0core_seen\n", __FUNCTION__);
+ return 0;
+ }
+#if 1 /* XXX: temporary sanity check, should be impossible */
+ if (cpus_empty(amd_mc_init_data.core0_mask)) {
+ printk(KERN_ERR "%s: Error: cpus_empty(core0_mask)\n", __FUNCTION__);
+ return -ENODEV;
+ }
+#endif
+
+ amd_is_multicore = 1;
+ if (current_cpu_data.x86 == 15 &&
+ current_cpu_data.x86_model >= 0x20 &&
+ current_cpu_data.x86_model < 0x40) {
+ amd_is_k8_mc_RevE = 1;
+ printk(KERN_INFO "perfctr/x86.c: multi-core K8 RevE detected:"
+ " restricting access to northbridge events\n");
+ } else {
+ amd_mc_core0_mask = amd_mc_init_data.core0_mask;
+ printk(KERN_INFO "perfctr/x86.c: multi-core AMDs detected:"
+ " forcing northbridge events to core0 CPUs\n");
+ }
+ return 0;
+}
+#else /* CONFIG_SMP */
+#define amd_multicore_init() (0)
+#endif /* CONFIG_SMP */
+
static int __init amd_init(void)
{
- static char k7_name[] __initdata = "AMD K7";
- static char k8_name[] __initdata = "AMD K8";
- static char k8c_name[] __initdata = "AMD K8C";
+ static char amd_name[] __initdata = "AMD K7/K8/Fam10h/Fam11h";
- if( !cpu_has_tsc )
+ if (!cpu_has_tsc)
return -ENODEV;
- switch( current_cpu_data.x86 ) {
+ switch (current_cpu_data.x86) {
+ case 6: /* K7 */
+ perfctr_info.cpu_type = PERFCTR_X86_AMD_K7;
+ break;
case 15: /* K8. Like a K7 with a different event set. */
- if( (current_cpu_data.x86_model > 5) ||
- (current_cpu_data.x86_model >= 4 && current_cpu_data.x86_mask >= 8) ) {
+ if ((current_cpu_data.x86_model > 5) ||
+ (current_cpu_data.x86_model >= 4 && current_cpu_data.x86_mask >= 8)) {
perfctr_info.cpu_type = PERFCTR_X86_AMD_K8C;
- perfctr_cpu_name = k8c_name;
} else {
perfctr_info.cpu_type = PERFCTR_X86_AMD_K8;
- perfctr_cpu_name = k8_name;
}
+ if (amd_multicore_init() < 0)
+ return -ENODEV;
break;
- case 6: /* K7. Model 1 does not have a local APIC.
- AMD Document #22007 Revision J hints that APIC-less
- K7s signal overflows as debug interrupts. */
- perfctr_info.cpu_type = PERFCTR_X86_AMD_K7;
- perfctr_cpu_name = k7_name;
+ case 16:
+ case 17:
+ is_fam10h = 1;
+ perfctr_info.cpu_type = PERFCTR_X86_AMD_FAM10H;
+ if (amd_multicore_init() < 0)
+ return -ENODEV;
break;
default:
return -ENODEV;
}
+ perfctr_set_tests_type(PTT_AMD);
+ perfctr_cpu_name = amd_name;
read_counters = rdpmc_read_counters;
write_control = k7_write_control;
check_control = k7_check_control;
- clear_counters = k7_clear_counters;
-#if PERFCTR_INTERRUPT_SUPPORT
- if( cpu_has_apic ) {
+ pmu_msrs = &k7_pmu_msrs;
+#ifdef CONFIG_X86_LOCAL_APIC
+ if (cpu_has_apic) {
perfctr_info.cpu_features |= PERFCTR_FEATURE_PCINT;
cpu_isuspend = k7_isuspend;
cpu_iresume = k7_iresume;
}
#endif
- perfctr_k7_init_tests();
return 0;
}
static int __init cyrix_init(void)
{
static char mii_name[] __initdata = "Cyrix 6x86MX/MII/III";
- if( !cpu_has_tsc )
+ if (!cpu_has_tsc)
return -ENODEV;
- switch( current_cpu_data.x86 ) {
+ switch (current_cpu_data.x86) {
case 6: /* 6x86MX, MII, or III */
perfctr_info.cpu_type = PERFCTR_X86_CYRIX_MII;
+ perfctr_set_tests_type(PTT_P5);
perfctr_cpu_name = mii_name;
read_counters = rdpmc_read_counters;
write_control = p5_write_control;
check_control = mii_check_control;
- clear_counters = p5_clear_counters;
- perfctr_mii_init_tests();
+ pmu_msrs = &p5_pmu_msrs;
return 0;
}
return -ENODEV;
@@ -1399,43 +2048,41 @@ static int __init cyrix_init(void)
static int __init centaur_init(void)
{
#if !defined(CONFIG_X86_TSC)
- static char wcc6_name[] __initdata = "WinChip C6";
- static char wc2_name[] __initdata = "WinChip 2/3";
+ static char winchip_name[] __initdata = "WinChip C6/2/3";
#endif
static char vc3_name[] __initdata = "VIA C3";
- switch( current_cpu_data.x86 ) {
+ switch (current_cpu_data.x86) {
#if !defined(CONFIG_X86_TSC)
case 5:
- switch( current_cpu_data.x86_model ) {
+ switch (current_cpu_data.x86_model) {
case 4: /* WinChip C6 */
perfctr_info.cpu_type = PERFCTR_X86_WINCHIP_C6;
- perfctr_cpu_name = wcc6_name;
break;
case 8: /* WinChip 2, 2A, or 2B */
case 9: /* WinChip 3, a 2A with larger cache and lower voltage */
perfctr_info.cpu_type = PERFCTR_X86_WINCHIP_2;
- perfctr_cpu_name = wc2_name;
break;
default:
return -ENODEV;
}
+ perfctr_set_tests_type(PTT_WINCHIP);
+ perfctr_cpu_name = winchip_name;
/*
* TSC must be inaccessible for perfctrs to work.
*/
- if( !(read_cr4() & X86_CR4_TSD) || cpu_has_tsc )
+ if (!(read_cr4() & X86_CR4_TSD) || cpu_has_tsc)
return -ENODEV;
perfctr_info.cpu_features &= ~PERFCTR_FEATURE_RDTSC;
read_counters = rdpmc_read_counters;
write_control = c6_write_control;
check_control = c6_check_control;
- clear_counters = p5_clear_counters;
- perfctr_c6_init_tests();
+ pmu_msrs = &p5_pmu_msrs;
return 0;
-#endif
+#endif /* !CONFIG_X86_TSC */
case 6: /* VIA C3 */
- if( !cpu_has_tsc )
+ if (!cpu_has_tsc)
return -ENODEV;
- switch( current_cpu_data.x86_model ) {
+ switch (current_cpu_data.x86_model) {
case 6: /* Cyrix III */
case 7: /* Samuel 2, Ezra (steppings >= 8) */
case 8: /* Ezra-T */
@@ -1445,12 +2092,12 @@ static int __init centaur_init(void)
return -ENODEV;
}
perfctr_info.cpu_type = PERFCTR_X86_VIA_C3;
+ perfctr_set_tests_type(PTT_VC3);
perfctr_cpu_name = vc3_name;
read_counters = rdpmc_read_counters;
write_control = p6_write_control;
check_control = vc3_check_control;
- clear_counters = vc3_clear_counters;
- perfctr_vc3_init_tests();
+ pmu_msrs = &vc3_pmu_msrs;
return 0;
}
return -ENODEV;
@@ -1459,42 +2106,73 @@ static int __init centaur_init(void)
static int __init generic_init(void)
{
static char generic_name[] __initdata = "Generic x86 with TSC";
- if( !cpu_has_tsc )
+ if (!cpu_has_tsc)
return -ENODEV;
perfctr_info.cpu_features &= ~PERFCTR_FEATURE_RDPMC;
perfctr_info.cpu_type = PERFCTR_X86_GENERIC;
+ perfctr_set_tests_type(PTT_GENERIC);
perfctr_cpu_name = generic_name;
check_control = generic_check_control;
write_control = p6_write_control;
read_counters = rdpmc_read_counters;
- clear_counters = generic_clear_counters;
- perfctr_generic_init_tests();
+ pmu_msrs = NULL;
return 0;
}
-static void __init perfctr_cpu_init_one(void *ignore)
+static void perfctr_cpu_invalidate_cache(void)
+{
+ struct per_cpu_cache *cache = get_cpu_cache();
+
+ /*
+ * per_cpu_cache[] is initialised to contain "impossible"
+ * evntsel values guaranteed to differ from anything accepted
+ * by perfctr_cpu_update_control().
+ * All-bits-one works for all currently supported processors.
+ * The memset also sets the ids to -1, which is intentional.
+ */
+ memset(cache, ~0, sizeof(struct per_cpu_cache));
+
+ /*
+ * To ensure that MSR_CORE_PERF_FIXED_CTR_CTRL is not written
+ * to on processors that do not have it, each CPU cache must
+ * indicate that it has an all-bits-zero value.
+ */
+ cache->core2_fixed_ctr_ctrl = 0;
+
+ /*
+ * To ensure that MSR_OFFCORE_RSP[0..1] are not written to
+ * on processors that do not have them, each CPU cache must
+ * indicate that they have all-bits-zero values.
+ */
+ cache->nhlm_offcore_rsp[0] = 0;
+ cache->nhlm_offcore_rsp[1] = 0;
+}
+
+static void perfctr_cpu_init_one(void *ignore)
{
/* PREEMPT note: when called via smp_call_function(),
this is in IRQ context with preemption disabled. */
- perfctr_cpu_clear_counters();
- if( cpu_has_apic )
+ perfctr_cpu_clear_counters(1);
+ perfctr_cpu_invalidate_cache();
+ if (cpu_has_apic)
apic_write(APIC_LVTPC, LOCAL_PERFCTR_VECTOR);
- if( perfctr_info.cpu_features & PERFCTR_FEATURE_RDPMC )
+ if (perfctr_info.cpu_features & PERFCTR_FEATURE_RDPMC)
set_in_cr4_local(X86_CR4_PCE);
}
-static void __exit perfctr_cpu_exit_one(void *ignore)
+static void perfctr_cpu_exit_one(void *ignore)
{
/* PREEMPT note: when called via smp_call_function(),
this is in IRQ context with preemption disabled. */
- perfctr_cpu_clear_counters();
- if( cpu_has_apic )
+ perfctr_cpu_clear_counters(0);
+ perfctr_cpu_invalidate_cache();
+ if (cpu_has_apic)
apic_write(APIC_LVTPC, APIC_DM_NMI | APIC_LVT_MASKED);
- if( perfctr_info.cpu_features & PERFCTR_FEATURE_RDPMC )
+ if (perfctr_info.cpu_features & PERFCTR_FEATURE_RDPMC)
clear_in_cr4_local(X86_CR4_PCE);
}
-#if defined(NMI_LOCAL_APIC) && defined(CONFIG_PM)
+#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PM)
static void perfctr_pm_suspend(void)
{
@@ -1508,11 +2186,16 @@ static void perfctr_pm_resume(void)
printk("perfctr/x86: PM resume\n");
}
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,71)
-
#include <linux/sysdev.h>
-static int perfctr_device_suspend(struct sys_device *dev, u32 state)
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,14)
+typedef pm_message_t perfctr_suspend_state_t;
+#else
+typedef u32 perfctr_suspend_state_t;
+#endif
+
+static int perfctr_device_suspend(struct sys_device *dev,
+ perfctr_suspend_state_t state)
{
perfctr_pm_suspend();
return 0;
@@ -1525,7 +2208,11 @@ static int perfctr_device_resume(struct sys_device *dev)
}
static struct sysdev_class perfctr_sysclass = {
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,25)
+ .name = "perfctr",
+#else
set_kset_name("perfctr"),
+#endif
.resume = perfctr_device_resume,
.suspend = perfctr_device_suspend,
};
@@ -1535,98 +2222,209 @@ static struct sys_device device_perfctr = {
.cls = &perfctr_sysclass,
};
-static void __init x86_pm_init(void)
+static void x86_pm_init(void)
{
- if( sysdev_class_register(&perfctr_sysclass) == 0 )
- sys_device_register(&device_perfctr);
+ if (sysdev_class_register(&perfctr_sysclass) == 0)
+ sysdev_register(&device_perfctr);
}
-static void __exit x86_pm_exit(void)
+static void x86_pm_exit(void)
{
- sys_device_unregister(&device_perfctr);
+ sysdev_unregister(&device_perfctr);
sysdev_class_unregister(&perfctr_sysclass);
}
-#else /* 2.4 kernel */
+#else /* CONFIG_X86_LOCAL_APIC && CONFIG_PM */
+
+static inline void x86_pm_init(void) { }
+static inline void x86_pm_exit(void) { }
+
+#endif /* CONFIG_X86_LOCAL_APIC && CONFIG_PM */
+
+#ifdef CONFIG_X86_LOCAL_APIC
-static int x86_pm_callback(struct pm_dev *dev, pm_request_t rqst, void *data)
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,6)
+static int reserve_lapic_nmi(void)
{
- switch( rqst ) {
- case PM_SUSPEND:
- perfctr_pm_suspend();
- break;
- case PM_RESUME:
- perfctr_pm_resume();
- break;
+ int ret = 0;
+ if (nmi_perfctr_msr) {
+ nmi_perfctr_msr = 0;
+ disable_lapic_nmi_watchdog();
+ ret = 1;
}
- return 0;
+ return ret;
}
-static struct pm_dev *x86_pmdev;
+static inline void release_lapic_nmi(void) { }
+#endif
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19)
-static void __init x86_pm_init(void)
+static void perfctr_release_perfctr_range(unsigned int first_msr, unsigned int nr_msrs)
{
- x86_pmdev = apic_pm_register(PM_SYS_DEV, 0, x86_pm_callback);
+ unsigned int i;
+
+ for(i = 0; i < nr_msrs; ++i)
+ release_perfctr_nmi(first_msr + i);
}
-static void __exit x86_pm_exit(void)
+static int perfctr_reserve_perfctr_range(unsigned int first_msr, unsigned int nr_msrs)
{
- if( x86_pmdev ) {
- apic_pm_unregister(x86_pmdev);
- x86_pmdev = NULL;
- }
+ unsigned int i;
+
+ for(i = 0; i < nr_msrs; ++i)
+ if (!reserve_perfctr_nmi(first_msr + i)) {
+ printk(KERN_ERR "perfctr/x86.c: failed to reserve perfctr MSR %#x\n",
+ first_msr + i);
+ perfctr_release_perfctr_range(first_msr, i);
+ return -1;
+ }
+ return 0;
}
-#endif /* 2.4 kernel */
+static void perfctr_release_evntsel_range(unsigned int first_msr, unsigned int nr_msrs)
+{
+ unsigned int i;
-#else
+ for(i = 0; i < nr_msrs; ++i)
+ release_evntsel_nmi(first_msr + i);
+}
-static inline void x86_pm_init(void) { }
-static inline void x86_pm_exit(void) { }
+static int perfctr_reserve_evntsel_range(unsigned int first_msr, unsigned int nr_msrs)
+{
+ unsigned int i;
+
+ for(i = 0; i < nr_msrs; ++i)
+ if (!reserve_evntsel_nmi(first_msr + i)) {
+ printk(KERN_ERR "perfctr/x86.c: failed to reserve evntsel MSR %#x\n",
+ first_msr + i);
+ perfctr_release_evntsel_range(first_msr, i);
+ return -1;
+ }
+ return 0;
+}
-#endif /* NMI_LOCAL_APIC && CONFIG_PM */
+static void perfctr_release_counters_cpu(void *ignore)
+{
+ const struct perfctr_pmu_msrs *pmu;
+ const struct perfctr_msr_range *msrs;
+ int i;
-#ifdef NMI_LOCAL_APIC
+ pmu = pmu_msrs;
+ if (!pmu)
+ return;
+ msrs = pmu->perfctrs;
+ if (msrs)
+ for(i = 0; msrs[i].first_msr; ++i)
+ perfctr_release_perfctr_range(msrs[i].first_msr, msrs[i].nr_msrs);
+ msrs = pmu->evntsels;
+ if (msrs)
+ for(i = 0; msrs[i].first_msr; ++i)
+ perfctr_release_evntsel_range(msrs[i].first_msr, msrs[i].nr_msrs);
+}
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,67)
-static void __init disable_lapic_nmi_watchdog(void)
+static void perfctr_release_counters(void)
{
-#ifdef CONFIG_PM
- if( nmi_pmdev ) {
- apic_pm_unregister(nmi_pmdev);
- nmi_pmdev = 0;
- }
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
+ perfctr_release_counters_cpu(NULL);
+#else
+ on_each_cpu(perfctr_release_counters_cpu, NULL, 1);
#endif
}
-#endif
-static void __init disable_nmi_watchdog(void)
+static void perfctr_reserve_counters_cpu(void *error)
{
- if( nmi_perfctr_msr ) {
- nmi_perfctr_msr = 0;
- disable_lapic_nmi_watchdog();
- printk(KERN_NOTICE "perfctr: disabled lapic_nmi_watchdog\n");
+ const struct perfctr_pmu_msrs *pmu;
+ const struct perfctr_msr_range *msrs;
+ int i;
+
+ pmu = pmu_msrs;
+ if (!pmu)
+ return;
+ msrs = pmu->perfctrs;
+ if (msrs) {
+ for(i = 0; msrs[i].first_msr; ++i)
+ if (perfctr_reserve_perfctr_range(msrs[i].first_msr, msrs[i].nr_msrs))
+ goto err_perfctrs;
}
+ msrs = pmu->evntsels;
+ if (msrs) {
+ for(i = 0; msrs[i].first_msr; ++i)
+ if (perfctr_reserve_evntsel_range(msrs[i].first_msr, msrs[i].nr_msrs))
+ goto err_evntsels;
+ }
+ return;
+
+ err_evntsels:
+ while (--i >= 0)
+ perfctr_release_evntsel_range(msrs[i].first_msr, msrs[i].nr_msrs);
+
+ msrs = pmu->perfctrs;
+ if (!msrs)
+ goto err;
+ for(i = 0; msrs[i].first_msr; ++i)
+ ;
+ err_perfctrs:
+ while (--i >= 0)
+ perfctr_release_perfctr_range(msrs[i].first_msr, msrs[i].nr_msrs);
+ err:
+ atomic_set((atomic_t*)error, -1);
}
+static int perfctr_reserve_counters(void)
+{
+ atomic_t error = ATOMIC_INIT(0);
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
+ perfctr_reserve_counters_cpu(&error);
#else
+ on_each_cpu(perfctr_reserve_counters_cpu, &error, 1);
+#endif
+ return atomic_read(&error);
+}
-static inline void disable_nmi_watchdog(void) { }
+static int reserve_lapic_nmi(void)
+{
+ if (nmi_watchdog != NMI_LOCAL_APIC)
+ return 0;
+ if (atomic_read(&nmi_active) <= 0)
+ return 0;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)
+ disable_lapic_nmi_watchdog();
+#else
+ on_each_cpu(stop_apic_nmi_watchdog, NULL, 1);
+#endif
+ return perfctr_reserve_counters();
+}
+static void release_lapic_nmi(void)
+{
+ perfctr_release_counters();
+ if (nmi_watchdog != NMI_LOCAL_APIC)
+ return;
+ if (atomic_read(&nmi_active) != 0)
+ return;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)
+ enable_lapic_nmi_watchdog();
+#else
+ on_each_cpu(setup_apic_nmi_watchdog, NULL, 1);
#endif
+}
+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) */
-static void invalidate_per_cpu_cache(void)
+#else /* CONFIG_X86_LOCAL_APIC */
+static inline int reserve_lapic_nmi(void) { return 0; }
+static inline void release_lapic_nmi(void) { }
+#endif /* CONFIG_X86_LOCAL_APIC */
+
+static void __init do_init_tests(void)
{
- /*
- * per_cpu_cache[] is initialised to contain "impossible"
- * evntsel values guaranteed to differ from anything accepted
- * by perfctr_cpu_update_control(). This way, initialisation of
- * a CPU's evntsel MSRs will happen automatically the first time
- * perfctr_cpu_write_control() executes on it.
- * All-bits-one works for all currently supported processors.
- * The memset also sets the ids to -1, which is intentional.
- */
- memset(per_cpu_cache, ~0, sizeof per_cpu_cache);
+#ifdef CONFIG_PERFCTR_INIT_TESTS
+ if (reserve_lapic_nmi() >= 0) {
+ perfctr_x86_init_tests();
+ release_lapic_nmi();
+ }
+#endif
}
int __init perfctr_cpu_init(void)
@@ -1639,8 +2437,8 @@ int __init perfctr_cpu_init(void)
by the init procedures if necessary. */
perfctr_info.cpu_features = PERFCTR_FEATURE_RDPMC | PERFCTR_FEATURE_RDTSC;
- if( cpu_has_msr ) {
- switch( current_cpu_data.x86_vendor ) {
+ if (cpu_has_msr) {
+ switch (current_cpu_data.x86_vendor) {
case X86_VENDOR_INTEL:
err = intel_init();
break;
@@ -1654,34 +2452,13 @@ int __init perfctr_cpu_init(void)
err = centaur_init();
}
}
- if( err ) {
+ if (err) {
err = generic_init(); /* last resort */
- if( err )
+ if (err)
goto out;
}
- /*
- * Put the hardware in a sane state:
- * - finalise resolution of backpatchable call sites
- * - clear perfctr MSRs
- * - set up APIC_LVTPC
- * - set CR4.PCE [on permanently due to __flush_tlb_global()]
- * - install our default interrupt handler
- */
- if( perfctr_info.cpu_features & PERFCTR_FEATURE_RDPMC )
- mmu_cr4_features |= X86_CR4_PCE;
+ do_init_tests();
finalise_backpatching();
- perfctr_cpu_init_one(NULL);
- smp_call_function(perfctr_cpu_init_one, NULL, 1, 1);
- perfctr_cpu_set_ihandler(NULL);
- /*
- * Fix up the connection to the local APIC:
- * - disable and disconnect the NMI watchdog
- * - register our PM callback
- */
- disable_nmi_watchdog();
- x86_pm_init();
-
- invalidate_per_cpu_cache();
perfctr_info.cpu_khz = perfctr_cpu_khz();
perfctr_info.tsc_to_cpu_mult = 1;
@@ -1693,15 +2470,6 @@ int __init perfctr_cpu_init(void)
void __exit perfctr_cpu_exit(void)
{
- preempt_disable();
- if( perfctr_info.cpu_features & PERFCTR_FEATURE_RDPMC )
- mmu_cr4_features &= ~X86_CR4_PCE;
- perfctr_cpu_exit_one(NULL);
- smp_call_function(perfctr_cpu_exit_one, NULL, 1, 1);
- perfctr_cpu_set_ihandler(NULL);
- x86_pm_exit();
- /* XXX: restart nmi watchdog? */
- preempt_enable();
}
/****************************************************************
@@ -1710,35 +2478,50 @@ void __exit perfctr_cpu_exit(void)
* *
****************************************************************/
+static DEFINE_MUTEX(mutex);
static const char *current_service = 0;
const char *perfctr_cpu_reserve(const char *service)
{
- if( current_service )
- return current_service;
+ const char *ret;
+
+ mutex_lock(&mutex);
+ ret = current_service;
+ if (ret)
+ goto out_unlock;
+ ret = "unknown driver (oprofile?)";
+ if (reserve_lapic_nmi() < 0)
+ goto out_unlock;
current_service = service;
__module_get(THIS_MODULE);
- return 0;
-}
-
-static void perfctr_cpu_clear_one(void *ignore)
-{
- /* PREEMPT note: when called via smp_call_function(),
- this is in IRQ context with preemption disabled. */
- perfctr_cpu_clear_counters();
+ if (perfctr_info.cpu_features & PERFCTR_FEATURE_RDPMC)
+ mmu_cr4_features |= X86_CR4_PCE;
+ on_each_cpu(perfctr_cpu_init_one, NULL, 1);
+ perfctr_cpu_set_ihandler(NULL);
+ x86_pm_init();
+ ret = NULL;
+ out_unlock:
+ mutex_unlock(&mutex);
+ return ret;
}
void perfctr_cpu_release(const char *service)
{
- if( service != current_service ) {
+ mutex_lock(&mutex);
+ if (service != current_service) {
printk(KERN_ERR "%s: attempt by %s to release while reserved by %s\n",
__FUNCTION__, service, current_service);
- } else {
- /* power down the counters */
- invalidate_per_cpu_cache();
- on_each_cpu(perfctr_cpu_clear_one, NULL, 1, 1);
- perfctr_cpu_set_ihandler(NULL);
- current_service = 0;
- module_put(THIS_MODULE);
+ goto out_unlock;
}
+ /* power down the counters */
+ if (perfctr_info.cpu_features & PERFCTR_FEATURE_RDPMC)
+ mmu_cr4_features &= ~X86_CR4_PCE;
+ on_each_cpu(perfctr_cpu_exit_one, NULL, 1);
+ perfctr_cpu_set_ihandler(NULL);
+ x86_pm_exit();
+ current_service = 0;
+ release_lapic_nmi();
+ module_put(THIS_MODULE);
+ out_unlock:
+ mutex_unlock(&mutex);
}
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/x86_compat.h b/src/perfctr-2.6.x/linux/drivers/perfctr/x86_compat.h
index 20a5b93cd2b90b31961e24153e517ee2436eff73..0b33695d4de7b001af23f2976e9d11d2668a9ccd 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/x86_compat.h
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/x86_compat.h
@@ -1,41 +1,55 @@
-/* $Id$
+/* $Id: x86_compat.h,v 1.33.2.5 2009/01/23 17:01:02 mikpe Exp $
* Performance-monitoring counters driver.
- * x86-specific compatibility definitions for 2.4/2.6 kernels.
+ * x86/x86_64-specific compatibility definitions for 2.6 kernels.
*
- * Copyright (C) 2000-2003 Mikael Pettersson
+ * Copyright (C) 2000-2007, 2009 Mikael Pettersson
*/
-#include <linux/config.h>
#include <linux/version.h>
-
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,18)
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
+#include <linux/config.h>
+#endif
/* missing from <asm-i386/cpufeature.h> */
#define cpu_has_msr boot_cpu_has(X86_FEATURE_MSR)
-#else /* 2.4 */
-
-/* missing from <asm-i386/processor.h> */
-#ifndef cpu_has_mmx /* added in 2.4.22-pre3 */
-#define cpu_has_mmx (test_bit(X86_FEATURE_MMX, boot_cpu_data.x86_capability))
-#endif
-#define cpu_has_msr (test_bit(X86_FEATURE_MSR, boot_cpu_data.x86_capability))
-#ifndef cpu_has_ht /* added in 2.4.22-pre3 */
-#define cpu_has_ht (test_bit(28, boot_cpu_data.x86_capability))
+/* 2.6.24-rc1 changed cpu_data from behaving like an array indexed
+ by cpu to being a macro with a cpu parameter. This emulates the
+ macro-with-parameter form in older kernels. */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
+static inline struct cpuinfo_x86 *perfctr_cpu_data(int cpu)
+{
+ return &cpu_data[cpu];
+}
+#undef cpu_data
+#define cpu_data(cpu) (*perfctr_cpu_data((cpu)))
#endif
-#endif /* 2.4 */
-
-/* irq_enter() and irq_exit() take two parameters in 2.4. However,
- we only use them to disable preemption in the interrupt handler,
- which isn't needed in non-preemptive 2.4 kernels. */
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
-#ifdef CONFIG_PREEMPT
-#error "not yet ported to 2.4+PREEMPT"
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16) && !defined(CONFIG_X86_64)
+/* Stop speculative execution */
+static inline void sync_core(void)
+{
+ int tmp;
+ asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
+}
#endif
-#undef irq_enter
-#undef irq_exit
-#define irq_enter() do{}while(0)
-#define irq_exit() do{}while(0)
+
+/* cpuid_count() was added in the 2.6.12 standard kernel, but it's been
+ backported to some distribution kernels including the 2.6.9-22 RHEL4
+ kernel. For simplicity, always use our version in older kernels. */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,12)
+/* Some CPUID calls want 'count' to be placed in ecx */
+static inline void perfctr_cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
+ int *edx)
+{
+ __asm__("cpuid"
+ : "=a" (*eax),
+ "=b" (*ebx),
+ "=c" (*ecx),
+ "=d" (*edx)
+ : "0" (op), "c" (count));
+}
+#undef cpuid_count
+#define cpuid_count(o,c,eax,ebx,ecx,edx) perfctr_cpuid_count((o),(c),(eax),(ebx),(ecx),(edx))
#endif
extern unsigned int perfctr_cpu_khz(void);
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/x86_setup.c b/src/perfctr-2.6.x/linux/drivers/perfctr/x86_setup.c
index 0cb777ce821f22f115ecee83545ea69438d8abfb..d5f972fab01544ea9f20b4e2a789c8b9c8abe73b 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/x86_setup.c
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/x86_setup.c
@@ -1,10 +1,13 @@
-/* $Id$
+/* $Id: x86_setup.c,v 1.47.2.9 2009/01/23 17:21:20 mikpe Exp $
* Performance-monitoring counters driver.
- * x86-specific kernel-resident code.
+ * x86/x86_64-specific kernel-resident code.
*
- * Copyright (C) 1999-2004 Mikael Pettersson
+ * Copyright (C) 1999-2007, 2009 Mikael Pettersson
*/
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
#include <linux/config.h>
+#endif
#include <linux/module.h>
#include <linux/init.h>
#include <linux/kernel.h>
@@ -17,95 +20,49 @@
#include "x86_compat.h"
#include "compat.h"
-/* XXX: belongs to a virtual_compat.c file */
-#if PERFCTR_CPUS_FORBIDDEN_MASK_NEEDED && defined(CONFIG_PERFCTR_VIRTUAL) && LINUX_VERSION_CODE < KERNEL_VERSION(2,4,21) && !defined(HAVE_SET_CPUS_ALLOWED)
-/**
- * set_cpus_allowed() - change a given task's processor affinity
- * @p: task to bind
- * @new_mask: bitmask of allowed processors
- *
- * Upon return, the task is running on a legal processor. Note the caller
- * must have a valid reference to the task: it must not exit() prematurely.
- * This call can sleep; do not hold locks on call.
- */
-void set_cpus_allowed(struct task_struct *p, unsigned long new_mask)
+#ifdef CONFIG_X86_LOCAL_APIC
+static void perfctr_default_ihandler(unsigned long pc)
{
- new_mask &= cpu_online_map;
- BUG_ON(!new_mask);
-
- /* This must be our own, safe, call from sys_vperfctr_control(). */
+}
- p->cpus_allowed = new_mask;
+static perfctr_ihandler_t perfctr_ihandler = perfctr_default_ihandler;
+static unsigned int interrupts_masked[NR_CPUS] __cacheline_aligned;
- /*
- * If the task is on a no-longer-allowed processor, we need to move
- * it. If the task is not current, then set need_resched and send
- * its processor an IPI to reschedule.
- */
- if (!(p->cpus_runnable & p->cpus_allowed)) {
- if (p != current) {
- p->need_resched = 1;
- smp_send_reschedule(p->processor);
- }
- /*
- * Wait until we are on a legal processor. If the task is
- * current, then we should be on a legal processor the next
- * time we reschedule. Otherwise, we need to wait for the IPI.
- */
- while (!(p->cpus_runnable & p->cpus_allowed))
- schedule();
- }
+void __perfctr_cpu_mask_interrupts(void)
+{
+ interrupts_masked[smp_processor_id()] = 1;
}
-EXPORT_SYMBOL(set_cpus_allowed);
-#endif
-#if PERFCTR_INTERRUPT_SUPPORT
-static void perfctr_default_ihandler(unsigned long pc)
+void __perfctr_cpu_unmask_interrupts(void)
{
+ interrupts_masked[smp_processor_id()] = 0;
}
-static perfctr_ihandler_t perfctr_ihandler = perfctr_default_ihandler;
-
asmlinkage void smp_perfctr_interrupt(struct pt_regs *regs)
{
/* PREEMPT note: invoked via an interrupt gate, which
masks interrupts. We're still on the originating CPU. */
/* XXX: recursive interrupts? delay the ACK, mask LVTPC, or queue? */
ack_APIC_irq();
+ if (interrupts_masked[smp_processor_id()])
+ return;
irq_enter();
- (*perfctr_ihandler)(regs->eip);
+ (*perfctr_ihandler)(instruction_pointer(regs));
irq_exit();
}
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,21)
-#define BUILD_PERFCTR_INTERRUPT(x,v) XBUILD_PERFCTR_INTERRUPT(x,v)
-#define XBUILD_PERFCTR_INTERRUPT(x,v) \
-__asm__( \
- "\n.text\n\t" \
- __ALIGN_STR "\n\t" \
- ".type " SYMBOL_NAME_STR(x) ",@function\n" \
- ".globl " SYMBOL_NAME_STR(x) "\n" \
-SYMBOL_NAME_STR(x) ":\n\t" \
- "pushl $" #v "-256\n\t" \
- SAVE_ALL \
- "pushl %esp\n\t" \
- "call " SYMBOL_NAME_STR(smp_ ## x) "\n\t" \
- "addl $4,%esp\n\t" \
- "jmp ret_from_intr\n\t" \
- ".size " SYMBOL_NAME_STR(x) ",.-" SYMBOL_NAME_STR(x) "\n" \
- ".previous\n");
-BUILD_PERFCTR_INTERRUPT(perfctr_interrupt,LOCAL_PERFCTR_VECTOR)
-#endif /* < 2.4.21 */
-
void perfctr_cpu_set_ihandler(perfctr_ihandler_t ihandler)
{
perfctr_ihandler = ihandler ? ihandler : perfctr_default_ihandler;
}
#endif
+#if defined(__x86_64__) || LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,13)
+extern unsigned int cpu_khz;
+#else
extern unsigned long cpu_khz;
+#endif
-/* Wrapper to avoid namespace clash in RedHat 8.0's 2.4.18-14 kernel. */
unsigned int perfctr_cpu_khz(void)
{
return cpu_khz;
@@ -115,19 +72,26 @@ unsigned int perfctr_cpu_khz(void)
EXPORT_SYMBOL_mmu_cr4_features;
EXPORT_SYMBOL(perfctr_cpu_khz);
-#ifdef NMI_LOCAL_APIC
-EXPORT_SYMBOL(nmi_perfctr_msr);
+#ifdef CONFIG_X86_LOCAL_APIC
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,67) && defined(CONFIG_PM)
-EXPORT_SYMBOL(apic_pm_register);
-EXPORT_SYMBOL(apic_pm_unregister);
-EXPORT_SYMBOL(nmi_pmdev);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19)
+#include <asm/nmi.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)
+EXPORT_SYMBOL(disable_lapic_nmi_watchdog);
+EXPORT_SYMBOL(enable_lapic_nmi_watchdog);
+#else
+EXPORT_SYMBOL(setup_apic_nmi_watchdog);
+EXPORT_SYMBOL(stop_apic_nmi_watchdog);
+#endif
#endif
-#endif /* NMI_LOCAL_APIC */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,6)
+EXPORT_SYMBOL(nmi_perfctr_msr);
+#endif
-#if PERFCTR_INTERRUPT_SUPPORT
+EXPORT_SYMBOL(__perfctr_cpu_mask_interrupts);
+EXPORT_SYMBOL(__perfctr_cpu_unmask_interrupts);
EXPORT_SYMBOL(perfctr_cpu_set_ihandler);
-#endif /* PERFCTR_INTERRUPT_SUPPORT */
+#endif /* CONFIG_X86_LOCAL_APIC */
#endif /* MODULE */
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/x86_tests.c b/src/perfctr-2.6.x/linux/drivers/perfctr/x86_tests.c
index a74da700acc464b61b153284db1b0a8e8f7ba20d..72e4975668ee4d95b57d98d0475e6286199d9e79 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/x86_tests.c
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/x86_tests.c
@@ -1,10 +1,13 @@
-/* $Id$
+/* $Id: x86_tests.c,v 1.23.2.14 2007/10/07 17:18:32 mikpe Exp $
* Performance-monitoring counters driver.
- * Optional x86-specific init-time tests.
+ * Optional x86/x86_64-specific init-time tests.
*
- * Copyright (C) 1999-2003 Mikael Pettersson
+ * Copyright (C) 1999-2007 Mikael Pettersson
*/
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
#include <linux/config.h>
+#endif
#define __NO_VERSION__
#include <linux/module.h>
#include <linux/init.h>
@@ -13,9 +16,14 @@
#include <linux/perfctr.h>
#include <asm/msr.h>
#undef MSR_P6_PERFCTR0
+#undef MSR_P6_EVNTSEL0
+#undef MSR_K7_PERFCTR0
+#undef MSR_K7_EVNTSEL0
+#undef MSR_CORE_PERF_FIXED_CTR_CTRL
#undef MSR_P4_IQ_CCCR0
#undef MSR_P4_CRU_ESCR0
-#include "compat.h"
+#include <asm/fixmap.h>
+#include <asm/apic.h>
#include "x86_compat.h"
#include "x86_tests.h"
@@ -29,6 +37,8 @@
#define MSR_K7_PERFCTR0 0xC0010004
#define K7_EVNTSEL0_VAL (0xC0 | (3<<16) | (1<<22))
#define VC3_EVNTSEL1_VAL 0xC0
+#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38D
+#define CORE2_PMC_FIXED_CTR0 ((1<<30) | 0)
#define MSR_P4_IQ_COUNTER0 0x30C
#define MSR_P4_IQ_CCCR0 0x36C
#define MSR_P4_CRU_ESCR0 0x3B8
@@ -39,6 +49,20 @@
#define X2(S) S";"S
#define X8(S) X2(X2(X2(S)))
+#ifdef __x86_64__
+#define CR4MOV "movq"
+#else
+#define CR4MOV "movl"
+#endif
+
+#ifndef CONFIG_X86_LOCAL_APIC
+#undef apic_write
+#define apic_write(reg,vector) do{}while(0)
+#endif
+
+#define rdtsc_low(low) \
+ __asm__ __volatile__("rdtsc" : "=a"(low) : : "edx")
+
static void __init do_rdpmc(unsigned pmc, unsigned unused2)
{
unsigned i;
@@ -63,16 +87,16 @@ static void __init do_wrmsr(unsigned msr, unsigned data)
static void __init do_rdcr4(unsigned unused1, unsigned unused2)
{
unsigned i;
- unsigned dummy;
+ unsigned long dummy;
for(i = 0; i < NITER/8; ++i)
- __asm__ __volatile__(X8("movl %%cr4,%0") : "=r"(dummy));
+ __asm__ __volatile__(X8(CR4MOV" %%cr4,%0") : "=r"(dummy));
}
static void __init do_wrcr4(unsigned cr4, unsigned unused2)
{
unsigned i;
for(i = 0; i < NITER/8; ++i)
- __asm__ __volatile__(X8("movl %0,%%cr4") : : "r"(cr4));
+ __asm__ __volatile__(X8(CR4MOV" %0,%%cr4") : : "r"((long)cr4));
}
static void __init do_rdtsc(unsigned unused1, unsigned unused2)
@@ -82,6 +106,36 @@ static void __init do_rdtsc(unsigned unused1, unsigned unused2)
__asm__ __volatile__(X8("rdtsc") : : : "eax", "edx");
}
+static void __init do_wrlvtpc(unsigned val, unsigned unused2)
+{
+ unsigned i;
+ for(i = 0; i < NITER/8; ++i) {
+ apic_write(APIC_LVTPC, val);
+ apic_write(APIC_LVTPC, val);
+ apic_write(APIC_LVTPC, val);
+ apic_write(APIC_LVTPC, val);
+ apic_write(APIC_LVTPC, val);
+ apic_write(APIC_LVTPC, val);
+ apic_write(APIC_LVTPC, val);
+ apic_write(APIC_LVTPC, val);
+ }
+}
+
+static void __init do_sync_core(unsigned unused1, unsigned unused2)
+{
+ unsigned i;
+ for(i = 0; i < NITER/8; ++i) {
+ sync_core();
+ sync_core();
+ sync_core();
+ sync_core();
+ sync_core();
+ sync_core();
+ sync_core();
+ sync_core();
+ }
+}
+
static void __init do_empty_loop(unsigned unused1, unsigned unused2)
{
unsigned i;
@@ -92,17 +146,19 @@ static void __init do_empty_loop(unsigned unused1, unsigned unused2)
static unsigned __init run(void (*doit)(unsigned, unsigned),
unsigned arg1, unsigned arg2)
{
- unsigned start, dummy, stop;
- rdtsc(start, dummy);
+ unsigned start, stop;
+ sync_core();
+ rdtsc_low(start);
(*doit)(arg1, arg2); /* should take < 2^32 cycles to complete */
- rdtsc(stop, dummy);
+ sync_core();
+ rdtsc_low(stop);
return stop - start;
}
static void __init init_tests_message(void)
{
printk(KERN_INFO "Please email the following PERFCTR INIT lines "
- "to mikpe@csd.uu.se\n"
+ "to mikpe@it.uu.se\n"
KERN_INFO "To remove this message, rebuild the driver "
"with CONFIG_PERFCTR_INIT_TESTS=n\n");
printk(KERN_INFO "PERFCTR INIT: vendor %u, family %u, model %u, stepping %u, clock %u kHz\n",
@@ -115,15 +171,15 @@ static void __init init_tests_message(void)
static void __init
measure_overheads(unsigned msr_evntsel0, unsigned evntsel0, unsigned msr_perfctr0,
- unsigned msr_cccr, unsigned cccr_val)
+ unsigned msr_cccr, unsigned cccr_val, unsigned is_core2)
{
int i;
- unsigned int loop, ticks[11];
- const char *name[11];
+ unsigned int loop, ticks[15];
+ const char *name[15];
- if( msr_evntsel0 )
+ if (msr_evntsel0)
wrmsr(msr_evntsel0, 0, 0);
- if( msr_cccr )
+ if (msr_cccr)
wrmsr(msr_cccr, 0, 0);
name[0] = "rdtsc";
@@ -149,12 +205,21 @@ measure_overheads(unsigned msr_evntsel0, unsigned evntsel0, unsigned msr_perfctr
ticks[9] = msr_cccr ? run(do_rdmsr, msr_cccr, 0) : 0;
name[10] = "wrmsr (cccr)";
ticks[10] = msr_cccr ? run(do_wrmsr, msr_cccr, cccr_val) : 0;
+ name[11] = "write LVTPC";
+ ticks[11] = (perfctr_info.cpu_features & PERFCTR_FEATURE_PCINT)
+ ? run(do_wrlvtpc, APIC_DM_NMI|APIC_LVT_MASKED, 0) : 0;
+ name[12] = "sync_core";
+ ticks[12] = run(do_sync_core, 0, 0);
+ name[13] = "read fixed_ctr0";
+ ticks[13] = is_core2 ? run(do_rdpmc, CORE2_PMC_FIXED_CTR0, 0) : 0;
+ name[14] = "wrmsr fixed_ctr_ctrl";
+ ticks[14] = is_core2 ? run(do_wrmsr, MSR_CORE_PERF_FIXED_CTR_CTRL, 0) : 0;
loop = run(do_empty_loop, 0, 0);
- if( msr_evntsel0 )
+ if (msr_evntsel0)
wrmsr(msr_evntsel0, 0, 0);
- if( msr_cccr )
+ if (msr_cccr)
wrmsr(msr_cccr, 0, 0);
init_tests_message();
@@ -162,7 +227,7 @@ measure_overheads(unsigned msr_evntsel0, unsigned evntsel0, unsigned msr_perfctr
printk(KERN_INFO "PERFCTR INIT: loop overhead is %u cycles\n", loop);
for(i = 0; i < ARRAY_SIZE(ticks); ++i) {
unsigned int x;
- if( !ticks[i] )
+ if (!ticks[i])
continue;
x = ((ticks[i] - loop) * 10) / NITER;
printk(KERN_INFO "PERFCTR INIT: %s cost is %u.%u cycles (%u total)\n",
@@ -170,23 +235,14 @@ measure_overheads(unsigned msr_evntsel0, unsigned evntsel0, unsigned msr_perfctr
}
}
-void __init perfctr_p5_init_tests(void)
-{
- measure_overheads(MSR_P5_CESR, P5_CESR_VAL, MSR_P5_CTR0, 0, 0);
-}
-
-void __init perfctr_p6_init_tests(void)
+#ifndef __x86_64__
+static inline void perfctr_p5_init_tests(void)
{
- measure_overheads(MSR_P6_EVNTSEL0, P6_EVNTSEL0_VAL, MSR_P6_PERFCTR0, 0, 0);
-}
-
-void __init perfctr_k7_init_tests(void)
-{
- measure_overheads(MSR_K7_EVNTSEL0, K7_EVNTSEL0_VAL, MSR_K7_PERFCTR0, 0, 0);
+ measure_overheads(MSR_P5_CESR, P5_CESR_VAL, MSR_P5_CTR0, 0, 0, 0);
}
#if !defined(CONFIG_X86_TSC)
-void __init perfctr_c6_init_tests(void)
+static inline void perfctr_c6_init_tests(void)
{
unsigned int cesr, dummy;
@@ -196,18 +252,74 @@ void __init perfctr_c6_init_tests(void)
}
#endif
-void __init perfctr_vc3_init_tests(void)
+static inline void perfctr_vc3_init_tests(void)
+{
+ measure_overheads(MSR_P6_EVNTSEL0+1, VC3_EVNTSEL1_VAL, MSR_P6_PERFCTR0+1, 0, 0, 0);
+}
+#endif /* !__x86_64__ */
+
+static inline void perfctr_p6_init_tests(void)
{
- measure_overheads(MSR_P6_EVNTSEL0+1, VC3_EVNTSEL1_VAL, MSR_P6_PERFCTR0+1, 0, 0);
+ measure_overheads(MSR_P6_EVNTSEL0, P6_EVNTSEL0_VAL, MSR_P6_PERFCTR0, 0, 0, 0);
}
-void __init perfctr_p4_init_tests(void)
+static inline void perfctr_core2_init_tests(void)
+{
+ measure_overheads(MSR_P6_EVNTSEL0, P6_EVNTSEL0_VAL, MSR_P6_PERFCTR0, 0, 0, 1);
+}
+
+static inline void perfctr_p4_init_tests(void)
{
measure_overheads(MSR_P4_CRU_ESCR0, P4_CRU_ESCR0_VAL, MSR_P4_IQ_COUNTER0,
- MSR_P4_IQ_CCCR0, P4_IQ_CCCR0_VAL);
+ MSR_P4_IQ_CCCR0, P4_IQ_CCCR0_VAL, 0);
}
-void __init perfctr_generic_init_tests(void)
+static inline void perfctr_k7_init_tests(void)
{
- measure_overheads(0, 0, 0, 0, 0);
+ measure_overheads(MSR_K7_EVNTSEL0, K7_EVNTSEL0_VAL, MSR_K7_PERFCTR0, 0, 0, 0);
+}
+
+static inline void perfctr_generic_init_tests(void)
+{
+ measure_overheads(0, 0, 0, 0, 0, 0);
+}
+
+enum perfctr_x86_tests_type perfctr_x86_tests_type __initdata = PTT_UNKNOWN;
+
+void __init perfctr_x86_init_tests(void)
+{
+ switch (perfctr_x86_tests_type) {
+#ifndef __x86_64__
+ case PTT_P5: /* Intel P5, P5MMX; Cyrix 6x86MX, MII, III */
+ perfctr_p5_init_tests();
+ break;
+#if !defined(CONFIG_X86_TSC)
+ case PTT_WINCHIP: /* WinChip C6, 2, 3 */
+ perfctr_c6_init_tests();
+ break;
+#endif
+ case PTT_VC3: /* VIA C3 */
+ perfctr_vc3_init_tests();
+ break;
+#endif /* !__x86_64__ */
+ case PTT_P6: /* Intel PPro, PII, PIII, PENTM, CORE */
+ perfctr_p6_init_tests();
+ break;
+ case PTT_CORE2: /* Intel Core 2 */
+ perfctr_core2_init_tests();
+ break;
+ case PTT_P4: /* Intel P4 */
+ perfctr_p4_init_tests();
+ break;
+ case PTT_AMD: /* AMD K7, K8 */
+ perfctr_k7_init_tests();
+ break;
+ case PTT_GENERIC:
+ perfctr_generic_init_tests();
+ break;
+ default:
+ printk(KERN_INFO "%s: unknown CPU type %u\n",
+ __FUNCTION__, perfctr_x86_tests_type);
+ break;
+ }
}
diff --git a/src/perfctr-2.6.x/linux/drivers/perfctr/x86_tests.h b/src/perfctr-2.6.x/linux/drivers/perfctr/x86_tests.h
index 2fbbdf1d415f95ab3c9636b8db2280ef14b16495..165874d21d1b06b384e79e5cecf27be39f2ff409 100755
--- a/src/perfctr-2.6.x/linux/drivers/perfctr/x86_tests.h
+++ b/src/perfctr-2.6.x/linux/drivers/perfctr/x86_tests.h
@@ -1,25 +1,31 @@
-/* $Id$
+/* $Id: x86_tests.h,v 1.8.2.3 2007/10/07 17:18:32 mikpe Exp $
* Performance-monitoring counters driver.
- * Optional x86-specific init-time tests.
+ * Optional x86/x86_64-specific init-time tests.
*
- * Copyright (C) 1999-2002 Mikael Pettersson
+ * Copyright (C) 1999-2004, 2007 Mikael Pettersson
*/
+/* 'enum perfctr_x86_tests_type' classifies CPUs according
+ to relevance for perfctr_x86_init_tests(). */
+enum perfctr_x86_tests_type {
+ PTT_UNKNOWN,
+ PTT_GENERIC,
+ PTT_P5,
+ PTT_P6,
+ PTT_CORE2,
+ PTT_P4,
+ PTT_AMD,
+ PTT_WINCHIP,
+ PTT_VC3,
+};
+
+extern enum perfctr_x86_tests_type perfctr_x86_tests_type;
+
+static inline void perfctr_set_tests_type(enum perfctr_x86_tests_type t)
+{
#ifdef CONFIG_PERFCTR_INIT_TESTS
-extern void perfctr_p5_init_tests(void);
-extern void perfctr_p6_init_tests(void);
-extern void perfctr_k7_init_tests(void);
-extern void perfctr_c6_init_tests(void);
-extern void perfctr_vc3_init_tests(void);
-extern void perfctr_p4_init_tests(void);
-extern void perfctr_generic_init_tests(void);
-#else
-#define perfctr_p5_init_tests()
-#define perfctr_p6_init_tests()
-#define perfctr_k7_init_tests()
-#define perfctr_c6_init_tests()
-#define perfctr_vc3_init_tests()
-#define perfctr_p4_init_tests()
-#define perfctr_generic_init_tests()
+ perfctr_x86_tests_type = t;
#endif
-#define perfctr_mii_init_tests() perfctr_p5_init_tests()
+}
+
+extern void perfctr_x86_init_tests(void);
diff --git a/src/perfctr-2.6.x/linux/include/asm-arm/perfctr.h b/src/perfctr-2.6.x/linux/include/asm-arm/perfctr.h
index 0c67c9f77f212a3d5eedc548c58e122bb1812047..e4df907c2a8658f510323fd28cce89100e5b048b 100644
--- a/src/perfctr-2.6.x/linux/include/asm-arm/perfctr.h
+++ b/src/perfctr-2.6.x/linux/include/asm-arm/perfctr.h
@@ -1,7 +1,7 @@
-/* $Id$
+/* $Id: perfctr.h,v 1.1.2.2 2009/06/11 12:33:51 mikpe Exp $
* ARM/XScale Performance-Monitoring Counters driver
*
- * Copyright (C) 2005-2007 Mikael Pettersson
+ * Copyright (C) 2005-2007, 2009 Mikael Pettersson
*/
#ifndef _ASM_ARM_PERFCTR_H
#define _ASM_ARM_PERFCTR_H
@@ -132,7 +132,7 @@ extern void perfctr_cpu_release(const char *service);
Check that the new control data is valid.
Update the driver's private control data.
Returns a negative error code if the control data is invalid. */
-extern int perfctr_cpu_update_control(struct perfctr_cpu_state *state, int is_global);
+extern int perfctr_cpu_update_control(struct perfctr_cpu_state *state, cpumask_t *cpumask);
/* Read a-mode counters. Subtract from start and accumulate into sums.
Must be called with preemption disabled. */
diff --git a/src/perfctr-2.6.x/linux/include/asm-i386/perfctr.h b/src/perfctr-2.6.x/linux/include/asm-i386/perfctr.h
index 769589f15a6708643e493ae766484b6087ce0552..9a5c02be8598c4ba614ea814964e6d34b61af0d8 100755
--- a/src/perfctr-2.6.x/linux/include/asm-i386/perfctr.h
+++ b/src/perfctr-2.6.x/linux/include/asm-i386/perfctr.h
@@ -1,181 +1 @@
-/* $Id$
- * x86 Performance-Monitoring Counters driver
- *
- * Copyright (C) 1999-2004 Mikael Pettersson
- */
-#ifndef _ASM_I386_PERFCTR_H
-#define _ASM_I386_PERFCTR_H
-
-struct perfctr_sum_ctrs {
- unsigned long long tsc;
- unsigned long long pmc[18];
-};
-
-struct perfctr_cpu_control {
- unsigned int tsc_on;
- unsigned int nractrs; /* # of a-mode counters */
- unsigned int nrictrs; /* # of i-mode counters */
- unsigned int pmc_map[18];
- unsigned int evntsel[18]; /* one per counter, even on P5 */
- struct {
- unsigned int escr[18];
- unsigned int pebs_enable; /* for replay tagging */
- unsigned int pebs_matrix_vert; /* for replay tagging */
- } p4;
- int ireset[18]; /* < 0, for i-mode counters */
- unsigned int _reserved1;
- unsigned int _reserved2;
- unsigned int _reserved3;
- unsigned int _reserved4;
-};
-
-struct perfctr_cpu_state {
- unsigned int cstatus;
- struct { /* k1 is opaque in the user ABI */
- unsigned int id;
- const void *isuspend_cpu;
- } k1;
- /* The two tsc fields must be inlined. Placing them in a
- sub-struct causes unwanted internal padding on x86-64. */
- unsigned int tsc_start;
- unsigned long long tsc_sum;
- struct {
- unsigned int map;
- unsigned int start;
- unsigned long long sum;
- } pmc[18]; /* the size is not part of the user ABI */
-#ifdef __KERNEL__
- struct perfctr_cpu_control control;
- unsigned int p4_escr_map[18];
-#endif
-};
-
-/* cstatus is a re-encoding of control.tsc_on/nractrs/nrictrs
- which should have less overhead in most cases */
-
-static inline
-unsigned int perfctr_mk_cstatus(unsigned int tsc_on, unsigned int nractrs,
- unsigned int nrictrs)
-{
- return (tsc_on<<31) | (nrictrs<<16) | ((nractrs+nrictrs)<<8) | nractrs;
-}
-
-static inline unsigned int perfctr_cstatus_enabled(unsigned int cstatus)
-{
- return cstatus;
-}
-
-static inline int perfctr_cstatus_has_tsc(unsigned int cstatus)
-{
- return (int)cstatus < 0; /* test and jump on sign */
-}
-
-static inline unsigned int perfctr_cstatus_nractrs(unsigned int cstatus)
-{
- return cstatus & 0x7F; /* and with imm8 */
-}
-
-static inline unsigned int perfctr_cstatus_nrctrs(unsigned int cstatus)
-{
- return (cstatus >> 8) & 0x7F;
-}
-
-static inline unsigned int perfctr_cstatus_has_ictrs(unsigned int cstatus)
-{
- return cstatus & (0x7F << 16);
-}
-
-/*
- * 'struct siginfo' support for perfctr overflow signals.
- * In unbuffered mode, si_code is set to SI_PMC_OVF and a bitmask
- * describing which perfctrs overflowed is put in si_pmc_ovf_mask.
- * A bitmask is used since more than one perfctr can have overflowed
- * by the time the interrupt handler runs.
- *
- * glibc's <signal.h> doesn't seem to define __SI_FAULT or __SI_CODE(),
- * and including <asm/siginfo.h> as well may cause redefinition errors,
- * so the user and kernel values are different #defines here.
- */
-#ifdef __KERNEL__
-#define SI_PMC_OVF (__SI_FAULT|'P')
-#else
-#define SI_PMC_OVF ('P')
-#endif
-#define si_pmc_ovf_mask _sifields._pad[0] /* XXX: use an unsigned field later */
-
-/* version number for user-visible CPU-specific data */
-#define PERFCTR_CPU_VERSION 0x0500 /* 5.0 */
-
-#ifdef __KERNEL__
-
-#if defined(CONFIG_PERFCTR) || defined(CONFIG_PERFCTR_MODULE)
-
-/* Driver init/exit. */
-extern int perfctr_cpu_init(void);
-extern void perfctr_cpu_exit(void);
-
-/* CPU type name. */
-extern char *perfctr_cpu_name;
-
-/* Hardware reservation. */
-extern const char *perfctr_cpu_reserve(const char *service);
-extern void perfctr_cpu_release(const char *service);
-
-/* PRE: state has no running interrupt-mode counters.
- Check that the new control data is valid.
- Update the driver's private control data.
- is_global should be zero for per-process counters and non-zero
- for global-mode counters. This matters for HT P4s, alas.
- Returns a negative error code if the control data is invalid. */
-extern int perfctr_cpu_update_control(struct perfctr_cpu_state *state, int is_global);
-
-/* Read a-mode counters. Subtract from start and accumulate into sums.
- Must be called with preemption disabled. */
-extern void perfctr_cpu_suspend(struct perfctr_cpu_state *state);
-
-/* Write control registers. Read a-mode counters into start.
- Must be called with preemption disabled. */
-extern void perfctr_cpu_resume(struct perfctr_cpu_state *state);
-
-/* Perform an efficient combined suspend/resume operation.
- Must be called with preemption disabled. */
-extern void perfctr_cpu_sample(struct perfctr_cpu_state *state);
-
-/* The type of a perfctr overflow interrupt handler.
- It will be called in IRQ context, with preemption disabled. */
-typedef void (*perfctr_ihandler_t)(unsigned long pc);
-
-#if defined(CONFIG_X86_LOCAL_APIC)
-#define PERFCTR_INTERRUPT_SUPPORT 1
-#endif
-
-#if PERFCTR_INTERRUPT_SUPPORT
-extern void perfctr_cpu_set_ihandler(perfctr_ihandler_t);
-extern void perfctr_cpu_ireload(struct perfctr_cpu_state*);
-extern unsigned int perfctr_cpu_identify_overflow(struct perfctr_cpu_state*);
-#else
-static inline void perfctr_cpu_set_ihandler(perfctr_ihandler_t x) { }
-#endif
-
-#if defined(CONFIG_SMP)
-/* CPUs in `perfctr_cpus_forbidden_mask' must not use the
- performance-monitoring counters. TSC use is unrestricted.
- This is needed to prevent resource conflicts on hyper-threaded P4s.
- The declaration of `perfctr_cpus_forbidden_mask' is in the driver's
- private compat.h, since it needs to handle cpumask_t incompatibilities. */
-#define PERFCTR_CPUS_FORBIDDEN_MASK_NEEDED 1
-#endif
-
-#endif /* CONFIG_PERFCTR */
-
-#if defined(CONFIG_KPERFCTR) && PERFCTR_INTERRUPT_SUPPORT
-asmlinkage void perfctr_interrupt(struct pt_regs*);
-#define perfctr_vector_init() \
- set_intr_gate(LOCAL_PERFCTR_VECTOR, perfctr_interrupt)
-#else
-#define perfctr_vector_init() do{}while(0)
-#endif
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_I386_PERFCTR_H */
+#include <asm-x86/perfctr.h>
diff --git a/src/perfctr-2.6.x/linux/include/asm-powerpc/perfctr.h b/src/perfctr-2.6.x/linux/include/asm-powerpc/perfctr.h
index ab192430254e104792042a9e2cef673460de6fe8..eca8b99e088514b7bf54d2e7712b8b10442a711b 100644
--- a/src/perfctr-2.6.x/linux/include/asm-powerpc/perfctr.h
+++ b/src/perfctr-2.6.x/linux/include/asm-powerpc/perfctr.h
@@ -1,7 +1,7 @@
-/* $Id$
+/* $Id: perfctr.h,v 1.1.2.3 2009/06/11 12:33:51 mikpe Exp $
* PPC32 Performance-Monitoring Counters driver
*
- * Copyright (C) 2004 Mikael Pettersson
+ * Copyright (C) 2004-2007, 2009 Mikael Pettersson
*/
#ifndef _ASM_PPC_PERFCTR_H
#define _ASM_PPC_PERFCTR_H
@@ -134,7 +134,7 @@ extern void perfctr_cpu_release(const char *service);
Check that the new control data is valid.
Update the driver's private control data.
Returns a negative error code if the control data is invalid. */
-extern int perfctr_cpu_update_control(struct perfctr_cpu_state *state, int is_global);
+extern int perfctr_cpu_update_control(struct perfctr_cpu_state *state, cpumask_t *cpumask);
/* Read a-mode counters. Subtract from start and accumulate into sums.
Must be called with preemption disabled. */
diff --git a/src/perfctr-2.6.x/linux/include/asm-ppc/perfctr.h b/src/perfctr-2.6.x/linux/include/asm-ppc/perfctr.h
index a167865d76c77a8bc5b643793c767592482be7b7..60261ece971508b1b45b5525ef221079745d668a 100755
--- a/src/perfctr-2.6.x/linux/include/asm-ppc/perfctr.h
+++ b/src/perfctr-2.6.x/linux/include/asm-ppc/perfctr.h
@@ -1,170 +1 @@
-/* $Id$
- * PPC32 Performance-Monitoring Counters driver
- *
- * Copyright (C) 2004 Mikael Pettersson
- */
-#ifndef _ASM_PPC_PERFCTR_H
-#define _ASM_PPC_PERFCTR_H
-
-/* perfctr_info.cpu_type values */
-#define PERFCTR_PPC_604 1
-#define PERFCTR_PPC_604e 2
-#define PERFCTR_PPC_750 3
-#define PERFCTR_PPC_7400 4
-#define PERFCTR_PPC_7450 5
-
-struct perfctr_sum_ctrs {
- unsigned long long tsc;
- unsigned long long pmc[6];
-};
-
-struct perfctr_cpu_control {
- unsigned int tsc_on;
- unsigned int nractrs; /* # of a-mode counters */
- unsigned int nrictrs; /* # of i-mode counters */
- unsigned int pmc_map[6];
- unsigned int evntsel[6]; /* one per counter, even on P5 */
- int ireset[6]; /* [0,0x7fffffff], for i-mode counters */
- struct {
- unsigned int mmcr0; /* sans PMC{1,2}SEL */
- unsigned int mmcr2; /* only THRESHMULT */
- /* IABR/DABR/BAMR not supported */
- } ppc;
- unsigned int _reserved1;
- unsigned int _reserved2;
- unsigned int _reserved3;
- unsigned int _reserved4;
-};
-
-struct perfctr_cpu_state {
- unsigned int cstatus;
- struct { /* k1 is opaque in the user ABI */
- unsigned int id;
- const void *isuspend_cpu;
- } k1;
- /* The two tsc fields must be inlined. Placing them in a
- sub-struct causes unwanted internal padding on x86-64. */
- unsigned int tsc_start;
- unsigned long long tsc_sum;
- struct {
- unsigned int map;
- unsigned int start;
- unsigned long long sum;
- } pmc[6]; /* the size is not part of the user ABI */
-#ifdef __KERNEL__
- unsigned int ppc_mmcr[3];
- struct perfctr_cpu_control control;
-#endif
-};
-
-/* cstatus is a re-encoding of control.tsc_on/nractrs/nrictrs
- which should have less overhead in most cases */
-/* XXX: ppc driver internally also uses cstatus&(1<<30) */
-
-static inline
-unsigned int perfctr_mk_cstatus(unsigned int tsc_on, unsigned int nractrs,
- unsigned int nrictrs)
-{
- return (tsc_on<<31) | (nrictrs<<16) | ((nractrs+nrictrs)<<8) | nractrs;
-}
-
-static inline unsigned int perfctr_cstatus_enabled(unsigned int cstatus)
-{
- return cstatus;
-}
-
-static inline int perfctr_cstatus_has_tsc(unsigned int cstatus)
-{
- return (int)cstatus < 0; /* test and jump on sign */
-}
-
-static inline unsigned int perfctr_cstatus_nractrs(unsigned int cstatus)
-{
- return cstatus & 0x7F; /* and with imm8 */
-}
-
-static inline unsigned int perfctr_cstatus_nrctrs(unsigned int cstatus)
-{
- return (cstatus >> 8) & 0x7F;
-}
-
-static inline unsigned int perfctr_cstatus_has_ictrs(unsigned int cstatus)
-{
- return cstatus & (0x7F << 16);
-}
-
-/*
- * 'struct siginfo' support for perfctr overflow signals.
- * In unbuffered mode, si_code is set to SI_PMC_OVF and a bitmask
- * describing which perfctrs overflowed is put in si_pmc_ovf_mask.
- * A bitmask is used since more than one perfctr can have overflowed
- * by the time the interrupt handler runs.
- *
- * glibc's <signal.h> doesn't seem to define __SI_FAULT or __SI_CODE(),
- * and including <asm/siginfo.h> as well may cause redefinition errors,
- * so the user and kernel values are different #defines here.
- */
-#ifdef __KERNEL__
-#define SI_PMC_OVF (__SI_FAULT|'P')
-#else
-#define SI_PMC_OVF ('P')
-#endif
-#define si_pmc_ovf_mask _sifields._pad[0] /* XXX: use an unsigned field later */
-
-/* version number for user-visible CPU-specific data */
-#define PERFCTR_CPU_VERSION 0 /* XXX: not yet cast in stone */
-
-#ifdef __KERNEL__
-
-#if defined(CONFIG_PERFCTR) || defined(CONFIG_PERFCTR_MODULE)
-
-/* Driver init/exit. */
-extern int perfctr_cpu_init(void);
-extern void perfctr_cpu_exit(void);
-
-/* CPU type name. */
-extern char *perfctr_cpu_name;
-
-/* Hardware reservation. */
-extern const char *perfctr_cpu_reserve(const char *service);
-extern void perfctr_cpu_release(const char *service);
-
-/* PRE: state has no running interrupt-mode counters.
- Check that the new control data is valid.
- Update the driver's private control data.
- Returns a negative error code if the control data is invalid. */
-extern int perfctr_cpu_update_control(struct perfctr_cpu_state *state, int is_global);
-
-/* Read a-mode counters. Subtract from start and accumulate into sums.
- Must be called with preemption disabled. */
-extern void perfctr_cpu_suspend(struct perfctr_cpu_state *state);
-
-/* Write control registers. Read a-mode counters into start.
- Must be called with preemption disabled. */
-extern void perfctr_cpu_resume(struct perfctr_cpu_state *state);
-
-/* Perform an efficient combined suspend/resume operation.
- Must be called with preemption disabled. */
-extern void perfctr_cpu_sample(struct perfctr_cpu_state *state);
-
-/* The type of a perfctr overflow interrupt handler.
- It will be called in IRQ context, with preemption disabled. */
-typedef void (*perfctr_ihandler_t)(unsigned long pc);
-
-/* XXX: The hardware supports overflow interrupts, but the driver
- does not yet enable this due to an erratum in 750/7400/7410. */
-//#define PERFCTR_INTERRUPT_SUPPORT 1
-
-#if PERFCTR_INTERRUPT_SUPPORT
-extern void perfctr_cpu_set_ihandler(perfctr_ihandler_t);
-extern void perfctr_cpu_ireload(struct perfctr_cpu_state*);
-extern unsigned int perfctr_cpu_identify_overflow(struct perfctr_cpu_state*);
-#else
-static inline void perfctr_cpu_set_ihandler(perfctr_ihandler_t x) { }
-#endif
-
-#endif /* CONFIG_PERFCTR */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_PPC_PERFCTR_H */
+#include <asm-powerpc/perfctr.h>
diff --git a/src/perfctr-2.6.x/linux/include/asm-x86/perfctr.h b/src/perfctr-2.6.x/linux/include/asm-x86/perfctr.h
index a5aa1d68b97c277aca896697a1aad3317cf58006..c48a20e744712bdaa065fbcbd0091764bd364e04 100644
--- a/src/perfctr-2.6.x/linux/include/asm-x86/perfctr.h
+++ b/src/perfctr-2.6.x/linux/include/asm-x86/perfctr.h
@@ -1,7 +1,7 @@
-/* $Id$
+/* $Id: perfctr.h,v 1.1.2.16 2010/11/07 19:46:06 mikpe Exp $
* x86/x86_64 Performance-Monitoring Counters driver
*
- * Copyright (C) 1999-2008 Mikael Pettersson
+ * Copyright (C) 1999-2010 Mikael Pettersson
*/
#ifndef _ASM_X86_PERFCTR_H
#define _ASM_X86_PERFCTR_H
@@ -25,9 +25,13 @@
#define PERFCTR_X86_AMD_K8C 15 /* Revision C */
#define PERFCTR_X86_INTEL_P4M3 16 /* model 3 and above */
#define PERFCTR_X86_INTEL_CORE 17 /* family 6 model 14 */
-#define PERFCTR_X86_INTEL_CORE2 18 /* family 6 models 15 and 23 */
-#define PERFCTR_X86_AMD_FAM10H 19 /* family 10h */
+#define PERFCTR_X86_INTEL_CORE2 18 /* family 6, models 15, 22, 23, 29 */
+#define PERFCTR_X86_AMD_FAM10H 19 /* family 10h, family 11h */
#define PERFCTR_X86_AMD_FAM10 PERFCTR_X86_AMD_FAM10H /* XXX: compat crap, delete soon */
+#define PERFCTR_X86_INTEL_ATOM 20 /* family 6 model 28 */
+#define PERFCTR_X86_INTEL_NHLM 21 /* Nehalem: family 6 models 26, 30, 46 */
+#define PERFCTR_X86_INTEL_COREI7 PERFCTR_X86_INTEL_NHLM /* XXX: compat crap, delete soon */
+#define PERFCTR_X86_INTEL_WSTMR 22 /* Westmere: family 6 models 37, 44 */
struct perfctr_sum_ctrs {
unsigned long long tsc;
@@ -48,6 +52,12 @@ struct perfctr_cpu_control {
unsigned int pebs_matrix_vert; /* for replay tagging */
} p4;
unsigned int evntsel_high[18];
+ /* Note: nhlm.offcore_rsp[] must not overlap evntsel_high[],
+ instead we make it overlap the p4.pebs_ fields */
+ struct {
+ unsigned int _padding[18];
+ unsigned int offcore_rsp[2];
+ } nhlm;
}; /* XXX: should be a named field 'u', but that breaks source-code compatibility */
int ireset[18]; /* < 0, for i-mode counters */
unsigned int _reserved1;
@@ -162,10 +172,12 @@ extern void perfctr_cpu_release(const char *service);
/* PRE: state has no running interrupt-mode counters.
Check that the new control data is valid.
Update the driver's private control data.
- is_global should be zero for per-process counters and non-zero
- for global-mode counters. This matters for HT P4s, alas.
+ cpumask must be NULL for global-mode counters and non-NULL
+ for per-thread counters. If cpumask is non-NULL and the control
+ data requires the task to be restricted to a specific set of
+ CPUs, then *cpumask will be updated accordingly.
Returns a negative error code if the control data is invalid. */
-extern int perfctr_cpu_update_control(struct perfctr_cpu_state *state, int is_global);
+extern int perfctr_cpu_update_control(struct perfctr_cpu_state *state, cpumask_t *cpumask);
/* Read a-mode counters. Subtract from start and accumulate into sums.
Must be called with preemption disabled. */
@@ -206,8 +218,14 @@ static inline int perfctr_cpu_has_pending_interrupt(const struct perfctr_cpu_sta
#if defined(CONFIG_KPERFCTR) && defined(CONFIG_X86_LOCAL_APIC)
asmlinkage void perfctr_interrupt(struct pt_regs*);
+#include <linux/version.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) /* 2.6.27-rc1 */
+#define perfctr_vector_init() \
+ alloc_intr_gate(LOCAL_PERFCTR_VECTOR, perfctr_interrupt)
+#else
#define perfctr_vector_init() \
set_intr_gate(LOCAL_PERFCTR_VECTOR, perfctr_interrupt)
+#endif
#else
#define perfctr_vector_init() do{}while(0)
#endif
diff --git a/src/perfctr-2.6.x/linux/include/asm-x86_64/perfctr.h b/src/perfctr-2.6.x/linux/include/asm-x86_64/perfctr.h
index 704d1b77e112a3a0e1c9c0c253e555cf7306d4c2..9a5c02be8598c4ba614ea814964e6d34b61af0d8 100755
--- a/src/perfctr-2.6.x/linux/include/asm-x86_64/perfctr.h
+++ b/src/perfctr-2.6.x/linux/include/asm-x86_64/perfctr.h
@@ -1,166 +1 @@
-/* $Id$
- * x86_64 Performance-Monitoring Counters driver
- *
- * Based on <asm-i386/perfctr.h>:
- * - removed P5- and P4-only stuff
- * - reduced the number of counters from 18 to 4
- * - PERFCTR_INTERRUPT_SUPPORT is always 1
- * - perfctr_cpus_forbidden_mask never needed (it's P4-only)
- *
- * Copyright (C) 2003 Mikael Pettersson
- */
-#ifndef _ASM_X86_64_PERFCTR_H
-#define _ASM_X86_64_PERFCTR_H
-
-struct perfctr_sum_ctrs {
- unsigned long long tsc;
- unsigned long long pmc[4];
-};
-
-struct perfctr_cpu_control {
- unsigned int tsc_on;
- unsigned int nractrs; /* # of a-mode counters */
- unsigned int nrictrs; /* # of i-mode counters */
- unsigned int pmc_map[4];
- unsigned int evntsel[4]; /* one per counter, even on P5 */
- int ireset[4]; /* < 0, for i-mode counters */
- unsigned int _reserved1;
- unsigned int _reserved2;
- unsigned int _reserved3;
- unsigned int _reserved4;
-};
-
-struct perfctr_cpu_state {
- unsigned int cstatus;
- struct { /* k1 is opaque in the user ABI */
- unsigned int id;
- int isuspend_cpu;
- } k1;
- /* The two tsc fields must be inlined. Placing them in a
- sub-struct causes unwanted internal padding on x86-64. */
- unsigned int tsc_start;
- unsigned long long tsc_sum;
- struct {
- unsigned int map;
- unsigned int start;
- unsigned long long sum;
- } pmc[4]; /* the size is not part of the user ABI */
-#ifdef __KERNEL__
- struct perfctr_cpu_control control;
-#endif
-};
-
-/* cstatus is a re-encoding of control.tsc_on/nractrs/nrictrs
- which should have less overhead in most cases */
-
-static inline
-unsigned int perfctr_mk_cstatus(unsigned int tsc_on, unsigned int nractrs,
- unsigned int nrictrs)
-{
- return (tsc_on<<31) | (nrictrs<<16) | ((nractrs+nrictrs)<<8) | nractrs;
-}
-
-static inline unsigned int perfctr_cstatus_enabled(unsigned int cstatus)
-{
- return cstatus;
-}
-
-static inline int perfctr_cstatus_has_tsc(unsigned int cstatus)
-{
- return (int)cstatus < 0; /* test and jump on sign */
-}
-
-static inline unsigned int perfctr_cstatus_nractrs(unsigned int cstatus)
-{
- return cstatus & 0x7F; /* and with imm8 */
-}
-
-static inline unsigned int perfctr_cstatus_nrctrs(unsigned int cstatus)
-{
- return (cstatus >> 8) & 0x7F;
-}
-
-static inline unsigned int perfctr_cstatus_has_ictrs(unsigned int cstatus)
-{
- return cstatus & (0x7F << 16);
-}
-
-/*
- * 'struct siginfo' support for perfctr overflow signals.
- * In unbuffered mode, si_code is set to SI_PMC_OVF and a bitmask
- * describing which perfctrs overflowed is put in si_pmc_ovf_mask.
- * A bitmask is used since more than one perfctr can have overflowed
- * by the time the interrupt handler runs.
- *
- * glibc's <signal.h> doesn't seem to define __SI_FAULT or __SI_CODE(),
- * and including <asm/siginfo.h> as well may cause redefinition errors,
- * so the user and kernel values are different #defines here.
- */
-#ifdef __KERNEL__
-#define SI_PMC_OVF (__SI_FAULT|'P')
-#else
-#define SI_PMC_OVF ('P')
-#endif
-#define si_pmc_ovf_mask _sifields._pad[0] /* XXX: use an unsigned field later */
-
-/* version number for user-visible CPU-specific data */
-#define PERFCTR_CPU_VERSION 0x0500 /* 5.0 */
-
-#ifdef __KERNEL__
-
-#if defined(CONFIG_PERFCTR) || defined(CONFIG_PERFCTR_MODULE)
-
-/* Driver init/exit. */
-extern int perfctr_cpu_init(void);
-extern void perfctr_cpu_exit(void);
-
-/* CPU type name. */
-extern char *perfctr_cpu_name;
-
-/* Hardware reservation. */
-extern const char *perfctr_cpu_reserve(const char *service);
-extern void perfctr_cpu_release(const char *service);
-
-/* PRE: state has no running interrupt-mode counters.
- Check that the new control data is valid.
- Update the driver's private control data.
- Returns a negative error code if the control data is invalid. */
-extern int perfctr_cpu_update_control(struct perfctr_cpu_state *state, int is_global);
-
-/* Read a-mode counters. Subtract from start and accumulate into sums.
- Must be called with preemption disabled. */
-extern void perfctr_cpu_suspend(struct perfctr_cpu_state *state);
-
-/* Write control registers. Read a-mode counters into start.
- Must be called with preemption disabled. */
-extern void perfctr_cpu_resume(struct perfctr_cpu_state *state);
-
-/* Perform an efficient combined suspend/resume operation.
- Must be called with preemption disabled. */
-extern void perfctr_cpu_sample(struct perfctr_cpu_state *state);
-
-/* The type of a perfctr overflow interrupt handler.
- It will be called in IRQ context, with preemption disabled. */
-typedef void (*perfctr_ihandler_t)(unsigned long pc);
-
-/* CONFIG_X86_LOCAL_APIC is always defined on x86-64, so overflow
- interrupt support is always included. */
-#define PERFCTR_INTERRUPT_SUPPORT 1
-
-extern void perfctr_cpu_set_ihandler(perfctr_ihandler_t);
-extern void perfctr_cpu_ireload(struct perfctr_cpu_state*);
-extern unsigned int perfctr_cpu_identify_overflow(struct perfctr_cpu_state*);
-
-#endif /* CONFIG_PERFCTR */
-
-#if defined(CONFIG_KPERFCTR)
-extern void perfctr_interrupt(void);
-#define perfctr_vector_init() \
- set_intr_gate(LOCAL_PERFCTR_VECTOR, perfctr_interrupt)
-#else
-#define perfctr_vector_init() do{}while(0)
-#endif
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_X86_64_PERFCTR_H */
+#include <asm-x86/perfctr.h>
diff --git a/src/perfctr-2.6.x/linux/include/linux/perfctr.h b/src/perfctr-2.6.x/linux/include/linux/perfctr.h
index 4a601c5c291df7e471f1da423ca575af2a65d931..de4d38058f423b2572e5e45af91c10500db73060 100755
--- a/src/perfctr-2.6.x/linux/include/linux/perfctr.h
+++ b/src/perfctr-2.6.x/linux/include/linux/perfctr.h
@@ -1,7 +1,7 @@
-/* $Id$
+/* $Id: perfctr.h,v 1.69.2.6 2009/01/23 17:31:57 mikpe Exp $
* Performance-Monitoring Counters driver
*
- * Copyright (C) 1999-2003 Mikael Pettersson
+ * Copyright (C) 1999-2009 Mikael Pettersson
*/
#ifndef _LINUX_PERFCTR_H
#define _LINUX_PERFCTR_H
@@ -30,27 +30,9 @@ struct perfctr_cpu_mask {
/* abi_version values: Lower 16 bits contain the CPU data version, upper
16 bits contain the API version. Each half has a major version in its
upper 8 bits, and a minor version in its lower 8 bits. */
-#define PERFCTR_API_VERSION 0x0501 /* 5.1 */
+#define PERFCTR_API_VERSION 0x0502 /* 5.2 */
#define PERFCTR_ABI_VERSION ((PERFCTR_API_VERSION<<16)|PERFCTR_CPU_VERSION)
-/* cpu_type values */
-#define PERFCTR_X86_GENERIC 0 /* any x86 with rdtsc */
-#define PERFCTR_X86_INTEL_P5 1 /* no rdpmc */
-#define PERFCTR_X86_INTEL_P5MMX 2
-#define PERFCTR_X86_INTEL_P6 3
-#define PERFCTR_X86_INTEL_PII 4
-#define PERFCTR_X86_INTEL_PIII 5
-#define PERFCTR_X86_CYRIX_MII 6
-#define PERFCTR_X86_WINCHIP_C6 7 /* no rdtsc */
-#define PERFCTR_X86_WINCHIP_2 8 /* no rdtsc */
-#define PERFCTR_X86_AMD_K7 9
-#define PERFCTR_X86_VIA_C3 10 /* no pmc0 */
-#define PERFCTR_X86_INTEL_P4 11 /* model 0 and 1 */
-#define PERFCTR_X86_INTEL_P4M2 12 /* model 2 and above */
-#define PERFCTR_X86_AMD_K8 13
-#define PERFCTR_X86_INTEL_PENTM 14 /* Pentium M */
-#define PERFCTR_X86_AMD_K8C 15 /* Revision C */
-
/* cpu_features flag bits */
#define PERFCTR_FEATURE_RDPMC 0x01
#define PERFCTR_FEATURE_RDTSC 0x02
@@ -66,12 +48,15 @@ struct vperfctr_control {
int si_signo;
struct perfctr_cpu_control cpu_control;
unsigned int preserve;
- unsigned int _reserved1;
+ unsigned int flags;
unsigned int _reserved2;
unsigned int _reserved3;
unsigned int _reserved4;
};
+/* vperfctr_control flags bits */
+#define VPERFCTR_CONTROL_CLOEXEC 0x01 /* close (unlink) state before exec */
+
/* parameter in GPERFCTR_CONTROL command */
struct gperfctr_cpu_control {
unsigned int cpu;
@@ -133,13 +118,6 @@ extern int sys_perfctr_cpus_forbidden(struct perfctr_cpu_mask*);
#ifdef __KERNEL__
-/* Needed for perfctr_set_cpus_allowed() prototype. */
-#include <linux/version.h>
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) && !defined(HAVE_CPUMASK_T)
-typedef unsigned long cpumask_t;
-#define PERFCTR_HAVE_CPUMASK_T
-#endif
-
#ifdef CONFIG_PERFCTR_VIRTUAL
/*
@@ -148,8 +126,8 @@ typedef unsigned long cpumask_t;
struct vperfctr; /* opaque */
/* process management operations */
-extern struct vperfctr *__vperfctr_copy(struct vperfctr*);
extern void __vperfctr_exit(struct vperfctr*);
+extern void __vperfctr_flush(struct vperfctr*);
extern void __vperfctr_suspend(struct vperfctr*);
extern void __vperfctr_resume(struct vperfctr*);
extern void __vperfctr_sample(struct vperfctr*);
@@ -159,44 +137,60 @@ extern void __vperfctr_set_cpus_allowed(struct task_struct*, struct vperfctr*, c
extern struct vperfctr_stub {
struct module *owner;
void (*exit)(struct vperfctr*);
+ void (*flush)(struct vperfctr*);
void (*suspend)(struct vperfctr*);
void (*resume)(struct vperfctr*);
void (*sample)(struct vperfctr*);
-#if PERFCTR_CPUS_FORBIDDEN_MASK_NEEDED
+#ifdef CONFIG_PERFCTR_CPUS_FORBIDDEN_MASK
void (*set_cpus_allowed)(struct task_struct*, struct vperfctr*, cpumask_t);
#endif
} vperfctr_stub;
extern void _vperfctr_exit(struct vperfctr*);
+extern void _vperfctr_flush(struct vperfctr*);
#define _vperfctr_suspend(x) vperfctr_stub.suspend((x))
#define _vperfctr_resume(x) vperfctr_stub.resume((x))
#define _vperfctr_sample(x) vperfctr_stub.sample((x))
#define _vperfctr_set_cpus_allowed(x,y,z) (*vperfctr_stub.set_cpus_allowed)((x),(y),(z))
#else /* !CONFIG_PERFCTR_MODULE */
#define _vperfctr_exit(x) __vperfctr_exit((x))
+#define _vperfctr_flush(x) __vperfctr_flush((x))
#define _vperfctr_suspend(x) __vperfctr_suspend((x))
#define _vperfctr_resume(x) __vperfctr_resume((x))
#define _vperfctr_sample(x) __vperfctr_sample((x))
#define _vperfctr_set_cpus_allowed(x,y,z) __vperfctr_set_cpus_allowed((x),(y),(z))
#endif /* CONFIG_PERFCTR_MODULE */
-static inline void perfctr_copy_thread(struct thread_struct *thread)
+static inline void perfctr_copy_task(struct task_struct *tsk, struct pt_regs *regs)
{
- thread->perfctr = NULL;
+ tsk->thread.perfctr = NULL; /* inheritance is not yet implemented */
+}
+
+static inline void perfctr_release_task(struct task_struct *tsk)
+{
+ /* nothing to do until inheritance is implemented */
}
static inline void perfctr_exit_thread(struct thread_struct *thread)
{
struct vperfctr *perfctr;
perfctr = thread->perfctr;
- if( perfctr )
+ if (perfctr)
_vperfctr_exit(perfctr);
}
+static inline void perfctr_flush_thread(struct thread_struct *thread)
+{
+ struct vperfctr *perfctr;
+ perfctr = thread->perfctr;
+ if (perfctr)
+ _vperfctr_flush(perfctr);
+}
+
static inline void perfctr_suspend_thread(struct thread_struct *prev)
{
struct vperfctr *perfctr;
perfctr = prev->perfctr;
- if( perfctr )
+ if (perfctr)
_vperfctr_suspend(perfctr);
}
@@ -204,7 +198,7 @@ static inline void perfctr_resume_thread(struct thread_struct *next)
{
struct vperfctr *perfctr;
perfctr = next->perfctr;
- if( perfctr )
+ if (perfctr)
_vperfctr_resume(perfctr);
}
@@ -212,18 +206,18 @@ static inline void perfctr_sample_thread(struct thread_struct *thread)
{
struct vperfctr *perfctr;
perfctr = thread->perfctr;
- if( perfctr )
+ if (perfctr)
_vperfctr_sample(perfctr);
}
static inline void perfctr_set_cpus_allowed(struct task_struct *p, cpumask_t new_mask)
{
-#if PERFCTR_CPUS_FORBIDDEN_MASK_NEEDED
+#ifdef CONFIG_PERFCTR_CPUS_FORBIDDEN_MASK
struct vperfctr *perfctr;
task_lock(p);
perfctr = p->thread.perfctr;
- if( perfctr )
+ if (perfctr)
_vperfctr_set_cpus_allowed(p, perfctr, new_mask);
task_unlock(p);
#endif
@@ -231,8 +225,10 @@ static inline void perfctr_set_cpus_allowed(struct task_struct *p, cpumask_t new
#else /* !CONFIG_PERFCTR_VIRTUAL */
-static inline void perfctr_copy_thread(struct thread_struct *t) { }
+static inline void perfctr_copy_task(struct task_struct *p, struct pt_regs *r) { }
+static inline void perfctr_release_task(struct task_struct *p) { }
static inline void perfctr_exit_thread(struct thread_struct *t) { }
+static inline void perfctr_flush_thread(struct thread_struct *t) { }
static inline void perfctr_suspend_thread(struct thread_struct *t) { }
static inline void perfctr_resume_thread(struct thread_struct *t) { }
static inline void perfctr_sample_thread(struct thread_struct *t) { }
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.10 b/src/perfctr-2.6.x/patches/patch-kernel-2.6.10
index c1d43cca8cb4712172a7ffebe221a70a7b35d752..5685583f569abb6026fb502383ecab85a8ab7ff0 100755
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.10
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.10
@@ -1,15 +1,20 @@
---- linux-2.6.10.perfctr26/CREDITS.~1~ 2004-12-25 12:16:16.000000000 +0100
-+++ linux-2.6.10.perfctr26/CREDITS 2004-12-25 12:39:35.000000000 +0100
-@@ -2592,6 +2592,7 @@ N: Mikael Pettersson
- E: mikpe@csd.uu.se
- W: http://www.csd.uu.se/~mikpe/
+--- linux-2.6.10.perfctr26/CREDITS.~1~ 2008-06-22 20:48:52.000000000 +0200
++++ linux-2.6.10.perfctr26/CREDITS 2008-06-22 20:57:42.000000000 +0200
+@@ -2589,9 +2589,10 @@ S: Ottawa, Ontario
+ S: Canada K2P 0X8
+
+ N: Mikael Pettersson
+-E: mikpe@csd.uu.se
+-W: http://www.csd.uu.se/~mikpe/
++E: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/
D: Miscellaneous fixes
+D: Performance-monitoring counters driver
N: Reed H. Petty
E: rhp@draper.net
---- linux-2.6.10.perfctr26/Documentation/ioctl-number.txt.~1~ 2004-10-19 13:01:17.000000000 +0200
-+++ linux-2.6.10.perfctr26/Documentation/ioctl-number.txt 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/Documentation/ioctl-number.txt.~1~ 2008-06-22 20:48:52.000000000 +0200
++++ linux-2.6.10.perfctr26/Documentation/ioctl-number.txt 2008-06-22 20:57:10.000000000 +0200
@@ -188,6 +188,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -19,23 +24,23 @@
0xDD 00-3F ZFCP device driver see drivers/s390/scsi/
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
---- linux-2.6.10.perfctr26/MAINTAINERS.~1~ 2004-12-25 12:16:16.000000000 +0100
-+++ linux-2.6.10.perfctr26/MAINTAINERS 2004-12-25 12:40:03.000000000 +0100
+--- linux-2.6.10.perfctr26/MAINTAINERS.~1~ 2008-06-22 20:48:52.000000000 +0200
++++ linux-2.6.10.perfctr26/MAINTAINERS 2008-06-22 20:57:42.000000000 +0200
@@ -1731,6 +1731,12 @@ M: tsbogend@alpha.franken.de
L: linux-net@vger.kernel.org
S: Maintained
+PERFORMANCE-MONITORING COUNTERS DRIVER
+P: Mikael Pettersson
-+M: mikpe@csd.uu.se
-+W: http://www.csd.uu.se/~mikpe/linux/perfctr/
++M: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
+S: Maintained
+
PHRAM MTD DRIVER
P: J�rn Engel
M: joern@wh.fh-wedel.de
---- linux-2.6.10.perfctr26/arch/i386/Kconfig.~1~ 2004-12-25 12:16:17.000000000 +0100
-+++ linux-2.6.10.perfctr26/arch/i386/Kconfig 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/arch/i386/Kconfig.~1~ 2008-06-22 20:48:52.000000000 +0200
++++ linux-2.6.10.perfctr26/arch/i386/Kconfig 2008-06-22 20:57:10.000000000 +0200
@@ -874,6 +874,8 @@ config REGPARM
generate incorrect output with certain kernel constructs when
-mregparm=3 is used.
@@ -45,8 +50,8 @@
endmenu
---- linux-2.6.10.perfctr26/arch/i386/kernel/entry.S.~1~ 2004-12-25 12:16:17.000000000 +0100
-+++ linux-2.6.10.perfctr26/arch/i386/kernel/entry.S 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/arch/i386/kernel/entry.S.~1~ 2008-06-22 20:48:52.000000000 +0200
++++ linux-2.6.10.perfctr26/arch/i386/kernel/entry.S 2008-06-22 20:57:10.000000000 +0200
@@ -375,6 +375,16 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -64,8 +69,8 @@
ENTRY(divide_error)
pushl $0 # no error code
pushl $do_divide_error
---- linux-2.6.10.perfctr26/arch/i386/kernel/i8259.c.~1~ 2004-12-25 12:16:17.000000000 +0100
-+++ linux-2.6.10.perfctr26/arch/i386/kernel/i8259.c 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/arch/i386/kernel/i8259.c.~1~ 2008-06-22 20:48:52.000000000 +0200
++++ linux-2.6.10.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 20:57:10.000000000 +0200
@@ -24,6 +24,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -83,8 +88,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.10.perfctr26/arch/i386/kernel/process.c.~1~ 2004-12-25 12:16:17.000000000 +0100
-+++ linux-2.6.10.perfctr26/arch/i386/kernel/process.c 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/arch/i386/kernel/process.c.~1~ 2008-06-22 20:48:52.000000000 +0200
++++ linux-2.6.10.perfctr26/arch/i386/kernel/process.c 2008-06-22 20:57:10.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -119,8 +124,8 @@
return prev_p;
}
---- linux-2.6.10.perfctr26/arch/ppc/Kconfig.~1~ 2004-12-25 12:16:18.000000000 +0100
-+++ linux-2.6.10.perfctr26/arch/ppc/Kconfig 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/arch/ppc/Kconfig.~1~ 2008-06-22 20:48:52.000000000 +0200
++++ linux-2.6.10.perfctr26/arch/ppc/Kconfig 2008-06-22 20:57:10.000000000 +0200
@@ -236,6 +236,8 @@ config NOT_COHERENT_CACHE
depends on 4xx || 8xx
default y
@@ -130,8 +135,8 @@
endmenu
menu "Platform options"
---- linux-2.6.10.perfctr26/arch/ppc/kernel/head.S.~1~ 2004-10-19 13:01:17.000000000 +0200
-+++ linux-2.6.10.perfctr26/arch/ppc/kernel/head.S 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/arch/ppc/kernel/head.S.~1~ 2008-06-22 20:17:14.000000000 +0200
++++ linux-2.6.10.perfctr26/arch/ppc/kernel/head.S 2008-06-22 20:57:10.000000000 +0200
@@ -502,7 +502,11 @@ SystemCall:
Trap_0f:
EXCEPTION_PROLOG
@@ -144,8 +149,8 @@
/*
* Handle TLB miss for instruction on 603/603e.
---- linux-2.6.10.perfctr26/arch/ppc/kernel/process.c.~1~ 2004-12-25 12:16:18.000000000 +0100
-+++ linux-2.6.10.perfctr26/arch/ppc/kernel/process.c 2004-12-25 12:42:03.000000000 +0100
+--- linux-2.6.10.perfctr26/arch/ppc/kernel/process.c.~1~ 2008-06-22 20:48:53.000000000 +0200
++++ linux-2.6.10.perfctr26/arch/ppc/kernel/process.c 2008-06-22 20:57:10.000000000 +0200
@@ -35,6 +35,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -181,8 +186,8 @@
return 0;
}
---- linux-2.6.10.perfctr26/arch/x86_64/Kconfig.~1~ 2004-12-25 12:16:18.000000000 +0100
-+++ linux-2.6.10.perfctr26/arch/x86_64/Kconfig 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/arch/x86_64/Kconfig.~1~ 2008-06-22 20:48:53.000000000 +0200
++++ linux-2.6.10.perfctr26/arch/x86_64/Kconfig 2008-06-22 20:57:10.000000000 +0200
@@ -338,6 +338,8 @@ config X86_MCE
machine check error logs. See
ftp://ftp.x86-64.org/pub/linux/tools/mcelog
@@ -192,8 +197,8 @@
endmenu
#
---- linux-2.6.10.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2004-12-25 12:16:18.000000000 +0100
-+++ linux-2.6.10.perfctr26/arch/x86_64/kernel/entry.S 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2008-06-22 20:48:53.000000000 +0200
++++ linux-2.6.10.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 20:57:10.000000000 +0200
@@ -560,6 +560,11 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
#endif
@@ -206,8 +211,8 @@
/*
* Exception entry points.
*/
---- linux-2.6.10.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2004-12-25 12:16:18.000000000 +0100
-+++ linux-2.6.10.perfctr26/arch/x86_64/kernel/i8259.c 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2008-06-22 20:48:53.000000000 +0200
++++ linux-2.6.10.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 20:57:10.000000000 +0200
@@ -24,6 +24,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -225,8 +230,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.10.perfctr26/arch/x86_64/kernel/process.c.~1~ 2004-12-25 12:16:18.000000000 +0100
-+++ linux-2.6.10.perfctr26/arch/x86_64/kernel/process.c 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/arch/x86_64/kernel/process.c.~1~ 2008-06-22 20:48:53.000000000 +0200
++++ linux-2.6.10.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 20:57:10.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/irq.h>
@@ -261,16 +266,34 @@
return prev_p;
}
---- linux-2.6.10.perfctr26/drivers/Makefile.~1~ 2004-12-25 12:16:18.000000000 +0100
-+++ linux-2.6.10.perfctr26/drivers/Makefile 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/drivers/Makefile.~1~ 2008-06-22 20:48:53.000000000 +0200
++++ linux-2.6.10.perfctr26/drivers/Makefile 2008-06-22 20:57:10.000000000 +0200
@@ -59,4 +59,5 @@ obj-$(CONFIG_MCA) += mca/
obj-$(CONFIG_EISA) += eisa/
obj-$(CONFIG_CPU_FREQ) += cpufreq/
obj-$(CONFIG_MMC) += mmc/
+obj-$(CONFIG_KPERFCTR) += perfctr/
obj-y += firmware/
---- linux-2.6.10.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2004-05-10 11:14:37.000000000 +0200
-+++ linux-2.6.10.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/fs/exec.c.~1~ 2008-06-22 20:48:53.000000000 +0200
++++ linux-2.6.10.perfctr26/fs/exec.c 2008-06-22 20:57:42.000000000 +0200
+@@ -47,6 +47,7 @@
+ #include <linux/security.h>
+ #include <linux/syscalls.h>
+ #include <linux/rmap.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -843,6 +844,7 @@ int flush_old_exec(struct linux_binprm *
+ tcomm[i] = '\0';
+ set_task_comm(current, tcomm);
+
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ if (bprm->e_uid != current->euid || bprm->e_gid != current->egid ||
+--- linux-2.6.10.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.10.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 20:57:10.000000000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -289,8 +312,8 @@
#define TIMER_IRQ 0
---- linux-2.6.10.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2004-01-09 13:19:11.000000000 +0100
-+++ linux-2.6.10.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.10.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 20:57:10.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -309,8 +332,8 @@
#define TIMER_IRQ 0
---- linux-2.6.10.perfctr26/include/asm-i386/processor.h.~1~ 2004-12-25 12:16:22.000000000 +0100
-+++ linux-2.6.10.perfctr26/include/asm-i386/processor.h 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/include/asm-i386/processor.h.~1~ 2008-06-22 20:48:54.000000000 +0200
++++ linux-2.6.10.perfctr26/include/asm-i386/processor.h 2008-06-22 20:57:10.000000000 +0200
@@ -436,6 +436,8 @@ struct thread_struct {
unsigned long *io_bitmap_ptr;
/* max allowed port in the bitmap, in bytes: */
@@ -320,8 +343,8 @@
};
#define INIT_THREAD { \
---- linux-2.6.10.perfctr26/include/asm-i386/system.h.~1~ 2004-12-25 12:16:22.000000000 +0100
-+++ linux-2.6.10.perfctr26/include/asm-i386/system.h 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/include/asm-i386/system.h.~1~ 2008-06-22 20:48:54.000000000 +0200
++++ linux-2.6.10.perfctr26/include/asm-i386/system.h 2008-06-22 20:57:10.000000000 +0200
@@ -14,6 +14,7 @@ extern struct task_struct * FASTCALL(__s
#define switch_to(prev,next,last) do { \
@@ -330,8 +353,8 @@
asm volatile("pushfl\n\t" \
"pushl %%ebp\n\t" \
"movl %%esp,%0\n\t" /* save ESP */ \
---- linux-2.6.10.perfctr26/include/asm-ppc/processor.h.~1~ 2004-08-14 13:14:29.000000000 +0200
-+++ linux-2.6.10.perfctr26/include/asm-ppc/processor.h 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/include/asm-ppc/processor.h.~1~ 2008-06-22 20:48:54.000000000 +0200
++++ linux-2.6.10.perfctr26/include/asm-ppc/processor.h 2008-06-22 20:57:10.000000000 +0200
@@ -126,6 +126,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
@@ -342,8 +365,8 @@
};
#define ARCH_MIN_TASKALIGN 16
---- linux-2.6.10.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2004-12-25 12:16:24.000000000 +0100
-+++ linux-2.6.10.perfctr26/include/asm-x86_64/hw_irq.h 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2008-06-22 20:48:54.000000000 +0200
++++ linux-2.6.10.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 20:57:10.000000000 +0200
@@ -65,14 +65,15 @@ struct hw_interrupt_type;
* sources per level' errata.
*/
@@ -362,8 +385,8 @@
#ifndef __ASSEMBLY__
---- linux-2.6.10.perfctr26/include/asm-x86_64/irq.h.~1~ 2004-12-25 12:16:24.000000000 +0100
-+++ linux-2.6.10.perfctr26/include/asm-x86_64/irq.h 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/include/asm-x86_64/irq.h.~1~ 2008-06-22 19:39:46.000000000 +0200
++++ linux-2.6.10.perfctr26/include/asm-x86_64/irq.h 2008-06-22 20:57:10.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -373,8 +396,8 @@
#ifdef CONFIG_PCI_MSI
#define NR_IRQS FIRST_SYSTEM_VECTOR
---- linux-2.6.10.perfctr26/include/asm-x86_64/processor.h.~1~ 2004-12-25 12:16:24.000000000 +0100
-+++ linux-2.6.10.perfctr26/include/asm-x86_64/processor.h 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/include/asm-x86_64/processor.h.~1~ 2008-06-22 20:48:54.000000000 +0200
++++ linux-2.6.10.perfctr26/include/asm-x86_64/processor.h 2008-06-22 20:57:10.000000000 +0200
@@ -258,6 +258,8 @@ struct thread_struct {
unsigned io_bitmap_max;
/* cached TLS descriptors. */
@@ -384,8 +407,8 @@
} __attribute__((aligned(16)));
#define INIT_THREAD {}
---- linux-2.6.10.perfctr26/include/asm-x86_64/system.h.~1~ 2004-12-25 12:16:24.000000000 +0100
-+++ linux-2.6.10.perfctr26/include/asm-x86_64/system.h 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/include/asm-x86_64/system.h.~1~ 2008-06-22 20:48:54.000000000 +0200
++++ linux-2.6.10.perfctr26/include/asm-x86_64/system.h 2008-06-22 20:57:10.000000000 +0200
@@ -26,7 +26,8 @@
#define __EXTRA_CLOBBER \
,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
@@ -406,8 +429,8 @@
extern void load_gs_index(unsigned);
---- linux-2.6.10.perfctr26/kernel/exit.c.~1~ 2004-12-25 12:16:25.000000000 +0100
-+++ linux-2.6.10.perfctr26/kernel/exit.c 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/kernel/exit.c.~1~ 2008-06-22 20:48:55.000000000 +0200
++++ linux-2.6.10.perfctr26/kernel/exit.c 2008-06-22 20:57:10.000000000 +0200
@@ -25,6 +25,7 @@
#include <linux/mount.h>
#include <linux/proc_fs.h>
@@ -424,8 +447,8 @@
sched_exit(p);
write_unlock_irq(&tasklist_lock);
spin_unlock(&p->proc_lock);
---- linux-2.6.10.perfctr26/kernel/sched.c.~1~ 2004-12-25 12:16:25.000000000 +0100
-+++ linux-2.6.10.perfctr26/kernel/sched.c 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/kernel/sched.c.~1~ 2008-06-22 20:48:55.000000000 +0200
++++ linux-2.6.10.perfctr26/kernel/sched.c 2008-06-22 20:57:10.000000000 +0200
@@ -40,6 +40,7 @@
#include <linux/rcupdate.h>
#include <linux/cpu.h>
@@ -443,8 +466,8 @@
rq = task_rq_lock(p, &flags);
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
---- linux-2.6.10.perfctr26/kernel/timer.c.~1~ 2004-12-25 12:16:25.000000000 +0100
-+++ linux-2.6.10.perfctr26/kernel/timer.c 2004-12-25 12:39:35.000000000 +0100
+--- linux-2.6.10.perfctr26/kernel/timer.c.~1~ 2008-06-22 20:48:55.000000000 +0200
++++ linux-2.6.10.perfctr26/kernel/timer.c 2008-06-22 20:57:10.000000000 +0200
@@ -31,6 +31,7 @@
#include <linux/time.h>
#include <linux/jiffies.h>
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.11 b/src/perfctr-2.6.x/patches/patch-kernel-2.6.11
index 3a9a829f191229000f75a2a7f2c75b584c2672fa..79f6eb19cf100facc187bde1fe90a0b2c7e3e010 100755
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.11
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.11
@@ -1,15 +1,20 @@
---- linux-2.6.11.perfctr26/CREDITS.~1~ 2005-03-02 19:24:14.000000000 +0100
-+++ linux-2.6.11.perfctr26/CREDITS 2005-03-02 19:43:29.000000000 +0100
-@@ -2620,6 +2620,7 @@ N: Mikael Pettersson
- E: mikpe@csd.uu.se
- W: http://www.csd.uu.se/~mikpe/
+--- linux-2.6.11.perfctr26/CREDITS.~1~ 2008-06-22 20:17:14.000000000 +0200
++++ linux-2.6.11.perfctr26/CREDITS 2008-06-22 20:20:14.000000000 +0200
+@@ -2617,9 +2617,10 @@ S: Ottawa, Ontario
+ S: Canada K2P 0X8
+
+ N: Mikael Pettersson
+-E: mikpe@csd.uu.se
+-W: http://www.csd.uu.se/~mikpe/
++E: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/
D: Miscellaneous fixes
+D: Performance-monitoring counters driver
N: Reed H. Petty
E: rhp@draper.net
---- linux-2.6.11.perfctr26/Documentation/ioctl-number.txt.~1~ 2005-03-02 19:24:14.000000000 +0100
-+++ linux-2.6.11.perfctr26/Documentation/ioctl-number.txt 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/Documentation/ioctl-number.txt.~1~ 2008-06-22 19:09:53.000000000 +0200
++++ linux-2.6.11.perfctr26/Documentation/ioctl-number.txt 2008-06-22 20:20:08.000000000 +0200
@@ -190,6 +190,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -19,23 +24,23 @@
0xDD 00-3F ZFCP device driver see drivers/s390/scsi/
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
---- linux-2.6.11.perfctr26/MAINTAINERS.~1~ 2005-03-02 19:24:14.000000000 +0100
-+++ linux-2.6.11.perfctr26/MAINTAINERS 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/MAINTAINERS.~1~ 2008-06-22 20:17:14.000000000 +0200
++++ linux-2.6.11.perfctr26/MAINTAINERS 2008-06-22 20:20:14.000000000 +0200
@@ -1769,6 +1769,12 @@ M: tsbogend@alpha.franken.de
L: linux-net@vger.kernel.org
S: Maintained
+PERFORMANCE-MONITORING COUNTERS DRIVER
+P: Mikael Pettersson
-+M: mikpe@csd.uu.se
-+W: http://www.csd.uu.se/~mikpe/linux/perfctr/
++M: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
+S: Maintained
+
PHRAM MTD DRIVER
P: J�rn Engel
M: joern@wh.fh-wedel.de
---- linux-2.6.11.perfctr26/arch/i386/Kconfig.~1~ 2005-03-02 19:24:14.000000000 +0100
-+++ linux-2.6.11.perfctr26/arch/i386/Kconfig 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/arch/i386/Kconfig.~1~ 2008-06-22 20:17:14.000000000 +0200
++++ linux-2.6.11.perfctr26/arch/i386/Kconfig 2008-06-22 20:20:08.000000000 +0200
@@ -888,6 +888,8 @@ config REGPARM
generate incorrect output with certain kernel constructs when
-mregparm=3 is used.
@@ -45,8 +50,8 @@
endmenu
---- linux-2.6.11.perfctr26/arch/i386/kernel/entry.S.~1~ 2005-03-02 19:24:14.000000000 +0100
-+++ linux-2.6.11.perfctr26/arch/i386/kernel/entry.S 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/arch/i386/kernel/entry.S.~1~ 2008-06-22 20:17:14.000000000 +0200
++++ linux-2.6.11.perfctr26/arch/i386/kernel/entry.S 2008-06-22 20:20:08.000000000 +0200
@@ -372,6 +372,16 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -64,8 +69,8 @@
ENTRY(divide_error)
pushl $0 # no error code
pushl $do_divide_error
---- linux-2.6.11.perfctr26/arch/i386/kernel/i8259.c.~1~ 2005-03-02 19:24:14.000000000 +0100
-+++ linux-2.6.11.perfctr26/arch/i386/kernel/i8259.c 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/arch/i386/kernel/i8259.c.~1~ 2008-06-22 20:17:14.000000000 +0200
++++ linux-2.6.11.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 20:20:08.000000000 +0200
@@ -24,6 +24,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -83,8 +88,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.11.perfctr26/arch/i386/kernel/process.c.~1~ 2005-03-02 19:24:14.000000000 +0100
-+++ linux-2.6.11.perfctr26/arch/i386/kernel/process.c 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/arch/i386/kernel/process.c.~1~ 2008-06-22 20:17:14.000000000 +0200
++++ linux-2.6.11.perfctr26/arch/i386/kernel/process.c 2008-06-22 20:20:08.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -119,8 +124,8 @@
return prev_p;
}
---- linux-2.6.11.perfctr26/arch/ppc/Kconfig.~1~ 2005-03-02 19:24:14.000000000 +0100
-+++ linux-2.6.11.perfctr26/arch/ppc/Kconfig 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/arch/ppc/Kconfig.~1~ 2008-06-22 20:17:14.000000000 +0200
++++ linux-2.6.11.perfctr26/arch/ppc/Kconfig 2008-06-22 20:20:08.000000000 +0200
@@ -245,6 +245,8 @@ config NOT_COHERENT_CACHE
depends on 4xx || 8xx
default y
@@ -130,8 +135,8 @@
endmenu
menu "Platform options"
---- linux-2.6.11.perfctr26/arch/ppc/kernel/head.S.~1~ 2004-10-19 13:01:17.000000000 +0200
-+++ linux-2.6.11.perfctr26/arch/ppc/kernel/head.S 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/arch/ppc/kernel/head.S.~1~ 2008-06-22 20:17:14.000000000 +0200
++++ linux-2.6.11.perfctr26/arch/ppc/kernel/head.S 2008-06-22 20:20:08.000000000 +0200
@@ -502,7 +502,11 @@ SystemCall:
Trap_0f:
EXCEPTION_PROLOG
@@ -144,8 +149,8 @@
/*
* Handle TLB miss for instruction on 603/603e.
---- linux-2.6.11.perfctr26/arch/ppc/kernel/process.c.~1~ 2005-03-02 19:24:14.000000000 +0100
-+++ linux-2.6.11.perfctr26/arch/ppc/kernel/process.c 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/arch/ppc/kernel/process.c.~1~ 2008-06-22 19:09:53.000000000 +0200
++++ linux-2.6.11.perfctr26/arch/ppc/kernel/process.c 2008-06-22 20:20:08.000000000 +0200
@@ -35,6 +35,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -181,8 +186,8 @@
return 0;
}
---- linux-2.6.11.perfctr26/arch/x86_64/Kconfig.~1~ 2005-03-02 19:24:15.000000000 +0100
-+++ linux-2.6.11.perfctr26/arch/x86_64/Kconfig 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/arch/x86_64/Kconfig.~1~ 2008-06-22 20:17:14.000000000 +0200
++++ linux-2.6.11.perfctr26/arch/x86_64/Kconfig 2008-06-22 20:20:08.000000000 +0200
@@ -350,6 +350,9 @@ config X86_MCE_INTEL
help
Additional support for intel specific MCE features such as
@@ -193,8 +198,8 @@
endmenu
#
---- linux-2.6.11.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2005-03-02 19:24:15.000000000 +0100
-+++ linux-2.6.11.perfctr26/arch/x86_64/kernel/entry.S 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2008-06-22 20:17:14.000000000 +0200
++++ linux-2.6.11.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 20:20:08.000000000 +0200
@@ -562,6 +562,11 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
#endif
@@ -207,8 +212,8 @@
/*
* Exception entry points.
*/
---- linux-2.6.11.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2005-03-02 19:24:15.000000000 +0100
-+++ linux-2.6.11.perfctr26/arch/x86_64/kernel/i8259.c 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2008-06-22 20:17:14.000000000 +0200
++++ linux-2.6.11.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 20:20:08.000000000 +0200
@@ -24,6 +24,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -226,8 +231,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.11.perfctr26/arch/x86_64/kernel/process.c.~1~ 2005-03-02 19:24:15.000000000 +0100
-+++ linux-2.6.11.perfctr26/arch/x86_64/kernel/process.c 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/arch/x86_64/kernel/process.c.~1~ 2008-06-22 20:17:14.000000000 +0200
++++ linux-2.6.11.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 20:20:08.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/irq.h>
@@ -262,8 +267,8 @@
return prev_p;
}
---- linux-2.6.11.perfctr26/drivers/Makefile.~1~ 2005-03-02 19:24:15.000000000 +0100
-+++ linux-2.6.11.perfctr26/drivers/Makefile 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/drivers/Makefile.~1~ 2008-06-22 20:17:14.000000000 +0200
++++ linux-2.6.11.perfctr26/drivers/Makefile 2008-06-22 20:20:08.000000000 +0200
@@ -61,5 +61,6 @@ obj-$(CONFIG_EISA) += eisa/
obj-$(CONFIG_CPU_FREQ) += cpufreq/
obj-$(CONFIG_MMC) += mmc/
@@ -271,8 +276,26 @@
+obj-$(CONFIG_KPERFCTR) += perfctr/
obj-y += firmware/
obj-$(CONFIG_CRYPTO) += crypto/
---- linux-2.6.11.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2004-05-10 11:14:37.000000000 +0200
-+++ linux-2.6.11.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/fs/exec.c.~1~ 2008-06-22 20:17:15.000000000 +0200
++++ linux-2.6.11.perfctr26/fs/exec.c 2008-06-22 20:20:14.000000000 +0200
+@@ -48,6 +48,7 @@
+ #include <linux/syscalls.h>
+ #include <linux/rmap.h>
+ #include <linux/acct.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -877,6 +878,7 @@ int flush_old_exec(struct linux_binprm *
+ tcomm[i] = '\0';
+ set_task_comm(current, tcomm);
+
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ if (bprm->e_uid != current->euid || bprm->e_gid != current->egid ||
+--- linux-2.6.11.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.11.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 20:20:08.000000000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -291,8 +314,8 @@
#define TIMER_IRQ 0
---- linux-2.6.11.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2004-01-09 13:19:11.000000000 +0100
-+++ linux-2.6.11.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.11.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 20:20:08.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -311,8 +334,8 @@
#define TIMER_IRQ 0
---- linux-2.6.11.perfctr26/include/asm-i386/processor.h.~1~ 2005-03-02 19:24:19.000000000 +0100
-+++ linux-2.6.11.perfctr26/include/asm-i386/processor.h 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/include/asm-i386/processor.h.~1~ 2008-06-22 20:17:15.000000000 +0200
++++ linux-2.6.11.perfctr26/include/asm-i386/processor.h 2008-06-22 20:20:08.000000000 +0200
@@ -444,6 +444,8 @@ struct thread_struct {
unsigned long *io_bitmap_ptr;
/* max allowed port in the bitmap, in bytes: */
@@ -322,8 +345,8 @@
};
#define INIT_THREAD { \
---- linux-2.6.11.perfctr26/include/asm-i386/system.h.~1~ 2005-03-02 19:24:19.000000000 +0100
-+++ linux-2.6.11.perfctr26/include/asm-i386/system.h 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/include/asm-i386/system.h.~1~ 2008-06-22 20:17:15.000000000 +0200
++++ linux-2.6.11.perfctr26/include/asm-i386/system.h 2008-06-22 20:20:08.000000000 +0200
@@ -14,6 +14,7 @@ extern struct task_struct * FASTCALL(__s
#define switch_to(prev,next,last) do { \
@@ -332,8 +355,8 @@
asm volatile("pushfl\n\t" \
"pushl %%ebp\n\t" \
"movl %%esp,%0\n\t" /* save ESP */ \
---- linux-2.6.11.perfctr26/include/asm-ppc/processor.h.~1~ 2005-03-02 19:24:19.000000000 +0100
-+++ linux-2.6.11.perfctr26/include/asm-ppc/processor.h 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/include/asm-ppc/processor.h.~1~ 2008-06-22 19:09:55.000000000 +0200
++++ linux-2.6.11.perfctr26/include/asm-ppc/processor.h 2008-06-22 20:20:08.000000000 +0200
@@ -122,6 +122,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
@@ -344,8 +367,8 @@
};
#define ARCH_MIN_TASKALIGN 16
---- linux-2.6.11.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2005-03-02 19:24:19.000000000 +0100
-+++ linux-2.6.11.perfctr26/include/asm-x86_64/hw_irq.h 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2008-06-22 19:21:39.000000000 +0200
++++ linux-2.6.11.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 20:20:08.000000000 +0200
@@ -65,14 +65,15 @@ struct hw_interrupt_type;
* sources per level' errata.
*/
@@ -364,8 +387,8 @@
#ifndef __ASSEMBLY__
---- linux-2.6.11.perfctr26/include/asm-x86_64/irq.h.~1~ 2004-12-25 12:16:24.000000000 +0100
-+++ linux-2.6.11.perfctr26/include/asm-x86_64/irq.h 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/include/asm-x86_64/irq.h.~1~ 2008-06-22 19:39:46.000000000 +0200
++++ linux-2.6.11.perfctr26/include/asm-x86_64/irq.h 2008-06-22 20:20:08.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -375,8 +398,8 @@
#ifdef CONFIG_PCI_MSI
#define NR_IRQS FIRST_SYSTEM_VECTOR
---- linux-2.6.11.perfctr26/include/asm-x86_64/processor.h.~1~ 2005-03-02 19:24:19.000000000 +0100
-+++ linux-2.6.11.perfctr26/include/asm-x86_64/processor.h 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/include/asm-x86_64/processor.h.~1~ 2008-06-22 20:17:15.000000000 +0200
++++ linux-2.6.11.perfctr26/include/asm-x86_64/processor.h 2008-06-22 20:20:08.000000000 +0200
@@ -253,6 +253,8 @@ struct thread_struct {
unsigned io_bitmap_max;
/* cached TLS descriptors. */
@@ -386,8 +409,8 @@
} __attribute__((aligned(16)));
#define INIT_THREAD {}
---- linux-2.6.11.perfctr26/include/asm-x86_64/system.h.~1~ 2005-03-02 19:24:19.000000000 +0100
-+++ linux-2.6.11.perfctr26/include/asm-x86_64/system.h 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/include/asm-x86_64/system.h.~1~ 2008-06-22 20:17:15.000000000 +0200
++++ linux-2.6.11.perfctr26/include/asm-x86_64/system.h 2008-06-22 20:20:08.000000000 +0200
@@ -26,7 +26,8 @@
#define __EXTRA_CLOBBER \
,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
@@ -408,8 +431,8 @@
extern void load_gs_index(unsigned);
---- linux-2.6.11.perfctr26/kernel/exit.c.~1~ 2005-03-02 19:24:20.000000000 +0100
-+++ linux-2.6.11.perfctr26/kernel/exit.c 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/kernel/exit.c.~1~ 2008-06-22 20:17:15.000000000 +0200
++++ linux-2.6.11.perfctr26/kernel/exit.c 2008-06-22 20:20:08.000000000 +0200
@@ -25,6 +25,7 @@
#include <linux/mount.h>
#include <linux/proc_fs.h>
@@ -426,8 +449,8 @@
sched_exit(p);
write_unlock_irq(&tasklist_lock);
spin_unlock(&p->proc_lock);
---- linux-2.6.11.perfctr26/kernel/sched.c.~1~ 2005-03-02 19:24:20.000000000 +0100
-+++ linux-2.6.11.perfctr26/kernel/sched.c 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/kernel/sched.c.~1~ 2008-06-22 20:17:15.000000000 +0200
++++ linux-2.6.11.perfctr26/kernel/sched.c 2008-06-22 20:20:08.000000000 +0200
@@ -41,6 +41,7 @@
#include <linux/rcupdate.h>
#include <linux/cpu.h>
@@ -445,8 +468,8 @@
rq = task_rq_lock(p, &flags);
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
---- linux-2.6.11.perfctr26/kernel/timer.c.~1~ 2005-03-02 19:24:20.000000000 +0100
-+++ linux-2.6.11.perfctr26/kernel/timer.c 2005-03-02 19:43:29.000000000 +0100
+--- linux-2.6.11.perfctr26/kernel/timer.c.~1~ 2008-06-22 20:17:15.000000000 +0200
++++ linux-2.6.11.perfctr26/kernel/timer.c 2008-06-22 20:20:08.000000000 +0200
@@ -31,6 +31,7 @@
#include <linux/time.h>
#include <linux/jiffies.h>
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.12 b/src/perfctr-2.6.x/patches/patch-kernel-2.6.12
index 913e8eaf2da5c73e8298f9f902d6b649b3f5b00d..466f3c53ffa137d608cc2ccfbc47b065d9fbe846 100644
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.12
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.12
@@ -1,15 +1,20 @@
---- linux-2.6.12.perfctr/CREDITS.~1~ 2005-06-19 11:36:37.000000000 +0200
-+++ linux-2.6.12.perfctr/CREDITS 2005-06-19 12:00:59.000000000 +0200
-@@ -2620,6 +2620,7 @@ N: Mikael Pettersson
- E: mikpe@csd.uu.se
- W: http://www.csd.uu.se/~mikpe/
+--- linux-2.6.12.perfctr26/CREDITS.~1~ 2008-06-22 19:39:44.000000000 +0200
++++ linux-2.6.12.perfctr26/CREDITS 2008-06-22 19:41:44.000000000 +0200
+@@ -2617,9 +2617,10 @@ S: Ottawa, Ontario
+ S: Canada K2P 0X8
+
+ N: Mikael Pettersson
+-E: mikpe@csd.uu.se
+-W: http://www.csd.uu.se/~mikpe/
++E: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/
D: Miscellaneous fixes
+D: Performance-monitoring counters driver
N: Reed H. Petty
E: rhp@draper.net
---- linux-2.6.12.perfctr/Documentation/ioctl-number.txt.~1~ 2005-03-02 19:24:14.000000000 +0100
-+++ linux-2.6.12.perfctr/Documentation/ioctl-number.txt 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/Documentation/ioctl-number.txt.~1~ 2008-06-22 19:09:53.000000000 +0200
++++ linux-2.6.12.perfctr26/Documentation/ioctl-number.txt 2008-06-22 19:41:40.000000000 +0200
@@ -190,6 +190,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -19,23 +24,23 @@
0xDD 00-3F ZFCP device driver see drivers/s390/scsi/
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
---- linux-2.6.12.perfctr/MAINTAINERS.~1~ 2005-06-19 11:36:37.000000000 +0200
-+++ linux-2.6.12.perfctr/MAINTAINERS 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/MAINTAINERS.~1~ 2008-06-22 19:39:44.000000000 +0200
++++ linux-2.6.12.perfctr26/MAINTAINERS 2008-06-22 19:41:44.000000000 +0200
@@ -1786,6 +1786,12 @@ M: tsbogend@alpha.franken.de
L: netdev@vger.kernel.org
S: Maintained
+PERFORMANCE-MONITORING COUNTERS DRIVER
+P: Mikael Pettersson
-+M: mikpe@csd.uu.se
-+W: http://www.csd.uu.se/~mikpe/linux/perfctr/
++M: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
+S: Maintained
+
PHRAM MTD DRIVER
P: J�rn Engel
M: joern@wh.fh-wedel.de
---- linux-2.6.12.perfctr/arch/i386/Kconfig.~1~ 2005-06-19 11:36:37.000000000 +0200
-+++ linux-2.6.12.perfctr/arch/i386/Kconfig 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/arch/i386/Kconfig.~1~ 2008-06-22 19:39:44.000000000 +0200
++++ linux-2.6.12.perfctr26/arch/i386/Kconfig 2008-06-22 19:41:40.000000000 +0200
@@ -939,6 +939,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -45,8 +50,8 @@
endmenu
---- linux-2.6.12.perfctr/arch/i386/kernel/entry.S.~1~ 2005-06-19 11:36:37.000000000 +0200
-+++ linux-2.6.12.perfctr/arch/i386/kernel/entry.S 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/arch/i386/kernel/entry.S.~1~ 2008-06-22 19:21:37.000000000 +0200
++++ linux-2.6.12.perfctr26/arch/i386/kernel/entry.S 2008-06-22 19:41:40.000000000 +0200
@@ -427,6 +427,16 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -64,8 +69,8 @@
ENTRY(divide_error)
pushl $0 # no error code
pushl $do_divide_error
---- linux-2.6.12.perfctr/arch/i386/kernel/i8259.c.~1~ 2005-06-19 11:36:37.000000000 +0200
-+++ linux-2.6.12.perfctr/arch/i386/kernel/i8259.c 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/arch/i386/kernel/i8259.c.~1~ 2008-06-22 19:39:44.000000000 +0200
++++ linux-2.6.12.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 19:41:40.000000000 +0200
@@ -24,6 +24,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -83,8 +88,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.12.perfctr/arch/i386/kernel/process.c.~1~ 2005-06-19 11:36:37.000000000 +0200
-+++ linux-2.6.12.perfctr/arch/i386/kernel/process.c 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/arch/i386/kernel/process.c.~1~ 2008-06-22 19:39:44.000000000 +0200
++++ linux-2.6.12.perfctr26/arch/i386/kernel/process.c 2008-06-22 19:41:40.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -119,8 +124,8 @@
return prev_p;
}
---- linux-2.6.12.perfctr/arch/ppc/Kconfig.~1~ 2005-06-19 11:36:38.000000000 +0200
-+++ linux-2.6.12.perfctr/arch/ppc/Kconfig 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/arch/ppc/Kconfig.~1~ 2008-06-22 19:39:44.000000000 +0200
++++ linux-2.6.12.perfctr26/arch/ppc/Kconfig 2008-06-22 19:41:40.000000000 +0200
@@ -257,6 +257,8 @@ config NOT_COHERENT_CACHE
depends on 4xx || 8xx
default y
@@ -130,8 +135,8 @@
endmenu
menu "Platform options"
---- linux-2.6.12.perfctr/arch/ppc/kernel/head.S.~1~ 2005-06-19 11:36:38.000000000 +0200
-+++ linux-2.6.12.perfctr/arch/ppc/kernel/head.S 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/arch/ppc/kernel/head.S.~1~ 2008-06-22 19:21:37.000000000 +0200
++++ linux-2.6.12.perfctr26/arch/ppc/kernel/head.S 2008-06-22 19:41:40.000000000 +0200
@@ -502,7 +502,11 @@ SystemCall:
Trap_0f:
EXCEPTION_PROLOG
@@ -144,8 +149,8 @@
/*
* Handle TLB miss for instruction on 603/603e.
---- linux-2.6.12.perfctr/arch/ppc/kernel/process.c.~1~ 2005-03-02 19:24:14.000000000 +0100
-+++ linux-2.6.12.perfctr/arch/ppc/kernel/process.c 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/arch/ppc/kernel/process.c.~1~ 2008-06-22 19:09:53.000000000 +0200
++++ linux-2.6.12.perfctr26/arch/ppc/kernel/process.c 2008-06-22 19:41:40.000000000 +0200
@@ -35,6 +35,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -181,8 +186,8 @@
return 0;
}
---- linux-2.6.12.perfctr/arch/x86_64/Kconfig.~1~ 2005-06-19 11:36:38.000000000 +0200
-+++ linux-2.6.12.perfctr/arch/x86_64/Kconfig 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/arch/x86_64/Kconfig.~1~ 2008-06-22 19:39:45.000000000 +0200
++++ linux-2.6.12.perfctr26/arch/x86_64/Kconfig 2008-06-22 19:41:40.000000000 +0200
@@ -381,6 +381,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -192,8 +197,8 @@
endmenu
#
---- linux-2.6.12.perfctr/arch/x86_64/kernel/entry.S.~1~ 2005-06-19 11:36:38.000000000 +0200
-+++ linux-2.6.12.perfctr/arch/x86_64/kernel/entry.S 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2008-06-22 19:39:45.000000000 +0200
++++ linux-2.6.12.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 19:41:40.000000000 +0200
@@ -554,6 +554,11 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
#endif
@@ -206,8 +211,8 @@
/*
* Exception entry points.
*/
---- linux-2.6.12.perfctr/arch/x86_64/kernel/i8259.c.~1~ 2005-06-19 11:36:38.000000000 +0200
-+++ linux-2.6.12.perfctr/arch/x86_64/kernel/i8259.c 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2008-06-22 19:39:45.000000000 +0200
++++ linux-2.6.12.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 19:41:40.000000000 +0200
@@ -24,6 +24,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -225,8 +230,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.12.perfctr/arch/x86_64/kernel/process.c.~1~ 2005-06-19 11:36:38.000000000 +0200
-+++ linux-2.6.12.perfctr/arch/x86_64/kernel/process.c 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/arch/x86_64/kernel/process.c.~1~ 2008-06-22 19:39:45.000000000 +0200
++++ linux-2.6.12.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 19:41:40.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/irq.h>
@@ -261,8 +266,8 @@
return prev_p;
}
---- linux-2.6.12.perfctr/drivers/Makefile.~1~ 2005-06-19 11:36:38.000000000 +0200
-+++ linux-2.6.12.perfctr/drivers/Makefile 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/drivers/Makefile.~1~ 2008-06-22 19:39:45.000000000 +0200
++++ linux-2.6.12.perfctr26/drivers/Makefile 2008-06-22 19:41:40.000000000 +0200
@@ -62,5 +62,6 @@ obj-$(CONFIG_CPU_FREQ) += cpufreq/
obj-$(CONFIG_MMC) += mmc/
obj-$(CONFIG_INFINIBAND) += infiniband/
@@ -270,8 +275,26 @@
+obj-$(CONFIG_KPERFCTR) += perfctr/
obj-y += firmware/
obj-$(CONFIG_CRYPTO) += crypto/
---- linux-2.6.12.perfctr/include/asm-i386/mach-default/irq_vectors.h.~1~ 2004-05-10 11:14:37.000000000 +0200
-+++ linux-2.6.12.perfctr/include/asm-i386/mach-default/irq_vectors.h 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/fs/exec.c.~1~ 2008-06-22 19:39:46.000000000 +0200
++++ linux-2.6.12.perfctr26/fs/exec.c 2008-06-22 19:41:44.000000000 +0200
+@@ -48,6 +48,7 @@
+ #include <linux/syscalls.h>
+ #include <linux/rmap.h>
+ #include <linux/acct.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -882,6 +883,7 @@ int flush_old_exec(struct linux_binprm *
+ set_task_comm(current, tcomm);
+
+ current->flags &= ~PF_RANDOMIZE;
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ if (bprm->e_uid != current->euid || bprm->e_gid != current->egid ||
+--- linux-2.6.12.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.12.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 19:41:40.000000000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -290,8 +313,8 @@
#define TIMER_IRQ 0
---- linux-2.6.12.perfctr/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2004-01-09 13:19:11.000000000 +0100
-+++ linux-2.6.12.perfctr/include/asm-i386/mach-visws/irq_vectors.h 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.12.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 19:41:40.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -310,8 +333,8 @@
#define TIMER_IRQ 0
---- linux-2.6.12.perfctr/include/asm-i386/processor.h.~1~ 2005-06-19 11:36:42.000000000 +0200
-+++ linux-2.6.12.perfctr/include/asm-i386/processor.h 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/include/asm-i386/processor.h.~1~ 2008-06-22 19:39:46.000000000 +0200
++++ linux-2.6.12.perfctr26/include/asm-i386/processor.h 2008-06-22 19:41:40.000000000 +0200
@@ -456,6 +456,8 @@ struct thread_struct {
unsigned long *io_bitmap_ptr;
/* max allowed port in the bitmap, in bytes: */
@@ -321,8 +344,8 @@
};
#define INIT_THREAD { \
---- linux-2.6.12.perfctr/include/asm-i386/system.h.~1~ 2005-06-19 11:36:42.000000000 +0200
-+++ linux-2.6.12.perfctr/include/asm-i386/system.h 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/include/asm-i386/system.h.~1~ 2008-06-22 19:21:39.000000000 +0200
++++ linux-2.6.12.perfctr26/include/asm-i386/system.h 2008-06-22 19:41:40.000000000 +0200
@@ -14,6 +14,7 @@ extern struct task_struct * FASTCALL(__s
#define switch_to(prev,next,last) do { \
@@ -331,8 +354,8 @@
asm volatile("pushfl\n\t" \
"pushl %%ebp\n\t" \
"movl %%esp,%0\n\t" /* save ESP */ \
---- linux-2.6.12.perfctr/include/asm-ppc/processor.h.~1~ 2005-03-02 19:24:19.000000000 +0100
-+++ linux-2.6.12.perfctr/include/asm-ppc/processor.h 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/include/asm-ppc/processor.h.~1~ 2008-06-22 19:09:55.000000000 +0200
++++ linux-2.6.12.perfctr26/include/asm-ppc/processor.h 2008-06-22 19:41:40.000000000 +0200
@@ -122,6 +122,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
@@ -343,8 +366,8 @@
};
#define ARCH_MIN_TASKALIGN 16
---- linux-2.6.12.perfctr/include/asm-x86_64/hw_irq.h.~1~ 2005-03-02 19:24:19.000000000 +0100
-+++ linux-2.6.12.perfctr/include/asm-x86_64/hw_irq.h 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2008-06-22 19:21:39.000000000 +0200
++++ linux-2.6.12.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 19:41:40.000000000 +0200
@@ -65,14 +65,15 @@ struct hw_interrupt_type;
* sources per level' errata.
*/
@@ -363,8 +386,8 @@
#ifndef __ASSEMBLY__
---- linux-2.6.12.perfctr/include/asm-x86_64/irq.h.~1~ 2004-12-25 12:16:24.000000000 +0100
-+++ linux-2.6.12.perfctr/include/asm-x86_64/irq.h 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/include/asm-x86_64/irq.h.~1~ 2008-06-22 19:39:46.000000000 +0200
++++ linux-2.6.12.perfctr26/include/asm-x86_64/irq.h 2008-06-22 19:41:40.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -374,8 +397,8 @@
#ifdef CONFIG_PCI_MSI
#define NR_IRQS FIRST_SYSTEM_VECTOR
---- linux-2.6.12.perfctr/include/asm-x86_64/processor.h.~1~ 2005-06-19 11:36:42.000000000 +0200
-+++ linux-2.6.12.perfctr/include/asm-x86_64/processor.h 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/include/asm-x86_64/processor.h.~1~ 2008-06-22 19:39:46.000000000 +0200
++++ linux-2.6.12.perfctr26/include/asm-x86_64/processor.h 2008-06-22 19:41:40.000000000 +0200
@@ -251,6 +251,8 @@ struct thread_struct {
unsigned io_bitmap_max;
/* cached TLS descriptors. */
@@ -385,8 +408,8 @@
} __attribute__((aligned(16)));
#define INIT_THREAD {}
---- linux-2.6.12.perfctr/include/asm-x86_64/system.h.~1~ 2005-06-19 11:36:42.000000000 +0200
-+++ linux-2.6.12.perfctr/include/asm-x86_64/system.h 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/include/asm-x86_64/system.h.~1~ 2008-06-22 19:39:46.000000000 +0200
++++ linux-2.6.12.perfctr26/include/asm-x86_64/system.h 2008-06-22 19:41:40.000000000 +0200
@@ -26,7 +26,8 @@
#define __EXTRA_CLOBBER \
,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
@@ -407,8 +430,8 @@
extern void load_gs_index(unsigned);
---- linux-2.6.12.perfctr/kernel/exit.c.~1~ 2005-06-19 11:36:43.000000000 +0200
-+++ linux-2.6.12.perfctr/kernel/exit.c 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/kernel/exit.c.~1~ 2008-06-22 19:39:46.000000000 +0200
++++ linux-2.6.12.perfctr26/kernel/exit.c 2008-06-22 19:41:40.000000000 +0200
@@ -25,6 +25,7 @@
#include <linux/mount.h>
#include <linux/proc_fs.h>
@@ -425,8 +448,8 @@
sched_exit(p);
write_unlock_irq(&tasklist_lock);
spin_unlock(&p->proc_lock);
---- linux-2.6.12.perfctr/kernel/sched.c.~1~ 2005-06-19 11:36:43.000000000 +0200
-+++ linux-2.6.12.perfctr/kernel/sched.c 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/kernel/sched.c.~1~ 2008-06-22 19:39:46.000000000 +0200
++++ linux-2.6.12.perfctr26/kernel/sched.c 2008-06-22 19:41:40.000000000 +0200
@@ -42,6 +42,7 @@
#include <linux/cpu.h>
#include <linux/cpuset.h>
@@ -444,8 +467,8 @@
rq = task_rq_lock(p, &flags);
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
---- linux-2.6.12.perfctr/kernel/timer.c.~1~ 2005-06-19 11:36:43.000000000 +0200
-+++ linux-2.6.12.perfctr/kernel/timer.c 2005-06-19 12:00:59.000000000 +0200
+--- linux-2.6.12.perfctr26/kernel/timer.c.~1~ 2008-06-22 19:39:46.000000000 +0200
++++ linux-2.6.12.perfctr26/kernel/timer.c 2008-06-22 19:41:40.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/jiffies.h>
#include <linux/posix-timers.h>
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.13 b/src/perfctr-2.6.x/patches/patch-kernel-2.6.13
index 348e7fd57a76e0e4a48a9b06e575d7dfb28ad6e0..982f78608e272d209ff1b52e77a45958b2d22968 100644
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.13
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.13
@@ -1,15 +1,20 @@
---- linux-2.6.13.perfctr26/CREDITS.~1~ 2005-08-29 14:34:26.000000000 +0200
-+++ linux-2.6.13.perfctr26/CREDITS 2005-08-29 14:43:33.000000000 +0200
-@@ -2627,6 +2627,7 @@ N: Mikael Pettersson
- E: mikpe@csd.uu.se
- W: http://www.csd.uu.se/~mikpe/
+--- linux-2.6.13.perfctr26/CREDITS.~1~ 2008-06-22 19:21:37.000000000 +0200
++++ linux-2.6.13.perfctr26/CREDITS 2008-06-22 19:24:32.000000000 +0200
+@@ -2624,9 +2624,10 @@ S: Ottawa, Ontario
+ S: Canada K2P 0X8
+
+ N: Mikael Pettersson
+-E: mikpe@csd.uu.se
+-W: http://www.csd.uu.se/~mikpe/
++E: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/
D: Miscellaneous fixes
+D: Performance-monitoring counters driver
N: Reed H. Petty
E: rhp@draper.net
---- linux-2.6.13.perfctr26/Documentation/ioctl-number.txt.~1~ 2005-03-02 19:24:14.000000000 +0100
-+++ linux-2.6.13.perfctr26/Documentation/ioctl-number.txt 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/Documentation/ioctl-number.txt.~1~ 2008-06-22 19:09:53.000000000 +0200
++++ linux-2.6.13.perfctr26/Documentation/ioctl-number.txt 2008-06-22 19:24:26.000000000 +0200
@@ -190,6 +190,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -19,23 +24,23 @@
0xDD 00-3F ZFCP device driver see drivers/s390/scsi/
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
---- linux-2.6.13.perfctr26/MAINTAINERS.~1~ 2005-08-29 14:34:26.000000000 +0200
-+++ linux-2.6.13.perfctr26/MAINTAINERS 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/MAINTAINERS.~1~ 2008-06-22 19:21:37.000000000 +0200
++++ linux-2.6.13.perfctr26/MAINTAINERS 2008-06-22 19:24:32.000000000 +0200
@@ -1842,6 +1842,12 @@ M: tsbogend@alpha.franken.de
L: netdev@vger.kernel.org
S: Maintained
+PERFORMANCE-MONITORING COUNTERS DRIVER
+P: Mikael Pettersson
-+M: mikpe@csd.uu.se
-+W: http://www.csd.uu.se/~mikpe/linux/perfctr/
++M: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
+S: Maintained
+
PHRAM MTD DRIVER
P: J�rn Engel
M: joern@wh.fh-wedel.de
---- linux-2.6.13.perfctr26/arch/i386/Kconfig.~1~ 2005-08-29 14:34:27.000000000 +0200
-+++ linux-2.6.13.perfctr26/arch/i386/Kconfig 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/arch/i386/Kconfig.~1~ 2008-06-22 19:21:37.000000000 +0200
++++ linux-2.6.13.perfctr26/arch/i386/Kconfig 2008-06-22 19:24:26.000000000 +0200
@@ -941,6 +941,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -45,8 +50,8 @@
source kernel/Kconfig.hz
config PHYSICAL_START
---- linux-2.6.13.perfctr26/arch/i386/kernel/entry.S.~1~ 2005-06-19 11:36:37.000000000 +0200
-+++ linux-2.6.13.perfctr26/arch/i386/kernel/entry.S 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/arch/i386/kernel/entry.S.~1~ 2008-06-22 19:21:37.000000000 +0200
++++ linux-2.6.13.perfctr26/arch/i386/kernel/entry.S 2008-06-22 19:24:26.000000000 +0200
@@ -427,6 +427,16 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -64,8 +69,8 @@
ENTRY(divide_error)
pushl $0 # no error code
pushl $do_divide_error
---- linux-2.6.13.perfctr26/arch/i386/kernel/i8259.c.~1~ 2005-08-29 14:34:27.000000000 +0200
-+++ linux-2.6.13.perfctr26/arch/i386/kernel/i8259.c 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/arch/i386/kernel/i8259.c.~1~ 2008-06-22 19:21:37.000000000 +0200
++++ linux-2.6.13.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 19:24:26.000000000 +0200
@@ -24,6 +24,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -83,8 +88,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.13.perfctr26/arch/i386/kernel/process.c.~1~ 2005-08-29 14:34:27.000000000 +0200
-+++ linux-2.6.13.perfctr26/arch/i386/kernel/process.c 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/arch/i386/kernel/process.c.~1~ 2008-06-22 19:21:37.000000000 +0200
++++ linux-2.6.13.perfctr26/arch/i386/kernel/process.c 2008-06-22 19:24:26.000000000 +0200
@@ -33,6 +33,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -119,8 +124,8 @@
return prev_p;
}
---- linux-2.6.13.perfctr26/arch/ppc/Kconfig.~1~ 2005-08-29 14:34:27.000000000 +0200
-+++ linux-2.6.13.perfctr26/arch/ppc/Kconfig 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/arch/ppc/Kconfig.~1~ 2008-06-22 19:21:37.000000000 +0200
++++ linux-2.6.13.perfctr26/arch/ppc/Kconfig 2008-06-22 19:24:26.000000000 +0200
@@ -279,6 +279,8 @@ config NOT_COHERENT_CACHE
depends on 4xx || 8xx || E200
default y
@@ -130,8 +135,8 @@
endmenu
menu "Platform options"
---- linux-2.6.13.perfctr26/arch/ppc/kernel/head.S.~1~ 2005-06-19 11:36:38.000000000 +0200
-+++ linux-2.6.13.perfctr26/arch/ppc/kernel/head.S 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/arch/ppc/kernel/head.S.~1~ 2008-06-22 19:21:37.000000000 +0200
++++ linux-2.6.13.perfctr26/arch/ppc/kernel/head.S 2008-06-22 19:24:26.000000000 +0200
@@ -502,7 +502,11 @@ SystemCall:
Trap_0f:
EXCEPTION_PROLOG
@@ -144,8 +149,8 @@
/*
* Handle TLB miss for instruction on 603/603e.
---- linux-2.6.13.perfctr26/arch/ppc/kernel/process.c.~1~ 2005-03-02 19:24:14.000000000 +0100
-+++ linux-2.6.13.perfctr26/arch/ppc/kernel/process.c 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/arch/ppc/kernel/process.c.~1~ 2008-06-22 19:09:53.000000000 +0200
++++ linux-2.6.13.perfctr26/arch/ppc/kernel/process.c 2008-06-22 19:24:26.000000000 +0200
@@ -35,6 +35,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -181,8 +186,8 @@
return 0;
}
---- linux-2.6.13.perfctr26/arch/x86_64/Kconfig.~1~ 2005-08-29 14:34:27.000000000 +0200
-+++ linux-2.6.13.perfctr26/arch/x86_64/Kconfig 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/arch/x86_64/Kconfig.~1~ 2008-06-22 19:21:38.000000000 +0200
++++ linux-2.6.13.perfctr26/arch/x86_64/Kconfig 2008-06-22 19:24:26.000000000 +0200
@@ -417,6 +417,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -192,8 +197,8 @@
source kernel/Kconfig.hz
endmenu
---- linux-2.6.13.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2005-08-29 14:34:27.000000000 +0200
-+++ linux-2.6.13.perfctr26/arch/x86_64/kernel/entry.S 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2008-06-22 19:21:38.000000000 +0200
++++ linux-2.6.13.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 19:24:26.000000000 +0200
@@ -554,6 +554,11 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
#endif
@@ -206,8 +211,8 @@
/*
* Exception entry points.
*/
---- linux-2.6.13.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2005-08-29 14:34:27.000000000 +0200
-+++ linux-2.6.13.perfctr26/arch/x86_64/kernel/i8259.c 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2008-06-22 19:21:38.000000000 +0200
++++ linux-2.6.13.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 19:24:26.000000000 +0200
@@ -24,6 +24,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -225,8 +230,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.13.perfctr26/arch/x86_64/kernel/process.c.~1~ 2005-08-29 14:34:27.000000000 +0200
-+++ linux-2.6.13.perfctr26/arch/x86_64/kernel/process.c 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/arch/x86_64/kernel/process.c.~1~ 2008-06-22 19:21:38.000000000 +0200
++++ linux-2.6.13.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 19:24:26.000000000 +0200
@@ -34,6 +34,7 @@
#include <linux/delay.h>
#include <linux/irq.h>
@@ -261,8 +266,8 @@
return prev_p;
}
---- linux-2.6.13.perfctr26/drivers/Makefile.~1~ 2005-08-29 14:34:27.000000000 +0200
-+++ linux-2.6.13.perfctr26/drivers/Makefile 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/drivers/Makefile.~1~ 2008-06-22 19:21:38.000000000 +0200
++++ linux-2.6.13.perfctr26/drivers/Makefile 2008-06-22 19:24:26.000000000 +0200
@@ -63,5 +63,6 @@ obj-$(CONFIG_CPU_FREQ) += cpufreq/
obj-$(CONFIG_MMC) += mmc/
obj-$(CONFIG_INFINIBAND) += infiniband/
@@ -270,8 +275,26 @@
+obj-$(CONFIG_KPERFCTR) += perfctr/
obj-y += firmware/
obj-$(CONFIG_CRYPTO) += crypto/
---- linux-2.6.13.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2004-05-10 11:14:37.000000000 +0200
-+++ linux-2.6.13.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/fs/exec.c.~1~ 2008-06-22 19:21:39.000000000 +0200
++++ linux-2.6.13.perfctr26/fs/exec.c 2008-06-22 19:24:32.000000000 +0200
+@@ -48,6 +48,7 @@
+ #include <linux/syscalls.h>
+ #include <linux/rmap.h>
+ #include <linux/acct.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -896,6 +897,7 @@ int flush_old_exec(struct linux_binprm *
+ set_task_comm(current, tcomm);
+
+ current->flags &= ~PF_RANDOMIZE;
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ if (bprm->e_uid != current->euid || bprm->e_gid != current->egid ||
+--- linux-2.6.13.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.13.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 19:24:26.000000000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -290,8 +313,8 @@
#define TIMER_IRQ 0
---- linux-2.6.13.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2004-01-09 13:19:11.000000000 +0100
-+++ linux-2.6.13.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.13.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 19:24:26.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -310,8 +333,8 @@
#define TIMER_IRQ 0
---- linux-2.6.13.perfctr26/include/asm-i386/processor.h.~1~ 2005-08-29 14:34:33.000000000 +0200
-+++ linux-2.6.13.perfctr26/include/asm-i386/processor.h 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/include/asm-i386/processor.h.~1~ 2008-06-22 19:21:39.000000000 +0200
++++ linux-2.6.13.perfctr26/include/asm-i386/processor.h 2008-06-22 19:24:26.000000000 +0200
@@ -456,6 +456,8 @@ struct thread_struct {
unsigned long *io_bitmap_ptr;
/* max allowed port in the bitmap, in bytes: */
@@ -321,8 +344,8 @@
};
#define INIT_THREAD { \
---- linux-2.6.13.perfctr26/include/asm-i386/system.h.~1~ 2005-06-19 11:36:42.000000000 +0200
-+++ linux-2.6.13.perfctr26/include/asm-i386/system.h 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/include/asm-i386/system.h.~1~ 2008-06-22 19:21:39.000000000 +0200
++++ linux-2.6.13.perfctr26/include/asm-i386/system.h 2008-06-22 19:24:26.000000000 +0200
@@ -14,6 +14,7 @@ extern struct task_struct * FASTCALL(__s
#define switch_to(prev,next,last) do { \
@@ -331,8 +354,8 @@
asm volatile("pushfl\n\t" \
"pushl %%ebp\n\t" \
"movl %%esp,%0\n\t" /* save ESP */ \
---- linux-2.6.13.perfctr26/include/asm-ppc/processor.h.~1~ 2005-03-02 19:24:19.000000000 +0100
-+++ linux-2.6.13.perfctr26/include/asm-ppc/processor.h 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/include/asm-ppc/processor.h.~1~ 2008-06-22 19:09:55.000000000 +0200
++++ linux-2.6.13.perfctr26/include/asm-ppc/processor.h 2008-06-22 19:24:26.000000000 +0200
@@ -122,6 +122,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
@@ -343,8 +366,8 @@
};
#define ARCH_MIN_TASKALIGN 16
---- linux-2.6.13.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2005-03-02 19:24:19.000000000 +0100
-+++ linux-2.6.13.perfctr26/include/asm-x86_64/hw_irq.h 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2008-06-22 19:21:39.000000000 +0200
++++ linux-2.6.13.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 19:24:26.000000000 +0200
@@ -65,14 +65,15 @@ struct hw_interrupt_type;
* sources per level' errata.
*/
@@ -363,8 +386,8 @@
#ifndef __ASSEMBLY__
---- linux-2.6.13.perfctr26/include/asm-x86_64/irq.h.~1~ 2005-08-29 14:34:33.000000000 +0200
-+++ linux-2.6.13.perfctr26/include/asm-x86_64/irq.h 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/include/asm-x86_64/irq.h.~1~ 2008-06-22 19:21:39.000000000 +0200
++++ linux-2.6.13.perfctr26/include/asm-x86_64/irq.h 2008-06-22 19:24:26.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -374,8 +397,8 @@
#ifdef CONFIG_PCI_MSI
#define NR_IRQS FIRST_SYSTEM_VECTOR
---- linux-2.6.13.perfctr26/include/asm-x86_64/processor.h.~1~ 2005-08-29 14:34:33.000000000 +0200
-+++ linux-2.6.13.perfctr26/include/asm-x86_64/processor.h 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/include/asm-x86_64/processor.h.~1~ 2008-06-22 19:21:39.000000000 +0200
++++ linux-2.6.13.perfctr26/include/asm-x86_64/processor.h 2008-06-22 19:24:26.000000000 +0200
@@ -252,6 +252,8 @@ struct thread_struct {
unsigned io_bitmap_max;
/* cached TLS descriptors. */
@@ -385,8 +408,8 @@
} __attribute__((aligned(16)));
#define INIT_THREAD {}
---- linux-2.6.13.perfctr26/include/asm-x86_64/system.h.~1~ 2005-08-29 14:34:33.000000000 +0200
-+++ linux-2.6.13.perfctr26/include/asm-x86_64/system.h 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/include/asm-x86_64/system.h.~1~ 2008-06-22 19:21:39.000000000 +0200
++++ linux-2.6.13.perfctr26/include/asm-x86_64/system.h 2008-06-22 19:24:26.000000000 +0200
@@ -26,7 +26,8 @@
#define __EXTRA_CLOBBER \
,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
@@ -407,8 +430,8 @@
extern void load_gs_index(unsigned);
---- linux-2.6.13.perfctr26/kernel/exit.c.~1~ 2005-08-29 14:34:34.000000000 +0200
-+++ linux-2.6.13.perfctr26/kernel/exit.c 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/kernel/exit.c.~1~ 2008-06-22 19:21:39.000000000 +0200
++++ linux-2.6.13.perfctr26/kernel/exit.c 2008-06-22 19:24:26.000000000 +0200
@@ -25,6 +25,7 @@
#include <linux/mount.h>
#include <linux/proc_fs.h>
@@ -425,8 +448,8 @@
sched_exit(p);
write_unlock_irq(&tasklist_lock);
spin_unlock(&p->proc_lock);
---- linux-2.6.13.perfctr26/kernel/sched.c.~1~ 2005-08-29 14:34:34.000000000 +0200
-+++ linux-2.6.13.perfctr26/kernel/sched.c 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/kernel/sched.c.~1~ 2008-06-22 19:21:39.000000000 +0200
++++ linux-2.6.13.perfctr26/kernel/sched.c 2008-06-22 19:24:26.000000000 +0200
@@ -42,6 +42,7 @@
#include <linux/cpu.h>
#include <linux/cpuset.h>
@@ -444,8 +467,8 @@
rq = task_rq_lock(p, &flags);
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
---- linux-2.6.13.perfctr26/kernel/timer.c.~1~ 2005-08-29 14:34:34.000000000 +0200
-+++ linux-2.6.13.perfctr26/kernel/timer.c 2005-08-29 14:43:33.000000000 +0200
+--- linux-2.6.13.perfctr26/kernel/timer.c.~1~ 2008-06-22 19:21:39.000000000 +0200
++++ linux-2.6.13.perfctr26/kernel/timer.c 2008-06-22 19:24:26.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/jiffies.h>
#include <linux/posix-timers.h>
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.14 b/src/perfctr-2.6.x/patches/patch-kernel-2.6.14
index ceef1cadfe1a8aed9cb3e66409bc0ecc9e055db7..dc07d786686e6ae6c775a51f513c2aa0a40abcca 100644
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.14
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.14
@@ -1,15 +1,20 @@
---- linux-2.6.14.perfctr26/CREDITS.~1~ 2005-10-28 11:24:05.000000000 +0200
-+++ linux-2.6.14.perfctr26/CREDITS 2005-10-28 13:20:19.000000000 +0200
-@@ -2629,6 +2629,7 @@ N: Mikael Pettersson
- E: mikpe@csd.uu.se
- W: http://www.csd.uu.se/~mikpe/
+--- linux-2.6.14.perfctr26/CREDITS.~1~ 2008-06-22 19:09:53.000000000 +0200
++++ linux-2.6.14.perfctr26/CREDITS 2008-06-22 19:12:23.000000000 +0200
+@@ -2626,9 +2626,10 @@ S: Ottawa, Ontario
+ S: Canada K2P 0X8
+
+ N: Mikael Pettersson
+-E: mikpe@csd.uu.se
+-W: http://www.csd.uu.se/~mikpe/
++E: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/
D: Miscellaneous fixes
+D: Performance-monitoring counters driver
N: Reed H. Petty
E: rhp@draper.net
---- linux-2.6.14.perfctr26/Documentation/ioctl-number.txt.~1~ 2005-03-02 19:24:14.000000000 +0100
-+++ linux-2.6.14.perfctr26/Documentation/ioctl-number.txt 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/Documentation/ioctl-number.txt.~1~ 2008-06-22 19:09:53.000000000 +0200
++++ linux-2.6.14.perfctr26/Documentation/ioctl-number.txt 2008-06-22 19:12:18.000000000 +0200
@@ -190,6 +190,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -19,23 +24,23 @@
0xDD 00-3F ZFCP device driver see drivers/s390/scsi/
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
---- linux-2.6.14.perfctr26/MAINTAINERS.~1~ 2005-10-28 11:24:05.000000000 +0200
-+++ linux-2.6.14.perfctr26/MAINTAINERS 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/MAINTAINERS.~1~ 2008-06-22 19:09:53.000000000 +0200
++++ linux-2.6.14.perfctr26/MAINTAINERS 2008-06-22 19:12:23.000000000 +0200
@@ -1923,6 +1923,12 @@ M: tsbogend@alpha.franken.de
L: netdev@vger.kernel.org
S: Maintained
+PERFORMANCE-MONITORING COUNTERS DRIVER
+P: Mikael Pettersson
-+M: mikpe@csd.uu.se
-+W: http://www.csd.uu.se/~mikpe/linux/perfctr/
++M: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
+S: Maintained
+
PHRAM MTD DRIVER
P: J�rn Engel
M: joern@wh.fh-wedel.de
---- linux-2.6.14.perfctr26/arch/i386/Kconfig.~1~ 2005-10-28 11:24:06.000000000 +0200
-+++ linux-2.6.14.perfctr26/arch/i386/Kconfig 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/arch/i386/Kconfig.~1~ 2008-06-22 19:09:53.000000000 +0200
++++ linux-2.6.14.perfctr26/arch/i386/Kconfig 2008-06-22 19:12:18.000000000 +0200
@@ -945,6 +945,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -45,8 +50,8 @@
source kernel/Kconfig.hz
config PHYSICAL_START
---- linux-2.6.14.perfctr26/arch/i386/kernel/entry.S.~1~ 2005-10-28 11:24:06.000000000 +0200
-+++ linux-2.6.14.perfctr26/arch/i386/kernel/entry.S 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/arch/i386/kernel/entry.S.~1~ 2008-06-22 19:09:53.000000000 +0200
++++ linux-2.6.14.perfctr26/arch/i386/kernel/entry.S 2008-06-22 19:12:18.000000000 +0200
@@ -430,6 +430,16 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -64,8 +69,8 @@
ENTRY(divide_error)
pushl $0 # no error code
pushl $do_divide_error
---- linux-2.6.14.perfctr26/arch/i386/kernel/i8259.c.~1~ 2005-10-28 11:24:06.000000000 +0200
-+++ linux-2.6.14.perfctr26/arch/i386/kernel/i8259.c 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/arch/i386/kernel/i8259.c.~1~ 2008-06-22 17:55:14.000000000 +0200
++++ linux-2.6.14.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 19:12:18.000000000 +0200
@@ -23,6 +23,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -83,8 +88,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.14.perfctr26/arch/i386/kernel/process.c.~1~ 2005-10-28 11:24:06.000000000 +0200
-+++ linux-2.6.14.perfctr26/arch/i386/kernel/process.c 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/arch/i386/kernel/process.c.~1~ 2008-06-22 19:09:53.000000000 +0200
++++ linux-2.6.14.perfctr26/arch/i386/kernel/process.c 2008-06-22 19:12:18.000000000 +0200
@@ -33,6 +33,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -119,8 +124,8 @@
return prev_p;
}
---- linux-2.6.14.perfctr26/arch/ppc/Kconfig.~1~ 2005-10-28 11:24:06.000000000 +0200
-+++ linux-2.6.14.perfctr26/arch/ppc/Kconfig 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/arch/ppc/Kconfig.~1~ 2008-06-22 19:09:53.000000000 +0200
++++ linux-2.6.14.perfctr26/arch/ppc/Kconfig 2008-06-22 19:12:18.000000000 +0200
@@ -288,6 +288,8 @@ config NOT_COHERENT_CACHE
depends on 4xx || 8xx || E200
default y
@@ -130,8 +135,8 @@
endmenu
menu "Platform options"
---- linux-2.6.14.perfctr26/arch/ppc/kernel/head.S.~1~ 2005-10-28 11:24:06.000000000 +0200
-+++ linux-2.6.14.perfctr26/arch/ppc/kernel/head.S 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/arch/ppc/kernel/head.S.~1~ 2008-06-22 19:09:53.000000000 +0200
++++ linux-2.6.14.perfctr26/arch/ppc/kernel/head.S 2008-06-22 19:12:18.000000000 +0200
@@ -502,7 +502,11 @@ SystemCall:
Trap_0f:
EXCEPTION_PROLOG
@@ -144,8 +149,8 @@
/*
* Handle TLB miss for instruction on 603/603e.
---- linux-2.6.14.perfctr26/arch/ppc/kernel/process.c.~1~ 2005-03-02 19:24:14.000000000 +0100
-+++ linux-2.6.14.perfctr26/arch/ppc/kernel/process.c 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/arch/ppc/kernel/process.c.~1~ 2008-06-22 19:09:53.000000000 +0200
++++ linux-2.6.14.perfctr26/arch/ppc/kernel/process.c 2008-06-22 19:12:18.000000000 +0200
@@ -35,6 +35,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -181,8 +186,8 @@
return 0;
}
---- linux-2.6.14.perfctr26/arch/x86_64/Kconfig.~1~ 2005-10-28 11:24:06.000000000 +0200
-+++ linux-2.6.14.perfctr26/arch/x86_64/Kconfig 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/arch/x86_64/Kconfig.~1~ 2008-06-22 19:09:53.000000000 +0200
++++ linux-2.6.14.perfctr26/arch/x86_64/Kconfig 2008-06-22 19:12:18.000000000 +0200
@@ -419,6 +419,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -192,8 +197,8 @@
source kernel/Kconfig.hz
endmenu
---- linux-2.6.14.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2005-10-28 11:24:06.000000000 +0200
-+++ linux-2.6.14.perfctr26/arch/x86_64/kernel/entry.S 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2008-06-22 19:09:53.000000000 +0200
++++ linux-2.6.14.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 19:12:18.000000000 +0200
@@ -645,6 +645,11 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
#endif
@@ -206,8 +211,8 @@
/*
* Exception entry points.
*/
---- linux-2.6.14.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2005-10-28 11:24:06.000000000 +0200
-+++ linux-2.6.14.perfctr26/arch/x86_64/kernel/i8259.c 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2008-06-22 19:09:53.000000000 +0200
++++ linux-2.6.14.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 19:12:18.000000000 +0200
@@ -23,6 +23,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -225,8 +230,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.14.perfctr26/arch/x86_64/kernel/process.c.~1~ 2005-10-28 11:24:06.000000000 +0200
-+++ linux-2.6.14.perfctr26/arch/x86_64/kernel/process.c 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/arch/x86_64/kernel/process.c.~1~ 2008-06-22 19:09:53.000000000 +0200
++++ linux-2.6.14.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 19:12:18.000000000 +0200
@@ -33,6 +33,7 @@
#include <linux/interrupt.h>
#include <linux/delay.h>
@@ -261,8 +266,8 @@
return prev_p;
}
---- linux-2.6.14.perfctr26/drivers/Makefile.~1~ 2005-10-28 11:24:07.000000000 +0200
-+++ linux-2.6.14.perfctr26/drivers/Makefile 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/drivers/Makefile.~1~ 2008-06-22 19:09:54.000000000 +0200
++++ linux-2.6.14.perfctr26/drivers/Makefile 2008-06-22 19:12:18.000000000 +0200
@@ -65,5 +65,6 @@ obj-$(CONFIG_CPU_FREQ) += cpufreq/
obj-$(CONFIG_MMC) += mmc/
obj-$(CONFIG_INFINIBAND) += infiniband/
@@ -270,8 +275,26 @@
+obj-$(CONFIG_KPERFCTR) += perfctr/
obj-y += firmware/
obj-$(CONFIG_CRYPTO) += crypto/
---- linux-2.6.14.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2004-05-10 11:14:37.000000000 +0200
-+++ linux-2.6.14.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/fs/exec.c.~1~ 2008-06-22 19:09:55.000000000 +0200
++++ linux-2.6.14.perfctr26/fs/exec.c 2008-06-22 19:12:23.000000000 +0200
+@@ -48,6 +48,7 @@
+ #include <linux/syscalls.h>
+ #include <linux/rmap.h>
+ #include <linux/acct.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -892,6 +893,7 @@ int flush_old_exec(struct linux_binprm *
+ set_task_comm(current, tcomm);
+
+ current->flags &= ~PF_RANDOMIZE;
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ if (bprm->e_uid != current->euid || bprm->e_gid != current->egid ||
+--- linux-2.6.14.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.14.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 19:12:18.000000000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -290,8 +313,8 @@
#define TIMER_IRQ 0
---- linux-2.6.14.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2004-01-09 13:19:11.000000000 +0100
-+++ linux-2.6.14.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.14.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 19:12:18.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -310,8 +333,8 @@
#define TIMER_IRQ 0
---- linux-2.6.14.perfctr26/include/asm-i386/processor.h.~1~ 2005-10-28 11:24:11.000000000 +0200
-+++ linux-2.6.14.perfctr26/include/asm-i386/processor.h 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/include/asm-i386/processor.h.~1~ 2008-06-22 19:09:55.000000000 +0200
++++ linux-2.6.14.perfctr26/include/asm-i386/processor.h 2008-06-22 19:12:18.000000000 +0200
@@ -458,6 +458,8 @@ struct thread_struct {
unsigned long iopl;
/* max allowed port in the bitmap, in bytes: */
@@ -321,8 +344,8 @@
};
#define INIT_THREAD { \
---- linux-2.6.14.perfctr26/include/asm-i386/system.h.~1~ 2005-10-28 11:24:11.000000000 +0200
-+++ linux-2.6.14.perfctr26/include/asm-i386/system.h 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/include/asm-i386/system.h.~1~ 2008-06-22 19:09:55.000000000 +0200
++++ linux-2.6.14.perfctr26/include/asm-i386/system.h 2008-06-22 19:12:18.000000000 +0200
@@ -14,6 +14,7 @@ extern struct task_struct * FASTCALL(__s
#define switch_to(prev,next,last) do { \
@@ -331,8 +354,8 @@
asm volatile("pushl %%ebp\n\t" \
"movl %%esp,%0\n\t" /* save ESP */ \
"movl %5,%%esp\n\t" /* restore ESP */ \
---- linux-2.6.14.perfctr26/include/asm-ppc/processor.h.~1~ 2005-03-02 19:24:19.000000000 +0100
-+++ linux-2.6.14.perfctr26/include/asm-ppc/processor.h 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/include/asm-ppc/processor.h.~1~ 2008-06-22 19:09:55.000000000 +0200
++++ linux-2.6.14.perfctr26/include/asm-ppc/processor.h 2008-06-22 19:12:18.000000000 +0200
@@ -122,6 +122,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
@@ -343,8 +366,8 @@
};
#define ARCH_MIN_TASKALIGN 16
---- linux-2.6.14.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2005-10-28 11:24:12.000000000 +0200
-+++ linux-2.6.14.perfctr26/include/asm-x86_64/hw_irq.h 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2008-06-22 19:09:55.000000000 +0200
++++ linux-2.6.14.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 19:12:18.000000000 +0200
@@ -67,14 +67,15 @@ struct hw_interrupt_type;
* sources per level' errata.
*/
@@ -363,8 +386,8 @@
#ifndef __ASSEMBLY__
---- linux-2.6.14.perfctr26/include/asm-x86_64/irq.h.~1~ 2005-10-28 11:24:12.000000000 +0200
-+++ linux-2.6.14.perfctr26/include/asm-x86_64/irq.h 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/include/asm-x86_64/irq.h.~1~ 2008-06-22 18:22:12.000000000 +0200
++++ linux-2.6.14.perfctr26/include/asm-x86_64/irq.h 2008-06-22 19:12:18.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -374,8 +397,8 @@
#ifdef CONFIG_PCI_MSI
#define NR_IRQS FIRST_SYSTEM_VECTOR
---- linux-2.6.14.perfctr26/include/asm-x86_64/processor.h.~1~ 2005-10-28 11:24:12.000000000 +0200
-+++ linux-2.6.14.perfctr26/include/asm-x86_64/processor.h 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/include/asm-x86_64/processor.h.~1~ 2008-06-22 19:09:55.000000000 +0200
++++ linux-2.6.14.perfctr26/include/asm-x86_64/processor.h 2008-06-22 19:12:18.000000000 +0200
@@ -252,6 +252,8 @@ struct thread_struct {
unsigned io_bitmap_max;
/* cached TLS descriptors. */
@@ -385,8 +408,8 @@
} __attribute__((aligned(16)));
#define INIT_THREAD { \
---- linux-2.6.14.perfctr26/include/asm-x86_64/system.h.~1~ 2005-10-28 11:24:12.000000000 +0200
-+++ linux-2.6.14.perfctr26/include/asm-x86_64/system.h 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/include/asm-x86_64/system.h.~1~ 2008-06-22 18:22:12.000000000 +0200
++++ linux-2.6.14.perfctr26/include/asm-x86_64/system.h 2008-06-22 19:12:18.000000000 +0200
@@ -26,7 +26,8 @@
#define __EXTRA_CLOBBER \
,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
@@ -407,8 +430,8 @@
extern void load_gs_index(unsigned);
---- linux-2.6.14.perfctr26/kernel/exit.c.~1~ 2005-10-28 11:24:12.000000000 +0200
-+++ linux-2.6.14.perfctr26/kernel/exit.c 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/kernel/exit.c.~1~ 2008-06-22 19:09:55.000000000 +0200
++++ linux-2.6.14.perfctr26/kernel/exit.c 2008-06-22 19:12:18.000000000 +0200
@@ -25,6 +25,7 @@
#include <linux/mount.h>
#include <linux/proc_fs.h>
@@ -425,8 +448,8 @@
sched_exit(p);
write_unlock_irq(&tasklist_lock);
spin_unlock(&p->proc_lock);
---- linux-2.6.14.perfctr26/kernel/sched.c.~1~ 2005-10-28 11:24:12.000000000 +0200
-+++ linux-2.6.14.perfctr26/kernel/sched.c 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/kernel/sched.c.~1~ 2008-06-22 19:09:55.000000000 +0200
++++ linux-2.6.14.perfctr26/kernel/sched.c 2008-06-22 19:12:18.000000000 +0200
@@ -42,6 +42,7 @@
#include <linux/cpu.h>
#include <linux/cpuset.h>
@@ -444,8 +467,8 @@
rq = task_rq_lock(p, &flags);
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
---- linux-2.6.14.perfctr26/kernel/timer.c.~1~ 2005-10-28 11:24:12.000000000 +0200
-+++ linux-2.6.14.perfctr26/kernel/timer.c 2005-10-28 13:20:19.000000000 +0200
+--- linux-2.6.14.perfctr26/kernel/timer.c.~1~ 2008-06-22 19:09:55.000000000 +0200
++++ linux-2.6.14.perfctr26/kernel/timer.c 2008-06-22 19:12:18.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/jiffies.h>
#include <linux/posix-timers.h>
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.15 b/src/perfctr-2.6.x/patches/patch-kernel-2.6.15
index dfaba15283d3d29e09451182793f884149c9d8b3..a18a270df4e4b0a7c4d8e4395390b6cc4216d653 100644
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.15
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.15
@@ -1,15 +1,20 @@
---- linux-2.6.15.perfctr26/CREDITS.~1~ 2006-01-03 11:51:54.000000000 +0100
-+++ linux-2.6.15.perfctr26/CREDITS 2006-01-03 11:59:09.000000000 +0100
-@@ -2634,6 +2634,7 @@ N: Mikael Pettersson
- E: mikpe@csd.uu.se
- W: http://www.csd.uu.se/~mikpe/
+--- linux-2.6.15.perfctr26/CREDITS.~1~ 2008-06-22 18:22:10.000000000 +0200
++++ linux-2.6.15.perfctr26/CREDITS 2008-06-22 18:25:45.000000000 +0200
+@@ -2631,9 +2631,10 @@ S: Ottawa, Ontario
+ S: Canada K2P 0X8
+
+ N: Mikael Pettersson
+-E: mikpe@csd.uu.se
+-W: http://www.csd.uu.se/~mikpe/
++E: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/
D: Miscellaneous fixes
+D: Performance-monitoring counters driver
N: Reed H. Petty
E: rhp@draper.net
---- linux-2.6.15.perfctr26/Documentation/ioctl-number.txt.~1~ 2006-01-03 11:51:55.000000000 +0100
-+++ linux-2.6.15.perfctr26/Documentation/ioctl-number.txt 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/Documentation/ioctl-number.txt.~1~ 2008-06-22 18:08:15.000000000 +0200
++++ linux-2.6.15.perfctr26/Documentation/ioctl-number.txt 2008-06-22 18:25:38.000000000 +0200
@@ -188,6 +188,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -19,23 +24,23 @@
0xDD 00-3F ZFCP device driver see drivers/s390/scsi/
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
---- linux-2.6.15.perfctr26/MAINTAINERS.~1~ 2006-01-03 11:51:55.000000000 +0100
-+++ linux-2.6.15.perfctr26/MAINTAINERS 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/MAINTAINERS.~1~ 2008-06-22 18:22:10.000000000 +0200
++++ linux-2.6.15.perfctr26/MAINTAINERS 2008-06-22 18:25:45.000000000 +0200
@@ -2027,6 +2027,12 @@ M: tsbogend@alpha.franken.de
L: netdev@vger.kernel.org
S: Maintained
+PERFORMANCE-MONITORING COUNTERS DRIVER
+P: Mikael Pettersson
-+M: mikpe@csd.uu.se
-+W: http://www.csd.uu.se/~mikpe/linux/perfctr/
++M: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
+S: Maintained
+
PHRAM MTD DRIVER
P: J�rn Engel
M: joern@wh.fh-wedel.de
---- linux-2.6.15.perfctr26/arch/i386/Kconfig.~1~ 2006-01-03 11:51:55.000000000 +0100
-+++ linux-2.6.15.perfctr26/arch/i386/Kconfig 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/arch/i386/Kconfig.~1~ 2008-06-22 18:22:11.000000000 +0200
++++ linux-2.6.15.perfctr26/arch/i386/Kconfig 2008-06-22 18:25:38.000000000 +0200
@@ -647,6 +647,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -45,8 +50,8 @@
source kernel/Kconfig.hz
config PHYSICAL_START
---- linux-2.6.15.perfctr26/arch/i386/kernel/entry.S.~1~ 2006-01-03 11:51:55.000000000 +0100
-+++ linux-2.6.15.perfctr26/arch/i386/kernel/entry.S 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/arch/i386/kernel/entry.S.~1~ 2008-06-22 18:22:11.000000000 +0200
++++ linux-2.6.15.perfctr26/arch/i386/kernel/entry.S 2008-06-22 18:25:38.000000000 +0200
@@ -430,6 +430,16 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -64,8 +69,8 @@
ENTRY(divide_error)
pushl $0 # no error code
pushl $do_divide_error
---- linux-2.6.15.perfctr26/arch/i386/kernel/i8259.c.~1~ 2005-10-28 11:24:06.000000000 +0200
-+++ linux-2.6.15.perfctr26/arch/i386/kernel/i8259.c 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/arch/i386/kernel/i8259.c.~1~ 2008-06-22 17:55:14.000000000 +0200
++++ linux-2.6.15.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 18:25:38.000000000 +0200
@@ -23,6 +23,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -83,8 +88,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.15.perfctr26/arch/i386/kernel/process.c.~1~ 2006-01-03 11:51:55.000000000 +0100
-+++ linux-2.6.15.perfctr26/arch/i386/kernel/process.c 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/arch/i386/kernel/process.c.~1~ 2008-06-22 18:22:11.000000000 +0200
++++ linux-2.6.15.perfctr26/arch/i386/kernel/process.c 2008-06-22 18:25:38.000000000 +0200
@@ -33,6 +33,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -119,8 +124,8 @@
return prev_p;
}
---- linux-2.6.15.perfctr26/arch/powerpc/Kconfig.~1~ 2006-01-03 11:51:55.000000000 +0100
-+++ linux-2.6.15.perfctr26/arch/powerpc/Kconfig 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/arch/powerpc/Kconfig.~1~ 2008-06-22 18:22:11.000000000 +0200
++++ linux-2.6.15.perfctr26/arch/powerpc/Kconfig 2008-06-22 18:25:38.000000000 +0200
@@ -237,6 +237,11 @@ config NOT_COHERENT_CACHE
bool
depends on 4xx || 8xx || E200
@@ -133,8 +138,8 @@
endmenu
source "init/Kconfig"
---- linux-2.6.15.perfctr26/arch/powerpc/kernel/head_32.S.~1~ 2006-01-03 11:51:55.000000000 +0100
-+++ linux-2.6.15.perfctr26/arch/powerpc/kernel/head_32.S 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/arch/powerpc/kernel/head_32.S.~1~ 2008-06-22 18:22:11.000000000 +0200
++++ linux-2.6.15.perfctr26/arch/powerpc/kernel/head_32.S 2008-06-22 18:25:38.000000000 +0200
@@ -458,7 +458,11 @@ SystemCall:
Trap_0f:
EXCEPTION_PROLOG
@@ -147,8 +152,8 @@
/*
* Handle TLB miss for instruction on 603/603e.
---- linux-2.6.15.perfctr26/arch/powerpc/kernel/process.c.~1~ 2006-01-03 11:51:55.000000000 +0100
-+++ linux-2.6.15.perfctr26/arch/powerpc/kernel/process.c 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/arch/powerpc/kernel/process.c.~1~ 2008-06-22 18:22:11.000000000 +0200
++++ linux-2.6.15.perfctr26/arch/powerpc/kernel/process.c 2008-06-22 18:25:38.000000000 +0200
@@ -34,6 +34,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -184,8 +189,8 @@
return 0;
}
---- linux-2.6.15.perfctr26/arch/ppc/Kconfig.~1~ 2006-01-03 11:51:56.000000000 +0100
-+++ linux-2.6.15.perfctr26/arch/ppc/Kconfig 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/arch/ppc/Kconfig.~1~ 2008-06-22 18:22:11.000000000 +0200
++++ linux-2.6.15.perfctr26/arch/ppc/Kconfig 2008-06-22 18:25:38.000000000 +0200
@@ -288,6 +288,8 @@ config NOT_COHERENT_CACHE
depends on 4xx || 8xx || E200
default y
@@ -195,8 +200,8 @@
endmenu
menu "Platform options"
---- linux-2.6.15.perfctr26/arch/ppc/kernel/head.S.~1~ 2006-01-03 11:51:56.000000000 +0100
-+++ linux-2.6.15.perfctr26/arch/ppc/kernel/head.S 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/arch/ppc/kernel/head.S.~1~ 2008-06-22 18:22:11.000000000 +0200
++++ linux-2.6.15.perfctr26/arch/ppc/kernel/head.S 2008-06-22 18:25:38.000000000 +0200
@@ -502,7 +502,11 @@ SystemCall:
Trap_0f:
EXCEPTION_PROLOG
@@ -209,8 +214,8 @@
/*
* Handle TLB miss for instruction on 603/603e.
---- linux-2.6.15.perfctr26/arch/ppc/kernel/process.c.~1~ 2006-01-03 11:51:56.000000000 +0100
-+++ linux-2.6.15.perfctr26/arch/ppc/kernel/process.c 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/arch/ppc/kernel/process.c.~1~ 2008-06-22 18:22:11.000000000 +0200
++++ linux-2.6.15.perfctr26/arch/ppc/kernel/process.c 2008-06-22 18:25:38.000000000 +0200
@@ -35,6 +35,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -246,8 +251,8 @@
return 0;
}
---- linux-2.6.15.perfctr26/arch/x86_64/Kconfig.~1~ 2006-01-03 11:51:56.000000000 +0100
-+++ linux-2.6.15.perfctr26/arch/x86_64/Kconfig 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/arch/x86_64/Kconfig.~1~ 2008-06-22 18:22:11.000000000 +0200
++++ linux-2.6.15.perfctr26/arch/x86_64/Kconfig 2008-06-22 18:25:38.000000000 +0200
@@ -444,6 +444,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -257,8 +262,8 @@
source kernel/Kconfig.hz
endmenu
---- linux-2.6.15.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2006-01-03 11:51:56.000000000 +0100
-+++ linux-2.6.15.perfctr26/arch/x86_64/kernel/entry.S 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2008-06-22 18:22:11.000000000 +0200
++++ linux-2.6.15.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 18:25:38.000000000 +0200
@@ -648,6 +648,11 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
#endif
@@ -271,8 +276,8 @@
/*
* Exception entry points.
*/
---- linux-2.6.15.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2006-01-03 11:51:56.000000000 +0100
-+++ linux-2.6.15.perfctr26/arch/x86_64/kernel/i8259.c 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2008-06-22 18:22:11.000000000 +0200
++++ linux-2.6.15.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 18:25:38.000000000 +0200
@@ -23,6 +23,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -290,8 +295,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.15.perfctr26/arch/x86_64/kernel/process.c.~1~ 2006-01-03 11:51:56.000000000 +0100
-+++ linux-2.6.15.perfctr26/arch/x86_64/kernel/process.c 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/arch/x86_64/kernel/process.c.~1~ 2008-06-22 18:22:11.000000000 +0200
++++ linux-2.6.15.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 18:25:38.000000000 +0200
@@ -33,6 +33,7 @@
#include <linux/interrupt.h>
#include <linux/delay.h>
@@ -326,8 +331,8 @@
return prev_p;
}
---- linux-2.6.15.perfctr26/drivers/Makefile.~1~ 2006-01-03 11:51:56.000000000 +0100
-+++ linux-2.6.15.perfctr26/drivers/Makefile 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/drivers/Makefile.~1~ 2008-06-22 18:22:11.000000000 +0200
++++ linux-2.6.15.perfctr26/drivers/Makefile 2008-06-22 18:25:38.000000000 +0200
@@ -67,6 +67,7 @@ obj-$(CONFIG_CPU_FREQ) += cpufreq/
obj-$(CONFIG_MMC) += mmc/
obj-$(CONFIG_INFINIBAND) += infiniband/
@@ -336,8 +341,26 @@
obj-y += firmware/
obj-$(CONFIG_CRYPTO) += crypto/
obj-$(CONFIG_SUPERH) += sh/
---- linux-2.6.15.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2004-05-10 11:14:37.000000000 +0200
-+++ linux-2.6.15.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/fs/exec.c.~1~ 2008-06-22 18:22:12.000000000 +0200
++++ linux-2.6.15.perfctr26/fs/exec.c 2008-06-22 18:25:45.000000000 +0200
+@@ -49,6 +49,7 @@
+ #include <linux/rmap.h>
+ #include <linux/acct.h>
+ #include <linux/cn_proc.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -883,6 +884,7 @@ int flush_old_exec(struct linux_binprm *
+ set_task_comm(current, tcomm);
+
+ current->flags &= ~PF_RANDOMIZE;
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ if (bprm->e_uid != current->euid || bprm->e_gid != current->egid ||
+--- linux-2.6.15.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.15.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 18:25:38.000000000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -356,8 +379,8 @@
#define TIMER_IRQ 0
---- linux-2.6.15.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2004-01-09 13:19:11.000000000 +0100
-+++ linux-2.6.15.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.15.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 18:25:38.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -376,8 +399,8 @@
#define TIMER_IRQ 0
---- linux-2.6.15.perfctr26/include/asm-i386/processor.h.~1~ 2006-01-03 11:52:02.000000000 +0100
-+++ linux-2.6.15.perfctr26/include/asm-i386/processor.h 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/include/asm-i386/processor.h.~1~ 2008-06-22 18:22:12.000000000 +0200
++++ linux-2.6.15.perfctr26/include/asm-i386/processor.h 2008-06-22 18:25:38.000000000 +0200
@@ -460,6 +460,8 @@ struct thread_struct {
unsigned long iopl;
/* max allowed port in the bitmap, in bytes: */
@@ -387,8 +410,8 @@
};
#define INIT_THREAD { \
---- linux-2.6.15.perfctr26/include/asm-i386/system.h.~1~ 2006-01-03 11:52:02.000000000 +0100
-+++ linux-2.6.15.perfctr26/include/asm-i386/system.h 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/include/asm-i386/system.h.~1~ 2008-06-22 18:22:12.000000000 +0200
++++ linux-2.6.15.perfctr26/include/asm-i386/system.h 2008-06-22 18:25:38.000000000 +0200
@@ -14,6 +14,7 @@ extern struct task_struct * FASTCALL(__s
#define switch_to(prev,next,last) do { \
@@ -397,8 +420,8 @@
asm volatile("pushl %%ebp\n\t" \
"movl %%esp,%0\n\t" /* save ESP */ \
"movl %5,%%esp\n\t" /* restore ESP */ \
---- linux-2.6.15.perfctr26/include/asm-powerpc/processor.h.~1~ 2006-01-03 11:52:06.000000000 +0100
-+++ linux-2.6.15.perfctr26/include/asm-powerpc/processor.h 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/include/asm-powerpc/processor.h.~1~ 2008-06-22 18:22:12.000000000 +0200
++++ linux-2.6.15.perfctr26/include/asm-powerpc/processor.h 2008-06-22 18:25:38.000000000 +0200
@@ -194,6 +194,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
@@ -409,8 +432,8 @@
};
#define ARCH_MIN_TASKALIGN 16
---- linux-2.6.15.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2006-01-03 11:52:07.000000000 +0100
-+++ linux-2.6.15.perfctr26/include/asm-x86_64/hw_irq.h 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2008-06-22 18:22:12.000000000 +0200
++++ linux-2.6.15.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 18:25:38.000000000 +0200
@@ -67,14 +67,15 @@ struct hw_interrupt_type;
* sources per level' errata.
*/
@@ -429,8 +452,8 @@
#ifndef __ASSEMBLY__
---- linux-2.6.15.perfctr26/include/asm-x86_64/irq.h.~1~ 2005-10-28 11:24:12.000000000 +0200
-+++ linux-2.6.15.perfctr26/include/asm-x86_64/irq.h 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/include/asm-x86_64/irq.h.~1~ 2008-06-22 18:22:12.000000000 +0200
++++ linux-2.6.15.perfctr26/include/asm-x86_64/irq.h 2008-06-22 18:25:38.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -440,8 +463,8 @@
#ifdef CONFIG_PCI_MSI
#define NR_IRQS FIRST_SYSTEM_VECTOR
---- linux-2.6.15.perfctr26/include/asm-x86_64/processor.h.~1~ 2006-01-03 11:52:07.000000000 +0100
-+++ linux-2.6.15.perfctr26/include/asm-x86_64/processor.h 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/include/asm-x86_64/processor.h.~1~ 2008-06-22 18:22:12.000000000 +0200
++++ linux-2.6.15.perfctr26/include/asm-x86_64/processor.h 2008-06-22 18:25:38.000000000 +0200
@@ -254,6 +254,8 @@ struct thread_struct {
unsigned io_bitmap_max;
/* cached TLS descriptors. */
@@ -451,8 +474,8 @@
} __attribute__((aligned(16)));
#define INIT_THREAD { \
---- linux-2.6.15.perfctr26/include/asm-x86_64/system.h.~1~ 2005-10-28 11:24:12.000000000 +0200
-+++ linux-2.6.15.perfctr26/include/asm-x86_64/system.h 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/include/asm-x86_64/system.h.~1~ 2008-06-22 18:22:12.000000000 +0200
++++ linux-2.6.15.perfctr26/include/asm-x86_64/system.h 2008-06-22 18:25:38.000000000 +0200
@@ -26,7 +26,8 @@
#define __EXTRA_CLOBBER \
,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
@@ -473,8 +496,8 @@
extern void load_gs_index(unsigned);
---- linux-2.6.15.perfctr26/kernel/exit.c.~1~ 2006-01-03 11:52:07.000000000 +0100
-+++ linux-2.6.15.perfctr26/kernel/exit.c 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/kernel/exit.c.~1~ 2008-06-22 18:22:12.000000000 +0200
++++ linux-2.6.15.perfctr26/kernel/exit.c 2008-06-22 18:25:38.000000000 +0200
@@ -25,6 +25,7 @@
#include <linux/mount.h>
#include <linux/proc_fs.h>
@@ -491,8 +514,8 @@
sched_exit(p);
write_unlock_irq(&tasklist_lock);
spin_unlock(&p->proc_lock);
---- linux-2.6.15.perfctr26/kernel/sched.c.~1~ 2006-01-03 11:52:07.000000000 +0100
-+++ linux-2.6.15.perfctr26/kernel/sched.c 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/kernel/sched.c.~1~ 2008-06-22 18:22:12.000000000 +0200
++++ linux-2.6.15.perfctr26/kernel/sched.c 2008-06-22 18:25:38.000000000 +0200
@@ -42,6 +42,7 @@
#include <linux/cpu.h>
#include <linux/cpuset.h>
@@ -510,8 +533,8 @@
rq = task_rq_lock(p, &flags);
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
---- linux-2.6.15.perfctr26/kernel/timer.c.~1~ 2006-01-03 11:52:07.000000000 +0100
-+++ linux-2.6.15.perfctr26/kernel/timer.c 2006-01-03 11:59:09.000000000 +0100
+--- linux-2.6.15.perfctr26/kernel/timer.c.~1~ 2008-06-22 18:22:12.000000000 +0200
++++ linux-2.6.15.perfctr26/kernel/timer.c 2008-06-22 18:25:38.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/jiffies.h>
#include <linux/posix-timers.h>
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.16 b/src/perfctr-2.6.x/patches/patch-kernel-2.6.16
index 3519572bf9bd06db9b521df210c3ca3790554bd2..184b51252c12826c0ed23d89c561ae65bddb1d0d 100644
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.16
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.16
@@ -1,15 +1,20 @@
---- linux-2.6.16.perfctr26/CREDITS.~1~ 2006-03-20 10:40:00.000000000 +0100
-+++ linux-2.6.16.perfctr26/CREDITS 2006-03-20 10:51:04.000000000 +0100
-@@ -2634,6 +2634,7 @@ N: Mikael Pettersson
- E: mikpe@csd.uu.se
- W: http://www.csd.uu.se/~mikpe/
+--- linux-2.6.16.perfctr26/CREDITS.~1~ 2008-06-22 18:08:15.000000000 +0200
++++ linux-2.6.16.perfctr26/CREDITS 2008-06-22 18:11:22.000000000 +0200
+@@ -2631,9 +2631,10 @@ S: Ottawa, Ontario
+ S: Canada K2P 0X8
+
+ N: Mikael Pettersson
+-E: mikpe@csd.uu.se
+-W: http://www.csd.uu.se/~mikpe/
++E: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/
D: Miscellaneous fixes
+D: Performance-monitoring counters driver
N: Reed H. Petty
E: rhp@draper.net
---- linux-2.6.16.perfctr26/Documentation/ioctl-number.txt.~1~ 2006-01-03 11:51:55.000000000 +0100
-+++ linux-2.6.16.perfctr26/Documentation/ioctl-number.txt 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/Documentation/ioctl-number.txt.~1~ 2008-06-22 18:08:15.000000000 +0200
++++ linux-2.6.16.perfctr26/Documentation/ioctl-number.txt 2008-06-22 18:11:15.000000000 +0200
@@ -188,6 +188,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -19,23 +24,23 @@
0xDD 00-3F ZFCP device driver see drivers/s390/scsi/
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
---- linux-2.6.16.perfctr26/MAINTAINERS.~1~ 2006-03-20 10:40:00.000000000 +0100
-+++ linux-2.6.16.perfctr26/MAINTAINERS 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/MAINTAINERS.~1~ 2008-06-22 18:08:15.000000000 +0200
++++ linux-2.6.16.perfctr26/MAINTAINERS 2008-06-22 18:11:22.000000000 +0200
@@ -2071,6 +2071,12 @@ M: tsbogend@alpha.franken.de
L: netdev@vger.kernel.org
S: Maintained
+PERFORMANCE-MONITORING COUNTERS DRIVER
+P: Mikael Pettersson
-+M: mikpe@csd.uu.se
-+W: http://www.csd.uu.se/~mikpe/linux/perfctr/
++M: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
+S: Maintained
+
PHRAM MTD DRIVER
P: J�rn Engel
M: joern@wh.fh-wedel.de
---- linux-2.6.16.perfctr26/arch/i386/Kconfig.~1~ 2006-03-20 10:40:00.000000000 +0100
-+++ linux-2.6.16.perfctr26/arch/i386/Kconfig 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/arch/i386/Kconfig.~1~ 2008-06-22 18:08:15.000000000 +0200
++++ linux-2.6.16.perfctr26/arch/i386/Kconfig 2008-06-22 18:11:15.000000000 +0200
@@ -685,6 +685,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -45,8 +50,8 @@
source kernel/Kconfig.hz
config KEXEC
---- linux-2.6.16.perfctr26/arch/i386/kernel/entry.S.~1~ 2006-03-20 10:40:00.000000000 +0100
-+++ linux-2.6.16.perfctr26/arch/i386/kernel/entry.S 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/arch/i386/kernel/entry.S.~1~ 2008-06-22 18:08:15.000000000 +0200
++++ linux-2.6.16.perfctr26/arch/i386/kernel/entry.S 2008-06-22 18:11:15.000000000 +0200
@@ -432,6 +432,16 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -64,8 +69,8 @@
ENTRY(divide_error)
pushl $0 # no error code
pushl $do_divide_error
---- linux-2.6.16.perfctr26/arch/i386/kernel/i8259.c.~1~ 2005-10-28 11:24:06.000000000 +0200
-+++ linux-2.6.16.perfctr26/arch/i386/kernel/i8259.c 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/arch/i386/kernel/i8259.c.~1~ 2008-06-22 17:55:14.000000000 +0200
++++ linux-2.6.16.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 18:11:15.000000000 +0200
@@ -23,6 +23,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -83,8 +88,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.16.perfctr26/arch/i386/kernel/process.c.~1~ 2006-03-20 10:40:00.000000000 +0100
-+++ linux-2.6.16.perfctr26/arch/i386/kernel/process.c 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/arch/i386/kernel/process.c.~1~ 2008-06-22 18:08:15.000000000 +0200
++++ linux-2.6.16.perfctr26/arch/i386/kernel/process.c 2008-06-22 18:11:15.000000000 +0200
@@ -33,6 +33,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -119,8 +124,8 @@
return prev_p;
}
---- linux-2.6.16.perfctr26/arch/powerpc/Kconfig.~1~ 2006-03-20 10:40:01.000000000 +0100
-+++ linux-2.6.16.perfctr26/arch/powerpc/Kconfig 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/arch/powerpc/Kconfig.~1~ 2008-06-22 18:08:15.000000000 +0200
++++ linux-2.6.16.perfctr26/arch/powerpc/Kconfig 2008-06-22 18:11:15.000000000 +0200
@@ -268,6 +268,11 @@ config NOT_COHERENT_CACHE
bool
depends on 4xx || 8xx || E200
@@ -133,8 +138,8 @@
endmenu
source "init/Kconfig"
---- linux-2.6.16.perfctr26/arch/powerpc/kernel/process.c.~1~ 2006-03-20 10:40:01.000000000 +0100
-+++ linux-2.6.16.perfctr26/arch/powerpc/kernel/process.c 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/arch/powerpc/kernel/process.c.~1~ 2008-06-22 18:08:15.000000000 +0200
++++ linux-2.6.16.perfctr26/arch/powerpc/kernel/process.c 2008-06-22 18:11:15.000000000 +0200
@@ -34,6 +34,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -170,8 +175,8 @@
return 0;
}
---- linux-2.6.16.perfctr26/arch/x86_64/Kconfig.~1~ 2006-03-20 10:40:03.000000000 +0100
-+++ linux-2.6.16.perfctr26/arch/x86_64/Kconfig 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/arch/x86_64/Kconfig.~1~ 2008-06-22 18:08:16.000000000 +0200
++++ linux-2.6.16.perfctr26/arch/x86_64/Kconfig 2008-06-22 18:11:15.000000000 +0200
@@ -462,6 +462,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -181,8 +186,8 @@
source kernel/Kconfig.hz
endmenu
---- linux-2.6.16.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2006-03-20 10:40:03.000000000 +0100
-+++ linux-2.6.16.perfctr26/arch/x86_64/kernel/entry.S 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2008-06-22 18:08:16.000000000 +0200
++++ linux-2.6.16.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 18:11:15.000000000 +0200
@@ -655,6 +655,11 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
#endif
@@ -195,8 +200,8 @@
/*
* Exception entry points.
*/
---- linux-2.6.16.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2006-03-20 10:40:03.000000000 +0100
-+++ linux-2.6.16.perfctr26/arch/x86_64/kernel/i8259.c 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2008-06-22 17:55:14.000000000 +0200
++++ linux-2.6.16.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 18:11:15.000000000 +0200
@@ -23,6 +23,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -214,8 +219,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.16.perfctr26/arch/x86_64/kernel/process.c.~1~ 2006-03-20 10:40:03.000000000 +0100
-+++ linux-2.6.16.perfctr26/arch/x86_64/kernel/process.c 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/arch/x86_64/kernel/process.c.~1~ 2008-06-22 18:08:16.000000000 +0200
++++ linux-2.6.16.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 18:11:15.000000000 +0200
@@ -33,6 +33,7 @@
#include <linux/interrupt.h>
#include <linux/delay.h>
@@ -250,8 +255,8 @@
return prev_p;
}
---- linux-2.6.16.perfctr26/drivers/Makefile.~1~ 2006-03-20 10:40:03.000000000 +0100
-+++ linux-2.6.16.perfctr26/drivers/Makefile 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/drivers/Makefile.~1~ 2008-06-22 18:08:16.000000000 +0200
++++ linux-2.6.16.perfctr26/drivers/Makefile 2008-06-22 18:11:15.000000000 +0200
@@ -70,6 +70,7 @@ obj-$(CONFIG_CPU_FREQ) += cpufreq/
obj-$(CONFIG_MMC) += mmc/
obj-$(CONFIG_INFINIBAND) += infiniband/
@@ -260,8 +265,26 @@
obj-y += firmware/
obj-$(CONFIG_CRYPTO) += crypto/
obj-$(CONFIG_SUPERH) += sh/
---- linux-2.6.16.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2004-05-10 11:14:37.000000000 +0200
-+++ linux-2.6.16.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/fs/exec.c.~1~ 2008-06-22 18:08:17.000000000 +0200
++++ linux-2.6.16.perfctr26/fs/exec.c 2008-06-22 18:11:22.000000000 +0200
+@@ -49,6 +49,7 @@
+ #include <linux/rmap.h>
+ #include <linux/acct.h>
+ #include <linux/cn_proc.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -883,6 +884,7 @@ int flush_old_exec(struct linux_binprm *
+ set_task_comm(current, tcomm);
+
+ current->flags &= ~PF_RANDOMIZE;
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ /* Set the new mm task size. We have to do that late because it may
+--- linux-2.6.16.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.16.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 18:11:15.000000000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -280,8 +303,8 @@
#define TIMER_IRQ 0
---- linux-2.6.16.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2004-01-09 13:19:11.000000000 +0100
-+++ linux-2.6.16.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.16.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 18:11:15.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -300,8 +323,8 @@
#define TIMER_IRQ 0
---- linux-2.6.16.perfctr26/include/asm-i386/processor.h.~1~ 2006-03-20 10:40:11.000000000 +0100
-+++ linux-2.6.16.perfctr26/include/asm-i386/processor.h 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/include/asm-i386/processor.h.~1~ 2008-06-22 18:08:17.000000000 +0200
++++ linux-2.6.16.perfctr26/include/asm-i386/processor.h 2008-06-22 18:11:15.000000000 +0200
@@ -464,6 +464,8 @@ struct thread_struct {
unsigned long iopl;
/* max allowed port in the bitmap, in bytes: */
@@ -311,8 +334,8 @@
};
#define INIT_THREAD { \
---- linux-2.6.16.perfctr26/include/asm-i386/system.h.~1~ 2006-03-20 10:40:11.000000000 +0100
-+++ linux-2.6.16.perfctr26/include/asm-i386/system.h 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/include/asm-i386/system.h.~1~ 2008-06-22 18:08:17.000000000 +0200
++++ linux-2.6.16.perfctr26/include/asm-i386/system.h 2008-06-22 18:11:15.000000000 +0200
@@ -14,6 +14,7 @@ extern struct task_struct * FASTCALL(__s
#define switch_to(prev,next,last) do { \
@@ -321,8 +344,8 @@
asm volatile("pushl %%ebp\n\t" \
"movl %%esp,%0\n\t" /* save ESP */ \
"movl %5,%%esp\n\t" /* restore ESP */ \
---- linux-2.6.16.perfctr26/include/asm-powerpc/processor.h.~1~ 2006-03-20 10:40:11.000000000 +0100
-+++ linux-2.6.16.perfctr26/include/asm-powerpc/processor.h 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/include/asm-powerpc/processor.h.~1~ 2008-06-22 18:08:17.000000000 +0200
++++ linux-2.6.16.perfctr26/include/asm-powerpc/processor.h 2008-06-22 18:11:15.000000000 +0200
@@ -193,6 +193,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
@@ -333,8 +356,8 @@
};
#define ARCH_MIN_TASKALIGN 16
---- linux-2.6.16.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2006-03-20 10:40:11.000000000 +0100
-+++ linux-2.6.16.perfctr26/include/asm-x86_64/hw_irq.h 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2008-06-22 17:55:16.000000000 +0200
++++ linux-2.6.16.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 18:11:15.000000000 +0200
@@ -67,14 +67,15 @@ struct hw_interrupt_type;
* sources per level' errata.
*/
@@ -353,8 +376,8 @@
#ifndef __ASSEMBLY__
---- linux-2.6.16.perfctr26/include/asm-x86_64/irq.h.~1~ 2006-03-20 10:40:11.000000000 +0100
-+++ linux-2.6.16.perfctr26/include/asm-x86_64/irq.h 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/include/asm-x86_64/irq.h.~1~ 2008-06-22 17:35:10.000000000 +0200
++++ linux-2.6.16.perfctr26/include/asm-x86_64/irq.h 2008-06-22 18:11:15.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -364,8 +387,8 @@
#ifdef CONFIG_PCI_MSI
#define NR_IRQS FIRST_SYSTEM_VECTOR
---- linux-2.6.16.perfctr26/include/asm-x86_64/processor.h.~1~ 2006-03-20 10:40:11.000000000 +0100
-+++ linux-2.6.16.perfctr26/include/asm-x86_64/processor.h 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/include/asm-x86_64/processor.h.~1~ 2008-06-22 18:08:17.000000000 +0200
++++ linux-2.6.16.perfctr26/include/asm-x86_64/processor.h 2008-06-22 18:11:15.000000000 +0200
@@ -260,6 +260,8 @@ struct thread_struct {
unsigned io_bitmap_max;
/* cached TLS descriptors. */
@@ -375,8 +398,8 @@
} __attribute__((aligned(16)));
#define INIT_THREAD { \
---- linux-2.6.16.perfctr26/include/asm-x86_64/system.h.~1~ 2006-03-20 10:40:11.000000000 +0100
-+++ linux-2.6.16.perfctr26/include/asm-x86_64/system.h 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/include/asm-x86_64/system.h.~1~ 2008-06-22 18:08:17.000000000 +0200
++++ linux-2.6.16.perfctr26/include/asm-x86_64/system.h 2008-06-22 18:11:15.000000000 +0200
@@ -26,7 +26,8 @@
#define __EXTRA_CLOBBER \
,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
@@ -397,8 +420,8 @@
extern void load_gs_index(unsigned);
---- linux-2.6.16.perfctr26/kernel/exit.c.~1~ 2006-03-20 10:40:12.000000000 +0100
-+++ linux-2.6.16.perfctr26/kernel/exit.c 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/kernel/exit.c.~1~ 2008-06-22 18:08:17.000000000 +0200
++++ linux-2.6.16.perfctr26/kernel/exit.c 2008-06-22 18:11:15.000000000 +0200
@@ -26,6 +26,7 @@
#include <linux/mount.h>
#include <linux/proc_fs.h>
@@ -415,8 +438,8 @@
sched_exit(p);
write_unlock_irq(&tasklist_lock);
spin_unlock(&p->proc_lock);
---- linux-2.6.16.perfctr26/kernel/sched.c.~1~ 2006-03-20 10:40:12.000000000 +0100
-+++ linux-2.6.16.perfctr26/kernel/sched.c 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/kernel/sched.c.~1~ 2008-06-22 18:08:17.000000000 +0200
++++ linux-2.6.16.perfctr26/kernel/sched.c 2008-06-22 18:11:15.000000000 +0200
@@ -44,6 +44,7 @@
#include <linux/cpu.h>
#include <linux/cpuset.h>
@@ -434,8 +457,8 @@
rq = task_rq_lock(p, &flags);
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
---- linux-2.6.16.perfctr26/kernel/timer.c.~1~ 2006-03-20 10:40:12.000000000 +0100
-+++ linux-2.6.16.perfctr26/kernel/timer.c 2006-03-20 10:51:04.000000000 +0100
+--- linux-2.6.16.perfctr26/kernel/timer.c.~1~ 2008-06-22 18:08:17.000000000 +0200
++++ linux-2.6.16.perfctr26/kernel/timer.c 2008-06-22 18:11:15.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/jiffies.h>
#include <linux/posix-timers.h>
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.16.46-0.12-suse b/src/perfctr-2.6.x/patches/patch-kernel-2.6.16.46-0.12-suse
index 462eb11bccc867f8b04911d2a3c2226ef22ed1e0..761a0700f31a8d36a94a55560dd5ca5547c3981a 100644
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.16.46-0.12-suse
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.16.46-0.12-suse
@@ -1,5 +1,5 @@
--- linux-2.6.16.46-0.12.perfctr26/CREDITS.~1~ 2006-03-20 06:53:29.000000000 +0100
-+++ linux-2.6.16.46-0.12.perfctr26/CREDITS 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/CREDITS 2008-06-23 00:44:21.000000000 +0200
@@ -2631,9 +2631,10 @@ S: Ottawa, Ontario
S: Canada K2P 0X8
@@ -14,7 +14,7 @@
N: Reed H. Petty
E: rhp@draper.net
--- linux-2.6.16.46-0.12.perfctr26/Documentation/ioctl-number.txt.~1~ 2006-03-20 06:53:29.000000000 +0100
-+++ linux-2.6.16.46-0.12.perfctr26/Documentation/ioctl-number.txt 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/Documentation/ioctl-number.txt 2008-06-23 00:44:21.000000000 +0200
@@ -188,6 +188,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -25,7 +25,7 @@
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
--- linux-2.6.16.46-0.12.perfctr26/MAINTAINERS.~1~ 2007-05-18 13:16:27.000000000 +0200
-+++ linux-2.6.16.46-0.12.perfctr26/MAINTAINERS 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/MAINTAINERS 2008-06-23 00:44:21.000000000 +0200
@@ -2096,6 +2096,12 @@ M: tsbogend@alpha.franken.de
L: netdev@vger.kernel.org
S: Maintained
@@ -40,7 +40,7 @@
P: J�rn Engel
M: joern@wh.fh-wedel.de
--- linux-2.6.16.46-0.12.perfctr26/arch/i386/Kconfig.~1~ 2007-05-18 13:16:33.000000000 +0200
-+++ linux-2.6.16.46-0.12.perfctr26/arch/i386/Kconfig 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/arch/i386/Kconfig 2008-06-23 00:44:21.000000000 +0200
@@ -739,6 +739,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -51,7 +51,7 @@
config KEXEC
--- linux-2.6.16.46-0.12.perfctr26/arch/i386/kernel/entry.S.~1~ 2007-05-18 13:16:32.000000000 +0200
-+++ linux-2.6.16.46-0.12.perfctr26/arch/i386/kernel/entry.S 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/arch/i386/kernel/entry.S 2008-06-23 00:44:21.000000000 +0200
@@ -446,6 +446,16 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -70,7 +70,7 @@
pushl $0 # no error code
pushl $do_divide_error
--- linux-2.6.16.46-0.12.perfctr26/arch/i386/kernel/i8259.c.~1~ 2007-05-18 13:16:13.000000000 +0200
-+++ linux-2.6.16.46-0.12.perfctr26/arch/i386/kernel/i8259.c 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/arch/i386/kernel/i8259.c 2008-06-23 00:44:21.000000000 +0200
@@ -23,6 +23,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -89,7 +89,7 @@
* Set the clock to HZ Hz, we already have a valid
* vector now:
--- linux-2.6.16.46-0.12.perfctr26/arch/i386/kernel/process.c.~1~ 2007-05-18 13:16:28.000000000 +0200
-+++ linux-2.6.16.46-0.12.perfctr26/arch/i386/kernel/process.c 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/arch/i386/kernel/process.c 2008-06-23 00:44:21.000000000 +0200
@@ -33,6 +33,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -125,7 +125,7 @@
}
--- linux-2.6.16.46-0.12.perfctr26/arch/powerpc/Kconfig.~1~ 2007-05-18 13:16:29.000000000 +0200
-+++ linux-2.6.16.46-0.12.perfctr26/arch/powerpc/Kconfig 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/arch/powerpc/Kconfig 2008-06-23 00:44:21.000000000 +0200
@@ -287,6 +287,11 @@ config NOT_COHERENT_CACHE
bool
depends on 4xx || 8xx || E200
@@ -139,7 +139,7 @@
source "init/Kconfig"
--- linux-2.6.16.46-0.12.perfctr26/arch/powerpc/kernel/process.c.~1~ 2007-05-18 13:16:31.000000000 +0200
-+++ linux-2.6.16.46-0.12.perfctr26/arch/powerpc/kernel/process.c 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/arch/powerpc/kernel/process.c 2008-06-23 00:44:21.000000000 +0200
@@ -34,6 +34,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -181,7 +181,7 @@
}
--- linux-2.6.16.46-0.12.perfctr26/arch/x86_64/Kconfig.~1~ 2007-05-18 13:16:32.000000000 +0200
-+++ linux-2.6.16.46-0.12.perfctr26/arch/x86_64/Kconfig 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/arch/x86_64/Kconfig 2008-06-23 00:44:21.000000000 +0200
@@ -532,6 +532,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -192,7 +192,7 @@
endmenu
--- linux-2.6.16.46-0.12.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2007-05-18 13:16:31.000000000 +0200
-+++ linux-2.6.16.46-0.12.perfctr26/arch/x86_64/kernel/entry.S 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/arch/x86_64/kernel/entry.S 2008-06-23 00:44:21.000000000 +0200
@@ -646,6 +646,11 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
#endif
@@ -206,7 +206,7 @@
* Exception entry points.
*/
--- linux-2.6.16.46-0.12.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2007-05-18 13:16:31.000000000 +0200
-+++ linux-2.6.16.46-0.12.perfctr26/arch/x86_64/kernel/i8259.c 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-23 00:44:21.000000000 +0200
@@ -23,6 +23,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -225,7 +225,7 @@
* Set the clock to HZ Hz, we already have a valid
* vector now:
--- linux-2.6.16.46-0.12.perfctr26/arch/x86_64/kernel/process.c.~1~ 2007-05-18 13:16:28.000000000 +0200
-+++ linux-2.6.16.46-0.12.perfctr26/arch/x86_64/kernel/process.c 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/arch/x86_64/kernel/process.c 2008-06-23 00:44:21.000000000 +0200
@@ -33,6 +33,7 @@
#include <linux/interrupt.h>
#include <linux/delay.h>
@@ -261,7 +261,7 @@
}
--- linux-2.6.16.46-0.12.perfctr26/drivers/Makefile.~1~ 2007-05-18 13:16:32.000000000 +0200
-+++ linux-2.6.16.46-0.12.perfctr26/drivers/Makefile 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/drivers/Makefile 2008-06-23 00:44:21.000000000 +0200
@@ -72,6 +72,7 @@ obj-$(CONFIG_CPU_FREQ) += cpufreq/
obj-$(CONFIG_MMC) += mmc/
obj-$(CONFIG_INFINIBAND) += infiniband/
@@ -270,8 +270,26 @@
obj-y += firmware/
obj-$(CONFIG_CRYPTO) += crypto/
obj-$(CONFIG_SUPERH) += sh/
+--- linux-2.6.16.46-0.12.perfctr26/fs/exec.c.~1~ 2007-05-18 13:16:31.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/fs/exec.c 2008-06-23 00:44:28.000000000 +0200
+@@ -51,6 +51,7 @@
+ #include <linux/cn_proc.h>
+ #include <linux/pagg.h>
+ #include <linux/audit.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -894,6 +895,7 @@ int flush_old_exec(struct linux_binprm *
+ set_task_comm(current, tcomm);
+
+ current->flags &= ~PF_RANDOMIZE;
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ /* Set the new mm task size. We have to do that late because it may
--- linux-2.6.16.46-0.12.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2007-05-18 13:16:25.000000000 +0200
-+++ linux-2.6.16.46-0.12.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-23 00:44:21.000000000 +0200
@@ -59,14 +59,15 @@
* sources per level' errata.
*/
@@ -291,7 +309,7 @@
#define TIMER_IRQ 0
--- linux-2.6.16.46-0.12.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2006-03-20 06:53:29.000000000 +0100
-+++ linux-2.6.16.46-0.12.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-23 00:44:21.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -311,7 +329,7 @@
#define TIMER_IRQ 0
--- linux-2.6.16.46-0.12.perfctr26/include/asm-i386/processor.h.~1~ 2007-05-18 13:16:27.000000000 +0200
-+++ linux-2.6.16.46-0.12.perfctr26/include/asm-i386/processor.h 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/include/asm-i386/processor.h 2008-06-23 00:44:21.000000000 +0200
@@ -470,6 +470,8 @@ struct thread_struct {
unsigned long iopl;
/* max allowed port in the bitmap, in bytes: */
@@ -322,7 +340,7 @@
#define INIT_THREAD { \
--- linux-2.6.16.46-0.12.perfctr26/include/asm-i386/system.h.~1~ 2007-05-18 13:16:32.000000000 +0200
-+++ linux-2.6.16.46-0.12.perfctr26/include/asm-i386/system.h 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/include/asm-i386/system.h 2008-06-23 00:44:21.000000000 +0200
@@ -18,6 +18,7 @@ extern struct task_struct * FASTCALL(__s
*/
#define switch_to(prev,next,last) do { \
@@ -332,7 +350,7 @@
"pushl %%ebp\n\t" \
"movl %%esp,%0\n\t" /* save ESP */ \
--- linux-2.6.16.46-0.12.perfctr26/include/asm-powerpc/processor.h.~1~ 2007-05-18 13:16:27.000000000 +0200
-+++ linux-2.6.16.46-0.12.perfctr26/include/asm-powerpc/processor.h 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/include/asm-powerpc/processor.h 2008-06-23 00:44:21.000000000 +0200
@@ -197,6 +197,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
@@ -344,7 +362,7 @@
#define ARCH_MIN_TASKALIGN 16
--- linux-2.6.16.46-0.12.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2007-05-18 13:16:31.000000000 +0200
-+++ linux-2.6.16.46-0.12.perfctr26/include/asm-x86_64/hw_irq.h 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-23 00:44:21.000000000 +0200
@@ -71,14 +71,15 @@ struct hw_interrupt_type;
* sources per level' errata.
*/
@@ -364,7 +382,7 @@
#ifndef __ASSEMBLY__
--- linux-2.6.16.46-0.12.perfctr26/include/asm-x86_64/irq.h.~1~ 2006-03-20 06:53:29.000000000 +0100
-+++ linux-2.6.16.46-0.12.perfctr26/include/asm-x86_64/irq.h 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/include/asm-x86_64/irq.h 2008-06-23 00:44:21.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -375,7 +393,7 @@
#ifdef CONFIG_PCI_MSI
#define NR_IRQS FIRST_SYSTEM_VECTOR
--- linux-2.6.16.46-0.12.perfctr26/include/asm-x86_64/processor.h.~1~ 2007-05-18 13:16:27.000000000 +0200
-+++ linux-2.6.16.46-0.12.perfctr26/include/asm-x86_64/processor.h 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/include/asm-x86_64/processor.h 2008-06-23 00:44:21.000000000 +0200
@@ -273,6 +273,8 @@ struct thread_struct {
unsigned io_bitmap_max;
/* cached TLS descriptors. */
@@ -386,7 +404,7 @@
#define INIT_THREAD { \
--- linux-2.6.16.46-0.12.perfctr26/include/asm-x86_64/system.h.~1~ 2007-05-18 13:16:11.000000000 +0200
-+++ linux-2.6.16.46-0.12.perfctr26/include/asm-x86_64/system.h 2008-05-29 23:14:21.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/include/asm-x86_64/system.h 2008-06-23 00:44:21.000000000 +0200
@@ -27,7 +27,8 @@
,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
@@ -408,7 +426,7 @@
extern void load_gs_index(unsigned);
--- linux-2.6.16.46-0.12.perfctr26/include/linux/config.h.~1~ 2006-03-20 06:53:29.000000000 +0100
-+++ linux-2.6.16.46-0.12.perfctr26/include/linux/config.h 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/include/linux/config.h 2008-06-23 00:44:21.000000000 +0200
@@ -3,6 +3,10 @@
/* This file is no longer in use and kept only for backward compatibility.
* autoconf.h is now included via -imacros on the commandline
@@ -421,7 +439,7 @@
#endif
--- linux-2.6.16.46-0.12.perfctr26/kernel/exit.c.~1~ 2007-05-18 13:16:31.000000000 +0200
-+++ linux-2.6.16.46-0.12.perfctr26/kernel/exit.c 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/kernel/exit.c 2008-06-23 00:44:21.000000000 +0200
@@ -30,6 +30,7 @@
#include <linux/mount.h>
#include <linux/proc_fs.h>
@@ -439,7 +457,7 @@
write_unlock_irq(&tasklist_lock);
spin_unlock(&p->proc_lock);
--- linux-2.6.16.46-0.12.perfctr26/kernel/sched.c.~1~ 2007-05-18 13:16:31.000000000 +0200
-+++ linux-2.6.16.46-0.12.perfctr26/kernel/sched.c 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/kernel/sched.c 2008-06-23 00:44:21.000000000 +0200
@@ -44,6 +44,7 @@
#include <linux/cpu.h>
#include <linux/cpuset.h>
@@ -458,7 +476,7 @@
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
--- linux-2.6.16.46-0.12.perfctr26/kernel/timer.c.~1~ 2007-05-18 13:16:32.000000000 +0200
-+++ linux-2.6.16.46-0.12.perfctr26/kernel/timer.c 2008-05-29 23:14:17.000000000 +0200
++++ linux-2.6.16.46-0.12.perfctr26/kernel/timer.c 2008-06-23 00:44:21.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/jiffies.h>
#include <linux/posix-timers.h>
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.17 b/src/perfctr-2.6.x/patches/patch-kernel-2.6.17
index 6d546444241136a019a8998fca4e43ca0e509d6c..5cfe3277b6afc498e3fa8ab97893443a3dc701e8 100644
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.17
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.17
@@ -1,15 +1,20 @@
---- linux-2.6.17.perfctr26/CREDITS.~1~ 2006-06-18 12:13:01.000000000 +0200
-+++ linux-2.6.17.perfctr26/CREDITS 2006-06-18 12:30:44.000000000 +0200
-@@ -2631,6 +2631,7 @@ N: Mikael Pettersson
- E: mikpe@csd.uu.se
- W: http://www.csd.uu.se/~mikpe/
+--- linux-2.6.17.perfctr26/CREDITS.~1~ 2008-06-22 17:55:14.000000000 +0200
++++ linux-2.6.17.perfctr26/CREDITS 2008-06-22 17:57:58.000000000 +0200
+@@ -2628,9 +2628,10 @@ S: Ottawa, Ontario
+ S: Canada K2P 0X8
+
+ N: Mikael Pettersson
+-E: mikpe@csd.uu.se
+-W: http://www.csd.uu.se/~mikpe/
++E: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/
D: Miscellaneous fixes
+D: Performance-monitoring counters driver
N: Reed H. Petty
E: rhp@draper.net
---- linux-2.6.17.perfctr26/Documentation/ioctl-number.txt.~1~ 2006-06-18 12:13:01.000000000 +0200
-+++ linux-2.6.17.perfctr26/Documentation/ioctl-number.txt 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/Documentation/ioctl-number.txt.~1~ 2008-06-22 17:55:14.000000000 +0200
++++ linux-2.6.17.perfctr26/Documentation/ioctl-number.txt 2008-06-22 17:57:52.000000000 +0200
@@ -186,6 +186,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -19,23 +24,23 @@
0xDD 00-3F ZFCP device driver see drivers/s390/scsi/
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
---- linux-2.6.17.perfctr26/MAINTAINERS.~1~ 2006-06-18 12:13:01.000000000 +0200
-+++ linux-2.6.17.perfctr26/MAINTAINERS 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/MAINTAINERS.~1~ 2008-06-22 17:55:14.000000000 +0200
++++ linux-2.6.17.perfctr26/MAINTAINERS 2008-06-22 17:57:58.000000000 +0200
@@ -2185,6 +2185,12 @@ M: tsbogend@alpha.franken.de
L: netdev@vger.kernel.org
S: Maintained
+PERFORMANCE-MONITORING COUNTERS DRIVER
+P: Mikael Pettersson
-+M: mikpe@csd.uu.se
-+W: http://www.csd.uu.se/~mikpe/linux/perfctr/
++M: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
+S: Maintained
+
PERSONALITY HANDLING
P: Christoph Hellwig
M: hch@infradead.org
---- linux-2.6.17.perfctr26/arch/i386/Kconfig.~1~ 2006-06-18 12:13:01.000000000 +0200
-+++ linux-2.6.17.perfctr26/arch/i386/Kconfig 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/arch/i386/Kconfig.~1~ 2008-06-22 17:55:14.000000000 +0200
++++ linux-2.6.17.perfctr26/arch/i386/Kconfig 2008-06-22 17:57:52.000000000 +0200
@@ -708,6 +708,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -45,8 +50,8 @@
source kernel/Kconfig.hz
config KEXEC
---- linux-2.6.17.perfctr26/arch/i386/kernel/entry.S.~1~ 2006-06-18 12:13:01.000000000 +0200
-+++ linux-2.6.17.perfctr26/arch/i386/kernel/entry.S 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/arch/i386/kernel/entry.S.~1~ 2008-06-22 17:55:14.000000000 +0200
++++ linux-2.6.17.perfctr26/arch/i386/kernel/entry.S 2008-06-22 17:57:52.000000000 +0200
@@ -436,6 +436,16 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -64,8 +69,8 @@
ENTRY(divide_error)
pushl $0 # no error code
pushl $do_divide_error
---- linux-2.6.17.perfctr26/arch/i386/kernel/i8259.c.~1~ 2005-10-28 11:24:06.000000000 +0200
-+++ linux-2.6.17.perfctr26/arch/i386/kernel/i8259.c 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/arch/i386/kernel/i8259.c.~1~ 2008-06-22 17:55:14.000000000 +0200
++++ linux-2.6.17.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 17:57:52.000000000 +0200
@@ -23,6 +23,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -83,8 +88,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.17.perfctr26/arch/i386/kernel/process.c.~1~ 2006-06-18 12:13:01.000000000 +0200
-+++ linux-2.6.17.perfctr26/arch/i386/kernel/process.c 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/arch/i386/kernel/process.c.~1~ 2008-06-22 17:55:14.000000000 +0200
++++ linux-2.6.17.perfctr26/arch/i386/kernel/process.c 2008-06-22 17:57:52.000000000 +0200
@@ -33,6 +33,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -119,8 +124,8 @@
return prev_p;
}
---- linux-2.6.17.perfctr26/arch/powerpc/Kconfig.~1~ 2006-06-18 12:13:01.000000000 +0200
-+++ linux-2.6.17.perfctr26/arch/powerpc/Kconfig 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/arch/powerpc/Kconfig.~1~ 2008-06-22 17:55:14.000000000 +0200
++++ linux-2.6.17.perfctr26/arch/powerpc/Kconfig 2008-06-22 17:57:52.000000000 +0200
@@ -299,6 +299,11 @@ config NOT_COHERENT_CACHE
bool
depends on 4xx || 8xx || E200
@@ -133,8 +138,8 @@
endmenu
source "init/Kconfig"
---- linux-2.6.17.perfctr26/arch/powerpc/kernel/process.c.~1~ 2006-06-18 12:13:01.000000000 +0200
-+++ linux-2.6.17.perfctr26/arch/powerpc/kernel/process.c 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/arch/powerpc/kernel/process.c.~1~ 2008-06-22 17:55:14.000000000 +0200
++++ linux-2.6.17.perfctr26/arch/powerpc/kernel/process.c 2008-06-22 17:57:52.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -170,8 +175,8 @@
return 0;
}
---- linux-2.6.17.perfctr26/arch/x86_64/Kconfig.~1~ 2006-06-18 12:13:02.000000000 +0200
-+++ linux-2.6.17.perfctr26/arch/x86_64/Kconfig 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/arch/x86_64/Kconfig.~1~ 2008-06-22 17:55:14.000000000 +0200
++++ linux-2.6.17.perfctr26/arch/x86_64/Kconfig 2008-06-22 17:57:52.000000000 +0200
@@ -491,6 +491,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -181,8 +186,8 @@
source kernel/Kconfig.hz
config REORDER
---- linux-2.6.17.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2006-06-18 12:13:02.000000000 +0200
-+++ linux-2.6.17.perfctr26/arch/x86_64/kernel/entry.S 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2008-06-22 17:55:14.000000000 +0200
++++ linux-2.6.17.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 17:57:52.000000000 +0200
@@ -642,6 +642,11 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
#endif
@@ -195,8 +200,8 @@
/*
* Exception entry points.
*/
---- linux-2.6.17.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2006-03-20 10:40:03.000000000 +0100
-+++ linux-2.6.17.perfctr26/arch/x86_64/kernel/i8259.c 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2008-06-22 17:55:14.000000000 +0200
++++ linux-2.6.17.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 17:57:52.000000000 +0200
@@ -23,6 +23,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -214,8 +219,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.17.perfctr26/arch/x86_64/kernel/process.c.~1~ 2006-06-18 12:13:02.000000000 +0200
-+++ linux-2.6.17.perfctr26/arch/x86_64/kernel/process.c 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/arch/x86_64/kernel/process.c.~1~ 2008-06-22 17:55:14.000000000 +0200
++++ linux-2.6.17.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 17:57:52.000000000 +0200
@@ -33,6 +33,7 @@
#include <linux/interrupt.h>
#include <linux/delay.h>
@@ -250,8 +255,8 @@
return prev_p;
}
---- linux-2.6.17.perfctr26/drivers/Makefile.~1~ 2006-06-18 12:13:02.000000000 +0200
-+++ linux-2.6.17.perfctr26/drivers/Makefile 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/drivers/Makefile.~1~ 2008-06-22 17:55:14.000000000 +0200
++++ linux-2.6.17.perfctr26/drivers/Makefile 2008-06-22 17:57:52.000000000 +0200
@@ -71,6 +71,7 @@ obj-$(CONFIG_NEW_LEDS) += leds/
obj-$(CONFIG_INFINIBAND) += infiniband/
obj-$(CONFIG_IPATH_CORE) += infiniband/
@@ -260,8 +265,26 @@
obj-y += firmware/
obj-$(CONFIG_CRYPTO) += crypto/
obj-$(CONFIG_SUPERH) += sh/
---- linux-2.6.17.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2004-05-10 11:14:37.000000000 +0200
-+++ linux-2.6.17.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/fs/exec.c.~1~ 2008-06-22 17:55:15.000000000 +0200
++++ linux-2.6.17.perfctr26/fs/exec.c 2008-06-22 17:57:58.000000000 +0200
+@@ -49,6 +49,7 @@
+ #include <linux/rmap.h>
+ #include <linux/acct.h>
+ #include <linux/cn_proc.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -889,6 +890,7 @@ int flush_old_exec(struct linux_binprm *
+ set_task_comm(current, tcomm);
+
+ current->flags &= ~PF_RANDOMIZE;
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ /* Set the new mm task size. We have to do that late because it may
+--- linux-2.6.17.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.17.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 17:57:52.000000000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -280,8 +303,8 @@
#define TIMER_IRQ 0
---- linux-2.6.17.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2004-01-09 13:19:11.000000000 +0100
-+++ linux-2.6.17.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.17.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 17:57:52.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -300,8 +323,8 @@
#define TIMER_IRQ 0
---- linux-2.6.17.perfctr26/include/asm-i386/processor.h.~1~ 2006-06-18 12:13:11.000000000 +0200
-+++ linux-2.6.17.perfctr26/include/asm-i386/processor.h 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/include/asm-i386/processor.h.~1~ 2008-06-22 17:55:16.000000000 +0200
++++ linux-2.6.17.perfctr26/include/asm-i386/processor.h 2008-06-22 17:57:52.000000000 +0200
@@ -469,6 +469,8 @@ struct thread_struct {
unsigned long iopl;
/* max allowed port in the bitmap, in bytes: */
@@ -311,8 +334,8 @@
};
#define INIT_THREAD { \
---- linux-2.6.17.perfctr26/include/asm-i386/system.h.~1~ 2006-06-18 12:13:11.000000000 +0200
-+++ linux-2.6.17.perfctr26/include/asm-i386/system.h 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/include/asm-i386/system.h.~1~ 2008-06-22 17:55:16.000000000 +0200
++++ linux-2.6.17.perfctr26/include/asm-i386/system.h 2008-06-22 17:57:52.000000000 +0200
@@ -14,6 +14,7 @@ extern struct task_struct * FASTCALL(__s
#define switch_to(prev,next,last) do { \
@@ -321,8 +344,8 @@
asm volatile("pushl %%ebp\n\t" \
"movl %%esp,%0\n\t" /* save ESP */ \
"movl %5,%%esp\n\t" /* restore ESP */ \
---- linux-2.6.17.perfctr26/include/asm-powerpc/processor.h.~1~ 2006-06-18 12:13:11.000000000 +0200
-+++ linux-2.6.17.perfctr26/include/asm-powerpc/processor.h 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/include/asm-powerpc/processor.h.~1~ 2008-06-22 17:55:16.000000000 +0200
++++ linux-2.6.17.perfctr26/include/asm-powerpc/processor.h 2008-06-22 17:57:52.000000000 +0200
@@ -169,6 +169,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
@@ -333,8 +356,8 @@
};
#define ARCH_MIN_TASKALIGN 16
---- linux-2.6.17.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2006-03-20 10:40:11.000000000 +0100
-+++ linux-2.6.17.perfctr26/include/asm-x86_64/hw_irq.h 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2008-06-22 17:55:16.000000000 +0200
++++ linux-2.6.17.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 17:57:52.000000000 +0200
@@ -67,14 +67,15 @@ struct hw_interrupt_type;
* sources per level' errata.
*/
@@ -353,8 +376,8 @@
#ifndef __ASSEMBLY__
---- linux-2.6.17.perfctr26/include/asm-x86_64/irq.h.~1~ 2006-03-20 10:40:11.000000000 +0100
-+++ linux-2.6.17.perfctr26/include/asm-x86_64/irq.h 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/include/asm-x86_64/irq.h.~1~ 2008-06-22 17:35:10.000000000 +0200
++++ linux-2.6.17.perfctr26/include/asm-x86_64/irq.h 2008-06-22 17:57:52.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -364,8 +387,8 @@
#ifdef CONFIG_PCI_MSI
#define NR_IRQS FIRST_SYSTEM_VECTOR
---- linux-2.6.17.perfctr26/include/asm-x86_64/processor.h.~1~ 2006-06-18 12:13:11.000000000 +0200
-+++ linux-2.6.17.perfctr26/include/asm-x86_64/processor.h 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/include/asm-x86_64/processor.h.~1~ 2008-06-22 17:55:16.000000000 +0200
++++ linux-2.6.17.perfctr26/include/asm-x86_64/processor.h 2008-06-22 17:57:52.000000000 +0200
@@ -264,6 +264,8 @@ struct thread_struct {
unsigned io_bitmap_max;
/* cached TLS descriptors. */
@@ -375,8 +398,8 @@
} __attribute__((aligned(16)));
#define INIT_THREAD { \
---- linux-2.6.17.perfctr26/include/asm-x86_64/system.h.~1~ 2006-06-18 12:13:11.000000000 +0200
-+++ linux-2.6.17.perfctr26/include/asm-x86_64/system.h 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/include/asm-x86_64/system.h.~1~ 2008-06-22 17:55:16.000000000 +0200
++++ linux-2.6.17.perfctr26/include/asm-x86_64/system.h 2008-06-22 17:57:52.000000000 +0200
@@ -26,7 +26,8 @@
#define __EXTRA_CLOBBER \
,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
@@ -397,8 +420,8 @@
extern void load_gs_index(unsigned);
---- linux-2.6.17.perfctr26/kernel/exit.c.~1~ 2006-06-18 12:13:11.000000000 +0200
-+++ linux-2.6.17.perfctr26/kernel/exit.c 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/kernel/exit.c.~1~ 2008-06-22 17:55:16.000000000 +0200
++++ linux-2.6.17.perfctr26/kernel/exit.c 2008-06-22 17:57:52.000000000 +0200
@@ -26,6 +26,7 @@
#include <linux/mount.h>
#include <linux/proc_fs.h>
@@ -415,8 +438,8 @@
sched_exit(p);
write_unlock_irq(&tasklist_lock);
spin_unlock(&p->proc_lock);
---- linux-2.6.17.perfctr26/kernel/sched.c.~1~ 2006-06-18 12:13:11.000000000 +0200
-+++ linux-2.6.17.perfctr26/kernel/sched.c 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/kernel/sched.c.~1~ 2008-06-22 17:55:16.000000000 +0200
++++ linux-2.6.17.perfctr26/kernel/sched.c 2008-06-22 17:57:52.000000000 +0200
@@ -44,6 +44,7 @@
#include <linux/cpu.h>
#include <linux/cpuset.h>
@@ -434,8 +457,8 @@
rq = task_rq_lock(p, &flags);
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
---- linux-2.6.17.perfctr26/kernel/timer.c.~1~ 2006-06-18 12:13:11.000000000 +0200
-+++ linux-2.6.17.perfctr26/kernel/timer.c 2006-06-18 12:30:44.000000000 +0200
+--- linux-2.6.17.perfctr26/kernel/timer.c.~1~ 2008-06-22 17:55:16.000000000 +0200
++++ linux-2.6.17.perfctr26/kernel/timer.c 2008-06-22 17:57:52.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/jiffies.h>
#include <linux/posix-timers.h>
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.18 b/src/perfctr-2.6.x/patches/patch-kernel-2.6.18
index 685fdc2d39562ea7f76fe961fc03c4eac039ee87..251fae532e98b82cee8722882fc60494e481b89b 100644
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.18
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.18
@@ -1,15 +1,20 @@
---- linux-2.6.18.perfctr26/CREDITS.~1~ 2006-09-20 19:28:35.000000000 +0200
-+++ linux-2.6.18.perfctr26/CREDITS 2006-09-20 19:57:36.000000000 +0200
-@@ -2632,6 +2632,7 @@ N: Mikael Pettersson
- E: mikpe@csd.uu.se
- W: http://www.csd.uu.se/~mikpe/
+--- linux-2.6.18.perfctr26/CREDITS.~1~ 2008-06-22 17:35:05.000000000 +0200
++++ linux-2.6.18.perfctr26/CREDITS 2008-06-22 17:37:20.000000000 +0200
+@@ -2629,9 +2629,10 @@ S: Ottawa, Ontario
+ S: Canada K2P 0X8
+
+ N: Mikael Pettersson
+-E: mikpe@csd.uu.se
+-W: http://www.csd.uu.se/~mikpe/
++E: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/
D: Miscellaneous fixes
+D: Performance-monitoring counters driver
N: Reed H. Petty
E: rhp@draper.net
---- linux-2.6.18.perfctr26/Documentation/ioctl-number.txt.~1~ 2006-09-20 19:28:35.000000000 +0200
-+++ linux-2.6.18.perfctr26/Documentation/ioctl-number.txt 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/Documentation/ioctl-number.txt.~1~ 2008-06-22 17:20:35.000000000 +0200
++++ linux-2.6.18.perfctr26/Documentation/ioctl-number.txt 2008-06-22 17:37:14.000000000 +0200
@@ -187,6 +187,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -19,23 +24,23 @@
0xDD 00-3F ZFCP device driver see drivers/s390/scsi/
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
---- linux-2.6.18.perfctr26/MAINTAINERS.~1~ 2006-09-20 19:28:35.000000000 +0200
-+++ linux-2.6.18.perfctr26/MAINTAINERS 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/MAINTAINERS.~1~ 2008-06-22 17:35:05.000000000 +0200
++++ linux-2.6.18.perfctr26/MAINTAINERS 2008-06-22 17:37:20.000000000 +0200
@@ -2272,6 +2272,12 @@ M: nagar@watson.ibm.com
L: linux-kernel@vger.kernel.org
S: Maintained
+PERFORMANCE-MONITORING COUNTERS DRIVER
+P: Mikael Pettersson
-+M: mikpe@csd.uu.se
-+W: http://www.csd.uu.se/~mikpe/linux/perfctr/
++M: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
+S: Maintained
+
PERSONALITY HANDLING
P: Christoph Hellwig
M: hch@infradead.org
---- linux-2.6.18.perfctr26/arch/i386/Kconfig.~1~ 2006-09-20 19:28:37.000000000 +0200
-+++ linux-2.6.18.perfctr26/arch/i386/Kconfig 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/arch/i386/Kconfig.~1~ 2008-06-22 17:35:05.000000000 +0200
++++ linux-2.6.18.perfctr26/arch/i386/Kconfig 2008-06-22 17:37:14.000000000 +0200
@@ -737,6 +737,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -45,8 +50,8 @@
source kernel/Kconfig.hz
config KEXEC
---- linux-2.6.18.perfctr26/arch/i386/kernel/entry.S.~1~ 2006-09-20 19:28:37.000000000 +0200
-+++ linux-2.6.18.perfctr26/arch/i386/kernel/entry.S 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/arch/i386/kernel/entry.S.~1~ 2008-06-22 17:35:05.000000000 +0200
++++ linux-2.6.18.perfctr26/arch/i386/kernel/entry.S 2008-06-22 17:37:14.000000000 +0200
@@ -591,6 +591,22 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -70,8 +75,8 @@
ENTRY(divide_error)
RING0_INT_FRAME
pushl $0 # no error code
---- linux-2.6.18.perfctr26/arch/i386/kernel/i8259.c.~1~ 2006-09-20 19:28:37.000000000 +0200
-+++ linux-2.6.18.perfctr26/arch/i386/kernel/i8259.c 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/arch/i386/kernel/i8259.c.~1~ 2008-06-22 17:35:05.000000000 +0200
++++ linux-2.6.18.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 17:37:14.000000000 +0200
@@ -22,6 +22,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -89,8 +94,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.18.perfctr26/arch/i386/kernel/process.c.~1~ 2006-09-20 19:28:37.000000000 +0200
-+++ linux-2.6.18.perfctr26/arch/i386/kernel/process.c 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/arch/i386/kernel/process.c.~1~ 2008-06-22 17:35:05.000000000 +0200
++++ linux-2.6.18.perfctr26/arch/i386/kernel/process.c 2008-06-22 17:37:14.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -125,8 +130,8 @@
return prev_p;
}
---- linux-2.6.18.perfctr26/arch/powerpc/Kconfig.~1~ 2006-09-20 19:28:42.000000000 +0200
-+++ linux-2.6.18.perfctr26/arch/powerpc/Kconfig 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/arch/powerpc/Kconfig.~1~ 2008-06-22 17:35:06.000000000 +0200
++++ linux-2.6.18.perfctr26/arch/powerpc/Kconfig 2008-06-22 17:37:14.000000000 +0200
@@ -320,6 +320,11 @@ config NOT_COHERENT_CACHE
bool
depends on 4xx || 8xx || E200
@@ -139,8 +144,8 @@
endmenu
source "init/Kconfig"
---- linux-2.6.18.perfctr26/arch/powerpc/kernel/process.c.~1~ 2006-09-20 19:28:42.000000000 +0200
-+++ linux-2.6.18.perfctr26/arch/powerpc/kernel/process.c 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/arch/powerpc/kernel/process.c.~1~ 2008-06-22 17:35:06.000000000 +0200
++++ linux-2.6.18.perfctr26/arch/powerpc/kernel/process.c 2008-06-22 17:37:14.000000000 +0200
@@ -31,6 +31,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -176,8 +181,8 @@
return 0;
}
---- linux-2.6.18.perfctr26/arch/x86_64/Kconfig.~1~ 2006-09-20 19:28:45.000000000 +0200
-+++ linux-2.6.18.perfctr26/arch/x86_64/Kconfig 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/arch/x86_64/Kconfig.~1~ 2008-06-22 17:35:06.000000000 +0200
++++ linux-2.6.18.perfctr26/arch/x86_64/Kconfig 2008-06-22 17:37:14.000000000 +0200
@@ -526,6 +526,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -187,8 +192,8 @@
source kernel/Kconfig.hz
config REORDER
---- linux-2.6.18.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2006-09-20 19:28:45.000000000 +0200
-+++ linux-2.6.18.perfctr26/arch/x86_64/kernel/entry.S 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2008-06-22 17:35:06.000000000 +0200
++++ linux-2.6.18.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 17:37:14.000000000 +0200
@@ -693,6 +693,12 @@ ENTRY(spurious_interrupt)
END(spurious_interrupt)
#endif
@@ -202,8 +207,8 @@
/*
* Exception entry points.
*/
---- linux-2.6.18.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2006-09-20 19:28:45.000000000 +0200
-+++ linux-2.6.18.perfctr26/arch/x86_64/kernel/i8259.c 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2008-06-22 17:35:06.000000000 +0200
++++ linux-2.6.18.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 17:37:14.000000000 +0200
@@ -22,6 +22,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -221,8 +226,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.18.perfctr26/arch/x86_64/kernel/process.c.~1~ 2006-09-20 19:28:45.000000000 +0200
-+++ linux-2.6.18.perfctr26/arch/x86_64/kernel/process.c 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/arch/x86_64/kernel/process.c.~1~ 2008-06-22 17:35:06.000000000 +0200
++++ linux-2.6.18.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 17:37:14.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/interrupt.h>
#include <linux/delay.h>
@@ -257,8 +262,8 @@
return prev_p;
}
---- linux-2.6.18.perfctr26/drivers/Makefile.~1~ 2006-09-20 19:28:46.000000000 +0200
-+++ linux-2.6.18.perfctr26/drivers/Makefile 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/drivers/Makefile.~1~ 2008-06-22 17:35:06.000000000 +0200
++++ linux-2.6.18.perfctr26/drivers/Makefile 2008-06-22 17:37:14.000000000 +0200
@@ -71,6 +71,7 @@ obj-$(CONFIG_NEW_LEDS) += leds/
obj-$(CONFIG_INFINIBAND) += infiniband/
obj-$(CONFIG_IPATH_CORE) += infiniband/
@@ -267,8 +272,26 @@
obj-y += firmware/
obj-$(CONFIG_CRYPTO) += crypto/
obj-$(CONFIG_SUPERH) += sh/
---- linux-2.6.18.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2004-05-10 11:14:37.000000000 +0200
-+++ linux-2.6.18.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/fs/exec.c.~1~ 2008-06-22 17:35:07.000000000 +0200
++++ linux-2.6.18.perfctr26/fs/exec.c 2008-06-22 17:37:20.000000000 +0200
+@@ -49,6 +49,7 @@
+ #include <linux/acct.h>
+ #include <linux/cn_proc.h>
+ #include <linux/audit.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -875,6 +876,7 @@ int flush_old_exec(struct linux_binprm *
+ set_task_comm(current, tcomm);
+
+ current->flags &= ~PF_RANDOMIZE;
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ /* Set the new mm task size. We have to do that late because it may
+--- linux-2.6.18.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.18.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 17:37:14.000000000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -287,8 +310,8 @@
#define TIMER_IRQ 0
---- linux-2.6.18.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2004-01-09 13:19:11.000000000 +0100
-+++ linux-2.6.18.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.18.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 17:37:14.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -307,8 +330,8 @@
#define TIMER_IRQ 0
---- linux-2.6.18.perfctr26/include/asm-i386/processor.h.~1~ 2006-09-20 19:28:55.000000000 +0200
-+++ linux-2.6.18.perfctr26/include/asm-i386/processor.h 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/include/asm-i386/processor.h.~1~ 2008-06-22 17:35:07.000000000 +0200
++++ linux-2.6.18.perfctr26/include/asm-i386/processor.h 2008-06-22 17:37:14.000000000 +0200
@@ -471,6 +471,8 @@ struct thread_struct {
unsigned long iopl;
/* max allowed port in the bitmap, in bytes: */
@@ -318,8 +341,8 @@
};
#define INIT_THREAD { \
---- linux-2.6.18.perfctr26/include/asm-i386/system.h.~1~ 2006-09-20 19:28:55.000000000 +0200
-+++ linux-2.6.18.perfctr26/include/asm-i386/system.h 2006-09-20 19:58:13.000000000 +0200
+--- linux-2.6.18.perfctr26/include/asm-i386/system.h.~1~ 2008-06-22 17:35:07.000000000 +0200
++++ linux-2.6.18.perfctr26/include/asm-i386/system.h 2008-06-22 17:37:14.000000000 +0200
@@ -17,6 +17,7 @@ extern struct task_struct * FASTCALL(__s
*/
#define switch_to(prev,next,last) do { \
@@ -328,8 +351,8 @@
asm volatile("pushfl\n\t" /* Save flags */ \
"pushl %%ebp\n\t" \
"movl %%esp,%0\n\t" /* save ESP */ \
---- linux-2.6.18.perfctr26/include/asm-powerpc/processor.h.~1~ 2006-09-20 19:28:56.000000000 +0200
-+++ linux-2.6.18.perfctr26/include/asm-powerpc/processor.h 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/include/asm-powerpc/processor.h.~1~ 2008-06-22 17:35:07.000000000 +0200
++++ linux-2.6.18.perfctr26/include/asm-powerpc/processor.h 2008-06-22 17:37:14.000000000 +0200
@@ -169,6 +169,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
@@ -340,8 +363,8 @@
};
#define ARCH_MIN_TASKALIGN 16
---- linux-2.6.18.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2006-09-20 19:28:57.000000000 +0200
-+++ linux-2.6.18.perfctr26/include/asm-x86_64/hw_irq.h 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2008-06-22 17:35:10.000000000 +0200
++++ linux-2.6.18.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 17:37:14.000000000 +0200
@@ -64,14 +64,15 @@ struct hw_interrupt_type;
* sources per level' errata.
*/
@@ -360,8 +383,8 @@
#ifndef __ASSEMBLY__
---- linux-2.6.18.perfctr26/include/asm-x86_64/irq.h.~1~ 2006-03-20 10:40:11.000000000 +0100
-+++ linux-2.6.18.perfctr26/include/asm-x86_64/irq.h 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/include/asm-x86_64/irq.h.~1~ 2008-06-22 17:35:10.000000000 +0200
++++ linux-2.6.18.perfctr26/include/asm-x86_64/irq.h 2008-06-22 17:37:14.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -371,8 +394,8 @@
#ifdef CONFIG_PCI_MSI
#define NR_IRQS FIRST_SYSTEM_VECTOR
---- linux-2.6.18.perfctr26/include/asm-x86_64/processor.h.~1~ 2006-09-20 19:28:57.000000000 +0200
-+++ linux-2.6.18.perfctr26/include/asm-x86_64/processor.h 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/include/asm-x86_64/processor.h.~1~ 2008-06-22 17:35:10.000000000 +0200
++++ linux-2.6.18.perfctr26/include/asm-x86_64/processor.h 2008-06-22 17:37:14.000000000 +0200
@@ -274,6 +274,8 @@ struct thread_struct {
unsigned io_bitmap_max;
/* cached TLS descriptors. */
@@ -382,8 +405,8 @@
} __attribute__((aligned(16)));
#define INIT_THREAD { \
---- linux-2.6.18.perfctr26/include/asm-x86_64/system.h.~1~ 2006-09-20 19:28:57.000000000 +0200
-+++ linux-2.6.18.perfctr26/include/asm-x86_64/system.h 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/include/asm-x86_64/system.h.~1~ 2008-06-22 17:35:10.000000000 +0200
++++ linux-2.6.18.perfctr26/include/asm-x86_64/system.h 2008-06-22 17:37:14.000000000 +0200
@@ -20,7 +20,8 @@
#define __EXTRA_CLOBBER \
,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
@@ -404,8 +427,8 @@
extern void load_gs_index(unsigned);
---- linux-2.6.18.perfctr26/kernel/exit.c.~1~ 2006-09-20 19:29:10.000000000 +0200
-+++ linux-2.6.18.perfctr26/kernel/exit.c 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/kernel/exit.c.~1~ 2008-06-22 17:35:10.000000000 +0200
++++ linux-2.6.18.perfctr26/kernel/exit.c 2008-06-22 17:37:14.000000000 +0200
@@ -25,6 +25,7 @@
#include <linux/mount.h>
#include <linux/proc_fs.h>
@@ -422,8 +445,8 @@
sched_exit(p);
write_unlock_irq(&tasklist_lock);
proc_flush_task(p);
---- linux-2.6.18.perfctr26/kernel/sched.c.~1~ 2006-09-20 19:29:10.000000000 +0200
-+++ linux-2.6.18.perfctr26/kernel/sched.c 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/kernel/sched.c.~1~ 2008-06-22 17:35:10.000000000 +0200
++++ linux-2.6.18.perfctr26/kernel/sched.c 2008-06-22 17:37:14.000000000 +0200
@@ -45,6 +45,7 @@
#include <linux/cpu.h>
#include <linux/cpuset.h>
@@ -441,8 +464,8 @@
rq = task_rq_lock(p, &flags);
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
---- linux-2.6.18.perfctr26/kernel/timer.c.~1~ 2006-09-20 19:29:10.000000000 +0200
-+++ linux-2.6.18.perfctr26/kernel/timer.c 2006-09-20 19:57:36.000000000 +0200
+--- linux-2.6.18.perfctr26/kernel/timer.c.~1~ 2008-06-22 17:35:10.000000000 +0200
++++ linux-2.6.18.perfctr26/kernel/timer.c 2008-06-22 17:37:14.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/jiffies.h>
#include <linux/posix-timers.h>
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.18-53.el5-redhat b/src/perfctr-2.6.x/patches/patch-kernel-2.6.18-53.el5-redhat
index 1278fb85e710eaf7890bc7b4af5948b49a43ee55..9857437a39581a2fdd4cd10ee04b2169982178a9 100644
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.18-53.el5-redhat
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.18-53.el5-redhat
@@ -1,5 +1,5 @@
--- linux-2.6.18-53.el5.perfctr26/CREDITS.~1~ 2007-11-15 23:42:57.000000000 +0100
-+++ linux-2.6.18-53.el5.perfctr26/CREDITS 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/CREDITS 2008-06-22 23:57:52.000000000 +0200
@@ -2635,9 +2635,10 @@ S: Ottawa, Ontario
S: Canada K2P 0X8
@@ -14,7 +14,7 @@
N: Reed H. Petty
E: rhp@draper.net
--- linux-2.6.18-53.el5.perfctr26/Documentation/ioctl-number.txt.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-53.el5.perfctr26/Documentation/ioctl-number.txt 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/Documentation/ioctl-number.txt 2008-06-22 23:57:52.000000000 +0200
@@ -187,6 +187,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -25,7 +25,7 @@
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
--- linux-2.6.18-53.el5.perfctr26/MAINTAINERS.~1~ 2007-11-15 23:42:58.000000000 +0100
-+++ linux-2.6.18-53.el5.perfctr26/MAINTAINERS 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/MAINTAINERS 2008-06-22 23:57:52.000000000 +0200
@@ -2326,6 +2326,12 @@ M: nagar@watson.ibm.com
L: linux-kernel@vger.kernel.org
S: Maintained
@@ -40,7 +40,7 @@
P: Christoph Hellwig
M: hch@infradead.org
--- linux-2.6.18-53.el5.perfctr26/arch/i386/Kconfig.~1~ 2007-11-15 23:42:58.000000000 +0100
-+++ linux-2.6.18-53.el5.perfctr26/arch/i386/Kconfig 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/arch/i386/Kconfig 2008-06-22 23:57:52.000000000 +0200
@@ -773,6 +773,8 @@ config VGA_NOPROBE
data. Say N here unless you are absolutely sure this is what you
want.
@@ -51,7 +51,7 @@
config KEXEC
--- linux-2.6.18-53.el5.perfctr26/arch/i386/kernel/entry.S.~1~ 2007-11-15 23:42:59.000000000 +0100
-+++ linux-2.6.18-53.el5.perfctr26/arch/i386/kernel/entry.S 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/arch/i386/kernel/entry.S 2008-06-22 23:57:52.000000000 +0200
@@ -586,6 +586,22 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -76,7 +76,7 @@
RING0_INT_FRAME
pushl $0 # no error code
--- linux-2.6.18-53.el5.perfctr26/arch/i386/kernel/i8259.c.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-53.el5.perfctr26/arch/i386/kernel/i8259.c 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 23:57:52.000000000 +0200
@@ -22,6 +22,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -95,7 +95,7 @@
* Set the clock to HZ Hz, we already have a valid
* vector now:
--- linux-2.6.18-53.el5.perfctr26/arch/i386/kernel/process.c.~1~ 2007-11-15 23:42:58.000000000 +0100
-+++ linux-2.6.18-53.el5.perfctr26/arch/i386/kernel/process.c 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/arch/i386/kernel/process.c 2008-06-22 23:57:52.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -131,7 +131,7 @@
}
--- linux-2.6.18-53.el5.perfctr26/arch/powerpc/Kconfig.~1~ 2007-11-15 23:42:50.000000000 +0100
-+++ linux-2.6.18-53.el5.perfctr26/arch/powerpc/Kconfig 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/arch/powerpc/Kconfig 2008-06-22 23:57:52.000000000 +0200
@@ -335,6 +335,11 @@ config NOT_COHERENT_CACHE
bool
depends on 4xx || 8xx || E200
@@ -145,7 +145,7 @@
source "init/Kconfig"
--- linux-2.6.18-53.el5.perfctr26/arch/powerpc/kernel/process.c.~1~ 2007-11-15 23:42:45.000000000 +0100
-+++ linux-2.6.18-53.el5.perfctr26/arch/powerpc/kernel/process.c 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/arch/powerpc/kernel/process.c 2008-06-22 23:57:52.000000000 +0200
@@ -31,6 +31,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -182,7 +182,7 @@
}
--- linux-2.6.18-53.el5.perfctr26/arch/x86_64/Kconfig.~1~ 2007-11-15 23:42:58.000000000 +0100
-+++ linux-2.6.18-53.el5.perfctr26/arch/x86_64/Kconfig 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/arch/x86_64/Kconfig 2008-06-22 23:57:52.000000000 +0200
@@ -569,6 +569,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -193,7 +193,7 @@
config REORDER
--- linux-2.6.18-53.el5.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2007-11-15 23:42:58.000000000 +0100
-+++ linux-2.6.18-53.el5.perfctr26/arch/x86_64/kernel/entry.S 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 23:57:52.000000000 +0200
@@ -699,6 +699,12 @@ ENTRY(spurious_interrupt)
END(spurious_interrupt)
#endif
@@ -208,7 +208,7 @@
* Exception entry points.
*/
--- linux-2.6.18-53.el5.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2007-11-15 23:42:50.000000000 +0100
-+++ linux-2.6.18-53.el5.perfctr26/arch/x86_64/kernel/i8259.c 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 23:57:52.000000000 +0200
@@ -22,6 +22,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -227,7 +227,7 @@
* Set the clock to HZ Hz, we already have a valid
* vector now:
--- linux-2.6.18-53.el5.perfctr26/arch/x86_64/kernel/process.c.~1~ 2007-11-15 23:42:58.000000000 +0100
-+++ linux-2.6.18-53.el5.perfctr26/arch/x86_64/kernel/process.c 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 23:57:52.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/interrupt.h>
#include <linux/delay.h>
@@ -263,7 +263,7 @@
}
--- linux-2.6.18-53.el5.perfctr26/drivers/Makefile.~1~ 2007-11-15 23:42:58.000000000 +0100
-+++ linux-2.6.18-53.el5.perfctr26/drivers/Makefile 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/drivers/Makefile 2008-06-22 23:57:52.000000000 +0200
@@ -74,6 +74,7 @@ obj-$(CONFIG_NEW_LEDS) += leds/
obj-$(CONFIG_INFINIBAND) += infiniband/
obj-$(CONFIG_IPATH_CORE) += infiniband/
@@ -272,8 +272,26 @@
obj-y += firmware/
obj-$(CONFIG_CRYPTO) += crypto/
obj-$(CONFIG_SUPERH) += sh/
+--- linux-2.6.18-53.el5.perfctr26/fs/exec.c.~1~ 2007-11-15 23:42:59.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/fs/exec.c 2008-06-22 23:57:59.000000000 +0200
+@@ -49,6 +49,7 @@
+ #include <linux/acct.h>
+ #include <linux/cn_proc.h>
+ #include <linux/audit.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -875,6 +876,7 @@ int flush_old_exec(struct linux_binprm *
+ set_task_comm(current, tcomm);
+
+ current->flags &= ~PF_RANDOMIZE;
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ /* Set the new mm task size. We have to do that late because it may
--- linux-2.6.18-53.el5.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-53.el5.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 23:57:52.000000000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -293,7 +311,7 @@
#define TIMER_IRQ 0
--- linux-2.6.18-53.el5.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-53.el5.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 23:57:52.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -313,7 +331,7 @@
#define TIMER_IRQ 0
--- linux-2.6.18-53.el5.perfctr26/include/asm-i386/processor.h.~1~ 2007-11-15 23:42:58.000000000 +0100
-+++ linux-2.6.18-53.el5.perfctr26/include/asm-i386/processor.h 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/include/asm-i386/processor.h 2008-06-22 23:57:52.000000000 +0200
@@ -474,6 +474,8 @@ struct thread_struct {
unsigned long iopl;
/* max allowed port in the bitmap, in bytes: */
@@ -324,7 +342,7 @@
#define INIT_THREAD { \
--- linux-2.6.18-53.el5.perfctr26/include/asm-i386/system.h.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-53.el5.perfctr26/include/asm-i386/system.h 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/include/asm-i386/system.h 2008-06-22 23:57:52.000000000 +0200
@@ -17,6 +17,7 @@ extern struct task_struct * FASTCALL(__s
*/
#define switch_to(prev,next,last) do { \
@@ -334,7 +352,7 @@
"pushl %%ebp\n\t" \
"movl %%esp,%0\n\t" /* save ESP */ \
--- linux-2.6.18-53.el5.perfctr26/include/asm-powerpc/processor.h.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-53.el5.perfctr26/include/asm-powerpc/processor.h 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/include/asm-powerpc/processor.h 2008-06-22 23:57:52.000000000 +0200
@@ -169,6 +169,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
@@ -346,7 +364,7 @@
#define ARCH_MIN_TASKALIGN 16
--- linux-2.6.18-53.el5.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-53.el5.perfctr26/include/asm-x86_64/hw_irq.h 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 23:57:52.000000000 +0200
@@ -64,14 +64,15 @@ struct hw_interrupt_type;
* sources per level' errata.
*/
@@ -366,7 +384,7 @@
#ifndef __ASSEMBLY__
--- linux-2.6.18-53.el5.perfctr26/include/asm-x86_64/irq.h.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-53.el5.perfctr26/include/asm-x86_64/irq.h 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/include/asm-x86_64/irq.h 2008-06-22 23:57:52.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -377,7 +395,7 @@
#ifdef CONFIG_PCI_MSI
#define NR_IRQS FIRST_SYSTEM_VECTOR
--- linux-2.6.18-53.el5.perfctr26/include/asm-x86_64/processor.h.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-53.el5.perfctr26/include/asm-x86_64/processor.h 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/include/asm-x86_64/processor.h 2008-06-22 23:57:52.000000000 +0200
@@ -274,6 +274,8 @@ struct thread_struct {
unsigned io_bitmap_max;
/* cached TLS descriptors. */
@@ -388,7 +406,7 @@
#define INIT_THREAD { \
--- linux-2.6.18-53.el5.perfctr26/include/asm-x86_64/system.h.~1~ 2007-11-15 23:42:49.000000000 +0100
-+++ linux-2.6.18-53.el5.perfctr26/include/asm-x86_64/system.h 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/include/asm-x86_64/system.h 2008-06-22 23:57:52.000000000 +0200
@@ -21,7 +21,8 @@
,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
@@ -410,7 +428,7 @@
extern void load_gs_index(unsigned);
--- linux-2.6.18-53.el5.perfctr26/include/linux/config.h.~1~ 2007-11-15 23:42:45.000000000 +0100
-+++ linux-2.6.18-53.el5.perfctr26/include/linux/config.h 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/include/linux/config.h 2008-06-22 23:57:52.000000000 +0200
@@ -3,6 +3,8 @@
/* This file is no longer in use and kept only for backward compatibility.
* autoconf.h is now included via -imacros on the commandline
@@ -421,7 +439,7 @@
#include <linux/autoconf.h>
#if !defined (__KERNEL__) && !defined(__KERNGLUE__)
--- linux-2.6.18-53.el5.perfctr26/kernel/exit.c.~1~ 2007-11-15 23:42:59.000000000 +0100
-+++ linux-2.6.18-53.el5.perfctr26/kernel/exit.c 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/kernel/exit.c 2008-06-22 23:57:52.000000000 +0200
@@ -26,6 +26,7 @@
#include <linux/mount.h>
#include <linux/proc_fs.h>
@@ -439,7 +457,7 @@
write_unlock_irq(&tasklist_lock);
proc_flush_task(p);
--- linux-2.6.18-53.el5.perfctr26/kernel/sched.c.~1~ 2007-11-15 23:42:50.000000000 +0100
-+++ linux-2.6.18-53.el5.perfctr26/kernel/sched.c 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/kernel/sched.c 2008-06-22 23:57:52.000000000 +0200
@@ -45,6 +45,7 @@
#include <linux/cpu.h>
#include <linux/cpuset.h>
@@ -458,7 +476,7 @@
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
--- linux-2.6.18-53.el5.perfctr26/kernel/timer.c.~1~ 2007-11-15 23:42:58.000000000 +0100
-+++ linux-2.6.18-53.el5.perfctr26/kernel/timer.c 2007-11-16 00:41:11.000000000 +0100
++++ linux-2.6.18-53.el5.perfctr26/kernel/timer.c 2008-06-22 23:57:52.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/jiffies.h>
#include <linux/posix-timers.h>
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.18-8.1.1.el5-redhat b/src/perfctr-2.6.x/patches/patch-kernel-2.6.18-8.1.1.el5-redhat
index 0c6a8e1da30c786ebb19d6852597f7bee2c5e5e4..01357697756186fa5037c1a2f9794309e6e86782 100644
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.18-8.1.1.el5-redhat
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.18-8.1.1.el5-redhat
@@ -1,19 +1,20 @@
--- linux-2.6.18-8.1.1.el5.perfctr26/CREDITS.~1~ 2007-03-26 23:35:12.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/CREDITS 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/CREDITS 2008-06-23 00:27:57.000000000 +0200
@@ -2629,9 +2629,10 @@ S: Ottawa, Ontario
S: Canada K2P 0X8
N: Mikael Pettersson
-E: mikpe@csd.uu.se
+-W: http://www.csd.uu.se/~mikpe/
+E: mikpe@it.uu.se
- W: http://www.csd.uu.se/~mikpe/
++W: http://user.it.uu.se/~mikpe/
D: Miscellaneous fixes
+D: Performance-monitoring counters driver
N: Reed H. Petty
E: rhp@draper.net
--- linux-2.6.18-8.1.1.el5.perfctr26/Documentation/ioctl-number.txt.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/Documentation/ioctl-number.txt 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/Documentation/ioctl-number.txt 2008-06-23 00:27:48.000000000 +0200
@@ -187,6 +187,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -24,7 +25,7 @@
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
--- linux-2.6.18-8.1.1.el5.perfctr26/MAINTAINERS.~1~ 2007-03-26 23:35:12.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/MAINTAINERS 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/MAINTAINERS 2008-06-23 00:27:57.000000000 +0200
@@ -2303,6 +2303,12 @@ M: nagar@watson.ibm.com
L: linux-kernel@vger.kernel.org
S: Maintained
@@ -32,14 +33,14 @@
+PERFORMANCE-MONITORING COUNTERS DRIVER
+P: Mikael Pettersson
+M: mikpe@it.uu.se
-+W: http://www.csd.uu.se/~mikpe/linux/perfctr/
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
+S: Maintained
+
PERSONALITY HANDLING
P: Christoph Hellwig
M: hch@infradead.org
--- linux-2.6.18-8.1.1.el5.perfctr26/arch/i386/Kconfig.~1~ 2007-03-26 23:35:18.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/arch/i386/Kconfig 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/arch/i386/Kconfig 2008-06-23 00:27:48.000000000 +0200
@@ -766,6 +766,8 @@ config VGA_NOPROBE
data. Say N here unless you are absolutely sure this is what you
want.
@@ -50,7 +51,7 @@
config KEXEC
--- linux-2.6.18-8.1.1.el5.perfctr26/arch/i386/kernel/entry.S.~1~ 2007-03-26 23:35:21.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/arch/i386/kernel/entry.S 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/arch/i386/kernel/entry.S 2008-06-23 00:27:48.000000000 +0200
@@ -588,6 +588,22 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -75,7 +76,7 @@
RING0_INT_FRAME
pushl $0 # no error code
--- linux-2.6.18-8.1.1.el5.perfctr26/arch/i386/kernel/i8259.c.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/arch/i386/kernel/i8259.c 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/arch/i386/kernel/i8259.c 2008-06-23 00:27:48.000000000 +0200
@@ -22,6 +22,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -94,7 +95,7 @@
* Set the clock to HZ Hz, we already have a valid
* vector now:
--- linux-2.6.18-8.1.1.el5.perfctr26/arch/i386/kernel/process.c.~1~ 2007-03-26 23:35:10.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/arch/i386/kernel/process.c 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/arch/i386/kernel/process.c 2008-06-23 00:27:48.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -130,7 +131,7 @@
}
--- linux-2.6.18-8.1.1.el5.perfctr26/arch/powerpc/Kconfig.~1~ 2007-03-26 23:35:18.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/arch/powerpc/Kconfig 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/arch/powerpc/Kconfig 2008-06-23 00:27:48.000000000 +0200
@@ -320,6 +320,11 @@ config NOT_COHERENT_CACHE
bool
depends on 4xx || 8xx || E200
@@ -144,7 +145,7 @@
source "init/Kconfig"
--- linux-2.6.18-8.1.1.el5.perfctr26/arch/powerpc/kernel/process.c.~1~ 2007-03-26 23:35:09.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/arch/powerpc/kernel/process.c 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/arch/powerpc/kernel/process.c 2008-06-23 00:27:48.000000000 +0200
@@ -31,6 +31,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -181,7 +182,7 @@
}
--- linux-2.6.18-8.1.1.el5.perfctr26/arch/x86_64/Kconfig.~1~ 2007-03-26 23:35:20.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/arch/x86_64/Kconfig 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/arch/x86_64/Kconfig 2008-06-23 00:27:48.000000000 +0200
@@ -562,6 +562,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -192,7 +193,7 @@
config REORDER
--- linux-2.6.18-8.1.1.el5.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2007-03-26 23:35:21.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/arch/x86_64/kernel/entry.S 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/arch/x86_64/kernel/entry.S 2008-06-23 00:27:48.000000000 +0200
@@ -695,6 +695,12 @@ ENTRY(spurious_interrupt)
END(spurious_interrupt)
#endif
@@ -207,7 +208,7 @@
* Exception entry points.
*/
--- linux-2.6.18-8.1.1.el5.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/arch/x86_64/kernel/i8259.c 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-23 00:27:48.000000000 +0200
@@ -22,6 +22,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -226,7 +227,7 @@
* Set the clock to HZ Hz, we already have a valid
* vector now:
--- linux-2.6.18-8.1.1.el5.perfctr26/arch/x86_64/kernel/process.c.~1~ 2007-03-26 23:35:20.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/arch/x86_64/kernel/process.c 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/arch/x86_64/kernel/process.c 2008-06-23 00:27:48.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/interrupt.h>
#include <linux/delay.h>
@@ -262,7 +263,7 @@
}
--- linux-2.6.18-8.1.1.el5.perfctr26/drivers/Makefile.~1~ 2007-03-26 23:35:11.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/drivers/Makefile 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/drivers/Makefile 2008-06-23 00:27:48.000000000 +0200
@@ -72,6 +72,7 @@ obj-$(CONFIG_NEW_LEDS) += leds/
obj-$(CONFIG_INFINIBAND) += infiniband/
obj-$(CONFIG_IPATH_CORE) += infiniband/
@@ -271,8 +272,26 @@
obj-y += firmware/
obj-$(CONFIG_CRYPTO) += crypto/
obj-$(CONFIG_SUPERH) += sh/
+--- linux-2.6.18-8.1.1.el5.perfctr26/fs/exec.c.~1~ 2007-03-26 23:35:11.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/fs/exec.c 2008-06-23 00:27:57.000000000 +0200
+@@ -49,6 +49,7 @@
+ #include <linux/acct.h>
+ #include <linux/cn_proc.h>
+ #include <linux/audit.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -875,6 +876,7 @@ int flush_old_exec(struct linux_binprm *
+ set_task_comm(current, tcomm);
+
+ current->flags &= ~PF_RANDOMIZE;
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ /* Set the new mm task size. We have to do that late because it may
--- linux-2.6.18-8.1.1.el5.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-23 00:27:48.000000000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -292,7 +311,7 @@
#define TIMER_IRQ 0
--- linux-2.6.18-8.1.1.el5.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-23 00:27:48.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -312,7 +331,7 @@
#define TIMER_IRQ 0
--- linux-2.6.18-8.1.1.el5.perfctr26/include/asm-i386/processor.h.~1~ 2007-03-26 23:35:11.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/include/asm-i386/processor.h 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/include/asm-i386/processor.h 2008-06-23 00:27:48.000000000 +0200
@@ -474,6 +474,8 @@ struct thread_struct {
unsigned long iopl;
/* max allowed port in the bitmap, in bytes: */
@@ -323,7 +342,7 @@
#define INIT_THREAD { \
--- linux-2.6.18-8.1.1.el5.perfctr26/include/asm-i386/system.h.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/include/asm-i386/system.h 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/include/asm-i386/system.h 2008-06-23 00:27:48.000000000 +0200
@@ -17,6 +17,7 @@ extern struct task_struct * FASTCALL(__s
*/
#define switch_to(prev,next,last) do { \
@@ -333,7 +352,7 @@
"pushl %%ebp\n\t" \
"movl %%esp,%0\n\t" /* save ESP */ \
--- linux-2.6.18-8.1.1.el5.perfctr26/include/asm-powerpc/processor.h.~1~ 2007-03-26 23:35:10.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/include/asm-powerpc/processor.h 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/include/asm-powerpc/processor.h 2008-06-23 00:27:48.000000000 +0200
@@ -169,6 +169,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
@@ -345,7 +364,7 @@
#define ARCH_MIN_TASKALIGN 16
--- linux-2.6.18-8.1.1.el5.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/include/asm-x86_64/hw_irq.h 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-23 00:27:48.000000000 +0200
@@ -64,14 +64,15 @@ struct hw_interrupt_type;
* sources per level' errata.
*/
@@ -365,7 +384,7 @@
#ifndef __ASSEMBLY__
--- linux-2.6.18-8.1.1.el5.perfctr26/include/asm-x86_64/irq.h.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/include/asm-x86_64/irq.h 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/include/asm-x86_64/irq.h 2008-06-23 00:27:48.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -376,7 +395,7 @@
#ifdef CONFIG_PCI_MSI
#define NR_IRQS FIRST_SYSTEM_VECTOR
--- linux-2.6.18-8.1.1.el5.perfctr26/include/asm-x86_64/processor.h.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/include/asm-x86_64/processor.h 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/include/asm-x86_64/processor.h 2008-06-23 00:27:48.000000000 +0200
@@ -274,6 +274,8 @@ struct thread_struct {
unsigned io_bitmap_max;
/* cached TLS descriptors. */
@@ -387,7 +406,7 @@
#define INIT_THREAD { \
--- linux-2.6.18-8.1.1.el5.perfctr26/include/asm-x86_64/system.h.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/include/asm-x86_64/system.h 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/include/asm-x86_64/system.h 2008-06-23 00:27:48.000000000 +0200
@@ -20,7 +20,8 @@
#define __EXTRA_CLOBBER \
,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
@@ -409,7 +428,7 @@
extern void load_gs_index(unsigned);
--- linux-2.6.18-8.1.1.el5.perfctr26/include/linux/config.h.~1~ 2007-03-26 23:35:10.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/include/linux/config.h 2007-04-09 16:09:00.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/include/linux/config.h 2008-06-23 00:27:48.000000000 +0200
@@ -3,6 +3,8 @@
/* This file is no longer in use and kept only for backward compatibility.
* autoconf.h is now included via -imacros on the commandline
@@ -420,7 +439,7 @@
#include <linux/autoconf.h>
#if !defined (__KERNEL__) && !defined(__KERNGLUE__)
--- linux-2.6.18-8.1.1.el5.perfctr26/kernel/exit.c.~1~ 2007-03-26 23:35:11.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/kernel/exit.c 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/kernel/exit.c 2008-06-23 00:27:48.000000000 +0200
@@ -26,6 +26,7 @@
#include <linux/mount.h>
#include <linux/proc_fs.h>
@@ -438,7 +457,7 @@
write_unlock_irq(&tasklist_lock);
proc_flush_task(p);
--- linux-2.6.18-8.1.1.el5.perfctr26/kernel/sched.c.~1~ 2007-03-26 23:35:16.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/kernel/sched.c 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/kernel/sched.c 2008-06-23 00:27:48.000000000 +0200
@@ -45,6 +45,7 @@
#include <linux/cpu.h>
#include <linux/cpuset.h>
@@ -457,7 +476,7 @@
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
--- linux-2.6.18-8.1.1.el5.perfctr26/kernel/timer.c.~1~ 2007-03-26 23:35:09.000000000 +0200
-+++ linux-2.6.18-8.1.1.el5.perfctr26/kernel/timer.c 2007-04-09 16:08:57.000000000 +0200
++++ linux-2.6.18-8.1.1.el5.perfctr26/kernel/timer.c 2008-06-23 00:27:48.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/jiffies.h>
#include <linux/posix-timers.h>
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.18-92.el5-redhat b/src/perfctr-2.6.x/patches/patch-kernel-2.6.18-92.el5-redhat
index eda52631a90a63445a4365e71fb2fc08998cd4de..9f234f4e98bbc4615d32c237cf0ec6b9e8cfa089 100644
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.18-92.el5-redhat
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.18-92.el5-redhat
@@ -1,5 +1,5 @@
--- linux-2.6.18-92.el5.perfctr26/CREDITS.~1~ 2008-05-25 21:12:38.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/CREDITS 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/CREDITS 2008-06-23 00:12:34.000000000 +0200
@@ -2635,9 +2635,10 @@ S: Ottawa, Ontario
S: Canada K2P 0X8
@@ -14,7 +14,7 @@
N: Reed H. Petty
E: rhp@draper.net
--- linux-2.6.18-92.el5.perfctr26/Documentation/ioctl-number.txt.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/Documentation/ioctl-number.txt 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/Documentation/ioctl-number.txt 2008-06-23 00:12:34.000000000 +0200
@@ -187,6 +187,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -25,7 +25,7 @@
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
--- linux-2.6.18-92.el5.perfctr26/MAINTAINERS.~1~ 2008-05-25 21:12:43.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/MAINTAINERS 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/MAINTAINERS 2008-06-23 00:12:34.000000000 +0200
@@ -2333,6 +2333,12 @@ M: nagar@watson.ibm.com
L: linux-kernel@vger.kernel.org
S: Maintained
@@ -40,7 +40,7 @@
P: Christoph Hellwig
M: hch@infradead.org
--- linux-2.6.18-92.el5.perfctr26/arch/i386/Kconfig.~1~ 2008-05-25 21:12:40.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/arch/i386/Kconfig 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/arch/i386/Kconfig 2008-06-23 00:12:34.000000000 +0200
@@ -773,6 +773,8 @@ config VGA_NOPROBE
data. Say N here unless you are absolutely sure this is what you
want.
@@ -51,7 +51,7 @@
config KEXEC
--- linux-2.6.18-92.el5.perfctr26/arch/i386/kernel/entry.S.~1~ 2008-05-25 21:12:41.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/arch/i386/kernel/entry.S 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/arch/i386/kernel/entry.S 2008-06-23 00:12:34.000000000 +0200
@@ -586,6 +586,22 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -76,7 +76,7 @@
RING0_INT_FRAME
pushl $0 # no error code
--- linux-2.6.18-92.el5.perfctr26/arch/i386/kernel/i8259.c.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/arch/i386/kernel/i8259.c 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/arch/i386/kernel/i8259.c 2008-06-23 00:12:34.000000000 +0200
@@ -22,6 +22,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -95,7 +95,7 @@
* Set the clock to HZ Hz, we already have a valid
* vector now:
--- linux-2.6.18-92.el5.perfctr26/arch/i386/kernel/process.c.~1~ 2008-05-25 21:12:39.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/arch/i386/kernel/process.c 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/arch/i386/kernel/process.c 2008-06-23 00:12:34.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -131,7 +131,7 @@
}
--- linux-2.6.18-92.el5.perfctr26/arch/powerpc/Kconfig.~1~ 2008-05-25 21:12:43.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/arch/powerpc/Kconfig 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/arch/powerpc/Kconfig 2008-06-23 00:12:34.000000000 +0200
@@ -335,6 +335,11 @@ config NOT_COHERENT_CACHE
bool
depends on 4xx || 8xx || E200
@@ -145,7 +145,7 @@
source "init/Kconfig"
--- linux-2.6.18-92.el5.perfctr26/arch/powerpc/kernel/process.c.~1~ 2008-05-25 21:12:31.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/arch/powerpc/kernel/process.c 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/arch/powerpc/kernel/process.c 2008-06-23 00:12:34.000000000 +0200
@@ -31,6 +31,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -182,7 +182,7 @@
}
--- linux-2.6.18-92.el5.perfctr26/arch/x86_64/Kconfig.~1~ 2008-05-25 21:12:40.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/arch/x86_64/Kconfig 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/arch/x86_64/Kconfig 2008-06-23 00:12:34.000000000 +0200
@@ -569,6 +569,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -193,7 +193,7 @@
config REORDER
--- linux-2.6.18-92.el5.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2008-05-25 21:12:46.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/arch/x86_64/kernel/entry.S 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/arch/x86_64/kernel/entry.S 2008-06-23 00:12:34.000000000 +0200
@@ -699,6 +699,12 @@ ENTRY(spurious_interrupt)
END(spurious_interrupt)
#endif
@@ -208,7 +208,7 @@
* Exception entry points.
*/
--- linux-2.6.18-92.el5.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2008-05-25 21:12:37.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/arch/x86_64/kernel/i8259.c 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-23 00:12:34.000000000 +0200
@@ -22,6 +22,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -227,7 +227,7 @@
* Set the clock to HZ Hz, we already have a valid
* vector now:
--- linux-2.6.18-92.el5.perfctr26/arch/x86_64/kernel/process.c.~1~ 2008-05-25 21:12:44.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/arch/x86_64/kernel/process.c 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/arch/x86_64/kernel/process.c 2008-06-23 00:12:34.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/interrupt.h>
#include <linux/delay.h>
@@ -263,7 +263,7 @@
}
--- linux-2.6.18-92.el5.perfctr26/drivers/Makefile.~1~ 2008-05-25 21:12:40.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/drivers/Makefile 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/drivers/Makefile 2008-06-23 00:12:34.000000000 +0200
@@ -74,6 +74,7 @@ obj-$(CONFIG_NEW_LEDS) += leds/
obj-$(CONFIG_INFINIBAND) += infiniband/
obj-$(CONFIG_IPATH_CORE) += infiniband/
@@ -272,8 +272,26 @@
obj-y += firmware/
obj-$(CONFIG_CRYPTO) += crypto/
obj-$(CONFIG_SUPERH) += sh/
+--- linux-2.6.18-92.el5.perfctr26/fs/exec.c.~1~ 2008-05-25 21:12:42.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/fs/exec.c 2008-06-23 00:12:41.000000000 +0200
+@@ -49,6 +49,7 @@
+ #include <linux/acct.h>
+ #include <linux/cn_proc.h>
+ #include <linux/audit.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -876,6 +877,7 @@ int flush_old_exec(struct linux_binprm *
+ set_task_comm(current, tcomm);
+
+ current->flags &= ~PF_RANDOMIZE;
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ /* Set the new mm task size. We have to do that late because it may
--- linux-2.6.18-92.el5.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-23 00:12:34.000000000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -293,7 +311,7 @@
#define TIMER_IRQ 0
--- linux-2.6.18-92.el5.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-23 00:12:34.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -313,7 +331,7 @@
#define TIMER_IRQ 0
--- linux-2.6.18-92.el5.perfctr26/include/asm-i386/processor.h.~1~ 2008-05-25 21:12:42.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/include/asm-i386/processor.h 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/include/asm-i386/processor.h 2008-06-23 00:12:34.000000000 +0200
@@ -475,6 +475,8 @@ struct thread_struct {
unsigned long iopl;
/* max allowed port in the bitmap, in bytes: */
@@ -324,7 +342,7 @@
#define INIT_THREAD { \
--- linux-2.6.18-92.el5.perfctr26/include/asm-i386/system.h.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/include/asm-i386/system.h 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/include/asm-i386/system.h 2008-06-23 00:12:34.000000000 +0200
@@ -17,6 +17,7 @@ extern struct task_struct * FASTCALL(__s
*/
#define switch_to(prev,next,last) do { \
@@ -334,7 +352,7 @@
"pushl %%ebp\n\t" \
"movl %%esp,%0\n\t" /* save ESP */ \
--- linux-2.6.18-92.el5.perfctr26/include/asm-powerpc/processor.h.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/include/asm-powerpc/processor.h 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/include/asm-powerpc/processor.h 2008-06-23 00:12:34.000000000 +0200
@@ -169,6 +169,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
@@ -346,7 +364,7 @@
#define ARCH_MIN_TASKALIGN 16
--- linux-2.6.18-92.el5.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/include/asm-x86_64/hw_irq.h 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-23 00:12:34.000000000 +0200
@@ -64,14 +64,15 @@ struct hw_interrupt_type;
* sources per level' errata.
*/
@@ -366,7 +384,7 @@
#ifndef __ASSEMBLY__
--- linux-2.6.18-92.el5.perfctr26/include/asm-x86_64/irq.h.~1~ 2006-09-20 05:42:06.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/include/asm-x86_64/irq.h 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/include/asm-x86_64/irq.h 2008-06-23 00:12:34.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -377,7 +395,7 @@
#ifdef CONFIG_PCI_MSI
#define NR_IRQS FIRST_SYSTEM_VECTOR
--- linux-2.6.18-92.el5.perfctr26/include/asm-x86_64/processor.h.~1~ 2008-05-25 21:12:42.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/include/asm-x86_64/processor.h 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/include/asm-x86_64/processor.h 2008-06-23 00:12:34.000000000 +0200
@@ -275,6 +275,8 @@ struct thread_struct {
unsigned io_bitmap_max;
/* cached TLS descriptors. */
@@ -388,7 +406,7 @@
#define INIT_THREAD { \
--- linux-2.6.18-92.el5.perfctr26/include/asm-x86_64/system.h.~1~ 2008-05-25 21:12:36.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/include/asm-x86_64/system.h 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/include/asm-x86_64/system.h 2008-06-23 00:12:34.000000000 +0200
@@ -21,7 +21,8 @@
,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
@@ -410,7 +428,7 @@
extern void load_gs_index(unsigned);
--- linux-2.6.18-92.el5.perfctr26/include/linux/config.h.~1~ 2008-05-25 21:12:32.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/include/linux/config.h 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/include/linux/config.h 2008-06-23 00:12:34.000000000 +0200
@@ -3,6 +3,8 @@
/* This file is no longer in use and kept only for backward compatibility.
* autoconf.h is now included via -imacros on the commandline
@@ -421,7 +439,7 @@
#include <linux/autoconf.h>
#if !defined (__KERNEL__) && !defined(__KERNGLUE__)
--- linux-2.6.18-92.el5.perfctr26/kernel/exit.c.~1~ 2008-05-25 21:12:42.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/kernel/exit.c 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/kernel/exit.c 2008-06-23 00:12:34.000000000 +0200
@@ -26,6 +26,7 @@
#include <linux/mount.h>
#include <linux/proc_fs.h>
@@ -439,7 +457,7 @@
write_unlock_irq(&tasklist_lock);
proc_flush_task(p);
--- linux-2.6.18-92.el5.perfctr26/kernel/sched.c.~1~ 2008-05-25 21:12:46.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/kernel/sched.c 2008-05-25 21:41:46.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/kernel/sched.c 2008-06-23 00:12:34.000000000 +0200
@@ -45,6 +45,7 @@
#include <linux/cpu.h>
#include <linux/cpuset.h>
@@ -458,7 +476,7 @@
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
--- linux-2.6.18-92.el5.perfctr26/kernel/timer.c.~1~ 2008-05-25 21:12:42.000000000 +0200
-+++ linux-2.6.18-92.el5.perfctr26/kernel/timer.c 2008-05-25 21:42:20.000000000 +0200
++++ linux-2.6.18-92.el5.perfctr26/kernel/timer.c 2008-06-23 00:12:34.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/jiffies.h>
#include <linux/posix-timers.h>
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.19 b/src/perfctr-2.6.x/patches/patch-kernel-2.6.19
index f156db3f102ce86c5dd07b3d4d9ec7522cbd0f20..293d83c5cbbd1c93f2722cdd4fccef7bf2ea4689 100644
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.19
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.19
@@ -1,15 +1,20 @@
---- linux-2.6.19.perfctr26/CREDITS.~1~ 2006-11-30 13:07:23.000000000 +0100
-+++ linux-2.6.19.perfctr26/CREDITS 2006-11-30 13:36:02.000000000 +0100
-@@ -2659,6 +2659,7 @@ N: Mikael Pettersson
- E: mikpe@csd.uu.se
- W: http://www.csd.uu.se/~mikpe/
+--- linux-2.6.19.perfctr26/CREDITS.~1~ 2008-06-22 17:20:35.000000000 +0200
++++ linux-2.6.19.perfctr26/CREDITS 2008-06-22 17:26:36.000000000 +0200
+@@ -2656,9 +2656,10 @@ S: Ottawa, Ontario
+ S: Canada K2P 0X8
+
+ N: Mikael Pettersson
+-E: mikpe@csd.uu.se
+-W: http://www.csd.uu.se/~mikpe/
++E: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/
D: Miscellaneous fixes
+D: Performance-monitoring counters driver
N: Reed H. Petty
E: rhp@draper.net
---- linux-2.6.19.perfctr26/Documentation/ioctl-number.txt.~1~ 2006-09-20 19:28:35.000000000 +0200
-+++ linux-2.6.19.perfctr26/Documentation/ioctl-number.txt 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/Documentation/ioctl-number.txt.~1~ 2008-06-22 17:20:35.000000000 +0200
++++ linux-2.6.19.perfctr26/Documentation/ioctl-number.txt 2008-06-22 17:26:29.000000000 +0200
@@ -187,6 +187,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -19,23 +24,23 @@
0xDD 00-3F ZFCP device driver see drivers/s390/scsi/
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
---- linux-2.6.19.perfctr26/MAINTAINERS.~1~ 2006-11-30 13:07:24.000000000 +0100
-+++ linux-2.6.19.perfctr26/MAINTAINERS 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/MAINTAINERS.~1~ 2008-06-22 17:20:35.000000000 +0200
++++ linux-2.6.19.perfctr26/MAINTAINERS 2008-06-22 17:26:36.000000000 +0200
@@ -2355,6 +2355,12 @@ M: nagar@watson.ibm.com
L: linux-kernel@vger.kernel.org
S: Maintained
+PERFORMANCE-MONITORING COUNTERS DRIVER
+P: Mikael Pettersson
-+M: mikpe@csd.uu.se
-+W: http://www.csd.uu.se/~mikpe/linux/perfctr/
++M: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
+S: Maintained
+
PERSONALITY HANDLING
P: Christoph Hellwig
M: hch@infradead.org
---- linux-2.6.19.perfctr26/arch/i386/Kconfig.~1~ 2006-11-30 13:07:24.000000000 +0100
-+++ linux-2.6.19.perfctr26/arch/i386/Kconfig 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/arch/i386/Kconfig.~1~ 2008-06-22 17:20:35.000000000 +0200
++++ linux-2.6.19.perfctr26/arch/i386/Kconfig 2008-06-22 17:26:29.000000000 +0200
@@ -741,6 +741,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -45,8 +50,8 @@
source kernel/Kconfig.hz
config KEXEC
---- linux-2.6.19.perfctr26/arch/i386/kernel/entry.S.~1~ 2006-11-30 13:07:24.000000000 +0100
-+++ linux-2.6.19.perfctr26/arch/i386/kernel/entry.S 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/arch/i386/kernel/entry.S.~1~ 2008-06-22 17:20:35.000000000 +0200
++++ linux-2.6.19.perfctr26/arch/i386/kernel/entry.S 2008-06-22 17:26:29.000000000 +0200
@@ -602,6 +602,22 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -70,8 +75,8 @@
KPROBE_ENTRY(page_fault)
RING0_EC_FRAME
pushl $do_page_fault
---- linux-2.6.19.perfctr26/arch/i386/kernel/i8259.c.~1~ 2006-11-30 13:07:24.000000000 +0100
-+++ linux-2.6.19.perfctr26/arch/i386/kernel/i8259.c 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/arch/i386/kernel/i8259.c.~1~ 2008-06-22 17:20:35.000000000 +0200
++++ linux-2.6.19.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 17:26:29.000000000 +0200
@@ -22,6 +22,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -89,8 +94,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.19.perfctr26/arch/i386/kernel/process.c.~1~ 2006-11-30 13:07:24.000000000 +0100
-+++ linux-2.6.19.perfctr26/arch/i386/kernel/process.c 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/arch/i386/kernel/process.c.~1~ 2008-06-22 17:20:35.000000000 +0200
++++ linux-2.6.19.perfctr26/arch/i386/kernel/process.c 2008-06-22 17:26:29.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -125,8 +130,8 @@
return prev_p;
}
---- linux-2.6.19.perfctr26/arch/powerpc/Kconfig.~1~ 2006-11-30 13:07:24.000000000 +0100
-+++ linux-2.6.19.perfctr26/arch/powerpc/Kconfig 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/arch/powerpc/Kconfig.~1~ 2008-06-22 17:20:36.000000000 +0200
++++ linux-2.6.19.perfctr26/arch/powerpc/Kconfig 2008-06-22 17:26:29.000000000 +0200
@@ -320,6 +320,11 @@ config NOT_COHERENT_CACHE
bool
depends on 4xx || 8xx || E200
@@ -139,8 +144,8 @@
endmenu
source "init/Kconfig"
---- linux-2.6.19.perfctr26/arch/powerpc/kernel/process.c.~1~ 2006-11-30 13:07:24.000000000 +0100
-+++ linux-2.6.19.perfctr26/arch/powerpc/kernel/process.c 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/arch/powerpc/kernel/process.c.~1~ 2008-06-22 17:08:53.000000000 +0200
++++ linux-2.6.19.perfctr26/arch/powerpc/kernel/process.c 2008-06-22 17:26:29.000000000 +0200
@@ -31,6 +31,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -176,8 +181,8 @@
return 0;
}
---- linux-2.6.19.perfctr26/arch/x86_64/Kconfig.~1~ 2006-11-30 13:07:25.000000000 +0100
-+++ linux-2.6.19.perfctr26/arch/x86_64/Kconfig 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/arch/x86_64/Kconfig.~1~ 2008-06-22 17:20:36.000000000 +0200
++++ linux-2.6.19.perfctr26/arch/x86_64/Kconfig 2008-06-22 17:26:29.000000000 +0200
@@ -573,6 +573,8 @@ config CC_STACKPROTECTOR_ALL
functions that use large-ish on-stack buffers. By enabling
this option, GCC will be asked to do this for ALL functions.
@@ -187,8 +192,8 @@
source kernel/Kconfig.hz
config REORDER
---- linux-2.6.19.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2006-11-30 13:07:25.000000000 +0100
-+++ linux-2.6.19.perfctr26/arch/x86_64/kernel/entry.S 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2008-06-22 17:20:36.000000000 +0200
++++ linux-2.6.19.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 17:26:29.000000000 +0200
@@ -713,6 +713,12 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
END(spurious_interrupt)
@@ -202,8 +207,8 @@
/*
* Exception entry points.
*/
---- linux-2.6.19.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2006-11-30 13:07:25.000000000 +0100
-+++ linux-2.6.19.perfctr26/arch/x86_64/kernel/i8259.c 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2008-06-22 17:20:36.000000000 +0200
++++ linux-2.6.19.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 17:26:29.000000000 +0200
@@ -22,6 +22,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -221,8 +226,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.19.perfctr26/arch/x86_64/kernel/process.c.~1~ 2006-11-30 13:07:25.000000000 +0100
-+++ linux-2.6.19.perfctr26/arch/x86_64/kernel/process.c 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/arch/x86_64/kernel/process.c.~1~ 2008-06-22 17:20:36.000000000 +0200
++++ linux-2.6.19.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 17:26:29.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/interrupt.h>
#include <linux/delay.h>
@@ -258,8 +263,8 @@
return prev_p;
}
---- linux-2.6.19.perfctr26/drivers/Makefile.~1~ 2006-11-30 13:07:25.000000000 +0100
-+++ linux-2.6.19.perfctr26/drivers/Makefile 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/drivers/Makefile.~1~ 2008-06-22 17:20:36.000000000 +0200
++++ linux-2.6.19.perfctr26/drivers/Makefile 2008-06-22 17:26:29.000000000 +0200
@@ -72,6 +72,7 @@ obj-$(CONFIG_NEW_LEDS) += leds/
obj-$(CONFIG_INFINIBAND) += infiniband/
obj-$(CONFIG_IPATH_CORE) += infiniband/
@@ -268,8 +273,26 @@
obj-y += firmware/
obj-$(CONFIG_CRYPTO) += crypto/
obj-$(CONFIG_SUPERH) += sh/
---- linux-2.6.19.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2004-05-10 11:14:37.000000000 +0200
-+++ linux-2.6.19.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/fs/exec.c.~1~ 2008-06-22 17:20:37.000000000 +0200
++++ linux-2.6.19.perfctr26/fs/exec.c 2008-06-22 17:26:36.000000000 +0200
+@@ -49,6 +49,7 @@
+ #include <linux/tsacct_kern.h>
+ #include <linux/cn_proc.h>
+ #include <linux/audit.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -872,6 +873,7 @@ int flush_old_exec(struct linux_binprm *
+ set_task_comm(current, tcomm);
+
+ current->flags &= ~PF_RANDOMIZE;
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ /* Set the new mm task size. We have to do that late because it may
+--- linux-2.6.19.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.19.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 17:26:29.000000000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -288,8 +311,8 @@
#define TIMER_IRQ 0
---- linux-2.6.19.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2004-01-09 13:19:11.000000000 +0100
-+++ linux-2.6.19.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.19.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 17:26:29.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -308,8 +331,8 @@
#define TIMER_IRQ 0
---- linux-2.6.19.perfctr26/include/asm-i386/processor.h.~1~ 2006-11-30 13:07:30.000000000 +0100
-+++ linux-2.6.19.perfctr26/include/asm-i386/processor.h 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/include/asm-i386/processor.h.~1~ 2008-06-22 17:20:37.000000000 +0200
++++ linux-2.6.19.perfctr26/include/asm-i386/processor.h 2008-06-22 17:26:29.000000000 +0200
@@ -467,6 +467,8 @@ struct thread_struct {
unsigned long iopl;
/* max allowed port in the bitmap, in bytes: */
@@ -319,8 +342,8 @@
};
#define INIT_THREAD { \
---- linux-2.6.19.perfctr26/include/asm-i386/system.h.~1~ 2006-11-30 13:07:30.000000000 +0100
-+++ linux-2.6.19.perfctr26/include/asm-i386/system.h 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/include/asm-i386/system.h.~1~ 2008-06-22 17:20:37.000000000 +0200
++++ linux-2.6.19.perfctr26/include/asm-i386/system.h 2008-06-22 17:26:29.000000000 +0200
@@ -17,6 +17,7 @@ extern struct task_struct * FASTCALL(__s
*/
#define switch_to(prev,next,last) do { \
@@ -329,8 +352,8 @@
asm volatile("pushfl\n\t" /* Save flags */ \
"pushl %%ebp\n\t" \
"movl %%esp,%0\n\t" /* save ESP */ \
---- linux-2.6.19.perfctr26/include/asm-powerpc/processor.h.~1~ 2006-11-30 13:07:31.000000000 +0100
-+++ linux-2.6.19.perfctr26/include/asm-powerpc/processor.h 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/include/asm-powerpc/processor.h.~1~ 2008-06-22 17:20:37.000000000 +0200
++++ linux-2.6.19.perfctr26/include/asm-powerpc/processor.h 2008-06-22 17:26:29.000000000 +0200
@@ -170,6 +170,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
@@ -341,8 +364,8 @@
};
#define ARCH_MIN_TASKALIGN 16
---- linux-2.6.19.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2006-11-30 13:07:31.000000000 +0100
-+++ linux-2.6.19.perfctr26/include/asm-x86_64/hw_irq.h 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2008-06-22 17:08:54.000000000 +0200
++++ linux-2.6.19.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 17:26:29.000000000 +0200
@@ -63,14 +63,15 @@
* sources per level' errata.
*/
@@ -361,8 +384,8 @@
#ifndef __ASSEMBLY__
---- linux-2.6.19.perfctr26/include/asm-x86_64/irq.h.~1~ 2006-11-30 13:07:31.000000000 +0100
-+++ linux-2.6.19.perfctr26/include/asm-x86_64/irq.h 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/include/asm-x86_64/irq.h.~1~ 2008-06-22 15:56:55.000000000 +0200
++++ linux-2.6.19.perfctr26/include/asm-x86_64/irq.h 2008-06-22 17:26:29.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -372,8 +395,8 @@
#define NR_IRQS (NR_VECTORS + (32 *NR_CPUS))
#define NR_IRQ_VECTORS NR_IRQS
---- linux-2.6.19.perfctr26/include/asm-x86_64/processor.h.~1~ 2006-11-30 13:07:31.000000000 +0100
-+++ linux-2.6.19.perfctr26/include/asm-x86_64/processor.h 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/include/asm-x86_64/processor.h.~1~ 2008-06-22 17:20:37.000000000 +0200
++++ linux-2.6.19.perfctr26/include/asm-x86_64/processor.h 2008-06-22 17:26:29.000000000 +0200
@@ -274,6 +274,8 @@ struct thread_struct {
unsigned io_bitmap_max;
/* cached TLS descriptors. */
@@ -383,8 +406,8 @@
} __attribute__((aligned(16)));
#define INIT_THREAD { \
---- linux-2.6.19.perfctr26/include/asm-x86_64/system.h.~1~ 2006-11-30 13:07:31.000000000 +0100
-+++ linux-2.6.19.perfctr26/include/asm-x86_64/system.h 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/include/asm-x86_64/system.h.~1~ 2008-06-22 16:44:02.000000000 +0200
++++ linux-2.6.19.perfctr26/include/asm-x86_64/system.h 2008-06-22 17:26:29.000000000 +0200
@@ -21,7 +21,8 @@
,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
@@ -405,8 +428,8 @@
extern void load_gs_index(unsigned);
---- linux-2.6.19.perfctr26/kernel/exit.c.~1~ 2006-11-30 13:07:31.000000000 +0100
-+++ linux-2.6.19.perfctr26/kernel/exit.c 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/kernel/exit.c.~1~ 2008-06-22 17:20:37.000000000 +0200
++++ linux-2.6.19.perfctr26/kernel/exit.c 2008-06-22 17:26:29.000000000 +0200
@@ -27,6 +27,7 @@
#include <linux/mount.h>
#include <linux/proc_fs.h>
@@ -423,8 +446,8 @@
sched_exit(p);
write_unlock_irq(&tasklist_lock);
proc_flush_task(p);
---- linux-2.6.19.perfctr26/kernel/sched.c.~1~ 2006-11-30 13:07:31.000000000 +0100
-+++ linux-2.6.19.perfctr26/kernel/sched.c 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/kernel/sched.c.~1~ 2008-06-22 17:20:37.000000000 +0200
++++ linux-2.6.19.perfctr26/kernel/sched.c 2008-06-22 17:26:29.000000000 +0200
@@ -45,6 +45,7 @@
#include <linux/cpu.h>
#include <linux/cpuset.h>
@@ -442,8 +465,8 @@
rq = task_rq_lock(p, &flags);
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
---- linux-2.6.19.perfctr26/kernel/timer.c.~1~ 2006-11-30 13:07:31.000000000 +0100
-+++ linux-2.6.19.perfctr26/kernel/timer.c 2006-11-30 13:36:02.000000000 +0100
+--- linux-2.6.19.perfctr26/kernel/timer.c.~1~ 2008-06-22 17:20:37.000000000 +0200
++++ linux-2.6.19.perfctr26/kernel/timer.c 2008-06-22 17:26:29.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/jiffies.h>
#include <linux/posix-timers.h>
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.20 b/src/perfctr-2.6.x/patches/patch-kernel-2.6.20
index e986aec5833cfefc4377be495eef9b60a13e2fc5..19fd4de7422b315fa7f1fc5dd9a199976b8a590b 100644
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.20
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.20
@@ -1,19 +1,20 @@
---- linux-2.6.20.perfctr26/CREDITS.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/CREDITS 2007-02-10 16:56:57.000000000 +0100
+--- linux-2.6.20.perfctr26/CREDITS.~1~ 2008-06-22 17:08:52.000000000 +0200
++++ linux-2.6.20.perfctr26/CREDITS 2008-06-22 17:10:48.000000000 +0200
@@ -2668,9 +2668,10 @@ S: Ottawa, Ontario
S: Canada K2P 0X8
N: Mikael Pettersson
-E: mikpe@csd.uu.se
+-W: http://www.csd.uu.se/~mikpe/
+E: mikpe@it.uu.se
- W: http://www.csd.uu.se/~mikpe/
++W: http://user.it.uu.se/~mikpe/
D: Miscellaneous fixes
+D: Performance-monitoring counters driver
N: Reed H. Petty
E: rhp@draper.net
---- linux-2.6.20.perfctr26/Documentation/ioctl-number.txt.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/Documentation/ioctl-number.txt 2007-02-10 16:57:55.000000000 +0100
+--- linux-2.6.20.perfctr26/Documentation/ioctl-number.txt.~1~ 2008-06-22 17:08:52.000000000 +0200
++++ linux-2.6.20.perfctr26/Documentation/ioctl-number.txt 2008-06-22 17:10:42.000000000 +0200
@@ -187,6 +187,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -23,8 +24,8 @@
0xDD 00-3F ZFCP device driver see drivers/s390/scsi/
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
---- linux-2.6.20.perfctr26/MAINTAINERS.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/MAINTAINERS 2007-02-10 16:57:05.000000000 +0100
+--- linux-2.6.20.perfctr26/MAINTAINERS.~1~ 2008-06-22 17:08:52.000000000 +0200
++++ linux-2.6.20.perfctr26/MAINTAINERS 2008-06-22 17:10:48.000000000 +0200
@@ -2577,6 +2577,12 @@ M: nagar@watson.ibm.com
L: linux-kernel@vger.kernel.org
S: Maintained
@@ -32,14 +33,14 @@
+PERFORMANCE-MONITORING COUNTERS DRIVER
+P: Mikael Pettersson
+M: mikpe@it.uu.se
-+W: http://www.csd.uu.se/~mikpe/linux/perfctr/
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
+S: Maintained
+
PERSONALITY HANDLING
P: Christoph Hellwig
M: hch@infradead.org
---- linux-2.6.20.perfctr26/arch/arm/Kconfig.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/arch/arm/Kconfig 2007-02-10 16:56:38.000000000 +0100
+--- linux-2.6.20.perfctr26/arch/arm/Kconfig.~1~ 2008-06-22 17:08:52.000000000 +0200
++++ linux-2.6.20.perfctr26/arch/arm/Kconfig 2008-06-22 17:10:42.000000000 +0200
@@ -398,6 +398,10 @@ config IWMMXT
Enable support for iWMMXt context switching at run time if
running on a CPU that supports it.
@@ -51,8 +52,8 @@
# bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
config XSCALE_PMU
bool
---- linux-2.6.20.perfctr26/arch/arm/kernel/process.c.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/arch/arm/kernel/process.c 2007-02-10 16:56:38.000000000 +0100
+--- linux-2.6.20.perfctr26/arch/arm/kernel/process.c.~1~ 2008-06-22 17:08:52.000000000 +0200
++++ linux-2.6.20.perfctr26/arch/arm/kernel/process.c 2008-06-22 17:10:42.000000000 +0200
@@ -28,6 +28,7 @@
#include <linux/cpu.h>
#include <linux/elfcore.h>
@@ -78,8 +79,8 @@
return 0;
}
---- linux-2.6.20.perfctr26/arch/i386/Kconfig.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/arch/i386/Kconfig 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/arch/i386/Kconfig.~1~ 2008-06-22 17:08:53.000000000 +0200
++++ linux-2.6.20.perfctr26/arch/i386/Kconfig 2008-06-22 17:10:42.000000000 +0200
@@ -745,6 +745,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -89,8 +90,8 @@
source kernel/Kconfig.hz
config KEXEC
---- linux-2.6.20.perfctr26/arch/i386/kernel/entry.S.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/arch/i386/kernel/entry.S 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/arch/i386/kernel/entry.S.~1~ 2008-06-22 17:08:53.000000000 +0200
++++ linux-2.6.20.perfctr26/arch/i386/kernel/entry.S 2008-06-22 17:10:42.000000000 +0200
@@ -626,6 +626,22 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -114,8 +115,8 @@
KPROBE_ENTRY(page_fault)
RING0_EC_FRAME
pushl $do_page_fault
---- linux-2.6.20.perfctr26/arch/i386/kernel/i8259.c.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/arch/i386/kernel/i8259.c 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/arch/i386/kernel/i8259.c.~1~ 2008-06-22 17:08:53.000000000 +0200
++++ linux-2.6.20.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 17:10:42.000000000 +0200
@@ -22,6 +22,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -133,8 +134,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.20.perfctr26/arch/i386/kernel/process.c.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/arch/i386/kernel/process.c 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/arch/i386/kernel/process.c.~1~ 2008-06-22 17:08:53.000000000 +0200
++++ linux-2.6.20.perfctr26/arch/i386/kernel/process.c 2008-06-22 17:10:42.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -169,8 +170,8 @@
return prev_p;
}
---- linux-2.6.20.perfctr26/arch/powerpc/Kconfig.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/arch/powerpc/Kconfig 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/arch/powerpc/Kconfig.~1~ 2008-06-22 17:08:53.000000000 +0200
++++ linux-2.6.20.perfctr26/arch/powerpc/Kconfig 2008-06-22 17:10:42.000000000 +0200
@@ -356,6 +356,11 @@ config NOT_COHERENT_CACHE
bool
depends on 4xx || 8xx || E200
@@ -183,8 +184,8 @@
endmenu
source "init/Kconfig"
---- linux-2.6.20.perfctr26/arch/powerpc/kernel/process.c.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/arch/powerpc/kernel/process.c 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/arch/powerpc/kernel/process.c.~1~ 2008-06-22 17:08:53.000000000 +0200
++++ linux-2.6.20.perfctr26/arch/powerpc/kernel/process.c 2008-06-22 17:10:42.000000000 +0200
@@ -31,6 +31,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -220,8 +221,8 @@
return 0;
}
---- linux-2.6.20.perfctr26/arch/x86_64/Kconfig.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/arch/x86_64/Kconfig 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/arch/x86_64/Kconfig.~1~ 2008-06-22 17:08:53.000000000 +0200
++++ linux-2.6.20.perfctr26/arch/x86_64/Kconfig 2008-06-22 17:10:42.000000000 +0200
@@ -607,6 +607,8 @@ config CC_STACKPROTECTOR_ALL
functions that use large-ish on-stack buffers. By enabling
this option, GCC will be asked to do this for ALL functions.
@@ -231,8 +232,8 @@
source kernel/Kconfig.hz
config REORDER
---- linux-2.6.20.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/arch/x86_64/kernel/entry.S 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2008-06-22 17:08:53.000000000 +0200
++++ linux-2.6.20.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 17:10:42.000000000 +0200
@@ -689,6 +689,12 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
END(spurious_interrupt)
@@ -246,8 +247,8 @@
/*
* Exception entry points.
*/
---- linux-2.6.20.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/arch/x86_64/kernel/i8259.c 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2008-06-22 17:08:53.000000000 +0200
++++ linux-2.6.20.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 17:10:42.000000000 +0200
@@ -22,6 +22,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -265,8 +266,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.20.perfctr26/arch/x86_64/kernel/process.c.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/arch/x86_64/kernel/process.c 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/arch/x86_64/kernel/process.c.~1~ 2008-06-22 17:08:53.000000000 +0200
++++ linux-2.6.20.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 17:10:42.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/interrupt.h>
#include <linux/delay.h>
@@ -302,8 +303,8 @@
return prev_p;
}
---- linux-2.6.20.perfctr26/drivers/Makefile.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/drivers/Makefile 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/drivers/Makefile.~1~ 2008-06-22 17:08:53.000000000 +0200
++++ linux-2.6.20.perfctr26/drivers/Makefile 2008-06-22 17:10:42.000000000 +0200
@@ -73,6 +73,7 @@ obj-$(CONFIG_NEW_LEDS) += leds/
obj-$(CONFIG_INFINIBAND) += infiniband/
obj-$(CONFIG_IPATH_CORE) += infiniband/
@@ -312,8 +313,26 @@
obj-y += firmware/
obj-$(CONFIG_CRYPTO) += crypto/
obj-$(CONFIG_SUPERH) += sh/
---- linux-2.6.20.perfctr26/include/asm-arm/processor.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/include/asm-arm/processor.h 2007-02-10 16:56:38.000000000 +0100
+--- linux-2.6.20.perfctr26/fs/exec.c.~1~ 2008-06-22 17:08:54.000000000 +0200
++++ linux-2.6.20.perfctr26/fs/exec.c 2008-06-22 17:10:48.000000000 +0200
+@@ -50,6 +50,7 @@
+ #include <linux/tsacct_kern.h>
+ #include <linux/cn_proc.h>
+ #include <linux/audit.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -873,6 +874,7 @@ int flush_old_exec(struct linux_binprm *
+ set_task_comm(current, tcomm);
+
+ current->flags &= ~PF_RANDOMIZE;
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ /* Set the new mm task size. We have to do that late because it may
+--- linux-2.6.20.perfctr26/include/asm-arm/processor.h.~1~ 2008-06-22 15:42:33.000000000 +0200
++++ linux-2.6.20.perfctr26/include/asm-arm/processor.h 2008-06-22 17:10:42.000000000 +0200
@@ -44,6 +44,10 @@ struct thread_struct {
unsigned long error_code;
/* debugging */
@@ -325,8 +344,8 @@
};
#define INIT_THREAD { }
---- linux-2.6.20.perfctr26/include/asm-arm/system.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/include/asm-arm/system.h 2007-02-10 16:56:38.000000000 +0100
+--- linux-2.6.20.perfctr26/include/asm-arm/system.h.~1~ 2008-06-22 17:08:54.000000000 +0200
++++ linux-2.6.20.perfctr26/include/asm-arm/system.h 2008-06-22 17:10:42.000000000 +0200
@@ -220,7 +220,9 @@ extern struct task_struct *__switch_to(s
#define switch_to(prev,next,last) \
@@ -337,8 +356,8 @@
} while (0)
/*
---- linux-2.6.20.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.20.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 17:10:42.000000000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -357,8 +376,8 @@
#define TIMER_IRQ 0
---- linux-2.6.20.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.20.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 17:10:42.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -377,8 +396,8 @@
#define TIMER_IRQ 0
---- linux-2.6.20.perfctr26/include/asm-i386/processor.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/include/asm-i386/processor.h 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/include/asm-i386/processor.h.~1~ 2008-06-22 17:08:54.000000000 +0200
++++ linux-2.6.20.perfctr26/include/asm-i386/processor.h 2008-06-22 17:10:42.000000000 +0200
@@ -418,6 +418,8 @@ struct thread_struct {
unsigned long iopl;
/* max allowed port in the bitmap, in bytes: */
@@ -388,8 +407,8 @@
};
#define INIT_THREAD { \
---- linux-2.6.20.perfctr26/include/asm-i386/system.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/include/asm-i386/system.h 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/include/asm-i386/system.h.~1~ 2008-06-22 16:44:00.000000000 +0200
++++ linux-2.6.20.perfctr26/include/asm-i386/system.h 2008-06-22 17:10:42.000000000 +0200
@@ -17,6 +17,7 @@ extern struct task_struct * FASTCALL(__s
*/
#define switch_to(prev,next,last) do { \
@@ -398,8 +417,8 @@
asm volatile("pushfl\n\t" /* Save flags */ \
"pushl %%ebp\n\t" \
"movl %%esp,%0\n\t" /* save ESP */ \
---- linux-2.6.20.perfctr26/include/asm-powerpc/processor.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/include/asm-powerpc/processor.h 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/include/asm-powerpc/processor.h.~1~ 2008-06-22 16:44:00.000000000 +0200
++++ linux-2.6.20.perfctr26/include/asm-powerpc/processor.h 2008-06-22 17:10:42.000000000 +0200
@@ -166,6 +166,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
@@ -410,8 +429,8 @@
};
#define ARCH_MIN_TASKALIGN 16
---- linux-2.6.20.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/include/asm-x86_64/hw_irq.h 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2008-06-22 17:08:54.000000000 +0200
++++ linux-2.6.20.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 17:10:42.000000000 +0200
@@ -63,14 +63,15 @@
* sources per level' errata.
*/
@@ -430,8 +449,8 @@
#ifndef __ASSEMBLY__
---- linux-2.6.20.perfctr26/include/asm-x86_64/irq.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/include/asm-x86_64/irq.h 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/include/asm-x86_64/irq.h.~1~ 2008-06-22 15:56:55.000000000 +0200
++++ linux-2.6.20.perfctr26/include/asm-x86_64/irq.h 2008-06-22 17:10:42.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -441,8 +460,8 @@
#define NR_IRQS (NR_VECTORS + (32 *NR_CPUS))
#define NR_IRQ_VECTORS NR_IRQS
---- linux-2.6.20.perfctr26/include/asm-x86_64/processor.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/include/asm-x86_64/processor.h 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/include/asm-x86_64/processor.h.~1~ 2008-06-22 16:44:02.000000000 +0200
++++ linux-2.6.20.perfctr26/include/asm-x86_64/processor.h 2008-06-22 17:10:42.000000000 +0200
@@ -274,6 +274,8 @@ struct thread_struct {
unsigned io_bitmap_max;
/* cached TLS descriptors. */
@@ -452,8 +471,8 @@
} __attribute__((aligned(16)));
#define INIT_THREAD { \
---- linux-2.6.20.perfctr26/include/asm-x86_64/system.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/include/asm-x86_64/system.h 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/include/asm-x86_64/system.h.~1~ 2008-06-22 16:44:02.000000000 +0200
++++ linux-2.6.20.perfctr26/include/asm-x86_64/system.h 2008-06-22 17:10:42.000000000 +0200
@@ -21,7 +21,8 @@
,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
@@ -474,8 +493,8 @@
extern void load_gs_index(unsigned);
---- linux-2.6.20.perfctr26/kernel/exit.c.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/kernel/exit.c 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/kernel/exit.c.~1~ 2008-06-22 17:08:54.000000000 +0200
++++ linux-2.6.20.perfctr26/kernel/exit.c 2008-06-22 17:10:42.000000000 +0200
@@ -28,6 +28,7 @@
#include <linux/mount.h>
#include <linux/proc_fs.h>
@@ -492,8 +511,8 @@
sched_exit(p);
write_unlock_irq(&tasklist_lock);
proc_flush_task(p);
---- linux-2.6.20.perfctr26/kernel/sched.c.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/kernel/sched.c 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/kernel/sched.c.~1~ 2008-06-22 17:08:55.000000000 +0200
++++ linux-2.6.20.perfctr26/kernel/sched.c 2008-06-22 17:10:42.000000000 +0200
@@ -45,6 +45,7 @@
#include <linux/cpu.h>
#include <linux/cpuset.h>
@@ -511,8 +530,8 @@
rq = task_rq_lock(p, &flags);
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
---- linux-2.6.20.perfctr26/kernel/timer.c.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.20.perfctr26/kernel/timer.c 2007-02-10 16:55:42.000000000 +0100
+--- linux-2.6.20.perfctr26/kernel/timer.c.~1~ 2008-06-22 17:08:55.000000000 +0200
++++ linux-2.6.20.perfctr26/kernel/timer.c 2008-06-22 17:10:42.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/jiffies.h>
#include <linux/posix-timers.h>
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.21 b/src/perfctr-2.6.x/patches/patch-kernel-2.6.21
index 19da4eb52cd28a6315faf813470221a13b33482b..f194b829818fdda4293f68b10dea15a2e98796fe 100644
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.21
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.21
@@ -1,15 +1,18 @@
---- linux-2.6.21.perfctr26/CREDITS.~1~ 2007-04-26 14:59:30.000000000 +0200
-+++ linux-2.6.21.perfctr26/CREDITS 2007-04-26 15:20:44.000000000 +0200
-@@ -2681,6 +2681,7 @@ N: Mikael Pettersson
+--- linux-2.6.21.perfctr26/CREDITS.~1~ 2008-06-22 16:43:58.000000000 +0200
++++ linux-2.6.21.perfctr26/CREDITS 2008-06-22 16:46:48.000000000 +0200
+@@ -2679,8 +2679,9 @@ S: Canada K2P 0X8
+
+ N: Mikael Pettersson
E: mikpe@it.uu.se
- W: http://www.csd.uu.se/~mikpe/
+-W: http://www.csd.uu.se/~mikpe/
++W: http://user.it.uu.se/~mikpe/
D: Miscellaneous fixes
+D: Performance-monitoring counters driver
N: Reed H. Petty
E: rhp@draper.net
---- linux-2.6.21.perfctr26/Documentation/ioctl-number.txt.~1~ 2007-04-26 14:59:30.000000000 +0200
-+++ linux-2.6.21.perfctr26/Documentation/ioctl-number.txt 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/Documentation/ioctl-number.txt.~1~ 2008-06-22 16:43:58.000000000 +0200
++++ linux-2.6.21.perfctr26/Documentation/ioctl-number.txt 2008-06-22 16:46:44.000000000 +0200
@@ -186,6 +186,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -19,8 +22,8 @@
0xDD 00-3F ZFCP device driver see drivers/s390/scsi/
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
---- linux-2.6.21.perfctr26/MAINTAINERS.~1~ 2007-04-26 14:59:30.000000000 +0200
-+++ linux-2.6.21.perfctr26/MAINTAINERS 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/MAINTAINERS.~1~ 2008-06-22 16:43:58.000000000 +0200
++++ linux-2.6.21.perfctr26/MAINTAINERS 2008-06-22 16:46:48.000000000 +0200
@@ -2641,6 +2641,12 @@ M: nagar@watson.ibm.com
L: linux-kernel@vger.kernel.org
S: Maintained
@@ -28,14 +31,14 @@
+PERFORMANCE-MONITORING COUNTERS DRIVER
+P: Mikael Pettersson
+M: mikpe@it.uu.se
-+W: http://www.csd.uu.se/~mikpe/linux/perfctr/
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
+S: Maintained
+
PERSONALITY HANDLING
P: Christoph Hellwig
M: hch@infradead.org
---- linux-2.6.21.perfctr26/arch/arm/Kconfig.~1~ 2007-04-26 14:59:30.000000000 +0200
-+++ linux-2.6.21.perfctr26/arch/arm/Kconfig 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/arch/arm/Kconfig.~1~ 2008-06-22 16:43:58.000000000 +0200
++++ linux-2.6.21.perfctr26/arch/arm/Kconfig 2008-06-22 16:46:44.000000000 +0200
@@ -444,6 +444,10 @@ config IWMMXT
Enable support for iWMMXt context switching at run time if
running on a CPU that supports it.
@@ -47,8 +50,8 @@
# bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
config XSCALE_PMU
bool
---- linux-2.6.21.perfctr26/arch/arm/kernel/process.c.~1~ 2007-04-26 14:59:30.000000000 +0200
-+++ linux-2.6.21.perfctr26/arch/arm/kernel/process.c 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/arch/arm/kernel/process.c.~1~ 2008-06-22 16:43:58.000000000 +0200
++++ linux-2.6.21.perfctr26/arch/arm/kernel/process.c 2008-06-22 16:46:44.000000000 +0200
@@ -28,6 +28,7 @@
#include <linux/cpu.h>
#include <linux/elfcore.h>
@@ -74,8 +77,8 @@
return 0;
}
---- linux-2.6.21.perfctr26/arch/i386/Kconfig.~1~ 2007-04-26 14:59:30.000000000 +0200
-+++ linux-2.6.21.perfctr26/arch/i386/Kconfig 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/arch/i386/Kconfig.~1~ 2008-06-22 16:43:59.000000000 +0200
++++ linux-2.6.21.perfctr26/arch/i386/Kconfig 2008-06-22 16:46:44.000000000 +0200
@@ -773,6 +773,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -85,8 +88,8 @@
source kernel/Kconfig.hz
config KEXEC
---- linux-2.6.21.perfctr26/arch/i386/kernel/entry.S.~1~ 2007-04-26 14:59:30.000000000 +0200
-+++ linux-2.6.21.perfctr26/arch/i386/kernel/entry.S 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/arch/i386/kernel/entry.S.~1~ 2008-06-22 16:43:59.000000000 +0200
++++ linux-2.6.21.perfctr26/arch/i386/kernel/entry.S 2008-06-22 16:46:44.000000000 +0200
@@ -648,6 +648,23 @@ ENDPROC(name)
BUILD_INTERRUPT(apic_vmi_timer_interrupt,LOCAL_TIMER_VECTOR)
#endif
@@ -111,8 +114,8 @@
KPROBE_ENTRY(page_fault)
RING0_EC_FRAME
pushl $do_page_fault
---- linux-2.6.21.perfctr26/arch/i386/kernel/i8259.c.~1~ 2007-04-26 14:59:30.000000000 +0200
-+++ linux-2.6.21.perfctr26/arch/i386/kernel/i8259.c 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/arch/i386/kernel/i8259.c.~1~ 2008-06-22 16:43:59.000000000 +0200
++++ linux-2.6.21.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 16:46:44.000000000 +0200
@@ -22,6 +22,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -130,8 +133,8 @@
/*
* External FPU? Set up irq13 if so, for
* original braindamaged IBM FERR coupling.
---- linux-2.6.21.perfctr26/arch/i386/kernel/process.c.~1~ 2007-04-26 14:59:30.000000000 +0200
-+++ linux-2.6.21.perfctr26/arch/i386/kernel/process.c 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/arch/i386/kernel/process.c.~1~ 2008-06-22 16:43:59.000000000 +0200
++++ linux-2.6.21.perfctr26/arch/i386/kernel/process.c 2008-06-22 16:46:44.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -166,8 +169,8 @@
return prev_p;
}
---- linux-2.6.21.perfctr26/arch/powerpc/Kconfig.~1~ 2007-04-26 14:59:30.000000000 +0200
-+++ linux-2.6.21.perfctr26/arch/powerpc/Kconfig 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/arch/powerpc/Kconfig.~1~ 2008-06-22 16:43:59.000000000 +0200
++++ linux-2.6.21.perfctr26/arch/powerpc/Kconfig 2008-06-22 16:46:44.000000000 +0200
@@ -363,6 +363,11 @@ config NOT_COHERENT_CACHE
bool
depends on 4xx || 8xx || E200
@@ -180,8 +183,8 @@
endmenu
source "init/Kconfig"
---- linux-2.6.21.perfctr26/arch/powerpc/kernel/process.c.~1~ 2007-04-26 14:59:30.000000000 +0200
-+++ linux-2.6.21.perfctr26/arch/powerpc/kernel/process.c 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/arch/powerpc/kernel/process.c.~1~ 2008-06-22 16:43:59.000000000 +0200
++++ linux-2.6.21.perfctr26/arch/powerpc/kernel/process.c 2008-06-22 16:46:44.000000000 +0200
@@ -31,6 +31,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -217,8 +220,8 @@
return 0;
}
---- linux-2.6.21.perfctr26/arch/x86_64/Kconfig.~1~ 2007-04-26 14:59:30.000000000 +0200
-+++ linux-2.6.21.perfctr26/arch/x86_64/Kconfig 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/arch/x86_64/Kconfig.~1~ 2008-06-22 16:43:59.000000000 +0200
++++ linux-2.6.21.perfctr26/arch/x86_64/Kconfig 2008-06-22 16:46:44.000000000 +0200
@@ -625,6 +625,8 @@ config CC_STACKPROTECTOR_ALL
functions that use large-ish on-stack buffers. By enabling
this option, GCC will be asked to do this for ALL functions.
@@ -228,8 +231,8 @@
source kernel/Kconfig.hz
config REORDER
---- linux-2.6.21.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2007-04-26 14:59:30.000000000 +0200
-+++ linux-2.6.21.perfctr26/arch/x86_64/kernel/entry.S 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2008-06-22 16:43:59.000000000 +0200
++++ linux-2.6.21.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 16:46:44.000000000 +0200
@@ -692,6 +692,12 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
END(spurious_interrupt)
@@ -243,8 +246,8 @@
/*
* Exception entry points.
*/
---- linux-2.6.21.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2007-04-26 14:59:30.000000000 +0200
-+++ linux-2.6.21.perfctr26/arch/x86_64/kernel/i8259.c 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2008-06-22 16:43:59.000000000 +0200
++++ linux-2.6.21.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 16:46:44.000000000 +0200
@@ -22,6 +22,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -262,8 +265,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.21.perfctr26/arch/x86_64/kernel/process.c.~1~ 2007-04-26 14:59:30.000000000 +0200
-+++ linux-2.6.21.perfctr26/arch/x86_64/kernel/process.c 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/arch/x86_64/kernel/process.c.~1~ 2008-06-22 16:43:59.000000000 +0200
++++ linux-2.6.21.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 16:46:44.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/interrupt.h>
#include <linux/delay.h>
@@ -299,8 +302,8 @@
return prev_p;
}
---- linux-2.6.21.perfctr26/drivers/Makefile.~1~ 2007-04-26 14:59:30.000000000 +0200
-+++ linux-2.6.21.perfctr26/drivers/Makefile 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/drivers/Makefile.~1~ 2008-06-22 16:43:59.000000000 +0200
++++ linux-2.6.21.perfctr26/drivers/Makefile 2008-06-22 16:46:44.000000000 +0200
@@ -74,6 +74,7 @@ obj-$(CONFIG_NEW_LEDS) += leds/
obj-$(CONFIG_INFINIBAND) += infiniband/
obj-$(CONFIG_IPATH_CORE) += infiniband/
@@ -309,8 +312,26 @@
obj-y += firmware/
obj-$(CONFIG_CRYPTO) += crypto/
obj-$(CONFIG_SUPERH) += sh/
---- linux-2.6.21.perfctr26/include/asm-arm/processor.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.21.perfctr26/include/asm-arm/processor.h 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/fs/exec.c.~1~ 2008-06-22 16:44:00.000000000 +0200
++++ linux-2.6.21.perfctr26/fs/exec.c 2008-06-22 16:46:48.000000000 +0200
+@@ -50,6 +50,7 @@
+ #include <linux/tsacct_kern.h>
+ #include <linux/cn_proc.h>
+ #include <linux/audit.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -871,6 +872,7 @@ int flush_old_exec(struct linux_binprm *
+ set_task_comm(current, tcomm);
+
+ current->flags &= ~PF_RANDOMIZE;
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ /* Set the new mm task size. We have to do that late because it may
+--- linux-2.6.21.perfctr26/include/asm-arm/processor.h.~1~ 2008-06-22 15:42:33.000000000 +0200
++++ linux-2.6.21.perfctr26/include/asm-arm/processor.h 2008-06-22 16:46:44.000000000 +0200
@@ -44,6 +44,10 @@ struct thread_struct {
unsigned long error_code;
/* debugging */
@@ -322,8 +343,8 @@
};
#define INIT_THREAD { }
---- linux-2.6.21.perfctr26/include/asm-arm/system.h.~1~ 2007-04-26 14:59:37.000000000 +0200
-+++ linux-2.6.21.perfctr26/include/asm-arm/system.h 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/include/asm-arm/system.h.~1~ 2008-06-22 16:44:00.000000000 +0200
++++ linux-2.6.21.perfctr26/include/asm-arm/system.h 2008-06-22 16:46:44.000000000 +0200
@@ -246,7 +246,9 @@ extern struct task_struct *__switch_to(s
#define switch_to(prev,next,last) \
@@ -334,8 +355,8 @@
} while (0)
/*
---- linux-2.6.21.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.21.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.21.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 16:46:44.000000000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -354,8 +375,8 @@
#define TIMER_IRQ 0
---- linux-2.6.21.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.21.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.21.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 16:46:44.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -374,8 +395,8 @@
#define TIMER_IRQ 0
---- linux-2.6.21.perfctr26/include/asm-i386/processor.h.~1~ 2007-04-26 14:59:37.000000000 +0200
-+++ linux-2.6.21.perfctr26/include/asm-i386/processor.h 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/include/asm-i386/processor.h.~1~ 2008-06-22 16:44:00.000000000 +0200
++++ linux-2.6.21.perfctr26/include/asm-i386/processor.h 2008-06-22 16:46:44.000000000 +0200
@@ -418,6 +418,8 @@ struct thread_struct {
unsigned long iopl;
/* max allowed port in the bitmap, in bytes: */
@@ -385,8 +406,8 @@
};
#define INIT_THREAD { \
---- linux-2.6.21.perfctr26/include/asm-i386/system.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.21.perfctr26/include/asm-i386/system.h 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/include/asm-i386/system.h.~1~ 2008-06-22 16:44:00.000000000 +0200
++++ linux-2.6.21.perfctr26/include/asm-i386/system.h 2008-06-22 16:46:44.000000000 +0200
@@ -17,6 +17,7 @@ extern struct task_struct * FASTCALL(__s
*/
#define switch_to(prev,next,last) do { \
@@ -395,8 +416,8 @@
asm volatile("pushfl\n\t" /* Save flags */ \
"pushl %%ebp\n\t" \
"movl %%esp,%0\n\t" /* save ESP */ \
---- linux-2.6.21.perfctr26/include/asm-powerpc/processor.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.21.perfctr26/include/asm-powerpc/processor.h 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/include/asm-powerpc/processor.h.~1~ 2008-06-22 16:44:00.000000000 +0200
++++ linux-2.6.21.perfctr26/include/asm-powerpc/processor.h 2008-06-22 16:46:44.000000000 +0200
@@ -166,6 +166,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
@@ -407,8 +428,8 @@
};
#define ARCH_MIN_TASKALIGN 16
---- linux-2.6.21.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2007-04-26 14:59:37.000000000 +0200
-+++ linux-2.6.21.perfctr26/include/asm-x86_64/hw_irq.h 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2008-06-22 16:09:15.000000000 +0200
++++ linux-2.6.21.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 16:46:44.000000000 +0200
@@ -84,14 +84,15 @@
* sources per level' errata.
*/
@@ -427,8 +448,8 @@
#ifndef __ASSEMBLY__
---- linux-2.6.21.perfctr26/include/asm-x86_64/irq.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.21.perfctr26/include/asm-x86_64/irq.h 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/include/asm-x86_64/irq.h.~1~ 2008-06-22 15:56:55.000000000 +0200
++++ linux-2.6.21.perfctr26/include/asm-x86_64/irq.h 2008-06-22 16:46:44.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -438,8 +459,8 @@
#define NR_IRQS (NR_VECTORS + (32 *NR_CPUS))
#define NR_IRQ_VECTORS NR_IRQS
---- linux-2.6.21.perfctr26/include/asm-x86_64/processor.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.21.perfctr26/include/asm-x86_64/processor.h 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/include/asm-x86_64/processor.h.~1~ 2008-06-22 16:44:02.000000000 +0200
++++ linux-2.6.21.perfctr26/include/asm-x86_64/processor.h 2008-06-22 16:46:44.000000000 +0200
@@ -274,6 +274,8 @@ struct thread_struct {
unsigned io_bitmap_max;
/* cached TLS descriptors. */
@@ -449,8 +470,8 @@
} __attribute__((aligned(16)));
#define INIT_THREAD { \
---- linux-2.6.21.perfctr26/include/asm-x86_64/system.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.21.perfctr26/include/asm-x86_64/system.h 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/include/asm-x86_64/system.h.~1~ 2008-06-22 16:44:02.000000000 +0200
++++ linux-2.6.21.perfctr26/include/asm-x86_64/system.h 2008-06-22 16:46:44.000000000 +0200
@@ -21,7 +21,8 @@
,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
@@ -471,8 +492,8 @@
extern void load_gs_index(unsigned);
---- linux-2.6.21.perfctr26/kernel/exit.c.~1~ 2007-04-26 14:59:37.000000000 +0200
-+++ linux-2.6.21.perfctr26/kernel/exit.c 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/kernel/exit.c.~1~ 2008-06-22 16:44:02.000000000 +0200
++++ linux-2.6.21.perfctr26/kernel/exit.c 2008-06-22 16:46:44.000000000 +0200
@@ -28,6 +28,7 @@
#include <linux/mount.h>
#include <linux/proc_fs.h>
@@ -489,8 +510,8 @@
sched_exit(p);
write_unlock_irq(&tasklist_lock);
proc_flush_task(p);
---- linux-2.6.21.perfctr26/kernel/sched.c.~1~ 2007-04-26 14:59:37.000000000 +0200
-+++ linux-2.6.21.perfctr26/kernel/sched.c 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/kernel/sched.c.~1~ 2008-06-22 16:44:02.000000000 +0200
++++ linux-2.6.21.perfctr26/kernel/sched.c 2008-06-22 16:46:44.000000000 +0200
@@ -45,6 +45,7 @@
#include <linux/cpu.h>
#include <linux/cpuset.h>
@@ -508,8 +529,8 @@
rq = task_rq_lock(p, &flags);
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
---- linux-2.6.21.perfctr26/kernel/timer.c.~1~ 2007-04-26 14:59:37.000000000 +0200
-+++ linux-2.6.21.perfctr26/kernel/timer.c 2007-04-26 15:20:44.000000000 +0200
+--- linux-2.6.21.perfctr26/kernel/timer.c.~1~ 2008-06-22 16:44:02.000000000 +0200
++++ linux-2.6.21.perfctr26/kernel/timer.c 2008-06-22 16:46:44.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/jiffies.h>
#include <linux/posix-timers.h>
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.22 b/src/perfctr-2.6.x/patches/patch-kernel-2.6.22
index 45acb1c10dae2ae6e738e3e9ded653a42e9b0624..92d1b6138ca1bdd284ad0d78304ff5b1ee8fccc4 100644
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.22
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.22
@@ -1,15 +1,18 @@
---- linux-2.6.22.perfctr26/CREDITS.~1~ 2007-07-09 22:01:30.000000000 +0200
-+++ linux-2.6.22.perfctr26/CREDITS 2007-07-09 22:07:45.000000000 +0200
-@@ -2687,6 +2687,7 @@ N: Mikael Pettersson
+--- linux-2.6.22.perfctr26/CREDITS.~1~ 2008-06-22 16:09:12.000000000 +0200
++++ linux-2.6.22.perfctr26/CREDITS 2008-06-22 16:16:39.000000000 +0200
+@@ -2685,8 +2685,9 @@ S: Canada K2P 0X8
+
+ N: Mikael Pettersson
E: mikpe@it.uu.se
- W: http://www.csd.uu.se/~mikpe/
+-W: http://www.csd.uu.se/~mikpe/
++W: http://user.it.uu.se/~mikpe/
D: Miscellaneous fixes
+D: Performance-monitoring counters driver
N: Reed H. Petty
E: rhp@draper.net
---- linux-2.6.22.perfctr26/Documentation/ioctl-number.txt.~1~ 2007-07-09 22:01:30.000000000 +0200
-+++ linux-2.6.22.perfctr26/Documentation/ioctl-number.txt 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/Documentation/ioctl-number.txt.~1~ 2008-06-22 16:09:12.000000000 +0200
++++ linux-2.6.22.perfctr26/Documentation/ioctl-number.txt 2008-06-22 16:16:32.000000000 +0200
@@ -187,6 +187,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -19,8 +22,8 @@
0xDD 00-3F ZFCP device driver see drivers/s390/scsi/
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
---- linux-2.6.22.perfctr26/MAINTAINERS.~1~ 2007-07-09 22:01:30.000000000 +0200
-+++ linux-2.6.22.perfctr26/MAINTAINERS 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/MAINTAINERS.~1~ 2008-06-22 16:09:12.000000000 +0200
++++ linux-2.6.22.perfctr26/MAINTAINERS 2008-06-22 16:16:39.000000000 +0200
@@ -2844,6 +2844,12 @@ M: nagar@watson.ibm.com
L: linux-kernel@vger.kernel.org
S: Maintained
@@ -28,14 +31,14 @@
+PERFORMANCE-MONITORING COUNTERS DRIVER
+P: Mikael Pettersson
+M: mikpe@it.uu.se
-+W: http://www.csd.uu.se/~mikpe/linux/perfctr/
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
+S: Maintained
+
PERSONALITY HANDLING
P: Christoph Hellwig
M: hch@infradead.org
---- linux-2.6.22.perfctr26/arch/arm/Kconfig.~1~ 2007-07-09 22:01:30.000000000 +0200
-+++ linux-2.6.22.perfctr26/arch/arm/Kconfig 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/arch/arm/Kconfig.~1~ 2008-06-22 16:09:12.000000000 +0200
++++ linux-2.6.22.perfctr26/arch/arm/Kconfig 2008-06-22 16:16:32.000000000 +0200
@@ -476,6 +476,10 @@ config IWMMXT
Enable support for iWMMXt context switching at run time if
running on a CPU that supports it.
@@ -47,8 +50,8 @@
# bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
config XSCALE_PMU
bool
---- linux-2.6.22.perfctr26/arch/arm/kernel/process.c.~1~ 2007-07-09 22:01:30.000000000 +0200
-+++ linux-2.6.22.perfctr26/arch/arm/kernel/process.c 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/arch/arm/kernel/process.c.~1~ 2008-06-22 16:09:12.000000000 +0200
++++ linux-2.6.22.perfctr26/arch/arm/kernel/process.c 2008-06-22 16:16:32.000000000 +0200
@@ -27,6 +27,7 @@
#include <linux/cpu.h>
#include <linux/elfcore.h>
@@ -74,8 +77,8 @@
return 0;
}
---- linux-2.6.22.perfctr26/arch/i386/Kconfig.~1~ 2007-07-09 22:01:31.000000000 +0200
-+++ linux-2.6.22.perfctr26/arch/i386/Kconfig 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/arch/i386/Kconfig.~1~ 2008-06-22 16:09:12.000000000 +0200
++++ linux-2.6.22.perfctr26/arch/i386/Kconfig 2008-06-22 16:16:32.000000000 +0200
@@ -781,6 +781,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -85,8 +88,8 @@
source kernel/Kconfig.hz
config KEXEC
---- linux-2.6.22.perfctr26/arch/i386/kernel/entry.S.~1~ 2007-07-09 22:01:31.000000000 +0200
-+++ linux-2.6.22.perfctr26/arch/i386/kernel/entry.S 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/arch/i386/kernel/entry.S.~1~ 2008-06-22 16:09:12.000000000 +0200
++++ linux-2.6.22.perfctr26/arch/i386/kernel/entry.S 2008-06-22 16:16:32.000000000 +0200
@@ -637,6 +637,23 @@ ENDPROC(name)
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -111,8 +114,8 @@
KPROBE_ENTRY(page_fault)
RING0_EC_FRAME
pushl $do_page_fault
---- linux-2.6.22.perfctr26/arch/i386/kernel/i8259.c.~1~ 2007-07-09 22:01:31.000000000 +0200
-+++ linux-2.6.22.perfctr26/arch/i386/kernel/i8259.c 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/arch/i386/kernel/i8259.c.~1~ 2008-06-22 15:56:52.000000000 +0200
++++ linux-2.6.22.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 16:16:32.000000000 +0200
@@ -21,6 +21,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -130,8 +133,8 @@
/*
* External FPU? Set up irq13 if so, for
* original braindamaged IBM FERR coupling.
---- linux-2.6.22.perfctr26/arch/i386/kernel/process.c.~1~ 2007-07-09 22:01:31.000000000 +0200
-+++ linux-2.6.22.perfctr26/arch/i386/kernel/process.c 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/arch/i386/kernel/process.c.~1~ 2008-06-22 16:09:12.000000000 +0200
++++ linux-2.6.22.perfctr26/arch/i386/kernel/process.c 2008-06-22 16:16:32.000000000 +0200
@@ -31,6 +31,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -166,8 +169,8 @@
return prev_p;
}
---- linux-2.6.22.perfctr26/arch/powerpc/Kconfig.~1~ 2007-07-09 22:01:31.000000000 +0200
-+++ linux-2.6.22.perfctr26/arch/powerpc/Kconfig 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/arch/powerpc/Kconfig.~1~ 2008-06-22 16:09:12.000000000 +0200
++++ linux-2.6.22.perfctr26/arch/powerpc/Kconfig 2008-06-22 16:16:32.000000000 +0200
@@ -393,6 +393,11 @@ config NOT_COHERENT_CACHE
config CONFIG_CHECK_CACHE_COHERENCY
@@ -180,8 +183,8 @@
endmenu
source "init/Kconfig"
---- linux-2.6.22.perfctr26/arch/powerpc/kernel/process.c.~1~ 2007-07-09 22:01:31.000000000 +0200
-+++ linux-2.6.22.perfctr26/arch/powerpc/kernel/process.c 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/arch/powerpc/kernel/process.c.~1~ 2008-06-22 16:09:12.000000000 +0200
++++ linux-2.6.22.perfctr26/arch/powerpc/kernel/process.c 2008-06-22 16:16:32.000000000 +0200
@@ -30,6 +30,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -217,8 +220,8 @@
return 0;
}
---- linux-2.6.22.perfctr26/arch/x86_64/Kconfig.~1~ 2007-07-09 22:01:31.000000000 +0200
-+++ linux-2.6.22.perfctr26/arch/x86_64/Kconfig 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/arch/x86_64/Kconfig.~1~ 2008-06-22 16:09:12.000000000 +0200
++++ linux-2.6.22.perfctr26/arch/x86_64/Kconfig 2008-06-22 16:16:32.000000000 +0200
@@ -661,6 +661,8 @@ config CC_STACKPROTECTOR_ALL
functions that use large-ish on-stack buffers. By enabling
this option, GCC will be asked to do this for ALL functions.
@@ -228,8 +231,8 @@
source kernel/Kconfig.hz
config K8_NB
---- linux-2.6.22.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2007-07-09 22:01:31.000000000 +0200
-+++ linux-2.6.22.perfctr26/arch/x86_64/kernel/entry.S 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2008-06-22 16:09:12.000000000 +0200
++++ linux-2.6.22.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 16:16:32.000000000 +0200
@@ -692,6 +692,12 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
END(spurious_interrupt)
@@ -243,8 +246,8 @@
/*
* Exception entry points.
*/
---- linux-2.6.22.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2007-07-09 22:01:31.000000000 +0200
-+++ linux-2.6.22.perfctr26/arch/x86_64/kernel/i8259.c 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2008-06-22 16:09:12.000000000 +0200
++++ linux-2.6.22.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 16:16:32.000000000 +0200
@@ -21,6 +21,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -262,8 +265,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.22.perfctr26/arch/x86_64/kernel/process.c.~1~ 2007-07-09 22:01:31.000000000 +0200
-+++ linux-2.6.22.perfctr26/arch/x86_64/kernel/process.c 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/arch/x86_64/kernel/process.c.~1~ 2008-06-22 16:09:13.000000000 +0200
++++ linux-2.6.22.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 16:16:32.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/interrupt.h>
#include <linux/delay.h>
@@ -299,8 +302,8 @@
return prev_p;
}
---- linux-2.6.22.perfctr26/drivers/Makefile.~1~ 2007-07-09 22:01:31.000000000 +0200
-+++ linux-2.6.22.perfctr26/drivers/Makefile 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/drivers/Makefile.~1~ 2008-06-22 16:09:13.000000000 +0200
++++ linux-2.6.22.perfctr26/drivers/Makefile 2008-06-22 16:16:32.000000000 +0200
@@ -74,6 +74,7 @@ obj-$(CONFIG_MMC) += mmc/
obj-$(CONFIG_NEW_LEDS) += leds/
obj-$(CONFIG_INFINIBAND) += infiniband/
@@ -309,8 +312,26 @@
obj-y += firmware/
obj-$(CONFIG_CRYPTO) += crypto/
obj-$(CONFIG_SUPERH) += sh/
---- linux-2.6.22.perfctr26/include/asm-arm/processor.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.22.perfctr26/include/asm-arm/processor.h 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/fs/exec.c.~1~ 2008-06-22 16:09:14.000000000 +0200
++++ linux-2.6.22.perfctr26/fs/exec.c 2008-06-22 16:16:39.000000000 +0200
+@@ -50,6 +50,7 @@
+ #include <linux/tsacct_kern.h>
+ #include <linux/cn_proc.h>
+ #include <linux/audit.h>
++#include <linux/perfctr.h>
+ #include <linux/signalfd.h>
+
+ #include <asm/uaccess.h>
+@@ -882,6 +883,7 @@ int flush_old_exec(struct linux_binprm *
+ set_task_comm(current, tcomm);
+
+ current->flags &= ~PF_RANDOMIZE;
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ /* Set the new mm task size. We have to do that late because it may
+--- linux-2.6.22.perfctr26/include/asm-arm/processor.h.~1~ 2008-06-22 15:42:33.000000000 +0200
++++ linux-2.6.22.perfctr26/include/asm-arm/processor.h 2008-06-22 16:16:32.000000000 +0200
@@ -44,6 +44,10 @@ struct thread_struct {
unsigned long error_code;
/* debugging */
@@ -322,8 +343,8 @@
};
#define INIT_THREAD { }
---- linux-2.6.22.perfctr26/include/asm-arm/system.h.~1~ 2007-07-09 22:01:36.000000000 +0200
-+++ linux-2.6.22.perfctr26/include/asm-arm/system.h 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/include/asm-arm/system.h.~1~ 2008-06-22 16:09:14.000000000 +0200
++++ linux-2.6.22.perfctr26/include/asm-arm/system.h 2008-06-22 16:16:32.000000000 +0200
@@ -251,7 +251,9 @@ extern struct task_struct *__switch_to(s
#define switch_to(prev,next,last) \
@@ -334,8 +355,8 @@
} while (0)
/*
---- linux-2.6.22.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.22.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.22.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 16:16:32.000000000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -354,8 +375,8 @@
#define TIMER_IRQ 0
---- linux-2.6.22.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.22.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.22.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 16:16:32.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -374,8 +395,8 @@
#define TIMER_IRQ 0
---- linux-2.6.22.perfctr26/include/asm-i386/processor.h.~1~ 2007-07-09 22:01:37.000000000 +0200
-+++ linux-2.6.22.perfctr26/include/asm-i386/processor.h 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/include/asm-i386/processor.h.~1~ 2008-06-22 16:09:14.000000000 +0200
++++ linux-2.6.22.perfctr26/include/asm-i386/processor.h 2008-06-22 16:16:32.000000000 +0200
@@ -370,6 +370,8 @@ struct thread_struct {
unsigned long iopl;
/* max allowed port in the bitmap, in bytes: */
@@ -385,8 +406,8 @@
};
#define INIT_THREAD { \
---- linux-2.6.22.perfctr26/include/asm-i386/system.h.~1~ 2007-07-09 22:01:37.000000000 +0200
-+++ linux-2.6.22.perfctr26/include/asm-i386/system.h 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/include/asm-i386/system.h.~1~ 2008-06-22 16:09:14.000000000 +0200
++++ linux-2.6.22.perfctr26/include/asm-i386/system.h 2008-06-22 16:16:32.000000000 +0200
@@ -17,6 +17,7 @@ extern struct task_struct * FASTCALL(__s
*/
#define switch_to(prev,next,last) do { \
@@ -395,8 +416,8 @@
asm volatile("pushfl\n\t" /* Save flags */ \
"pushl %%ebp\n\t" \
"movl %%esp,%0\n\t" /* save ESP */ \
---- linux-2.6.22.perfctr26/include/asm-powerpc/processor.h.~1~ 2007-07-09 22:01:37.000000000 +0200
-+++ linux-2.6.22.perfctr26/include/asm-powerpc/processor.h 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/include/asm-powerpc/processor.h.~1~ 2008-06-22 16:09:15.000000000 +0200
++++ linux-2.6.22.perfctr26/include/asm-powerpc/processor.h 2008-06-22 16:16:32.000000000 +0200
@@ -165,6 +165,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
@@ -407,8 +428,8 @@
};
#define ARCH_MIN_TASKALIGN 16
---- linux-2.6.22.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2007-04-26 14:59:37.000000000 +0200
-+++ linux-2.6.22.perfctr26/include/asm-x86_64/hw_irq.h 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2008-06-22 16:09:15.000000000 +0200
++++ linux-2.6.22.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 16:16:32.000000000 +0200
@@ -84,14 +84,15 @@
* sources per level' errata.
*/
@@ -427,8 +448,8 @@
#ifndef __ASSEMBLY__
---- linux-2.6.22.perfctr26/include/asm-x86_64/irq.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.22.perfctr26/include/asm-x86_64/irq.h 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/include/asm-x86_64/irq.h.~1~ 2008-06-22 15:56:55.000000000 +0200
++++ linux-2.6.22.perfctr26/include/asm-x86_64/irq.h 2008-06-22 16:16:32.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -438,8 +459,8 @@
#define NR_IRQS (NR_VECTORS + (32 *NR_CPUS))
#define NR_IRQ_VECTORS NR_IRQS
---- linux-2.6.22.perfctr26/include/asm-x86_64/processor.h.~1~ 2007-07-09 22:01:37.000000000 +0200
-+++ linux-2.6.22.perfctr26/include/asm-x86_64/processor.h 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/include/asm-x86_64/processor.h.~1~ 2008-06-22 16:09:15.000000000 +0200
++++ linux-2.6.22.perfctr26/include/asm-x86_64/processor.h 2008-06-22 16:16:32.000000000 +0200
@@ -239,6 +239,8 @@ struct thread_struct {
unsigned io_bitmap_max;
/* cached TLS descriptors. */
@@ -449,8 +470,8 @@
} __attribute__((aligned(16)));
#define INIT_THREAD { \
---- linux-2.6.22.perfctr26/include/asm-x86_64/system.h.~1~ 2007-07-09 22:01:37.000000000 +0200
-+++ linux-2.6.22.perfctr26/include/asm-x86_64/system.h 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/include/asm-x86_64/system.h.~1~ 2008-06-22 16:09:15.000000000 +0200
++++ linux-2.6.22.perfctr26/include/asm-x86_64/system.h 2008-06-22 16:16:32.000000000 +0200
@@ -21,7 +21,8 @@
,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
@@ -471,8 +492,8 @@
extern void load_gs_index(unsigned);
---- linux-2.6.22.perfctr26/kernel/exit.c.~1~ 2007-07-09 22:01:37.000000000 +0200
-+++ linux-2.6.22.perfctr26/kernel/exit.c 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/kernel/exit.c.~1~ 2008-06-22 16:09:15.000000000 +0200
++++ linux-2.6.22.perfctr26/kernel/exit.c 2008-06-22 16:16:32.000000000 +0200
@@ -29,6 +29,7 @@
#include <linux/proc_fs.h>
#include <linux/kthread.h>
@@ -489,8 +510,8 @@
sched_exit(p);
write_unlock_irq(&tasklist_lock);
proc_flush_task(p);
---- linux-2.6.22.perfctr26/kernel/sched.c.~1~ 2007-07-09 22:01:37.000000000 +0200
-+++ linux-2.6.22.perfctr26/kernel/sched.c 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/kernel/sched.c.~1~ 2008-06-22 16:09:15.000000000 +0200
++++ linux-2.6.22.perfctr26/kernel/sched.c 2008-06-22 16:16:32.000000000 +0200
@@ -45,6 +45,7 @@
#include <linux/cpu.h>
#include <linux/cpuset.h>
@@ -508,8 +529,8 @@
rq = task_rq_lock(p, &flags);
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
---- linux-2.6.22.perfctr26/kernel/timer.c.~1~ 2007-07-09 22:01:37.000000000 +0200
-+++ linux-2.6.22.perfctr26/kernel/timer.c 2007-07-09 22:07:45.000000000 +0200
+--- linux-2.6.22.perfctr26/kernel/timer.c.~1~ 2008-06-22 16:09:15.000000000 +0200
++++ linux-2.6.22.perfctr26/kernel/timer.c 2008-06-22 16:16:32.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/jiffies.h>
#include <linux/posix-timers.h>
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.23 b/src/perfctr-2.6.x/patches/patch-kernel-2.6.23
index b7e9d3f0647648aab59abc47ce32877e9058dce3..a2d8794e8e872c6fec9b26deb805a19671963516 100644
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.23
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.23
@@ -1,5 +1,5 @@
---- linux-2.6.23.perfctr26/CREDITS.~1~ 2007-10-10 10:33:19.000000000 +0200
-+++ linux-2.6.23.perfctr26/CREDITS 2007-10-14 18:38:24.000000000 +0200
+--- linux-2.6.23.perfctr26/CREDITS.~1~ 2008-06-22 15:56:52.000000000 +0200
++++ linux-2.6.23.perfctr26/CREDITS 2008-06-22 15:58:34.000000000 +0200
@@ -2686,8 +2686,9 @@ S: Canada K2P 0X8
N: Mikael Pettersson
@@ -11,8 +11,8 @@
N: Reed H. Petty
E: rhp@draper.net
---- linux-2.6.23.perfctr26/Documentation/ioctl-number.txt.~1~ 2007-10-10 10:33:19.000000000 +0200
-+++ linux-2.6.23.perfctr26/Documentation/ioctl-number.txt 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/Documentation/ioctl-number.txt.~1~ 2008-06-22 15:42:29.000000000 +0200
++++ linux-2.6.23.perfctr26/Documentation/ioctl-number.txt 2008-06-22 15:58:34.000000000 +0200
@@ -187,6 +187,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -22,8 +22,8 @@
0xDD 00-3F ZFCP device driver see drivers/s390/scsi/
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
---- linux-2.6.23.perfctr26/MAINTAINERS.~1~ 2007-10-10 10:33:19.000000000 +0200
-+++ linux-2.6.23.perfctr26/MAINTAINERS 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/MAINTAINERS.~1~ 2008-06-22 15:56:52.000000000 +0200
++++ linux-2.6.23.perfctr26/MAINTAINERS 2008-06-22 15:58:34.000000000 +0200
@@ -2937,6 +2937,12 @@ M: nagar@watson.ibm.com
L: linux-kernel@vger.kernel.org
S: Maintained
@@ -37,8 +37,8 @@
PERSONALITY HANDLING
P: Christoph Hellwig
M: hch@infradead.org
---- linux-2.6.23.perfctr26/arch/arm/Kconfig.~1~ 2007-10-10 10:33:19.000000000 +0200
-+++ linux-2.6.23.perfctr26/arch/arm/Kconfig 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/arch/arm/Kconfig.~1~ 2008-06-22 15:56:52.000000000 +0200
++++ linux-2.6.23.perfctr26/arch/arm/Kconfig 2008-06-22 15:58:34.000000000 +0200
@@ -491,6 +491,10 @@ config IWMMXT
Enable support for iWMMXt context switching at run time if
running on a CPU that supports it.
@@ -50,8 +50,8 @@
# bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
config XSCALE_PMU
bool
---- linux-2.6.23.perfctr26/arch/arm/kernel/process.c.~1~ 2007-10-10 10:33:19.000000000 +0200
-+++ linux-2.6.23.perfctr26/arch/arm/kernel/process.c 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/arch/arm/kernel/process.c.~1~ 2008-06-22 15:56:52.000000000 +0200
++++ linux-2.6.23.perfctr26/arch/arm/kernel/process.c 2008-06-22 15:58:34.000000000 +0200
@@ -27,6 +27,7 @@
#include <linux/cpu.h>
#include <linux/elfcore.h>
@@ -77,8 +77,8 @@
return 0;
}
---- linux-2.6.23.perfctr26/arch/i386/Kconfig.~1~ 2007-10-10 10:33:19.000000000 +0200
-+++ linux-2.6.23.perfctr26/arch/i386/Kconfig 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/arch/i386/Kconfig.~1~ 2008-06-22 15:56:52.000000000 +0200
++++ linux-2.6.23.perfctr26/arch/i386/Kconfig 2008-06-22 15:58:34.000000000 +0200
@@ -796,6 +796,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
@@ -88,8 +88,8 @@
source kernel/Kconfig.hz
config KEXEC
---- linux-2.6.23.perfctr26/arch/i386/kernel/entry.S.~1~ 2007-10-10 10:33:19.000000000 +0200
-+++ linux-2.6.23.perfctr26/arch/i386/kernel/entry.S 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/arch/i386/kernel/entry.S.~1~ 2008-06-22 15:56:52.000000000 +0200
++++ linux-2.6.23.perfctr26/arch/i386/kernel/entry.S 2008-06-22 15:58:34.000000000 +0200
@@ -635,6 +635,23 @@ ENDPROC(name)
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -114,8 +114,8 @@
KPROBE_ENTRY(page_fault)
RING0_EC_FRAME
pushl $do_page_fault
---- linux-2.6.23.perfctr26/arch/i386/kernel/i8259.c.~1~ 2007-07-09 22:01:31.000000000 +0200
-+++ linux-2.6.23.perfctr26/arch/i386/kernel/i8259.c 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/arch/i386/kernel/i8259.c.~1~ 2008-06-22 15:56:52.000000000 +0200
++++ linux-2.6.23.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 15:58:34.000000000 +0200
@@ -21,6 +21,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -133,8 +133,8 @@
/*
* External FPU? Set up irq13 if so, for
* original braindamaged IBM FERR coupling.
---- linux-2.6.23.perfctr26/arch/i386/kernel/process.c.~1~ 2007-10-10 10:33:19.000000000 +0200
-+++ linux-2.6.23.perfctr26/arch/i386/kernel/process.c 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/arch/i386/kernel/process.c.~1~ 2008-06-22 15:56:52.000000000 +0200
++++ linux-2.6.23.perfctr26/arch/i386/kernel/process.c 2008-06-22 15:58:34.000000000 +0200
@@ -31,6 +31,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -169,8 +169,8 @@
return prev_p;
}
---- linux-2.6.23.perfctr26/arch/powerpc/kernel/process.c.~1~ 2007-10-10 10:33:22.000000000 +0200
-+++ linux-2.6.23.perfctr26/arch/powerpc/kernel/process.c 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/arch/powerpc/kernel/process.c.~1~ 2008-06-22 15:56:52.000000000 +0200
++++ linux-2.6.23.perfctr26/arch/powerpc/kernel/process.c 2008-06-22 15:58:34.000000000 +0200
@@ -30,6 +30,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -206,8 +206,8 @@
return 0;
}
---- linux-2.6.23.perfctr26/arch/powerpc/platforms/Kconfig.cputype.~1~ 2007-10-10 10:33:22.000000000 +0200
-+++ linux-2.6.23.perfctr26/arch/powerpc/platforms/Kconfig.cputype 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/arch/powerpc/platforms/Kconfig.cputype.~1~ 2008-06-22 15:56:52.000000000 +0200
++++ linux-2.6.23.perfctr26/arch/powerpc/platforms/Kconfig.cputype 2008-06-22 15:58:34.000000000 +0200
@@ -218,4 +218,8 @@ config NOT_COHERENT_CACHE
config CHECK_CACHE_COHERENCY
bool
@@ -217,8 +217,8 @@
+endif
+
endmenu
---- linux-2.6.23.perfctr26/arch/x86_64/Kconfig.~1~ 2007-10-10 10:33:22.000000000 +0200
-+++ linux-2.6.23.perfctr26/arch/x86_64/Kconfig 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/arch/x86_64/Kconfig.~1~ 2008-06-22 15:56:53.000000000 +0200
++++ linux-2.6.23.perfctr26/arch/x86_64/Kconfig 2008-06-22 15:58:34.000000000 +0200
@@ -669,6 +669,8 @@ config CC_STACKPROTECTOR_ALL
functions that use large-ish on-stack buffers. By enabling
this option, GCC will be asked to do this for ALL functions.
@@ -228,8 +228,8 @@
source kernel/Kconfig.hz
config K8_NB
---- linux-2.6.23.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2007-10-10 10:33:22.000000000 +0200
-+++ linux-2.6.23.perfctr26/arch/x86_64/kernel/entry.S 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2008-06-22 15:56:53.000000000 +0200
++++ linux-2.6.23.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 15:58:34.000000000 +0200
@@ -692,6 +692,12 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
END(spurious_interrupt)
@@ -243,8 +243,8 @@
/*
* Exception entry points.
*/
---- linux-2.6.23.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2007-10-10 10:33:22.000000000 +0200
-+++ linux-2.6.23.perfctr26/arch/x86_64/kernel/i8259.c 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2008-06-22 15:56:53.000000000 +0200
++++ linux-2.6.23.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 15:58:34.000000000 +0200
@@ -21,6 +21,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -262,8 +262,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.23.perfctr26/arch/x86_64/kernel/process.c.~1~ 2007-10-10 10:33:22.000000000 +0200
-+++ linux-2.6.23.perfctr26/arch/x86_64/kernel/process.c 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/arch/x86_64/kernel/process.c.~1~ 2008-06-22 15:56:53.000000000 +0200
++++ linux-2.6.23.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 15:58:34.000000000 +0200
@@ -33,6 +33,7 @@
#include <linux/interrupt.h>
#include <linux/delay.h>
@@ -299,8 +299,8 @@
return prev_p;
}
---- linux-2.6.23.perfctr26/drivers/Makefile.~1~ 2007-10-10 10:33:23.000000000 +0200
-+++ linux-2.6.23.perfctr26/drivers/Makefile 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/drivers/Makefile.~1~ 2008-06-22 15:56:53.000000000 +0200
++++ linux-2.6.23.perfctr26/drivers/Makefile 2008-06-22 15:58:34.000000000 +0200
@@ -80,6 +80,7 @@ obj-$(CONFIG_MMC) += mmc/
obj-$(CONFIG_NEW_LEDS) += leds/
obj-$(CONFIG_INFINIBAND) += infiniband/
@@ -309,8 +309,26 @@
obj-y += firmware/
obj-$(CONFIG_CRYPTO) += crypto/
obj-$(CONFIG_SUPERH) += sh/
---- linux-2.6.23.perfctr26/include/asm-arm/processor.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.23.perfctr26/include/asm-arm/processor.h 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/fs/exec.c.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.23.perfctr26/fs/exec.c 2008-06-22 15:58:20.000000000 +0200
+@@ -50,6 +50,7 @@
+ #include <linux/tsacct_kern.h>
+ #include <linux/cn_proc.h>
+ #include <linux/audit.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -1065,6 +1066,7 @@ int flush_old_exec(struct linux_binprm *
+ set_task_comm(current, tcomm);
+
+ current->flags &= ~PF_RANDOMIZE;
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ /* Set the new mm task size. We have to do that late because it may
+--- linux-2.6.23.perfctr26/include/asm-arm/processor.h.~1~ 2008-06-22 15:42:33.000000000 +0200
++++ linux-2.6.23.perfctr26/include/asm-arm/processor.h 2008-06-22 15:58:34.000000000 +0200
@@ -44,6 +44,10 @@ struct thread_struct {
unsigned long error_code;
/* debugging */
@@ -322,8 +340,8 @@
};
#define INIT_THREAD { }
---- linux-2.6.23.perfctr26/include/asm-arm/system.h.~1~ 2007-10-10 10:33:38.000000000 +0200
-+++ linux-2.6.23.perfctr26/include/asm-arm/system.h 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/include/asm-arm/system.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.23.perfctr26/include/asm-arm/system.h 2008-06-22 15:58:34.000000000 +0200
@@ -251,7 +251,9 @@ extern struct task_struct *__switch_to(s
#define switch_to(prev,next,last) \
@@ -334,8 +352,8 @@
} while (0)
#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
---- linux-2.6.23.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.23.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.23.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 15:58:34.000000000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -354,8 +372,8 @@
#define TIMER_IRQ 0
---- linux-2.6.23.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.23.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.23.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 15:58:34.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -374,8 +392,8 @@
#define TIMER_IRQ 0
---- linux-2.6.23.perfctr26/include/asm-i386/processor.h.~1~ 2007-10-10 10:33:38.000000000 +0200
-+++ linux-2.6.23.perfctr26/include/asm-i386/processor.h 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/include/asm-i386/processor.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.23.perfctr26/include/asm-i386/processor.h 2008-06-22 15:58:34.000000000 +0200
@@ -363,6 +363,8 @@ struct thread_struct {
unsigned long iopl;
/* max allowed port in the bitmap, in bytes: */
@@ -385,8 +403,8 @@
};
#define INIT_THREAD { \
---- linux-2.6.23.perfctr26/include/asm-i386/system.h.~1~ 2007-10-10 10:33:38.000000000 +0200
-+++ linux-2.6.23.perfctr26/include/asm-i386/system.h 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/include/asm-i386/system.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.23.perfctr26/include/asm-i386/system.h 2008-06-22 15:58:34.000000000 +0200
@@ -17,6 +17,7 @@ extern struct task_struct * FASTCALL(__s
*/
#define switch_to(prev,next,last) do { \
@@ -395,8 +413,8 @@
asm volatile("pushfl\n\t" /* Save flags */ \
"pushl %%ebp\n\t" \
"movl %%esp,%0\n\t" /* save ESP */ \
---- linux-2.6.23.perfctr26/include/asm-powerpc/processor.h.~1~ 2007-10-10 10:33:38.000000000 +0200
-+++ linux-2.6.23.perfctr26/include/asm-powerpc/processor.h 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/include/asm-powerpc/processor.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.23.perfctr26/include/asm-powerpc/processor.h 2008-06-22 15:58:34.000000000 +0200
@@ -157,6 +157,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
@@ -407,8 +425,8 @@
};
#define ARCH_MIN_TASKALIGN 16
---- linux-2.6.23.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2007-10-10 10:33:38.000000000 +0200
-+++ linux-2.6.23.perfctr26/include/asm-x86_64/hw_irq.h 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2008-06-22 15:56:55.000000000 +0200
++++ linux-2.6.23.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 15:58:34.000000000 +0200
@@ -84,14 +84,15 @@
* sources per level' errata.
*/
@@ -427,8 +445,8 @@
#ifndef __ASSEMBLY__
---- linux-2.6.23.perfctr26/include/asm-x86_64/irq.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.23.perfctr26/include/asm-x86_64/irq.h 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/include/asm-x86_64/irq.h.~1~ 2008-06-22 15:56:55.000000000 +0200
++++ linux-2.6.23.perfctr26/include/asm-x86_64/irq.h 2008-06-22 15:58:34.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -438,8 +456,8 @@
#define NR_IRQS (NR_VECTORS + (32 *NR_CPUS))
#define NR_IRQ_VECTORS NR_IRQS
---- linux-2.6.23.perfctr26/include/asm-x86_64/processor.h.~1~ 2007-10-10 10:33:38.000000000 +0200
-+++ linux-2.6.23.perfctr26/include/asm-x86_64/processor.h 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/include/asm-x86_64/processor.h.~1~ 2008-06-22 15:56:55.000000000 +0200
++++ linux-2.6.23.perfctr26/include/asm-x86_64/processor.h 2008-06-22 15:58:34.000000000 +0200
@@ -239,6 +239,8 @@ struct thread_struct {
unsigned io_bitmap_max;
/* cached TLS descriptors. */
@@ -449,8 +467,8 @@
} __attribute__((aligned(16)));
#define INIT_THREAD { \
---- linux-2.6.23.perfctr26/include/asm-x86_64/system.h.~1~ 2007-10-10 10:33:38.000000000 +0200
-+++ linux-2.6.23.perfctr26/include/asm-x86_64/system.h 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/include/asm-x86_64/system.h.~1~ 2008-06-22 15:56:55.000000000 +0200
++++ linux-2.6.23.perfctr26/include/asm-x86_64/system.h 2008-06-22 15:58:34.000000000 +0200
@@ -21,7 +21,8 @@
,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
@@ -471,8 +489,8 @@
extern void load_gs_index(unsigned);
---- linux-2.6.23.perfctr26/kernel/exit.c.~1~ 2007-10-10 10:33:38.000000000 +0200
-+++ linux-2.6.23.perfctr26/kernel/exit.c 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/kernel/exit.c.~1~ 2008-06-22 15:56:55.000000000 +0200
++++ linux-2.6.23.perfctr26/kernel/exit.c 2008-06-22 15:58:34.000000000 +0200
@@ -28,6 +28,7 @@
#include <linux/proc_fs.h>
#include <linux/kthread.h>
@@ -489,8 +507,8 @@
write_unlock_irq(&tasklist_lock);
proc_flush_task(p);
release_thread(p);
---- linux-2.6.23.perfctr26/kernel/sched.c.~1~ 2007-10-10 10:33:38.000000000 +0200
-+++ linux-2.6.23.perfctr26/kernel/sched.c 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/kernel/sched.c.~1~ 2008-06-22 15:56:55.000000000 +0200
++++ linux-2.6.23.perfctr26/kernel/sched.c 2008-06-22 15:58:34.000000000 +0200
@@ -51,6 +51,7 @@
#include <linux/cpu.h>
#include <linux/cpuset.h>
@@ -508,8 +526,8 @@
rq = task_rq_lock(p, &flags);
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
---- linux-2.6.23.perfctr26/kernel/timer.c.~1~ 2007-10-10 10:33:38.000000000 +0200
-+++ linux-2.6.23.perfctr26/kernel/timer.c 2007-10-14 18:37:10.000000000 +0200
+--- linux-2.6.23.perfctr26/kernel/timer.c.~1~ 2008-06-22 15:56:55.000000000 +0200
++++ linux-2.6.23.perfctr26/kernel/timer.c 2008-06-22 15:58:34.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/jiffies.h>
#include <linux/posix-timers.h>
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.24 b/src/perfctr-2.6.x/patches/patch-kernel-2.6.24
index 0b791b1ea0c317afeeb15fbbbdfcbde7db090098..48be2fd2ef3eb322f168cd136b0baaca338374a5 100644
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.24
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.24
@@ -1,5 +1,5 @@
---- linux-2.6.24.perfctr26/CREDITS.~1~ 2008-01-25 12:31:54.000000000 +0100
-+++ linux-2.6.24.perfctr26/CREDITS 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/CREDITS.~1~ 2008-06-22 15:42:29.000000000 +0200
++++ linux-2.6.24.perfctr26/CREDITS 2008-06-22 15:44:14.000000000 +0200
@@ -2710,6 +2710,7 @@ N: Mikael Pettersson
E: mikpe@it.uu.se
W: http://user.it.uu.se/~mikpe/linux/
@@ -8,8 +8,8 @@
N: Reed H. Petty
E: rhp@draper.net
---- linux-2.6.24.perfctr26/Documentation/ioctl-number.txt.~1~ 2007-10-10 10:33:19.000000000 +0200
-+++ linux-2.6.24.perfctr26/Documentation/ioctl-number.txt 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/Documentation/ioctl-number.txt.~1~ 2008-06-22 15:42:29.000000000 +0200
++++ linux-2.6.24.perfctr26/Documentation/ioctl-number.txt 2008-06-22 15:44:14.000000000 +0200
@@ -187,6 +187,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -19,8 +19,8 @@
0xDD 00-3F ZFCP device driver see drivers/s390/scsi/
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
---- linux-2.6.24.perfctr26/MAINTAINERS.~1~ 2008-01-25 12:31:54.000000000 +0100
-+++ linux-2.6.24.perfctr26/MAINTAINERS 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/MAINTAINERS.~1~ 2008-06-22 15:42:29.000000000 +0200
++++ linux-2.6.24.perfctr26/MAINTAINERS 2008-06-22 15:44:14.000000000 +0200
@@ -2980,6 +2980,12 @@ M: nagar@watson.ibm.com
L: linux-kernel@vger.kernel.org
S: Maintained
@@ -34,8 +34,8 @@
PERSONALITY HANDLING
P: Christoph Hellwig
M: hch@infradead.org
---- linux-2.6.24.perfctr26/arch/arm/Kconfig.~1~ 2008-01-25 12:31:54.000000000 +0100
-+++ linux-2.6.24.perfctr26/arch/arm/Kconfig 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/arch/arm/Kconfig.~1~ 2008-06-22 15:42:29.000000000 +0200
++++ linux-2.6.24.perfctr26/arch/arm/Kconfig 2008-06-22 15:44:14.000000000 +0200
@@ -494,6 +494,10 @@ config IWMMXT
Enable support for iWMMXt context switching at run time if
running on a CPU that supports it.
@@ -47,8 +47,8 @@
# bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
config XSCALE_PMU
bool
---- linux-2.6.24.perfctr26/arch/arm/kernel/process.c.~1~ 2008-01-25 12:31:54.000000000 +0100
-+++ linux-2.6.24.perfctr26/arch/arm/kernel/process.c 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/arch/arm/kernel/process.c.~1~ 2008-06-22 15:42:29.000000000 +0200
++++ linux-2.6.24.perfctr26/arch/arm/kernel/process.c 2008-06-22 15:44:14.000000000 +0200
@@ -27,6 +27,7 @@
#include <linux/cpu.h>
#include <linux/elfcore.h>
@@ -74,8 +74,8 @@
return 0;
}
---- linux-2.6.24.perfctr26/arch/powerpc/kernel/process.c.~1~ 2008-01-25 12:31:55.000000000 +0100
-+++ linux-2.6.24.perfctr26/arch/powerpc/kernel/process.c 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/arch/powerpc/kernel/process.c.~1~ 2008-06-22 15:42:30.000000000 +0200
++++ linux-2.6.24.perfctr26/arch/powerpc/kernel/process.c 2008-06-22 15:44:14.000000000 +0200
@@ -30,6 +30,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -111,8 +111,8 @@
return 0;
}
---- linux-2.6.24.perfctr26/arch/powerpc/platforms/Kconfig.cputype.~1~ 2008-01-25 12:31:55.000000000 +0100
-+++ linux-2.6.24.perfctr26/arch/powerpc/platforms/Kconfig.cputype 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/arch/powerpc/platforms/Kconfig.cputype.~1~ 2008-06-22 15:42:30.000000000 +0200
++++ linux-2.6.24.perfctr26/arch/powerpc/platforms/Kconfig.cputype 2008-06-22 15:44:14.000000000 +0200
@@ -234,4 +234,8 @@ config NOT_COHERENT_CACHE
config CHECK_CACHE_COHERENCY
bool
@@ -122,8 +122,8 @@
+endif
+
endmenu
---- linux-2.6.24.perfctr26/arch/x86/Kconfig.~1~ 2008-01-25 12:31:55.000000000 +0100
-+++ linux-2.6.24.perfctr26/arch/x86/Kconfig 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/arch/x86/Kconfig.~1~ 2008-06-22 15:42:30.000000000 +0200
++++ linux-2.6.24.perfctr26/arch/x86/Kconfig 2008-06-22 15:44:14.000000000 +0200
@@ -1060,6 +1060,8 @@ config CC_STACKPROTECTOR_ALL
functions that use large-ish on-stack buffers. By enabling
this option, GCC will be asked to do this for ALL functions.
@@ -133,8 +133,8 @@
source kernel/Kconfig.hz
config KEXEC
---- linux-2.6.24.perfctr26/arch/x86/kernel/entry_32.S.~1~ 2008-01-25 12:31:55.000000000 +0100
-+++ linux-2.6.24.perfctr26/arch/x86/kernel/entry_32.S 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/arch/x86/kernel/entry_32.S.~1~ 2008-06-22 15:42:30.000000000 +0200
++++ linux-2.6.24.perfctr26/arch/x86/kernel/entry_32.S 2008-06-22 15:44:14.000000000 +0200
@@ -639,6 +639,23 @@ ENDPROC(name)
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -159,8 +159,8 @@
KPROBE_ENTRY(page_fault)
RING0_EC_FRAME
pushl $do_page_fault
---- linux-2.6.24.perfctr26/arch/x86/kernel/entry_64.S.~1~ 2008-01-25 12:31:55.000000000 +0100
-+++ linux-2.6.24.perfctr26/arch/x86/kernel/entry_64.S 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/arch/x86/kernel/entry_64.S.~1~ 2008-06-22 15:42:30.000000000 +0200
++++ linux-2.6.24.perfctr26/arch/x86/kernel/entry_64.S 2008-06-22 15:44:14.000000000 +0200
@@ -696,6 +696,12 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
END(spurious_interrupt)
@@ -174,8 +174,8 @@
/*
* Exception entry points.
*/
---- linux-2.6.24.perfctr26/arch/x86/kernel/i8259_32.c.~1~ 2008-01-25 12:31:55.000000000 +0100
-+++ linux-2.6.24.perfctr26/arch/x86/kernel/i8259_32.c 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/arch/x86/kernel/i8259_32.c.~1~ 2008-06-22 15:42:30.000000000 +0200
++++ linux-2.6.24.perfctr26/arch/x86/kernel/i8259_32.c 2008-06-22 15:44:14.000000000 +0200
@@ -20,6 +20,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -193,8 +193,8 @@
/*
* External FPU? Set up irq13 if so, for
* original braindamaged IBM FERR coupling.
---- linux-2.6.24.perfctr26/arch/x86/kernel/i8259_64.c.~1~ 2008-01-25 12:31:55.000000000 +0100
-+++ linux-2.6.24.perfctr26/arch/x86/kernel/i8259_64.c 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/arch/x86/kernel/i8259_64.c.~1~ 2008-06-22 15:42:30.000000000 +0200
++++ linux-2.6.24.perfctr26/arch/x86/kernel/i8259_64.c 2008-06-22 15:44:14.000000000 +0200
@@ -21,6 +21,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -212,8 +212,8 @@
if (!acpi_ioapic)
setup_irq(2, &irq2);
}
---- linux-2.6.24.perfctr26/arch/x86/kernel/process_32.c.~1~ 2008-01-25 12:31:55.000000000 +0100
-+++ linux-2.6.24.perfctr26/arch/x86/kernel/process_32.c 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/arch/x86/kernel/process_32.c.~1~ 2008-06-22 15:42:30.000000000 +0200
++++ linux-2.6.24.perfctr26/arch/x86/kernel/process_32.c 2008-06-22 15:44:14.000000000 +0200
@@ -29,6 +29,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -248,8 +248,8 @@
return prev_p;
}
---- linux-2.6.24.perfctr26/arch/x86/kernel/process_64.c.~1~ 2008-01-25 12:31:55.000000000 +0100
-+++ linux-2.6.24.perfctr26/arch/x86/kernel/process_64.c 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/arch/x86/kernel/process_64.c.~1~ 2008-06-22 15:42:30.000000000 +0200
++++ linux-2.6.24.perfctr26/arch/x86/kernel/process_64.c 2008-06-22 15:44:14.000000000 +0200
@@ -31,6 +31,7 @@
#include <linux/interrupt.h>
#include <linux/delay.h>
@@ -285,8 +285,8 @@
return prev_p;
}
---- linux-2.6.24.perfctr26/drivers/Makefile.~1~ 2008-01-25 12:31:55.000000000 +0100
-+++ linux-2.6.24.perfctr26/drivers/Makefile 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/drivers/Makefile.~1~ 2008-06-22 15:42:30.000000000 +0200
++++ linux-2.6.24.perfctr26/drivers/Makefile 2008-06-22 15:44:14.000000000 +0200
@@ -80,6 +80,7 @@ obj-$(CONFIG_MMC) += mmc/
obj-$(CONFIG_NEW_LEDS) += leds/
obj-$(CONFIG_INFINIBAND) += infiniband/
@@ -295,8 +295,26 @@
obj-y += firmware/
obj-$(CONFIG_CRYPTO) += crypto/
obj-$(CONFIG_SUPERH) += sh/
---- linux-2.6.24.perfctr26/include/asm-arm/processor.h.~1~ 2007-02-04 19:44:54.000000000 +0100
-+++ linux-2.6.24.perfctr26/include/asm-arm/processor.h 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/fs/exec.c.~1~ 2008-06-22 15:42:32.000000000 +0200
++++ linux-2.6.24.perfctr26/fs/exec.c 2008-06-22 15:43:55.000000000 +0200
+@@ -51,6 +51,7 @@
+ #include <linux/tsacct_kern.h>
+ #include <linux/cn_proc.h>
+ #include <linux/audit.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -1019,6 +1020,7 @@ int flush_old_exec(struct linux_binprm *
+ set_task_comm(current, tcomm);
+
+ current->flags &= ~PF_RANDOMIZE;
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ /* Set the new mm task size. We have to do that late because it may
+--- linux-2.6.24.perfctr26/include/asm-arm/processor.h.~1~ 2008-06-22 15:42:33.000000000 +0200
++++ linux-2.6.24.perfctr26/include/asm-arm/processor.h 2008-06-22 15:44:14.000000000 +0200
@@ -44,6 +44,10 @@ struct thread_struct {
unsigned long error_code;
/* debugging */
@@ -308,8 +326,8 @@
};
#define INIT_THREAD { }
---- linux-2.6.24.perfctr26/include/asm-arm/system.h.~1~ 2008-01-25 12:31:57.000000000 +0100
-+++ linux-2.6.24.perfctr26/include/asm-arm/system.h 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/include/asm-arm/system.h.~1~ 2008-06-22 15:42:33.000000000 +0200
++++ linux-2.6.24.perfctr26/include/asm-arm/system.h 2008-06-22 15:44:14.000000000 +0200
@@ -264,7 +264,9 @@ extern struct task_struct *__switch_to(s
#define switch_to(prev,next,last) \
@@ -320,8 +338,8 @@
} while (0)
#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
---- linux-2.6.24.perfctr26/include/asm-powerpc/processor.h.~1~ 2008-01-25 12:31:57.000000000 +0100
-+++ linux-2.6.24.perfctr26/include/asm-powerpc/processor.h 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/include/asm-powerpc/processor.h.~1~ 2008-06-22 15:42:33.000000000 +0200
++++ linux-2.6.24.perfctr26/include/asm-powerpc/processor.h 2008-06-22 15:44:14.000000000 +0200
@@ -157,6 +157,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
@@ -332,8 +350,8 @@
};
#define ARCH_MIN_TASKALIGN 16
---- linux-2.6.24.perfctr26/include/asm-x86/hw_irq_64.h.~1~ 2008-01-25 12:31:58.000000000 +0100
-+++ linux-2.6.24.perfctr26/include/asm-x86/hw_irq_64.h 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/include/asm-x86/hw_irq_64.h.~1~ 2008-06-22 15:42:33.000000000 +0200
++++ linux-2.6.24.perfctr26/include/asm-x86/hw_irq_64.h 2008-06-22 15:44:14.000000000 +0200
@@ -84,14 +84,15 @@
* sources per level' errata.
*/
@@ -353,7 +371,7 @@
#ifndef __ASSEMBLY__
--- linux-2.6.24.perfctr26/include/asm-x86/irq_64.h.~1~ 2008-01-25 12:31:58.000000000 +0100
-+++ linux-2.6.24.perfctr26/include/asm-x86/irq_64.h 2008-01-25 12:46:16.000000000 +0100
++++ linux-2.6.24.perfctr26/include/asm-x86/irq_64.h 2008-06-22 15:44:14.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -364,7 +382,7 @@
#define NR_IRQS (NR_VECTORS + (32 *NR_CPUS))
#define NR_IRQ_VECTORS NR_IRQS
--- linux-2.6.24.perfctr26/include/asm-x86/mach-default/irq_vectors.h.~1~ 2008-01-25 12:31:58.000000000 +0100
-+++ linux-2.6.24.perfctr26/include/asm-x86/mach-default/irq_vectors.h 2008-01-25 12:46:16.000000000 +0100
++++ linux-2.6.24.perfctr26/include/asm-x86/mach-default/irq_vectors.h 2008-06-22 15:44:14.000000000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -384,7 +402,7 @@
#define TIMER_IRQ 0
--- linux-2.6.24.perfctr26/include/asm-x86/mach-visws/irq_vectors.h.~1~ 2008-01-25 12:31:58.000000000 +0100
-+++ linux-2.6.24.perfctr26/include/asm-x86/mach-visws/irq_vectors.h 2008-01-25 12:46:16.000000000 +0100
++++ linux-2.6.24.perfctr26/include/asm-x86/mach-visws/irq_vectors.h 2008-06-22 15:44:14.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -403,8 +421,8 @@
#define TIMER_IRQ 0
---- linux-2.6.24.perfctr26/include/asm-x86/processor_32.h.~1~ 2008-01-25 12:31:58.000000000 +0100
-+++ linux-2.6.24.perfctr26/include/asm-x86/processor_32.h 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/include/asm-x86/processor_32.h.~1~ 2008-06-22 15:42:33.000000000 +0200
++++ linux-2.6.24.perfctr26/include/asm-x86/processor_32.h 2008-06-22 15:44:14.000000000 +0200
@@ -369,6 +369,8 @@ struct thread_struct {
unsigned long iopl;
/* max allowed port in the bitmap, in bytes: */
@@ -414,8 +432,8 @@
};
#define INIT_THREAD { \
---- linux-2.6.24.perfctr26/include/asm-x86/processor_64.h.~1~ 2008-01-25 12:31:58.000000000 +0100
-+++ linux-2.6.24.perfctr26/include/asm-x86/processor_64.h 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/include/asm-x86/processor_64.h.~1~ 2008-06-22 15:42:33.000000000 +0200
++++ linux-2.6.24.perfctr26/include/asm-x86/processor_64.h 2008-06-22 15:44:14.000000000 +0200
@@ -241,6 +241,8 @@ struct thread_struct {
unsigned io_bitmap_max;
/* cached TLS descriptors. */
@@ -425,8 +443,8 @@
} __attribute__((aligned(16)));
#define INIT_THREAD { \
---- linux-2.6.24.perfctr26/include/asm-x86/system_32.h.~1~ 2008-01-25 12:31:58.000000000 +0100
-+++ linux-2.6.24.perfctr26/include/asm-x86/system_32.h 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/include/asm-x86/system_32.h.~1~ 2008-06-22 15:42:33.000000000 +0200
++++ linux-2.6.24.perfctr26/include/asm-x86/system_32.h 2008-06-22 15:44:14.000000000 +0200
@@ -18,6 +18,7 @@ extern struct task_struct * FASTCALL(__s
*/
#define switch_to(prev,next,last) do { \
@@ -435,8 +453,8 @@
asm volatile("pushfl\n\t" /* Save flags */ \
"pushl %%ebp\n\t" \
"movl %%esp,%0\n\t" /* save ESP */ \
---- linux-2.6.24.perfctr26/include/asm-x86/system_64.h.~1~ 2008-01-25 12:31:58.000000000 +0100
-+++ linux-2.6.24.perfctr26/include/asm-x86/system_64.h 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/include/asm-x86/system_64.h.~1~ 2008-06-22 15:42:33.000000000 +0200
++++ linux-2.6.24.perfctr26/include/asm-x86/system_64.h 2008-06-22 15:44:14.000000000 +0200
@@ -25,7 +25,8 @@
,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
@@ -457,8 +475,8 @@
extern void load_gs_index(unsigned);
---- linux-2.6.24.perfctr26/kernel/exit.c.~1~ 2008-01-25 12:31:58.000000000 +0100
-+++ linux-2.6.24.perfctr26/kernel/exit.c 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/kernel/exit.c.~1~ 2008-06-22 15:42:33.000000000 +0200
++++ linux-2.6.24.perfctr26/kernel/exit.c 2008-06-22 15:44:14.000000000 +0200
@@ -28,6 +28,7 @@
#include <linux/proc_fs.h>
#include <linux/kthread.h>
@@ -475,8 +493,8 @@
write_unlock_irq(&tasklist_lock);
release_thread(p);
call_rcu(&p->rcu, delayed_put_task_struct);
---- linux-2.6.24.perfctr26/kernel/sched.c.~1~ 2008-01-25 12:31:58.000000000 +0100
-+++ linux-2.6.24.perfctr26/kernel/sched.c 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/kernel/sched.c.~1~ 2008-06-22 15:42:33.000000000 +0200
++++ linux-2.6.24.perfctr26/kernel/sched.c 2008-06-22 15:44:14.000000000 +0200
@@ -52,6 +52,7 @@
#include <linux/cpu.h>
#include <linux/cpuset.h>
@@ -494,8 +512,8 @@
rq = task_rq_lock(p, &flags);
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
---- linux-2.6.24.perfctr26/kernel/timer.c.~1~ 2008-01-25 12:31:58.000000000 +0100
-+++ linux-2.6.24.perfctr26/kernel/timer.c 2008-01-25 12:46:16.000000000 +0100
+--- linux-2.6.24.perfctr26/kernel/timer.c.~1~ 2008-06-22 15:42:33.000000000 +0200
++++ linux-2.6.24.perfctr26/kernel/timer.c 2008-06-22 15:44:14.000000000 +0200
@@ -33,6 +33,7 @@
#include <linux/jiffies.h>
#include <linux/posix-timers.h>
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.25 b/src/perfctr-2.6.x/patches/patch-kernel-2.6.25
index ef004da05309949bd92f331301bd8ceb6750072d..a7ce160a6ad827c78b6ef50aef63cfa90506a784 100644
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.25
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.25
@@ -1,5 +1,5 @@
--- linux-2.6.25.perfctr26/CREDITS.~1~ 2008-04-17 18:22:31.000000000 +0200
-+++ linux-2.6.25.perfctr26/CREDITS 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/CREDITS 2008-06-22 15:17:34.000000000 +0200
@@ -2717,6 +2717,7 @@ N: Mikael Pettersson
E: mikpe@it.uu.se
W: http://user.it.uu.se/~mikpe/linux/
@@ -9,7 +9,7 @@
N: Reed H. Petty
E: rhp@draper.net
--- linux-2.6.25.perfctr26/Documentation/ioctl-number.txt.~1~ 2008-04-17 18:22:31.000000000 +0200
-+++ linux-2.6.25.perfctr26/Documentation/ioctl-number.txt 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/Documentation/ioctl-number.txt 2008-06-22 15:17:34.000000000 +0200
@@ -188,6 +188,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -20,7 +20,7 @@
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
--- linux-2.6.25.perfctr26/MAINTAINERS.~1~ 2008-04-17 18:22:31.000000000 +0200
-+++ linux-2.6.25.perfctr26/MAINTAINERS 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/MAINTAINERS 2008-06-22 15:17:34.000000000 +0200
@@ -3098,6 +3098,12 @@ M: nagar@watson.ibm.com
L: linux-kernel@vger.kernel.org
S: Maintained
@@ -35,7 +35,7 @@
P: Christoph Hellwig
M: hch@infradead.org
--- linux-2.6.25.perfctr26/arch/arm/Kconfig.~1~ 2008-04-17 18:22:31.000000000 +0200
-+++ linux-2.6.25.perfctr26/arch/arm/Kconfig 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/arch/arm/Kconfig 2008-06-22 15:17:34.000000000 +0200
@@ -573,6 +573,10 @@ config IWMMXT
Enable support for iWMMXt context switching at run time if
running on a CPU that supports it.
@@ -48,7 +48,7 @@
config XSCALE_PMU
bool
--- linux-2.6.25.perfctr26/arch/arm/kernel/process.c.~1~ 2008-04-17 18:22:31.000000000 +0200
-+++ linux-2.6.25.perfctr26/arch/arm/kernel/process.c 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/arch/arm/kernel/process.c 2008-06-22 15:17:34.000000000 +0200
@@ -26,6 +26,7 @@
#include <linux/cpu.h>
#include <linux/elfcore.h>
@@ -75,7 +75,7 @@
}
--- linux-2.6.25.perfctr26/arch/powerpc/kernel/process.c.~1~ 2008-04-17 18:22:32.000000000 +0200
-+++ linux-2.6.25.perfctr26/arch/powerpc/kernel/process.c 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/arch/powerpc/kernel/process.c 2008-06-22 15:17:34.000000000 +0200
@@ -30,6 +30,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -113,7 +113,7 @@
}
--- linux-2.6.25.perfctr26/arch/powerpc/platforms/Kconfig.cputype.~1~ 2008-04-17 18:22:32.000000000 +0200
-+++ linux-2.6.25.perfctr26/arch/powerpc/platforms/Kconfig.cputype 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/arch/powerpc/platforms/Kconfig.cputype 2008-06-22 15:17:34.000000000 +0200
@@ -232,4 +232,8 @@ config NOT_COHERENT_CACHE
config CHECK_CACHE_COHERENCY
bool
@@ -124,7 +124,7 @@
+
endmenu
--- linux-2.6.25.perfctr26/arch/x86/Kconfig.~1~ 2008-04-17 18:22:32.000000000 +0200
-+++ linux-2.6.25.perfctr26/arch/x86/Kconfig 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/arch/x86/Kconfig 2008-06-22 15:17:34.000000000 +0200
@@ -1074,6 +1074,8 @@ config CC_STACKPROTECTOR_ALL
functions that use large-ish on-stack buffers. By enabling
this option, GCC will be asked to do this for ALL functions.
@@ -135,7 +135,7 @@
config KEXEC
--- linux-2.6.25.perfctr26/arch/x86/kernel/entry_32.S.~1~ 2008-04-17 18:22:32.000000000 +0200
-+++ linux-2.6.25.perfctr26/arch/x86/kernel/entry_32.S 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/arch/x86/kernel/entry_32.S 2008-06-22 15:17:34.000000000 +0200
@@ -640,6 +640,23 @@ ENDPROC(name)
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -161,7 +161,7 @@
RING0_EC_FRAME
pushl $do_page_fault
--- linux-2.6.25.perfctr26/arch/x86/kernel/entry_64.S.~1~ 2008-04-17 18:22:32.000000000 +0200
-+++ linux-2.6.25.perfctr26/arch/x86/kernel/entry_64.S 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/arch/x86/kernel/entry_64.S 2008-06-22 15:17:34.000000000 +0200
@@ -730,6 +730,12 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
END(spurious_interrupt)
@@ -176,7 +176,7 @@
* Exception entry points.
*/
--- linux-2.6.25.perfctr26/arch/x86/kernel/i8259_32.c.~1~ 2008-04-17 18:22:32.000000000 +0200
-+++ linux-2.6.25.perfctr26/arch/x86/kernel/i8259_32.c 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/arch/x86/kernel/i8259_32.c 2008-06-22 15:17:34.000000000 +0200
@@ -20,6 +20,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -195,7 +195,7 @@
* External FPU? Set up irq13 if so, for
* original braindamaged IBM FERR coupling.
--- linux-2.6.25.perfctr26/arch/x86/kernel/i8259_64.c.~1~ 2008-04-17 18:22:32.000000000 +0200
-+++ linux-2.6.25.perfctr26/arch/x86/kernel/i8259_64.c 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/arch/x86/kernel/i8259_64.c 2008-06-22 15:17:34.000000000 +0200
@@ -21,6 +21,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -214,7 +214,7 @@
setup_irq(2, &irq2);
}
--- linux-2.6.25.perfctr26/arch/x86/kernel/process_32.c.~1~ 2008-04-17 18:22:32.000000000 +0200
-+++ linux-2.6.25.perfctr26/arch/x86/kernel/process_32.c 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/arch/x86/kernel/process_32.c 2008-06-22 15:17:34.000000000 +0200
@@ -28,6 +28,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -250,7 +250,7 @@
}
--- linux-2.6.25.perfctr26/arch/x86/kernel/process_64.c.~1~ 2008-04-17 18:22:32.000000000 +0200
-+++ linux-2.6.25.perfctr26/arch/x86/kernel/process_64.c 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/arch/x86/kernel/process_64.c 2008-06-22 15:17:34.000000000 +0200
@@ -31,6 +31,7 @@
#include <linux/delay.h>
#include <linux/module.h>
@@ -287,7 +287,7 @@
}
--- linux-2.6.25.perfctr26/drivers/Makefile.~1~ 2008-04-17 18:22:32.000000000 +0200
-+++ linux-2.6.25.perfctr26/drivers/Makefile 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/drivers/Makefile 2008-06-22 15:17:34.000000000 +0200
@@ -82,6 +82,7 @@ obj-$(CONFIG_MEMSTICK) += memstick/
obj-$(CONFIG_NEW_LEDS) += leds/
obj-$(CONFIG_INFINIBAND) += infiniband/
@@ -296,8 +296,26 @@
obj-y += firmware/
obj-$(CONFIG_CRYPTO) += crypto/
obj-$(CONFIG_SUPERH) += sh/
+--- linux-2.6.25.perfctr26/fs/exec.c.~1~ 2008-04-17 18:22:35.000000000 +0200
++++ linux-2.6.25.perfctr26/fs/exec.c 2008-06-22 15:17:56.000000000 +0200
+@@ -51,6 +51,7 @@
+ #include <linux/tsacct_kern.h>
+ #include <linux/cn_proc.h>
+ #include <linux/audit.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -1006,6 +1007,7 @@ int flush_old_exec(struct linux_binprm *
+ set_task_comm(current, tcomm);
+
+ current->flags &= ~PF_RANDOMIZE;
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ /* Set the new mm task size. We have to do that late because it may
--- linux-2.6.25.perfctr26/include/asm-arm/processor.h.~1~ 2008-04-17 18:22:35.000000000 +0200
-+++ linux-2.6.25.perfctr26/include/asm-arm/processor.h 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/include/asm-arm/processor.h 2008-06-22 15:17:34.000000000 +0200
@@ -50,6 +50,10 @@ struct thread_struct {
unsigned long error_code;
/* debugging */
@@ -310,7 +328,7 @@
#define INIT_THREAD { }
--- linux-2.6.25.perfctr26/include/asm-arm/system.h.~1~ 2008-04-17 18:22:35.000000000 +0200
-+++ linux-2.6.25.perfctr26/include/asm-arm/system.h 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/include/asm-arm/system.h 2008-06-22 15:17:34.000000000 +0200
@@ -264,7 +264,9 @@ extern struct task_struct *__switch_to(s
#define switch_to(prev,next,last) \
@@ -322,7 +340,7 @@
#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
--- linux-2.6.25.perfctr26/include/asm-powerpc/processor.h.~1~ 2008-04-17 18:22:36.000000000 +0200
-+++ linux-2.6.25.perfctr26/include/asm-powerpc/processor.h 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/include/asm-powerpc/processor.h 2008-06-22 15:17:34.000000000 +0200
@@ -177,6 +177,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
@@ -334,7 +352,7 @@
#define ARCH_MIN_TASKALIGN 16
--- linux-2.6.25.perfctr26/include/asm-x86/hw_irq_64.h.~1~ 2008-04-17 18:22:36.000000000 +0200
-+++ linux-2.6.25.perfctr26/include/asm-x86/hw_irq_64.h 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/include/asm-x86/hw_irq_64.h 2008-06-22 15:17:34.000000000 +0200
@@ -84,14 +84,15 @@
* sources per level' errata.
*/
@@ -354,7 +372,7 @@
#ifndef __ASSEMBLY__
--- linux-2.6.25.perfctr26/include/asm-x86/irq_64.h.~1~ 2008-01-25 12:31:58.000000000 +0100
-+++ linux-2.6.25.perfctr26/include/asm-x86/irq_64.h 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/include/asm-x86/irq_64.h 2008-06-22 15:17:34.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -365,7 +383,7 @@
#define NR_IRQS (NR_VECTORS + (32 *NR_CPUS))
#define NR_IRQ_VECTORS NR_IRQS
--- linux-2.6.25.perfctr26/include/asm-x86/mach-default/irq_vectors.h.~1~ 2008-01-25 12:31:58.000000000 +0100
-+++ linux-2.6.25.perfctr26/include/asm-x86/mach-default/irq_vectors.h 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/include/asm-x86/mach-default/irq_vectors.h 2008-06-22 15:17:34.000000000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -385,7 +403,7 @@
#define TIMER_IRQ 0
--- linux-2.6.25.perfctr26/include/asm-x86/mach-visws/irq_vectors.h.~1~ 2008-01-25 12:31:58.000000000 +0100
-+++ linux-2.6.25.perfctr26/include/asm-x86/mach-visws/irq_vectors.h 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/include/asm-x86/mach-visws/irq_vectors.h 2008-06-22 15:17:34.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -405,7 +423,7 @@
#define TIMER_IRQ 0
--- linux-2.6.25.perfctr26/include/asm-x86/processor.h.~1~ 2008-04-17 18:22:36.000000000 +0200
-+++ linux-2.6.25.perfctr26/include/asm-x86/processor.h 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/include/asm-x86/processor.h 2008-06-22 15:17:34.000000000 +0200
@@ -349,6 +349,8 @@ struct thread_struct {
unsigned long iopl;
/* max allowed port in the bitmap, in bytes: */
@@ -416,7 +434,7 @@
unsigned long debugctlmsr;
/* Debug Store - if not 0 points to a DS Save Area configuration;
--- linux-2.6.25.perfctr26/include/asm-x86/system.h.~1~ 2008-04-17 18:22:36.000000000 +0200
-+++ linux-2.6.25.perfctr26/include/asm-x86/system.h 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/include/asm-x86/system.h 2008-06-22 15:17:34.000000000 +0200
@@ -29,6 +29,7 @@ struct task_struct *__switch_to(struct t
*/
#define switch_to(prev, next, last) do { \
@@ -446,7 +464,7 @@
#ifdef __KERNEL__
--- linux-2.6.25.perfctr26/kernel/exit.c.~1~ 2008-04-17 18:22:36.000000000 +0200
-+++ linux-2.6.25.perfctr26/kernel/exit.c 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/kernel/exit.c 2008-06-22 15:17:34.000000000 +0200
@@ -28,6 +28,7 @@
#include <linux/proc_fs.h>
#include <linux/kthread.h>
@@ -464,7 +482,7 @@
release_thread(p);
call_rcu(&p->rcu, delayed_put_task_struct);
--- linux-2.6.25.perfctr26/kernel/sched.c.~1~ 2008-04-17 18:22:36.000000000 +0200
-+++ linux-2.6.25.perfctr26/kernel/sched.c 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/kernel/sched.c 2008-06-22 15:17:34.000000000 +0200
@@ -54,6 +54,7 @@
#include <linux/cpu.h>
#include <linux/cpuset.h>
@@ -483,7 +501,7 @@
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
--- linux-2.6.25.perfctr26/kernel/timer.c.~1~ 2008-04-17 18:22:36.000000000 +0200
-+++ linux-2.6.25.perfctr26/kernel/timer.c 2008-04-17 18:41:06.000000000 +0200
++++ linux-2.6.25.perfctr26/kernel/timer.c 2008-06-22 15:17:34.000000000 +0200
@@ -33,6 +33,7 @@
#include <linux/jiffies.h>
#include <linux/posix-timers.h>
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.5 b/src/perfctr-2.6.x/patches/patch-kernel-2.6.5
index f5183fc4b25584ebc5636ccbcffc6dcf23543777..fd541e557764c53f5b721d937a8950bfc02a4950 100755
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.5
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.5
@@ -1,16 +1,21 @@
---- linux-2.6.5-perfctr/CREDITS.~1~ 2004-04-04 13:49:10.000000000 +0200
-+++ linux-2.6.5-perfctr/CREDITS 2004-04-04 14:01:31.000000000 +0200
-@@ -2513,6 +2513,7 @@
- E: mikpe@csd.uu.se
- W: http://www.csd.uu.se/~mikpe/
+--- linux-2.6.5.perfctr26/CREDITS.~1~ 2008-06-22 22:08:43.000000000 +0200
++++ linux-2.6.5.perfctr26/CREDITS 2008-06-22 22:11:07.061321000 +0200
+@@ -2510,9 +2510,10 @@ S: Ottawa, Ontario
+ S: Canada K2P 0X8
+
+ N: Mikael Pettersson
+-E: mikpe@csd.uu.se
+-W: http://www.csd.uu.se/~mikpe/
++E: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/
D: Miscellaneous fixes
+D: Performance-monitoring counters driver
N: Reed H. Petty
E: rhp@draper.net
---- linux-2.6.5-perfctr/Documentation/ioctl-number.txt.~1~ 2004-03-11 14:01:25.000000000 +0100
-+++ linux-2.6.5-perfctr/Documentation/ioctl-number.txt 2004-04-04 14:01:31.000000000 +0200
-@@ -187,5 +187,7 @@
+--- linux-2.6.5.perfctr26/Documentation/ioctl-number.txt.~1~ 2008-06-22 21:52:21.000000000 +0200
++++ linux-2.6.5.perfctr26/Documentation/ioctl-number.txt 2008-06-22 22:11:02.011321000 +0200
+@@ -187,5 +187,7 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
<mailto:michael.klein@puffin.lb.shuttle.de>
@@ -18,24 +23,24 @@
+ <mailto:mikpe@csd.uu.se>
0xDD 00-3F ZFCP device driver see drivers/s390/scsi/
<mailto:aherrman@de.ibm.com>
---- linux-2.6.5-perfctr/MAINTAINERS.~1~ 2004-04-04 13:49:10.000000000 +0200
-+++ linux-2.6.5-perfctr/MAINTAINERS 2004-04-04 14:01:31.000000000 +0200
-@@ -1603,6 +1603,12 @@
+--- linux-2.6.5.perfctr26/MAINTAINERS.~1~ 2008-06-22 22:08:43.000000000 +0200
++++ linux-2.6.5.perfctr26/MAINTAINERS 2008-06-22 22:11:07.061321000 +0200
+@@ -1603,6 +1603,12 @@ M: george@mvista.com
L: linux-net@vger.kernel.org
S: Supported
+PERFORMANCE-MONITORING COUNTERS DRIVER
+P: Mikael Pettersson
-+M: mikpe@csd.uu.se
-+W: http://www.csd.uu.se/~mikpe/linux/perfctr/
++M: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
+S: Maintained
+
PNP SUPPORT
P: Adam Belay
M: ambx1@neo.rr.com
---- linux-2.6.5-perfctr/arch/i386/Kconfig.~1~ 2004-04-04 13:49:10.000000000 +0200
-+++ linux-2.6.5-perfctr/arch/i386/Kconfig 2004-04-04 14:01:31.000000000 +0200
-@@ -847,6 +847,8 @@
+--- linux-2.6.5.perfctr26/arch/i386/Kconfig.~1~ 2008-06-22 22:08:43.000000000 +0200
++++ linux-2.6.5.perfctr26/arch/i386/Kconfig 2008-06-22 22:11:02.011321000 +0200
+@@ -847,6 +847,8 @@ config REGPARM
generate incorrect output with certain kernel constructs when
-mregparm=3 is used.
@@ -44,9 +49,9 @@
endmenu
---- linux-2.6.5-perfctr/arch/i386/kernel/entry.S.~1~ 2004-03-11 14:01:25.000000000 +0100
-+++ linux-2.6.5-perfctr/arch/i386/kernel/entry.S 2004-04-04 14:01:31.000000000 +0200
-@@ -412,6 +412,16 @@
+--- linux-2.6.5.perfctr26/arch/i386/kernel/entry.S.~1~ 2008-06-22 22:08:43.000000000 +0200
++++ linux-2.6.5.perfctr26/arch/i386/kernel/entry.S 2008-06-22 22:11:02.011321000 +0200
+@@ -412,6 +412,16 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -63,8 +68,8 @@
ENTRY(divide_error)
pushl $0 # no error code
pushl $do_divide_error
---- linux-2.6.5-perfctr/arch/i386/kernel/i8259.c.~1~ 2004-03-11 14:01:25.000000000 +0100
-+++ linux-2.6.5-perfctr/arch/i386/kernel/i8259.c 2004-04-04 14:01:31.000000000 +0200
+--- linux-2.6.5.perfctr26/arch/i386/kernel/i8259.c.~1~ 2008-06-22 22:08:43.000000000 +0200
++++ linux-2.6.5.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 22:11:02.011321000 +0200
@@ -23,6 +23,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -73,7 +78,7 @@
#include <linux/irq.h>
-@@ -432,6 +433,8 @@
+@@ -432,6 +433,8 @@ void __init init_IRQ(void)
*/
intr_init_hook();
@@ -82,8 +87,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.5-perfctr/arch/i386/kernel/process.c.~1~ 2004-04-04 13:49:10.000000000 +0200
-+++ linux-2.6.5-perfctr/arch/i386/kernel/process.c 2004-04-04 14:01:31.000000000 +0200
+--- linux-2.6.5.perfctr26/arch/i386/kernel/process.c.~1~ 2008-06-22 22:08:43.000000000 +0200
++++ linux-2.6.5.perfctr26/arch/i386/kernel/process.c 2008-06-22 22:11:02.011321000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -92,7 +97,7 @@
#include <linux/mc146818rtc.h>
#include <linux/module.h>
#include <linux/kallsyms.h>
-@@ -296,6 +297,7 @@
+@@ -296,6 +297,7 @@ void exit_thread(void)
kfree(tsk->thread.io_bitmap_ptr);
tsk->thread.io_bitmap_ptr = NULL;
}
@@ -100,25 +105,16 @@
}
void flush_thread(void)
-@@ -358,6 +360,8 @@
+@@ -358,6 +360,8 @@ int copy_thread(int nr, unsigned long cl
savesegment(fs,p->thread.fs);
savesegment(gs,p->thread.gs);
-+ perfctr_copy_thread(&p->thread);
++ perfctr_copy_task(p, regs);
+
tsk = current;
if (unlikely(NULL != tsk->thread.io_bitmap_ptr)) {
p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
-@@ -503,6 +507,8 @@
-
- /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */
-
-+ perfctr_suspend_thread(prev);
-+
- __unlazy_fpu(prev_p);
-
- /*
-@@ -565,6 +571,9 @@
+@@ -565,6 +569,9 @@ struct task_struct fastcall * __switch_t
*/
tss->io_bitmap_base = INVALID_IO_BITMAP_OFFSET;
}
@@ -128,9 +124,9 @@
return prev_p;
}
---- linux-2.6.5-perfctr/arch/ppc/Kconfig.~1~ 2004-04-04 13:49:10.000000000 +0200
-+++ linux-2.6.5-perfctr/arch/ppc/Kconfig 2004-04-04 14:01:31.000000000 +0200
-@@ -214,6 +214,8 @@
+--- linux-2.6.5.perfctr26/arch/ppc/Kconfig.~1~ 2008-06-22 22:08:43.000000000 +0200
++++ linux-2.6.5.perfctr26/arch/ppc/Kconfig 2008-06-22 22:11:02.011321000 +0200
+@@ -214,6 +214,8 @@ config NOT_COHERENT_CACHE
depends on 4xx || 8xx
default y
@@ -139,8 +135,22 @@
endmenu
menu "Platform options"
---- linux-2.6.5-perfctr/arch/ppc/kernel/process.c.~1~ 2004-04-04 13:49:10.000000000 +0200
-+++ linux-2.6.5-perfctr/arch/ppc/kernel/process.c 2004-04-04 14:01:31.000000000 +0200
+--- linux-2.6.5.perfctr26/arch/ppc/kernel/head.S.~1~ 2008-06-22 22:08:43.000000000 +0200
++++ linux-2.6.5.perfctr26/arch/ppc/kernel/head.S 2008-06-22 22:11:02.021321000 +0200
+@@ -502,7 +502,11 @@ Trap_0f:
+ #endif
+ EXCEPTION_PROLOG
+ addi r3,r1,STACK_FRAME_OVERHEAD
++#ifdef CONFIG_PERFCTR_INTERRUPT_SUPPORT
++ EXC_XFER_EE(0xf00, do_perfctr_interrupt)
++#else
+ EXC_XFER_EE(0xf00, UnknownException)
++#endif
+
+ /*
+ * Handle TLB miss for instruction on 603/603e.
+--- linux-2.6.5.perfctr26/arch/ppc/kernel/process.c.~1~ 2008-06-22 22:08:43.000000000 +0200
++++ linux-2.6.5.perfctr26/arch/ppc/kernel/process.c 2008-06-22 22:11:02.021321000 +0200
@@ -35,6 +35,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -149,7 +159,7 @@
#include <asm/pgtable.h>
#include <asm/uaccess.h>
-@@ -253,7 +254,9 @@
+@@ -253,7 +254,9 @@ struct task_struct *__switch_to(struct t
new->thread.regs->msr |= MSR_VEC;
new_thread = &new->thread;
old_thread = ¤t->thread;
@@ -159,7 +169,7 @@
local_irq_restore(s);
return last;
}
-@@ -312,6 +315,7 @@
+@@ -312,6 +315,7 @@ void exit_thread(void)
last_task_used_math = NULL;
if (last_task_used_altivec == current)
last_task_used_altivec = NULL;
@@ -167,18 +177,18 @@
}
void flush_thread(void)
-@@ -398,6 +402,8 @@
+@@ -398,6 +402,8 @@ copy_thread(int nr, unsigned long clone_
p->thread.last_syscall = -1;
-+ perfctr_copy_thread(&p->thread);
++ perfctr_copy_task(p, regs);
+
return 0;
}
---- linux-2.6.5-perfctr/arch/x86_64/Kconfig.~1~ 2004-04-04 13:49:10.000000000 +0200
-+++ linux-2.6.5-perfctr/arch/x86_64/Kconfig 2004-04-04 14:01:31.000000000 +0200
-@@ -307,6 +307,8 @@
+--- linux-2.6.5.perfctr26/arch/x86_64/Kconfig.~1~ 2008-06-22 22:08:43.000000000 +0200
++++ linux-2.6.5.perfctr26/arch/x86_64/Kconfig 2008-06-22 22:11:02.021321000 +0200
+@@ -307,6 +307,8 @@ config X86_MCE
bool
default y
@@ -187,9 +197,9 @@
endmenu
---- linux-2.6.5-perfctr/arch/x86_64/kernel/entry.S.~1~ 2004-04-04 13:49:10.000000000 +0200
-+++ linux-2.6.5-perfctr/arch/x86_64/kernel/entry.S 2004-04-04 14:01:31.000000000 +0200
-@@ -556,6 +556,11 @@
+--- linux-2.6.5.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2008-06-22 22:08:43.000000000 +0200
++++ linux-2.6.5.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 22:11:02.021321000 +0200
+@@ -556,6 +556,11 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
#endif
@@ -197,12 +207,12 @@
+ENTRY(perfctr_interrupt)
+ apicinterrupt LOCAL_PERFCTR_VECTOR,smp_perfctr_interrupt
+#endif
-+
++
/*
* Exception entry points.
*/
---- linux-2.6.5-perfctr/arch/x86_64/kernel/i8259.c.~1~ 2004-03-11 14:01:27.000000000 +0100
-+++ linux-2.6.5-perfctr/arch/x86_64/kernel/i8259.c 2004-04-04 14:01:31.000000000 +0200
+--- linux-2.6.5.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2008-06-22 22:08:43.000000000 +0200
++++ linux-2.6.5.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 22:11:02.021321000 +0200
@@ -23,6 +23,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -211,7 +221,7 @@
#include <linux/irq.h>
-@@ -484,6 +485,8 @@
+@@ -484,6 +485,8 @@ void __init init_IRQ(void)
set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
#endif
@@ -220,8 +230,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.5-perfctr/arch/x86_64/kernel/process.c.~1~ 2004-04-04 13:49:10.000000000 +0200
-+++ linux-2.6.5-perfctr/arch/x86_64/kernel/process.c 2004-04-04 14:01:31.000000000 +0200
+--- linux-2.6.5.perfctr26/arch/x86_64/kernel/process.c.~1~ 2008-06-22 22:08:43.000000000 +0200
++++ linux-2.6.5.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 22:11:02.021321000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/irq.h>
@@ -230,7 +240,7 @@
#include <linux/version.h>
#include <asm/uaccess.h>
-@@ -261,6 +262,7 @@
+@@ -261,6 +262,7 @@ void exit_thread(void)
(init_tss + smp_processor_id())->io_bitmap_base =
INVALID_IO_BITMAP_OFFSET;
}
@@ -238,25 +248,16 @@
}
void flush_thread(void)
-@@ -364,6 +366,8 @@
+@@ -364,6 +366,8 @@ int copy_thread(int nr, unsigned long cl
asm("movl %%es,%0" : "=m" (p->thread.es));
asm("movl %%ds,%0" : "=m" (p->thread.ds));
-+ perfctr_copy_thread(&p->thread);
++ perfctr_copy_task(p, regs);
+
if (unlikely(me->thread.io_bitmap_ptr != NULL)) {
p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
if (!p->thread.io_bitmap_ptr)
-@@ -410,6 +414,8 @@
- int cpu = smp_processor_id();
- struct tss_struct *tss = init_tss + cpu;
-
-+ perfctr_suspend_thread(prev);
-+
- unlazy_fpu(prev_p);
-
- /*
-@@ -513,6 +519,8 @@
+@@ -513,6 +517,8 @@ struct task_struct *__switch_to(struct t
}
}
@@ -265,17 +266,35 @@
return prev_p;
}
---- linux-2.6.5-perfctr/drivers/Makefile.~1~ 2004-04-04 13:49:10.000000000 +0200
-+++ linux-2.6.5-perfctr/drivers/Makefile 2004-04-04 14:01:31.000000000 +0200
-@@ -49,4 +49,5 @@
+--- linux-2.6.5.perfctr26/drivers/Makefile.~1~ 2008-06-22 21:52:21.000000000 +0200
++++ linux-2.6.5.perfctr26/drivers/Makefile 2008-06-22 22:11:02.021321000 +0200
+@@ -49,4 +49,5 @@ obj-$(CONFIG_ISDN) += isdn/
obj-$(CONFIG_MCA) += mca/
obj-$(CONFIG_EISA) += eisa/
obj-$(CONFIG_CPU_FREQ) += cpufreq/
+obj-$(CONFIG_KPERFCTR) += perfctr/
obj-y += firmware/
---- linux-2.6.5-perfctr/include/asm-i386/apic.h.~1~ 2004-02-18 11:09:53.000000000 +0100
-+++ linux-2.6.5-perfctr/include/asm-i386/apic.h 2004-04-04 14:01:31.000000000 +0200
-@@ -99,6 +99,8 @@
+--- linux-2.6.5.perfctr26/fs/exec.c.~1~ 2008-06-22 22:08:44.000000000 +0200
++++ linux-2.6.5.perfctr26/fs/exec.c 2008-06-22 22:11:07.061321000 +0200
+@@ -46,6 +46,7 @@
+ #include <linux/security.h>
+ #include <linux/syscalls.h>
+ #include <linux/rmap-locking.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/pgalloc.h>
+@@ -830,6 +831,7 @@ int flush_old_exec(struct linux_binprm *
+ }
+ current->comm[i] = '\0';
+
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ if (bprm->e_uid != current->euid || bprm->e_gid != current->egid ||
+--- linux-2.6.5.perfctr26/include/asm-i386/apic.h.~1~ 2008-06-22 22:08:44.000000000 +0200
++++ linux-2.6.5.perfctr26/include/asm-i386/apic.h 2008-06-22 22:11:02.021321000 +0200
+@@ -99,6 +99,8 @@ extern unsigned int nmi_watchdog;
#define NMI_LOCAL_APIC 2
#define NMI_INVALID 3
@@ -284,8 +303,8 @@
#endif /* CONFIG_X86_LOCAL_APIC */
#endif /* __ASM_APIC_H */
---- linux-2.6.5-perfctr/include/asm-i386/mach-default/irq_vectors.h.~1~ 2004-01-09 13:19:11.000000000 +0100
-+++ linux-2.6.5-perfctr/include/asm-i386/mach-default/irq_vectors.h 2004-04-04 14:01:31.000000000 +0200
+--- linux-2.6.5.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2008-06-22 22:08:44.000000000 +0200
++++ linux-2.6.5.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 22:11:02.021321000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -304,8 +323,8 @@
#define TIMER_IRQ 0
---- linux-2.6.5-perfctr/include/asm-i386/mach-pc9800/irq_vectors.h.~1~ 2004-01-09 13:19:11.000000000 +0100
-+++ linux-2.6.5-perfctr/include/asm-i386/mach-pc9800/irq_vectors.h 2004-04-04 14:01:31.000000000 +0200
+--- linux-2.6.5.perfctr26/include/asm-i386/mach-pc9800/irq_vectors.h.~1~ 2008-06-22 21:52:22.000000000 +0200
++++ linux-2.6.5.perfctr26/include/asm-i386/mach-pc9800/irq_vectors.h 2008-06-22 22:11:02.021321000 +0200
@@ -59,14 +59,15 @@
* sources per level' errata.
*/
@@ -324,8 +343,8 @@
#define TIMER_IRQ 0
---- linux-2.6.5-perfctr/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2004-01-09 13:19:11.000000000 +0100
-+++ linux-2.6.5-perfctr/include/asm-i386/mach-visws/irq_vectors.h 2004-04-04 14:01:31.000000000 +0200
+--- linux-2.6.5.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.5.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 22:11:02.021321000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -344,9 +363,9 @@
#define TIMER_IRQ 0
---- linux-2.6.5-perfctr/include/asm-i386/processor.h.~1~ 2004-03-11 14:01:30.000000000 +0100
-+++ linux-2.6.5-perfctr/include/asm-i386/processor.h 2004-04-04 14:01:31.000000000 +0200
-@@ -425,6 +425,8 @@
+--- linux-2.6.5.perfctr26/include/asm-i386/processor.h.~1~ 2008-06-22 22:08:44.000000000 +0200
++++ linux-2.6.5.perfctr26/include/asm-i386/processor.h 2008-06-22 22:11:02.021321000 +0200
+@@ -425,6 +425,8 @@ struct thread_struct {
unsigned int saved_fs, saved_gs;
/* IO permissions */
unsigned long *io_bitmap_ptr;
@@ -355,19 +374,31 @@
};
#define INIT_THREAD { \
---- linux-2.6.5-perfctr/include/asm-ppc/processor.h.~1~ 2003-09-28 12:19:57.000000000 +0200
-+++ linux-2.6.5-perfctr/include/asm-ppc/processor.h 2004-04-04 14:01:31.000000000 +0200
-@@ -119,6 +119,7 @@
+--- linux-2.6.5.perfctr26/include/asm-i386/system.h.~1~ 2008-06-22 21:52:22.000000000 +0200
++++ linux-2.6.5.perfctr26/include/asm-i386/system.h 2008-06-22 22:11:02.021321000 +0200
+@@ -14,6 +14,7 @@ extern struct task_struct * FASTCALL(__s
+
+ #define switch_to(prev,next,last) do { \
+ unsigned long esi,edi; \
++ perfctr_suspend_thread(&(prev)->thread); \
+ asm volatile("pushfl\n\t" \
+ "pushl %%ebp\n\t" \
+ "movl %%esp,%0\n\t" /* save ESP */ \
+--- linux-2.6.5.perfctr26/include/asm-ppc/processor.h.~1~ 2008-06-22 22:08:44.000000000 +0200
++++ linux-2.6.5.perfctr26/include/asm-ppc/processor.h 2008-06-22 22:11:02.021321000 +0200
+@@ -119,6 +119,9 @@ struct thread_struct {
unsigned long vrsave;
int used_vr; /* set if process has used altivec */
#endif /* CONFIG_ALTIVEC */
++#ifdef CONFIG_PERFCTR_VIRTUAL
+ struct vperfctr *perfctr; /* performance counters */
++#endif
};
#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
---- linux-2.6.5-perfctr/include/asm-x86_64/apic.h.~1~ 2004-03-11 14:01:30.000000000 +0100
-+++ linux-2.6.5-perfctr/include/asm-x86_64/apic.h 2004-04-04 14:01:31.000000000 +0200
-@@ -95,6 +95,8 @@
+--- linux-2.6.5.perfctr26/include/asm-x86_64/apic.h.~1~ 2008-06-22 22:08:44.000000000 +0200
++++ linux-2.6.5.perfctr26/include/asm-x86_64/apic.h 2008-06-22 22:11:02.021321000 +0200
+@@ -95,6 +95,8 @@ extern unsigned int nmi_watchdog;
#define NMI_LOCAL_APIC 2
#define NMI_INVALID 3
@@ -376,9 +407,9 @@
#endif /* CONFIG_X86_LOCAL_APIC */
#define clustered_apic_mode 0
---- linux-2.6.5-perfctr/include/asm-x86_64/hw_irq.h.~1~ 2004-02-18 11:09:53.000000000 +0100
-+++ linux-2.6.5-perfctr/include/asm-x86_64/hw_irq.h 2004-04-04 14:01:31.000000000 +0200
-@@ -65,14 +65,15 @@
+--- linux-2.6.5.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2008-06-22 21:52:22.000000000 +0200
++++ linux-2.6.5.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 22:11:02.021321000 +0200
+@@ -65,14 +65,15 @@ struct hw_interrupt_type;
* sources per level' errata.
*/
#define LOCAL_TIMER_VECTOR 0xef
@@ -396,8 +427,8 @@
#ifndef __ASSEMBLY__
---- linux-2.6.5-perfctr/include/asm-x86_64/irq.h.~1~ 2004-01-09 13:19:11.000000000 +0100
-+++ linux-2.6.5-perfctr/include/asm-x86_64/irq.h 2004-04-04 14:01:31.000000000 +0200
+--- linux-2.6.5.perfctr26/include/asm-x86_64/irq.h.~1~ 2008-06-22 22:08:44.000000000 +0200
++++ linux-2.6.5.perfctr26/include/asm-x86_64/irq.h 2008-06-22 22:11:02.021321000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -407,9 +438,9 @@
#ifdef CONFIG_PCI_USE_VECTOR
#define NR_IRQS FIRST_SYSTEM_VECTOR
---- linux-2.6.5-perfctr/include/asm-x86_64/processor.h.~1~ 2004-04-04 13:49:11.000000000 +0200
-+++ linux-2.6.5-perfctr/include/asm-x86_64/processor.h 2004-04-04 14:01:31.000000000 +0200
-@@ -252,6 +252,8 @@
+--- linux-2.6.5.perfctr26/include/asm-x86_64/processor.h.~1~ 2008-06-22 22:08:44.000000000 +0200
++++ linux-2.6.5.perfctr26/include/asm-x86_64/processor.h 2008-06-22 22:11:02.021321000 +0200
+@@ -252,6 +252,8 @@ struct thread_struct {
unsigned long *io_bitmap_ptr;
/* cached TLS descriptors. */
u64 tls_array[GDT_ENTRY_TLS_ENTRIES];
@@ -418,8 +449,48 @@
};
#define INIT_THREAD {}
---- linux-2.6.5-perfctr/kernel/sched.c.~1~ 2004-04-04 13:49:11.000000000 +0200
-+++ linux-2.6.5-perfctr/kernel/sched.c 2004-04-04 14:01:31.000000000 +0200
+--- linux-2.6.5.perfctr26/include/asm-x86_64/system.h.~1~ 2008-06-22 21:43:09.000000000 +0200
++++ linux-2.6.5.perfctr26/include/asm-x86_64/system.h 2008-06-22 22:11:02.021321000 +0200
+@@ -26,7 +26,8 @@
+ #define __EXTRA_CLOBBER \
+ ,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
+
+-#define switch_to(prev,next,last) \
++#define switch_to(prev,next,last) do { \
++ perfctr_suspend_thread(&(prev)->thread); \
+ asm volatile(SAVE_CONTEXT \
+ "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */ \
+ "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */ \
+@@ -46,7 +47,8 @@
+ [tif_fork] "i" (TIF_FORK), \
+ [thread_info] "i" (offsetof(struct task_struct, thread_info)), \
+ [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent)) \
+- : "memory", "cc" __EXTRA_CLOBBER)
++ : "memory", "cc" __EXTRA_CLOBBER); \
++} while (0)
+
+ extern void load_gs_index(unsigned);
+
+--- linux-2.6.5.perfctr26/kernel/exit.c.~1~ 2008-06-22 22:08:44.000000000 +0200
++++ linux-2.6.5.perfctr26/kernel/exit.c 2008-06-22 22:11:02.021321000 +0200
+@@ -22,6 +22,7 @@
+ #include <linux/profile.h>
+ #include <linux/mount.h>
+ #include <linux/proc_fs.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/pgtable.h>
+@@ -95,6 +96,7 @@ repeat:
+ p->parent->cnswap += p->nswap + p->cnswap;
+ p->parent->cnvcsw += p->nvcsw + p->cnvcsw;
+ p->parent->cnivcsw += p->nivcsw + p->cnivcsw;
++ perfctr_release_task(p);
+ sched_exit(p);
+ write_unlock_irq(&tasklist_lock);
+ spin_unlock(&p->proc_lock);
+--- linux-2.6.5.perfctr26/kernel/sched.c.~1~ 2008-06-22 22:08:44.000000000 +0200
++++ linux-2.6.5.perfctr26/kernel/sched.c 2008-06-22 22:11:02.021321000 +0200
@@ -38,6 +38,7 @@
#include <linux/rcupdate.h>
#include <linux/cpu.h>
@@ -428,7 +499,7 @@
#include <linux/kthread.h>
#ifdef CONFIG_NUMA
-@@ -2716,6 +2717,8 @@
+@@ -2716,6 +2717,8 @@ int set_cpus_allowed(task_t *p, cpumask_
migration_req_t req;
runqueue_t *rq;
@@ -437,8 +508,8 @@
rq = task_rq_lock(p, &flags);
if (any_online_cpu(new_mask) == NR_CPUS) {
ret = -EINVAL;
---- linux-2.6.5-perfctr/kernel/timer.c.~1~ 2004-04-04 13:49:11.000000000 +0200
-+++ linux-2.6.5-perfctr/kernel/timer.c 2004-04-04 14:01:31.000000000 +0200
+--- linux-2.6.5.perfctr26/kernel/timer.c.~1~ 2008-06-22 22:08:44.000000000 +0200
++++ linux-2.6.5.perfctr26/kernel/timer.c 2008-06-22 22:11:02.021321000 +0200
@@ -31,6 +31,7 @@
#include <linux/time.h>
#include <linux/jiffies.h>
@@ -447,7 +518,7 @@
#include <asm/uaccess.h>
#include <asm/div64.h>
-@@ -731,6 +732,7 @@
+@@ -731,6 +732,7 @@ void update_one_process(struct task_stru
do_process_times(p, user, system);
do_it_virt(p, user);
do_it_prof(p);
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.5-7.276-suse b/src/perfctr-2.6.x/patches/patch-kernel-2.6.5-7.276-suse
index fb8048701ecc717e09bd8439a9a54005010a2407..7766e9b4b2b79a2ae558ec02eb7e469e172b0301 100644
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.5-7.276-suse
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.5-7.276-suse
@@ -1,15 +1,20 @@
--- linux-2.6.5-7.276.perfctr26/CREDITS.~1~ 2006-07-24 19:32:29.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/CREDITS 2007-09-09 18:40:56.010235528 +0200
-@@ -2522,6 +2522,7 @@ N: Mikael Pettersson
- E: mikpe@csd.uu.se
- W: http://www.csd.uu.se/~mikpe/
++++ linux-2.6.5-7.276.perfctr26/CREDITS 2008-06-22 22:40:33.000000000 +0200
+@@ -2519,9 +2519,10 @@ S: Ottawa, Ontario
+ S: Canada K2P 0X8
+
+ N: Mikael Pettersson
+-E: mikpe@csd.uu.se
+-W: http://www.csd.uu.se/~mikpe/
++E: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/
D: Miscellaneous fixes
+D: Performance-monitoring counters driver
N: Reed H. Petty
E: rhp@draper.net
--- linux-2.6.5-7.276.perfctr26/Documentation/ioctl-number.txt.~1~ 2004-04-04 05:38:18.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/Documentation/ioctl-number.txt 2007-09-09 18:47:06.315940504 +0200
++++ linux-2.6.5-7.276.perfctr26/Documentation/ioctl-number.txt 2008-06-22 22:40:27.000000000 +0200
@@ -187,5 +187,7 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -19,7 +24,7 @@
0xDD 00-3F ZFCP device driver see drivers/s390/scsi/
<mailto:aherrman@de.ibm.com>
--- linux-2.6.5-7.276.perfctr26/MAINTAINERS.~1~ 2006-07-24 19:32:43.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/MAINTAINERS 2007-09-09 18:47:37.914136848 +0200
++++ linux-2.6.5-7.276.perfctr26/MAINTAINERS 2008-06-22 22:40:33.000000000 +0200
@@ -1613,6 +1613,12 @@ M: george@mvista.com
L: linux-net@vger.kernel.org
S: Supported
@@ -27,14 +32,14 @@
+PERFORMANCE-MONITORING COUNTERS DRIVER
+P: Mikael Pettersson
+M: mikpe@it.uu.se
-+W: http://www.csd.uu.se/~mikpe/linux/perfctr/
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
+S: Maintained
+
PNP SUPPORT
P: Adam Belay
M: ambx1@neo.rr.com
--- linux-2.6.5-7.276.perfctr26/arch/i386/Kconfig.~1~ 2006-07-24 19:32:22.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/arch/i386/Kconfig 2007-09-09 18:40:56.011235376 +0200
++++ linux-2.6.5-7.276.perfctr26/arch/i386/Kconfig 2008-06-22 22:40:27.000000000 +0200
@@ -857,6 +857,8 @@ config REGPARM
generate incorrect output with certain kernel constructs when
-mregparm=3 is used.
@@ -45,7 +50,7 @@
menu "Special options"
--- linux-2.6.5-7.276.perfctr26/arch/i386/kernel/entry.S.~1~ 2006-07-24 19:32:29.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/arch/i386/kernel/entry.S 2007-09-09 18:40:56.011235376 +0200
++++ linux-2.6.5-7.276.perfctr26/arch/i386/kernel/entry.S 2008-06-22 22:40:27.000000000 +0200
@@ -444,6 +444,16 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -64,7 +69,7 @@
pushl $0 # no error code
pushl $do_divide_error
--- linux-2.6.5-7.276.perfctr26/arch/i386/kernel/i8259.c.~1~ 2006-07-24 19:32:08.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/arch/i386/kernel/i8259.c 2007-09-09 18:40:56.011235376 +0200
++++ linux-2.6.5-7.276.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 22:40:27.000000000 +0200
@@ -23,6 +23,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -83,7 +88,7 @@
* Set the clock to HZ Hz, we already have a valid
* vector now:
--- linux-2.6.5-7.276.perfctr26/arch/i386/kernel/process.c.~1~ 2006-07-24 19:32:43.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/arch/i386/kernel/process.c 2007-09-09 18:40:56.012235224 +0200
++++ linux-2.6.5-7.276.perfctr26/arch/i386/kernel/process.c 2008-06-22 22:40:27.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -120,7 +125,7 @@
}
--- linux-2.6.5-7.276.perfctr26/arch/ppc/Kconfig.~1~ 2006-07-24 19:32:22.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/arch/ppc/Kconfig 2007-09-09 18:40:56.013235072 +0200
++++ linux-2.6.5-7.276.perfctr26/arch/ppc/Kconfig 2008-06-22 22:40:27.000000000 +0200
@@ -214,6 +214,8 @@ config NOT_COHERENT_CACHE
depends on 4xx || 8xx
default y
@@ -131,7 +136,7 @@
menu "Platform options"
--- linux-2.6.5-7.276.perfctr26/arch/ppc/kernel/head.S.~1~ 2006-07-24 19:32:03.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/arch/ppc/kernel/head.S 2007-09-09 18:40:56.013235072 +0200
++++ linux-2.6.5-7.276.perfctr26/arch/ppc/kernel/head.S 2008-06-22 22:40:27.000000000 +0200
@@ -502,7 +502,11 @@ SystemCall:
Trap_0f:
EXCEPTION_PROLOG
@@ -145,7 +150,7 @@
/*
* Handle TLB miss for instruction on 603/603e.
--- linux-2.6.5-7.276.perfctr26/arch/ppc/kernel/process.c.~1~ 2006-07-24 19:32:29.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/arch/ppc/kernel/process.c 2007-09-09 18:40:56.013235072 +0200
++++ linux-2.6.5-7.276.perfctr26/arch/ppc/kernel/process.c 2008-06-22 22:40:27.000000000 +0200
@@ -36,6 +36,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -182,7 +187,7 @@
}
--- linux-2.6.5-7.276.perfctr26/arch/x86_64/Kconfig.~1~ 2006-07-24 19:32:43.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/arch/x86_64/Kconfig 2007-09-09 18:40:56.014234920 +0200
++++ linux-2.6.5-7.276.perfctr26/arch/x86_64/Kconfig 2008-06-22 22:40:27.000000000 +0200
@@ -332,6 +332,8 @@ config X86_MCE
bool
default y
@@ -193,7 +198,7 @@
--- linux-2.6.5-7.276.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2006-07-24 19:32:47.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/arch/x86_64/kernel/entry.S 2007-09-09 18:40:56.014234920 +0200
++++ linux-2.6.5-7.276.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 22:40:27.000000000 +0200
@@ -545,6 +545,11 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
#endif
@@ -207,7 +212,7 @@
* Exception entry points.
*/
--- linux-2.6.5-7.276.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2006-07-24 19:32:47.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/arch/x86_64/kernel/i8259.c 2007-09-09 18:40:56.014234920 +0200
++++ linux-2.6.5-7.276.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 22:40:27.000000000 +0200
@@ -23,6 +23,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -226,7 +231,7 @@
* Set the clock to HZ Hz, we already have a valid
* vector now:
--- linux-2.6.5-7.276.perfctr26/arch/x86_64/kernel/process.c.~1~ 2006-07-24 19:32:47.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/arch/x86_64/kernel/process.c 2007-09-09 18:40:56.015234768 +0200
++++ linux-2.6.5-7.276.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 22:40:27.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/irq.h>
@@ -262,7 +267,7 @@
}
--- linux-2.6.5-7.276.perfctr26/drivers/Makefile.~1~ 2006-07-24 19:32:47.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/drivers/Makefile 2007-09-09 18:40:56.015234768 +0200
++++ linux-2.6.5-7.276.perfctr26/drivers/Makefile 2008-06-22 22:40:27.000000000 +0200
@@ -51,6 +51,7 @@ obj-$(CONFIG_ISDN) += isdn/
obj-$(CONFIG_MCA) += mca/
obj-$(CONFIG_EISA) += eisa/
@@ -271,8 +276,26 @@
obj-$(CONFIG_INFINIBAND) += infiniband/
obj-$(CONFIG_BLK_DEV_SGIIOC4) += sn/
obj-y += firmware/
+--- linux-2.6.5-7.276.perfctr26/fs/exec.c.~1~ 2006-07-24 19:32:47.000000000 +0200
++++ linux-2.6.5-7.276.perfctr26/fs/exec.c 2008-06-22 22:40:33.000000000 +0200
+@@ -47,6 +47,7 @@
+ #include <linux/security.h>
+ #include <linux/syscalls.h>
+ #include <linux/objrmap.h>
++#include <linux/perfctr.h>
+ #include <linux/ckrm.h>
+ #include <linux/audit.h>
+ #include <linux/trigevent_hooks.h>
+@@ -889,6 +890,7 @@ int flush_old_exec(struct linux_binprm *
+ }
+ current->comm[i] = '\0';
+
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ if (bprm->e_uid != current->euid || bprm->e_gid != current->egid ||
--- linux-2.6.5-7.276.perfctr26/include/asm-i386/apic.h.~1~ 2006-07-24 19:32:43.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/include/asm-i386/apic.h 2007-09-09 18:40:56.015234768 +0200
++++ linux-2.6.5-7.276.perfctr26/include/asm-i386/apic.h 2008-06-22 22:40:27.000000000 +0200
@@ -101,6 +101,8 @@ extern unsigned int nmi_watchdog;
#define NMI_LOCAL_APIC 2
#define NMI_INVALID 3
@@ -283,7 +306,7 @@
#endif /* __ASM_APIC_H */
--- linux-2.6.5-7.276.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2006-07-24 19:32:43.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2007-09-09 18:44:08.952903784 +0200
++++ linux-2.6.5-7.276.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 22:40:27.000000000 +0200
@@ -55,14 +55,15 @@
* sources per level' errata.
*/
@@ -303,7 +326,7 @@
#define TIMER_IRQ 0
--- linux-2.6.5-7.276.perfctr26/include/asm-i386/mach-pc9800/irq_vectors.h.~1~ 2004-04-04 05:36:16.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/include/asm-i386/mach-pc9800/irq_vectors.h 2007-09-09 18:40:56.016234616 +0200
++++ linux-2.6.5-7.276.perfctr26/include/asm-i386/mach-pc9800/irq_vectors.h 2008-06-22 22:40:27.000000000 +0200
@@ -59,14 +59,15 @@
* sources per level' errata.
*/
@@ -323,7 +346,7 @@
#define TIMER_IRQ 0
--- linux-2.6.5-7.276.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2004-04-04 05:36:18.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2007-09-09 18:40:56.016234616 +0200
++++ linux-2.6.5-7.276.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 22:40:27.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -343,7 +366,7 @@
#define TIMER_IRQ 0
--- linux-2.6.5-7.276.perfctr26/include/asm-i386/processor.h.~1~ 2006-07-24 19:32:35.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/include/asm-i386/processor.h 2007-09-09 18:40:56.016234616 +0200
++++ linux-2.6.5-7.276.perfctr26/include/asm-i386/processor.h 2008-06-22 22:40:27.000000000 +0200
@@ -428,6 +428,8 @@ struct thread_struct {
unsigned int saved_fs, saved_gs;
/* IO permissions */
@@ -354,7 +377,7 @@
#define INIT_THREAD { \
--- linux-2.6.5-7.276.perfctr26/include/asm-i386/system.h.~1~ 2006-07-24 19:32:43.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/include/asm-i386/system.h 2007-09-09 18:40:56.016234616 +0200
++++ linux-2.6.5-7.276.perfctr26/include/asm-i386/system.h 2008-06-22 22:40:27.000000000 +0200
@@ -14,6 +14,7 @@ extern struct task_struct * FASTCALL(__s
#define switch_to(prev,next,last) do { \
@@ -364,7 +387,7 @@
"pushl %%ebp\n\t" \
"movl %%esp,%0\n\t" /* save ESP */ \
--- linux-2.6.5-7.276.perfctr26/include/asm-ppc/processor.h.~1~ 2006-07-24 19:32:11.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/include/asm-ppc/processor.h 2007-09-09 18:40:56.017234464 +0200
++++ linux-2.6.5-7.276.perfctr26/include/asm-ppc/processor.h 2008-06-22 22:40:27.000000000 +0200
@@ -119,6 +119,9 @@ struct thread_struct {
unsigned long vrsave;
int used_vr; /* set if process has used altivec */
@@ -376,7 +399,7 @@
#define ARCH_MIN_TASKALIGN 16
--- linux-2.6.5-7.276.perfctr26/include/asm-x86_64/apic.h.~1~ 2006-07-24 19:32:43.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/include/asm-x86_64/apic.h 2007-09-09 18:40:56.017234464 +0200
++++ linux-2.6.5-7.276.perfctr26/include/asm-x86_64/apic.h 2008-06-22 22:40:27.000000000 +0200
@@ -97,6 +97,8 @@ extern unsigned int nmi_watchdog;
#define NMI_LOCAL_APIC 2
#define NMI_INVALID 3
@@ -387,7 +410,7 @@
#define esr_disable 0
--- linux-2.6.5-7.276.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2006-07-24 19:32:43.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/include/asm-x86_64/hw_irq.h 2007-09-09 18:46:20.428916392 +0200
++++ linux-2.6.5-7.276.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 22:40:27.000000000 +0200
@@ -65,14 +65,15 @@ struct hw_interrupt_type;
* sources per level' errata.
*/
@@ -407,7 +430,7 @@
#ifndef __ASSEMBLY__
--- linux-2.6.5-7.276.perfctr26/include/asm-x86_64/irq.h.~1~ 2006-07-24 19:32:29.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/include/asm-x86_64/irq.h 2007-09-09 18:40:56.017234464 +0200
++++ linux-2.6.5-7.276.perfctr26/include/asm-x86_64/irq.h 2008-06-22 22:40:27.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -418,7 +441,7 @@
#ifdef CONFIG_PCI_USE_VECTOR
#define NR_IRQS FIRST_SYSTEM_VECTOR
--- linux-2.6.5-7.276.perfctr26/include/asm-x86_64/processor.h.~1~ 2006-07-24 19:32:40.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/include/asm-x86_64/processor.h 2007-09-09 18:40:56.018234312 +0200
++++ linux-2.6.5-7.276.perfctr26/include/asm-x86_64/processor.h 2008-06-22 22:40:27.000000000 +0200
@@ -261,6 +261,8 @@ struct thread_struct {
unsigned long *io_bitmap_ptr;
/* cached TLS descriptors. */
@@ -429,7 +452,7 @@
#define INIT_THREAD {}
--- linux-2.6.5-7.276.perfctr26/include/asm-x86_64/system.h.~1~ 2006-07-24 19:32:40.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/include/asm-x86_64/system.h 2007-09-09 18:40:56.018234312 +0200
++++ linux-2.6.5-7.276.perfctr26/include/asm-x86_64/system.h 2008-06-22 22:40:27.000000000 +0200
@@ -26,7 +26,8 @@
#define __EXTRA_CLOBBER \
,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
@@ -451,7 +474,7 @@
extern void load_gs_index(unsigned);
--- linux-2.6.5-7.276.perfctr26/include/linux/config.h.~1~ 2004-04-04 05:38:19.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/include/linux/config.h 2007-09-09 18:40:56.018234312 +0200
++++ linux-2.6.5-7.276.perfctr26/include/linux/config.h 2008-06-22 22:40:27.000000000 +0200
@@ -3,4 +3,7 @@
#include <linux/autoconf.h>
@@ -461,7 +484,7 @@
+
#endif
--- linux-2.6.5-7.276.perfctr26/kernel/exit.c.~1~ 2006-07-24 19:32:46.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/kernel/exit.c 2007-09-09 18:40:56.019234160 +0200
++++ linux-2.6.5-7.276.perfctr26/kernel/exit.c 2008-06-22 22:40:27.000000000 +0200
@@ -25,6 +25,7 @@
#include <linux/profile.h>
#include <linux/mount.h>
@@ -479,7 +502,7 @@
write_unlock_irq(&tasklist_lock);
spin_unlock(&p->proc_lock);
--- linux-2.6.5-7.276.perfctr26/kernel/sched.c.~1~ 2006-07-24 19:32:44.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/kernel/sched.c 2007-09-09 18:40:56.020234008 +0200
++++ linux-2.6.5-7.276.perfctr26/kernel/sched.c 2008-06-22 22:40:27.000000000 +0200
@@ -38,6 +38,7 @@
#include <linux/rcupdate.h>
#include <linux/cpu.h>
@@ -498,7 +521,7 @@
if (any_online_cpu(new_mask) == NR_CPUS) {
ret = -EINVAL;
--- linux-2.6.5-7.276.perfctr26/kernel/timer.c.~1~ 2006-07-24 19:32:41.000000000 +0200
-+++ linux-2.6.5-7.276.perfctr26/kernel/timer.c 2007-09-09 18:40:56.021233856 +0200
++++ linux-2.6.5-7.276.perfctr26/kernel/timer.c 2008-06-22 22:40:27.000000000 +0200
@@ -31,6 +31,7 @@
#include <linux/time.h>
#include <linux/jiffies.h>
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.6 b/src/perfctr-2.6.x/patches/patch-kernel-2.6.6
index 5e340c81977569e6bac1269d739f8804f52c2d1a..d349b063d1506e7d81624ffcdd4d5f01b9d1d703 100755
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.6
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.6
@@ -1,16 +1,21 @@
---- linux-2.6.6-perfctr/CREDITS.~1~ 2004-05-10 11:14:35.000000000 +0200
-+++ linux-2.6.6-perfctr/CREDITS 2004-05-10 11:40:56.000000000 +0200
-@@ -2527,6 +2527,7 @@
- E: mikpe@csd.uu.se
- W: http://www.csd.uu.se/~mikpe/
+--- linux-2.6.6.perfctr26/CREDITS.~1~ 2008-06-22 22:01:16.000000000 +0200
++++ linux-2.6.6.perfctr26/CREDITS 2008-06-22 22:03:12.251321000 +0200
+@@ -2524,9 +2524,10 @@ S: Ottawa, Ontario
+ S: Canada K2P 0X8
+
+ N: Mikael Pettersson
+-E: mikpe@csd.uu.se
+-W: http://www.csd.uu.se/~mikpe/
++E: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/
D: Miscellaneous fixes
+D: Performance-monitoring counters driver
N: Reed H. Petty
E: rhp@draper.net
---- linux-2.6.6-perfctr/Documentation/ioctl-number.txt.~1~ 2004-03-11 14:01:25.000000000 +0100
-+++ linux-2.6.6-perfctr/Documentation/ioctl-number.txt 2004-05-10 11:40:56.000000000 +0200
-@@ -187,5 +187,7 @@
+--- linux-2.6.6.perfctr26/Documentation/ioctl-number.txt.~1~ 2008-06-22 21:52:21.000000000 +0200
++++ linux-2.6.6.perfctr26/Documentation/ioctl-number.txt 2008-06-22 22:03:07.281321000 +0200
+@@ -187,5 +187,7 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
<mailto:michael.klein@puffin.lb.shuttle.de>
@@ -18,24 +23,24 @@
+ <mailto:mikpe@csd.uu.se>
0xDD 00-3F ZFCP device driver see drivers/s390/scsi/
<mailto:aherrman@de.ibm.com>
---- linux-2.6.6-perfctr/MAINTAINERS.~1~ 2004-05-10 11:14:35.000000000 +0200
-+++ linux-2.6.6-perfctr/MAINTAINERS 2004-05-10 11:40:56.000000000 +0200
-@@ -1619,6 +1619,12 @@
+--- linux-2.6.6.perfctr26/MAINTAINERS.~1~ 2008-06-22 22:01:16.000000000 +0200
++++ linux-2.6.6.perfctr26/MAINTAINERS 2008-06-22 22:03:12.251321000 +0200
+@@ -1619,6 +1619,12 @@ M: george@mvista.com
L: linux-net@vger.kernel.org
S: Supported
+PERFORMANCE-MONITORING COUNTERS DRIVER
+P: Mikael Pettersson
-+M: mikpe@csd.uu.se
-+W: http://www.csd.uu.se/~mikpe/linux/perfctr/
++M: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
+S: Maintained
+
PNP SUPPORT
P: Adam Belay
M: ambx1@neo.rr.com
---- linux-2.6.6-perfctr/arch/i386/Kconfig.~1~ 2004-05-10 11:14:35.000000000 +0200
-+++ linux-2.6.6-perfctr/arch/i386/Kconfig 2004-05-10 11:40:56.000000000 +0200
-@@ -851,6 +851,8 @@
+--- linux-2.6.6.perfctr26/arch/i386/Kconfig.~1~ 2008-06-22 22:01:16.000000000 +0200
++++ linux-2.6.6.perfctr26/arch/i386/Kconfig 2008-06-22 22:03:07.281321000 +0200
+@@ -851,6 +851,8 @@ config REGPARM
generate incorrect output with certain kernel constructs when
-mregparm=3 is used.
@@ -44,9 +49,9 @@
endmenu
---- linux-2.6.6-perfctr/arch/i386/kernel/entry.S.~1~ 2004-05-10 11:14:35.000000000 +0200
-+++ linux-2.6.6-perfctr/arch/i386/kernel/entry.S 2004-05-10 11:40:56.000000000 +0200
-@@ -412,6 +412,16 @@
+--- linux-2.6.6.perfctr26/arch/i386/kernel/entry.S.~1~ 2008-06-22 22:01:16.000000000 +0200
++++ linux-2.6.6.perfctr26/arch/i386/kernel/entry.S 2008-06-22 22:03:07.281321000 +0200
+@@ -412,6 +412,16 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -63,8 +68,8 @@
ENTRY(divide_error)
pushl $0 # no error code
pushl $do_divide_error
---- linux-2.6.6-perfctr/arch/i386/kernel/i8259.c.~1~ 2004-05-10 11:14:35.000000000 +0200
-+++ linux-2.6.6-perfctr/arch/i386/kernel/i8259.c 2004-05-10 11:40:56.000000000 +0200
+--- linux-2.6.6.perfctr26/arch/i386/kernel/i8259.c.~1~ 2008-06-22 21:52:21.000000000 +0200
++++ linux-2.6.6.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 22:03:07.281321000 +0200
@@ -23,6 +23,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -73,7 +78,7 @@
#include <linux/irq.h>
-@@ -432,6 +433,8 @@
+@@ -432,6 +433,8 @@ void __init init_IRQ(void)
*/
intr_init_hook();
@@ -82,8 +87,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.6-perfctr/arch/i386/kernel/process.c.~1~ 2004-05-10 11:14:35.000000000 +0200
-+++ linux-2.6.6-perfctr/arch/i386/kernel/process.c 2004-05-10 11:40:56.000000000 +0200
+--- linux-2.6.6.perfctr26/arch/i386/kernel/process.c.~1~ 2008-06-22 22:01:16.000000000 +0200
++++ linux-2.6.6.perfctr26/arch/i386/kernel/process.c 2008-06-22 22:03:07.281321000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -92,7 +97,7 @@
#include <linux/mc146818rtc.h>
#include <linux/module.h>
#include <linux/kallsyms.h>
-@@ -300,6 +301,7 @@
+@@ -300,6 +301,7 @@ void exit_thread(void)
tss->io_bitmap_base = INVALID_IO_BITMAP_OFFSET;
put_cpu();
}
@@ -100,25 +105,16 @@
}
void flush_thread(void)
-@@ -362,6 +364,8 @@
+@@ -362,6 +364,8 @@ int copy_thread(int nr, unsigned long cl
savesegment(fs,p->thread.fs);
savesegment(gs,p->thread.gs);
-+ perfctr_copy_thread(&p->thread);
++ perfctr_copy_task(p, regs);
+
tsk = current;
if (unlikely(NULL != tsk->thread.io_bitmap_ptr)) {
p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
-@@ -507,6 +511,8 @@
-
- /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */
-
-+ perfctr_suspend_thread(prev);
-+
- __unlazy_fpu(prev_p);
-
- /*
-@@ -569,6 +575,9 @@
+@@ -569,6 +573,9 @@ struct task_struct fastcall * __switch_t
*/
tss->io_bitmap_base = INVALID_IO_BITMAP_OFFSET;
}
@@ -128,9 +124,9 @@
return prev_p;
}
---- linux-2.6.6-perfctr/arch/ppc/Kconfig.~1~ 2004-05-10 11:14:36.000000000 +0200
-+++ linux-2.6.6-perfctr/arch/ppc/Kconfig 2004-05-10 11:40:56.000000000 +0200
-@@ -214,6 +214,8 @@
+--- linux-2.6.6.perfctr26/arch/ppc/Kconfig.~1~ 2008-06-22 22:01:16.000000000 +0200
++++ linux-2.6.6.perfctr26/arch/ppc/Kconfig 2008-06-22 22:03:07.281321000 +0200
+@@ -214,6 +214,8 @@ config NOT_COHERENT_CACHE
depends on 4xx || 8xx
default y
@@ -139,8 +135,45 @@
endmenu
menu "Platform options"
---- linux-2.6.6-perfctr/arch/ppc/kernel/process.c.~1~ 2004-05-10 11:14:36.000000000 +0200
-+++ linux-2.6.6-perfctr/arch/ppc/kernel/process.c 2004-05-10 11:40:56.000000000 +0200
+--- linux-2.6.6.perfctr26/arch/ppc/kernel/head.S.~1~ 2008-06-22 22:01:16.000000000 +0200
++++ linux-2.6.6.perfctr26/arch/ppc/kernel/head.S 2008-06-22 22:03:07.281321000 +0200
+@@ -496,14 +496,16 @@ SystemCall:
+ b Trap_0f
+
+ . = 0xf20
+-#ifdef CONFIG_ALTIVEC
+ b AltiVecUnavailable
+-#endif
+
+ Trap_0f:
+ EXCEPTION_PROLOG
+ addi r3,r1,STACK_FRAME_OVERHEAD
++#ifdef CONFIG_PERFCTR_INTERRUPT_SUPPORT
++ EXC_XFER_EE(0xf00, do_perfctr_interrupt)
++#else
+ EXC_XFER_EE(0xf00, UnknownException)
++#endif
+
+ /*
+ * Handle TLB miss for instruction on 603/603e.
+@@ -746,11 +748,14 @@ DataStoreTLBMiss:
+
+ . = 0x3000
+
+-#ifdef CONFIG_ALTIVEC
+ AltiVecUnavailable:
+ EXCEPTION_PROLOG
++#ifdef CONFIG_ALTIVEC
+ bne load_up_altivec /* if from user, just load it up */
+ EXC_XFER_EE_LITE(0xf20, KernelAltiVec)
++#else
++ addi r3,r1,STACK_FRAME_OVERHEAD
++ EXC_XFER_EE(0xf00, UnknownException)
+ #endif /* CONFIG_ALTIVEC */
+
+ #ifdef CONFIG_PPC64BRIDGE
+--- linux-2.6.6.perfctr26/arch/ppc/kernel/process.c.~1~ 2008-06-22 22:01:16.000000000 +0200
++++ linux-2.6.6.perfctr26/arch/ppc/kernel/process.c 2008-06-22 22:03:07.281321000 +0200
@@ -35,6 +35,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -149,7 +182,7 @@
#include <asm/pgtable.h>
#include <asm/uaccess.h>
-@@ -253,7 +254,9 @@
+@@ -253,7 +254,9 @@ struct task_struct *__switch_to(struct t
new->thread.regs->msr |= MSR_VEC;
new_thread = &new->thread;
old_thread = ¤t->thread;
@@ -159,7 +192,7 @@
local_irq_restore(s);
return last;
}
-@@ -322,6 +325,7 @@
+@@ -322,6 +325,7 @@ void exit_thread(void)
last_task_used_math = NULL;
if (last_task_used_altivec == current)
last_task_used_altivec = NULL;
@@ -167,18 +200,18 @@
}
void flush_thread(void)
-@@ -408,6 +412,8 @@
+@@ -408,6 +412,8 @@ copy_thread(int nr, unsigned long clone_
p->thread.last_syscall = -1;
-+ perfctr_copy_thread(&p->thread);
++ perfctr_copy_task(p, regs);
+
return 0;
}
---- linux-2.6.6-perfctr/arch/x86_64/Kconfig.~1~ 2004-05-10 11:14:36.000000000 +0200
-+++ linux-2.6.6-perfctr/arch/x86_64/Kconfig 2004-05-10 11:40:56.000000000 +0200
-@@ -309,6 +309,8 @@
+--- linux-2.6.6.perfctr26/arch/x86_64/Kconfig.~1~ 2008-06-22 22:01:16.000000000 +0200
++++ linux-2.6.6.perfctr26/arch/x86_64/Kconfig 2008-06-22 22:03:07.281321000 +0200
+@@ -309,6 +309,8 @@ config X86_MCE
bool
default y
@@ -187,9 +220,9 @@
endmenu
---- linux-2.6.6-perfctr/arch/x86_64/kernel/entry.S.~1~ 2004-05-10 11:14:36.000000000 +0200
-+++ linux-2.6.6-perfctr/arch/x86_64/kernel/entry.S 2004-05-10 11:40:56.000000000 +0200
-@@ -557,6 +557,11 @@
+--- linux-2.6.6.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2008-06-22 21:43:08.000000000 +0200
++++ linux-2.6.6.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 22:03:07.281321000 +0200
+@@ -557,6 +557,11 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
#endif
@@ -197,12 +230,12 @@
+ENTRY(perfctr_interrupt)
+ apicinterrupt LOCAL_PERFCTR_VECTOR,smp_perfctr_interrupt
+#endif
-+
++
/*
* Exception entry points.
*/
---- linux-2.6.6-perfctr/arch/x86_64/kernel/i8259.c.~1~ 2004-05-10 11:14:36.000000000 +0200
-+++ linux-2.6.6-perfctr/arch/x86_64/kernel/i8259.c 2004-05-10 11:40:56.000000000 +0200
+--- linux-2.6.6.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2008-06-22 21:52:21.000000000 +0200
++++ linux-2.6.6.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 22:03:07.291321000 +0200
@@ -24,6 +24,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -211,7 +244,7 @@
#include <linux/irq.h>
-@@ -485,6 +486,8 @@
+@@ -485,6 +486,8 @@ void __init init_IRQ(void)
set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
#endif
@@ -220,8 +253,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.6-perfctr/arch/x86_64/kernel/process.c.~1~ 2004-05-10 11:14:36.000000000 +0200
-+++ linux-2.6.6-perfctr/arch/x86_64/kernel/process.c 2004-05-10 11:40:56.000000000 +0200
+--- linux-2.6.6.perfctr26/arch/x86_64/kernel/process.c.~1~ 2008-06-22 22:01:16.000000000 +0200
++++ linux-2.6.6.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 22:03:07.291321000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/irq.h>
@@ -230,7 +263,7 @@
#include <linux/version.h>
#include <asm/uaccess.h>
-@@ -262,6 +263,7 @@
+@@ -262,6 +263,7 @@ void exit_thread(void)
tss->io_bitmap_base = INVALID_IO_BITMAP_OFFSET;
put_cpu();
}
@@ -238,25 +271,16 @@
}
void flush_thread(void)
-@@ -365,6 +367,8 @@
+@@ -365,6 +367,8 @@ int copy_thread(int nr, unsigned long cl
asm("movl %%es,%0" : "=m" (p->thread.es));
asm("movl %%ds,%0" : "=m" (p->thread.ds));
-+ perfctr_copy_thread(&p->thread);
++ perfctr_copy_task(p, regs);
+
if (unlikely(me->thread.io_bitmap_ptr != NULL)) {
p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
if (!p->thread.io_bitmap_ptr)
-@@ -411,6 +415,8 @@
- int cpu = smp_processor_id();
- struct tss_struct *tss = init_tss + cpu;
-
-+ perfctr_suspend_thread(prev);
-+
- unlazy_fpu(prev_p);
-
- /*
-@@ -514,6 +520,8 @@
+@@ -514,6 +518,8 @@ struct task_struct *__switch_to(struct t
}
}
@@ -265,16 +289,34 @@
return prev_p;
}
---- linux-2.6.6-perfctr/drivers/Makefile.~1~ 2004-04-04 13:49:10.000000000 +0200
-+++ linux-2.6.6-perfctr/drivers/Makefile 2004-05-10 11:40:56.000000000 +0200
-@@ -49,4 +49,5 @@
+--- linux-2.6.6.perfctr26/drivers/Makefile.~1~ 2008-06-22 21:52:21.000000000 +0200
++++ linux-2.6.6.perfctr26/drivers/Makefile 2008-06-22 22:03:07.291321000 +0200
+@@ -49,4 +49,5 @@ obj-$(CONFIG_ISDN) += isdn/
obj-$(CONFIG_MCA) += mca/
obj-$(CONFIG_EISA) += eisa/
obj-$(CONFIG_CPU_FREQ) += cpufreq/
+obj-$(CONFIG_KPERFCTR) += perfctr/
obj-y += firmware/
---- linux-2.6.6-perfctr/include/asm-i386/mach-default/irq_vectors.h.~1~ 2004-05-10 11:14:37.000000000 +0200
-+++ linux-2.6.6-perfctr/include/asm-i386/mach-default/irq_vectors.h 2004-05-10 11:40:56.000000000 +0200
+--- linux-2.6.6.perfctr26/fs/exec.c.~1~ 2008-06-22 22:01:17.000000000 +0200
++++ linux-2.6.6.perfctr26/fs/exec.c 2008-06-22 22:03:12.261321000 +0200
+@@ -46,6 +46,7 @@
+ #include <linux/security.h>
+ #include <linux/syscalls.h>
+ #include <linux/rmap.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/pgalloc.h>
+@@ -845,6 +846,7 @@ int flush_old_exec(struct linux_binprm *
+ }
+ current->comm[i] = '\0';
+
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ if (bprm->e_uid != current->euid || bprm->e_gid != current->egid ||
+--- linux-2.6.6.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.6.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 22:03:07.291321000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -293,8 +335,8 @@
#define TIMER_IRQ 0
---- linux-2.6.6-perfctr/include/asm-i386/mach-pc9800/irq_vectors.h.~1~ 2004-01-09 13:19:11.000000000 +0100
-+++ linux-2.6.6-perfctr/include/asm-i386/mach-pc9800/irq_vectors.h 2004-05-10 11:40:56.000000000 +0200
+--- linux-2.6.6.perfctr26/include/asm-i386/mach-pc9800/irq_vectors.h.~1~ 2008-06-22 21:52:22.000000000 +0200
++++ linux-2.6.6.perfctr26/include/asm-i386/mach-pc9800/irq_vectors.h 2008-06-22 22:03:07.291321000 +0200
@@ -59,14 +59,15 @@
* sources per level' errata.
*/
@@ -313,8 +355,8 @@
#define TIMER_IRQ 0
---- linux-2.6.6-perfctr/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2004-01-09 13:19:11.000000000 +0100
-+++ linux-2.6.6-perfctr/include/asm-i386/mach-visws/irq_vectors.h 2004-05-10 11:40:56.000000000 +0200
+--- linux-2.6.6.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.6.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 22:03:07.291321000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -333,9 +375,9 @@
#define TIMER_IRQ 0
---- linux-2.6.6-perfctr/include/asm-i386/processor.h.~1~ 2004-05-10 11:14:37.000000000 +0200
-+++ linux-2.6.6-perfctr/include/asm-i386/processor.h 2004-05-10 11:40:56.000000000 +0200
-@@ -427,6 +427,8 @@
+--- linux-2.6.6.perfctr26/include/asm-i386/processor.h.~1~ 2008-06-22 22:01:17.000000000 +0200
++++ linux-2.6.6.perfctr26/include/asm-i386/processor.h 2008-06-22 22:03:07.291321000 +0200
+@@ -427,6 +427,8 @@ struct thread_struct {
unsigned int saved_fs, saved_gs;
/* IO permissions */
unsigned long *io_bitmap_ptr;
@@ -344,19 +386,31 @@
};
#define INIT_THREAD { \
---- linux-2.6.6-perfctr/include/asm-ppc/processor.h.~1~ 2004-05-10 11:14:37.000000000 +0200
-+++ linux-2.6.6-perfctr/include/asm-ppc/processor.h 2004-05-10 11:40:56.000000000 +0200
-@@ -119,6 +119,7 @@
+--- linux-2.6.6.perfctr26/include/asm-i386/system.h.~1~ 2008-06-22 21:52:22.000000000 +0200
++++ linux-2.6.6.perfctr26/include/asm-i386/system.h 2008-06-22 22:03:07.291321000 +0200
+@@ -14,6 +14,7 @@ extern struct task_struct * FASTCALL(__s
+
+ #define switch_to(prev,next,last) do { \
+ unsigned long esi,edi; \
++ perfctr_suspend_thread(&(prev)->thread); \
+ asm volatile("pushfl\n\t" \
+ "pushl %%ebp\n\t" \
+ "movl %%esp,%0\n\t" /* save ESP */ \
+--- linux-2.6.6.perfctr26/include/asm-ppc/processor.h.~1~ 2008-06-22 21:52:22.000000000 +0200
++++ linux-2.6.6.perfctr26/include/asm-ppc/processor.h 2008-06-22 22:03:07.291321000 +0200
+@@ -119,6 +119,9 @@ struct thread_struct {
unsigned long vrsave;
int used_vr; /* set if process has used altivec */
#endif /* CONFIG_ALTIVEC */
++#ifdef CONFIG_PERFCTR_VIRTUAL
+ struct vperfctr *perfctr; /* performance counters */
++#endif
};
#define ARCH_MIN_TASKALIGN 16
---- linux-2.6.6-perfctr/include/asm-x86_64/hw_irq.h.~1~ 2004-02-18 11:09:53.000000000 +0100
-+++ linux-2.6.6-perfctr/include/asm-x86_64/hw_irq.h 2004-05-10 11:40:56.000000000 +0200
-@@ -65,14 +65,15 @@
+--- linux-2.6.6.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2008-06-22 21:52:22.000000000 +0200
++++ linux-2.6.6.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 22:03:07.291321000 +0200
+@@ -65,14 +65,15 @@ struct hw_interrupt_type;
* sources per level' errata.
*/
#define LOCAL_TIMER_VECTOR 0xef
@@ -374,8 +428,8 @@
#ifndef __ASSEMBLY__
---- linux-2.6.6-perfctr/include/asm-x86_64/irq.h.~1~ 2004-05-10 11:14:37.000000000 +0200
-+++ linux-2.6.6-perfctr/include/asm-x86_64/irq.h 2004-05-10 11:40:56.000000000 +0200
+--- linux-2.6.6.perfctr26/include/asm-x86_64/irq.h.~1~ 2008-06-22 21:52:22.000000000 +0200
++++ linux-2.6.6.perfctr26/include/asm-x86_64/irq.h 2008-06-22 22:03:07.291321000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -385,9 +439,9 @@
#ifdef CONFIG_PCI_USE_VECTOR
#define NR_IRQS FIRST_SYSTEM_VECTOR
---- linux-2.6.6-perfctr/include/asm-x86_64/processor.h.~1~ 2004-05-10 11:14:37.000000000 +0200
-+++ linux-2.6.6-perfctr/include/asm-x86_64/processor.h 2004-05-10 11:40:56.000000000 +0200
-@@ -253,6 +253,8 @@
+--- linux-2.6.6.perfctr26/include/asm-x86_64/processor.h.~1~ 2008-06-22 22:01:17.000000000 +0200
++++ linux-2.6.6.perfctr26/include/asm-x86_64/processor.h 2008-06-22 22:03:07.291321000 +0200
+@@ -253,6 +253,8 @@ struct thread_struct {
unsigned long *io_bitmap_ptr;
/* cached TLS descriptors. */
u64 tls_array[GDT_ENTRY_TLS_ENTRIES];
@@ -396,8 +450,48 @@
};
#define INIT_THREAD {}
---- linux-2.6.6-perfctr/kernel/sched.c.~1~ 2004-05-10 11:14:37.000000000 +0200
-+++ linux-2.6.6-perfctr/kernel/sched.c 2004-05-10 11:40:56.000000000 +0200
+--- linux-2.6.6.perfctr26/include/asm-x86_64/system.h.~1~ 2008-06-22 21:43:09.000000000 +0200
++++ linux-2.6.6.perfctr26/include/asm-x86_64/system.h 2008-06-22 22:03:07.291321000 +0200
+@@ -26,7 +26,8 @@
+ #define __EXTRA_CLOBBER \
+ ,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
+
+-#define switch_to(prev,next,last) \
++#define switch_to(prev,next,last) do { \
++ perfctr_suspend_thread(&(prev)->thread); \
+ asm volatile(SAVE_CONTEXT \
+ "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */ \
+ "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */ \
+@@ -46,7 +47,8 @@
+ [tif_fork] "i" (TIF_FORK), \
+ [thread_info] "i" (offsetof(struct task_struct, thread_info)), \
+ [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent)) \
+- : "memory", "cc" __EXTRA_CLOBBER)
++ : "memory", "cc" __EXTRA_CLOBBER); \
++} while (0)
+
+ extern void load_gs_index(unsigned);
+
+--- linux-2.6.6.perfctr26/kernel/exit.c.~1~ 2008-06-22 22:01:17.000000000 +0200
++++ linux-2.6.6.perfctr26/kernel/exit.c 2008-06-22 22:03:07.291321000 +0200
+@@ -22,6 +22,7 @@
+ #include <linux/profile.h>
+ #include <linux/mount.h>
+ #include <linux/proc_fs.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/pgtable.h>
+@@ -94,6 +95,7 @@ repeat:
+ p->parent->cmaj_flt += p->maj_flt + p->cmaj_flt;
+ p->parent->cnvcsw += p->nvcsw + p->cnvcsw;
+ p->parent->cnivcsw += p->nivcsw + p->cnivcsw;
++ perfctr_release_task(p);
+ sched_exit(p);
+ write_unlock_irq(&tasklist_lock);
+ spin_unlock(&p->proc_lock);
+--- linux-2.6.6.perfctr26/kernel/sched.c.~1~ 2008-06-22 22:01:17.000000000 +0200
++++ linux-2.6.6.perfctr26/kernel/sched.c 2008-06-22 22:03:07.291321000 +0200
@@ -38,6 +38,7 @@
#include <linux/rcupdate.h>
#include <linux/cpu.h>
@@ -406,7 +500,7 @@
#include <linux/kthread.h>
#ifdef CONFIG_NUMA
-@@ -2726,6 +2727,8 @@
+@@ -2726,6 +2727,8 @@ int set_cpus_allowed(task_t *p, cpumask_
migration_req_t req;
runqueue_t *rq;
@@ -415,8 +509,8 @@
rq = task_rq_lock(p, &flags);
if (any_online_cpu(new_mask) == NR_CPUS) {
ret = -EINVAL;
---- linux-2.6.6-perfctr/kernel/timer.c.~1~ 2004-05-10 11:14:37.000000000 +0200
-+++ linux-2.6.6-perfctr/kernel/timer.c 2004-05-10 11:40:56.000000000 +0200
+--- linux-2.6.6.perfctr26/kernel/timer.c.~1~ 2008-06-22 22:01:17.000000000 +0200
++++ linux-2.6.6.perfctr26/kernel/timer.c 2008-06-22 22:03:07.291321000 +0200
@@ -31,6 +31,7 @@
#include <linux/time.h>
#include <linux/jiffies.h>
@@ -425,7 +519,7 @@
#include <asm/uaccess.h>
#include <asm/div64.h>
-@@ -800,6 +801,7 @@
+@@ -800,6 +801,7 @@ void update_one_process(struct task_stru
do_process_times(p, user, system);
do_it_virt(p, user);
do_it_prof(p);
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.7 b/src/perfctr-2.6.x/patches/patch-kernel-2.6.7
index 44f2431cf59d3e3db843675115cf191aac85938a..2d53a43042668a7b169936f9eff827aa2c0f54e0 100755
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.7
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.7
@@ -1,16 +1,21 @@
---- linux-2.6.7-perfctr/CREDITS.~1~ 2004-06-16 11:14:07.000000000 +0200
-+++ linux-2.6.7-perfctr/CREDITS 2004-06-16 11:31:12.836842949 +0200
-@@ -2527,6 +2527,7 @@
- E: mikpe@csd.uu.se
- W: http://www.csd.uu.se/~mikpe/
+--- linux-2.6.7.perfctr26/CREDITS.~1~ 2008-06-22 21:52:21.000000000 +0200
++++ linux-2.6.7.perfctr26/CREDITS 2008-06-22 21:54:46.651321000 +0200
+@@ -2524,9 +2524,10 @@ S: Ottawa, Ontario
+ S: Canada K2P 0X8
+
+ N: Mikael Pettersson
+-E: mikpe@csd.uu.se
+-W: http://www.csd.uu.se/~mikpe/
++E: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/
D: Miscellaneous fixes
+D: Performance-monitoring counters driver
N: Reed H. Petty
E: rhp@draper.net
---- linux-2.6.7-perfctr/Documentation/ioctl-number.txt.~1~ 2004-03-11 14:01:25.000000000 +0100
-+++ linux-2.6.7-perfctr/Documentation/ioctl-number.txt 2004-06-16 11:31:12.836842949 +0200
-@@ -187,5 +187,7 @@
+--- linux-2.6.7.perfctr26/Documentation/ioctl-number.txt.~1~ 2008-06-22 21:52:21.000000000 +0200
++++ linux-2.6.7.perfctr26/Documentation/ioctl-number.txt 2008-06-22 21:54:40.251321000 +0200
+@@ -187,5 +187,7 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
<mailto:michael.klein@puffin.lb.shuttle.de>
@@ -18,24 +23,24 @@
+ <mailto:mikpe@csd.uu.se>
0xDD 00-3F ZFCP device driver see drivers/s390/scsi/
<mailto:aherrman@de.ibm.com>
---- linux-2.6.7-perfctr/MAINTAINERS.~1~ 2004-06-16 11:14:07.000000000 +0200
-+++ linux-2.6.7-perfctr/MAINTAINERS 2004-06-16 11:31:12.846843099 +0200
-@@ -1615,6 +1615,12 @@
+--- linux-2.6.7.perfctr26/MAINTAINERS.~1~ 2008-06-22 21:52:21.000000000 +0200
++++ linux-2.6.7.perfctr26/MAINTAINERS 2008-06-22 21:54:46.651321000 +0200
+@@ -1615,6 +1615,12 @@ M: george@mvista.com
L: linux-net@vger.kernel.org
S: Supported
+PERFORMANCE-MONITORING COUNTERS DRIVER
+P: Mikael Pettersson
-+M: mikpe@csd.uu.se
-+W: http://www.csd.uu.se/~mikpe/linux/perfctr/
++M: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
+S: Maintained
+
PNP SUPPORT
P: Adam Belay
M: ambx1@neo.rr.com
---- linux-2.6.7-perfctr/arch/i386/Kconfig.~1~ 2004-06-16 11:14:08.000000000 +0200
-+++ linux-2.6.7-perfctr/arch/i386/Kconfig 2004-06-16 11:31:12.866843399 +0200
-@@ -864,6 +864,8 @@
+--- linux-2.6.7.perfctr26/arch/i386/Kconfig.~1~ 2008-06-22 21:52:21.000000000 +0200
++++ linux-2.6.7.perfctr26/arch/i386/Kconfig 2008-06-22 21:54:40.251321000 +0200
+@@ -864,6 +864,8 @@ config REGPARM
generate incorrect output with certain kernel constructs when
-mregparm=3 is used.
@@ -44,9 +49,9 @@
endmenu
---- linux-2.6.7-perfctr/arch/i386/kernel/entry.S.~1~ 2004-06-16 11:14:08.000000000 +0200
-+++ linux-2.6.7-perfctr/arch/i386/kernel/entry.S 2004-06-16 11:31:12.886843700 +0200
-@@ -406,6 +406,16 @@
+--- linux-2.6.7.perfctr26/arch/i386/kernel/entry.S.~1~ 2008-06-22 21:43:08.000000000 +0200
++++ linux-2.6.7.perfctr26/arch/i386/kernel/entry.S 2008-06-22 21:54:40.251321000 +0200
+@@ -406,6 +406,16 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -63,8 +68,8 @@
ENTRY(divide_error)
pushl $0 # no error code
pushl $do_divide_error
---- linux-2.6.7-perfctr/arch/i386/kernel/i8259.c.~1~ 2004-05-10 11:14:35.000000000 +0200
-+++ linux-2.6.7-perfctr/arch/i386/kernel/i8259.c 2004-06-16 11:31:12.896843850 +0200
+--- linux-2.6.7.perfctr26/arch/i386/kernel/i8259.c.~1~ 2008-06-22 21:52:21.000000000 +0200
++++ linux-2.6.7.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 21:54:40.261321000 +0200
@@ -23,6 +23,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -73,7 +78,7 @@
#include <linux/irq.h>
-@@ -432,6 +433,8 @@
+@@ -432,6 +433,8 @@ void __init init_IRQ(void)
*/
intr_init_hook();
@@ -82,8 +87,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.7-perfctr/arch/i386/kernel/process.c.~1~ 2004-06-16 11:14:08.000000000 +0200
-+++ linux-2.6.7-perfctr/arch/i386/kernel/process.c 2004-06-16 11:31:12.896843850 +0200
+--- linux-2.6.7.perfctr26/arch/i386/kernel/process.c.~1~ 2008-06-22 21:52:21.000000000 +0200
++++ linux-2.6.7.perfctr26/arch/i386/kernel/process.c 2008-06-22 21:54:40.261321000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -92,7 +97,7 @@
#include <linux/mc146818rtc.h>
#include <linux/module.h>
#include <linux/kallsyms.h>
-@@ -304,6 +305,7 @@
+@@ -304,6 +305,7 @@ void exit_thread(void)
tss->io_bitmap_base = INVALID_IO_BITMAP_OFFSET;
put_cpu();
}
@@ -100,25 +105,16 @@
}
void flush_thread(void)
-@@ -366,6 +368,8 @@
+@@ -366,6 +368,8 @@ int copy_thread(int nr, unsigned long cl
savesegment(fs,p->thread.fs);
savesegment(gs,p->thread.gs);
-+ perfctr_copy_thread(&p->thread);
++ perfctr_copy_task(p, regs);
+
tsk = current;
if (unlikely(NULL != tsk->thread.io_bitmap_ptr)) {
p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
-@@ -511,6 +515,8 @@
-
- /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */
-
-+ perfctr_suspend_thread(prev);
-+
- __unlazy_fpu(prev_p);
-
- /*
-@@ -573,6 +579,9 @@
+@@ -573,6 +577,9 @@ struct task_struct fastcall * __switch_t
*/
tss->io_bitmap_base = INVALID_IO_BITMAP_OFFSET;
}
@@ -128,9 +124,9 @@
return prev_p;
}
---- linux-2.6.7-perfctr/arch/ppc/Kconfig.~1~ 2004-06-16 11:14:09.000000000 +0200
-+++ linux-2.6.7-perfctr/arch/ppc/Kconfig 2004-06-16 11:31:12.906844000 +0200
-@@ -214,6 +214,8 @@
+--- linux-2.6.7.perfctr26/arch/ppc/Kconfig.~1~ 2008-06-22 21:52:21.000000000 +0200
++++ linux-2.6.7.perfctr26/arch/ppc/Kconfig 2008-06-22 21:54:40.261321000 +0200
+@@ -214,6 +214,8 @@ config NOT_COHERENT_CACHE
depends on 4xx || 8xx
default y
@@ -139,8 +135,22 @@
endmenu
menu "Platform options"
---- linux-2.6.7-perfctr/arch/ppc/kernel/process.c.~1~ 2004-06-16 11:14:09.000000000 +0200
-+++ linux-2.6.7-perfctr/arch/ppc/kernel/process.c 2004-06-16 11:31:12.926844301 +0200
+--- linux-2.6.7.perfctr26/arch/ppc/kernel/head.S.~1~ 2008-06-22 21:52:21.000000000 +0200
++++ linux-2.6.7.perfctr26/arch/ppc/kernel/head.S 2008-06-22 21:54:40.261321000 +0200
+@@ -502,7 +502,11 @@ SystemCall:
+ Trap_0f:
+ EXCEPTION_PROLOG
+ addi r3,r1,STACK_FRAME_OVERHEAD
++#ifdef CONFIG_PERFCTR_INTERRUPT_SUPPORT
++ EXC_XFER_EE(0xf00, do_perfctr_interrupt)
++#else
+ EXC_XFER_EE(0xf00, UnknownException)
++#endif
+
+ /*
+ * Handle TLB miss for instruction on 603/603e.
+--- linux-2.6.7.perfctr26/arch/ppc/kernel/process.c.~1~ 2008-06-22 21:52:21.000000000 +0200
++++ linux-2.6.7.perfctr26/arch/ppc/kernel/process.c 2008-06-22 21:54:40.261321000 +0200
@@ -35,6 +35,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -149,7 +159,7 @@
#include <asm/pgtable.h>
#include <asm/uaccess.h>
-@@ -253,7 +254,9 @@
+@@ -253,7 +254,9 @@ struct task_struct *__switch_to(struct t
new->thread.regs->msr |= MSR_VEC;
new_thread = &new->thread;
old_thread = ¤t->thread;
@@ -159,7 +169,7 @@
local_irq_restore(s);
return last;
}
-@@ -322,6 +325,7 @@
+@@ -322,6 +325,7 @@ void exit_thread(void)
last_task_used_math = NULL;
if (last_task_used_altivec == current)
last_task_used_altivec = NULL;
@@ -167,18 +177,18 @@
}
void flush_thread(void)
-@@ -408,6 +412,8 @@
+@@ -408,6 +412,8 @@ copy_thread(int nr, unsigned long clone_
p->thread.last_syscall = -1;
-+ perfctr_copy_thread(&p->thread);
++ perfctr_copy_task(p, regs);
+
return 0;
}
---- linux-2.6.7-perfctr/arch/x86_64/Kconfig.~1~ 2004-06-16 11:14:10.000000000 +0200
-+++ linux-2.6.7-perfctr/arch/x86_64/Kconfig 2004-06-16 11:31:12.936844451 +0200
-@@ -318,6 +318,8 @@
+--- linux-2.6.7.perfctr26/arch/x86_64/Kconfig.~1~ 2008-06-22 21:43:08.000000000 +0200
++++ linux-2.6.7.perfctr26/arch/x86_64/Kconfig 2008-06-22 21:54:40.261321000 +0200
+@@ -318,6 +318,8 @@ config X86_MCE
bool
default y
@@ -187,9 +197,9 @@
endmenu
---- linux-2.6.7-perfctr/arch/x86_64/kernel/entry.S.~1~ 2004-05-10 11:14:36.000000000 +0200
-+++ linux-2.6.7-perfctr/arch/x86_64/kernel/entry.S 2004-06-16 11:31:12.946844601 +0200
-@@ -557,6 +557,11 @@
+--- linux-2.6.7.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2008-06-22 21:43:08.000000000 +0200
++++ linux-2.6.7.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 21:54:40.261321000 +0200
+@@ -557,6 +557,11 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
#endif
@@ -197,12 +207,12 @@
+ENTRY(perfctr_interrupt)
+ apicinterrupt LOCAL_PERFCTR_VECTOR,smp_perfctr_interrupt
+#endif
-+
++
/*
* Exception entry points.
*/
---- linux-2.6.7-perfctr/arch/x86_64/kernel/i8259.c.~1~ 2004-05-10 11:14:36.000000000 +0200
-+++ linux-2.6.7-perfctr/arch/x86_64/kernel/i8259.c 2004-06-16 11:31:12.946844601 +0200
+--- linux-2.6.7.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2008-06-22 21:52:21.000000000 +0200
++++ linux-2.6.7.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 21:54:40.261321000 +0200
@@ -24,6 +24,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -211,7 +221,7 @@
#include <linux/irq.h>
-@@ -485,6 +486,8 @@
+@@ -485,6 +486,8 @@ void __init init_IRQ(void)
set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
#endif
@@ -220,8 +230,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.7-perfctr/arch/x86_64/kernel/process.c.~1~ 2004-06-16 11:14:10.000000000 +0200
-+++ linux-2.6.7-perfctr/arch/x86_64/kernel/process.c 2004-06-16 11:31:12.946844601 +0200
+--- linux-2.6.7.perfctr26/arch/x86_64/kernel/process.c.~1~ 2008-06-22 21:43:08.000000000 +0200
++++ linux-2.6.7.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 21:54:40.261321000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/irq.h>
@@ -230,7 +240,7 @@
#include <linux/version.h>
#include <asm/uaccess.h>
-@@ -262,6 +263,7 @@
+@@ -262,6 +263,7 @@ void exit_thread(void)
tss->io_bitmap_base = INVALID_IO_BITMAP_OFFSET;
put_cpu();
}
@@ -238,25 +248,16 @@
}
void flush_thread(void)
-@@ -365,6 +367,8 @@
+@@ -365,6 +367,8 @@ int copy_thread(int nr, unsigned long cl
asm("movl %%es,%0" : "=m" (p->thread.es));
asm("movl %%ds,%0" : "=m" (p->thread.ds));
-+ perfctr_copy_thread(&p->thread);
++ perfctr_copy_task(p, regs);
+
if (unlikely(me->thread.io_bitmap_ptr != NULL)) {
p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
if (!p->thread.io_bitmap_ptr)
-@@ -411,6 +415,8 @@
- int cpu = smp_processor_id();
- struct tss_struct *tss = init_tss + cpu;
-
-+ perfctr_suspend_thread(prev);
-+
- unlazy_fpu(prev_p);
-
- /*
-@@ -514,6 +520,8 @@
+@@ -514,6 +518,8 @@ struct task_struct *__switch_to(struct t
}
}
@@ -265,16 +266,34 @@
return prev_p;
}
---- linux-2.6.7-perfctr/drivers/Makefile.~1~ 2004-04-04 13:49:10.000000000 +0200
-+++ linux-2.6.7-perfctr/drivers/Makefile 2004-06-16 11:31:12.946844601 +0200
-@@ -49,4 +49,5 @@
+--- linux-2.6.7.perfctr26/drivers/Makefile.~1~ 2008-06-22 21:52:21.000000000 +0200
++++ linux-2.6.7.perfctr26/drivers/Makefile 2008-06-22 21:54:40.261321000 +0200
+@@ -49,4 +49,5 @@ obj-$(CONFIG_ISDN) += isdn/
obj-$(CONFIG_MCA) += mca/
obj-$(CONFIG_EISA) += eisa/
obj-$(CONFIG_CPU_FREQ) += cpufreq/
+obj-$(CONFIG_KPERFCTR) += perfctr/
obj-y += firmware/
---- linux-2.6.7-perfctr/include/asm-i386/mach-default/irq_vectors.h.~1~ 2004-05-10 11:14:37.000000000 +0200
-+++ linux-2.6.7-perfctr/include/asm-i386/mach-default/irq_vectors.h 2004-06-16 11:31:12.956844752 +0200
+--- linux-2.6.7.perfctr26/fs/exec.c.~1~ 2008-06-22 21:52:22.000000000 +0200
++++ linux-2.6.7.perfctr26/fs/exec.c 2008-06-22 21:54:46.651321000 +0200
+@@ -46,6 +46,7 @@
+ #include <linux/security.h>
+ #include <linux/syscalls.h>
+ #include <linux/rmap.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/pgalloc.h>
+@@ -836,6 +837,7 @@ int flush_old_exec(struct linux_binprm *
+ }
+ current->comm[i] = '\0';
+
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ if (bprm->e_uid != current->euid || bprm->e_gid != current->egid ||
+--- linux-2.6.7.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.7.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 21:54:40.261321000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -293,8 +312,8 @@
#define TIMER_IRQ 0
---- linux-2.6.7-perfctr/include/asm-i386/mach-pc9800/irq_vectors.h.~1~ 2004-01-09 13:19:11.000000000 +0100
-+++ linux-2.6.7-perfctr/include/asm-i386/mach-pc9800/irq_vectors.h 2004-06-16 11:31:12.966844902 +0200
+--- linux-2.6.7.perfctr26/include/asm-i386/mach-pc9800/irq_vectors.h.~1~ 2008-06-22 21:52:22.000000000 +0200
++++ linux-2.6.7.perfctr26/include/asm-i386/mach-pc9800/irq_vectors.h 2008-06-22 21:54:40.261321000 +0200
@@ -59,14 +59,15 @@
* sources per level' errata.
*/
@@ -313,8 +332,8 @@
#define TIMER_IRQ 0
---- linux-2.6.7-perfctr/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2004-01-09 13:19:11.000000000 +0100
-+++ linux-2.6.7-perfctr/include/asm-i386/mach-visws/irq_vectors.h 2004-06-16 11:31:12.966844902 +0200
+--- linux-2.6.7.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.7.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 21:54:40.261321000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -333,9 +352,9 @@
#define TIMER_IRQ 0
---- linux-2.6.7-perfctr/include/asm-i386/processor.h.~1~ 2004-06-16 11:14:23.000000000 +0200
-+++ linux-2.6.7-perfctr/include/asm-i386/processor.h 2004-06-16 11:31:12.976845052 +0200
-@@ -428,6 +428,8 @@
+--- linux-2.6.7.perfctr26/include/asm-i386/processor.h.~1~ 2008-06-22 21:52:22.000000000 +0200
++++ linux-2.6.7.perfctr26/include/asm-i386/processor.h 2008-06-22 21:54:40.261321000 +0200
+@@ -428,6 +428,8 @@ struct thread_struct {
unsigned int saved_fs, saved_gs;
/* IO permissions */
unsigned long *io_bitmap_ptr;
@@ -344,19 +363,31 @@
};
#define INIT_THREAD { \
---- linux-2.6.7-perfctr/include/asm-ppc/processor.h.~1~ 2004-05-10 11:14:37.000000000 +0200
-+++ linux-2.6.7-perfctr/include/asm-ppc/processor.h 2004-06-16 11:31:12.976845052 +0200
-@@ -119,6 +119,7 @@
+--- linux-2.6.7.perfctr26/include/asm-i386/system.h.~1~ 2008-06-22 21:52:22.000000000 +0200
++++ linux-2.6.7.perfctr26/include/asm-i386/system.h 2008-06-22 21:54:40.261321000 +0200
+@@ -14,6 +14,7 @@ extern struct task_struct * FASTCALL(__s
+
+ #define switch_to(prev,next,last) do { \
+ unsigned long esi,edi; \
++ perfctr_suspend_thread(&(prev)->thread); \
+ asm volatile("pushfl\n\t" \
+ "pushl %%ebp\n\t" \
+ "movl %%esp,%0\n\t" /* save ESP */ \
+--- linux-2.6.7.perfctr26/include/asm-ppc/processor.h.~1~ 2008-06-22 21:52:22.000000000 +0200
++++ linux-2.6.7.perfctr26/include/asm-ppc/processor.h 2008-06-22 21:54:40.261321000 +0200
+@@ -119,6 +119,9 @@ struct thread_struct {
unsigned long vrsave;
int used_vr; /* set if process has used altivec */
#endif /* CONFIG_ALTIVEC */
++#ifdef CONFIG_PERFCTR_VIRTUAL
+ struct vperfctr *perfctr; /* performance counters */
++#endif
};
#define ARCH_MIN_TASKALIGN 16
---- linux-2.6.7-perfctr/include/asm-x86_64/hw_irq.h.~1~ 2004-02-18 11:09:53.000000000 +0100
-+++ linux-2.6.7-perfctr/include/asm-x86_64/hw_irq.h 2004-06-16 11:31:12.996845353 +0200
-@@ -65,14 +65,15 @@
+--- linux-2.6.7.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2008-06-22 21:52:22.000000000 +0200
++++ linux-2.6.7.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 21:54:40.261321000 +0200
+@@ -65,14 +65,15 @@ struct hw_interrupt_type;
* sources per level' errata.
*/
#define LOCAL_TIMER_VECTOR 0xef
@@ -374,8 +405,8 @@
#ifndef __ASSEMBLY__
---- linux-2.6.7-perfctr/include/asm-x86_64/irq.h.~1~ 2004-05-10 11:14:37.000000000 +0200
-+++ linux-2.6.7-perfctr/include/asm-x86_64/irq.h 2004-06-16 11:31:12.996845353 +0200
+--- linux-2.6.7.perfctr26/include/asm-x86_64/irq.h.~1~ 2008-06-22 21:52:22.000000000 +0200
++++ linux-2.6.7.perfctr26/include/asm-x86_64/irq.h 2008-06-22 21:54:40.261321000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -385,9 +416,9 @@
#ifdef CONFIG_PCI_USE_VECTOR
#define NR_IRQS FIRST_SYSTEM_VECTOR
---- linux-2.6.7-perfctr/include/asm-x86_64/processor.h.~1~ 2004-06-16 11:14:27.000000000 +0200
-+++ linux-2.6.7-perfctr/include/asm-x86_64/processor.h 2004-06-16 11:31:13.006845503 +0200
-@@ -253,6 +253,8 @@
+--- linux-2.6.7.perfctr26/include/asm-x86_64/processor.h.~1~ 2008-06-22 21:52:22.000000000 +0200
++++ linux-2.6.7.perfctr26/include/asm-x86_64/processor.h 2008-06-22 21:54:40.261321000 +0200
+@@ -253,6 +253,8 @@ struct thread_struct {
unsigned long *io_bitmap_ptr;
/* cached TLS descriptors. */
u64 tls_array[GDT_ENTRY_TLS_ENTRIES];
@@ -396,8 +427,48 @@
} __attribute__((aligned(16)));
#define INIT_THREAD {}
---- linux-2.6.7-perfctr/kernel/sched.c.~1~ 2004-06-16 11:14:30.000000000 +0200
-+++ linux-2.6.7-perfctr/kernel/sched.c 2004-06-16 11:31:13.006845503 +0200
+--- linux-2.6.7.perfctr26/include/asm-x86_64/system.h.~1~ 2008-06-22 21:43:09.000000000 +0200
++++ linux-2.6.7.perfctr26/include/asm-x86_64/system.h 2008-06-22 21:54:40.261321000 +0200
+@@ -26,7 +26,8 @@
+ #define __EXTRA_CLOBBER \
+ ,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
+
+-#define switch_to(prev,next,last) \
++#define switch_to(prev,next,last) do { \
++ perfctr_suspend_thread(&(prev)->thread); \
+ asm volatile(SAVE_CONTEXT \
+ "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */ \
+ "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */ \
+@@ -46,7 +47,8 @@
+ [tif_fork] "i" (TIF_FORK), \
+ [thread_info] "i" (offsetof(struct task_struct, thread_info)), \
+ [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent)) \
+- : "memory", "cc" __EXTRA_CLOBBER)
++ : "memory", "cc" __EXTRA_CLOBBER); \
++} while (0)
+
+ extern void load_gs_index(unsigned);
+
+--- linux-2.6.7.perfctr26/kernel/exit.c.~1~ 2008-06-22 21:52:22.000000000 +0200
++++ linux-2.6.7.perfctr26/kernel/exit.c 2008-06-22 21:54:40.261321000 +0200
+@@ -23,6 +23,7 @@
+ #include <linux/mount.h>
+ #include <linux/proc_fs.h>
+ #include <linux/mempolicy.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/unistd.h>
+@@ -96,6 +97,7 @@ repeat:
+ p->parent->cmaj_flt += p->maj_flt + p->cmaj_flt;
+ p->parent->cnvcsw += p->nvcsw + p->cnvcsw;
+ p->parent->cnivcsw += p->nivcsw + p->cnivcsw;
++ perfctr_release_task(p);
+ sched_exit(p);
+ write_unlock_irq(&tasklist_lock);
+ spin_unlock(&p->proc_lock);
+--- linux-2.6.7.perfctr26/kernel/sched.c.~1~ 2008-06-22 21:52:22.000000000 +0200
++++ linux-2.6.7.perfctr26/kernel/sched.c 2008-06-22 21:54:40.261321000 +0200
@@ -39,6 +39,7 @@
#include <linux/rcupdate.h>
#include <linux/cpu.h>
@@ -406,7 +477,7 @@
#include <linux/kthread.h>
#include <asm/unistd.h>
-@@ -3319,6 +3320,8 @@
+@@ -3319,6 +3320,8 @@ int set_cpus_allowed(task_t *p, cpumask_
migration_req_t req;
runqueue_t *rq;
@@ -415,8 +486,8 @@
rq = task_rq_lock(p, &flags);
if (any_online_cpu(new_mask) == NR_CPUS) {
ret = -EINVAL;
---- linux-2.6.7-perfctr/kernel/timer.c.~1~ 2004-06-16 11:14:30.000000000 +0200
-+++ linux-2.6.7-perfctr/kernel/timer.c 2004-06-16 11:31:13.006845503 +0200
+--- linux-2.6.7.perfctr26/kernel/timer.c.~1~ 2008-06-22 21:52:22.000000000 +0200
++++ linux-2.6.7.perfctr26/kernel/timer.c 2008-06-22 21:54:40.261321000 +0200
@@ -31,6 +31,7 @@
#include <linux/time.h>
#include <linux/jiffies.h>
@@ -425,7 +496,7 @@
#include <asm/uaccess.h>
#include <asm/unistd.h>
-@@ -835,6 +836,7 @@
+@@ -835,6 +836,7 @@ void update_one_process(struct task_stru
do_process_times(p, user, system);
do_it_virt(p, user);
do_it_prof(p);
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.8.1 b/src/perfctr-2.6.x/patches/patch-kernel-2.6.8.1
index bd50833655b9f264c021e0ee21b458900c168caf..81d6b730430a40f626645ff2fa9c8ffb1c31cd64 100755
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.8.1
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.8.1
@@ -1,16 +1,21 @@
---- linux-2.6.8.1-perfctr26/CREDITS.~1~ 2004-08-14 13:14:24.000000000 +0200
-+++ linux-2.6.8.1-perfctr26/CREDITS 2004-08-15 18:01:49.134977000 +0200
-@@ -2538,6 +2538,7 @@
- E: mikpe@csd.uu.se
- W: http://www.csd.uu.se/~mikpe/
+--- linux-2.6.8.1.perfctr26/CREDITS.~1~ 2008-06-22 21:43:08.000000000 +0200
++++ linux-2.6.8.1.perfctr26/CREDITS 2008-06-22 21:46:32.201321000 +0200
+@@ -2535,9 +2535,10 @@ S: Ottawa, Ontario
+ S: Canada K2P 0X8
+
+ N: Mikael Pettersson
+-E: mikpe@csd.uu.se
+-W: http://www.csd.uu.se/~mikpe/
++E: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/
D: Miscellaneous fixes
+D: Performance-monitoring counters driver
N: Reed H. Petty
E: rhp@draper.net
---- linux-2.6.8.1-perfctr26/Documentation/ioctl-number.txt.~1~ 2004-08-14 13:14:24.000000000 +0200
-+++ linux-2.6.8.1-perfctr26/Documentation/ioctl-number.txt 2004-08-15 18:01:49.134977000 +0200
-@@ -187,6 +187,8 @@
+--- linux-2.6.8.1.perfctr26/Documentation/ioctl-number.txt.~1~ 2008-06-22 21:43:08.000000000 +0200
++++ linux-2.6.8.1.perfctr26/Documentation/ioctl-number.txt 2008-06-22 21:46:27.231321000 +0200
+@@ -187,6 +187,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
<mailto:michael.klein@puffin.lb.shuttle.de>
@@ -19,24 +24,24 @@
0xDD 00-3F ZFCP device driver see drivers/s390/scsi/
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
---- linux-2.6.8.1-perfctr26/MAINTAINERS.~1~ 2004-08-14 13:14:24.000000000 +0200
-+++ linux-2.6.8.1-perfctr26/MAINTAINERS 2004-08-15 18:01:49.134977000 +0200
-@@ -1673,6 +1673,12 @@
+--- linux-2.6.8.1.perfctr26/MAINTAINERS.~1~ 2008-06-22 21:43:08.000000000 +0200
++++ linux-2.6.8.1.perfctr26/MAINTAINERS 2008-06-22 21:46:32.201321000 +0200
+@@ -1673,6 +1673,12 @@ M: george@mvista.com
L: linux-net@vger.kernel.org
S: Supported
+PERFORMANCE-MONITORING COUNTERS DRIVER
+P: Mikael Pettersson
-+M: mikpe@csd.uu.se
-+W: http://www.csd.uu.se/~mikpe/linux/perfctr/
++M: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
+S: Maintained
+
PNP SUPPORT
P: Adam Belay
M: ambx1@neo.rr.com
---- linux-2.6.8.1-perfctr26/arch/i386/Kconfig.~1~ 2004-08-14 13:14:24.000000000 +0200
-+++ linux-2.6.8.1-perfctr26/arch/i386/Kconfig 2004-08-15 18:01:49.134977000 +0200
-@@ -865,6 +865,8 @@
+--- linux-2.6.8.1.perfctr26/arch/i386/Kconfig.~1~ 2008-06-22 21:43:08.000000000 +0200
++++ linux-2.6.8.1.perfctr26/arch/i386/Kconfig 2008-06-22 21:46:27.231321000 +0200
+@@ -865,6 +865,8 @@ config REGPARM
generate incorrect output with certain kernel constructs when
-mregparm=3 is used.
@@ -45,9 +50,9 @@
endmenu
---- linux-2.6.8.1-perfctr26/arch/i386/kernel/entry.S.~1~ 2004-06-16 11:14:08.000000000 +0200
-+++ linux-2.6.8.1-perfctr26/arch/i386/kernel/entry.S 2004-08-15 18:01:49.134977000 +0200
-@@ -406,6 +406,16 @@
+--- linux-2.6.8.1.perfctr26/arch/i386/kernel/entry.S.~1~ 2008-06-22 21:43:08.000000000 +0200
++++ linux-2.6.8.1.perfctr26/arch/i386/kernel/entry.S 2008-06-22 21:46:27.231321000 +0200
+@@ -406,6 +406,16 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -64,8 +69,8 @@
ENTRY(divide_error)
pushl $0 # no error code
pushl $do_divide_error
---- linux-2.6.8.1-perfctr26/arch/i386/kernel/i8259.c.~1~ 2004-08-14 13:14:24.000000000 +0200
-+++ linux-2.6.8.1-perfctr26/arch/i386/kernel/i8259.c 2004-08-15 18:01:49.134977000 +0200
+--- linux-2.6.8.1.perfctr26/arch/i386/kernel/i8259.c.~1~ 2008-06-22 21:43:08.000000000 +0200
++++ linux-2.6.8.1.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 21:46:27.231321000 +0200
@@ -23,6 +23,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -74,7 +79,7 @@
#include <linux/irq.h>
-@@ -427,6 +428,8 @@
+@@ -427,6 +428,8 @@ void __init init_IRQ(void)
*/
intr_init_hook();
@@ -83,8 +88,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.8.1-perfctr26/arch/i386/kernel/process.c.~1~ 2004-08-14 13:14:24.000000000 +0200
-+++ linux-2.6.8.1-perfctr26/arch/i386/kernel/process.c 2004-08-15 18:01:49.144977000 +0200
+--- linux-2.6.8.1.perfctr26/arch/i386/kernel/process.c.~1~ 2008-06-22 21:43:08.000000000 +0200
++++ linux-2.6.8.1.perfctr26/arch/i386/kernel/process.c 2008-06-22 21:46:27.231321000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -93,7 +98,7 @@
#include <linux/mc146818rtc.h>
#include <linux/module.h>
#include <linux/kallsyms.h>
-@@ -304,6 +305,7 @@
+@@ -304,6 +305,7 @@ void exit_thread(void)
tss->io_bitmap_base = INVALID_IO_BITMAP_OFFSET;
put_cpu();
}
@@ -101,25 +106,16 @@
}
void flush_thread(void)
-@@ -366,6 +368,8 @@
+@@ -366,6 +368,8 @@ int copy_thread(int nr, unsigned long cl
savesegment(fs,p->thread.fs);
savesegment(gs,p->thread.gs);
-+ perfctr_copy_thread(&p->thread);
++ perfctr_copy_task(p, regs);
+
tsk = current;
if (unlikely(NULL != tsk->thread.io_bitmap_ptr)) {
p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
-@@ -511,6 +515,8 @@
-
- /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */
-
-+ perfctr_suspend_thread(prev);
-+
- __unlazy_fpu(prev_p);
-
- /*
-@@ -573,6 +579,9 @@
+@@ -573,6 +577,9 @@ struct task_struct fastcall * __switch_t
*/
tss->io_bitmap_base = INVALID_IO_BITMAP_OFFSET;
}
@@ -129,9 +125,9 @@
return prev_p;
}
---- linux-2.6.8.1-perfctr26/arch/ppc/Kconfig.~1~ 2004-08-14 13:14:24.000000000 +0200
-+++ linux-2.6.8.1-perfctr26/arch/ppc/Kconfig 2004-08-15 18:01:49.144977000 +0200
-@@ -243,6 +243,8 @@
+--- linux-2.6.8.1.perfctr26/arch/ppc/Kconfig.~1~ 2008-06-22 21:43:08.000000000 +0200
++++ linux-2.6.8.1.perfctr26/arch/ppc/Kconfig 2008-06-22 21:46:27.231321000 +0200
+@@ -243,6 +243,8 @@ config NOT_COHERENT_CACHE
depends on 4xx || 8xx
default y
@@ -140,8 +136,22 @@
endmenu
menu "Platform options"
---- linux-2.6.8.1-perfctr26/arch/ppc/kernel/process.c.~1~ 2004-08-14 13:14:25.000000000 +0200
-+++ linux-2.6.8.1-perfctr26/arch/ppc/kernel/process.c 2004-08-15 18:01:49.144977000 +0200
+--- linux-2.6.8.1.perfctr26/arch/ppc/kernel/head.S.~1~ 2008-06-22 21:43:08.000000000 +0200
++++ linux-2.6.8.1.perfctr26/arch/ppc/kernel/head.S 2008-06-22 21:46:27.231321000 +0200
+@@ -502,7 +502,11 @@ SystemCall:
+ Trap_0f:
+ EXCEPTION_PROLOG
+ addi r3,r1,STACK_FRAME_OVERHEAD
++#ifdef CONFIG_PERFCTR_INTERRUPT_SUPPORT
++ EXC_XFER_EE(0xf00, do_perfctr_interrupt)
++#else
+ EXC_XFER_EE(0xf00, UnknownException)
++#endif
+
+ /*
+ * Handle TLB miss for instruction on 603/603e.
+--- linux-2.6.8.1.perfctr26/arch/ppc/kernel/process.c.~1~ 2008-06-22 21:43:08.000000000 +0200
++++ linux-2.6.8.1.perfctr26/arch/ppc/kernel/process.c 2008-06-22 21:46:27.231321000 +0200
@@ -35,6 +35,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -150,7 +160,7 @@
#include <linux/mqueue.h>
#include <asm/pgtable.h>
-@@ -301,7 +302,9 @@
+@@ -301,7 +302,9 @@ struct task_struct *__switch_to(struct t
#endif /* CONFIG_SPE */
new_thread = &new->thread;
old_thread = ¤t->thread;
@@ -160,7 +170,7 @@
local_irq_restore(s);
return last;
}
-@@ -370,6 +373,7 @@
+@@ -370,6 +373,7 @@ void exit_thread(void)
last_task_used_math = NULL;
if (last_task_used_altivec == current)
last_task_used_altivec = NULL;
@@ -168,18 +178,18 @@
}
void flush_thread(void)
-@@ -460,6 +464,8 @@
+@@ -460,6 +464,8 @@ copy_thread(int nr, unsigned long clone_
p->thread.last_syscall = -1;
-+ perfctr_copy_thread(&p->thread);
++ perfctr_copy_task(p, regs);
+
return 0;
}
---- linux-2.6.8.1-perfctr26/arch/x86_64/Kconfig.~1~ 2004-06-16 11:14:10.000000000 +0200
-+++ linux-2.6.8.1-perfctr26/arch/x86_64/Kconfig 2004-08-15 18:01:49.144977000 +0200
-@@ -318,6 +318,8 @@
+--- linux-2.6.8.1.perfctr26/arch/x86_64/Kconfig.~1~ 2008-06-22 21:43:08.000000000 +0200
++++ linux-2.6.8.1.perfctr26/arch/x86_64/Kconfig 2008-06-22 21:46:27.231321000 +0200
+@@ -318,6 +318,8 @@ config X86_MCE
bool
default y
@@ -188,9 +198,9 @@
endmenu
---- linux-2.6.8.1-perfctr26/arch/x86_64/kernel/entry.S.~1~ 2004-05-10 11:14:36.000000000 +0200
-+++ linux-2.6.8.1-perfctr26/arch/x86_64/kernel/entry.S 2004-08-15 18:01:49.144977000 +0200
-@@ -557,6 +557,11 @@
+--- linux-2.6.8.1.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2008-06-22 21:43:08.000000000 +0200
++++ linux-2.6.8.1.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 21:46:27.231321000 +0200
+@@ -557,6 +557,11 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
#endif
@@ -198,12 +208,12 @@
+ENTRY(perfctr_interrupt)
+ apicinterrupt LOCAL_PERFCTR_VECTOR,smp_perfctr_interrupt
+#endif
-+
++
/*
* Exception entry points.
*/
---- linux-2.6.8.1-perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2004-08-14 13:14:25.000000000 +0200
-+++ linux-2.6.8.1-perfctr26/arch/x86_64/kernel/i8259.c 2004-08-15 18:01:49.144977000 +0200
+--- linux-2.6.8.1.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2008-06-22 21:43:08.000000000 +0200
++++ linux-2.6.8.1.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 21:46:27.231321000 +0200
@@ -24,6 +24,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -212,7 +222,7 @@
#include <linux/irq.h>
-@@ -509,6 +510,8 @@
+@@ -509,6 +510,8 @@ void __init init_IRQ(void)
set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
#endif
@@ -221,8 +231,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.8.1-perfctr26/arch/x86_64/kernel/process.c.~1~ 2004-06-16 11:14:10.000000000 +0200
-+++ linux-2.6.8.1-perfctr26/arch/x86_64/kernel/process.c 2004-08-15 18:01:49.144977000 +0200
+--- linux-2.6.8.1.perfctr26/arch/x86_64/kernel/process.c.~1~ 2008-06-22 21:43:08.000000000 +0200
++++ linux-2.6.8.1.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 21:46:27.231321000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/irq.h>
@@ -231,7 +241,7 @@
#include <linux/version.h>
#include <asm/uaccess.h>
-@@ -262,6 +263,7 @@
+@@ -262,6 +263,7 @@ void exit_thread(void)
tss->io_bitmap_base = INVALID_IO_BITMAP_OFFSET;
put_cpu();
}
@@ -239,25 +249,16 @@
}
void flush_thread(void)
-@@ -365,6 +367,8 @@
+@@ -365,6 +367,8 @@ int copy_thread(int nr, unsigned long cl
asm("movl %%es,%0" : "=m" (p->thread.es));
asm("movl %%ds,%0" : "=m" (p->thread.ds));
-+ perfctr_copy_thread(&p->thread);
++ perfctr_copy_task(p, regs);
+
if (unlikely(me->thread.io_bitmap_ptr != NULL)) {
p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
if (!p->thread.io_bitmap_ptr)
-@@ -411,6 +415,8 @@
- int cpu = smp_processor_id();
- struct tss_struct *tss = init_tss + cpu;
-
-+ perfctr_suspend_thread(prev);
-+
- unlazy_fpu(prev_p);
-
- /*
-@@ -514,6 +520,8 @@
+@@ -514,6 +518,8 @@ struct task_struct *__switch_to(struct t
}
}
@@ -266,16 +267,34 @@
return prev_p;
}
---- linux-2.6.8.1-perfctr26/drivers/Makefile.~1~ 2004-08-14 13:14:25.000000000 +0200
-+++ linux-2.6.8.1-perfctr26/drivers/Makefile 2004-08-15 18:01:49.144977000 +0200
-@@ -50,4 +50,5 @@
+--- linux-2.6.8.1.perfctr26/drivers/Makefile.~1~ 2008-06-22 21:43:08.000000000 +0200
++++ linux-2.6.8.1.perfctr26/drivers/Makefile 2008-06-22 21:46:27.231321000 +0200
+@@ -50,4 +50,5 @@ obj-$(CONFIG_ISDN) += isdn/
obj-$(CONFIG_MCA) += mca/
obj-$(CONFIG_EISA) += eisa/
obj-$(CONFIG_CPU_FREQ) += cpufreq/
+obj-$(CONFIG_KPERFCTR) += perfctr/
obj-y += firmware/
---- linux-2.6.8.1-perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2004-05-10 11:14:37.000000000 +0200
-+++ linux-2.6.8.1-perfctr26/include/asm-i386/mach-default/irq_vectors.h 2004-08-15 18:01:49.144977000 +0200
+--- linux-2.6.8.1.perfctr26/fs/exec.c.~1~ 2008-06-22 21:43:09.000000000 +0200
++++ linux-2.6.8.1.perfctr26/fs/exec.c 2008-06-22 21:46:32.201321000 +0200
+@@ -46,6 +46,7 @@
+ #include <linux/security.h>
+ #include <linux/syscalls.h>
+ #include <linux/rmap.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -836,6 +837,7 @@ int flush_old_exec(struct linux_binprm *
+ }
+ current->comm[i] = '\0';
+
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ if (bprm->e_uid != current->euid || bprm->e_gid != current->egid ||
+--- linux-2.6.8.1.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.8.1.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 21:46:27.231321000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -294,8 +313,8 @@
#define TIMER_IRQ 0
---- linux-2.6.8.1-perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2004-01-09 13:19:11.000000000 +0100
-+++ linux-2.6.8.1-perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2004-08-15 18:01:49.144977000 +0200
+--- linux-2.6.8.1.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.8.1.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 21:46:27.231321000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -314,9 +333,9 @@
#define TIMER_IRQ 0
---- linux-2.6.8.1-perfctr26/include/asm-i386/processor.h.~1~ 2004-08-14 13:14:29.000000000 +0200
-+++ linux-2.6.8.1-perfctr26/include/asm-i386/processor.h 2004-08-15 18:01:49.144977000 +0200
-@@ -422,6 +422,8 @@
+--- linux-2.6.8.1.perfctr26/include/asm-i386/processor.h.~1~ 2008-06-22 21:43:09.000000000 +0200
++++ linux-2.6.8.1.perfctr26/include/asm-i386/processor.h 2008-06-22 21:46:27.231321000 +0200
+@@ -422,6 +422,8 @@ struct thread_struct {
unsigned int saved_fs, saved_gs;
/* IO permissions */
unsigned long *io_bitmap_ptr;
@@ -325,19 +344,31 @@
};
#define INIT_THREAD { \
---- linux-2.6.8.1-perfctr26/include/asm-ppc/processor.h.~1~ 2004-08-14 13:14:29.000000000 +0200
-+++ linux-2.6.8.1-perfctr26/include/asm-ppc/processor.h 2004-08-15 18:01:49.144977000 +0200
-@@ -126,6 +126,7 @@
+--- linux-2.6.8.1.perfctr26/include/asm-i386/system.h.~1~ 2008-06-22 21:14:49.000000000 +0200
++++ linux-2.6.8.1.perfctr26/include/asm-i386/system.h 2008-06-22 21:46:27.231321000 +0200
+@@ -14,6 +14,7 @@ extern struct task_struct * FASTCALL(__s
+
+ #define switch_to(prev,next,last) do { \
+ unsigned long esi,edi; \
++ perfctr_suspend_thread(&(prev)->thread); \
+ asm volatile("pushfl\n\t" \
+ "pushl %%ebp\n\t" \
+ "movl %%esp,%0\n\t" /* save ESP */ \
+--- linux-2.6.8.1.perfctr26/include/asm-ppc/processor.h.~1~ 2008-06-22 20:48:54.000000000 +0200
++++ linux-2.6.8.1.perfctr26/include/asm-ppc/processor.h 2008-06-22 21:46:27.231321000 +0200
+@@ -126,6 +126,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
#endif /* CONFIG_SPE */
++#ifdef CONFIG_PERFCTR_VIRTUAL
+ struct vperfctr *perfctr; /* performance counters */
++#endif
};
#define ARCH_MIN_TASKALIGN 16
---- linux-2.6.8.1-perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2004-08-14 13:14:29.000000000 +0200
-+++ linux-2.6.8.1-perfctr26/include/asm-x86_64/hw_irq.h 2004-08-15 18:01:49.144977000 +0200
-@@ -65,14 +65,15 @@
+--- linux-2.6.8.1.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2008-06-22 21:43:09.000000000 +0200
++++ linux-2.6.8.1.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 21:46:27.231321000 +0200
+@@ -65,14 +65,15 @@ struct hw_interrupt_type;
* sources per level' errata.
*/
#define LOCAL_TIMER_VECTOR 0xef
@@ -355,8 +386,8 @@
#ifndef __ASSEMBLY__
---- linux-2.6.8.1-perfctr26/include/asm-x86_64/irq.h.~1~ 2004-08-14 13:14:29.000000000 +0200
-+++ linux-2.6.8.1-perfctr26/include/asm-x86_64/irq.h 2004-08-15 18:01:49.144977000 +0200
+--- linux-2.6.8.1.perfctr26/include/asm-x86_64/irq.h.~1~ 2008-06-22 21:14:49.000000000 +0200
++++ linux-2.6.8.1.perfctr26/include/asm-x86_64/irq.h 2008-06-22 21:46:27.231321000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -366,9 +397,9 @@
#ifdef CONFIG_PCI_MSI
#define NR_IRQS FIRST_SYSTEM_VECTOR
---- linux-2.6.8.1-perfctr26/include/asm-x86_64/processor.h.~1~ 2004-08-14 13:14:29.000000000 +0200
-+++ linux-2.6.8.1-perfctr26/include/asm-x86_64/processor.h 2004-08-15 18:01:49.144977000 +0200
-@@ -253,6 +253,8 @@
+--- linux-2.6.8.1.perfctr26/include/asm-x86_64/processor.h.~1~ 2008-06-22 21:43:09.000000000 +0200
++++ linux-2.6.8.1.perfctr26/include/asm-x86_64/processor.h 2008-06-22 21:46:27.231321000 +0200
+@@ -253,6 +253,8 @@ struct thread_struct {
unsigned long *io_bitmap_ptr;
/* cached TLS descriptors. */
u64 tls_array[GDT_ENTRY_TLS_ENTRIES];
@@ -377,8 +408,48 @@
} __attribute__((aligned(16)));
#define INIT_THREAD {}
---- linux-2.6.8.1-perfctr26/kernel/sched.c.~1~ 2004-08-14 13:14:29.000000000 +0200
-+++ linux-2.6.8.1-perfctr26/kernel/sched.c 2004-08-15 18:01:49.144977000 +0200
+--- linux-2.6.8.1.perfctr26/include/asm-x86_64/system.h.~1~ 2008-06-22 21:43:09.000000000 +0200
++++ linux-2.6.8.1.perfctr26/include/asm-x86_64/system.h 2008-06-22 21:46:27.231321000 +0200
+@@ -26,7 +26,8 @@
+ #define __EXTRA_CLOBBER \
+ ,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
+
+-#define switch_to(prev,next,last) \
++#define switch_to(prev,next,last) do { \
++ perfctr_suspend_thread(&(prev)->thread); \
+ asm volatile(SAVE_CONTEXT \
+ "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */ \
+ "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */ \
+@@ -46,7 +47,8 @@
+ [tif_fork] "i" (TIF_FORK), \
+ [thread_info] "i" (offsetof(struct task_struct, thread_info)), \
+ [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent)) \
+- : "memory", "cc" __EXTRA_CLOBBER)
++ : "memory", "cc" __EXTRA_CLOBBER); \
++} while (0)
+
+ extern void load_gs_index(unsigned);
+
+--- linux-2.6.8.1.perfctr26/kernel/exit.c.~1~ 2008-06-22 21:43:09.000000000 +0200
++++ linux-2.6.8.1.perfctr26/kernel/exit.c 2008-06-22 21:46:27.231321000 +0200
+@@ -23,6 +23,7 @@
+ #include <linux/mount.h>
+ #include <linux/proc_fs.h>
+ #include <linux/mempolicy.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/unistd.h>
+@@ -96,6 +97,7 @@ repeat:
+ p->parent->cmaj_flt += p->maj_flt + p->cmaj_flt;
+ p->parent->cnvcsw += p->nvcsw + p->cnvcsw;
+ p->parent->cnivcsw += p->nivcsw + p->cnivcsw;
++ perfctr_release_task(p);
+ sched_exit(p);
+ write_unlock_irq(&tasklist_lock);
+ spin_unlock(&p->proc_lock);
+--- linux-2.6.8.1.perfctr26/kernel/sched.c.~1~ 2008-06-22 21:43:09.000000000 +0200
++++ linux-2.6.8.1.perfctr26/kernel/sched.c 2008-06-22 21:46:27.241321000 +0200
@@ -39,6 +39,7 @@
#include <linux/rcupdate.h>
#include <linux/cpu.h>
@@ -387,7 +458,7 @@
#include <linux/kthread.h>
#include <asm/tlb.h>
-@@ -3334,6 +3335,8 @@
+@@ -3334,6 +3335,8 @@ int set_cpus_allowed(task_t *p, cpumask_
migration_req_t req;
runqueue_t *rq;
@@ -396,8 +467,8 @@
rq = task_rq_lock(p, &flags);
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
---- linux-2.6.8.1-perfctr26/kernel/timer.c.~1~ 2004-08-14 13:14:29.000000000 +0200
-+++ linux-2.6.8.1-perfctr26/kernel/timer.c 2004-08-15 18:01:49.144977000 +0200
+--- linux-2.6.8.1.perfctr26/kernel/timer.c.~1~ 2008-06-22 21:43:09.000000000 +0200
++++ linux-2.6.8.1.perfctr26/kernel/timer.c 2008-06-22 21:46:27.241321000 +0200
@@ -31,6 +31,7 @@
#include <linux/time.h>
#include <linux/jiffies.h>
@@ -406,7 +477,7 @@
#include <asm/uaccess.h>
#include <asm/unistd.h>
-@@ -835,6 +836,7 @@
+@@ -835,6 +836,7 @@ static void update_one_process(struct ta
do_process_times(p, user, system);
do_it_virt(p, user);
do_it_prof(p);
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.9 b/src/perfctr-2.6.x/patches/patch-kernel-2.6.9
index 6ff28fb38ff0ed8b4ddf6fabfb7591b7fd7a5a1b..dab8d4dba183032c788c2a31453e8c4d670bc742 100755
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.9
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.9
@@ -1,16 +1,21 @@
---- linux-2.6.9.perfctr26/CREDITS.~1~ 2004-10-19 13:01:17.000000000 +0200
-+++ linux-2.6.9.perfctr26/CREDITS 2004-10-19 13:26:14.946195000 +0200
-@@ -2586,6 +2586,7 @@
- E: mikpe@csd.uu.se
- W: http://www.csd.uu.se/~mikpe/
+--- linux-2.6.9.perfctr26/CREDITS.~1~ 2008-06-22 21:14:47.000000000 +0200
++++ linux-2.6.9.perfctr26/CREDITS 2008-06-22 21:16:50.911321000 +0200
+@@ -2583,9 +2583,10 @@ S: Ottawa, Ontario
+ S: Canada K2P 0X8
+
+ N: Mikael Pettersson
+-E: mikpe@csd.uu.se
+-W: http://www.csd.uu.se/~mikpe/
++E: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/
D: Miscellaneous fixes
+D: Performance-monitoring counters driver
N: Reed H. Petty
E: rhp@draper.net
---- linux-2.6.9.perfctr26/Documentation/ioctl-number.txt.~1~ 2004-10-19 13:01:17.000000000 +0200
-+++ linux-2.6.9.perfctr26/Documentation/ioctl-number.txt 2004-10-19 13:26:14.946195000 +0200
-@@ -188,6 +188,8 @@
+--- linux-2.6.9.perfctr26/Documentation/ioctl-number.txt.~1~ 2008-06-22 20:48:52.000000000 +0200
++++ linux-2.6.9.perfctr26/Documentation/ioctl-number.txt 2008-06-22 21:16:46.521321000 +0200
+@@ -188,6 +188,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
<mailto:michael.klein@puffin.lb.shuttle.de>
@@ -19,24 +24,24 @@
0xDD 00-3F ZFCP device driver see drivers/s390/scsi/
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
---- linux-2.6.9.perfctr26/MAINTAINERS.~1~ 2004-10-19 13:01:17.000000000 +0200
-+++ linux-2.6.9.perfctr26/MAINTAINERS 2004-10-19 13:26:14.946195000 +0200
-@@ -1725,6 +1725,12 @@
+--- linux-2.6.9.perfctr26/MAINTAINERS.~1~ 2008-06-22 21:14:47.000000000 +0200
++++ linux-2.6.9.perfctr26/MAINTAINERS 2008-06-22 21:16:50.911321000 +0200
+@@ -1725,6 +1725,12 @@ M: tsbogend@alpha.franken.de
L: linux-net@vger.kernel.org
S: Maintained
+PERFORMANCE-MONITORING COUNTERS DRIVER
+P: Mikael Pettersson
-+M: mikpe@csd.uu.se
-+W: http://www.csd.uu.se/~mikpe/linux/perfctr/
++M: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
+S: Maintained
+
POSIX CLOCKS and TIMERS
P: George Anzinger
M: george@mvista.com
---- linux-2.6.9.perfctr26/arch/i386/Kconfig.~1~ 2004-10-19 13:01:17.000000000 +0200
-+++ linux-2.6.9.perfctr26/arch/i386/Kconfig 2004-10-19 13:26:14.946195000 +0200
-@@ -868,6 +868,8 @@
+--- linux-2.6.9.perfctr26/arch/i386/Kconfig.~1~ 2008-06-22 21:14:47.000000000 +0200
++++ linux-2.6.9.perfctr26/arch/i386/Kconfig 2008-06-22 21:16:46.521321000 +0200
+@@ -868,6 +868,8 @@ config REGPARM
generate incorrect output with certain kernel constructs when
-mregparm=3 is used.
@@ -45,9 +50,9 @@
endmenu
---- linux-2.6.9.perfctr26/arch/i386/kernel/entry.S.~1~ 2004-10-19 13:01:17.000000000 +0200
-+++ linux-2.6.9.perfctr26/arch/i386/kernel/entry.S 2004-10-19 13:26:14.946195000 +0200
-@@ -406,6 +406,16 @@
+--- linux-2.6.9.perfctr26/arch/i386/kernel/entry.S.~1~ 2008-06-22 21:14:47.000000000 +0200
++++ linux-2.6.9.perfctr26/arch/i386/kernel/entry.S 2008-06-22 21:16:46.521321000 +0200
+@@ -406,6 +406,16 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -64,8 +69,8 @@
ENTRY(divide_error)
pushl $0 # no error code
pushl $do_divide_error
---- linux-2.6.9.perfctr26/arch/i386/kernel/i8259.c.~1~ 2004-10-19 13:01:17.000000000 +0200
-+++ linux-2.6.9.perfctr26/arch/i386/kernel/i8259.c 2004-10-19 13:26:14.956195000 +0200
+--- linux-2.6.9.perfctr26/arch/i386/kernel/i8259.c.~1~ 2008-06-22 21:14:47.000000000 +0200
++++ linux-2.6.9.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 21:16:46.521321000 +0200
@@ -24,6 +24,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -74,7 +79,7 @@
#include <linux/irq.h>
-@@ -413,6 +414,8 @@
+@@ -413,6 +414,8 @@ void __init init_IRQ(void)
*/
intr_init_hook();
@@ -83,8 +88,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.9.perfctr26/arch/i386/kernel/process.c.~1~ 2004-10-19 13:01:17.000000000 +0200
-+++ linux-2.6.9.perfctr26/arch/i386/kernel/process.c 2004-10-19 13:26:14.956195000 +0200
+--- linux-2.6.9.perfctr26/arch/i386/kernel/process.c.~1~ 2008-06-22 21:14:47.000000000 +0200
++++ linux-2.6.9.perfctr26/arch/i386/kernel/process.c 2008-06-22 21:16:46.521321000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -93,7 +98,7 @@
#include <linux/mc146818rtc.h>
#include <linux/module.h>
#include <linux/kallsyms.h>
-@@ -316,6 +317,7 @@
+@@ -316,6 +317,7 @@ void exit_thread(void)
tss->io_bitmap_base = INVALID_IO_BITMAP_OFFSET;
put_cpu();
}
@@ -101,25 +106,16 @@
}
void flush_thread(void)
-@@ -378,6 +380,8 @@
+@@ -378,6 +380,8 @@ int copy_thread(int nr, unsigned long cl
savesegment(fs,p->thread.fs);
savesegment(gs,p->thread.gs);
-+ perfctr_copy_thread(&p->thread);
++ perfctr_copy_task(p, regs);
+
tsk = current;
if (unlikely(NULL != tsk->thread.io_bitmap_ptr)) {
p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
-@@ -558,6 +562,8 @@
-
- /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */
-
-+ perfctr_suspend_thread(prev);
-+
- __unlazy_fpu(prev_p);
-
- /*
-@@ -601,6 +607,8 @@
+@@ -601,6 +605,8 @@ struct task_struct fastcall * __switch_t
if (unlikely(prev->io_bitmap_ptr || next->io_bitmap_ptr))
handle_io_bitmap(next, tss);
@@ -128,9 +124,9 @@
return prev_p;
}
---- linux-2.6.9.perfctr26/arch/ppc/Kconfig.~1~ 2004-10-19 13:01:17.000000000 +0200
-+++ linux-2.6.9.perfctr26/arch/ppc/Kconfig 2004-10-19 13:26:14.956195000 +0200
-@@ -243,6 +243,8 @@
+--- linux-2.6.9.perfctr26/arch/ppc/Kconfig.~1~ 2008-06-22 21:14:47.000000000 +0200
++++ linux-2.6.9.perfctr26/arch/ppc/Kconfig 2008-06-22 21:16:46.521321000 +0200
+@@ -243,6 +243,8 @@ config NOT_COHERENT_CACHE
depends on 4xx || 8xx
default y
@@ -139,8 +135,22 @@
endmenu
menu "Platform options"
---- linux-2.6.9.perfctr26/arch/ppc/kernel/process.c.~1~ 2004-10-19 13:01:17.000000000 +0200
-+++ linux-2.6.9.perfctr26/arch/ppc/kernel/process.c 2004-10-19 13:26:14.956195000 +0200
+--- linux-2.6.9.perfctr26/arch/ppc/kernel/head.S.~1~ 2008-06-22 20:17:14.000000000 +0200
++++ linux-2.6.9.perfctr26/arch/ppc/kernel/head.S 2008-06-22 21:16:46.521321000 +0200
+@@ -502,7 +502,11 @@ SystemCall:
+ Trap_0f:
+ EXCEPTION_PROLOG
+ addi r3,r1,STACK_FRAME_OVERHEAD
++#ifdef CONFIG_PERFCTR_INTERRUPT_SUPPORT
++ EXC_XFER_EE(0xf00, do_perfctr_interrupt)
++#else
+ EXC_XFER_EE(0xf00, UnknownException)
++#endif
+
+ /*
+ * Handle TLB miss for instruction on 603/603e.
+--- linux-2.6.9.perfctr26/arch/ppc/kernel/process.c.~1~ 2008-06-22 21:14:47.000000000 +0200
++++ linux-2.6.9.perfctr26/arch/ppc/kernel/process.c 2008-06-22 21:16:46.521321000 +0200
@@ -35,6 +35,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -149,7 +159,7 @@
#include <linux/mqueue.h>
#include <linux/hardirq.h>
-@@ -301,7 +302,9 @@
+@@ -301,7 +302,9 @@ struct task_struct *__switch_to(struct t
#endif /* CONFIG_SPE */
new_thread = &new->thread;
old_thread = ¤t->thread;
@@ -159,7 +169,7 @@
local_irq_restore(s);
return last;
}
-@@ -370,6 +373,7 @@
+@@ -370,6 +373,7 @@ void exit_thread(void)
last_task_used_math = NULL;
if (last_task_used_altivec == current)
last_task_used_altivec = NULL;
@@ -167,18 +177,18 @@
}
void flush_thread(void)
-@@ -460,6 +464,8 @@
+@@ -460,6 +464,8 @@ copy_thread(int nr, unsigned long clone_
p->thread.last_syscall = -1;
-+ perfctr_copy_thread(&p->thread);
++ perfctr_copy_task(p, regs);
+
return 0;
}
---- linux-2.6.9.perfctr26/arch/x86_64/Kconfig.~1~ 2004-10-19 13:01:17.000000000 +0200
-+++ linux-2.6.9.perfctr26/arch/x86_64/Kconfig 2004-10-19 13:26:14.956195000 +0200
-@@ -327,6 +327,8 @@
+--- linux-2.6.9.perfctr26/arch/x86_64/Kconfig.~1~ 2008-06-22 21:14:47.000000000 +0200
++++ linux-2.6.9.perfctr26/arch/x86_64/Kconfig 2008-06-22 21:16:46.521321000 +0200
+@@ -327,6 +327,8 @@ config X86_MCE
machine check error logs. See
ftp://ftp.x86-64.org/pub/linux/tools/mcelog
@@ -187,9 +197,9 @@
endmenu
---- linux-2.6.9.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2004-10-19 13:01:17.000000000 +0200
-+++ linux-2.6.9.perfctr26/arch/x86_64/kernel/entry.S 2004-10-19 13:26:14.956195000 +0200
-@@ -560,6 +560,11 @@
+--- linux-2.6.9.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2008-06-22 21:14:47.000000000 +0200
++++ linux-2.6.9.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 21:16:46.521321000 +0200
+@@ -560,6 +560,11 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
#endif
@@ -197,12 +207,12 @@
+ENTRY(perfctr_interrupt)
+ apicinterrupt LOCAL_PERFCTR_VECTOR,smp_perfctr_interrupt
+#endif
-+
++
/*
* Exception entry points.
*/
---- linux-2.6.9.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2004-10-19 13:01:17.000000000 +0200
-+++ linux-2.6.9.perfctr26/arch/x86_64/kernel/i8259.c 2004-10-19 13:26:14.956195000 +0200
+--- linux-2.6.9.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2008-06-22 21:14:47.000000000 +0200
++++ linux-2.6.9.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 21:16:46.521321000 +0200
@@ -24,6 +24,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -211,7 +221,7 @@
#include <linux/irq.h>
-@@ -560,6 +561,8 @@
+@@ -560,6 +561,8 @@ void __init init_IRQ(void)
set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
#endif
@@ -220,8 +230,8 @@
/*
* Set the clock to HZ Hz, we already have a valid
* vector now:
---- linux-2.6.9.perfctr26/arch/x86_64/kernel/process.c.~1~ 2004-10-19 13:01:17.000000000 +0200
-+++ linux-2.6.9.perfctr26/arch/x86_64/kernel/process.c 2004-10-19 13:26:14.956195000 +0200
+--- linux-2.6.9.perfctr26/arch/x86_64/kernel/process.c.~1~ 2008-06-22 21:14:47.000000000 +0200
++++ linux-2.6.9.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 21:16:46.521321000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/irq.h>
@@ -230,7 +240,7 @@
#include <linux/version.h>
#include <asm/uaccess.h>
-@@ -272,6 +273,7 @@
+@@ -272,6 +273,7 @@ void exit_thread(void)
t->io_bitmap_max = 0;
put_cpu();
}
@@ -238,25 +248,16 @@
}
void flush_thread(void)
-@@ -375,6 +377,8 @@
+@@ -375,6 +377,8 @@ int copy_thread(int nr, unsigned long cl
asm("movl %%es,%0" : "=m" (p->thread.es));
asm("movl %%ds,%0" : "=m" (p->thread.ds));
-+ perfctr_copy_thread(&p->thread);
++ perfctr_copy_task(p, regs);
+
if (unlikely(me->thread.io_bitmap_ptr != NULL)) {
p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
if (!p->thread.io_bitmap_ptr) {
-@@ -425,6 +429,8 @@
- int cpu = smp_processor_id();
- struct tss_struct *tss = &per_cpu(init_tss, cpu);
-
-+ perfctr_suspend_thread(prev);
-+
- unlazy_fpu(prev_p);
-
- /*
-@@ -524,6 +530,8 @@
+@@ -524,6 +528,8 @@ struct task_struct *__switch_to(struct t
}
}
@@ -265,16 +266,34 @@
return prev_p;
}
---- linux-2.6.9.perfctr26/drivers/Makefile.~1~ 2004-10-19 13:01:17.000000000 +0200
-+++ linux-2.6.9.perfctr26/drivers/Makefile 2004-10-19 13:26:14.956195000 +0200
-@@ -58,4 +58,5 @@
+--- linux-2.6.9.perfctr26/drivers/Makefile.~1~ 2008-06-22 21:14:47.000000000 +0200
++++ linux-2.6.9.perfctr26/drivers/Makefile 2008-06-22 21:16:46.521321000 +0200
+@@ -58,4 +58,5 @@ obj-$(CONFIG_MCA) += mca/
obj-$(CONFIG_EISA) += eisa/
obj-$(CONFIG_CPU_FREQ) += cpufreq/
obj-$(CONFIG_MMC) += mmc/
+obj-$(CONFIG_KPERFCTR) += perfctr/
obj-y += firmware/
---- linux-2.6.9.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2004-05-10 11:14:37.000000000 +0200
-+++ linux-2.6.9.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2004-10-19 13:26:14.956195000 +0200
+--- linux-2.6.9.perfctr26/fs/exec.c.~1~ 2008-06-22 21:14:48.000000000 +0200
++++ linux-2.6.9.perfctr26/fs/exec.c 2008-06-22 21:16:50.911321000 +0200
+@@ -46,6 +46,7 @@
+ #include <linux/security.h>
+ #include <linux/syscalls.h>
+ #include <linux/rmap.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -856,6 +857,7 @@ int flush_old_exec(struct linux_binprm *
+ tcomm[i] = '\0';
+ set_task_comm(current, tcomm);
+
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ if (bprm->e_uid != current->euid || bprm->e_gid != current->egid ||
+--- linux-2.6.9.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.9.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 21:16:46.521321000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -293,8 +312,8 @@
#define TIMER_IRQ 0
---- linux-2.6.9.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2004-01-09 13:19:11.000000000 +0100
-+++ linux-2.6.9.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2004-10-19 13:26:14.956195000 +0200
+--- linux-2.6.9.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2008-06-22 15:56:54.000000000 +0200
++++ linux-2.6.9.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 21:16:46.521321000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -313,9 +332,9 @@
#define TIMER_IRQ 0
---- linux-2.6.9.perfctr26/include/asm-i386/processor.h.~1~ 2004-10-19 13:01:21.000000000 +0200
-+++ linux-2.6.9.perfctr26/include/asm-i386/processor.h 2004-10-19 13:26:14.956195000 +0200
-@@ -435,6 +435,8 @@
+--- linux-2.6.9.perfctr26/include/asm-i386/processor.h.~1~ 2008-06-22 21:14:49.000000000 +0200
++++ linux-2.6.9.perfctr26/include/asm-i386/processor.h 2008-06-22 21:16:46.521321000 +0200
+@@ -435,6 +435,8 @@ struct thread_struct {
unsigned long *io_bitmap_ptr;
/* max allowed port in the bitmap, in bytes: */
unsigned long io_bitmap_max;
@@ -324,19 +343,31 @@
};
#define INIT_THREAD { \
---- linux-2.6.9.perfctr26/include/asm-ppc/processor.h.~1~ 2004-08-14 13:14:29.000000000 +0200
-+++ linux-2.6.9.perfctr26/include/asm-ppc/processor.h 2004-10-19 13:26:14.956195000 +0200
-@@ -126,6 +126,7 @@
+--- linux-2.6.9.perfctr26/include/asm-i386/system.h.~1~ 2008-06-22 21:14:49.000000000 +0200
++++ linux-2.6.9.perfctr26/include/asm-i386/system.h 2008-06-22 21:16:46.521321000 +0200
+@@ -14,6 +14,7 @@ extern struct task_struct * FASTCALL(__s
+
+ #define switch_to(prev,next,last) do { \
+ unsigned long esi,edi; \
++ perfctr_suspend_thread(&(prev)->thread); \
+ asm volatile("pushfl\n\t" \
+ "pushl %%ebp\n\t" \
+ "movl %%esp,%0\n\t" /* save ESP */ \
+--- linux-2.6.9.perfctr26/include/asm-ppc/processor.h.~1~ 2008-06-22 20:48:54.000000000 +0200
++++ linux-2.6.9.perfctr26/include/asm-ppc/processor.h 2008-06-22 21:16:46.521321000 +0200
+@@ -126,6 +126,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
#endif /* CONFIG_SPE */
++#ifdef CONFIG_PERFCTR_VIRTUAL
+ struct vperfctr *perfctr; /* performance counters */
++#endif
};
#define ARCH_MIN_TASKALIGN 16
---- linux-2.6.9.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2004-10-19 13:01:21.000000000 +0200
-+++ linux-2.6.9.perfctr26/include/asm-x86_64/hw_irq.h 2004-10-19 13:26:14.956195000 +0200
-@@ -65,14 +65,15 @@
+--- linux-2.6.9.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2008-06-22 21:14:49.000000000 +0200
++++ linux-2.6.9.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 21:16:46.521321000 +0200
+@@ -65,14 +65,15 @@ struct hw_interrupt_type;
* sources per level' errata.
*/
#define LOCAL_TIMER_VECTOR 0xef
@@ -354,8 +385,8 @@
#ifndef __ASSEMBLY__
---- linux-2.6.9.perfctr26/include/asm-x86_64/irq.h.~1~ 2004-08-14 13:14:29.000000000 +0200
-+++ linux-2.6.9.perfctr26/include/asm-x86_64/irq.h 2004-10-19 13:26:14.956195000 +0200
+--- linux-2.6.9.perfctr26/include/asm-x86_64/irq.h.~1~ 2008-06-22 21:14:49.000000000 +0200
++++ linux-2.6.9.perfctr26/include/asm-x86_64/irq.h 2008-06-22 21:16:46.521321000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -365,9 +396,9 @@
#ifdef CONFIG_PCI_MSI
#define NR_IRQS FIRST_SYSTEM_VECTOR
---- linux-2.6.9.perfctr26/include/asm-x86_64/processor.h.~1~ 2004-10-19 13:01:21.000000000 +0200
-+++ linux-2.6.9.perfctr26/include/asm-x86_64/processor.h 2004-10-19 13:26:14.956195000 +0200
-@@ -257,6 +257,8 @@
+--- linux-2.6.9.perfctr26/include/asm-x86_64/processor.h.~1~ 2008-06-22 21:14:49.000000000 +0200
++++ linux-2.6.9.perfctr26/include/asm-x86_64/processor.h 2008-06-22 21:16:46.521321000 +0200
+@@ -257,6 +257,8 @@ struct thread_struct {
unsigned io_bitmap_max;
/* cached TLS descriptors. */
u64 tls_array[GDT_ENTRY_TLS_ENTRIES];
@@ -376,8 +407,48 @@
} __attribute__((aligned(16)));
#define INIT_THREAD {}
---- linux-2.6.9.perfctr26/kernel/sched.c.~1~ 2004-10-19 13:01:21.000000000 +0200
-+++ linux-2.6.9.perfctr26/kernel/sched.c 2004-10-19 13:26:14.966195000 +0200
+--- linux-2.6.9.perfctr26/include/asm-x86_64/system.h.~1~ 2008-06-22 21:14:49.000000000 +0200
++++ linux-2.6.9.perfctr26/include/asm-x86_64/system.h 2008-06-22 21:16:46.521321000 +0200
+@@ -26,7 +26,8 @@
+ #define __EXTRA_CLOBBER \
+ ,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
+
+-#define switch_to(prev,next,last) \
++#define switch_to(prev,next,last) do { \
++ perfctr_suspend_thread(&(prev)->thread); \
+ asm volatile(SAVE_CONTEXT \
+ "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */ \
+ "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */ \
+@@ -46,7 +47,8 @@
+ [tif_fork] "i" (TIF_FORK), \
+ [thread_info] "i" (offsetof(struct task_struct, thread_info)), \
+ [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent)) \
+- : "memory", "cc" __EXTRA_CLOBBER)
++ : "memory", "cc" __EXTRA_CLOBBER); \
++} while (0)
+
+ extern void load_gs_index(unsigned);
+
+--- linux-2.6.9.perfctr26/kernel/exit.c.~1~ 2008-06-22 21:14:49.000000000 +0200
++++ linux-2.6.9.perfctr26/kernel/exit.c 2008-06-22 21:16:46.531321000 +0200
+@@ -24,6 +24,7 @@
+ #include <linux/mount.h>
+ #include <linux/proc_fs.h>
+ #include <linux/mempolicy.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/unistd.h>
+@@ -89,6 +90,7 @@ repeat:
+ zap_leader = (leader->exit_signal == -1);
+ }
+
++ perfctr_release_task(p);
+ sched_exit(p);
+ write_unlock_irq(&tasklist_lock);
+ spin_unlock(&p->proc_lock);
+--- linux-2.6.9.perfctr26/kernel/sched.c.~1~ 2008-06-22 21:14:49.000000000 +0200
++++ linux-2.6.9.perfctr26/kernel/sched.c 2008-06-22 21:16:46.531321000 +0200
@@ -40,6 +40,7 @@
#include <linux/rcupdate.h>
#include <linux/cpu.h>
@@ -386,7 +457,7 @@
#include <linux/kthread.h>
#include <linux/seq_file.h>
#include <linux/times.h>
-@@ -3840,6 +3841,8 @@
+@@ -3840,6 +3841,8 @@ int set_cpus_allowed(task_t *p, cpumask_
migration_req_t req;
runqueue_t *rq;
@@ -395,8 +466,8 @@
rq = task_rq_lock(p, &flags);
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
---- linux-2.6.9.perfctr26/kernel/timer.c.~1~ 2004-10-19 13:01:22.000000000 +0200
-+++ linux-2.6.9.perfctr26/kernel/timer.c 2004-10-19 13:26:14.966195000 +0200
+--- linux-2.6.9.perfctr26/kernel/timer.c.~1~ 2008-06-22 21:14:49.000000000 +0200
++++ linux-2.6.9.perfctr26/kernel/timer.c 2008-06-22 21:16:46.531321000 +0200
@@ -31,6 +31,7 @@
#include <linux/time.h>
#include <linux/jiffies.h>
@@ -405,7 +476,7 @@
#include <asm/uaccess.h>
#include <asm/unistd.h>
-@@ -848,6 +849,7 @@
+@@ -848,6 +849,7 @@ static void update_one_process(struct ta
do_process_times(p, user, system);
do_it_virt(p, user);
do_it_prof(p);
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.9-55.EL-redhat b/src/perfctr-2.6.x/patches/patch-kernel-2.6.9-55.EL-redhat
index 617880b113697e2c53eb3bbc4f600523c8e784c8..1183ff888716346d4b0239574b161d96f05ec63a 100644
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.9-55.EL-redhat
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.9-55.EL-redhat
@@ -1,19 +1,20 @@
--- linux-2.6.9-55.EL.perfctr26/CREDITS.~1~ 2004-10-18 23:54:39.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/CREDITS 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/CREDITS 2008-06-22 23:08:24.000000000 +0200
@@ -2583,9 +2583,10 @@ S: Ottawa, Ontario
S: Canada K2P 0X8
N: Mikael Pettersson
-E: mikpe@csd.uu.se
+-W: http://www.csd.uu.se/~mikpe/
+E: mikpe@it.uu.se
- W: http://www.csd.uu.se/~mikpe/
++W: http://user.it.uu.se/~mikpe/
D: Miscellaneous fixes
+D: Performance-monitoring counters driver
N: Reed H. Petty
E: rhp@draper.net
--- linux-2.6.9-55.EL.perfctr26/Documentation/ioctl-number.txt.~1~ 2004-10-18 23:55:27.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/Documentation/ioctl-number.txt 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/Documentation/ioctl-number.txt 2008-06-22 23:08:18.000000000 +0200
@@ -188,6 +188,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -24,7 +25,7 @@
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
--- linux-2.6.9-55.EL.perfctr26/MAINTAINERS.~1~ 2007-06-17 18:08:56.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/MAINTAINERS 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/MAINTAINERS 2008-06-22 23:08:24.000000000 +0200
@@ -1730,6 +1730,12 @@ M: tsbogend@alpha.franken.de
L: linux-net@vger.kernel.org
S: Maintained
@@ -32,14 +33,14 @@
+PERFORMANCE-MONITORING COUNTERS DRIVER
+P: Mikael Pettersson
+M: mikpe@it.uu.se
-+W: http://www.csd.uu.se/~mikpe/linux/perfctr/
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
+S: Maintained
+
POSIX CLOCKS and TIMERS
P: George Anzinger
M: george@mvista.com
--- linux-2.6.9-55.EL.perfctr26/arch/i386/Kconfig.~1~ 2007-06-17 18:08:57.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/arch/i386/Kconfig 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/arch/i386/Kconfig 2008-06-22 23:08:18.000000000 +0200
@@ -960,6 +960,8 @@ config REGPARM
generate incorrect output with certain kernel constructs when
-mregparm=3 is used.
@@ -50,7 +51,7 @@
--- linux-2.6.9-55.EL.perfctr26/arch/i386/kernel/entry.S.~1~ 2007-06-17 18:08:57.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/arch/i386/kernel/entry.S 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/arch/i386/kernel/entry.S 2008-06-22 23:08:18.000000000 +0200
@@ -561,6 +561,16 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -69,7 +70,7 @@
pushl $0 # no error code
pushl $do_divide_error
--- linux-2.6.9-55.EL.perfctr26/arch/i386/kernel/i8259.c.~1~ 2004-10-18 23:55:18.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/arch/i386/kernel/i8259.c 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 23:08:18.000000000 +0200
@@ -24,6 +24,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -88,7 +89,7 @@
* Set the clock to HZ Hz, we already have a valid
* vector now:
--- linux-2.6.9-55.EL.perfctr26/arch/i386/kernel/process.c.~1~ 2007-06-17 18:08:57.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/arch/i386/kernel/process.c 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/arch/i386/kernel/process.c 2008-06-22 23:08:18.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -124,7 +125,7 @@
}
--- linux-2.6.9-55.EL.perfctr26/arch/ppc/Kconfig.~1~ 2004-10-18 23:55:29.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/arch/ppc/Kconfig 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/arch/ppc/Kconfig 2008-06-22 23:08:18.000000000 +0200
@@ -243,6 +243,8 @@ config NOT_COHERENT_CACHE
depends on 4xx || 8xx
default y
@@ -135,7 +136,7 @@
menu "Platform options"
--- linux-2.6.9-55.EL.perfctr26/arch/ppc/kernel/head.S.~1~ 2007-06-17 18:08:57.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/arch/ppc/kernel/head.S 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/arch/ppc/kernel/head.S 2008-06-22 23:08:18.000000000 +0200
@@ -502,7 +502,11 @@ SystemCall:
Trap_0f:
EXCEPTION_PROLOG
@@ -149,7 +150,7 @@
/*
* Handle TLB miss for instruction on 603/603e.
--- linux-2.6.9-55.EL.perfctr26/arch/ppc/kernel/process.c.~1~ 2007-06-17 18:08:55.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/arch/ppc/kernel/process.c 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/arch/ppc/kernel/process.c 2008-06-22 23:08:18.000000000 +0200
@@ -35,6 +35,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -186,7 +187,7 @@
}
--- linux-2.6.9-55.EL.perfctr26/arch/x86_64/Kconfig.~1~ 2007-06-17 18:08:57.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/arch/x86_64/Kconfig 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/arch/x86_64/Kconfig 2008-06-22 23:08:18.000000000 +0200
@@ -401,6 +401,8 @@ config X86_MCE_AMD
Additional support for AMD specific MCE features such as
the DRAM Error Threshold.
@@ -197,7 +198,7 @@
--- linux-2.6.9-55.EL.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2007-06-17 18:08:46.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/arch/x86_64/kernel/entry.S 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 23:08:18.000000000 +0200
@@ -563,6 +563,11 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
#endif
@@ -211,7 +212,7 @@
* Exception entry points.
*/
--- linux-2.6.9-55.EL.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2007-06-17 18:08:46.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/arch/x86_64/kernel/i8259.c 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 23:08:18.000000000 +0200
@@ -24,6 +24,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -230,7 +231,7 @@
* Set the clock to HZ Hz, we already have a valid
* vector now:
--- linux-2.6.9-55.EL.perfctr26/arch/x86_64/kernel/process.c.~1~ 2007-06-17 18:08:57.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/arch/x86_64/kernel/process.c 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 23:08:18.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/irq.h>
@@ -266,7 +267,7 @@
}
--- linux-2.6.9-55.EL.perfctr26/drivers/Makefile.~1~ 2007-06-17 18:08:56.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/drivers/Makefile 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/drivers/Makefile 2008-06-22 23:08:18.000000000 +0200
@@ -62,5 +62,6 @@ obj-$(CONFIG_MCA) += mca/
obj-$(CONFIG_EISA) += eisa/
obj-$(CONFIG_CPU_FREQ) += cpufreq/
@@ -274,8 +275,26 @@
+obj-$(CONFIG_KPERFCTR) += perfctr/
obj-$(CONFIG_INFINIBAND) += infiniband/
obj-y += firmware/
+--- linux-2.6.9-55.EL.perfctr26/fs/exec.c.~1~ 2007-06-17 18:08:57.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/fs/exec.c 2008-06-22 23:08:24.000000000 +0200
+@@ -48,6 +48,7 @@
+ #include <linux/syscalls.h>
+ #include <linux/rmap.h>
+ #include <linux/audit.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -906,6 +907,7 @@ int flush_old_exec(struct linux_binprm *
+ set_task_comm(current, tcomm);
+
+ current->flags &= ~PF_RELOCEXEC;
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ if (bprm->e_uid != current->euid || bprm->e_gid != current->egid ||
--- linux-2.6.9-55.EL.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2004-10-18 23:53:44.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 23:08:18.000000000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -295,7 +314,7 @@
#define TIMER_IRQ 0
--- linux-2.6.9-55.EL.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2004-10-18 23:53:13.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 23:08:18.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -315,7 +334,7 @@
#define TIMER_IRQ 0
--- linux-2.6.9-55.EL.perfctr26/include/asm-i386/processor.h.~1~ 2007-06-17 18:08:47.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/include/asm-i386/processor.h 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/include/asm-i386/processor.h 2008-06-22 23:08:18.000000000 +0200
@@ -454,6 +454,8 @@ struct thread_struct {
unsigned long *io_bitmap_ptr;
/* max allowed port in the bitmap, in bytes: */
@@ -326,7 +345,7 @@
#define INIT_THREAD { \
--- linux-2.6.9-55.EL.perfctr26/include/asm-i386/system.h.~1~ 2004-10-18 23:53:06.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/include/asm-i386/system.h 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/include/asm-i386/system.h 2008-06-22 23:08:18.000000000 +0200
@@ -14,6 +14,7 @@ extern struct task_struct * FASTCALL(__s
#define switch_to(prev,next,last) do { \
@@ -336,7 +355,7 @@
"pushl %%ebp\n\t" \
"movl %%esp,%0\n\t" /* save ESP */ \
--- linux-2.6.9-55.EL.perfctr26/include/asm-ppc/processor.h.~1~ 2004-10-18 23:53:06.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/include/asm-ppc/processor.h 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/include/asm-ppc/processor.h 2008-06-22 23:08:18.000000000 +0200
@@ -126,6 +126,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
@@ -348,7 +367,7 @@
#define ARCH_MIN_TASKALIGN 16
--- linux-2.6.9-55.EL.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2007-06-17 18:08:46.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/include/asm-x86_64/hw_irq.h 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 23:08:18.000000000 +0200
@@ -66,14 +66,15 @@ struct hw_interrupt_type;
* sources per level' errata.
*/
@@ -368,7 +387,7 @@
#ifndef __ASSEMBLY__
--- linux-2.6.9-55.EL.perfctr26/include/asm-x86_64/irq.h.~1~ 2007-06-17 18:08:52.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/include/asm-x86_64/irq.h 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/include/asm-x86_64/irq.h 2008-06-22 23:08:18.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -379,7 +398,7 @@
#ifdef CONFIG_PCI_MSI
#define NR_IRQS FIRST_SYSTEM_VECTOR
--- linux-2.6.9-55.EL.perfctr26/include/asm-x86_64/processor.h.~1~ 2007-06-17 18:08:45.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/include/asm-x86_64/processor.h 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/include/asm-x86_64/processor.h 2008-06-22 23:08:18.000000000 +0200
@@ -262,6 +262,8 @@ struct thread_struct {
unsigned io_bitmap_max;
/* cached TLS descriptors. */
@@ -390,7 +409,7 @@
#define INIT_THREAD {}
--- linux-2.6.9-55.EL.perfctr26/include/asm-x86_64/system.h.~1~ 2007-06-17 18:08:46.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/include/asm-x86_64/system.h 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/include/asm-x86_64/system.h 2008-06-22 23:08:18.000000000 +0200
@@ -26,7 +26,8 @@
#define __EXTRA_CLOBBER \
,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
@@ -412,7 +431,7 @@
extern void load_gs_index(unsigned);
--- linux-2.6.9-55.EL.perfctr26/kernel/exit.c.~1~ 2007-06-17 18:08:57.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/kernel/exit.c 2007-06-17 19:20:25.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/kernel/exit.c 2008-06-22 23:08:18.000000000 +0200
@@ -25,6 +25,7 @@
#include <linux/mount.h>
#include <linux/proc_fs.h>
@@ -430,7 +449,7 @@
write_unlock_irq(&tasklist_lock);
spin_unlock(&p->proc_lock);
--- linux-2.6.9-55.EL.perfctr26/kernel/sched.c.~1~ 2007-06-17 18:08:57.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/kernel/sched.c 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/kernel/sched.c 2008-06-22 23:08:18.000000000 +0200
@@ -41,6 +41,7 @@
#include <linux/rcupdate.h>
#include <linux/cpu.h>
@@ -449,7 +468,7 @@
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
--- linux-2.6.9-55.EL.perfctr26/kernel/timer.c.~1~ 2007-06-17 18:08:57.000000000 +0200
-+++ linux-2.6.9-55.EL.perfctr26/kernel/timer.c 2007-06-17 19:19:53.000000000 +0200
++++ linux-2.6.9-55.EL.perfctr26/kernel/timer.c 2008-06-22 23:08:18.000000000 +0200
@@ -31,6 +31,7 @@
#include <linux/time.h>
#include <linux/jiffies.h>
diff --git a/src/perfctr-2.6.x/patches/patch-kernel-2.6.9-67.EL-redhat b/src/perfctr-2.6.x/patches/patch-kernel-2.6.9-67.EL-redhat
index c40c3352d1bef4517ec2bfebb3bdee4258974006..b89aaf32e0579ff582131d029ac4b9beda05b57f 100644
--- a/src/perfctr-2.6.x/patches/patch-kernel-2.6.9-67.EL-redhat
+++ b/src/perfctr-2.6.x/patches/patch-kernel-2.6.9-67.EL-redhat
@@ -1,5 +1,5 @@
--- linux-2.6.9-67.EL.perfctr26/CREDITS.~1~ 2004-10-18 23:54:39.000000000 +0200
-+++ linux-2.6.9-67.EL.perfctr26/CREDITS 2007-12-27 16:38:38.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/CREDITS 2008-06-22 23:31:37.000000000 +0200
@@ -2583,9 +2583,10 @@ S: Ottawa, Ontario
S: Canada K2P 0X8
@@ -14,7 +14,7 @@
N: Reed H. Petty
E: rhp@draper.net
--- linux-2.6.9-67.EL.perfctr26/Documentation/ioctl-number.txt.~1~ 2004-10-18 23:55:27.000000000 +0200
-+++ linux-2.6.9-67.EL.perfctr26/Documentation/ioctl-number.txt 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/Documentation/ioctl-number.txt 2008-06-22 23:31:37.000000000 +0200
@@ -188,6 +188,8 @@ Code Seq# Include File Comments
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
0xCB 00-1F CBM serial IEC bus in development:
@@ -25,7 +25,7 @@
<mailto:aherrman@de.ibm.com>
0xF3 00-3F video/sisfb.h sisfb (in development)
--- linux-2.6.9-67.EL.perfctr26/MAINTAINERS.~1~ 2007-12-27 16:09:54.000000000 +0100
-+++ linux-2.6.9-67.EL.perfctr26/MAINTAINERS 2007-12-27 16:38:57.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/MAINTAINERS 2008-06-22 23:31:37.000000000 +0200
@@ -1737,6 +1737,12 @@ M: tsbogend@alpha.franken.de
L: linux-net@vger.kernel.org
S: Maintained
@@ -40,7 +40,7 @@
P: George Anzinger
M: george@mvista.com
--- linux-2.6.9-67.EL.perfctr26/arch/i386/Kconfig.~1~ 2007-12-27 16:09:55.000000000 +0100
-+++ linux-2.6.9-67.EL.perfctr26/arch/i386/Kconfig 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/arch/i386/Kconfig 2008-06-22 23:31:37.000000000 +0200
@@ -960,6 +960,8 @@ config REGPARM
generate incorrect output with certain kernel constructs when
-mregparm=3 is used.
@@ -51,7 +51,7 @@
--- linux-2.6.9-67.EL.perfctr26/arch/i386/kernel/entry.S.~1~ 2007-12-27 16:09:55.000000000 +0100
-+++ linux-2.6.9-67.EL.perfctr26/arch/i386/kernel/entry.S 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/arch/i386/kernel/entry.S 2008-06-22 23:31:37.000000000 +0200
@@ -561,6 +561,16 @@ ENTRY(name) \
/* The include is where all of the SMP etc. interrupts come from */
#include "entry_arch.h"
@@ -70,7 +70,7 @@
pushl $0 # no error code
pushl $do_divide_error
--- linux-2.6.9-67.EL.perfctr26/arch/i386/kernel/i8259.c.~1~ 2004-10-18 23:55:18.000000000 +0200
-+++ linux-2.6.9-67.EL.perfctr26/arch/i386/kernel/i8259.c 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/arch/i386/kernel/i8259.c 2008-06-22 23:31:37.000000000 +0200
@@ -24,6 +24,7 @@
#include <asm/apic.h>
#include <asm/arch_hooks.h>
@@ -89,7 +89,7 @@
* Set the clock to HZ Hz, we already have a valid
* vector now:
--- linux-2.6.9-67.EL.perfctr26/arch/i386/kernel/process.c.~1~ 2007-12-27 16:09:55.000000000 +0100
-+++ linux-2.6.9-67.EL.perfctr26/arch/i386/kernel/process.c 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/arch/i386/kernel/process.c 2008-06-22 23:31:37.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/reboot.h>
@@ -125,7 +125,7 @@
}
--- linux-2.6.9-67.EL.perfctr26/arch/ppc/Kconfig.~1~ 2004-10-18 23:55:29.000000000 +0200
-+++ linux-2.6.9-67.EL.perfctr26/arch/ppc/Kconfig 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/arch/ppc/Kconfig 2008-06-22 23:31:37.000000000 +0200
@@ -243,6 +243,8 @@ config NOT_COHERENT_CACHE
depends on 4xx || 8xx
default y
@@ -136,7 +136,7 @@
menu "Platform options"
--- linux-2.6.9-67.EL.perfctr26/arch/ppc/kernel/head.S.~1~ 2007-12-27 16:09:55.000000000 +0100
-+++ linux-2.6.9-67.EL.perfctr26/arch/ppc/kernel/head.S 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/arch/ppc/kernel/head.S 2008-06-22 23:31:37.000000000 +0200
@@ -502,7 +502,11 @@ SystemCall:
Trap_0f:
EXCEPTION_PROLOG
@@ -150,7 +150,7 @@
/*
* Handle TLB miss for instruction on 603/603e.
--- linux-2.6.9-67.EL.perfctr26/arch/ppc/kernel/process.c.~1~ 2007-12-27 16:09:54.000000000 +0100
-+++ linux-2.6.9-67.EL.perfctr26/arch/ppc/kernel/process.c 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/arch/ppc/kernel/process.c 2008-06-22 23:31:37.000000000 +0200
@@ -35,6 +35,7 @@
#include <linux/init_task.h>
#include <linux/module.h>
@@ -187,7 +187,7 @@
}
--- linux-2.6.9-67.EL.perfctr26/arch/x86_64/Kconfig.~1~ 2007-12-27 16:09:55.000000000 +0100
-+++ linux-2.6.9-67.EL.perfctr26/arch/x86_64/Kconfig 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/arch/x86_64/Kconfig 2008-06-22 23:31:37.000000000 +0200
@@ -401,6 +401,8 @@ config X86_MCE_AMD
Additional support for AMD specific MCE features such as
the DRAM Error Threshold.
@@ -198,7 +198,7 @@
--- linux-2.6.9-67.EL.perfctr26/arch/x86_64/kernel/entry.S.~1~ 2007-12-27 16:09:41.000000000 +0100
-+++ linux-2.6.9-67.EL.perfctr26/arch/x86_64/kernel/entry.S 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/arch/x86_64/kernel/entry.S 2008-06-22 23:31:37.000000000 +0200
@@ -563,6 +563,11 @@ ENTRY(spurious_interrupt)
apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
#endif
@@ -212,7 +212,7 @@
* Exception entry points.
*/
--- linux-2.6.9-67.EL.perfctr26/arch/x86_64/kernel/i8259.c.~1~ 2007-12-27 16:09:41.000000000 +0100
-+++ linux-2.6.9-67.EL.perfctr26/arch/x86_64/kernel/i8259.c 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/arch/x86_64/kernel/i8259.c 2008-06-22 23:31:37.000000000 +0200
@@ -24,6 +24,7 @@
#include <asm/delay.h>
#include <asm/desc.h>
@@ -231,7 +231,7 @@
* Set the clock to HZ Hz, we already have a valid
* vector now:
--- linux-2.6.9-67.EL.perfctr26/arch/x86_64/kernel/process.c.~1~ 2007-12-27 16:09:55.000000000 +0100
-+++ linux-2.6.9-67.EL.perfctr26/arch/x86_64/kernel/process.c 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/arch/x86_64/kernel/process.c 2008-06-22 23:31:37.000000000 +0200
@@ -32,6 +32,7 @@
#include <linux/delay.h>
#include <linux/irq.h>
@@ -267,7 +267,7 @@
}
--- linux-2.6.9-67.EL.perfctr26/drivers/Makefile.~1~ 2007-12-27 16:09:55.000000000 +0100
-+++ linux-2.6.9-67.EL.perfctr26/drivers/Makefile 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/drivers/Makefile 2008-06-22 23:31:37.000000000 +0200
@@ -62,5 +62,6 @@ obj-$(CONFIG_MCA) += mca/
obj-$(CONFIG_EISA) += eisa/
obj-$(CONFIG_CPU_FREQ) += cpufreq/
@@ -275,8 +275,26 @@
+obj-$(CONFIG_KPERFCTR) += perfctr/
obj-$(CONFIG_INFINIBAND) += infiniband/
obj-y += firmware/
+--- linux-2.6.9-67.EL.perfctr26/fs/exec.c.~1~ 2007-12-27 16:09:55.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/fs/exec.c 2008-06-22 23:31:44.000000000 +0200
+@@ -48,6 +48,7 @@
+ #include <linux/syscalls.h>
+ #include <linux/rmap.h>
+ #include <linux/audit.h>
++#include <linux/perfctr.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/mmu_context.h>
+@@ -917,6 +918,7 @@ int flush_old_exec(struct linux_binprm *
+ set_task_comm(current, tcomm);
+
+ current->flags &= ~PF_RELOCEXEC;
++ perfctr_flush_thread(¤t->thread);
+ flush_thread();
+
+ if (bprm->e_uid != current->euid || bprm->e_gid != current->egid) {
--- linux-2.6.9-67.EL.perfctr26/include/asm-i386/mach-default/irq_vectors.h.~1~ 2004-10-18 23:53:44.000000000 +0200
-+++ linux-2.6.9-67.EL.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/include/asm-i386/mach-default/irq_vectors.h 2008-06-22 23:31:37.000000000 +0200
@@ -56,14 +56,15 @@
* sources per level' errata.
*/
@@ -296,7 +314,7 @@
#define TIMER_IRQ 0
--- linux-2.6.9-67.EL.perfctr26/include/asm-i386/mach-visws/irq_vectors.h.~1~ 2004-10-18 23:53:13.000000000 +0200
-+++ linux-2.6.9-67.EL.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/include/asm-i386/mach-visws/irq_vectors.h 2008-06-22 23:31:37.000000000 +0200
@@ -35,14 +35,15 @@
* sources per level' errata.
*/
@@ -316,7 +334,7 @@
#define TIMER_IRQ 0
--- linux-2.6.9-67.EL.perfctr26/include/asm-i386/processor.h.~1~ 2007-12-27 16:09:55.000000000 +0100
-+++ linux-2.6.9-67.EL.perfctr26/include/asm-i386/processor.h 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/include/asm-i386/processor.h 2008-06-22 23:31:37.000000000 +0200
@@ -455,6 +455,8 @@ struct thread_struct {
unsigned long *io_bitmap_ptr;
/* max allowed port in the bitmap, in bytes: */
@@ -327,7 +345,7 @@
#define INIT_THREAD { \
--- linux-2.6.9-67.EL.perfctr26/include/asm-i386/system.h.~1~ 2004-10-18 23:53:06.000000000 +0200
-+++ linux-2.6.9-67.EL.perfctr26/include/asm-i386/system.h 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/include/asm-i386/system.h 2008-06-22 23:31:37.000000000 +0200
@@ -14,6 +14,7 @@ extern struct task_struct * FASTCALL(__s
#define switch_to(prev,next,last) do { \
@@ -337,7 +355,7 @@
"pushl %%ebp\n\t" \
"movl %%esp,%0\n\t" /* save ESP */ \
--- linux-2.6.9-67.EL.perfctr26/include/asm-ppc/processor.h.~1~ 2004-10-18 23:53:06.000000000 +0200
-+++ linux-2.6.9-67.EL.perfctr26/include/asm-ppc/processor.h 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/include/asm-ppc/processor.h 2008-06-22 23:31:37.000000000 +0200
@@ -126,6 +126,9 @@ struct thread_struct {
unsigned long spefscr; /* SPE & eFP status */
int used_spe; /* set if process has used spe */
@@ -349,7 +367,7 @@
#define ARCH_MIN_TASKALIGN 16
--- linux-2.6.9-67.EL.perfctr26/include/asm-x86_64/hw_irq.h.~1~ 2007-12-27 16:09:41.000000000 +0100
-+++ linux-2.6.9-67.EL.perfctr26/include/asm-x86_64/hw_irq.h 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/include/asm-x86_64/hw_irq.h 2008-06-22 23:31:37.000000000 +0200
@@ -66,14 +66,15 @@ struct hw_interrupt_type;
* sources per level' errata.
*/
@@ -369,7 +387,7 @@
#ifndef __ASSEMBLY__
--- linux-2.6.9-67.EL.perfctr26/include/asm-x86_64/irq.h.~1~ 2007-12-27 16:09:49.000000000 +0100
-+++ linux-2.6.9-67.EL.perfctr26/include/asm-x86_64/irq.h 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/include/asm-x86_64/irq.h 2008-06-22 23:31:37.000000000 +0200
@@ -29,7 +29,7 @@
*/
#define NR_VECTORS 256
@@ -380,7 +398,7 @@
#ifdef CONFIG_PCI_MSI
#define NR_IRQS FIRST_SYSTEM_VECTOR
--- linux-2.6.9-67.EL.perfctr26/include/asm-x86_64/processor.h.~1~ 2007-12-27 16:09:41.000000000 +0100
-+++ linux-2.6.9-67.EL.perfctr26/include/asm-x86_64/processor.h 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/include/asm-x86_64/processor.h 2008-06-22 23:31:37.000000000 +0200
@@ -263,6 +263,8 @@ struct thread_struct {
unsigned io_bitmap_max;
/* cached TLS descriptors. */
@@ -391,7 +409,7 @@
#define INIT_THREAD {}
--- linux-2.6.9-67.EL.perfctr26/include/asm-x86_64/system.h.~1~ 2007-12-27 16:09:41.000000000 +0100
-+++ linux-2.6.9-67.EL.perfctr26/include/asm-x86_64/system.h 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/include/asm-x86_64/system.h 2008-06-22 23:31:37.000000000 +0200
@@ -26,7 +26,8 @@
#define __EXTRA_CLOBBER \
,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
@@ -413,7 +431,7 @@
extern void load_gs_index(unsigned);
--- linux-2.6.9-67.EL.perfctr26/kernel/exit.c.~1~ 2007-12-27 16:09:55.000000000 +0100
-+++ linux-2.6.9-67.EL.perfctr26/kernel/exit.c 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/kernel/exit.c 2008-06-22 23:31:37.000000000 +0200
@@ -25,6 +25,7 @@
#include <linux/mount.h>
#include <linux/proc_fs.h>
@@ -431,7 +449,7 @@
write_unlock_irq(&tasklist_lock);
spin_unlock(&p->proc_lock);
--- linux-2.6.9-67.EL.perfctr26/kernel/sched.c.~1~ 2007-12-27 16:09:55.000000000 +0100
-+++ linux-2.6.9-67.EL.perfctr26/kernel/sched.c 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/kernel/sched.c 2008-06-22 23:31:37.000000000 +0200
@@ -41,6 +41,7 @@
#include <linux/rcupdate.h>
#include <linux/cpu.h>
@@ -450,7 +468,7 @@
if (!cpus_intersects(new_mask, cpu_online_map)) {
ret = -EINVAL;
--- linux-2.6.9-67.EL.perfctr26/kernel/timer.c.~1~ 2007-12-27 16:09:55.000000000 +0100
-+++ linux-2.6.9-67.EL.perfctr26/kernel/timer.c 2007-12-27 16:36:41.000000000 +0100
++++ linux-2.6.9-67.EL.perfctr26/kernel/timer.c 2008-06-22 23:31:37.000000000 +0200
@@ -31,6 +31,7 @@
#include <linux/time.h>
#include <linux/jiffies.h>
diff --git a/src/perfctr-2.6.x/perfctr.spec b/src/perfctr-2.6.x/perfctr.spec
index 4c7ae3b0e3f4438f77e8b9fcaac8cd4a9d47e927..8e33acd20b9daf256aa93359a6499f234f7aae1e 100755
--- a/src/perfctr-2.6.x/perfctr.spec
+++ b/src/perfctr-2.6.x/perfctr.spec
@@ -1,10 +1,10 @@
Name: perfctr
-Summary: Linux/x86 performance monitoring counters software
-Version: 2.6.5
+Summary: Linux performance monitoring counters software
+Version: 2.6.42
Release: 1
License: LGPL
Group: Development/Tools
-URL: http://www.csd.uu.se/~mikpe/linux/perfctr/
+URL: http://user.it.uu.se/~mikpe/linux/perfctr/
BuildRoot: %{_tmppath}/%{name}-%{version}-%{release}-buildroot
Source: %{name}-%{version}.tar.gz
@@ -41,7 +41,8 @@ make install2 \
PREFIX=%{buildroot}/%{_prefix} \
BINDIR=%{buildroot}/%{_bindir} \
LIBDIR=%{buildroot}/%{_libdir} \
- INCLDIR=%{buildroot}/%{_includedir}
+ INCLDIR=%{buildroot}/%{_includedir} \
+ ETCDIR=%{buildroot}/etc
/sbin/ldconfig -n %{buildroot}/%{_libdir}
%clean
@@ -51,34 +52,25 @@ rm -rf %{buildroot}
%defattr(-,root,root,-)
%{_bindir}/perfex
%{_libdir}/*.so*
+%config /etc/rc.d/init.d/perfctr
+%config /etc/udev/rules.d/*perfctr.rules
%doc README CHANGES TODO OTHER
%post
-function fix_mod_config() {
- filename="$1"
- tmpfile="$filename.perfctr-tmp"
-
- if [ -f "$filename" ]; then
- if LC_ALL=C fgrep -q 'alias char-major-10-182 perfctr' "$filename" ; then
- :
- else
- cat "$filename" > "$tmpfile"
- echo 'alias char-major-10-182 perfctr' >> "$tmpfile"
- cp -f -- "$tmpfile" "$filename"
- rm -f -- "$tmpfile"
- fi
- fi
-}
-
-fix_mod_config /etc/modules.conf
-
if [ ! -c /dev/perfctr ]; then
mknod -m 644 /dev/perfctr c 10 182
fi
+/sbin/chkconfig --add perfctr
+
/sbin/ldconfig
+%preun
+if [ "$1" = 0 ]; then
+ /sbin/chkconfig --del perfctr
+fi
+
%postun -p /sbin/ldconfig
%files devel
@@ -89,6 +81,23 @@ fi
%changelog
+* Fri Jan 23 2009 Mikael Pettersson <mikpe@it.uu.se> -
+- Remove 2.4 kernel support: do not fix up /etc/modules.conf.
+
+* Sun Oct 07 2007 Mikael Pettersson <mikpe@it.uu.se> -
+- Corrected URL.
+
+* Wed Jul 18 2007 Mikael Pettersson <mikpe@it.uu.se> -
+- Correct udev rules path (/etc/udev.d/ -> /etc/udev/).
+
+* Mon Apr 09 2007 Mikael Pettersson <mikpe@it.uu.se> -
+- Install perfctr udev rules file and perfctr rc script
+ so /dev/perfctr creation with correct permissions and
+ perfctr module autoloading can work with udev.
+
+* Tue Sep 16 2004 Mikael Pettersson <mikpe@csd.uu.se> -
+- Dropped obsolete x86 qualification from Summary.
+
* Sun Dec 21 2003 Mikael Pettersson <mikpe@csd.uu.se> -
- Create /dev/perfctr in %post, not in %install and %files.
This avoids incorrect deletion of the node on package uninstall.
diff --git a/src/perfctr-2.6.x/update-kernel b/src/perfctr-2.6.x/update-kernel
index 5bba66599b2422487985e2dd7eb24410dc67ccf2..9d874f27355c79f207d363cc059ffde9f899ea1e 100755
--- a/src/perfctr-2.6.x/update-kernel
+++ b/src/perfctr-2.6.x/update-kernel
@@ -1,5 +1,5 @@
#!/bin/sh
-# $Id$
+# $Id: update-kernel,v 1.9.2.7 2010/07/01 17:22:27 mikpe Exp $
# usage:
# cd ${kernelsrcdir}
# ${perfctrsrcdir}/update-kernel
@@ -12,6 +12,7 @@ dryrun=
sym=
backup=
maybe_redhat=
+maybe_suse=
VERSION=
PATCHLEVEL=
SUBLEVEL=
@@ -37,7 +38,8 @@ get_perfctr_srcdir() {
get_arch() {
if [ -z "$ARCH" ]; then
- ARCH=`uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/`
+ OLDARCH=`uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/`
+ ARCH=`echo $OLDARCH | sed -e s/i386/x86/ -e s/x86_64/x86/ -e s/ppc.*/powerpc/`
fi
}
@@ -79,7 +81,7 @@ get_options() {
}
check_pwd_is_kernel_srcdir() {
- if [ ! -f drivers/Makefile -o ! -f "arch/$ARCH/kernel/Makefile" ]; then
+ if [ ! -f drivers/Makefile -o \( ! -f "arch/$ARCH/kernel/Makefile" -a ! -f "arch/$OLDARCH/kernel/Makefile" \) ]; then
echo "Error: `pwd` does not appear to be the top-level kernel source directory"
usage
fi
@@ -93,14 +95,31 @@ check_kernel_srcdir_is_clean() {
}
get_makefile_variable() {
- eval `grep "^$1 *=" Makefile | head -1 | sed 's/ *= */=/'`
+ eval `grep "^$1 *=" Makefile | head -n 1 | sed 's/ *= */=/'`
+}
+
+get_extra_version() {
+ EXTRAVERSION=`grep "^EXTRAVERSION *=" Makefile | head -n 1 | sed 's/ *= */=/'`
+ case "$EXTRAVERSION" in
+ 'EXTRAVERSION=-$(shell echo $(CONFIG_RELEASE)-$(CONFIG_CFGNAME))')
+ maybe_suse=1
+ EXTRAVERSION='EXTRAVERSION=-$(shell echo $(CONFIG_RELEASE))'
+ ;;
+ esac
+ MKF=`cat <<EOF
+-include .config
+$EXTRAVERSION
+default:
+ @echo EXTRAVERSION='\\$(EXTRAVERSION)'
+EOF`
+ eval `echo "$MKF" | make -f -`
}
get_kernel_version() {
get_makefile_variable VERSION
get_makefile_variable PATCHLEVEL
get_makefile_variable SUBLEVEL
- get_makefile_variable EXTRAVERSION
+ get_extra_version
case "$EXTRAVERSION" in
*custom)
maybe_redhat=1
@@ -156,11 +175,29 @@ try_redhat() {
fi
}
+try_suse() {
+ if [ -n "$EXTRAVERSION" -a -n "$maybe_suse" ]; then
+ if [ -f "$perfctr/patches/patch-kernel-$kernel-suse" ]; then
+ patch="$kernel-suse"
+ echo Found patch for SuSE kernel "$kernel"
+ else
+ alias=`grep ^$kernel-suse $perfctr/patches/aliases | awk -F/ '{ print $2 }'`
+ if [ -n "$alias" -a -f "$perfctr/patches/patch-kernel-$alias" ]; then
+ patch="$alias"
+ echo Using patch "$alias" for SuSE kernel "$kernel"
+ fi
+ fi
+ fi
+}
+
deduce_patch() {
try_standard
if [ -z "$patch" ]; then
try_redhat
fi
+ if [ -z "$patch" ]; then
+ try_suse
+ fi
if [ -z "$patch" ]; then
echo Error: no suitable patch found for kernel "$kernel"
echo See "$perfctr/patches/" for supported kernel versions
@@ -188,29 +225,46 @@ apply_patch() {
patch $dryrun $bVt -p1 < "$perfctr/patches/patch-kernel-$patch"
}
-install_files_by_symlinks() {
- echo ln -sf ${perfctr}/linux/include/asm-$ARCH/perfctr.h include/asm-$ARCH/
- ln -sf ${perfctr}/linux/include/asm-$ARCH/perfctr.h include/asm-$ARCH/
- echo ln -sf ${perfctr}/linux/include/linux/perfctr.h include/linux/
- ln -sf ${perfctr}/linux/include/linux/perfctr.h include/linux/
- echo ln -sf ${perfctr}/linux/drivers/perfctr drivers/
- ln -sf ${perfctr}/linux/drivers/perfctr drivers/
-}
-
-install_files_by_tar() {
- tar -C "$perfctr/linux" --exclude CVS -cf - . | tar -xf -
- rm -f include/asm
+install_file() {
+ if [ -n "$sym" ]; then
+ echo ln -sf ${perfctr}/$1/$2 $3/
+ if [ -z "$dryrun" ]; then
+ ln -sf ${perfctr}/$1/$2 $3/
+ fi
+ else
+ echo tar -C "${perfctr}/$1/" --exclude CVS -cf - $2 '|' tar -C $3/ -xf -
+ if [ -z "$dryrun" ]; then
+ tar -C "${perfctr}/$1/" --exclude CVS -cf - $2 | tar -C $3/ -xf -
+ fi
+ fi
}
install_files() {
echo
echo Installing new kernel source files
echo
- if [ -n "$sym" ]; then
- install_files_by_symlinks
+ if [ -d arch/x86/include/asm ]; then
+ install_file linux/include/asm-x86 perfctr.h arch/x86/include/asm
+ elif [ -d include/asm-x86 ]; then
+ install_file linux/include/asm-x86 perfctr.h include/asm-x86
+ else
+ install_file linux/include/asm-x86 perfctr.h include/asm-i386
+ install_file linux/include/asm-x86 perfctr.h include/asm-x86_64
+ fi
+ if [ -d arch/powerpc/include/asm ]; then
+ install_file linux/include/asm-powerpc perfctr.h arch/powerpc/include/asm
+ elif [ -d include/asm-powerpc ]; then
+ install_file linux/include/asm-powerpc perfctr.h include/asm-powerpc
else
- install_files_by_tar
+ install_file linux/include/asm-powerpc perfctr.h include/asm-ppc
fi
+ if [ -d arch/arm/include/asm ]; then
+ install_file linux/include/asm-arm perfctr.h arch/arm/include/asm
+ else
+ install_file linux/include/asm-arm perfctr.h include/asm-arm
+ fi
+ install_file linux/include/linux perfctr.h include/linux
+ install_file linux/drivers perfctr drivers
}
get_perfctr_srcdir
@@ -223,6 +277,4 @@ if [ -z "$nopatch" ]; then
identify_patch
apply_patch
fi
-if [ -z "$dryrun" ]; then
- install_files
-fi
+install_files
diff --git a/src/perfctr-2.6.x/usr.lib/Makefile b/src/perfctr-2.6.x/usr.lib/Makefile
index 02e3a952a7935b5142596ea390cb1edd44a1b598..43dbe685598357e998e34b78b4b1212947c04582 100755
--- a/src/perfctr-2.6.x/usr.lib/Makefile
+++ b/src/perfctr-2.6.x/usr.lib/Makefile
@@ -1,4 +1,4 @@
-# $Id$
+# $Id: Makefile,v 1.26.2.46 2010/11/07 19:48:14 mikpe Exp $
SHELL=/bin/sh
ARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/)
diff --git a/src/perfctr-2.6.x/usr.lib/arch.h b/src/perfctr-2.6.x/usr.lib/arch.h
index f57f30b0320d4c6bc3a83b63d8dd366368756ce5..1055f65b136bbee93b416a033a659f50033ddad3 100755
--- a/src/perfctr-2.6.x/usr.lib/arch.h
+++ b/src/perfctr-2.6.x/usr.lib/arch.h
@@ -1,7 +1,7 @@
-/* $Id$
+/* $Id: arch.h,v 1.1.2.1 2007/02/11 20:15:03 mikpe Exp $
* Architecture-specific code for performance counters library.
*
- * Copyright (C) 2004 Mikael Pettersson
+ * Copyright (C) 2004-2007 Mikael Pettersson
*/
#ifndef __LIB_PERFCTR_ARCH_H
#define __LIB_PERFCTR_ARCH_H
@@ -10,6 +10,8 @@
#include "x86.h"
#elif defined(__powerpc__)
#include "ppc.h"
+#elif defined(__arm__)
+#include "arm.h"
#endif
#endif /* __LIB_PERFCTR_ARCH_H */
diff --git a/src/perfctr-2.6.x/usr.lib/arm.c b/src/perfctr-2.6.x/usr.lib/arm.c
index 9a785e50b506fc29d72d25f6bacb82f9dd8616dd..6d0b93c6d807d5d85578fd9c784d3b83370ba535 100644
--- a/src/perfctr-2.6.x/usr.lib/arm.c
+++ b/src/perfctr-2.6.x/usr.lib/arm.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: arm.c,v 1.1.2.1 2007/02/11 20:15:03 mikpe Exp $
* ARM-specific perfctr library procedures.
*
* Copyright (C) 2005-2007 Mikael Pettersson
diff --git a/src/perfctr-2.6.x/usr.lib/arm.h b/src/perfctr-2.6.x/usr.lib/arm.h
index 4a6a4f67eb9fe6916f294a0726da59e0f2c79a20..56b65ea93a06ead9d06140cc586ab171b67fb568 100644
--- a/src/perfctr-2.6.x/usr.lib/arm.h
+++ b/src/perfctr-2.6.x/usr.lib/arm.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: arm.h,v 1.1.2.1 2007/02/11 20:15:03 mikpe Exp $
* ARM-specific code for performance counters library.
*
* Copyright (C) 2005-2007 Mikael Pettersson
diff --git a/src/perfctr-2.6.x/usr.lib/event_set.h b/src/perfctr-2.6.x/usr.lib/event_set.h
index 21151a98cbd0eadb1199b168f5ebe83f647fd1cd..3bc2d96b5ffc56be77beab9416ab04994aa42349 100755
--- a/src/perfctr-2.6.x/usr.lib/event_set.h
+++ b/src/perfctr-2.6.x/usr.lib/event_set.h
@@ -1,7 +1,7 @@
-/* $Id$
+/* $Id: event_set.h,v 1.5 2004/02/20 21:32:06 mikpe Exp $
* Common definitions used when creating event set descriptions.
*
- * Copyright (C) 2003 Mikael Pettersson
+ * Copyright (C) 2003-2004 Mikael Pettersson
*/
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
@@ -86,3 +86,4 @@ extern const struct perfctr_event_set perfctr_k7_event_set;
extern const struct perfctr_event_set perfctr_k8_event_set;
extern const struct perfctr_event_set perfctr_pentm_event_set;
extern const struct perfctr_event_set perfctr_k8c_event_set;
+extern const struct perfctr_event_set perfctr_p4m3_event_set;
diff --git a/src/perfctr-2.6.x/usr.lib/event_set_amd.c b/src/perfctr-2.6.x/usr.lib/event_set_amd.c
index 178f3a6022cf2f036f3a530244dc32e10d7d9bf7..58487747e2aa48023bbbffc4d97901838e1e9a7a 100755
--- a/src/perfctr-2.6.x/usr.lib/event_set_amd.c
+++ b/src/perfctr-2.6.x/usr.lib/event_set_amd.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: event_set_amd.c,v 1.8.2.1 2004/08/02 22:27:06 mikpe Exp $
* Performance counter event descriptions for AMD K7 and K8.
*
* Copyright (C) 2003 Mikael Pettersson
@@ -13,7 +13,7 @@
*
* "BIOS and Kernel Developer's Guide for AMD Athlon 64 and
* AMD Opteron Processors", Chapter 10: "Performance Monitoring".
- * AMD Publication #26094, Revision 3.04 (at http://www.amd.com).
+ * AMD Publication #26094, Revision 3.14 (at http://www.amd.com).
* "Revision Guide for AMD Opteron Processors",
* AMD Publication #25759, Revision 3.09
@@ -188,7 +188,7 @@ static const struct perfctr_event k7_unofficial_events[] = {
"Single-bit ECC errors detected/corrected" },
{ 0x75, 0xF, UM(k7_um_invalidates), "INTERNAL_CACHE_LINE_INVALIDATES", /* not in K8 */
"Internal cache line invalidates" },
- { 0x76, 0xF, NULL, "CYCLES_PROCESSOR_IS_RUNNING", /* also in K8, unofficially */
+ { 0x76, 0xF, NULL, "CYCLES_PROCESSOR_IS_RUNNING", /* also in K8 */
"Cycles processor is running (not in HLT or STPCLK)" },
{ 0x79, 0xF, UM(k7_um_L2_requests), "L2_REQUESTS", /* not in K8 */
"L2 requests" },
@@ -447,7 +447,7 @@ static const struct perfctr_event k8_common_events[] = {
{ 0x4B, 0xF, UM(k8_um_prefetch), "DISPATCHED_PRE_INSTRS",
"Dispatched prefetch instructions" },
/* 0x4C: added in Revision C */
- { 0x76, 0xF, NULL, "CYCLES_PROCESSOR_IS_RUNNING", /* undocumented */
+ { 0x76, 0xF, NULL, "CPU_CLK_UNHALTED", /* XXX: was CYCLES_PROCESSOR_IS_RUNNING */
"Cycles processor is running (not in HLT or STPCLK)" },
{ 0x7D, 0xF, UM(k8_um_int_L2_req), "BU_INT_L2_REQ",
"Internal L2 request" },
diff --git a/src/perfctr-2.6.x/usr.lib/event_set_arm.c b/src/perfctr-2.6.x/usr.lib/event_set_arm.c
index 5f9a62094ff9838b864a1e6acd4bb311566c49b5..4b709381ff1c98b0c50c8d89c036c3d86e3654c1 100644
--- a/src/perfctr-2.6.x/usr.lib/event_set_arm.c
+++ b/src/perfctr-2.6.x/usr.lib/event_set_arm.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: event_set_arm.c,v 1.1.2.1 2007/02/11 20:15:03 mikpe Exp $
* Descriptions of the events available for different processor types.
*
* Copyright (C) 2005-2007 Mikael Pettersson
diff --git a/src/perfctr-2.6.x/usr.lib/event_set_centaur.c b/src/perfctr-2.6.x/usr.lib/event_set_centaur.c
index c751e3b1d0099db27b57879b92d7d777e5d7891a..8405309059707fcab6ce944a8cf664bd90373ea0 100755
--- a/src/perfctr-2.6.x/usr.lib/event_set_centaur.c
+++ b/src/perfctr-2.6.x/usr.lib/event_set_centaur.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: event_set_centaur.c,v 1.1 2003/02/16 21:08:54 mikpe Exp $
* Performance counter event descriptions for Centaur chips:
* IDT WinChip C6/2/3 and VIA C3.
*
diff --git a/src/perfctr-2.6.x/usr.lib/event_set_centaur.o b/src/perfctr-2.6.x/usr.lib/event_set_centaur.o
new file mode 100644
index 0000000000000000000000000000000000000000..213e4ce73412d527b5b1197c73e5ec6a03a7ec90
Binary files /dev/null and b/src/perfctr-2.6.x/usr.lib/event_set_centaur.o differ
diff --git a/src/perfctr-2.6.x/usr.lib/event_set_centaur.os b/src/perfctr-2.6.x/usr.lib/event_set_centaur.os
new file mode 100644
index 0000000000000000000000000000000000000000..71a07e23709810c90688995e7435eb426c809b10
Binary files /dev/null and b/src/perfctr-2.6.x/usr.lib/event_set_centaur.os differ
diff --git a/src/perfctr-2.6.x/usr.lib/event_set_p4.c b/src/perfctr-2.6.x/usr.lib/event_set_p4.c
index 30cf25d9096811959e7c6462d6fc5ef3ae09fbd9..97650ff07bf6da9bfaaf6a24489b924713ba0d42 100755
--- a/src/perfctr-2.6.x/usr.lib/event_set_p4.c
+++ b/src/perfctr-2.6.x/usr.lib/event_set_p4.c
@@ -1,7 +1,7 @@
-/* $Id$
+/* $Id: event_set_p4.c,v 1.5 2004/02/20 21:32:06 mikpe Exp $
* Performance counter event descriptions for Intel P4.
*
- * Copyright (C) 2003 Mikael Pettersson
+ * Copyright (C) 2003-2004 Mikael Pettersson
*
* This is still preliminary:
* - need mapping from enum escr_set to <cccr bitmask, escr select>
@@ -199,6 +199,13 @@ static const struct perfctr_unit_mask_2 p4_um_x87_SIMD_moves_uop = {
{ 0x10, "ALLP2:count all x87/SIMD load uops" } }
};
+static const struct perfctr_unit_mask_1 p4_um_TC_misc = {
+ { .type = perfctr_um_type_bitmask,
+ .default_value = 0x10,
+ .nvalues = 1 },
+ { { 0x10, "FLUSH:Number of flushes" } }
+};
+
static const struct perfctr_unit_mask_1 p4_um_global_power_events = {
{ .type = perfctr_um_type_bitmask,
.default_value = 0x01,
@@ -424,6 +431,8 @@ static const struct perfctr_event p4_events[] = {
"x87 floating-point uops" },
{ 0x2E, FIRM_ESCR_0_1, UM(p4_um_x87_SIMD_moves_uop), "x87_SIMD_moves_uop",
"x87 FPU, MMX, SSE, or SSE2 load, store, and move uops" },
+ { 0x06, TC_ESCR_0_1, UM(p4_um_TC_misc), "TC_misc",
+ "miscellaneous events detected by the TC" },
{ 0x13, FSB_ESCR_0_1, UM(p4_um_global_power_events), "global_power_events",
"time during which the processor is not stopped" },
{ 0x05, MS_ESCR_0_1, UM(p4_um_tc_ms_xfer), "tc_ms_xfer",
@@ -486,3 +495,20 @@ const struct perfctr_event_set perfctr_p4_event_set = {
.nevents = ARRAY_SIZE(p4_events),
.events = p4_events,
};
+
+/*
+ * Intel Pentium 4 Model 3 events.
+ */
+
+static const struct perfctr_event p4m3_events[] = {
+ { 0x07, CRU_ESCR_0_1, UM(p4_um_nbogus_bogus), "instr_completed",
+ "retired and completed instructions" },
+};
+
+const struct perfctr_event_set perfctr_p4m3_event_set = {
+ .cpu_type = PERFCTR_X86_INTEL_P4M3,
+ .event_prefix = "P4M3_",
+ .include = &perfctr_p4_event_set,
+ .nevents = ARRAY_SIZE(p4m3_events),
+ .events = p4m3_events,
+};
diff --git a/src/perfctr-2.6.x/usr.lib/event_set_p5.c b/src/perfctr-2.6.x/usr.lib/event_set_p5.c
index c328d70228a5e2a249933284844df08197a73789..80f8939211af474c745a9c9860db273568e897ad 100755
--- a/src/perfctr-2.6.x/usr.lib/event_set_p5.c
+++ b/src/perfctr-2.6.x/usr.lib/event_set_p5.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: event_set_p5.c,v 1.1 2003/02/16 21:08:54 mikpe Exp $
* Performance counter event descriptions for Intel P5 and P5 MMX
* processors, and Cyrix 6x86/MII/III processors.
*
diff --git a/src/perfctr-2.6.x/usr.lib/event_set_p5.o b/src/perfctr-2.6.x/usr.lib/event_set_p5.o
new file mode 100644
index 0000000000000000000000000000000000000000..cc511241385019ab3633ec7ce26386ec04ac796e
Binary files /dev/null and b/src/perfctr-2.6.x/usr.lib/event_set_p5.o differ
diff --git a/src/perfctr-2.6.x/usr.lib/event_set_p5.os b/src/perfctr-2.6.x/usr.lib/event_set_p5.os
new file mode 100644
index 0000000000000000000000000000000000000000..d5aae92916ec59b03ec7b518f08a1baf5fa8573e
Binary files /dev/null and b/src/perfctr-2.6.x/usr.lib/event_set_p5.os differ
diff --git a/src/perfctr-2.6.x/usr.lib/event_set_p6.c b/src/perfctr-2.6.x/usr.lib/event_set_p6.c
index 508a0b5833fcbe3f46ad3231f7ea339696ad043a..59645839de2199a71f276c451fef954950f536ef 100755
--- a/src/perfctr-2.6.x/usr.lib/event_set_p6.c
+++ b/src/perfctr-2.6.x/usr.lib/event_set_p6.c
@@ -1,12 +1,12 @@
-/* $Id$
+/* $Id: event_set_p6.c,v 1.5 2004/05/02 21:45:47 mikpe Exp $
* Performance counter event descriptions for the Intel P6 family.
*
- * Copyright (C) 2003 Mikael Pettersson
+ * Copyright (C) 2003-2004 Mikael Pettersson
*
* References
* ----------
* [IA32, Volume 3] "Intel Architecture Software Developer's Manual,
- * Volume 3: System Programming Guide". Intel document number 245472-011.
+ * Volume 3: System Programming Guide". Intel document number 25366813.
* (at http://developer.intel.com/)
*/
#include <stddef.h> /* for NULL */
@@ -38,81 +38,144 @@ static const struct perfctr_unit_mask_2 p6_um_ebl = {
static const struct perfctr_event p6_events[] = {
/* Data Cache Unit (DCU) */
- { 0x43, 0x3, NULL, "DATA_MEM_REFS" },
- { 0x45, 0x3, NULL, "DCU_LINES_IN" },
- { 0x46, 0x3, NULL, "DCU_M_LINES_IN" },
- { 0x47, 0x3, NULL, "DCU_M_LINES_OUT" },
- { 0x48, 0x3, NULL, "DCU_MISS_OUTSTANDING" },
+ { 0x43, 0x3, NULL, "DATA_MEM_REFS",
+ "All memory references, cachable and non" },
+ { 0x45, 0x3, NULL, "DCU_LINES_IN",
+ "Total lines allocated in the DCU" },
+ { 0x46, 0x3, NULL, "DCU_M_LINES_IN",
+ "Number of M state lines allocated in DCU" },
+ { 0x47, 0x3, NULL, "DCU_M_LINES_OUT",
+ "Number of M lines evicted from the DCU" },
+ { 0x48, 0x3, NULL, "DCU_MISS_OUTSTANDING",
+ "Number of cycles while DCU miss outstanding" },
/* Instruction Fetch Unit (IFU) */
- { 0x80, 0x3, NULL, "IFU_IFETCH" }, /* XXX: was IFU_FETCH */
- { 0x81, 0x3, NULL, "IFU_IFETCH_MISS" }, /* XXX: was IFU_FETCH_MISS */
- { 0x85, 0x3, NULL, "ITLB_MISS" },
- { 0x86, 0x3, NULL, "IFU_MEM_STALL" },
- { 0x87, 0x3, NULL, "ILD_STALL" },
+ { 0x80, 0x3, NULL, "IFU_IFETCH",
+ "Number of non/cachable instruction fetches" }, /* XXX: was IFU_FETCH */
+ { 0x81, 0x3, NULL, "IFU_IFETCH_MISS",
+ "Number of instruction fetch misses" }, /* XXX: was IFU_FETCH_MISS */
+ { 0x85, 0x3, NULL, "ITLB_MISS",
+ "Number of ITLB misses" },
+ { 0x86, 0x3, NULL, "IFU_MEM_STALL",
+ "Cycles instruction fetch pipe is stalled" },
+ { 0x87, 0x3, NULL, "ILD_STALL",
+ "Cycles instruction length decoder is stalled" },
/* L2 Cache */
- { 0x28, 0x3, UM(p6_um_mesi), "L2_IFETCH" },
- { 0x2A, 0x3, UM(p6_um_mesi), "L2_ST" },
- { 0x25, 0x3, NULL, "L2_M_LINES_INM" },
- { 0x2E, 0x3, UM(p6_um_mesi), "L2_RQSTS" },
- { 0x21, 0x3, NULL, "L2_ADS" },
- { 0x22, 0x3, NULL, "L2_DBUS_BUSY" },
- { 0x23, 0x3, NULL, "L2_DBUS_BUSY_RD" },
+ { 0x28, 0x3, UM(p6_um_mesi), "L2_IFETCH",
+ "Number of L2 instruction fetches" },
+ { 0x2A, 0x3, UM(p6_um_mesi), "L2_ST",
+ "Number of L2 data stores" },
+ { 0x25, 0x3, NULL, "L2_M_LINES_INM",
+ "Number of modified lines allocated in L2" },
+ { 0x2E, 0x3, UM(p6_um_mesi), "L2_RQSTS",
+ "Number of L2 requests" },
+ { 0x21, 0x3, NULL, "L2_ADS",
+ "Number of L2 address strobes" },
+ { 0x22, 0x3, NULL, "L2_DBUS_BUSY",
+ "Number of cycles data bus was busy" },
+ { 0x23, 0x3, NULL, "L2_DBUS_BUSY_RD",
+ "Cycles data bus was busy in xfer from L2 to CPU" },
/* External Bus Logic (EBL) */
- { 0x62, 0x3, UM(p6_um_ebl), "BUS_DRDY_CLOCKS" },
- { 0x63, 0x3, UM(p6_um_ebl), "BUS_LOCK_CLOCKS" },
- { 0x60, 0x3, NULL, "BUS_REQ_OUTSTANDING" },
- { 0x65, 0x3, UM(p6_um_ebl), "BUS_TRAN_BRD" },
- { 0x66, 0x3, UM(p6_um_ebl), "BUS_TRAN_RFO" },
- { 0x67, 0x3, UM(p6_um_ebl), "BUS_TRANS_WB" },
- { 0x68, 0x3, UM(p6_um_ebl), "BUS_TRAN_IFETCH" },
- { 0x69, 0x3, UM(p6_um_ebl), "BUS_TRAN_INVAL" },
- { 0x6A, 0x3, UM(p6_um_ebl), "BUS_TRAN_PWR" },
- { 0x6B, 0x3, UM(p6_um_ebl), "BUS_TRANS_P" },
- { 0x6C, 0x3, UM(p6_um_ebl), "BUS_TRANS_IO" },
+ { 0x62, 0x3, UM(p6_um_ebl), "BUS_DRDY_CLOCKS",
+ "Number of clocks DRDY is asserted" },
+ { 0x63, 0x3, UM(p6_um_ebl), "BUS_LOCK_CLOCKS",
+ "Number of clocks LOCK is asserted" },
+ { 0x60, 0x3, NULL, "BUS_REQ_OUTSTANDING",
+ "Number of outstanding bus requests" },
+ { 0x65, 0x3, UM(p6_um_ebl), "BUS_TRAN_BRD",
+ "Number of burst read transactions" },
+ { 0x66, 0x3, UM(p6_um_ebl), "BUS_TRAN_RFO",
+ "Number of read for ownership transactions" },
+ { 0x67, 0x3, UM(p6_um_ebl), "BUS_TRANS_WB",
+ "Number of write back transactions" },
+ { 0x68, 0x3, UM(p6_um_ebl), "BUS_TRAN_IFETCH",
+ "Number of instruction fetch transactions" },
+ { 0x69, 0x3, UM(p6_um_ebl), "BUS_TRAN_INVAL",
+ "Number of invalidate transactions" },
+ { 0x6A, 0x3, UM(p6_um_ebl), "BUS_TRAN_PWR",
+ "Number of partial write transactions" },
+ { 0x6B, 0x3, UM(p6_um_ebl), "BUS_TRANS_P",
+ "Number of partial transactions" },
+ { 0x6C, 0x3, UM(p6_um_ebl), "BUS_TRANS_IO",
+ "Number of I/O transactions" },
{ 0x6D, 0x3, UM(p6_um_ebl), "BUS_TRAN_DEF" },
- { 0x6E, 0x3, UM(p6_um_ebl), "BUS_TRAN_BURST" },
- { 0x70, 0x3, UM(p6_um_ebl), "BUS_TRAN_ANY" },
- { 0x6F, 0x3, UM(p6_um_ebl), "BUS_TRAN_MEM" },
- { 0x64, 0x3, NULL, "BUS_DATA_RCV" },
- { 0x61, 0x3, NULL, "BUS_BNR_DRV" },
- { 0x7A, 0x3, NULL, "BUS_HIT_DRV" },
- { 0x7B, 0x3, NULL, "BUS_HITM_DRV" },
- { 0x7E, 0x3, NULL, "BUS_SNOOP_STALL" },
+ { 0x6E, 0x3, UM(p6_um_ebl), "BUS_TRAN_BURST",
+ "Number of burst transactions" },
+ { 0x70, 0x3, UM(p6_um_ebl), "BUS_TRAN_ANY",
+ "Number of all transactions" },
+ { 0x6F, 0x3, UM(p6_um_ebl), "BUS_TRAN_MEM",
+ "Number of memory transactions" },
+ { 0x64, 0x3, NULL, "BUS_DATA_RCV",
+ "Bus cycles this processor is receiving data" },
+ { 0x61, 0x3, NULL, "BUS_BNR_DRV",
+ "Bus cycles this processor is driving BNR pin" },
+ { 0x7A, 0x3, NULL, "BUS_HIT_DRV",
+ "Bus cycles this processor is driving HIT pin" },
+ { 0x7B, 0x3, NULL, "BUS_HITM_DRV",
+ "Bus cycles this processor is driving HITM pin" },
+ { 0x7E, 0x3, NULL, "BUS_SNOOP_STALL",
+ "Cycles during bus snoop stall" },
/* Floating-Point Unit */
- { 0xC1, 0x1, NULL, "FLOPS" },
- { 0x10, 0x1, NULL, "FP_COMP_OPS_EXE" },
- { 0x11, 0x2, NULL, "FP_ASSIST" },
- { 0x12, 0x2, NULL, "MUL" },
- { 0x13, 0x2, NULL, "DIV" },
- { 0x14, 0x1, NULL, "CYCLES_DIV_BUSY" },
+ { 0xC1, 0x1, NULL, "FLOPS",
+ "Number of computational FP operations executed" },
+ { 0x10, 0x1, NULL, "FP_COMP_OPS_EXE",
+ "Number of computational FP operations executed" },
+ { 0x11, 0x2, NULL, "FP_ASSIST",
+ "Number of FP exceptions handled by microcode" },
+ { 0x12, 0x2, NULL, "MUL",
+ "Number of multiplies" },
+ { 0x13, 0x2, NULL, "DIV",
+ "Number of divides" },
+ { 0x14, 0x1, NULL, "CYCLES_DIV_BUSY",
+ "Cycles divider is busy" },
/* Memory Ordering */
- { 0x03, 0x3, NULL, "LD_BLOCKS" },
- { 0x04, 0x3, NULL, "SB_DRAINS" },
- { 0x05, 0x3, NULL, "MISALIGN_MEM_REF" },
+ { 0x03, 0x3, NULL, "LD_BLOCKS",
+ "Number of store buffer blocks" },
+ { 0x04, 0x3, NULL, "SB_DRAINS",
+ "Number of store buffer drain cycles" },
+ { 0x05, 0x3, NULL, "MISALIGN_MEM_REF",
+ "Number of misaligned data memory references" },
/* Instruction Decoding and Retirement */
- { 0xC0, 0x3, NULL, "INST_RETIRED" },
- { 0xC2, 0x3, NULL, "UOPS_RETIRED" },
- { 0xD0, 0x3, NULL, "INST_DECODED" },
+ { 0xC0, 0x3, NULL, "INST_RETIRED",
+ "Number of instructions retired" },
+ { 0xC2, 0x3, NULL, "UOPS_RETIRED",
+ "Number of UOPs retired" },
+ { 0xD0, 0x3, NULL, "INST_DECODED",
+ "Number of instructions decoded" },
/* Interrupts */
- { 0xC8, 0x3, NULL, "HW_INT_RX" },
- { 0xC6, 0x3, NULL, "CYCLES_INT_MASKED" },
- { 0xC7, 0x3, NULL, "CYCLES_INT_PENDING_AND_MASKED" },
+ { 0xC8, 0x3, NULL, "HW_INT_RX",
+ "Number of hardware interrupts received" },
+ { 0xC6, 0x3, NULL, "CYCLES_INT_MASKED",
+ "Cycles interrupts are disabled" },
+ { 0xC7, 0x3, NULL, "CYCLES_INT_PENDING_AND_MASKED",
+ "Cycles interrupts are disabled with pending interrupts" },
/* Branches */
- { 0xC4, 0x3, NULL, "BR_INST_RETIRED" },
- { 0xC5, 0x3, NULL, "BR_MISS_PRED_RETIRED" },
- { 0xC9, 0x3, NULL, "BR_TAKEN_RETIRED" },
- { 0xCA, 0x3, NULL, "BR_MISS_PRED_TAKEN_RET" },
- { 0xE0, 0x3, NULL, "BR_INST_DECODED" },
- { 0xE2, 0x3, NULL, "BTB_MISSES" },
- { 0xE4, 0x3, NULL, "BR_BOGUS" },
- { 0xE6, 0x3, NULL, "BACLEARS" },
+ { 0xC4, 0x3, NULL, "BR_INST_RETIRED",
+ "Number of branch instructions retired" },
+ { 0xC5, 0x3, NULL, "BR_MISS_PRED_RETIRED",
+ "Number of mispredicted branches retired" },
+ { 0xC9, 0x3, NULL, "BR_TAKEN_RETIRED",
+ "Number of taken branches retired" },
+ { 0xCA, 0x3, NULL, "BR_MISS_PRED_TAKEN_RET",
+ "Number of taken mispredictions branches retired" },
+ { 0xE0, 0x3, NULL, "BR_INST_DECODED",
+ "Number of branch instructions decoded" },
+ { 0xE2, 0x3, NULL, "BTB_MISSES",
+ "Number of branches that miss the BTB" },
+ { 0xE4, 0x3, NULL, "BR_BOGUS",
+ "Number of bogus branches" },
+ { 0xE6, 0x3, NULL, "BACLEARS",
+ "Number of times BACLEAR is asserted" },
/* Stalls */
- { 0xA2, 0x3, NULL, "RESOURCE_STALLS" },
- { 0xD2, 0x3, NULL, "PARTIAL_RAT_STALLS" },
+ { 0xA2, 0x3, NULL, "RESOURCE_STALLS",
+ "Cycles during resource related stalls" },
+ { 0xD2, 0x3, NULL, "PARTIAL_RAT_STALLS",
+ "Cycles or events for partial stalls" },
/* Segment Register Loads */
- { 0x06, 0x3, NULL, "SEGMENT_REG_LOADS" },
+ { 0x06, 0x3, NULL, "SEGMENT_REG_LOADS",
+ "Number of segment register loads" },
/* Clocks */
- { 0x79, 0x3, NULL, "CPU_CLK_UNHALTED" },
+ { 0x79, 0x3, NULL, "CPU_CLK_UNHALTED",
+ "Clocks processor is not halted" },
};
const struct perfctr_event_set p6_event_set = {
@@ -125,10 +188,14 @@ const struct perfctr_event_set p6_event_set = {
static const struct perfctr_event ppro_events[] = {
/* L2 cache */
- { 0x29, 0x3, UM(p6_um_mesi), "L2_LD" }, /* redefined in Pentium M */
- { 0x24, 0x3, NULL, "L2_LINES_IN" }, /* redefined in Pentium M */
- { 0x26, 0x3, NULL, "L2_LINES_OUT" }, /* redefined in Pentium M */
- { 0x27, 0x3, NULL, "L2_M_LINES_OUTM" }, /* redefined in Pentium M */
+ { 0x29, 0x3, UM(p6_um_mesi), "L2_LD",
+ "Number of L2 data loads" }, /* redefined in Pentium M */
+ { 0x24, 0x3, NULL, "L2_LINES_IN",
+ "Number of allocated lines in L2" }, /* redefined in Pentium M */
+ { 0x26, 0x3, NULL, "L2_LINES_OUT",
+ "Number of recovered lines from L2" }, /* redefined in Pentium M */
+ { 0x27, 0x3, NULL, "L2_M_LINES_OUTM",
+ "Number of modified lines removed from L2" }, /* redefined in Pentium M */
};
const struct perfctr_event_set perfctr_ppro_event_set = {
@@ -182,11 +249,16 @@ static const struct perfctr_unit_mask_4 p2_um_seg_reg_rename = {
static const struct perfctr_event p2andp3_events[] = {
/* MMX Unit */
- { 0xB1, 0x3, NULL, "MMX_SAT_INSTR_EXEC" },
- { 0xB2, 0x3, UM(p2_um_mmx_uops_exec), "MMX_UOPS_EXEC" },
- { 0xB3, 0x3, UM(p2_um_mmx_instr_type_exec), "MMX_INSTR_TYPE_EXEC" },
- { 0xCC, 0x3, UM(p2_um_fp_mmx_trans), "FP_MMX_TRANS" },
- { 0xCD, 0x3, NULL, "MMX_ASSIST" },
+ { 0xB1, 0x3, NULL, "MMX_SAT_INSTR_EXEC",
+ "Number of MMX saturating instructions executed" },
+ { 0xB2, 0x3, UM(p2_um_mmx_uops_exec), "MMX_UOPS_EXEC",
+ "Number of MMX UOPS executed" },
+ { 0xB3, 0x3, UM(p2_um_mmx_instr_type_exec), "MMX_INSTR_TYPE_EXEC",
+ "Number of MMX packing instructions" },
+ { 0xCC, 0x3, UM(p2_um_fp_mmx_trans), "FP_MMX_TRANS",
+ "MMX-floating point transitions" },
+ { 0xCD, 0x3, NULL, "MMX_ASSIST",
+ "Number of EMMS instructions executed" },
/* Segment Register Renaming */
{ 0xD4, 0x3, UM(p2_um_seg_reg_rename), "SEG_RENAME_STALLS" },
{ 0xD5, 0x3, UM(p2_um_seg_reg_rename), "SEG_REG_RENAMES" },
@@ -204,7 +276,8 @@ static const struct perfctr_event_set p2andp3_event_set = {
static const struct perfctr_event p2_events[] = { /* not in PIII :-( */
/* MMX Unit */
{ 0xB0, 0x3, NULL, "MMX_INSTR_EXEC" },
- { 0xCE, 0x3, NULL, "MMX_INSTR_RET" },
+ { 0xCE, 0x3, NULL, "MMX_INSTR_RET",
+ "Number of MMX instructions retired" },
};
const struct perfctr_event_set perfctr_p2_event_set = {
@@ -232,8 +305,10 @@ static const struct perfctr_unit_mask_4 p3_um_kni_prefetch = {
static const struct perfctr_event p3_events_1[] = {
/* Memory Ordering */
- { 0x07, 0x3, UM(p3_um_kni_prefetch), "EMON_KNI_PREF_DISPATCHED" },
- { 0x4B, 0x3, UM(p3_um_kni_prefetch), "EMON_KNI_PREF_MISS" },
+ { 0x07, 0x3, UM(p3_um_kni_prefetch), "EMON_KNI_PREF_DISPATCHED",
+ "Number of KNI pre-fetch/weakly ordered insns dispatched" },
+ { 0x4B, 0x3, UM(p3_um_kni_prefetch), "EMON_KNI_PREF_MISS",
+ "Number of KNI pre-fetch/weakly ordered insns that miss all caches" },
};
static const struct perfctr_event_set p3_event_set_1 = {
@@ -254,8 +329,10 @@ static const struct perfctr_unit_mask_2 p3_um_kni_inst_retired = {
static const struct perfctr_event p3_events_2[] = {
/* Instruction Decoding and Retirement */
- { 0xD8, 0x3, UM(p3_um_kni_inst_retired), "EMON_KNI_INST_RETIRED" }, /* redefined in Pentium M */
- { 0xD9, 0x3, UM(p3_um_kni_inst_retired), "EMON_KNI_COMP_INST_RET" }, /* redefined in Pentium M */
+ { 0xD8, 0x3, UM(p3_um_kni_inst_retired), "EMON_KNI_INST_RETIRED",
+ "Number of KNI instructions retired" }, /* redefined in Pentium M */
+ { 0xD9, 0x3, UM(p3_um_kni_inst_retired), "EMON_KNI_COMP_INST_RET",
+ "Number of KNI computation instructions retired" }, /* redefined in Pentium M */
};
const struct perfctr_event_set perfctr_p3_event_set = {
@@ -300,8 +377,8 @@ static const struct perfctr_unit_mask_4 pentm_um_sse_inst_ret = {
{ .type = perfctr_um_type_exclusive,
.default_value = 0x00,
.nvalues = 4 },
- { { 0x00, "SSE Packed Single" },
- { 0x01, "SSE Packed-Single and Scalar-Single" },
+ { { 0x00, "SSE Packed Single and Scalar Single" },
+ { 0x01, "SSE Packed-Single" },
{ 0x02, "SSE2 Packed-Double" },
{ 0x03, "SSE2 Scalar-Double" } }
};
@@ -327,34 +404,57 @@ static const struct perfctr_unit_mask_3 pentm_um_fused_uops = {
static const struct perfctr_event pentm_events[] = {
/* L2 cache */
- { 0x24, 0x3, UM(pentm_um_mesi_prefetch), "L2_LINES_IN" }, /* redefined */
- { 0x26, 0x3, UM(pentm_um_mesi_prefetch), "L2_LINES_OUT" }, /* redefined */
- { 0x27, 0x3, UM(pentm_um_mesi_prefetch), "L2_M_LINES_OUT" }, /* redefined */
- { 0x29, 0x3, UM(pentm_um_mesi_prefetch), "L2_LD" }, /* redefined */
+ { 0x24, 0x3, UM(pentm_um_mesi_prefetch), "L2_LINES_IN",
+ "Number of allocated lines in L2" }, /* redefined */
+ { 0x26, 0x3, UM(pentm_um_mesi_prefetch), "L2_LINES_OUT",
+ "Number of recovered lines from L2" }, /* redefined */
+ { 0x27, 0x3, UM(pentm_um_mesi_prefetch), "L2_M_LINES_OUT",
+ "Number of modified lines in L2, except hardware-prefetched" }, /* redefined */
+ { 0x29, 0x3, UM(pentm_um_mesi_prefetch), "L2_LD",
+ "Number of L2 data loads" }, /* redefined */
/* Power Management */
- { 0x58, 0x3, UM(pentm_um_est_trans), "EMON_EST_TRANS" },
- { 0x59, 0x3, NULL, "EMON_THERMAL_TRIP" /*XXX: set bit 22(!?) for edge */ },
+ { 0x58, 0x3, UM(pentm_um_est_trans), "EMON_EST_TRANS",
+ "Number of SpeedStep(R) thermal transitions" },
+ { 0x59, 0x3, NULL, "EMON_THERMAL_TRIP", /*XXX: set bit 22(!?) for edge */
+ "Number of thermal trips (CPU temp exceeded 100C)" },
/* BPU */
- { 0x88, 0x3, NULL, "BR_INST_EXEC" },
- { 0x89, 0x3, NULL, "BR_MISSP_EXEC" },
- { 0x8A, 0x3, NULL, "BR_BAC_MISSP_EXEC" },
- { 0x8B, 0x3, NULL, "BR_CND_EXEC" },
- { 0x8C, 0x3, NULL, "BR_CND_MISSP_EXEC" },
- { 0x8D, 0x3, NULL, "BR_IND_EXEC" },
- { 0x8E, 0x3, NULL, "BR_IND_MISSP_EXEC" },
- { 0x8F, 0x3, NULL, "BR_RET_EXEC" },
- { 0x90, 0x3, NULL, "BR_RE_MISSP_EXEC" },
- { 0x91, 0x3, NULL, "BR_RET_BAC_MISSP_EXEC" },
- { 0x92, 0x3, NULL, "BR_CALL_EXEC" },
- { 0x93, 0x3, NULL, "BR_CALL_MISSP_EXEC" },
- { 0x94, 0x3, NULL, "BR_IND_CALL_EXEC" },
+ { 0x88, 0x3, NULL, "BR_INST_EXEC",
+ "All executed branches (not necessarily retired)" },
+ { 0x89, 0x3, NULL, "BR_MISSP_EXEC",
+ "Number of branch instruction mispredicted at execution" },
+ { 0x8A, 0x3, NULL, "BR_BAC_MISSP_EXEC",
+ "Number of branch instructions mispredicted at decoding" },
+ { 0x8B, 0x3, NULL, "BR_CND_EXEC",
+ "Number of conditional branch instructions executed" },
+ { 0x8C, 0x3, NULL, "BR_CND_MISSP_EXEC",
+ "Number of mispredicted conditional branch instructions executed" },
+ { 0x8D, 0x3, NULL, "BR_IND_EXEC",
+ "Number of indirect branch instructions executed" },
+ { 0x8E, 0x3, NULL, "BR_IND_MISSP_EXEC",
+ "Number of mispredicted indirect branch instructions executed" },
+ { 0x8F, 0x3, NULL, "BR_RET_EXEC",
+ "Number of return branch instructions executed" },
+ { 0x90, 0x3, NULL, "BR_RET_MISSP_EXEC",
+ "Number of mispredicted return branch instructions executed"},
+ { 0x91, 0x3, NULL, "BR_RET_BAC_MISSP_EXEC",
+ "Number of executed return branch instructions mispredicted at decoding" },
+ { 0x92, 0x3, NULL, "BR_CALL_EXEC",
+ "Number of function calls executed using CALL instruction" },
+ { 0x93, 0x3, NULL, "BR_CALL_MISSP_EXEC",
+ "Number of mispredicted CALL instructions executed" },
+ { 0x94, 0x3, NULL, "BR_IND_CALL_EXEC",
+ "Number of mispredicted indirect CALL instructions executed" },
/* Decoder */
- { 0xCE, 0x3, NULL, "EMON_SIMD_INSTR_RETIRED" },
+ { 0xCE, 0x3, NULL, "EMON_SIMD_INSTR_RETIRED",
+ "Number of SIMD instructions retired" },
{ 0xD3, 0x3, NULL, "EMON_SYNCH_UOPS" },
{ 0xD7, 0x3, NULL, "EMON_ESP_UOPS" },
- { 0xD8, 0x3, UM(pentm_um_sse_inst_ret), "EMON_SSE_SSE2_INST_RETIRED" }, /* redefined */
- { 0xD9, 0x3, UM(pentm_um_sse_comp_inst_ret), "EMON_SSE_SSE2_COMP_INST_RETIRED" }, /* redefined */
- { 0xDA, 0x3, UM(pentm_um_fused_uops), "EMON_FUSED_UOPS_RET" },
+ { 0xD8, 0x3, UM(pentm_um_sse_inst_ret), "EMON_SSE_SSE2_INST_RETIRED",
+ "Number of SSE2 instructions retired" }, /* redefined */
+ { 0xD9, 0x3, UM(pentm_um_sse_comp_inst_ret), "EMON_SSE_SSE2_COMP_INST_RETIRED",
+ "Number of scalar-double SSE2 instructions retired" }, /* redefined */
+ { 0xDA, 0x3, UM(pentm_um_fused_uops), "EMON_FUSED_UOPS_RET",
+ "Number of fused UOPS retired" },
{ 0xDB, 0x3, NULL, "EMON_UNFUSION" },
/* Prefetcher */
{ 0xF0, 0x3, NULL, "EMON_PREF_RQSTS_UP" },
diff --git a/src/perfctr-2.6.x/usr.lib/event_set_p6.o b/src/perfctr-2.6.x/usr.lib/event_set_p6.o
new file mode 100644
index 0000000000000000000000000000000000000000..2a29c94459680ec32f65570b3fcd8b56aa28dd07
Binary files /dev/null and b/src/perfctr-2.6.x/usr.lib/event_set_p6.o differ
diff --git a/src/perfctr-2.6.x/usr.lib/event_set_p6.os b/src/perfctr-2.6.x/usr.lib/event_set_p6.os
new file mode 100644
index 0000000000000000000000000000000000000000..fd5c91de6009683b934c338e25f2f4953e07bb3c
Binary files /dev/null and b/src/perfctr-2.6.x/usr.lib/event_set_p6.os differ
diff --git a/src/perfctr-2.6.x/usr.lib/event_set_ppc.c b/src/perfctr-2.6.x/usr.lib/event_set_ppc.c
index 161af02dddabf6d085851fa9544e24470c83f671..972ab8c9c0ceb57ccfb1b71e566cfa7be69c8b56 100755
--- a/src/perfctr-2.6.x/usr.lib/event_set_ppc.c
+++ b/src/perfctr-2.6.x/usr.lib/event_set_ppc.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: event_set_ppc.c,v 1.2.2.1 2004/08/02 22:26:42 mikpe Exp $
* Descriptions of the events available for different processor types.
*
* Copyright (C) 2004 Mikael Pettersson
@@ -369,7 +369,7 @@ const struct perfctr_event_set perfctr_ppc604e_event_set = {
};
/*
- * PowerPC 750 events. (MPC750, PPC750, PPC750CX, PPC750FX)
+ * PowerPC 750 events. (MPC750, PPC750, PPC750CX, PPC750FX, PPC750GX)
* Unrelated to PPC604/PPC604e, except for the common events 0-4.
*/
@@ -399,7 +399,7 @@ static const struct perfctr_event ppc750_events[] = {
"branch in the instruction stream" },
/* XXX: PPC750 defined PMC1 event 0x0D as L1_ICACHE_MISSES, but that
was probably an error. L1_ICACHE_MISSES is PMC2 event 0x05, and
- MPC750/PPC750CX/PPC750FX don't define PMC1 event 0x0D at all. */
+ MPC750/PPC750CX/PPC750FX/750GX don't define PMC1 event 0x0D at all. */
/*
* PMC2 events
*/
@@ -439,11 +439,11 @@ static const struct perfctr_event ppc750_events[] = {
{ 0x07, 0x04, NULL, "L2_DATA_MISSES",
"Number of L2 data misses" },
{ 0x08, 0x04, NULL, "TAKEN_BRANCHES",
- /* XXX: PPC750/PPC750CX describes this as predicted & taken branches */
+ /* XXX: PPC750/PPC750CX/PPC750FX/PPC750GX describe this as predicted & taken branches */
"Number of taken branches, including predicted branches" },
{ 0x09, 0x04, NULL, "USER_MARKED_UNMARKED_TRANSITIONS",
/* XXX: PPC750 adds a "RESERVED" after the event description.
- PPC750CX and PPC750FX mark event 0x9 as reserved. */
+ PPC750CX/PPC750FX/PPC750GX mark event 0x9 as reserved. */
"Number of transitions between marked and unmarked processes while in "
"user mode. That is, the number of MSR[PM] bit toggles while the "
"processor is in user mode" },
@@ -472,11 +472,11 @@ static const struct perfctr_event ppc750_events[] = {
"Number of cycles spent performing table searches for DTLB accesses" },
/* 0x07: reserved */
{ 0x08, 0x08, NULL, "MISPREDICTED_BRANCHES",
- /* XXX: PPC750/PPC750CX/PPC750FX add a "RESERVED" after the event description */
+ /* XXX: PPC750/PPC750CX/PPC750FX/PPC750GX add "RESERVED" after the event description */
"Number of mispredicted branches" },
{ 0x09, 0x08, NULL, "SUPERVISOR_MARKED_UNMARKED_TRANSITIONS",
/* XXX: In MPC750UM first "supervisor" is "user", presumably a typo.
- PPC750/PPC750CX/PPC750FX mark event 0x09 as reserved. */
+ PPC750/PPC750CX/PPC750FX/PPC750GX mark event 0x09 as reserved. */
"Number of transitions between marked and unmarked processes while in "
"supervisor mode. That is, the number of MSR[PM] bit toggles while the "
"processor is in supervisor mode" },
@@ -494,7 +494,7 @@ static const struct perfctr_event ppc750_events[] = {
"having two unresolved branches" },
/* XXX: PPC750 defined PMC4 event 0x1F as L1_DCACHE_MISSES, but that
was probably an error. L1_DCACHE_MISSES is PMC3 event 0x05, and
- MPC750/PPC750CX/PPC750FX don't define PMC4 event 0x1F at all. */
+ MPC750/PPC750CX/PPC750FX/PPC750GX don't define PMC4 event 0x1F at all. */
};
const struct perfctr_event_set perfctr_ppc750_event_set = {
diff --git a/src/perfctr-2.6.x/usr.lib/event_set_x86.c b/src/perfctr-2.6.x/usr.lib/event_set_x86.c
index 33f8aac89a5217b7680b07551f8e6844dbc52d56..a645f6a11f152a990832e39d362d50c0fadd0b3e 100755
--- a/src/perfctr-2.6.x/usr.lib/event_set_x86.c
+++ b/src/perfctr-2.6.x/usr.lib/event_set_x86.c
@@ -1,7 +1,7 @@
-/* $Id$
+/* $Id: event_set_x86.c,v 1.2.2.1 2004/08/02 22:27:27 mikpe Exp $
* Descriptions of the events available for different processor types.
*
- * Copyright (C) 1999-2003 Mikael Pettersson
+ * Copyright (C) 1999-2004 Mikael Pettersson
*/
#include <stddef.h> /* for NULL */
#include "libperfctr.h"
@@ -40,6 +40,7 @@ static const struct perfctr_event_set * const cpu_event_set[] = {
[PERFCTR_X86_INTEL_P4M2] = &perfctr_p4_event_set,
[PERFCTR_X86_INTEL_PENTM] = &perfctr_pentm_event_set,
#endif
+ [PERFCTR_X86_INTEL_P4M3] = &perfctr_p4m3_event_set,
[PERFCTR_X86_AMD_K8] = &perfctr_k8_event_set,
[PERFCTR_X86_AMD_K8C] = &perfctr_k8c_event_set,
};
diff --git a/src/perfctr-2.6.x/usr.lib/gen-event-codes.c b/src/perfctr-2.6.x/usr.lib/gen-event-codes.c
index 716e035621b2e2278bd2b632cc95f30dd564ced8..f470fafd57d2f9efd950d67fe9997cbaa1ae4b4a 100755
--- a/src/perfctr-2.6.x/usr.lib/gen-event-codes.c
+++ b/src/perfctr-2.6.x/usr.lib/gen-event-codes.c
@@ -1,8 +1,8 @@
-/* $Id$
+/* $Id: gen-event-codes.c,v 1.7.2.2 2007/02/11 20:15:03 mikpe Exp $
*
* Generate symbolic constants for performance counter events.
*
- * Copyright (C) 2003-2004 Mikael Pettersson
+ * Copyright (C) 2003-2007 Mikael Pettersson
*/
#include <stdio.h>
#include <stdlib.h> /* for exit() */
@@ -66,6 +66,7 @@ int main(void)
print_cpu_type(PERFCTR_X86_AMD_K7);
#endif
#if defined(__i386__) || defined(__x86_64__)
+ print_cpu_type(PERFCTR_X86_INTEL_P4M3);
print_cpu_type(PERFCTR_X86_AMD_K8);
print_cpu_type(PERFCTR_X86_AMD_K8C);
#endif
@@ -73,6 +74,9 @@ int main(void)
print_cpu_type(PERFCTR_PPC_604);
print_cpu_type(PERFCTR_PPC_604e);
print_cpu_type(PERFCTR_PPC_750);
+#endif
+#if defined(__arm__)
+ print_cpu_type(PERFCTR_ARM_XSC1);
#endif
return 0;
}
diff --git a/src/perfctr-2.6.x/usr.lib/global.c b/src/perfctr-2.6.x/usr.lib/global.c
index c408c632ce209267dfdc508d3cceee5d1ca06128..4ca3eb2c95a62976472254c7b7b29fbb8cfa7392 100755
--- a/src/perfctr-2.6.x/usr.lib/global.c
+++ b/src/perfctr-2.6.x/usr.lib/global.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: global.c,v 1.10 2003/08/19 13:37:08 mikpe Exp $
* Library interface to global-mode performance counters.
*
* Copyright (C) 1999-2003 Mikael Pettersson
diff --git a/src/perfctr-2.6.x/usr.lib/libperfctr.h b/src/perfctr-2.6.x/usr.lib/libperfctr.h
index c299f636f9e65753bd1058b88b9436c7e744e75a..f0ddb009a69800d5fc5b440e340f2c5f12b85a5d 100755
--- a/src/perfctr-2.6.x/usr.lib/libperfctr.h
+++ b/src/perfctr-2.6.x/usr.lib/libperfctr.h
@@ -1,7 +1,7 @@
-/* $Id$
+/* $Id: libperfctr.h,v 1.35.2.3 2009/01/23 20:25:42 mikpe Exp $
* Library interface to Linux x86 Performance-Monitoring Counters.
*
- * Copyright (C) 1999-2003 Mikael Pettersson
+ * Copyright (C) 1999-2009 Mikael Pettersson
*/
#ifndef __LIB_PERFCTR_H
@@ -26,6 +26,9 @@ int _vperfctr_read_sum(int fd, struct perfctr_sum_ctrs*);
struct vperfctr; /* opaque */
+struct vperfctr *vperfctr_open_mode(unsigned int mode);
+#define VPERFCTR_OPEN_CREAT_EXCL 3
+
struct vperfctr *vperfctr_open(void);
int vperfctr_info(const struct vperfctr*, struct perfctr_info*);
struct perfctr_cpus_info *vperfctr_cpus_info(const struct vperfctr*);
@@ -56,6 +59,7 @@ int rvperfctr_read_state(const struct rvperfctr*, struct perfctr_sum_ctrs*,
struct vperfctr_control*);
int rvperfctr_control(const struct rvperfctr*, struct vperfctr_control*);
int rvperfctr_stop(const struct rvperfctr*);
+int rvperfctr_iresume(const struct rvperfctr*);
int rvperfctr_unlink(const struct rvperfctr*);
void rvperfctr_close(struct rvperfctr*);
@@ -127,6 +131,7 @@ static __inline__ int perfctr_abi_check_fd(int fd)
}
int perfctr_info(int fd, struct perfctr_info *info);
+int perfctr_get_info(struct perfctr_info *info);
struct perfctr_cpus_info *perfctr_cpus_info(int fd);
unsigned int perfctr_info_nrctrs(const struct perfctr_info*);
const char *perfctr_info_cpu_name(const struct perfctr_info*);
diff --git a/src/perfctr-2.6.x/usr.lib/misc.c b/src/perfctr-2.6.x/usr.lib/misc.c
index f98de0bc77c02a2b9442efb567b9774fd1b2201f..a4ca338e7e7b457b3bf9007d643932c471769203 100755
--- a/src/perfctr-2.6.x/usr.lib/misc.c
+++ b/src/perfctr-2.6.x/usr.lib/misc.c
@@ -1,14 +1,16 @@
-/* $Id$
+/* $Id: misc.c,v 1.20.2.1 2005/12/22 22:44:49 mikpe Exp $
* Miscellaneous perfctr operations.
*
* Copyright (C) 1999-2004 Mikael Pettersson
*/
#include <errno.h>
+#include <fcntl.h>
#include <sys/ioctl.h>
#include <stddef.h>
#include <stdio.h>
#include <stdlib.h>
+#include <unistd.h>
#include "libperfctr.h"
#include "marshal.h"
#include "arch.h"
@@ -40,6 +42,18 @@ int perfctr_info(int fd, struct perfctr_info *info)
return 0;
}
+int perfctr_get_info(struct perfctr_info *info)
+{
+ int fd, ret;
+
+ fd = open("/dev/perfctr", O_RDONLY);
+ if (fd < 0)
+ return -1;
+ ret = perfctr_info(fd, info);
+ close(fd);
+ return ret;
+}
+
struct perfctr_cpus_info *perfctr_cpus_info(int fd)
{
struct perfctr_cpu_mask dummy;
diff --git a/src/perfctr-2.6.x/usr.lib/ppc.c b/src/perfctr-2.6.x/usr.lib/ppc.c
index 53a50fd6338ea48456560c75363bca1a3c2ba33c..c83db13319d8a77153e9b7a65d2d5810dccfa49a 100755
--- a/src/perfctr-2.6.x/usr.lib/ppc.c
+++ b/src/perfctr-2.6.x/usr.lib/ppc.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: ppc.c,v 1.2.2.3 2004/11/13 16:31:09 mikpe Exp $
* PPC32-specific perfctr library procedures.
*
* Copyright (C) 2004 Mikael Pettersson
@@ -22,6 +22,7 @@ void perfctr_info_cpu_init(struct perfctr_info *info)
break;
case 0x0008: /* 750/740 */
case 0x7000: case 0x7001: /* 750FX */
+ case 0x7002: /* 750GX */
cpu_type = PERFCTR_PPC_750;
break;
case 0x000C: /* 7400 */
@@ -31,10 +32,12 @@ void perfctr_info_cpu_init(struct perfctr_info *info)
case 0x8000: /* 7451/7441 */
case 0x8001: /* 7455/7445 */
case 0x8002: /* 7457/7447 */
+ case 0x8003: /* 7447A */
+ case 0x8004: /* 7448 */
cpu_type = PERFCTR_PPC_7450;
break;
default:
- cpu_type = 0;
+ cpu_type = PERFCTR_PPC_GENERIC;
}
info->cpu_type = cpu_type;
}
@@ -58,6 +61,8 @@ unsigned int perfctr_info_nrctrs(const struct perfctr_info *info)
const char *perfctr_info_cpu_name(const struct perfctr_info *info)
{
switch( info->cpu_type ) {
+ case PERFCTR_PPC_GENERIC:
+ return "Generic PowerPC with TB";
case PERFCTR_PPC_604:
return "PowerPC 604";
case PERFCTR_PPC_604e:
diff --git a/src/perfctr-2.6.x/usr.lib/ppc.h b/src/perfctr-2.6.x/usr.lib/ppc.h
index 601a50213ae194ca8b8a170a8e7e3d6860c6c6e2..295b70cbcc7f33d3dc9a4fd88ddc8f2f9ce8a84a 100755
--- a/src/perfctr-2.6.x/usr.lib/ppc.h
+++ b/src/perfctr-2.6.x/usr.lib/ppc.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: ppc.h,v 1.1 2004/01/26 13:21:41 mikpe Exp $
* PPC32-specific code for performance counters library.
*
* Copyright (C) 2004 Mikael Pettersson
diff --git a/src/perfctr-2.6.x/usr.lib/virtual.c b/src/perfctr-2.6.x/usr.lib/virtual.c
index 5a555b4ab77be80e0b1bc7ca779d21c5077b0f5a..37069e1612db28f6bc4728901ebc889b18233096 100755
--- a/src/perfctr-2.6.x/usr.lib/virtual.c
+++ b/src/perfctr-2.6.x/usr.lib/virtual.c
@@ -1,7 +1,7 @@
-/* $Id$
+/* $Id: virtual.c,v 1.22.2.10 2009/01/23 20:25:42 mikpe Exp $
* Library interface to virtual per-process performance counters.
*
- * Copyright (C) 1999-2004 Mikael Pettersson
+ * Copyright (C) 1999-2009 Mikael Pettersson
*/
#include <stdio.h>
@@ -20,49 +20,23 @@
/*
* Code to open (with or without creation) per-process perfctrs,
- * for both the current open("/proc/pid/perfctr", mode) and the
- * future ioctl(dev_perfctr_fd, VPERFCTR_{CREAT,OPEN}, pid) APIs.
+ * using the ioctl(dev_perfctr_fd, VPERFCTR_{CREAT,OPEN}, pid) API.
*/
-static int _vperfctr_open_pid_old(int pid, int try_creat, int try_rdonly, int *isnew)
-{
- const char *filename;
- char namebuf[64];
- int fd;
-
- if( !pid )
- filename = "/proc/self/perfctr";
- else {
- snprintf(namebuf, sizeof namebuf, "/proc/%d/perfctr", pid);
- filename = namebuf;
- }
- *isnew = 1;
- fd = -1;
- if( try_creat )
- fd = open(filename, O_RDONLY|O_CREAT);
- if( fd < 0 && (try_creat ? errno == EEXIST : 1) && try_rdonly ) {
- *isnew = 0;
- fd = open(filename, O_RDONLY);
- }
- return fd;
-}
-
-static int _vperfctr_open_pid_new(int pid, int try_creat, int try_rdonly, int *isnew)
+static int _vperfctr_open_pid(int pid, int try_creat)
{
int dev_perfctr_fd, fd;
dev_perfctr_fd = open("/dev/perfctr", O_RDONLY);
- if( dev_perfctr_fd < 0 )
+ if (dev_perfctr_fd < 0)
return -1;
- *isnew = 1;
- fd = -1;
- if( try_creat )
+ if (try_creat)
fd = ioctl(dev_perfctr_fd, VPERFCTR_CREAT, pid);
- if( fd < 0 && (try_creat ? errno == EEXIST : 1) && try_rdonly ) {
- *isnew = 0;
+ else
fd = ioctl(dev_perfctr_fd, VPERFCTR_OPEN, pid);
- }
close(dev_perfctr_fd);
+ if (fcntl(fd, F_SETFD, FD_CLOEXEC) < 0)
+ perror("fcntl");
return fd;
}
@@ -72,12 +46,7 @@ static int _vperfctr_open_pid_new(int pid, int try_creat, int try_rdonly, int *i
int _vperfctr_open(int creat)
{
- int dummy, fd;
-
- fd = _vperfctr_open_pid_new(0, creat, !creat, &dummy);
- if( fd < 0 )
- fd = _vperfctr_open_pid_old(0, creat, !creat, &dummy);
- return fd;
+ return _vperfctr_open_pid(0, creat);
}
int _vperfctr_control(int fd, const struct vperfctr_control *control)
@@ -106,49 +75,59 @@ struct vperfctr {
unsigned char have_rdpmc;
};
-static int vperfctr_open_pid(int pid, struct vperfctr *perfctr)
+static int vperfctr_open_pid(int pid, struct vperfctr *perfctr, unsigned int mode)
{
- int fd, isnew;
+ int fd, creat;
struct perfctr_info info;
- fd = _vperfctr_open_pid_new(pid, 1, 1, &isnew);
- if( fd < 0 ) {
- fd = _vperfctr_open_pid_old(pid, 1, 1, &isnew);
- if( fd < 0 )
- goto out_perfctr;
+ if (mode == 0)
+ creat = 0;
+ else if (mode == VPERFCTR_OPEN_CREAT_EXCL)
+ creat = 1;
+ else {
+ errno = EINVAL;
+ return -1;
}
+ fd = _vperfctr_open_pid(pid, creat);
+ if (fd < 0)
+ goto out_perfctr;
perfctr->fd = fd;
- if( perfctr_abi_check_fd(perfctr->fd) < 0 )
+ if (perfctr_abi_check_fd(perfctr->fd) < 0)
goto out_fd;
- if( perfctr_info(perfctr->fd, &info) < 0 )
+ if (perfctr_info(perfctr->fd, &info) < 0)
goto out_fd;
perfctr->have_rdpmc = (info.cpu_features & PERFCTR_FEATURE_RDPMC) != 0;
perfctr->kstate = mmap(NULL, PAGE_SIZE, PROT_READ,
MAP_SHARED, perfctr->fd, 0);
- if( perfctr->kstate != MAP_FAILED )
+ if (perfctr->kstate != MAP_FAILED)
return 0;
munmap((void*)perfctr->kstate, PAGE_SIZE);
out_fd:
- if( isnew )
+ if (creat)
vperfctr_unlink(perfctr);
close(perfctr->fd);
out_perfctr:
return -1;
}
-struct vperfctr *vperfctr_open(void)
+struct vperfctr *vperfctr_open_mode(unsigned int mode)
{
struct vperfctr *perfctr;
perfctr = malloc(sizeof(*perfctr));
- if( perfctr ) {
- if( vperfctr_open_pid(0, perfctr) == 0 )
+ if (perfctr) {
+ if (vperfctr_open_pid(0, perfctr, mode) == 0)
return perfctr;
free(perfctr);
}
return NULL;
}
+struct vperfctr *vperfctr_open(void)
+{
+ return vperfctr_open_mode(VPERFCTR_OPEN_CREAT_EXCL);
+}
+
int vperfctr_info(const struct vperfctr *vperfctr, struct perfctr_info *info)
{
return perfctr_info(vperfctr->fd, info);
@@ -168,51 +147,60 @@ struct perfctr_cpus_info *vperfctr_cpus_info(const struct vperfctr *vperfctr)
unsigned long long vperfctr_read_tsc(const struct vperfctr *self)
{
+#if defined(rdtscl)
unsigned long long sum;
unsigned int tsc0, tsc1, now;
volatile const struct vperfctr_state *kstate;
kstate = self->kstate;
- if( likely(kstate->cpu_state.cstatus != 0) ) {
+ if (likely(kstate->cpu_state.cstatus != 0)) {
tsc0 = kstate->cpu_state.tsc_start;
retry:
rdtscl(now);
sum = kstate->cpu_state.tsc_sum;
tsc1 = kstate->cpu_state.tsc_start;
- if( likely(tsc1 == tsc0) )
+ if (likely(tsc1 == tsc0))
return sum += (now - tsc0);
tsc0 = tsc1;
goto retry; /* better gcc code than with a do{}while() loop */
}
return kstate->cpu_state.tsc_sum;
+#else
+ struct perfctr_sum_ctrs sum_ctrs;
+ if (_vperfctr_read_sum(self->fd, &sum_ctrs) < 0)
+ perror(__FUNCTION__);
+ return sum_ctrs.tsc;
+#endif
}
unsigned long long vperfctr_read_pmc(const struct vperfctr *self, unsigned i)
{
+ struct perfctr_sum_ctrs sum_ctrs;
+#if defined(rdpmcl)
unsigned long long sum;
unsigned int start, now;
unsigned int tsc0, tsc1;
volatile const struct vperfctr_state *kstate;
unsigned int cstatus;
- struct perfctr_sum_ctrs sum_ctrs;
kstate = self->kstate;
cstatus = kstate->cpu_state.cstatus;
/* gcc 3.0 generates crap code for likely(E1 && E2) :-( */
- if( perfctr_cstatus_has_tsc(cstatus) && vperfctr_has_rdpmc(self) ) {
+ if (perfctr_cstatus_has_tsc(cstatus) && vperfctr_has_rdpmc(self)) {
tsc0 = kstate->cpu_state.tsc_start;
retry:
rdpmcl(kstate->cpu_state.pmc[i].map, now);
start = kstate->cpu_state.pmc[i].start;
sum = kstate->cpu_state.pmc[i].sum;
tsc1 = kstate->cpu_state.tsc_start;
- if( likely(tsc1 == tsc0) ) {
+ if (likely(tsc1 == tsc0)) {
return sum += (now - start);
}
tsc0 = tsc1;
goto retry;
}
- if( _vperfctr_read_sum(self->fd, &sum_ctrs) < 0 )
+#endif
+ if (_vperfctr_read_sum(self->fd, &sum_ctrs) < 0)
perror(__FUNCTION__);
return sum_ctrs.pmc[i];
}
@@ -226,6 +214,7 @@ static int vperfctr_read_ctrs_slow(const struct vperfctr *vperfctr,
int vperfctr_read_ctrs(const struct vperfctr *self,
struct perfctr_sum_ctrs *sum)
{
+#if defined(rdtscl) && defined(rdpmcl)
unsigned int tsc0, now;
unsigned int cstatus, nrctrs;
volatile const struct vperfctr_state *kstate;
@@ -237,7 +226,7 @@ int vperfctr_read_ctrs(const struct vperfctr *self,
kstate = self->kstate;
cstatus = kstate->cpu_state.cstatus;
nrctrs = perfctr_cstatus_nrctrs(cstatus);
- if( perfctr_cstatus_has_tsc(cstatus) && (!nrctrs || vperfctr_has_rdpmc(self)) ) {
+ if (perfctr_cstatus_has_tsc(cstatus) && (!nrctrs || vperfctr_has_rdpmc(self))) {
retry:
tsc0 = kstate->cpu_state.tsc_start;
rdtscl(now);
@@ -246,20 +235,21 @@ int vperfctr_read_ctrs(const struct vperfctr *self,
rdpmcl(kstate->cpu_state.pmc[i].map, now);
sum->pmc[i] = kstate->cpu_state.pmc[i].sum + (now - kstate->cpu_state.pmc[i].start);
}
- if( likely(tsc0 == kstate->cpu_state.tsc_start) )
+ if (likely(tsc0 == kstate->cpu_state.tsc_start))
return 0;
goto retry;
}
+#endif
return vperfctr_read_ctrs_slow(self, sum);
}
int vperfctr_read_state(const struct vperfctr *self, struct perfctr_sum_ctrs *sum,
struct vperfctr_control *control)
{
- if( _vperfctr_read_sum(self->fd, sum) < 0 )
+ if (_vperfctr_read_sum(self->fd, sum) < 0)
return -1;
/* For historical reasons, control may be NULL. */
- if( control && _vperfctr_read_control(self->fd, control) < 0 )
+ if (control && _vperfctr_read_control(self->fd, control) < 0)
return -1;
return 0;
}
@@ -313,8 +303,8 @@ struct rvperfctr *rvperfctr_open(int pid)
struct rvperfctr *rvperfctr;
rvperfctr = malloc(sizeof(*rvperfctr));
- if( rvperfctr ) {
- if( vperfctr_open_pid(pid, &rvperfctr->vperfctr) == 0 ) {
+ if (rvperfctr) {
+ if (vperfctr_open_pid(pid, &rvperfctr->vperfctr, VPERFCTR_OPEN_CREAT_EXCL) == 0) {
rvperfctr->pid = pid;
return rvperfctr;
}
@@ -357,6 +347,11 @@ int rvperfctr_stop(const struct rvperfctr *rvperfctr)
return vperfctr_stop(&rvperfctr->vperfctr);
}
+int rvperfctr_iresume(const struct rvperfctr *rvperfctr)
+{
+ return vperfctr_iresume(&rvperfctr->vperfctr);
+}
+
int rvperfctr_unlink(const struct rvperfctr *rvperfctr)
{
return vperfctr_unlink(&rvperfctr->vperfctr);
diff --git a/src/perfctr-2.6.x/usr.lib/x86.c b/src/perfctr-2.6.x/usr.lib/x86.c
index d5b841a5bf9c1411dc6425c95860119fc65dd136..2d05c381f601fda30d99e536b8346ed886bf0407 100755
--- a/src/perfctr-2.6.x/usr.lib/x86.c
+++ b/src/perfctr-2.6.x/usr.lib/x86.c
@@ -1,41 +1,97 @@
-/* $Id$
+/* $Id: x86.c,v 1.2.2.11 2010/11/07 19:46:06 mikpe Exp $
* x86-specific perfctr library procedures.
*
- * Copyright (C) 1999-2004 Mikael Pettersson
+ * Copyright (C) 1999-2010 Mikael Pettersson
*/
#include <stdio.h>
#include "libperfctr.h"
-unsigned int perfctr_info_nrctrs(const struct perfctr_info *info)
+struct cpuid { /* The field order must not be changed. */
+ unsigned int eax;
+ unsigned int ebx; /* When eax was 1, &ebx should be the start */
+ unsigned int edx; /* of the 12-byte vendor identification string. */
+ unsigned int ecx;
+};
+
+static void get_cpuid(unsigned int op, struct cpuid *cpuid)
{
- switch( info->cpu_type ) {
-#if defined(__x86_64__)
- case PERFCTR_X86_AMD_K8:
- case PERFCTR_X86_AMD_K8C:
- return 4;
- default:
+ unsigned int save_ebx;
+ unsigned int tmp_ebx;
+
+ __asm__(
+ "movl %%ebx, %0\n\t"
+ "cpuid\n\t"
+ "movl %%ebx, %1\n\t"
+ "movl %0, %%ebx"
+ : "=m"(save_ebx), "=m"(tmp_ebx), "=a"(cpuid->eax), "=d"(cpuid->edx), "=c"(cpuid->ecx)
+ : "a"(op));
+ cpuid->ebx = tmp_ebx;
+}
+
+static unsigned int atom_nrctrs(void)
+{
+ struct cpuid cpuid;
+
+ get_cpuid(0, &cpuid);
+ if (cpuid.eax < 0xA) {
+ printf("%s: cpuid[0].eax == %u, unable to query 0xA leaf\n",
+ __FUNCTION__, cpuid.eax);
return 0;
-#else
- case PERFCTR_X86_GENERIC:
+ }
+ get_cpuid(0xA, &cpuid);
+ if ((cpuid.eax & 0xff) < 2) {
+ printf("%s: cpuid[0xA].eax == 0x%08x appears bogus\n",
+ __FUNCTION__, cpuid.eax);
return 0;
- case PERFCTR_X86_VIA_C3:
- return 1;
+ }
+ return ((cpuid.eax >> 8) & 0xff) + (cpuid.edx & 0x1f);
+}
+
+unsigned int perfctr_info_nrctrs(const struct perfctr_info *info)
+{
+ switch (info->cpu_type) {
+#if !defined(__x86_64__)
+ case PERFCTR_X86_INTEL_P5:
+ case PERFCTR_X86_INTEL_P5MMX:
+ case PERFCTR_X86_INTEL_P6:
+ case PERFCTR_X86_INTEL_PII:
+ case PERFCTR_X86_INTEL_PIII:
+ case PERFCTR_X86_CYRIX_MII:
+ case PERFCTR_X86_WINCHIP_C6:
+ case PERFCTR_X86_WINCHIP_2:
+ case PERFCTR_X86_INTEL_PENTM:
+ case PERFCTR_X86_INTEL_CORE:
+ return 2;
case PERFCTR_X86_AMD_K7:
- case PERFCTR_X86_AMD_K8:
- case PERFCTR_X86_AMD_K8C:
return 4;
+ case PERFCTR_X86_VIA_C3:
+ return 1;
case PERFCTR_X86_INTEL_P4:
case PERFCTR_X86_INTEL_P4M2:
return 18;
+#endif
+ case PERFCTR_X86_INTEL_P4M3:
+ return 18;
+ case PERFCTR_X86_AMD_K8:
+ case PERFCTR_X86_AMD_K8C:
+ case PERFCTR_X86_AMD_FAM10H:
+ return 4;
+ case PERFCTR_X86_INTEL_CORE2:
+ return 5;
+ case PERFCTR_X86_INTEL_ATOM:
+ return atom_nrctrs();
+ case PERFCTR_X86_INTEL_NHLM:
+ case PERFCTR_X86_INTEL_WSTMR:
+ return 7;
+ case PERFCTR_X86_GENERIC:
default:
- return 2;
-#endif
+ return 0;
}
}
const char *perfctr_info_cpu_name(const struct perfctr_info *info)
{
- switch( info->cpu_type ) {
+ switch (info->cpu_type) {
case PERFCTR_X86_GENERIC:
return "Generic x86 with TSC";
#if !defined(__x86_64__)
@@ -65,11 +121,25 @@ const char *perfctr_info_cpu_name(const struct perfctr_info *info)
return "Intel Pentium 4 Model 2";
case PERFCTR_X86_INTEL_PENTM:
return "Intel Pentium M";
+ case PERFCTR_X86_INTEL_CORE:
+ return "Intel Core";
#endif
+ case PERFCTR_X86_INTEL_CORE2:
+ return "Intel Core 2";
+ case PERFCTR_X86_INTEL_P4M3:
+ return "Intel Pentium 4 Model 3";
case PERFCTR_X86_AMD_K8:
return "AMD K8";
case PERFCTR_X86_AMD_K8C:
return "AMD K8 Revision C";
+ case PERFCTR_X86_AMD_FAM10H:
+ return "AMD Family 10h";
+ case PERFCTR_X86_INTEL_ATOM:
+ return "Intel Atom";
+ case PERFCTR_X86_INTEL_NHLM:
+ return "Intel Nehalem";
+ case PERFCTR_X86_INTEL_WSTMR:
+ return "Intel Westmere";
default:
return "?";
}
@@ -85,25 +155,21 @@ void perfctr_cpu_control_print(const struct perfctr_cpu_control *control)
printf("tsc_on\t\t\t%u\n", control->tsc_on);
printf("nractrs\t\t\t%u\n", nractrs);
- if( nrictrs )
+ if (nrictrs)
printf("nrictrs\t\t\t%u\n", nrictrs);
for(i = 0; i < nrctrs; ++i) {
- if( control->pmc_map[i] >= 18 ) /* for P4 'fast rdpmc' cases */
+ if (control->pmc_map[i] >= 18) /* for Core2 fixed counters or P4 fast rdpmc */
printf("pmc_map[%u]\t\t0x%08X\n", i, control->pmc_map[i]);
else
printf("pmc_map[%u]\t\t%u\n", i, control->pmc_map[i]);
printf("evntsel[%u]\t\t0x%08X\n", i, control->evntsel[i]);
-#if !defined(__x86_64__)
- if( control->p4.escr[i] )
+ if (control->p4.escr[i])
printf("escr[%u]\t\t\t0x%08X\n", i, control->p4.escr[i]);
-#endif
- if( i >= nractrs )
+ if (i >= nractrs)
printf("ireset[%u]\t\t%d\n", i, control->ireset[i]);
}
-#if !defined(__x86_64__)
- if( control->p4.pebs_enable )
+ if (control->p4.pebs_enable)
printf("pebs_enable\t\t0x%08X\n", control->p4.pebs_enable);
- if( control->p4.pebs_matrix_vert )
+ if (control->p4.pebs_matrix_vert)
printf("pebs_matrix_vert\t0x%08X\n", control->p4.pebs_matrix_vert);
-#endif
}
diff --git a/src/perfctr-2.6.x/usr.lib/x86.h b/src/perfctr-2.6.x/usr.lib/x86.h
index e1f394cf0fb1d0153b35ffa1315b9d4d724b3dbb..757c61f7933ef6f3690ef605ef4c03049f1ad553 100755
--- a/src/perfctr-2.6.x/usr.lib/x86.h
+++ b/src/perfctr-2.6.x/usr.lib/x86.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: x86.h,v 1.1 2004/01/26 13:21:41 mikpe Exp $
* x86-specific code for performance counters library.
*
* Copyright (C) 1999-2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/CHANGES b/src/perfctr-2.7.x/CHANGES
index 65e6d43b8c9ffc08b30fd72795b50b5ff8c86164..4f7bb31b658f68b731d84342dbc2c8ee97312b2c 100644
--- a/src/perfctr-2.7.x/CHANGES
+++ b/src/perfctr-2.7.x/CHANGES
@@ -1,4 +1,4 @@
-$Id$
+$Id: CHANGES,v 1.177 2007/10/06 13:02:07 mikpe Exp $
CHANGES
=======
@@ -6,6 +6,50 @@ $Id$
[High-level changes in reverse chronological order. Detailed
driver changes are in linux/drivers/perfctr/RELEASE-NOTES.]
+Version 2.7.21.1, 2007-10-06
+- ppc64: recognise the PowerPC 970MP.
+- Perfex: On ppc64, do not truncate the MMCR1 value to 32 bits.
+ Bug fix from Philip Mucci.
+
+Version 2.7.21, 2007-10-03
+- Updated to support kernels 2.6.18 to 2.6.22. The system
+ call numbers used in these kernels differs from those used
+ in older kernels. The user-space library has been updated
+ and will support both these newer kernels as well as the
+ older kernels supported by perfctr-2.7.19/2.7.20/2.7.20.2.
+- Corrected kernel driver Makefile to unbreak call-site
+ backpatching in the x86 driver.
+- Updated x86 driver to match the one in perfctr-2.6.28 in
+ terms of fixes, CPU support, and kernel version support.
+- Updated references to my email address and perfctrs' web URL
+ to match current reality.
+
+Version 2.7.20.2, 2006-08-27
+- Changed library to adjust its system call numbers based
+ on the running kernel's version. Provides compatibility
+ with kernels using perfctr-2.7.19 or perfctr-2.7.20.
+
+Version 2.7.20.1, 2006-08-25
+- Added patch file for a SuSE 2.6.16.21-SLES10 kernel.
+ Contributed by Eric Kjeldergaard @ IBM.
+
+Version 2.7.20, 2006-08-20
+- Updated to support kernels 2.6.16, 2.6.17, and 2.6.18-rc4.
+- Migrated ppc64 from include/asm-ppc64/ to include/asm-powerpc/.
+- Updated perfctr system call numbers on all platforms, due to
+ other system call additions since kernel 2.6.14.
+
+Version 2.7.19, 2005-11-08
+- The self and signal examples have been updated for Power5/PPC970.
+- The ppc64 driver has been updated to compile correctly in
+ recent 2.6 kernels.
+- The x86 kernel driver has been updated to work correctly
+ on dual-core P4 processors. Previous versions would fail
+ during CPU detection (on HT DC P4s) or would erroneously
+ restrict access for one of the cores (non-HT DC P4s).
+- The ppc32 driver will now compile in kernels that lack Open
+ Firmware support, which is needed for some embedded systems.
+
Version 2.7.18, 2005-06-06
- Fixed a 32/64-bit bug in the vperfctr_read_ctrs() library
function, which caused problems on ppc64 and unnecessary
diff --git a/src/perfctr-2.7.x/INSTALL b/src/perfctr-2.7.x/INSTALL
index 6bea3db0d34b066d6ac54c024bebff439c95a32d..51d528451487bf5374d1351a3d16ecbad618139d 100644
--- a/src/perfctr-2.7.x/INSTALL
+++ b/src/perfctr-2.7.x/INSTALL
@@ -1,4 +1,4 @@
-$Id$
+$Id: INSTALL,v 1.20 2005/04/08 10:21:16 mikpe Exp $
INSTALLATION INSTRUCTIONS
=========================
diff --git a/src/perfctr-2.7.x/Makefile b/src/perfctr-2.7.x/Makefile
index d4e53342fb9fba5258dc5f83b1fef880736be995..7224b1218ac655a2d2cf9fa117d8afaa956949cc 100644
--- a/src/perfctr-2.7.x/Makefile
+++ b/src/perfctr-2.7.x/Makefile
@@ -1,5 +1,6 @@
SHELL=/bin/sh
ARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/)
+ASM_ARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/ -e s/ppc.*/powerpc/)
SUBDIRS=usr.lib examples
default: linux/include/asm/perfctr.h
@@ -12,7 +13,7 @@ all-subdirs:
linux/include/asm/perfctr.h config configure:
rm -f linux/include/asm
- ln -s asm-${ARCH} linux/include/asm
+ ln -s asm-${ASM_ARCH} linux/include/asm
install: default
etc/install.sh "$(PREFIX)" "$(BINDIR)" "$(LIBDIR)" "$(INCLDIR)" "$(ARCH)"
diff --git a/src/perfctr-2.7.x/README b/src/perfctr-2.7.x/README
index a9cab89704b183c9a9aed30801caee6d25a047db..c1d8571b4c52b0df41ae0811f3e1460fea6117e0 100644
--- a/src/perfctr-2.7.x/README
+++ b/src/perfctr-2.7.x/README
@@ -1,7 +1,7 @@
-$Id$
+$Id: README,v 1.48 2007/10/06 13:02:07 mikpe Exp $
Linux Performance-Monitoring Counters Driver
- Mikael Pettersson <mikpe@csd.uu.se>
+ Mikael Pettersson <mikpe@it.uu.se>
========================================================================
@@ -100,7 +100,7 @@ Limitations
Availability
------------
This and future versions of this package can be downloaded from
-<http://www.csd.uu.se/~mikpe/linux/perfctr/>.
+<http://user.it.uu.se/~mikpe/linux/perfctr/>.
The perfctr-devel mailing list is an open forum for driver update
announcements and general discussions about the perfctr driver
@@ -110,7 +110,7 @@ and its usage. To subscribe to perfctr-devel, visit
Licensing
---------
-Copyright (C) 1999-2004 Mikael Pettersson <mikpe@csd.uu.se>
+Copyright (C) 1999-2007 Mikael Pettersson <mikpe@it.uu.se>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
diff --git a/src/perfctr-2.7.x/etc/install.sh b/src/perfctr-2.7.x/etc/install.sh
index a7551dd2f2089d24e557368609914e6b6d38419c..6e3bb72d94dc4f7c7944bfa8105fef26ad6c25b3 100755
--- a/src/perfctr-2.7.x/etc/install.sh
+++ b/src/perfctr-2.7.x/etc/install.sh
@@ -1,5 +1,5 @@
#!/bin/sh
-# $Id$
+# $Id: install.sh,v 1.2 2005/01/16 22:44:34 mikpe Exp $
# usage: etc/install.sh PREFIX BINDIR LIBDIR INCLDIR ARCH
# If unset, {BIN,LIB,INCL}DIR are given default values from PREFIX.
# Then make install2 is invoked with the final {BIN,LIB,INCL}DIR.
diff --git a/src/perfctr-2.7.x/etc/p4.c b/src/perfctr-2.7.x/etc/p4.c
index 1494096ab5cb04515b214b100c6484a7bce0a88b..6b3f8ed211eb351eec441b5a39ce06e8b0951357 100644
--- a/src/perfctr-2.7.x/etc/p4.c
+++ b/src/perfctr-2.7.x/etc/p4.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: p4.c,v 1.7 2004/02/20 21:33:25 mikpe Exp $
*
* pipe stdout through 'sort -u' to see:
* - which ESCRs are usable, and the events they support
diff --git a/src/perfctr-2.7.x/examples/global/Makefile b/src/perfctr-2.7.x/examples/global/Makefile
index 9f6384240bd3e1c40a1f37a1023886bb11a51811..df8d8a273048e0ee2ca67e13fa66f009b4a9327e 100644
--- a/src/perfctr-2.7.x/examples/global/Makefile
+++ b/src/perfctr-2.7.x/examples/global/Makefile
@@ -1,4 +1,4 @@
-# $Id$
+# $Id: Makefile,v 1.9 2005/03/23 02:02:54 mikpe Exp $
SHELL=/bin/sh
ARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/)
diff --git a/src/perfctr-2.7.x/examples/global/arch.h b/src/perfctr-2.7.x/examples/global/arch.h
index 7935e9d81856484079df5d1670146a4e03c7a049..345748c163ee030907b310f21b86b48cd462ddc6 100644
--- a/src/perfctr-2.7.x/examples/global/arch.h
+++ b/src/perfctr-2.7.x/examples/global/arch.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: arch.h,v 1.1 2004/01/11 22:07:12 mikpe Exp $
* Architecture-specific support code.
*
* Copyright (C) 2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/examples/global/global.c b/src/perfctr-2.7.x/examples/global/global.c
index 286b2eda1af38eadf4abde73cdf7f70be6dc591f..782746502548f006bc1e7d9fe7dc0118d176f785 100644
--- a/src/perfctr-2.7.x/examples/global/global.c
+++ b/src/perfctr-2.7.x/examples/global/global.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: global.c,v 1.37 2004/01/12 14:25:40 mikpe Exp $
*
* usage: ./global [sampling_interval_usec [sleep_interval_sec]]
*
diff --git a/src/perfctr-2.7.x/examples/global/ppc.c b/src/perfctr-2.7.x/examples/global/ppc.c
index d1a94ba2a1d49040a59593be24abbe95495a35eb..4398d558a04c3edf317f2bb6a29d2db388450b13 100644
--- a/src/perfctr-2.7.x/examples/global/ppc.c
+++ b/src/perfctr-2.7.x/examples/global/ppc.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: ppc.c,v 1.2 2004/06/21 22:24:30 mikpe Exp $
* PPC32-specific code.
*
* Copyright (C) 2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/examples/global/x86.c b/src/perfctr-2.7.x/examples/global/x86.c
index 9ef952d9f92043c551fc0c4914ed569462a105cc..b90d3e7d5a7476d0ba60b1c7f798ba5b27e124f3 100644
--- a/src/perfctr-2.7.x/examples/global/x86.c
+++ b/src/perfctr-2.7.x/examples/global/x86.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: x86.c,v 1.3 2004/08/02 14:36:10 mikpe Exp $
* x86-specific code.
*
* Copyright (C) 2000-2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/examples/perfex/Makefile b/src/perfctr-2.7.x/examples/perfex/Makefile
index 4910a19de08017a7866e0921f442629e9eb24e16..b07d9ac0c1b4c239b91cd7488076aff54ab2ba92 100644
--- a/src/perfctr-2.7.x/examples/perfex/Makefile
+++ b/src/perfctr-2.7.x/examples/perfex/Makefile
@@ -1,4 +1,4 @@
-# $Id$
+# $Id: Makefile,v 1.8 2005/04/09 10:51:17 mikpe Exp $
SHELL=/bin/sh
ARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/)
diff --git a/src/perfctr-2.7.x/examples/perfex/arch.h b/src/perfctr-2.7.x/examples/perfex/arch.h
index 0c3f8eabac5929aee95e36a8dcd6d41c1618ab8c..97a36ba12aee9baae1c04bb4de7627c461360c5d 100644
--- a/src/perfctr-2.7.x/examples/perfex/arch.h
+++ b/src/perfctr-2.7.x/examples/perfex/arch.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: arch.h,v 1.5 2005/03/23 02:02:54 mikpe Exp $
* Architecture-specific support code.
*
* Copyright (C) 2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/examples/perfex/perfex.c b/src/perfctr-2.7.x/examples/perfex/perfex.c
index 9886b9fa34a21ead2c1ea60dd7baa9b86561d5c5..6f3cb05147d889a0daa9d8fb46c935f57e09a884 100644
--- a/src/perfctr-2.7.x/examples/perfex/perfex.c
+++ b/src/perfctr-2.7.x/examples/perfex/perfex.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: perfex.c,v 1.35 2005/01/16 22:51:20 mikpe Exp $
*
* NAME
* perfex - a command-line interface to processor performance counters
diff --git a/src/perfctr-2.7.x/examples/perfex/ppc.c b/src/perfctr-2.7.x/examples/perfex/ppc.c
index d086d785c8873c325efa4ce4ebc5e3c2543900fa..eedf61d3ebf71a43b79d4018106e89177ddace8a 100644
--- a/src/perfctr-2.7.x/examples/perfex/ppc.c
+++ b/src/perfctr-2.7.x/examples/perfex/ppc.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: ppc.c,v 1.5 2005/03/14 01:48:42 mikpe Exp $
* PPC32-specific code.
*
* Copyright (C) 2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/examples/perfex/ppc.h b/src/perfctr-2.7.x/examples/perfex/ppc.h
index 1b492bd951d92e83b89d35b3c6e0c83cf7cb30d4..064e688619607553d98a0c09ff9c99f23880bef4 100644
--- a/src/perfctr-2.7.x/examples/perfex/ppc.h
+++ b/src/perfctr-2.7.x/examples/perfex/ppc.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: ppc.h,v 1.1 2004/01/12 01:56:15 mikpe Exp $
* PPC32-specific declarations.
*
* Copyright (C) 2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/examples/perfex/ppc64.c b/src/perfctr-2.7.x/examples/perfex/ppc64.c
index 46043ae3022621c9e471d38936248f1a21bb33e0..1a5ef8097464afbcde299cd9e978ffe5431774aa 100644
--- a/src/perfctr-2.7.x/examples/perfex/ppc64.c
+++ b/src/perfctr-2.7.x/examples/perfex/ppc64.c
@@ -83,11 +83,20 @@ static int parse_value(const char *arg, unsigned long *value)
return endp[0] != '\0';
}
+static int parse_value_ull(const char *arg, unsigned long long *value)
+{
+ char *endp;
+
+ *value = strtoull(arg, &endp, 16);
+ return endp[0] != '\0';
+}
+
int do_arch_option(int ch,
const char *arg,
struct perfctr_cpu_control *cpu_control)
{
unsigned long spec_value;
+ unsigned long long spec_value_ull;
switch( ch ) {
case 1:
@@ -98,11 +107,11 @@ int do_arch_option(int ch,
cpu_control->ppc64.mmcr0 = spec_value;
return 0;
case 2:
- if( parse_value(arg, &spec_value) ) {
+ if( parse_value_ull(arg, &spec_value_ull) ) {
fprintf(stderr, "perfex: invalid value: '%s'\n", arg);
exit(1);
}
- cpu_control->ppc64.mmcr1 = spec_value;
+ cpu_control->ppc64.mmcr1 = spec_value_ull;
return 0;
case 3:
if( parse_value(arg, &spec_value) ) {
diff --git a/src/perfctr-2.7.x/examples/perfex/x86.c b/src/perfctr-2.7.x/examples/perfex/x86.c
index 6472e59b6ea10bfb1a6d9d0d0ec699135a607b5d..a28b49cd60d4aba79bc2c676bea3ce658020f33a 100644
--- a/src/perfctr-2.7.x/examples/perfex/x86.c
+++ b/src/perfctr-2.7.x/examples/perfex/x86.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: x86.c,v 1.6 2005/03/14 01:48:42 mikpe Exp $
* x86-specific code.
*
* Copyright (C) 1999-2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/examples/perfex/x86.h b/src/perfctr-2.7.x/examples/perfex/x86.h
index 9dda42308f07a2c481d5d1dd0d954e44d60cc4ff..428d842e394c6132af0af516f386e046ae186049 100644
--- a/src/perfctr-2.7.x/examples/perfex/x86.h
+++ b/src/perfctr-2.7.x/examples/perfex/x86.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: x86.h,v 1.1 2004/01/11 22:07:12 mikpe Exp $
* x86-specific declarations.
*
* Copyright (C) 1999-2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/examples/self/Makefile b/src/perfctr-2.7.x/examples/self/Makefile
index 487b63d8c3d5053ec45647d95986d6aa17857074..1473904d191d9d5aca0467992dc6969d10d89f71 100644
--- a/src/perfctr-2.7.x/examples/self/Makefile
+++ b/src/perfctr-2.7.x/examples/self/Makefile
@@ -1,4 +1,4 @@
-# $Id$
+# $Id: Makefile,v 1.8 2005/04/09 10:51:17 mikpe Exp $
SHELL=/bin/sh
ARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/)
diff --git a/src/perfctr-2.7.x/examples/self/arch.h b/src/perfctr-2.7.x/examples/self/arch.h
index a1e663a0e09e590bce01793a7b15dbcb62b26558..9bf92805b32c09b4bd13cf859413930fca9be3d2 100644
--- a/src/perfctr-2.7.x/examples/self/arch.h
+++ b/src/perfctr-2.7.x/examples/self/arch.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: arch.h,v 1.1 2004/01/11 22:07:12 mikpe Exp $
* Architecture-specific support code.
*
* Copyright (C) 2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/examples/self/ppc.c b/src/perfctr-2.7.x/examples/self/ppc.c
index 0bffa9d236de90bd96e5c98335e5cbf556b1acd8..ff943766a39b976682a2165ee57ca43a2027157d 100644
--- a/src/perfctr-2.7.x/examples/self/ppc.c
+++ b/src/perfctr-2.7.x/examples/self/ppc.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: ppc.c,v 1.4 2005/03/14 01:48:42 mikpe Exp $
* PPC32-specific code.
*
* Copyright (C) 2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/examples/self/self.c b/src/perfctr-2.7.x/examples/self/self.c
index 678a5bcf3d2a65f7267f5694695c73f25d9c704a..ef913c61b670bd1f0bb17e043ca0da1fd65c1d9a 100644
--- a/src/perfctr-2.7.x/examples/self/self.c
+++ b/src/perfctr-2.7.x/examples/self/self.c
@@ -1,7 +1,7 @@
-/* $Id$
+/* $Id: self.c,v 1.33 2005/11/07 01:48:13 mikpe Exp $
*
* This test program illustrates how a process may use the
- * Linux x86 Performance-Monitoring Counters interface to
+ * Linux Performance-Monitoring Counters interface to
* monitor its own execution.
*
* The library uses mmap() to map the kernel's accumulated counter
diff --git a/src/perfctr-2.7.x/examples/self/x86.c b/src/perfctr-2.7.x/examples/self/x86.c
index 5e9e67eb32a860e2881b5ba32abcbeae3a2b15f3..4d48c45367d3fba56ee9047d3a35a945254351e3 100644
--- a/src/perfctr-2.7.x/examples/self/x86.c
+++ b/src/perfctr-2.7.x/examples/self/x86.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: x86.c,v 1.5 2005/03/14 01:48:42 mikpe Exp $
* x86-specific code.
*
* Copyright (C) 1999-2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/examples/signal/Makefile b/src/perfctr-2.7.x/examples/signal/Makefile
index 6755a881ebd37fe65e87570b885bbe0d76312d3c..0ca1afd6812adace9da85bbaab8339f7b716ca72 100644
--- a/src/perfctr-2.7.x/examples/signal/Makefile
+++ b/src/perfctr-2.7.x/examples/signal/Makefile
@@ -1,4 +1,4 @@
-# $Id$
+# $Id: Makefile,v 1.7 2005/04/09 10:51:17 mikpe Exp $
SHELL=/bin/sh
ARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/)
diff --git a/src/perfctr-2.7.x/examples/signal/arch.h b/src/perfctr-2.7.x/examples/signal/arch.h
index 507842629bb11cc9eadae8e6fcd2638b56328124..e222beb7e5cfb23f86a86b0e1ec1f8e416fa2ca1 100644
--- a/src/perfctr-2.7.x/examples/signal/arch.h
+++ b/src/perfctr-2.7.x/examples/signal/arch.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: arch.h,v 1.2 2005/01/16 22:55:11 mikpe Exp $
* Architecture-specific support code.
*
* Copyright (C) 2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/examples/signal/ppc.c b/src/perfctr-2.7.x/examples/signal/ppc.c
index 4c463833f8091f4c749f6d84799a1bf62b331239..3d164a380da0ea636ad7c2d11b5a1ab2c2d7e1da 100644
--- a/src/perfctr-2.7.x/examples/signal/ppc.c
+++ b/src/perfctr-2.7.x/examples/signal/ppc.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: ppc.c,v 1.4 2005/03/14 01:48:42 mikpe Exp $
* PPC32-specific code.
*
* Copyright (C) 2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/examples/signal/signal.c b/src/perfctr-2.7.x/examples/signal/signal.c
index 0545c952ab289c9ecf19bee6d3550b594eb70ed8..b26ce1177d11d375a148f5ce3bbe3be06fb32987 100644
--- a/src/perfctr-2.7.x/examples/signal/signal.c
+++ b/src/perfctr-2.7.x/examples/signal/signal.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: signal.c,v 1.20 2005/04/08 14:37:55 mikpe Exp $
*
* This test program illustrates how performance counter overflow
* can be caught and sent to the process as a user-specified signal.
diff --git a/src/perfctr-2.7.x/examples/signal/x86.c b/src/perfctr-2.7.x/examples/signal/x86.c
index 7cc09ed4a059ac4a55c89460afdb5a92f48e1b53..ca801ed0db11ab0c61f6be87ecd28f4614f78242 100644
--- a/src/perfctr-2.7.x/examples/signal/x86.c
+++ b/src/perfctr-2.7.x/examples/signal/x86.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: x86.c,v 1.7 2005/03/14 01:48:42 mikpe Exp $
* x86-specific code.
*
* Copyright (C) 2001-2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/linux/Documentation/perfctr/low-level-api.txt b/src/perfctr-2.7.x/linux/Documentation/perfctr/low-level-api.txt
index b470b2cf3a477e773f0e276458549d6b2a0e13ce..251e610ccf899c342d5f6a596df93eec0912b130 100644
--- a/src/perfctr-2.7.x/linux/Documentation/perfctr/low-level-api.txt
+++ b/src/perfctr-2.7.x/linux/Documentation/perfctr/low-level-api.txt
@@ -1,4 +1,4 @@
-$Id$
+$Id: low-level-api.txt,v 1.1 2004/07/02 18:57:05 mikpe Exp $
PERFCTR LOW-LEVEL DRIVERS API
=============================
diff --git a/src/perfctr-2.7.x/linux/Documentation/perfctr/low-level-ppc32.txt b/src/perfctr-2.7.x/linux/Documentation/perfctr/low-level-ppc32.txt
index 39213a7a15f0b30a890d01a84bff5d8ba719ba88..1f777a33b9f2552cf7094e18c33d28b0c641d8a9 100644
--- a/src/perfctr-2.7.x/linux/Documentation/perfctr/low-level-ppc32.txt
+++ b/src/perfctr-2.7.x/linux/Documentation/perfctr/low-level-ppc32.txt
@@ -1,4 +1,4 @@
-$Id$
+$Id: low-level-ppc32.txt,v 1.1 2004/07/02 18:57:05 mikpe Exp $
PERFCTRS PPC32 LOW-LEVEL API
============================
diff --git a/src/perfctr-2.7.x/linux/Documentation/perfctr/low-level-x86.txt b/src/perfctr-2.7.x/linux/Documentation/perfctr/low-level-x86.txt
index 61514323d235dc79bcbde08772c728bbd3e733ac..bae45ab196e31d22bb20dbd5c322841733de763c 100644
--- a/src/perfctr-2.7.x/linux/Documentation/perfctr/low-level-x86.txt
+++ b/src/perfctr-2.7.x/linux/Documentation/perfctr/low-level-x86.txt
@@ -1,4 +1,4 @@
-$Id$
+$Id: low-level-x86.txt,v 1.2 2004/07/11 17:12:28 mikpe Exp $
PERFCTRS X86 LOW-LEVEL API
==========================
diff --git a/src/perfctr-2.7.x/linux/Documentation/perfctr/overview.txt b/src/perfctr-2.7.x/linux/Documentation/perfctr/overview.txt
index 2af23168a82b98c68d963e64a1eeaa0d27512343..12d0d8fbc0a25c99f1116f5304fc9dcaecafd77d 100644
--- a/src/perfctr-2.7.x/linux/Documentation/perfctr/overview.txt
+++ b/src/perfctr-2.7.x/linux/Documentation/perfctr/overview.txt
@@ -1,4 +1,4 @@
-$Id$
+$Id: overview.txt,v 1.2 2004/07/17 00:30:49 mikpe Exp $
AN OVERVIEW OF PERFCTR
======================
diff --git a/src/perfctr-2.7.x/linux/Documentation/perfctr/virtual.txt b/src/perfctr-2.7.x/linux/Documentation/perfctr/virtual.txt
index b67c932cb82f1613eda41b1be27f54344daf7a9c..2b03e2d1b0d81c418e3fc0c34b7c6d63240fa625 100644
--- a/src/perfctr-2.7.x/linux/Documentation/perfctr/virtual.txt
+++ b/src/perfctr-2.7.x/linux/Documentation/perfctr/virtual.txt
@@ -1,4 +1,4 @@
-$Id$
+$Id: virtual.txt,v 1.3 2004/08/09 09:42:22 mikpe Exp $
VIRTUAL PER-PROCESS PERFORMANCE COUNTERS
========================================
diff --git a/src/perfctr-2.7.x/linux/drivers/perfctr/Kconfig b/src/perfctr-2.7.x/linux/drivers/perfctr/Kconfig
index 0c2c756265737860266ff01c7e7248d7f11baa18..d5c2fabe8a1418796087f50694fd0bc57f6b214e 100644
--- a/src/perfctr-2.7.x/linux/drivers/perfctr/Kconfig
+++ b/src/perfctr-2.7.x/linux/drivers/perfctr/Kconfig
@@ -1,4 +1,4 @@
-# $Id$
+# $Id: Kconfig,v 1.15 2004/10/10 12:05:42 mikpe Exp $
# Performance-monitoring counters driver configuration
#
diff --git a/src/perfctr-2.7.x/linux/drivers/perfctr/Makefile b/src/perfctr-2.7.x/linux/drivers/perfctr/Makefile
index de7410bcff160a21722afb55de387c2234018dea..9f0fa78b79876788d795f628e9f2e4832c93aa0c 100644
--- a/src/perfctr-2.7.x/linux/drivers/perfctr/Makefile
+++ b/src/perfctr-2.7.x/linux/drivers/perfctr/Makefile
@@ -1,6 +1,13 @@
-# $Id$
+# $Id: Makefile,v 1.28 2007/10/06 13:02:07 mikpe Exp $
# Makefile for the Performance-monitoring counters driver.
+my_check_gcc = $(shell if $(CC) $(CFLAGS) $(1) -S -o /dev/null -xc /dev/null > /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi ;)
+EXTRA_CFLAGS_$(CONFIG_X86) := $(call my_check_gcc,-fno-unit-at-a-time,)
+EXTRA_CFLAGS_$(CONFIG_X86_64) :=
+EXTRA_CFLAGS_$(CONFIG_PPC32) :=
+EXTRA_CFLAGS_$(CONFIG_PPC64) :=
+EXTRA_CFLAGS := $(EXTRA_CFLAGS_y)
+
# This also covers x86_64.
perfctr-objs-$(CONFIG_X86) := x86.o
tests-objs-$(CONFIG_X86) := x86_tests.o
diff --git a/src/perfctr-2.7.x/linux/drivers/perfctr/RELEASE-NOTES b/src/perfctr-2.7.x/linux/drivers/perfctr/RELEASE-NOTES
index 308fa36547f8458de47147ac5798b4ea9c9bb225..77436cdfb26cb15ca4e532de9c834f7c2a7199b9 100644
--- a/src/perfctr-2.7.x/linux/drivers/perfctr/RELEASE-NOTES
+++ b/src/perfctr-2.7.x/linux/drivers/perfctr/RELEASE-NOTES
@@ -1,8 +1,44 @@
-$Id$
+$Id: RELEASE-NOTES,v 1.341 2007/10/06 13:02:07 mikpe Exp $
RELEASE NOTES
=============
+Version 2.7.21.1, 2007-10-06
+- Bumped copyright dates.
+
+Version 2.7.21, 2007-10-03
+- Updated many files for <linux/config.h> deprecation change
+ in kernel 2.6.19.
+- Updated log messages containing my email address to use
+ my current @it.uu.se address, as @csd.uu.se == /dev/null.
+- Updated virtual.c for workqueue changes in kernel 2.6.20.
+- Updated virtual.c for i_blksize change in kernel 2.6.19.
+- Updated x86.c to match perfctr-2.6.28, including updates
+ for Intel Core and Core2, a P4 HT detection bug fix, and
+ updates for nmi watchdog changes in kernels 2.6.19, 2.6.21,
+ and 2.6.22.
+- Updated Makefile to unbreak call-site backpatching in x86.c.
+
+Version 2.7.20, 2006-08-20
+- Moved ppc64 perfctr.h from asm-ppc64/ to asm-powerpc/.
+- Updated ppc.c to use {reserve,release}_pmc_hardware()
+ to dynamically claim and release the PMC resources.
+- Updated ppc.c, virtual.c, and x86.c to use new-style
+ mutexes instead of old-style binary semaphores.
+- Updated virtual.c for get_sb_pseudo() change in kernel 2.6.18.
+- Updated x86.c for <asm/nmi.h> change in kernel 2.6.18.
+- Updated x86_tests.c for sync_core() change in kernel 2.6.16.
+
+Version 2.7.19, 2005-11-08
+- Updated ppc64.c to handle that CPU_FTR_PMC8 has been replaced
+ by cur_cpu_spec->num_pmcs. From David Gibson.
+- The dual-core P4s changed the layout rules for the initial
+ APIC ID, which broke the x86 driver on DC P4s. Updated the
+ HT thread ID detection code to match current IA32 SDM Vol3.
+- x86.c: pm_message_t fix for suspend(), from 2.6.13-mm2.
+- The ppc32 driver will now compile in kernels that lack Open
+ Firmware support, which is needed for some embedded systems.
+
Version 2.7.17, 2005-05-26
- (All archs) Added u32 seqlock to user-visible state, replacing
samplecnt on ppc/ppc64. perfctr_cpu_{suspend,resume,sample}()
diff --git a/src/perfctr-2.7.x/linux/drivers/perfctr/cpumask.h b/src/perfctr-2.7.x/linux/drivers/perfctr/cpumask.h
index d2d2cd2794fc041838181553c83cd03f4bbbbbd9..ec9438e59d518f26e1b07485e7cb8d5846c30ab0 100644
--- a/src/perfctr-2.7.x/linux/drivers/perfctr/cpumask.h
+++ b/src/perfctr-2.7.x/linux/drivers/perfctr/cpumask.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: cpumask.h,v 1.11 2004/07/12 22:44:14 mikpe Exp $
* Performance-monitoring counters driver.
* Partial simulation of cpumask_t on non-cpumask_t kernels.
* Extension to allow inspecting a cpumask_t as array of ulong.
diff --git a/src/perfctr-2.7.x/linux/drivers/perfctr/init.c b/src/perfctr-2.7.x/linux/drivers/perfctr/init.c
index 1fcdfb8c8c3c813ab3923be506cb6ffe360895ae..afc300010b8cca11d933d942acb9ed85d5be60de 100644
--- a/src/perfctr-2.7.x/linux/drivers/perfctr/init.c
+++ b/src/perfctr-2.7.x/linux/drivers/perfctr/init.c
@@ -1,10 +1,13 @@
-/* $Id$
+/* $Id: init.c,v 1.83 2007/10/06 13:02:07 mikpe Exp $
* Performance-monitoring counters driver.
* Top-level initialisation code.
*
- * Copyright (C) 1999-2005 Mikael Pettersson
+ * Copyright (C) 1999-2007 Mikael Pettersson
*/
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
#include <linux/config.h>
+#endif
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/sched.h>
diff --git a/src/perfctr-2.7.x/linux/drivers/perfctr/ppc.c b/src/perfctr-2.7.x/linux/drivers/perfctr/ppc.c
index be0b4aa0e4dfd3499e877d6b8f371f2b44332ac9..d209d80e47f26489158969e22bc5f4f18e36f092 100644
--- a/src/perfctr-2.7.x/linux/drivers/perfctr/ppc.c
+++ b/src/perfctr-2.7.x/linux/drivers/perfctr/ppc.c
@@ -1,9 +1,12 @@
-/* $Id$
+/* $Id: ppc.c,v 1.43 2007/10/06 13:02:07 mikpe Exp $
* PPC32 performance-monitoring counters driver.
*
- * Copyright (C) 2004-2005 Mikael Pettersson
+ * Copyright (C) 2004-2007 Mikael Pettersson
*/
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
#include <linux/config.h>
+#endif
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/fs.h>
@@ -65,15 +68,29 @@ void do_perfctr_interrupt(struct pt_regs *regs)
preempt_enable_no_resched();
}
+static inline int perfctr_reserve_pmc_hardware(void)
+{
+ return reserve_pmc_hardware(do_perfctr_interrupt);
+}
+
void perfctr_cpu_set_ihandler(perfctr_ihandler_t ihandler)
{
perfctr_ihandler = ihandler ? ihandler : perfctr_default_ihandler;
}
#else
+static inline int perfctr_reserve_pmc_hardware(void)
+{
+ return reserve_pmc_hardware(NULL);
+}
#define perfctr_cstatus_has_ictrs(cstatus) 0
#endif
+static inline void perfctr_release_pmc_hardware(void)
+{
+ release_pmc_hardware();
+}
+
#if defined(CONFIG_SMP) && defined(CONFIG_PERFCTR_INTERRUPT_SUPPORT)
static inline void
@@ -888,6 +905,7 @@ static unsigned int __init pll_to_core_khz(enum pll_type pll_type)
/* Extract core and timebase frequencies from Open Firmware. */
+#ifdef CONFIG_PPC_OF
static unsigned int __init of_to_core_khz(void)
{
struct device_node *cpu;
@@ -905,6 +923,9 @@ static unsigned int __init of_to_core_khz(void)
perfctr_info.tsc_to_cpu_mult = core / tb;
return core / 1000;
}
+#else
+static inline unsigned int of_to_core_khz(void) { return 0; }
+#endif
static unsigned int __init detect_cpu_khz(enum pll_type pll_type)
{
@@ -1045,7 +1066,6 @@ int __init perfctr_cpu_init(void)
goto out;
}
- perfctr_cpu_reset();
init_done = 1;
out:
return err;
@@ -1053,7 +1073,6 @@ int __init perfctr_cpu_init(void)
void __exit perfctr_cpu_exit(void)
{
- perfctr_cpu_reset();
}
/****************************************************************
@@ -1062,7 +1081,7 @@ void __exit perfctr_cpu_exit(void)
* *
****************************************************************/
-static DECLARE_MUTEX(mutex);
+static DEFINE_MUTEX(mutex);
static const char *current_service = 0;
const char *perfctr_cpu_reserve(const char *service)
@@ -1071,17 +1090,24 @@ const char *perfctr_cpu_reserve(const char *service)
if (!init_done)
return "unsupported hardware";
- down(&mutex);
+ mutex_lock(&mutex);
ret = current_service;
- if (!ret)
- current_service = service;
- up(&mutex);
+ if (ret)
+ goto out_unlock;
+ ret = "unknown driver (oprofile?)";
+ if (perfctr_reserve_pmc_hardware() < 0)
+ goto out_unlock;
+ current_service = service;
+ perfctr_cpu_reset();
+ ret = NULL;
+ out_unlock:
+ mutex_unlock(&mutex);
return ret;
}
void perfctr_cpu_release(const char *service)
{
- down(&mutex);
+ mutex_lock(&mutex);
if (service != current_service) {
printk(KERN_ERR "%s: attempt by %s to release while reserved by %s\n",
__FUNCTION__, service, current_service);
@@ -1089,6 +1115,7 @@ void perfctr_cpu_release(const char *service)
/* power down the counters */
perfctr_cpu_reset();
current_service = 0;
+ perfctr_release_pmc_hardware();
}
- up(&mutex);
+ mutex_unlock(&mutex);
}
diff --git a/src/perfctr-2.7.x/linux/drivers/perfctr/ppc64.c b/src/perfctr-2.7.x/linux/drivers/perfctr/ppc64.c
index ceee84eb371d9277586c1c5eebd1ff321c36e168..65a361aead0adc28dc6aa346f7042c637c73d3fb 100644
--- a/src/perfctr-2.7.x/linux/drivers/perfctr/ppc64.c
+++ b/src/perfctr-2.7.x/linux/drivers/perfctr/ppc64.c
@@ -3,10 +3,12 @@
*
* based on Mikael Pettersson's 32 bit ppc code
* Copyright (C) 2004 David Gibson, IBM Corporation.
- * Copyright (C) 2004 Mikael Pettersson
+ * Copyright (C) 2004, 2007 Mikael Pettersson
*/
-
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
#include <linux/config.h>
+#endif
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/fs.h>
@@ -178,17 +180,22 @@ static void ppc64_clear_counters(void)
mtspr(SPRN_MMCR1, 0);
mtspr(SPRN_MMCRA, 0);
- mtspr(SPRN_PMC1, 0);
- mtspr(SPRN_PMC2, 0);
- mtspr(SPRN_PMC3, 0);
- mtspr(SPRN_PMC4, 0);
- mtspr(SPRN_PMC5, 0);
- mtspr(SPRN_PMC6, 0);
-
- if (cpu_has_feature(CPU_FTR_PMC8)) {
+ if (cur_cpu_spec->num_pmcs >= 1)
+ mtspr(SPRN_PMC1, 0);
+ if (cur_cpu_spec->num_pmcs >= 2)
+ mtspr(SPRN_PMC2, 0);
+ if (cur_cpu_spec->num_pmcs >= 3)
+ mtspr(SPRN_PMC3, 0);
+ if (cur_cpu_spec->num_pmcs >= 4)
+ mtspr(SPRN_PMC4, 0);
+ if (cur_cpu_spec->num_pmcs >= 5)
+ mtspr(SPRN_PMC5, 0);
+ if (cur_cpu_spec->num_pmcs >= 6)
+ mtspr(SPRN_PMC6, 0);
+ if (cur_cpu_spec->num_pmcs >= 7)
mtspr(SPRN_PMC7, 0);
+ if (cur_cpu_spec->num_pmcs >= 8)
mtspr(SPRN_PMC8, 0);
- }
}
/*
@@ -319,10 +326,7 @@ unsigned int perfctr_cpu_identify_overflow(struct perfctr_cpu_state *state)
{
unsigned int cstatus, nractrs, nrctrs, i;
unsigned int pmc_mask = 0;
- int nr_pmcs = 6;
-
- if (cpu_has_feature(CPU_FTR_PMC8))
- nr_pmcs = 8;
+ int nr_pmcs = cur_cpu_spec->num_pmcs;
cstatus = state->user.cstatus;
nractrs = perfctr_cstatus_nractrs(cstatus);
@@ -393,10 +397,7 @@ static inline int check_ireset(struct perfctr_cpu_state *state) { return 0; }
static int check_control(struct perfctr_cpu_state *state)
{
unsigned int i, nractrs, nrctrs, pmc_mask, pmc;
- unsigned int nr_pmcs = 6;
-
- if (cpu_has_feature(CPU_FTR_PMC8))
- nr_pmcs = 8;
+ unsigned int nr_pmcs = cur_cpu_spec->num_pmcs;
nractrs = state->control.header.nractrs;
nrctrs = nractrs + state->control.header.nrictrs;
diff --git a/src/perfctr-2.7.x/linux/drivers/perfctr/ppc64_tests.c b/src/perfctr-2.7.x/linux/drivers/perfctr/ppc64_tests.c
index 678935af460c85f40db9f8c3d1baa318ab2ee5c3..3ba8f15f1d83dd2b12d229a294c2519c4a472cd6 100644
--- a/src/perfctr-2.7.x/linux/drivers/perfctr/ppc64_tests.c
+++ b/src/perfctr-2.7.x/linux/drivers/perfctr/ppc64_tests.c
@@ -3,9 +3,12 @@
* Optional PPC64-specific init-time tests.
*
* Copyright (C) 2004 David Gibson, IBM Corporation.
- * Copyright (C) 2004 Mikael Pettersson
+ * Copyright (C) 2004, 2007 Mikael Pettersson
*/
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
#include <linux/config.h>
+#endif
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/fs.h>
@@ -122,7 +125,7 @@ static void __init init_tests_message(void)
{
#if 0
printk(KERN_INFO "Please email the following PERFCTR INIT lines "
- "to mikpe@csd.uu.se\n"
+ "to mikpe@it.uu.se\n"
KERN_INFO "To remove this message, rebuild the driver "
"with CONFIG_PERFCTR_INIT_TESTS=n\n");
printk(KERN_INFO "PERFCTR INIT: PVR 0x%08x, CPU clock %u kHz, TB clock %lu kHz\n",
diff --git a/src/perfctr-2.7.x/linux/drivers/perfctr/ppc_tests.c b/src/perfctr-2.7.x/linux/drivers/perfctr/ppc_tests.c
index 8f67d316a010af0cb97b3111da927eb377ba061d..5987fa6cc30c4f3760adfc650db57d0fa9321863 100644
--- a/src/perfctr-2.7.x/linux/drivers/perfctr/ppc_tests.c
+++ b/src/perfctr-2.7.x/linux/drivers/perfctr/ppc_tests.c
@@ -1,10 +1,13 @@
-/* $Id$
+/* $Id: ppc_tests.c,v 1.8 2007/10/06 13:02:07 mikpe Exp $
* Performance-monitoring counters driver.
* Optional PPC32-specific init-time tests.
*
- * Copyright (C) 2004 Mikael Pettersson
+ * Copyright (C) 2004, 2007 Mikael Pettersson
*/
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
#include <linux/config.h>
+#endif
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/fs.h>
@@ -121,7 +124,7 @@ static void __init init_tests_message(void)
{
unsigned int pvr = mfspr(SPRN_PVR);
printk(KERN_INFO "Please email the following PERFCTR INIT lines "
- "to mikpe@csd.uu.se\n"
+ "to mikpe@it.uu.se\n"
KERN_INFO "To remove this message, rebuild the driver "
"with CONFIG_PERFCTR_INIT_TESTS=n\n");
printk(KERN_INFO "PERFCTR INIT: PVR 0x%08x, CPU clock %u kHz, TB clock %u kHz\n",
diff --git a/src/perfctr-2.7.x/linux/drivers/perfctr/ppc_tests.h b/src/perfctr-2.7.x/linux/drivers/perfctr/ppc_tests.h
index 8a28b854a91f7a2c4dcaf2b8c81e07ca3f513c63..66704ab286b0cb68bb012d8ef45a48ca82d86410 100644
--- a/src/perfctr-2.7.x/linux/drivers/perfctr/ppc_tests.h
+++ b/src/perfctr-2.7.x/linux/drivers/perfctr/ppc_tests.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: ppc_tests.h,v 1.2 2004/06/21 22:17:15 mikpe Exp $
* Performance-monitoring counters driver.
* Optional PPC32-specific init-time tests.
*
diff --git a/src/perfctr-2.7.x/linux/drivers/perfctr/version.h b/src/perfctr-2.7.x/linux/drivers/perfctr/version.h
index ef596eae747e240c0a86297e4e1cf76af1a1e343..69dc5bd68da3d3f70ef66f12f02dc6a54035f336 100644
--- a/src/perfctr-2.7.x/linux/drivers/perfctr/version.h
+++ b/src/perfctr-2.7.x/linux/drivers/perfctr/version.h
@@ -1 +1 @@
-#define VERSION "2.7.17"
+#define VERSION "2.7.21.1"
diff --git a/src/perfctr-2.7.x/linux/drivers/perfctr/virtual.c b/src/perfctr-2.7.x/linux/drivers/perfctr/virtual.c
index dab260f33d9e75577c5f63b70e544a6b50e1e6dd..9dd90f98ca0d74627bc6959c4a338192a361dbfb 100644
--- a/src/perfctr-2.7.x/linux/drivers/perfctr/virtual.c
+++ b/src/perfctr-2.7.x/linux/drivers/perfctr/virtual.c
@@ -1,9 +1,12 @@
-/* $Id$
+/* $Id: virtual.c,v 1.117 2007/10/06 13:02:07 mikpe Exp $
* Virtual per-process performance counters.
*
- * Copyright (C) 1999-2005 Mikael Pettersson
+ * Copyright (C) 1999-2007 Mikael Pettersson
*/
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
#include <linux/config.h>
+#endif
#include <linux/init.h>
#include <linux/compiler.h> /* for unlikely() in 2.4.18 and older */
#include <linux/kernel.h>
@@ -88,7 +91,7 @@ static inline void vperfctr_init_bad_cpus_allowed(struct vperfctr *perfctr) { }
****************************************************************/
/* XXX: perhaps relax this to number of _live_ perfctrs */
-static DECLARE_MUTEX(nrctrs_mutex);
+static DEFINE_MUTEX(nrctrs_mutex);
static int nrctrs;
static const char this_service[] = __FILE__;
@@ -97,13 +100,13 @@ static int inc_nrctrs(void)
const char *other;
other = NULL;
- down(&nrctrs_mutex);
+ mutex_lock(&nrctrs_mutex);
if (++nrctrs == 1) {
other = perfctr_cpu_reserve(this_service);
if (other)
nrctrs = 0;
}
- up(&nrctrs_mutex);
+ mutex_unlock(&nrctrs_mutex);
if (other) {
printk(KERN_ERR __FILE__
": cannot operate, perfctr hardware taken by '%s'\n",
@@ -116,10 +119,10 @@ static int inc_nrctrs(void)
static void dec_nrctrs(void)
{
- down(&nrctrs_mutex);
+ mutex_lock(&nrctrs_mutex);
if (--nrctrs == 0)
perfctr_cpu_release(this_service);
- up(&nrctrs_mutex);
+ mutex_unlock(&nrctrs_mutex);
}
/* Allocate a `struct vperfctr'. Claim and reserve
@@ -164,16 +167,28 @@ static void put_vperfctr(struct vperfctr *perfctr)
vperfctr_free(perfctr);
}
-static void scheduled_vperfctr_free(void *perfctr)
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
+static void scheduled_vperfctr_free(struct work_struct *work)
+{
+ struct vperfctr *perfctr = container_of(work, struct vperfctr, work);
+ vperfctr_free(perfctr);
+}
+#else
+static void scheduled_vperfctr_free(void *data)
{
- vperfctr_free((struct vperfctr*)perfctr);
+ vperfctr_free((struct vperfctr*)data);
}
+#endif
static void schedule_put_vperfctr(struct vperfctr *perfctr)
{
if (!atomic_dec_and_test(&perfctr->count))
return;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
+ INIT_WORK(&perfctr->work, scheduled_vperfctr_free);
+#else
INIT_WORK(&perfctr->work, scheduled_vperfctr_free, perfctr);
+#endif
schedule_work(&perfctr->work);
}
@@ -443,9 +458,8 @@ static void do_vperfctr_release(struct vperfctr *child_perfctr, struct task_stru
schedule_put_vperfctr(child_perfctr);
}
-static void scheduled_release(void *data)
+static void do_scheduled_release(struct vperfctr *child_perfctr)
{
- struct vperfctr *child_perfctr = data;
struct task_struct *parent_tsk = child_perfctr->parent_tsk;
task_lock(parent_tsk);
@@ -454,6 +468,19 @@ static void scheduled_release(void *data)
put_task_struct(parent_tsk);
}
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
+static void scheduled_release(struct work_struct *work)
+{
+ struct vperfctr *perfctr = container_of(work, struct vperfctr, work);
+ do_scheduled_release(perfctr);
+}
+#else
+static void scheduled_release(void *data)
+{
+ do_scheduled_release((struct vperfctr*)data);
+}
+#endif
+
void __vperfctr_release(struct task_struct *child_tsk)
{
struct task_struct *parent_tsk = child_tsk->parent;
@@ -464,7 +491,11 @@ void __vperfctr_release(struct task_struct *child_tsk)
do_vperfctr_release(child_perfctr, parent_tsk);
else {
get_task_struct(parent_tsk);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
+ INIT_WORK(&child_perfctr->work, scheduled_release);
+#else
INIT_WORK(&child_perfctr->work, scheduled_release, child_perfctr);
+#endif
child_perfctr->parent_tsk = parent_tsk;
schedule_work(&child_perfctr->work);
}
@@ -916,12 +947,22 @@ static struct file_operations vperfctr_file_ops = {
is unfortunately not the same in 2.4 and 2.6. */
#include <linux/mount.h> /* needed for 2.6, included by fs.h in 2.4 */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18)
+static int
+vperfctrfs_get_sb(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data,
+ struct vfsmount *mnt)
+{
+ return get_sb_pseudo(fs_type, "vperfctr:", NULL, VPERFCTRFS_MAGIC, mnt);
+}
+#else
static struct super_block *
vperfctrfs_get_sb(struct file_system_type *fs_type,
int flags, const char *dev_name, void *data)
{
return get_sb_pseudo(fs_type, "vperfctr:", NULL, VPERFCTRFS_MAGIC);
}
+#endif
static struct file_system_type vperfctrfs_type = {
.name = "vperfctrfs",
@@ -966,7 +1007,9 @@ static struct inode *vperfctr_get_inode(void)
inode->i_uid = current->fsuid;
inode->i_gid = current->fsgid;
inode->i_atime = inode->i_mtime = inode->i_ctime = CURRENT_TIME;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) && !DONT_HAVE_i_blksize
inode->i_blksize = 0;
+#endif
return inode;
}
diff --git a/src/perfctr-2.7.x/linux/drivers/perfctr/virtual.h b/src/perfctr-2.7.x/linux/drivers/perfctr/virtual.h
index 7d75f34c98d205420761e45f6bd83d919607757e..5115013eb03a11ebe66ea575ca0ac563252d4a5a 100644
--- a/src/perfctr-2.7.x/linux/drivers/perfctr/virtual.h
+++ b/src/perfctr-2.7.x/linux/drivers/perfctr/virtual.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: virtual.h,v 1.13 2004/05/31 18:18:55 mikpe Exp $
* Virtual per-process performance counters.
*
* Copyright (C) 1999-2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/linux/drivers/perfctr/x86.c b/src/perfctr-2.7.x/linux/drivers/perfctr/x86.c
index 6b13463a811a93d871002d958159f58ad1d538e1..687e95aa52d3892a8f89a414d1c4044a7d20eeb9 100644
--- a/src/perfctr-2.7.x/linux/drivers/perfctr/x86.c
+++ b/src/perfctr-2.7.x/linux/drivers/perfctr/x86.c
@@ -1,13 +1,17 @@
-/* $Id$
+/* $Id: x86.c,v 1.165 2007/10/06 13:02:07 mikpe Exp $
* x86/x86_64 performance-monitoring counters driver.
*
- * Copyright (C) 1999-2005 Mikael Pettersson
+ * Copyright (C) 1999-2007 Mikael Pettersson
*/
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
#include <linux/config.h>
+#endif
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/perfctr.h>
+#include <linux/mutex.h>
#include <asm/msr.h>
#undef MSR_P6_PERFCTR0
@@ -17,6 +21,9 @@
struct hw_interrupt_type;
#include <asm/hw_irq.h>
#include <asm/timex.h> /* cpu_khz */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18) && defined(CONFIG_X86_LOCAL_APIC)
+#include <asm/nmi.h>
+#endif
#include "cpumask.h"
#include "x86_tests.h"
@@ -45,6 +52,18 @@ struct perfctr_low_ctrs {
unsigned int pmc[18];
};
+/* Structures for describing the set of PMU MSRs. */
+struct perfctr_msr_range {
+ unsigned int first_msr;
+ unsigned int nr_msrs;
+};
+
+struct perfctr_pmu_msrs {
+ const struct perfctr_msr_range *perfctrs; /* for {reserve,release}_perfctr_nmi() */
+ const struct perfctr_msr_range *evntsels; /* for {reserve,release}_evntsel_nmi() */
+ const struct perfctr_msr_range *extras;
+};
+
/* Intel P5, Cyrix 6x86MX/MII/III, Centaur WinChip C6/2/3 */
#define MSR_P5_CESR 0x11
#define MSR_P5_CTR0 0x12 /* .. 0x13 */
@@ -69,7 +88,7 @@ struct perfctr_low_ctrs {
/* AMD K8 */
#define IS_K8_NB_EVENT(EVNTSEL) ((((EVNTSEL) >> 5) & 0x7) == 0x7)
-/* Intel P4, Intel Pentium M */
+/* Intel P4, Intel Pentium M, Intel Core */
#define MSR_IA32_MISC_ENABLE 0x1A0
#define MSR_IA32_MISC_ENABLE_PERF_AVAIL (1<<7) /* read-only status bit */
#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12) /* read-only status bit */
@@ -145,7 +164,8 @@ static unsigned int new_id(void)
return id;
}
-#ifdef CONFIG_X86_LOCAL_APIC
+#if defined(CONFIG_X86_LOCAL_APIC)
+
static void perfctr_default_ihandler(unsigned long pc)
{
}
@@ -180,13 +200,13 @@ static inline void perfctr_cpu_unmask_interrupts(struct per_cpu_cache *cache)
cache->interrupts_masked = 0;
}
-#else
+#else /* CONFIG_X86_LOCAL_APIC */
#define perfctr_cstatus_has_ictrs(cstatus) 0
#undef cpu_has_apic
#define cpu_has_apic 0
#undef apic_write
#define apic_write(reg,vector) do{}while(0)
-#endif
+#endif /* CONFIG_X86_LOCAL_APIC */
#if defined(CONFIG_SMP)
@@ -207,11 +227,11 @@ static inline void clear_isuspend_cpu(struct perfctr_cpu_state *state)
state->isuspend_cpu = NR_CPUS;
}
-#else
+#else /* CONFIG_SMP */
static inline void set_isuspend_cpu(struct perfctr_cpu_state *state, int cpu) { }
static inline int is_isuspend_cpu(const struct perfctr_cpu_state *state, int cpu) { return 1; }
static inline void clear_isuspend_cpu(struct perfctr_cpu_state *state) { }
-#endif
+#endif /* CONFIG_SMP */
/****************************************************************
* *
@@ -322,10 +342,14 @@ static void rdpmc_read_counters(const struct perfctr_cpu_state *state,
}
/* shared with MII and C6 */
-static void p5_clear_counters(void)
-{
- clear_msr_range(MSR_P5_CESR, 1+2);
-}
+static const struct perfctr_msr_range p5_extras[] = {
+ { MSR_P5_CESR, 1+2 },
+ { 0, 0 },
+};
+
+static const struct perfctr_pmu_msrs p5_pmu_msrs = {
+ .extras = p5_extras,
+};
/*
* Cyrix 6x86/MII/III.
@@ -384,11 +408,11 @@ static void c6_write_control(const struct perfctr_cpu_state *state)
wrmsr(MSR_P5_CESR, cesr, 0);
}
}
-#endif
+#endif /* !CONFIG_X86_TSC */
/*
- * Intel P6 family (Pentium Pro, Pentium II, and Pentium III cores,
- * and Xeon and Celeron versions of Pentium II and III cores).
+ * Intel P6 family (Pentium Pro, Pentium II, Pentium III, Pentium M, and
+ * Intel Core, including Xeon and Celeron versions of Pentium II and III).
* - One TSC and two 40-bit PMCs.
* - One 32-bit EVNTSEL MSR for each PMC.
* - EVNTSEL0 contains a global enable/disable bit.
@@ -402,6 +426,7 @@ static void c6_write_control(const struct perfctr_cpu_state *state)
*/
static int k8_is_multicore; /* affects northbridge events */
+static int p6_is_core2; /* affects P6_EVNTSEL_ENABLE usage */
/* shared with K7 */
static int p6_like_check_control(struct perfctr_cpu_state *state, int is_k7, int is_global)
@@ -427,7 +452,7 @@ static int p6_like_check_control(struct perfctr_cpu_state *state, int is_k7, int
if (evntsel & P6_EVNTSEL_RESERVED)
return -EPERM;
/* check ENable bit */
- if (is_k7) {
+ if (is_k7 || p6_is_core2) {
/* ENable bit must be set in each evntsel */
if (!(evntsel & P6_EVNTSEL_ENABLE))
return -EINVAL;
@@ -575,11 +600,20 @@ static void p6_write_control(const struct perfctr_cpu_state *state)
p6_like_write_control(state, MSR_P6_EVNTSEL0);
}
-static void p6_clear_counters(void)
-{
- clear_msr_range(MSR_P6_EVNTSEL0, 2);
- clear_msr_range(MSR_P6_PERFCTR0, 2);
-}
+static const struct perfctr_msr_range p6_perfctrs[] = {
+ { MSR_P6_PERFCTR0, 2 },
+ { 0, 0 },
+};
+
+static const struct perfctr_msr_range p6_evntsels[] = {
+ { MSR_P6_EVNTSEL0, 2 },
+ { 0, 0 },
+};
+
+static const struct perfctr_pmu_msrs p6_pmu_msrs = {
+ .perfctrs = p6_perfctrs,
+ .evntsels = p6_evntsels,
+};
/*
* AMD K7 family (Athlon, Duron).
@@ -620,10 +654,20 @@ static void k7_write_control(const struct perfctr_cpu_state *state)
p6_like_write_control(state, MSR_K7_EVNTSEL0);
}
-static void k7_clear_counters(void)
-{
- clear_msr_range(MSR_K7_EVNTSEL0, 4+4);
-}
+static const struct perfctr_msr_range k7_perfctrs[] = {
+ { MSR_K7_PERFCTR0, 4 },
+ { 0, 0 },
+};
+
+static const struct perfctr_msr_range k7_evntsels[] = {
+ { MSR_K7_EVNTSEL0, 4 },
+ { 0, 0 },
+};
+
+static const struct perfctr_pmu_msrs k7_pmu_msrs = {
+ .perfctrs = k7_perfctrs,
+ .evntsels = k7_evntsels,
+};
/*
* VIA C3 family.
@@ -881,23 +925,42 @@ static void p4_write_control(const struct perfctr_cpu_state *state)
cache->id = state->id;
}
-static void p4_clear_counters(void)
-{
+static const struct perfctr_msr_range p4_perfctrs[] = {
+ { MSR_P4_PERFCTR0, 18 },
+ { 0, 0 },
+};
+
+static const struct perfctr_msr_range p4_evntsels[] = {
+ { 0x3BA, 2 }, /* IQ_ESCR{0,1}: only models <= 2 have them */
+ { 0x3A0, 26 },
+ { 0x3BC, 3 },
+ { 0x3C0, 6 },
+ { 0x3C8, 6 },
+ { 0x3E0, 2 },
+ { 0, 0 },
+};
+
+static const struct perfctr_msr_range p4_extras[] = {
/* MSR 0x3F0 seems to have a default value of 0xFC00, but current
docs doesn't fully define it, so leave it alone for now. */
- /* clear PEBS_ENABLE and PEBS_MATRIX_VERT; they handle both PEBS
- and ReplayTagging, and should exist even if PEBS is disabled */
- clear_msr_range(0x3F1, 2);
- clear_msr_range(0x3A0, 26);
- if (p4_IQ_ESCR_ok)
- clear_msr_range(0x3BA, 2);
- clear_msr_range(0x3BC, 3);
- clear_msr_range(0x3C0, 6);
- clear_msr_range(0x3C8, 6);
- clear_msr_range(0x3E0, 2);
- clear_msr_range(MSR_P4_CCCR0, 18);
- clear_msr_range(MSR_P4_PERFCTR0, 18);
-}
+ /* PEBS_ENABLE and PEBS_MATRIX_VERT handle both PEBS and
+ ReplayTagging, and should exist even if PEBS is disabled */
+ { 0x3F1, 2 },
+ { MSR_P4_CCCR0, 18 },
+ { 0, 0 },
+};
+
+static const struct perfctr_pmu_msrs p4_pmu_msrs_models_0to2 = {
+ .perfctrs = p4_perfctrs,
+ .evntsels = p4_evntsels,
+ .extras = p4_extras,
+};
+
+static const struct perfctr_pmu_msrs p4_pmu_msrs_models_3up = {
+ .perfctrs = p4_perfctrs,
+ .evntsels = p4_evntsels+1,
+ .extras = p4_extras,
+};
/*
* Generic driver for any x86 with a working TSC.
@@ -910,10 +973,6 @@ static int generic_check_control(struct perfctr_cpu_state *state, int is_global)
return 0;
}
-static void generic_clear_counters(void)
-{
-}
-
/*
* Driver methods, internal and exported.
*
@@ -1218,10 +1277,38 @@ void perfctr_cpu_sample(struct perfctr_cpu_state *state)
write_perfseq_end(&state->user.sequence);
}
-static void (*clear_counters)(void);
+static void (*clear_counters)(void); /* VIA C3 needs non-standard initialisation */
+static const struct perfctr_pmu_msrs *pmu_msrs;
+
static void perfctr_cpu_clear_counters(void)
{
- return clear_counters();
+ const struct perfctr_pmu_msrs *pmu;
+ const struct perfctr_msr_range *msrs;
+ int i;
+
+ if (clear_counters) {
+ clear_counters();
+ return;
+ }
+
+ pmu = pmu_msrs;
+ if (!pmu)
+ return;
+
+ /* The order below is significant: evntsels must be cleared
+ before the perfctrs. */
+ msrs = pmu->evntsels;
+ if (msrs)
+ for(i = 0; msrs[i].first_msr; ++i)
+ clear_msr_range(msrs[i].first_msr, msrs[i].nr_msrs);
+ msrs = pmu->extras;
+ if (msrs)
+ for(i = 0; msrs[i].first_msr; ++i)
+ clear_msr_range(msrs[i].first_msr, msrs[i].nr_msrs);
+ msrs = pmu->perfctrs;
+ if (msrs)
+ for(i = 0; msrs[i].first_msr; ++i)
+ clear_msr_range(msrs[i].first_msr, msrs[i].nr_msrs);
}
/****************************************************************
@@ -1277,13 +1364,98 @@ static void __init finalise_backpatching(void)
cpumask_t perfctr_cpus_forbidden_mask;
+static inline unsigned int find_mask(unsigned int nrvals)
+{
+ unsigned int tmp = nrvals;
+ unsigned int index_msb = 31;
+
+ if (!tmp)
+ return 0;
+ while (!(tmp & (1<<31))) {
+ tmp <<= 1;
+ --index_msb;
+ }
+ if (nrvals & (nrvals - 1))
+ ++index_msb;
+ return ~(~0 << index_msb);
+}
+
static void __init p4_ht_mask_setup_cpu(void *forbidden)
{
- unsigned int local_apic_physical_id = cpuid_ebx(1) >> 24;
- unsigned int logical_processor_id = local_apic_physical_id & 1;
- if (logical_processor_id != 0)
+ int cpu = smp_processor_id();
+ unsigned int cpuid_maxlev;
+ unsigned int cpuid1_ebx, cpuid1_edx, cpuid4_eax;
+ unsigned int initial_APIC_ID;
+ unsigned int max_cores_per_package;
+ unsigned int max_lp_per_package;
+ unsigned int max_lp_per_core;
+ unsigned int smt_id;
+
+ /*
+ * The following big chunk of code detects the current logical processor's
+ * SMT ID (thread number). This is quite complicated, see AP-485 and Volume 3
+ * of Intel's IA-32 Manual (especially section 7.10) for details.
+ */
+
+ /* Ensure that CPUID reports all levels. */
+ if (cpu_data[cpu].x86_model == 3) { /* >= 3? */
+ unsigned int low, high;
+ rdmsr(MSR_IA32_MISC_ENABLE, low, high);
+ if (low & (1<<22)) { /* LIMIT_CPUID_MAXVAL */
+ low &= ~(1<<22);
+ wrmsr(MSR_IA32_MISC_ENABLE, low, high);
+ printk(KERN_INFO "perfctr/x86.c: CPU %d: removed CPUID level limitation\n",
+ cpu);
+ }
+ }
+
+ /* Find the highest standard CPUID level. */
+ cpuid_maxlev = cpuid_eax(0);
+ if (cpuid_maxlev < 1) {
+ printk(KERN_INFO "perfctr/x86: CPU %d: impossibly low # of CPUID levels: %u\n",
+ cpu, cpuid_maxlev);
+ return;
+ }
+ cpuid1_ebx = cpuid_ebx(1);
+ cpuid1_edx = cpuid_edx(1);
+
+ /* Find the initial (HW-assigned) APIC ID of this logical processor. */
+ initial_APIC_ID = cpuid1_ebx >> 24;
+
+ /* Find the max number of logical processors per physical processor package. */
+ if (cpuid1_edx & (1 << 28)) /* HT is supported */
+ max_lp_per_package = (cpuid1_ebx >> 16) & 0xFF;
+ else /* HT is not supported */
+ max_lp_per_package = 1;
+
+ /* Find the max number of processor cores per physical processor package. */
+ if (cpuid_maxlev >= 4) {
+ /* For CPUID level 4 we need a zero in ecx as input to CPUID, but
+ cpuid_eax() doesn't do that. So we resort to using cpuid_count()
+ with reference parameters and dummy outputs. */
+ unsigned int dummy;
+ cpuid_count(4, 0, &cpuid4_eax, &dummy, &dummy, &dummy);
+ max_cores_per_package = (cpuid4_eax >> 26) + 1;
+ } else {
+ cpuid4_eax = 0;
+ max_cores_per_package = 1;
+ }
+
+ max_lp_per_core = max_lp_per_package / max_cores_per_package;
+
+ smt_id = initial_APIC_ID & find_mask(max_lp_per_core);
+
+ printk(KERN_INFO "perfctr/x86.c: CPU %d: cpuid_ebx(1) 0x%08x, cpuid_edx(1) 0x%08x, cpuid_eax(4) 0x%08x, cpuid_maxlev %u, max_cores_per_package %u, SMT_ID %u\n",
+ cpu, cpuid1_ebx, cpuid1_edx, cpuid4_eax, cpuid_maxlev, max_cores_per_package, smt_id);
+
+ /*
+ * Now (finally!) check the SMT ID. The CPU numbers for non-zero SMT ID
+ * threads are recorded in the forbidden set, to allow performance counter
+ * hardware resource conflicts between sibling threads to be prevented.
+ */
+ if (smt_id != 0)
/* We rely on cpu_set() being atomic! */
- cpu_set(smp_processor_id(), *(cpumask_t*)forbidden);
+ cpu_set(cpu, *(cpumask_t*)forbidden);
}
static int __init p4_ht_smp_init(void)
@@ -1316,12 +1488,6 @@ static int __init p4_ht_init(void)
if (!cpu_has_ht)
return 0;
nr_siblings = (cpuid_ebx(1) >> 16) & 0xFF;
- if (nr_siblings > 2) {
- printk(KERN_WARNING "perfctr/x86.c: hyper-threaded P4s detected:"
- " unsupported number of siblings: %u -- bailing out\n",
- nr_siblings);
- return -ENODEV;
- }
if (nr_siblings < 2)
return 0;
p4_is_ht = 1; /* needed even in a UP kernel */
@@ -1356,18 +1522,21 @@ static int __init intel_init(void)
perfctr_cpu_name = p5_name;
write_control = p5_write_control;
check_control = p5_check_control;
- clear_counters = p5_clear_counters;
+ pmu_msrs = &p5_pmu_msrs;
get_reg_offset = p5_reg_offset;
return 0;
case 6:
- if (current_cpu_data.x86_model == 9 ||
- current_cpu_data.x86_model == 13) { /* Pentium M */
- /* Pentium M added the MISC_ENABLE MSR from P4. */
+ /* Check MSR_IA32_MISC_ENABLE_PERF_AVAIL on relevant models. */
+ if (current_cpu_data.x86_model == 9 || /* Pentium M */
+ current_cpu_data.x86_model == 13 || /* Pentium M */
+ current_cpu_data.x86_model == 14 || /* Intel Core */
+ current_cpu_data.x86_model == 15) { /* Intel Core 2 */
rdmsr_low(MSR_IA32_MISC_ENABLE, misc_enable);
if (!(misc_enable & MSR_IA32_MISC_ENABLE_PERF_AVAIL))
break;
- /* Erratum Y3 probably does not apply since we
- read only the low 32 bits. */
+ }
+ if (current_cpu_data.x86_model == 15) { /* Intel Core 2 */
+ p6_is_core2 = 1;
} else if (current_cpu_data.x86_model < 3) { /* Pentium Pro */
/* Avoid Pentium Pro Erratum 26. */
if (current_cpu_data.x86_mask < 9)
@@ -1378,7 +1547,7 @@ static int __init intel_init(void)
read_counters = rdpmc_read_counters;
write_control = p6_write_control;
check_control = p6_check_control;
- clear_counters = p6_clear_counters;
+ pmu_msrs = &p6_pmu_msrs;
get_reg_offset = p6_reg_offset;
#ifdef CONFIG_X86_LOCAL_APIC
if (cpu_has_apic) {
@@ -1387,7 +1556,9 @@ static int __init intel_init(void)
cpu_iresume = p6_iresume;
/* P-M apparently inherited P4's LVTPC auto-masking :-( */
if (current_cpu_data.x86_model == 9 ||
- current_cpu_data.x86_model == 13)
+ current_cpu_data.x86_model == 13 ||
+ current_cpu_data.x86_model == 14 ||
+ current_cpu_data.x86_model == 15)
lvtpc_reinit_needed = 1;
}
#endif
@@ -1407,7 +1578,10 @@ static int __init intel_init(void)
read_counters = rdpmc_read_counters;
write_control = p4_write_control;
check_control = p4_check_control;
- clear_counters = p4_clear_counters;
+ if (current_cpu_data.x86_model <= 2)
+ pmu_msrs = &p4_pmu_msrs_models_0to2;
+ else
+ pmu_msrs = &p4_pmu_msrs_models_3up;
get_reg_offset = p4_reg_offset;
#ifdef CONFIG_X86_LOCAL_APIC
if (cpu_has_apic) {
@@ -1461,9 +1635,9 @@ static void __init k8_multicore_init(void)
printk(KERN_INFO "perfctr/x86.c: multi-core K8s detected:"
" restricting access to northbridge events\n");
}
-#else
+#else /* CONFIG_SMP */
#define k8_multicore_init() do{}while(0)
-#endif
+#endif /* CONFIG_SMP */
static int __init amd_init(void)
{
@@ -1485,7 +1659,7 @@ static int __init amd_init(void)
read_counters = rdpmc_read_counters;
write_control = k7_write_control;
check_control = k7_check_control;
- clear_counters = k7_clear_counters;
+ pmu_msrs = &k7_pmu_msrs;
get_reg_offset = k7_reg_offset;
#ifdef CONFIG_X86_LOCAL_APIC
if (cpu_has_apic) {
@@ -1509,7 +1683,7 @@ static int __init cyrix_init(void)
read_counters = rdpmc_read_counters;
write_control = p5_write_control;
check_control = mii_check_control;
- clear_counters = p5_clear_counters;
+ pmu_msrs = &p5_pmu_msrs;
get_reg_offset = p5_reg_offset;
return 0;
}
@@ -1544,10 +1718,10 @@ static int __init centaur_init(void)
read_counters = rdpmc_read_counters;
write_control = c6_write_control;
check_control = c6_check_control;
- clear_counters = p5_clear_counters;
+ pmu_msrs = &p5_pmu_msrs;
get_reg_offset = p5_reg_offset;
return 0;
-#endif
+#endif /* !CONFIG_X86_TSC */
case 6: /* VIA C3 */
if (!cpu_has_tsc)
return -ENODEV;
@@ -1566,6 +1740,7 @@ static int __init centaur_init(void)
write_control = p6_write_control;
check_control = vc3_check_control;
clear_counters = vc3_clear_counters;
+ pmu_msrs = NULL;
get_reg_offset = p6_reg_offset;
return 0;
}
@@ -1583,7 +1758,7 @@ static int __init generic_init(void)
check_control = generic_check_control;
write_control = p6_write_control;
read_counters = rdpmc_read_counters;
- clear_counters = generic_clear_counters;
+ pmu_msrs = NULL;
get_reg_offset = generic_reg_offset;
return 0;
}
@@ -1640,7 +1815,7 @@ static void perfctr_pm_resume(void)
#include <linux/sysdev.h>
-static int perfctr_device_suspend(struct sys_device *dev, u32 state)
+static int perfctr_device_suspend(struct sys_device *dev, pm_message_t state)
{
perfctr_pm_suspend();
return 0;
@@ -1675,17 +1850,173 @@ static void x86_pm_exit(void)
sysdev_class_unregister(&perfctr_sysclass);
}
-#else
+#else /* CONFIG_X86_LOCAL_APIC && CONFIG_PM */
static inline void x86_pm_init(void) { }
static inline void x86_pm_exit(void) { }
#endif /* CONFIG_X86_LOCAL_APIC && CONFIG_PM */
-#if !defined(CONFIG_X86_LOCAL_APIC)
+#ifdef CONFIG_X86_LOCAL_APIC
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19)
+
+static void perfctr_release_perfctr_range(unsigned int first_msr, unsigned int nr_msrs)
+{
+ unsigned int i;
+
+ for(i = 0; i < nr_msrs; ++i)
+ release_perfctr_nmi(first_msr + i);
+}
+
+static int perfctr_reserve_perfctr_range(unsigned int first_msr, unsigned int nr_msrs)
+{
+ unsigned int i;
+
+ for(i = 0; i < nr_msrs; ++i)
+ if (!reserve_perfctr_nmi(first_msr + i)) {
+ printk(KERN_ERR "perfctr/x86.c: failed to reserve perfctr MSR %#x\n",
+ first_msr + i);
+ perfctr_release_perfctr_range(first_msr, i);
+ return -1;
+ }
+ return 0;
+}
+
+static void perfctr_release_evntsel_range(unsigned int first_msr, unsigned int nr_msrs)
+{
+ unsigned int i;
+
+ for(i = 0; i < nr_msrs; ++i)
+ release_evntsel_nmi(first_msr + i);
+}
+
+static int perfctr_reserve_evntsel_range(unsigned int first_msr, unsigned int nr_msrs)
+{
+ unsigned int i;
+
+ for(i = 0; i < nr_msrs; ++i)
+ if (!reserve_evntsel_nmi(first_msr + i)) {
+ printk(KERN_ERR "perfctr/x86.c: failed to reserve evntsel MSR %#x\n",
+ first_msr + i);
+ perfctr_release_evntsel_range(first_msr, i);
+ return -1;
+ }
+ return 0;
+}
+
+static void perfctr_release_counters_cpu(void *ignore)
+{
+ const struct perfctr_pmu_msrs *pmu;
+ const struct perfctr_msr_range *msrs;
+ int i;
+
+ pmu = pmu_msrs;
+ if (!pmu)
+ return;
+ msrs = pmu->perfctrs;
+ if (msrs)
+ for(i = 0; msrs[i].first_msr; ++i)
+ perfctr_release_perfctr_range(msrs[i].first_msr, msrs[i].nr_msrs);
+ msrs = pmu->evntsels;
+ if (msrs)
+ for(i = 0; msrs[i].first_msr; ++i)
+ perfctr_release_evntsel_range(msrs[i].first_msr, msrs[i].nr_msrs);
+}
+
+static void perfctr_release_counters(void)
+{
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
+ perfctr_release_counters_cpu(NULL);
+#else
+ on_each_cpu(perfctr_release_counters_cpu, NULL, 1, 1);
+#endif
+}
+
+static void perfctr_reserve_counters_cpu(void *error)
+{
+ const struct perfctr_pmu_msrs *pmu;
+ const struct perfctr_msr_range *msrs;
+ int i;
+
+ pmu = pmu_msrs;
+ if (!pmu)
+ return;
+ msrs = pmu->perfctrs;
+ if (msrs) {
+ for(i = 0; msrs[i].first_msr; ++i)
+ if (perfctr_reserve_perfctr_range(msrs[i].first_msr, msrs[i].nr_msrs))
+ goto err_perfctrs;
+ }
+ msrs = pmu->evntsels;
+ if (msrs) {
+ for(i = 0; msrs[i].first_msr; ++i)
+ if (perfctr_reserve_evntsel_range(msrs[i].first_msr, msrs[i].nr_msrs))
+ goto err_evntsels;
+ }
+ return;
+
+ err_evntsels:
+ while (--i >= 0)
+ perfctr_release_evntsel_range(msrs[i].first_msr, msrs[i].nr_msrs);
+
+ msrs = pmu->perfctrs;
+ if (!msrs)
+ goto err;
+ for(i = 0; msrs[i].first_msr; ++i)
+ ;
+ err_perfctrs:
+ while (--i >= 0)
+ perfctr_release_perfctr_range(msrs[i].first_msr, msrs[i].nr_msrs);
+ err:
+ atomic_set((atomic_t*)error, -1);
+}
+
+static int perfctr_reserve_counters(void)
+{
+ atomic_t error = ATOMIC_INIT(0);
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
+ perfctr_reserve_counters_cpu(&error);
+#else
+ on_each_cpu(perfctr_reserve_counters_cpu, &error, 1, 1);
+#endif
+ return atomic_read(&error);
+}
+
+static int reserve_lapic_nmi(void)
+{
+ if (nmi_watchdog != NMI_LOCAL_APIC)
+ return 0;
+ if (atomic_read(&nmi_active) <= 0)
+ return 0;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)
+ disable_lapic_nmi_watchdog();
+#else
+ on_each_cpu(stop_apic_nmi_watchdog, NULL, 1, 1);
+#endif
+ return perfctr_reserve_counters();
+}
+
+static void release_lapic_nmi(void)
+{
+ perfctr_release_counters();
+ if (nmi_watchdog != NMI_LOCAL_APIC)
+ return;
+ if (atomic_read(&nmi_active) != 0)
+ return;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)
+ enable_lapic_nmi_watchdog();
+#else
+ on_each_cpu(setup_apic_nmi_watchdog, NULL, 1, 1);
+#endif
+}
+#endif
+
+#else /* CONFIG_X86_LOCAL_APIC */
static inline int reserve_lapic_nmi(void) { return 0; }
static inline void release_lapic_nmi(void) { }
-#endif
+#endif /* CONFIG_X86_LOCAL_APIC */
static void do_init_tests(void)
{
@@ -1751,7 +2082,7 @@ void __exit perfctr_cpu_exit(void)
* *
****************************************************************/
-static DECLARE_MUTEX(mutex);
+static DEFINE_MUTEX(mutex);
static const char *current_service = 0;
const char *perfctr_cpu_reserve(const char *service)
@@ -1760,13 +2091,13 @@ const char *perfctr_cpu_reserve(const char *service)
if (!init_done)
return "unsupported hardware";
- down(&mutex);
+ mutex_lock(&mutex);
ret = current_service;
if (ret)
- goto out_up;
+ goto out_unlock;
ret = "unknown driver (oprofile?)";
if (reserve_lapic_nmi() < 0)
- goto out_up;
+ goto out_unlock;
current_service = service;
if (perfctr_info.cpu_features & PERFCTR_FEATURE_RDPMC)
mmu_cr4_features |= X86_CR4_PCE;
@@ -1774,18 +2105,18 @@ const char *perfctr_cpu_reserve(const char *service)
perfctr_cpu_set_ihandler(NULL);
x86_pm_init();
ret = NULL;
- out_up:
- up(&mutex);
+ out_unlock:
+ mutex_unlock(&mutex);
return ret;
}
void perfctr_cpu_release(const char *service)
{
- down(&mutex);
+ mutex_lock(&mutex);
if (service != current_service) {
printk(KERN_ERR "%s: attempt by %s to release while reserved by %s\n",
__FUNCTION__, service, current_service);
- goto out_up;
+ goto out_unlock;
}
/* power down the counters */
if (perfctr_info.cpu_features & PERFCTR_FEATURE_RDPMC)
@@ -1795,6 +2126,6 @@ void perfctr_cpu_release(const char *service)
x86_pm_exit();
current_service = 0;
release_lapic_nmi();
- out_up:
- up(&mutex);
+ out_unlock:
+ mutex_unlock(&mutex);
}
diff --git a/src/perfctr-2.7.x/linux/drivers/perfctr/x86_tests.c b/src/perfctr-2.7.x/linux/drivers/perfctr/x86_tests.c
index 8152d3dcc7c7faa0419684734d466ad24ea9d0c2..ed3168554520f9f1480c7f74fb0484ca4b7cb794 100644
--- a/src/perfctr-2.7.x/linux/drivers/perfctr/x86_tests.c
+++ b/src/perfctr-2.7.x/linux/drivers/perfctr/x86_tests.c
@@ -1,10 +1,13 @@
-/* $Id$
+/* $Id: x86_tests.c,v 1.36 2007/10/06 13:02:07 mikpe Exp $
* Performance-monitoring counters driver.
* Optional x86/x86_64-specific init-time tests.
*
- * Copyright (C) 1999-2004 Mikael Pettersson
+ * Copyright (C) 1999-2007 Mikael Pettersson
*/
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
#include <linux/config.h>
+#endif
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/fs.h>
@@ -49,15 +52,6 @@
#define apic_write(reg,vector) do{}while(0)
#endif
-#if !defined(__x86_64__)
-/* Avoid speculative execution by the CPU */
-extern inline void sync_core(void)
-{
- int tmp;
- asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
-}
-#endif
-
static void __init do_rdpmc(unsigned pmc, unsigned unused2)
{
unsigned i;
@@ -153,7 +147,7 @@ static unsigned __init run(void (*doit)(unsigned, unsigned),
static void __init init_tests_message(void)
{
printk(KERN_INFO "Please email the following PERFCTR INIT lines "
- "to mikpe@csd.uu.se\n"
+ "to mikpe@it.uu.se\n"
KERN_INFO "To remove this message, rebuild the driver "
"with CONFIG_PERFCTR_INIT_TESTS=n\n");
printk(KERN_INFO "PERFCTR INIT: vendor %u, family %u, model %u, stepping %u, clock %u kHz\n",
@@ -232,11 +226,6 @@ static inline void perfctr_p5_init_tests(void)
measure_overheads(MSR_P5_CESR, P5_CESR_VAL, MSR_P5_CTR0, 0, 0);
}
-static inline void perfctr_p6_init_tests(void)
-{
- measure_overheads(MSR_P6_EVNTSEL0, P6_EVNTSEL0_VAL, MSR_P6_PERFCTR0, 0, 0);
-}
-
#if !defined(CONFIG_X86_TSC)
static inline void perfctr_c6_init_tests(void)
{
@@ -254,6 +243,11 @@ static inline void perfctr_vc3_init_tests(void)
}
#endif /* !__x86_64__ */
+static inline void perfctr_p6_init_tests(void)
+{
+ measure_overheads(MSR_P6_EVNTSEL0, P6_EVNTSEL0_VAL, MSR_P6_PERFCTR0, 0, 0);
+}
+
static inline void perfctr_p4_init_tests(void)
{
measure_overheads(MSR_P4_CRU_ESCR0, P4_CRU_ESCR0_VAL, MSR_P4_IQ_COUNTER0,
@@ -279,9 +273,6 @@ void __init perfctr_x86_init_tests(void)
case PTT_P5: /* Intel P5, P5MMX; Cyrix 6x86MX, MII, III */
perfctr_p5_init_tests();
break;
- case PTT_P6: /* Intel PPro, PII, PIII, PENTM */
- perfctr_p6_init_tests();
- break;
#if !defined(CONFIG_X86_TSC)
case PTT_WINCHIP: /* WinChip C6, 2, 3 */
perfctr_c6_init_tests();
@@ -291,6 +282,9 @@ void __init perfctr_x86_init_tests(void)
perfctr_vc3_init_tests();
break;
#endif /* !__x86_64__ */
+ case PTT_P6: /* Intel PPro, PII, PIII, PENTM, CORE */
+ perfctr_p6_init_tests();
+ break;
case PTT_P4: /* Intel P4 */
perfctr_p4_init_tests();
break;
diff --git a/src/perfctr-2.7.x/linux/drivers/perfctr/x86_tests.h b/src/perfctr-2.7.x/linux/drivers/perfctr/x86_tests.h
index 37eb0e8d581657ff830b92ce1f1928492137a672..aa644de0d963a8efadb75f48a1eba5c5f2467a29 100644
--- a/src/perfctr-2.7.x/linux/drivers/perfctr/x86_tests.h
+++ b/src/perfctr-2.7.x/linux/drivers/perfctr/x86_tests.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: x86_tests.h,v 1.10 2004/05/22 20:48:57 mikpe Exp $
* Performance-monitoring counters driver.
* Optional x86/x86_64-specific init-time tests.
*
diff --git a/src/perfctr-2.7.x/linux/include/asm-i386/perfctr.h b/src/perfctr-2.7.x/linux/include/asm-i386/perfctr.h
index f28c40d81f0d9931805fd506b5437657dd4ba072..0af03845a77dcc47275c1aeded845b9b730bb30d 100644
--- a/src/perfctr-2.7.x/linux/include/asm-i386/perfctr.h
+++ b/src/perfctr-2.7.x/linux/include/asm-i386/perfctr.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: perfctr.h,v 1.64 2005/05/26 00:37:36 mikpe Exp $
* x86/x86_64 Performance-Monitoring Counters driver
*
* Copyright (C) 1999-2005 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/linux/include/asm-ppc/perfctr.h b/src/perfctr-2.7.x/linux/include/asm-ppc/perfctr.h
index 0a914af5772a2d99d95be6122bdb955d3241ea72..af743325557bb5e801ce3f08f5a8888bf901fb76 100644
--- a/src/perfctr-2.7.x/linux/include/asm-ppc/perfctr.h
+++ b/src/perfctr-2.7.x/linux/include/asm-ppc/perfctr.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: perfctr.h,v 1.20 2005/05/26 00:37:36 mikpe Exp $
* PPC32 Performance-Monitoring Counters driver
*
* Copyright (C) 2004-2005 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/linux/include/linux/perfctr.h b/src/perfctr-2.7.x/linux/include/linux/perfctr.h
index c624ed8e41a8a42d7b71cd8df1add0289c5dded6..f8a736ecd833938f6f08fd2fe0d58aeca961366a 100644
--- a/src/perfctr-2.7.x/linux/include/linux/perfctr.h
+++ b/src/perfctr-2.7.x/linux/include/linux/perfctr.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: perfctr.h,v 1.95 2005/10/02 13:01:30 mikpe Exp $
* Performance-Monitoring Counters driver
*
* Copyright (C) 1999-2005 Mikael Pettersson
@@ -168,7 +168,7 @@ static inline void write_perfseq_begin(__u32 *seq)
static inline void write_perfseq_end(__u32 *seq)
{
- ++*seq;
+ ++*seq;
}
#endif /* __KERNEL__ */
diff --git a/src/perfctr-2.7.x/patches/patch-kernel-2.6.16 b/src/perfctr-2.7.x/patches/patch-kernel-2.6.16
new file mode 100644
index 0000000000000000000000000000000000000000..8fbb22c0a261f371f251f20aed8aceef4dc89b42
--- /dev/null
+++ b/src/perfctr-2.7.x/patches/patch-kernel-2.6.16
@@ -0,0 +1,786 @@
+diff -rupN linux-2.6.16/CREDITS linux-2.6.16.perfctr27/CREDITS
+--- linux-2.6.16/CREDITS 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.perfctr27/CREDITS 2006-08-11 03:48:19.000000000 +0200
+@@ -2634,6 +2634,7 @@ N: Mikael Pettersson
+ E: mikpe@csd.uu.se
+ W: http://www.csd.uu.se/~mikpe/
+ D: Miscellaneous fixes
++D: Performance-monitoring counters driver
+
+ N: Reed H. Petty
+ E: rhp@draper.net
+diff -rupN linux-2.6.16/MAINTAINERS linux-2.6.16.perfctr27/MAINTAINERS
+--- linux-2.6.16/MAINTAINERS 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.perfctr27/MAINTAINERS 2006-08-11 03:48:19.000000000 +0200
+@@ -2071,6 +2071,12 @@ M: tsbogend@alpha.franken.de
+ L: netdev@vger.kernel.org
+ S: Maintained
+
++PERFORMANCE-MONITORING COUNTERS DRIVER
++P: Mikael Pettersson
++M: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
++S: Maintained
++
+ PHRAM MTD DRIVER
+ P: J�rn Engel
+ M: joern@wh.fh-wedel.de
+diff -rupN linux-2.6.16/arch/i386/Kconfig linux-2.6.16.perfctr27/arch/i386/Kconfig
+--- linux-2.6.16/arch/i386/Kconfig 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.perfctr27/arch/i386/Kconfig 2006-08-11 03:48:19.000000000 +0200
+@@ -685,6 +685,8 @@ config SECCOMP
+
+ If unsure, say Y. Only embedded should say N here.
+
++source "drivers/perfctr/Kconfig"
++
+ source kernel/Kconfig.hz
+
+ config KEXEC
+diff -rupN linux-2.6.16/arch/i386/kernel/entry.S linux-2.6.16.perfctr27/arch/i386/kernel/entry.S
+--- linux-2.6.16/arch/i386/kernel/entry.S 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.perfctr27/arch/i386/kernel/entry.S 2006-08-11 03:48:19.000000000 +0200
+@@ -432,6 +432,16 @@ ENTRY(name) \
+ /* The include is where all of the SMP etc. interrupts come from */
+ #include "entry_arch.h"
+
++#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PERFCTR)
++ENTRY(perfctr_interrupt)
++ pushl $LOCAL_PERFCTR_VECTOR-256
++ SAVE_ALL
++ pushl %esp
++ call smp_perfctr_interrupt
++ addl $4, %esp
++ jmp ret_from_intr
++#endif
++
+ ENTRY(divide_error)
+ pushl $0 # no error code
+ pushl $do_divide_error
+diff -rupN linux-2.6.16/arch/i386/kernel/i8259.c linux-2.6.16.perfctr27/arch/i386/kernel/i8259.c
+--- linux-2.6.16/arch/i386/kernel/i8259.c 2005-10-28 11:24:06.000000000 +0200
++++ linux-2.6.16.perfctr27/arch/i386/kernel/i8259.c 2006-08-11 03:48:19.000000000 +0200
+@@ -23,6 +23,7 @@
+ #include <asm/apic.h>
+ #include <asm/arch_hooks.h>
+ #include <asm/i8259.h>
++#include <asm/perfctr.h>
+
+ #include <io_ports.h>
+
+@@ -421,6 +422,8 @@ void __init init_IRQ(void)
+ */
+ intr_init_hook();
+
++ perfctr_vector_init();
++
+ /*
+ * Set the clock to HZ Hz, we already have a valid
+ * vector now:
+diff -rupN linux-2.6.16/arch/i386/kernel/process.c linux-2.6.16.perfctr27/arch/i386/kernel/process.c
+--- linux-2.6.16/arch/i386/kernel/process.c 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.perfctr27/arch/i386/kernel/process.c 2006-08-11 03:48:19.000000000 +0200
+@@ -33,6 +33,7 @@
+ #include <linux/delay.h>
+ #include <linux/reboot.h>
+ #include <linux/init.h>
++#include <linux/perfctr.h>
+ #include <linux/mc146818rtc.h>
+ #include <linux/module.h>
+ #include <linux/kallsyms.h>
+@@ -388,6 +389,7 @@ void exit_thread(void)
+ tss->io_bitmap_base = INVALID_IO_BITMAP_OFFSET;
+ put_cpu();
+ }
++ perfctr_exit_thread(&tsk->thread);
+ }
+
+ void flush_thread(void)
+@@ -439,6 +441,8 @@ int copy_thread(int nr, unsigned long cl
+ savesegment(fs,p->thread.fs);
+ savesegment(gs,p->thread.gs);
+
++ perfctr_copy_task(p, regs);
++
+ tsk = current;
+ if (unlikely(NULL != tsk->thread.io_bitmap_ptr)) {
+ p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
+@@ -697,6 +701,8 @@ struct task_struct fastcall * __switch_t
+
+ disable_tsc(prev_p, next_p);
+
++ perfctr_resume_thread(next);
++
+ return prev_p;
+ }
+
+diff -rupN linux-2.6.16/arch/i386/kernel/syscall_table.S linux-2.6.16.perfctr27/arch/i386/kernel/syscall_table.S
+--- linux-2.6.16/arch/i386/kernel/syscall_table.S 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.perfctr27/arch/i386/kernel/syscall_table.S 2006-08-11 03:48:23.000000000 +0200
+@@ -310,3 +310,14 @@ ENTRY(sys_call_table)
+ .long sys_pselect6
+ .long sys_ppoll
+ .long sys_unshare /* 310 */
++ .long sys_ni_syscall
++ .long sys_ni_syscall
++ .long sys_ni_syscall
++ .long sys_ni_syscall
++ .long sys_ni_syscall /* 315 */
++ .long sys_ni_syscall
++ .long sys_ni_syscall
++ .long sys_vperfctr_open
++ .long sys_vperfctr_control
++ .long sys_vperfctr_write /* 320 */
++ .long sys_vperfctr_read
+diff -rupN linux-2.6.16/arch/powerpc/Kconfig linux-2.6.16.perfctr27/arch/powerpc/Kconfig
+--- linux-2.6.16/arch/powerpc/Kconfig 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.perfctr27/arch/powerpc/Kconfig 2006-08-11 03:48:19.000000000 +0200
+@@ -268,6 +268,9 @@ config NOT_COHERENT_CACHE
+ bool
+ depends on 4xx || 8xx || E200
+ default y
++
++source "drivers/perfctr/Kconfig"
++
+ endmenu
+
+ source "init/Kconfig"
+diff -rupN linux-2.6.16/arch/powerpc/kernel/process.c linux-2.6.16.perfctr27/arch/powerpc/kernel/process.c
+--- linux-2.6.16/arch/powerpc/kernel/process.c 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.perfctr27/arch/powerpc/kernel/process.c 2006-08-11 03:48:19.000000000 +0200
+@@ -34,6 +34,7 @@
+ #include <linux/init_task.h>
+ #include <linux/module.h>
+ #include <linux/kallsyms.h>
++#include <linux/perfctr.h>
+ #include <linux/mqueue.h>
+ #include <linux/hardirq.h>
+ #include <linux/utsname.h>
+@@ -330,7 +331,9 @@ struct task_struct *__switch_to(struct t
+ #endif
+
+ local_irq_save(flags);
++ perfctr_suspend_thread(&prev->thread);
+ last = _switch(old_thread, new_thread);
++ perfctr_resume_thread(¤t->thread);
+
+ local_irq_restore(flags);
+
+@@ -459,6 +462,7 @@ void exit_thread(void)
+ {
+ kprobe_flush_task(current);
+ discard_lazy_cpu_state();
++ perfctr_exit_thread(¤t->thread);
+ }
+
+ void flush_thread(void)
+@@ -571,6 +575,8 @@ int copy_thread(int nr, unsigned long cl
+ p->thread.last_syscall = -1;
+ #endif
+
++ perfctr_copy_task(p, regs);
++
+ return 0;
+ }
+
+diff -rupN linux-2.6.16/arch/powerpc/kernel/systbl.S linux-2.6.16.perfctr27/arch/powerpc/kernel/systbl.S
+--- linux-2.6.16/arch/powerpc/kernel/systbl.S 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.perfctr27/arch/powerpc/kernel/systbl.S 2006-08-11 03:48:23.000000000 +0200
+@@ -322,3 +322,25 @@ SYSCALL(spu_create)
+ COMPAT_SYS(pselect6)
+ COMPAT_SYS(ppoll)
+ SYSCALL(unshare)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(vperfctr_open)
++SYSCALL(vperfctr_control)
++SYSCALL(vperfctr_write)
++SYSCALL(vperfctr_read)
+diff -rupN linux-2.6.16/arch/x86_64/Kconfig linux-2.6.16.perfctr27/arch/x86_64/Kconfig
+--- linux-2.6.16/arch/x86_64/Kconfig 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.perfctr27/arch/x86_64/Kconfig 2006-08-11 03:48:19.000000000 +0200
+@@ -462,6 +462,8 @@ config SECCOMP
+
+ If unsure, say Y. Only embedded should say N here.
+
++source "drivers/perfctr/Kconfig"
++
+ source kernel/Kconfig.hz
+
+ endmenu
+diff -rupN linux-2.6.16/arch/x86_64/ia32/ia32entry.S linux-2.6.16.perfctr27/arch/x86_64/ia32/ia32entry.S
+--- linux-2.6.16/arch/x86_64/ia32/ia32entry.S 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.perfctr27/arch/x86_64/ia32/ia32entry.S 2006-08-11 03:48:23.000000000 +0200
+@@ -688,6 +688,17 @@ ia32_sys_call_table:
+ .quad sys_ni_syscall /* pselect6 for now */
+ .quad sys_ni_syscall /* ppoll for now */
+ .quad sys_unshare /* 310 */
++ .quad sys_ni_syscall
++ .quad sys_ni_syscall
++ .quad sys_ni_syscall
++ .quad sys_ni_syscall
++ .quad sys_ni_syscall /* 315 */
++ .quad sys_ni_syscall
++ .quad sys_ni_syscall
++ .quad sys_vperfctr_open
++ .quad sys_vperfctr_control
++ .quad sys_vperfctr_write /* 320 */
++ .quad sys_vperfctr_read
+ ia32_syscall_end:
+ .rept IA32_NR_syscalls-(ia32_syscall_end-ia32_sys_call_table)/8
+ .quad ni_syscall
+diff -rupN linux-2.6.16/arch/x86_64/kernel/entry.S linux-2.6.16.perfctr27/arch/x86_64/kernel/entry.S
+--- linux-2.6.16/arch/x86_64/kernel/entry.S 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.perfctr27/arch/x86_64/kernel/entry.S 2006-08-11 03:48:19.000000000 +0200
+@@ -655,6 +655,11 @@ ENTRY(spurious_interrupt)
+ apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
+ #endif
+
++#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PERFCTR)
++ENTRY(perfctr_interrupt)
++ apicinterrupt LOCAL_PERFCTR_VECTOR,smp_perfctr_interrupt
++#endif
++
+ /*
+ * Exception entry points.
+ */
+diff -rupN linux-2.6.16/arch/x86_64/kernel/i8259.c linux-2.6.16.perfctr27/arch/x86_64/kernel/i8259.c
+--- linux-2.6.16/arch/x86_64/kernel/i8259.c 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.perfctr27/arch/x86_64/kernel/i8259.c 2006-08-11 03:48:19.000000000 +0200
+@@ -23,6 +23,7 @@
+ #include <asm/delay.h>
+ #include <asm/desc.h>
+ #include <asm/apic.h>
++#include <asm/perfctr.h>
+
+ /*
+ * Common place to define all x86 IRQ vectors
+@@ -591,6 +592,8 @@ void __init init_IRQ(void)
+ set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
+ #endif
+
++ perfctr_vector_init();
++
+ /*
+ * Set the clock to HZ Hz, we already have a valid
+ * vector now:
+diff -rupN linux-2.6.16/arch/x86_64/kernel/process.c linux-2.6.16.perfctr27/arch/x86_64/kernel/process.c
+--- linux-2.6.16/arch/x86_64/kernel/process.c 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.perfctr27/arch/x86_64/kernel/process.c 2006-08-11 03:48:19.000000000 +0200
+@@ -33,6 +33,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/delay.h>
+ #include <linux/ptrace.h>
++#include <linux/perfctr.h>
+ #include <linux/utsname.h>
+ #include <linux/random.h>
+ #include <linux/kprobes.h>
+@@ -372,6 +373,7 @@ void exit_thread(void)
+ t->io_bitmap_max = 0;
+ put_cpu();
+ }
++ perfctr_exit_thread(&me->thread);
+ }
+
+ void flush_thread(void)
+@@ -473,6 +475,8 @@ int copy_thread(int nr, unsigned long cl
+ asm("mov %%es,%0" : "=m" (p->thread.es));
+ asm("mov %%ds,%0" : "=m" (p->thread.ds));
+
++ perfctr_copy_task(p, regs);
++
+ if (unlikely(me->thread.io_bitmap_ptr != NULL)) {
+ p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
+ if (!p->thread.io_bitmap_ptr) {
+@@ -627,6 +631,8 @@ __switch_to(struct task_struct *prev_p,
+ }
+ }
+
++ perfctr_resume_thread(next);
++
+ return prev_p;
+ }
+
+diff -rupN linux-2.6.16/drivers/Makefile linux-2.6.16.perfctr27/drivers/Makefile
+--- linux-2.6.16/drivers/Makefile 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.perfctr27/drivers/Makefile 2006-08-11 03:48:19.000000000 +0200
+@@ -70,6 +70,7 @@ obj-$(CONFIG_CPU_FREQ) += cpufreq/
+ obj-$(CONFIG_MMC) += mmc/
+ obj-$(CONFIG_INFINIBAND) += infiniband/
+ obj-$(CONFIG_SGI_SN) += sn/
++obj-$(CONFIG_PERFCTR) += perfctr/
+ obj-y += firmware/
+ obj-$(CONFIG_CRYPTO) += crypto/
+ obj-$(CONFIG_SUPERH) += sh/
+diff -rupN linux-2.6.16/include/asm-i386/mach-default/irq_vectors.h linux-2.6.16.perfctr27/include/asm-i386/mach-default/irq_vectors.h
+--- linux-2.6.16/include/asm-i386/mach-default/irq_vectors.h 2004-05-10 11:14:37.000000000 +0200
++++ linux-2.6.16.perfctr27/include/asm-i386/mach-default/irq_vectors.h 2006-08-11 03:48:19.000000000 +0200
+@@ -56,14 +56,15 @@
+ * sources per level' errata.
+ */
+ #define LOCAL_TIMER_VECTOR 0xef
++#define LOCAL_PERFCTR_VECTOR 0xee
+
+ /*
+- * First APIC vector available to drivers: (vectors 0x30-0xee)
++ * First APIC vector available to drivers: (vectors 0x30-0xed)
+ * we start at 0x31 to spread out vectors evenly between priority
+ * levels. (0x80 is the syscall vector)
+ */
+ #define FIRST_DEVICE_VECTOR 0x31
+-#define FIRST_SYSTEM_VECTOR 0xef
++#define FIRST_SYSTEM_VECTOR 0xee
+
+ #define TIMER_IRQ 0
+
+diff -rupN linux-2.6.16/include/asm-i386/mach-visws/irq_vectors.h linux-2.6.16.perfctr27/include/asm-i386/mach-visws/irq_vectors.h
+--- linux-2.6.16/include/asm-i386/mach-visws/irq_vectors.h 2004-01-09 13:19:11.000000000 +0100
++++ linux-2.6.16.perfctr27/include/asm-i386/mach-visws/irq_vectors.h 2006-08-11 03:48:19.000000000 +0200
+@@ -35,14 +35,15 @@
+ * sources per level' errata.
+ */
+ #define LOCAL_TIMER_VECTOR 0xef
++#define LOCAL_PERFCTR_VECTOR 0xee
+
+ /*
+- * First APIC vector available to drivers: (vectors 0x30-0xee)
++ * First APIC vector available to drivers: (vectors 0x30-0xed)
+ * we start at 0x31 to spread out vectors evenly between priority
+ * levels. (0x80 is the syscall vector)
+ */
+ #define FIRST_DEVICE_VECTOR 0x31
+-#define FIRST_SYSTEM_VECTOR 0xef
++#define FIRST_SYSTEM_VECTOR 0xee
+
+ #define TIMER_IRQ 0
+
+diff -rupN linux-2.6.16/include/asm-i386/processor.h linux-2.6.16.perfctr27/include/asm-i386/processor.h
+--- linux-2.6.16/include/asm-i386/processor.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.perfctr27/include/asm-i386/processor.h 2006-08-11 03:48:19.000000000 +0200
+@@ -464,6 +464,8 @@ struct thread_struct {
+ unsigned long iopl;
+ /* max allowed port in the bitmap, in bytes: */
+ unsigned long io_bitmap_max;
++/* performance counters */
++ struct vperfctr *perfctr;
+ };
+
+ #define INIT_THREAD { \
+diff -rupN linux-2.6.16/include/asm-i386/system.h linux-2.6.16.perfctr27/include/asm-i386/system.h
+--- linux-2.6.16/include/asm-i386/system.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.perfctr27/include/asm-i386/system.h 2006-08-11 03:48:19.000000000 +0200
+@@ -14,6 +14,7 @@ extern struct task_struct * FASTCALL(__s
+
+ #define switch_to(prev,next,last) do { \
+ unsigned long esi,edi; \
++ perfctr_suspend_thread(&(prev)->thread); \
+ asm volatile("pushl %%ebp\n\t" \
+ "movl %%esp,%0\n\t" /* save ESP */ \
+ "movl %5,%%esp\n\t" /* restore ESP */ \
+diff -rupN linux-2.6.16/include/asm-i386/unistd.h linux-2.6.16.perfctr27/include/asm-i386/unistd.h
+--- linux-2.6.16/include/asm-i386/unistd.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.perfctr27/include/asm-i386/unistd.h 2006-08-11 03:48:23.000000000 +0200
+@@ -316,8 +316,12 @@
+ #define __NR_pselect6 308
+ #define __NR_ppoll 309
+ #define __NR_unshare 310
++#define __NR_vperfctr_open 318
++#define __NR_vperfctr_control (__NR_vperfctr_open+1)
++#define __NR_vperfctr_write (__NR_vperfctr_open+2)
++#define __NR_vperfctr_read (__NR_vperfctr_open+3)
+
+-#define NR_syscalls 311
++#define NR_syscalls 322
+
+ /*
+ * user-visible error numbers are in the range -1 - -128: see
+diff -rupN linux-2.6.16/include/asm-powerpc/processor.h linux-2.6.16.perfctr27/include/asm-powerpc/processor.h
+--- linux-2.6.16/include/asm-powerpc/processor.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.perfctr27/include/asm-powerpc/processor.h 2006-08-11 03:48:19.000000000 +0200
+@@ -193,6 +193,9 @@ struct thread_struct {
+ unsigned long spefscr; /* SPE & eFP status */
+ int used_spe; /* set if process has used spe */
+ #endif /* CONFIG_SPE */
++#ifdef CONFIG_PERFCTR_VIRTUAL
++ struct vperfctr *perfctr; /* performance counters */
++#endif
+ };
+
+ #define ARCH_MIN_TASKALIGN 16
+diff -rupN linux-2.6.16/include/asm-powerpc/reg.h linux-2.6.16.perfctr27/include/asm-powerpc/reg.h
+--- linux-2.6.16/include/asm-powerpc/reg.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.perfctr27/include/asm-powerpc/reg.h 2006-08-11 03:48:19.000000000 +0200
+@@ -365,10 +365,8 @@
+ #define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */
+ #define SPRN_PVR 0x11F /* Processor Version Register */
+ #define SPRN_RPA 0x3D6 /* Required Physical Address Register */
+-#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
+ #define SPRN_SDR1 0x019 /* MMU Hash Base Register */
+ #define SPRN_ASR 0x118 /* Address Space Register */
+-#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
+ #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
+ #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
+ #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
+@@ -403,13 +401,6 @@
+ #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
+ #define THRM3_E (1<<0)
+ #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
+-#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
+-#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
+-#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
+-#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
+-#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
+-#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
+-#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
+ #define SPRN_VRSAVE 0x100 /* Vector Register Save Register */
+ #define SPRN_XER 0x001 /* Fixed Point Exception Register */
+
+@@ -455,33 +446,7 @@
+ #define SPRN_SDAR 781
+
+ #else /* 32-bit */
+-#define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */
+-#define MMCR0_FC 0x80000000UL /* freeze counters */
+-#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
+-#define MMCR0_FCP 0x20000000UL /* freeze in problem state */
+-#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
+-#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
+-#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
+-#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
+-#define MMCR0_TBEE 0x00400000UL /* time base exception enable */
+-#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
+ #define MMCR0_PMCnCE 0x00004000UL /* count enable for all but PMC 1*/
+-#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
+-#define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */
+-#define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */
+-
+-#define SPRN_MMCR1 956
+-#define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */
+-#define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */
+-#define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */
+-#define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */
+-#define SPRN_MMCR2 944
+-#define SPRN_PMC1 953 /* Performance Counter Register 1 */
+-#define SPRN_PMC2 954 /* Performance Counter Register 2 */
+-#define SPRN_PMC3 957 /* Performance Counter Register 3 */
+-#define SPRN_PMC4 958 /* Performance Counter Register 4 */
+-#define SPRN_PMC5 945 /* Performance Counter Register 5 */
+-#define SPRN_PMC6 946 /* Performance Counter Register 6 */
+
+ #define SPRN_SIAR 955 /* Sampled Instruction Address Register */
+
+@@ -493,6 +458,77 @@
+ #define MMCR0_PMC2_CYCLES 0x1
+ #define MMCR0_PMC2_ITLB 0x7
+ #define MMCR0_PMC2_LOADMISSTIME 0x5
++
++/* Performance-monitoring control and counter registers */
++#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 (604 and up) */
++#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 (604e and up) */
++#define SPRN_MMCR2 0x3B0 /* Monitor Mode Control Register 2 (7400 and up) */
++#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 (604 and up) */
++#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 (604 and up) */
++#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 (604e and up) */
++#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 (604e and up) */
++#define SPRN_PMC5 0x3B1 /* Performance Counter Register 5 (7450 and up) */
++#define SPRN_PMC6 0x3B2 /* Performance Counter Register 6 (7450 and up) */
++#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register (604 and up) */
++#define SPRN_SDA 0x3BF /* Sampled Data Address Register (604/604e only) */
++#define SPRN_BAMR 0x3B7 /* Breakpoint Address Mask Register (7400 and up) */
++
++#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 (750 and up) */
++#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 (750 and up) */
++#define SPRN_UMMCR2 0x3A0 /* User Monitor Mode Control Register 0 (7400 and up) */
++#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 (750 and up) */
++#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 (750 and up) */
++#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 (750 and up) */
++#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 (750 and up) */
++#define SPRN_UPMC5 0x3A1 /* User Performance Counter Register 5 (7450 and up) */
++#define SPRN_UPMC6 0x3A2 /* User Performance Counter Register 5 (7450 and up) */
++#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register (750 and up) */
++#define SPRN_UBAMR 0x3A7 /* User Breakpoint Address Mask Register (7400 and up) */
++
++/* MMCR0 layout (74xx terminology) */
++#define MMCR0_FC 0x80000000 /* Freeze counters unconditionally. */
++#define MMCR0_FCS 0x40000000 /* Freeze counters while MSR[PR]=0 (supervisor mode). */
++#define MMCR0_FCP 0x20000000 /* Freeze counters while MSR[PR]=1 (user mode). */
++#define MMCR0_FCM1 0x10000000 /* Freeze counters while MSR[PM]=1. */
++#define MMCR0_FCM0 0x08000000 /* Freeze counters while MSR[PM]=0. */
++#define MMCR0_PMXE 0x04000000 /* Enable performance monitor exceptions.
++ * Cleared by hardware when a PM exception occurs.
++ * 604: PMXE is not cleared by hardware.
++ */
++#define MMCR0_FCECE 0x02000000 /* Freeze counters on enabled condition or event.
++ * FCECE is treated as 0 if TRIGGER is 1.
++ * 74xx: FC is set when the event occurs.
++ * 604/750: ineffective when PMXE=0.
++ */
++#define MMCR0_TBSEL 0x01800000 /* Time base lower (TBL) bit selector.
++ * 00: bit 31, 01: bit 23, 10: bit 19, 11: bit 15.
++ */
++#define MMCR0_TBEE 0x00400000 /* Enable event on TBL bit transition from 0 to 1. */
++#define MMCR0_THRESHOLD 0x003F0000 /* Threshold value for certain events. */
++#define MMCR0_PMC1CE 0x00008000 /* Enable event on PMC1 overflow. */
++#define MMCR0_PMCjCE 0x00004000 /* Enable event on PMC2-PMC6 overflow.
++ * 604/750: Overrides FCECE (DISCOUNT).
++ */
++#define MMCR0_TRIGGER 0x00002000 /* Disable PMC2-PMC6 until PMC1 overflow or other event.
++ * 74xx: cleared by hardware when the event occurs.
++ */
++#define MMCR0_PMC1SEL 0x00001FC0 /* PMC1 event selector, 7 bits. */
++#define MMCR0_PMC2SEL 0x0000003F /* PMC2 event selector, 6 bits. */
++
++/* MMCR1 layout (604e-7457) */
++#define MMCR1_PMC3SEL 0xF8000000 /* PMC3 event selector, 5 bits. */
++#define MMCR1_PMC4SEL 0x07C00000 /* PMC4 event selector, 5 bits. */
++#define MMCR1_PMC5SEL 0x003E0000 /* PMC5 event selector, 5 bits. (745x only) */
++#define MMCR1_PMC6SEL 0x0001F800 /* PMC6 event selector, 6 bits. (745x only) */
++#define MMCR1__RESERVED 0x000007FF /* should be zero */
++
++/* MMCR2 layout (7400-7457) */
++#define MMCR2_THRESHMULT 0x80000000 /* MMCR0[THRESHOLD] multiplier. */
++#define MMCR2_SMCNTEN 0x40000000 /* 7400/7410 only, should be zero. */
++#define MMCR2_SMINTEN 0x20000000 /* 7400/7410 only, should be zero. */
++#define MMCR2__RESERVED 0x1FFFFFFF /* should be zero */
++#define MMCR2_RESERVED (MMCR2_SMCNTEN | MMCR2_SMINTEN | MMCR2__RESERVED)
++
+ #endif
+
+ /* Processor Version Register (PVR) field extraction */
+diff -rupN linux-2.6.16/include/asm-powerpc/unistd.h linux-2.6.16.perfctr27/include/asm-powerpc/unistd.h
+--- linux-2.6.16/include/asm-powerpc/unistd.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.perfctr27/include/asm-powerpc/unistd.h 2006-08-11 03:48:23.000000000 +0200
+@@ -301,8 +301,12 @@
+ #define __NR_pselect6 280
+ #define __NR_ppoll 281
+ #define __NR_unshare 282
++#define __NR_vperfctr_open 301
++#define __NR_vperfctr_control (__NR_vperfctr_open+1)
++#define __NR_vperfctr_write (__NR_vperfctr_open+2)
++#define __NR_vperfctr_read (__NR_vperfctr_open+3)
+
+-#define __NR_syscalls 283
++#define __NR_syscalls 305
+
+ #ifdef __KERNEL__
+ #define __NR__exit __NR_exit
+diff -rupN linux-2.6.16/include/asm-x86_64/hw_irq.h linux-2.6.16.perfctr27/include/asm-x86_64/hw_irq.h
+--- linux-2.6.16/include/asm-x86_64/hw_irq.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.perfctr27/include/asm-x86_64/hw_irq.h 2006-08-11 03:48:19.000000000 +0200
+@@ -67,14 +67,15 @@ struct hw_interrupt_type;
+ * sources per level' errata.
+ */
+ #define LOCAL_TIMER_VECTOR 0xef
++#define LOCAL_PERFCTR_VECTOR 0xee
+
+ /*
+- * First APIC vector available to drivers: (vectors 0x30-0xee)
++ * First APIC vector available to drivers: (vectors 0x30-0xed)
+ * we start at 0x31 to spread out vectors evenly between priority
+ * levels. (0x80 is the syscall vector)
+ */
+ #define FIRST_DEVICE_VECTOR 0x31
+-#define FIRST_SYSTEM_VECTOR 0xef /* duplicated in irq.h */
++#define FIRST_SYSTEM_VECTOR 0xee /* duplicated in irq.h */
+
+
+ #ifndef __ASSEMBLY__
+diff -rupN linux-2.6.16/include/asm-x86_64/ia32_unistd.h linux-2.6.16.perfctr27/include/asm-x86_64/ia32_unistd.h
+--- linux-2.6.16/include/asm-x86_64/ia32_unistd.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.perfctr27/include/asm-x86_64/ia32_unistd.h 2006-08-11 03:48:23.000000000 +0200
+@@ -316,7 +316,11 @@
+ #define __NR_ia32_pselect6 308
+ #define __NR_ia32_ppoll 309
+ #define __NR_ia32_unshare 310
++#define __NR_ia32_vperfctr_open 318
++#define __NR_ia32_vperfctr_control (__NR_ia32_vperfctr_open+1)
++#define __NR_ia32_vperfctr_write (__NR_ia32_vperfctr_open+2)
++#define __NR_ia32_vperfctr_read (__NR_ia32_vperfctr_open+3)
+
+-#define IA32_NR_syscalls 315 /* must be > than biggest syscall! */
++#define IA32_NR_syscalls 322 /* must be > than biggest syscall! */
+
+ #endif /* _ASM_X86_64_IA32_UNISTD_H_ */
+diff -rupN linux-2.6.16/include/asm-x86_64/irq.h linux-2.6.16.perfctr27/include/asm-x86_64/irq.h
+--- linux-2.6.16/include/asm-x86_64/irq.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.perfctr27/include/asm-x86_64/irq.h 2006-08-11 03:48:19.000000000 +0200
+@@ -29,7 +29,7 @@
+ */
+ #define NR_VECTORS 256
+
+-#define FIRST_SYSTEM_VECTOR 0xef /* duplicated in hw_irq.h */
++#define FIRST_SYSTEM_VECTOR 0xee /* duplicated in hw_irq.h */
+
+ #ifdef CONFIG_PCI_MSI
+ #define NR_IRQS FIRST_SYSTEM_VECTOR
+diff -rupN linux-2.6.16/include/asm-x86_64/processor.h linux-2.6.16.perfctr27/include/asm-x86_64/processor.h
+--- linux-2.6.16/include/asm-x86_64/processor.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.perfctr27/include/asm-x86_64/processor.h 2006-08-11 03:48:19.000000000 +0200
+@@ -260,6 +260,8 @@ struct thread_struct {
+ unsigned io_bitmap_max;
+ /* cached TLS descriptors. */
+ u64 tls_array[GDT_ENTRY_TLS_ENTRIES];
++/* performance counters */
++ struct vperfctr *perfctr;
+ } __attribute__((aligned(16)));
+
+ #define INIT_THREAD { \
+diff -rupN linux-2.6.16/include/asm-x86_64/system.h linux-2.6.16.perfctr27/include/asm-x86_64/system.h
+--- linux-2.6.16/include/asm-x86_64/system.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.perfctr27/include/asm-x86_64/system.h 2006-08-11 03:48:19.000000000 +0200
+@@ -26,7 +26,8 @@
+ #define __EXTRA_CLOBBER \
+ ,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
+
+-#define switch_to(prev,next,last) \
++#define switch_to(prev,next,last) do { \
++ perfctr_suspend_thread(&(prev)->thread); \
+ asm volatile(SAVE_CONTEXT \
+ "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */ \
+ "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */ \
+@@ -46,7 +47,8 @@
+ [tif_fork] "i" (TIF_FORK), \
+ [thread_info] "i" (offsetof(struct task_struct, thread_info)), \
+ [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent)) \
+- : "memory", "cc" __EXTRA_CLOBBER)
++ : "memory", "cc" __EXTRA_CLOBBER); \
++} while (0)
+
+ extern void load_gs_index(unsigned);
+
+diff -rupN linux-2.6.16/include/asm-x86_64/unistd.h linux-2.6.16.perfctr27/include/asm-x86_64/unistd.h
+--- linux-2.6.16/include/asm-x86_64/unistd.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.perfctr27/include/asm-x86_64/unistd.h 2006-08-11 03:48:23.000000000 +0200
+@@ -605,8 +605,30 @@ __SYSCALL(__NR_pselect6, sys_ni_syscall)
+ __SYSCALL(__NR_ppoll, sys_ni_syscall) /* for now */
+ #define __NR_unshare 272
+ __SYSCALL(__NR_unshare, sys_unshare)
++#define __NR_set_robust_list 273
++__SYSCALL(__NR_set_robust_list, sys_ni_syscall)
++#define __NR_get_robust_list 274
++__SYSCALL(__NR_get_robust_list, sys_ni_syscall)
++#define __NR_splice 275
++__SYSCALL(__NR_splice, sys_ni_syscall)
++#define __NR_tee 276
++__SYSCALL(__NR_tee, sys_ni_syscall)
++#define __NR_sync_file_range 277
++__SYSCALL(__NR_sync_file_range, sys_ni_syscall)
++#define __NR_vmsplice 278
++__SYSCALL(__NR_vmsplice, sys_ni_syscall)
++#define __NR_move_pages 279
++__SYSCALL(__NR_move_pages, sys_ni_syscall)
++#define __NR_vperfctr_open 280
++__SYSCALL(__NR_vperfctr_open, sys_vperfctr_open)
++#define __NR_vperfctr_control (__NR_vperfctr_open+1)
++__SYSCALL(__NR_vperfctr_control, sys_vperfctr_control)
++#define __NR_vperfctr_write (__NR_vperfctr_open+2)
++__SYSCALL(__NR_vperfctr_write, sys_vperfctr_write)
++#define __NR_vperfctr_read (__NR_vperfctr_open+3)
++__SYSCALL(__NR_vperfctr_read, sys_vperfctr_read)
+
+-#define __NR_syscall_max __NR_unshare
++#define __NR_syscall_max __NR_vperfctr_read
+
+ #ifndef __NO_STUBS
+
+diff -rupN linux-2.6.16/include/linux/sched.h linux-2.6.16.perfctr27/include/linux/sched.h
+--- linux-2.6.16/include/linux/sched.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.perfctr27/include/linux/sched.h 2006-08-11 03:48:19.000000000 +0200
+@@ -1222,6 +1222,9 @@ extern void unhash_process(struct task_s
+ * subscriptions and synchronises with wait4(). Also used in procfs. Also
+ * pins the final release of task.io_context. Also protects ->cpuset.
+ *
++ * Synchronises set_cpus_allowed(), unlink, and creat of ->thread.perfctr.
++ * [if CONFIG_PERFCTR_VIRTUAL]
++ *
+ * Nests both inside and outside of read_lock(&tasklist_lock).
+ * It must not be nested with write_lock_irq(&tasklist_lock),
+ * neither inside nor outside.
+diff -rupN linux-2.6.16/kernel/exit.c linux-2.6.16.perfctr27/kernel/exit.c
+--- linux-2.6.16/kernel/exit.c 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.perfctr27/kernel/exit.c 2006-08-11 03:48:19.000000000 +0200
+@@ -26,6 +26,7 @@
+ #include <linux/mount.h>
+ #include <linux/proc_fs.h>
+ #include <linux/mempolicy.h>
++#include <linux/perfctr.h>
+ #include <linux/cpuset.h>
+ #include <linux/syscalls.h>
+ #include <linux/signal.h>
+@@ -102,6 +103,7 @@ repeat:
+ zap_leader = (leader->exit_signal == -1);
+ }
+
++ perfctr_release_task(p);
+ sched_exit(p);
+ write_unlock_irq(&tasklist_lock);
+ spin_unlock(&p->proc_lock);
+diff -rupN linux-2.6.16/kernel/sched.c linux-2.6.16.perfctr27/kernel/sched.c
+--- linux-2.6.16/kernel/sched.c 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.perfctr27/kernel/sched.c 2006-08-11 03:48:19.000000000 +0200
+@@ -44,6 +44,7 @@
+ #include <linux/cpu.h>
+ #include <linux/cpuset.h>
+ #include <linux/percpu.h>
++#include <linux/perfctr.h>
+ #include <linux/kthread.h>
+ #include <linux/seq_file.h>
+ #include <linux/syscalls.h>
+@@ -4393,6 +4394,8 @@ int set_cpus_allowed(task_t *p, cpumask_
+ migration_req_t req;
+ runqueue_t *rq;
+
++ perfctr_set_cpus_allowed(p, new_mask);
++
+ rq = task_rq_lock(p, &flags);
+ if (!cpus_intersects(new_mask, cpu_online_map)) {
+ ret = -EINVAL;
+diff -rupN linux-2.6.16/kernel/sys_ni.c linux-2.6.16.perfctr27/kernel/sys_ni.c
+--- linux-2.6.16/kernel/sys_ni.c 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.perfctr27/kernel/sys_ni.c 2006-08-11 03:48:19.000000000 +0200
+@@ -68,6 +68,10 @@ cond_syscall(compat_sys_mq_timedsend);
+ cond_syscall(compat_sys_mq_timedreceive);
+ cond_syscall(compat_sys_mq_notify);
+ cond_syscall(compat_sys_mq_getsetattr);
++cond_syscall(sys_vperfctr_open);
++cond_syscall(sys_vperfctr_control);
++cond_syscall(sys_vperfctr_write);
++cond_syscall(sys_vperfctr_read);
+ cond_syscall(sys_mbind);
+ cond_syscall(sys_get_mempolicy);
+ cond_syscall(sys_set_mempolicy);
+diff -rupN linux-2.6.16/kernel/timer.c linux-2.6.16.perfctr27/kernel/timer.c
+--- linux-2.6.16/kernel/timer.c 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.perfctr27/kernel/timer.c 2006-08-11 03:48:19.000000000 +0200
+@@ -32,6 +32,7 @@
+ #include <linux/jiffies.h>
+ #include <linux/posix-timers.h>
+ #include <linux/cpu.h>
++#include <linux/perfctr.h>
+ #include <linux/syscalls.h>
+ #include <linux/delay.h>
+
+@@ -837,6 +838,7 @@ void update_process_times(int user_tick)
+ account_user_time(p, jiffies_to_cputime(1));
+ else
+ account_system_time(p, HARDIRQ_OFFSET, jiffies_to_cputime(1));
++ perfctr_sample_thread(&p->thread);
+ run_local_timers();
+ if (rcu_pending(cpu))
+ rcu_check_callbacks(cpu, user_tick);
diff --git a/src/perfctr-2.7.x/patches/patch-kernel-2.6.16.21-SLES10 b/src/perfctr-2.7.x/patches/patch-kernel-2.6.16.21-SLES10
new file mode 100644
index 0000000000000000000000000000000000000000..34dd996ac64fb658c6ec3756d930ba8edba12559
--- /dev/null
+++ b/src/perfctr-2.7.x/patches/patch-kernel-2.6.16.21-SLES10
@@ -0,0 +1,787 @@
+diff -rupN linux-2.6.16.21/CREDITS linux-2.6.16.21.perfctr27/CREDITS
+--- linux-2.6.16.21/CREDITS 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.21.perfctr27/CREDITS 2006-08-11 03:48:19.000000000 +0200
+@@ -2634,6 +2634,7 @@ N: Mikael Pettersson
+ E: mikpe@csd.uu.se
+ W: http://www.csd.uu.se/~mikpe/
+ D: Miscellaneous fixes
++D: Performance-monitoring counters driver
+
+ N: Reed H. Petty
+ E: rhp@draper.net
+diff -rupN linux-2.6.16.21/MAINTAINERS linux-2.6.16.21.perfctr27/MAINTAINERS
+--- linux-2.6.16.21/MAINTAINERS 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.21.perfctr27/MAINTAINERS 2006-08-11 03:48:19.000000000 +0200
+@@ -2071,6 +2071,12 @@ M: tsbogend@alpha.franken.de
+ L: netdev@vger.kernel.org
+ S: Maintained
+
++PERFORMANCE-MONITORING COUNTERS DRIVER
++P: Mikael Pettersson
++M: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
++S: Maintained
++
+ PHRAM MTD DRIVER
+ P: J�rn Engel
+ M: joern@wh.fh-wedel.de
+diff -rupN linux-2.6.16.21/arch/i386/Kconfig linux-2.6.16.21.perfctr27/arch/i386/Kconfig
+--- linux-2.6.16.21/arch/i386/Kconfig 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.21.perfctr27/arch/i386/Kconfig 2006-08-11 03:48:19.000000000 +0200
+@@ -685,6 +685,8 @@ config SECCOMP
+
+ If unsure, say Y. Only embedded should say N here.
+
++source "drivers/perfctr/Kconfig"
++
+ source kernel/Kconfig.hz
+
+ config KEXEC
+diff -rupN linux-2.6.16.21/arch/i386/kernel/entry.S linux-2.6.16.21.perfctr27/arch/i386/kernel/entry.S
+--- linux-2.6.16.21/arch/i386/kernel/entry.S 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.21.perfctr27/arch/i386/kernel/entry.S 2006-08-11 03:48:19.000000000 +0200
+@@ -432,6 +432,16 @@ ENTRY(name) \
+ /* The include is where all of the SMP etc. interrupts come from */
+ #include "entry_arch.h"
+
++#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PERFCTR)
++ENTRY(perfctr_interrupt)
++ pushl $LOCAL_PERFCTR_VECTOR-256
++ SAVE_ALL
++ pushl %esp
++ call smp_perfctr_interrupt
++ addl $4, %esp
++ jmp ret_from_intr
++#endif
++
+ ENTRY(divide_error)
+ pushl $0 # no error code
+ pushl $do_divide_error
+diff -rupN linux-2.6.16.21/arch/i386/kernel/i8259.c linux-2.6.16.21.perfctr27/arch/i386/kernel/i8259.c
+--- linux-2.6.16.21/arch/i386/kernel/i8259.c 2005-10-28 11:24:06.000000000 +0200
++++ linux-2.6.16.21.perfctr27/arch/i386/kernel/i8259.c 2006-08-11 03:48:19.000000000 +0200
+@@ -23,6 +23,7 @@
+ #include <asm/apic.h>
+ #include <asm/arch_hooks.h>
+ #include <asm/i8259.h>
++#include <asm/perfctr.h>
+
+ #include <io_ports.h>
+
+@@ -421,6 +422,8 @@ void __init init_IRQ(void)
+ */
+ intr_init_hook();
+
++ perfctr_vector_init();
++
+ /*
+ * Set the clock to HZ Hz, we already have a valid
+ * vector now:
+diff -rupN linux-2.6.16.21/arch/i386/kernel/process.c linux-2.6.16.21.perfctr27/arch/i386/kernel/process.c
+--- linux-2.6.16.21/arch/i386/kernel/process.c 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.21.perfctr27/arch/i386/kernel/process.c 2006-08-11 03:48:19.000000000 +0200
+@@ -33,6 +33,7 @@
+ #include <linux/delay.h>
+ #include <linux/reboot.h>
+ #include <linux/init.h>
++#include <linux/perfctr.h>
+ #include <linux/mc146818rtc.h>
+ #include <linux/module.h>
+ #include <linux/kallsyms.h>
+@@ -388,6 +389,7 @@ void exit_thread(void)
+ tss->io_bitmap_base = INVALID_IO_BITMAP_OFFSET;
+ put_cpu();
+ }
++ perfctr_exit_thread(&tsk->thread);
+ }
+
+ void flush_thread(void)
+@@ -439,6 +441,8 @@ int copy_thread(int nr, unsigned long cl
+ savesegment(fs,p->thread.fs);
+ savesegment(gs,p->thread.gs);
+
++ perfctr_copy_task(p, regs);
++
+ tsk = current;
+ if (unlikely(NULL != tsk->thread.io_bitmap_ptr)) {
+ p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
+@@ -697,6 +701,8 @@ struct task_struct fastcall * __switch_t
+
+ disable_tsc(prev_p, next_p);
+
++ perfctr_resume_thread(next);
++
+ return prev_p;
+ }
+
+diff -rupN linux-2.6.16.21/arch/i386/kernel/syscall_table.S linux-2.6.16.21.perfctr27/arch/i386/kernel/syscall_table.S
+--- linux-2.6.16.21/arch/i386/kernel/syscall_table.S 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.21.perfctr27/arch/i386/kernel/syscall_table.S 2006-08-11 03:48:23.000000000 +0200
+@@ -310,3 +310,14 @@ ENTRY(sys_call_table)
+ .long sys_pselect6
+ .long sys_ppoll
+ .long sys_unshare /* 310 */
++ .long sys_ni_syscall
++ .long sys_ni_syscall
++ .long sys_ni_syscall
++ .long sys_ni_syscall
++ .long sys_ni_syscall /* 315 */
++ .long sys_ni_syscall
++ .long sys_ni_syscall
++ .long sys_vperfctr_open
++ .long sys_vperfctr_control
++ .long sys_vperfctr_write /* 320 */
++ .long sys_vperfctr_read
+diff -rupN linux-2.6.16.21/arch/powerpc/Kconfig linux-2.6.16.21.perfctr27/arch/powerpc/Kconfig
+--- linux-2.6.16.21/arch/powerpc/Kconfig 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.21.perfctr27/arch/powerpc/Kconfig 2006-08-11 03:48:19.000000000 +0200
+@@ -268,6 +268,9 @@ config NOT_COHERENT_CACHE
+ bool
+ depends on 4xx || 8xx || E200
+ default y
++
++source "drivers/perfctr/Kconfig"
++
+ endmenu
+
+ source "init/Kconfig"
+diff -rupN linux-2.6.16.21/arch/powerpc/kernel/process.c linux-2.6.16.21.perfctr27/arch/powerpc/kernel/process.c
+--- linux-2.6.16.21/arch/powerpc/kernel/process.c 2006-07-03 14:17:57.000000000 -0500
++++ linux-2.6.16.21.perfctr27/arch/powerpc/kernel/process.c 2006-08-22 11:32:37.000000000 -0500
+@@ -34,6 +34,7 @@
+ #include <linux/init_task.h>
+ #include <linux/module.h>
+ #include <linux/kallsyms.h>
++#include <linux/perfctr.h>
+ #include <linux/mqueue.h>
+ #include <linux/hardirq.h>
+ #include <linux/utsname.h>
+@@ -330,11 +331,13 @@ struct task_struct *__switch_to(struct t
+ #endif
+
+ local_irq_save(flags);
++ perfctr_suspend_thread(&prev->thread);
+
+ account_system_vtime(current);
+ account_process_vtime(current);
+ calculate_steal_time();
+
+ last = _switch(old_thread, new_thread);
++ perfctr_resume_thread(¤t->thread);
+
+ local_irq_restore(flags);
+@@ -464,6 +467,7 @@ void exit_thread(void)
+ {
+ kprobe_flush_task(current);
+ discard_lazy_cpu_state();
++ perfctr_exit_thread(¤t->thread);
+ }
+
+ void flush_thread(void)
+@@ -576,6 +580,8 @@ int copy_thread(int nr, unsigned long cl
+ p->thread.last_syscall = -1;
+ #endif
+
++ perfctr_copy_task(p, regs);
++
+ return 0;
+ }
+
+diff -rupN linux-2.6.16.21/arch/powerpc/kernel/systbl.S linux-2.6.16.21.perfctr27/arch/powerpc/kernel/systbl.S
+--- linux-2.6.16.21/arch/powerpc/kernel/systbl.S 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.21.perfctr27/arch/powerpc/kernel/systbl.S 2006-08-11 03:48:23.000000000 +0200
+@@ -322,3 +322,25 @@ SYSCALL(spu_create)
+ COMPAT_SYS(pselect6)
+ COMPAT_SYS(ppoll)
+ SYSCALL(unshare)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(ni_syscall)
++SYSCALL(vperfctr_open)
++SYSCALL(vperfctr_control)
++SYSCALL(vperfctr_write)
++SYSCALL(vperfctr_read)
+diff -rupN linux-2.6.16.21/arch/x86_64/Kconfig linux-2.6.16.21.perfctr27/arch/x86_64/Kconfig
+--- linux-2.6.16.21/arch/x86_64/Kconfig 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.21.perfctr27/arch/x86_64/Kconfig 2006-08-11 03:48:19.000000000 +0200
+@@ -462,6 +462,8 @@ config SECCOMP
+
+ If unsure, say Y. Only embedded should say N here.
+
++source "drivers/perfctr/Kconfig"
++
+ source kernel/Kconfig.hz
+
+ endmenu
+diff -rupN linux-2.6.16.21/arch/x86_64/ia32/ia32entry.S linux-2.6.16.21.perfctr27/arch/x86_64/ia32/ia32entry.S
+--- linux-2.6.16.21/arch/x86_64/ia32/ia32entry.S 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.21.perfctr27/arch/x86_64/ia32/ia32entry.S 2006-08-11 03:48:23.000000000 +0200
+@@ -688,6 +688,17 @@ ia32_sys_call_table:
+ .quad sys_ni_syscall /* pselect6 for now */
+ .quad sys_ni_syscall /* ppoll for now */
+ .quad sys_unshare /* 310 */
++ .quad sys_ni_syscall
++ .quad sys_ni_syscall
++ .quad sys_ni_syscall
++ .quad sys_ni_syscall
++ .quad sys_ni_syscall /* 315 */
++ .quad sys_ni_syscall
++ .quad sys_ni_syscall
++ .quad sys_vperfctr_open
++ .quad sys_vperfctr_control
++ .quad sys_vperfctr_write /* 320 */
++ .quad sys_vperfctr_read
+ ia32_syscall_end:
+ .rept IA32_NR_syscalls-(ia32_syscall_end-ia32_sys_call_table)/8
+ .quad ni_syscall
+diff -rupN linux-2.6.16.21/arch/x86_64/kernel/entry.S linux-2.6.16.21.perfctr27/arch/x86_64/kernel/entry.S
+--- linux-2.6.16.21/arch/x86_64/kernel/entry.S 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.21.perfctr27/arch/x86_64/kernel/entry.S 2006-08-11 03:48:19.000000000 +0200
+@@ -655,6 +655,11 @@ ENTRY(spurious_interrupt)
+ apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
+ #endif
+
++#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PERFCTR)
++ENTRY(perfctr_interrupt)
++ apicinterrupt LOCAL_PERFCTR_VECTOR,smp_perfctr_interrupt
++#endif
++
+ /*
+ * Exception entry points.
+ */
+diff -rupN linux-2.6.16.21/arch/x86_64/kernel/i8259.c linux-2.6.16.21.perfctr27/arch/x86_64/kernel/i8259.c
+--- linux-2.6.16.21/arch/x86_64/kernel/i8259.c 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.21.perfctr27/arch/x86_64/kernel/i8259.c 2006-08-11 03:48:19.000000000 +0200
+@@ -23,6 +23,7 @@
+ #include <asm/delay.h>
+ #include <asm/desc.h>
+ #include <asm/apic.h>
++#include <asm/perfctr.h>
+
+ /*
+ * Common place to define all x86 IRQ vectors
+@@ -591,6 +592,8 @@ void __init init_IRQ(void)
+ set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
+ #endif
+
++ perfctr_vector_init();
++
+ /*
+ * Set the clock to HZ Hz, we already have a valid
+ * vector now:
+diff -rupN linux-2.6.16.21/arch/x86_64/kernel/process.c linux-2.6.16.21.perfctr27/arch/x86_64/kernel/process.c
+--- linux-2.6.16.21/arch/x86_64/kernel/process.c 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.21.perfctr27/arch/x86_64/kernel/process.c 2006-08-11 03:48:19.000000000 +0200
+@@ -33,6 +33,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/delay.h>
+ #include <linux/ptrace.h>
++#include <linux/perfctr.h>
+ #include <linux/utsname.h>
+ #include <linux/random.h>
+ #include <linux/kprobes.h>
+@@ -372,6 +373,7 @@ void exit_thread(void)
+ t->io_bitmap_max = 0;
+ put_cpu();
+ }
++ perfctr_exit_thread(&me->thread);
+ }
+
+ void flush_thread(void)
+@@ -473,6 +475,8 @@ int copy_thread(int nr, unsigned long cl
+ asm("mov %%es,%0" : "=m" (p->thread.es));
+ asm("mov %%ds,%0" : "=m" (p->thread.ds));
+
++ perfctr_copy_task(p, regs);
++
+ if (unlikely(me->thread.io_bitmap_ptr != NULL)) {
+ p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
+ if (!p->thread.io_bitmap_ptr) {
+@@ -627,6 +631,8 @@ __switch_to(struct task_struct *prev_p,
+ }
+ }
+
++ perfctr_resume_thread(next);
++
+ return prev_p;
+ }
+
+diff -rupN linux-2.6.16.21/drivers/Makefile linux-2.6.16.21.perfctr27/drivers/Makefile
+--- linux-2.6.16.21/drivers/Makefile 2006-08-10 21:57:06.000000000 +0200
++++ linux-2.6.16.21.perfctr27/drivers/Makefile 2006-08-11 03:48:19.000000000 +0200
+@@ -70,6 +70,7 @@ obj-$(CONFIG_CPU_FREQ) += cpufreq/
+ obj-$(CONFIG_MMC) += mmc/
+ obj-$(CONFIG_INFINIBAND) += infiniband/
+ obj-$(CONFIG_SGI_SN) += sn/
++obj-$(CONFIG_PERFCTR) += perfctr/
+ obj-y += firmware/
+ obj-$(CONFIG_CRYPTO) += crypto/
+ obj-$(CONFIG_SUPERH) += sh/
+diff -rupN linux-2.6.16.21/include/asm-i386/mach-default/irq_vectors.h linux-2.6.16.21.perfctr27/include/asm-i386/mach-default/irq_vectors.h
+--- linux-2.6.16.21/include/asm-i386/mach-default/irq_vectors.h 2004-05-10 11:14:37.000000000 +0200
++++ linux-2.6.16.21.perfctr27/include/asm-i386/mach-default/irq_vectors.h 2006-08-11 03:48:19.000000000 +0200
+@@ -56,14 +56,15 @@
+ * sources per level' errata.
+ */
+ #define LOCAL_TIMER_VECTOR 0xef
++#define LOCAL_PERFCTR_VECTOR 0xee
+
+ /*
+- * First APIC vector available to drivers: (vectors 0x30-0xee)
++ * First APIC vector available to drivers: (vectors 0x30-0xed)
+ * we start at 0x31 to spread out vectors evenly between priority
+ * levels. (0x80 is the syscall vector)
+ */
+ #define FIRST_DEVICE_VECTOR 0x31
+-#define FIRST_SYSTEM_VECTOR 0xef
++#define FIRST_SYSTEM_VECTOR 0xee
+
+ #define TIMER_IRQ 0
+
+diff -rupN linux-2.6.16.21/include/asm-i386/mach-visws/irq_vectors.h linux-2.6.16.21.perfctr27/include/asm-i386/mach-visws/irq_vectors.h
+--- linux-2.6.16.21/include/asm-i386/mach-visws/irq_vectors.h 2004-01-09 13:19:11.000000000 +0100
++++ linux-2.6.16.21.perfctr27/include/asm-i386/mach-visws/irq_vectors.h 2006-08-11 03:48:19.000000000 +0200
+@@ -35,14 +35,15 @@
+ * sources per level' errata.
+ */
+ #define LOCAL_TIMER_VECTOR 0xef
++#define LOCAL_PERFCTR_VECTOR 0xee
+
+ /*
+- * First APIC vector available to drivers: (vectors 0x30-0xee)
++ * First APIC vector available to drivers: (vectors 0x30-0xed)
+ * we start at 0x31 to spread out vectors evenly between priority
+ * levels. (0x80 is the syscall vector)
+ */
+ #define FIRST_DEVICE_VECTOR 0x31
+-#define FIRST_SYSTEM_VECTOR 0xef
++#define FIRST_SYSTEM_VECTOR 0xee
+
+ #define TIMER_IRQ 0
+
+diff -rupN linux-2.6.16.21/include/asm-i386/processor.h linux-2.6.16.21.perfctr27/include/asm-i386/processor.h
+--- linux-2.6.16.21/include/asm-i386/processor.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.21.perfctr27/include/asm-i386/processor.h 2006-08-11 03:48:19.000000000 +0200
+@@ -464,6 +464,8 @@ struct thread_struct {
+ unsigned long iopl;
+ /* max allowed port in the bitmap, in bytes: */
+ unsigned long io_bitmap_max;
++/* performance counters */
++ struct vperfctr *perfctr;
+ };
+
+ #define INIT_THREAD { \
+diff -rupN linux-2.6.16.21/include/asm-i386/system.h linux-2.6.16.21.perfctr27/include/asm-i386/system.h
+--- linux-2.6.16.21/include/asm-i386/system.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.21.perfctr27/include/asm-i386/system.h 2006-08-11 03:48:19.000000000 +0200
+@@ -14,6 +14,7 @@ extern struct task_struct * FASTCALL(__s
+
+ #define switch_to(prev,next,last) do { \
+ unsigned long esi,edi; \
++ perfctr_suspend_thread(&(prev)->thread); \
+ asm volatile("pushl %%ebp\n\t" \
+ "movl %%esp,%0\n\t" /* save ESP */ \
+ "movl %5,%%esp\n\t" /* restore ESP */ \
+diff -rupN linux-2.6.16.21/include/asm-i386/unistd.h linux-2.6.16.21.perfctr27/include/asm-i386/unistd.h
+--- linux-2.6.16.21/include/asm-i386/unistd.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.21.perfctr27/include/asm-i386/unistd.h 2006-08-11 03:48:23.000000000 +0200
+@@ -316,8 +316,12 @@
+ #define __NR_pselect6 308
+ #define __NR_ppoll 309
+ #define __NR_unshare 310
++#define __NR_vperfctr_open 311
++#define __NR_vperfctr_control (__NR_vperfctr_open+1)
++#define __NR_vperfctr_write (__NR_vperfctr_open+2)
++#define __NR_vperfctr_read (__NR_vperfctr_open+3)
+
+-#define NR_syscalls 311
++#define NR_syscalls 315
+
+ /*
+ * user-visible error numbers are in the range -1 - -128: see
+diff -rupN linux-2.6.16.21/include/asm-powerpc/processor.h linux-2.6.16.21.perfctr27/include/asm-powerpc/processor.h
+--- linux-2.6.16.21/include/asm-powerpc/processor.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.21.perfctr27/include/asm-powerpc/processor.h 2006-08-11 03:48:19.000000000 +0200
+@@ -193,6 +193,9 @@ struct thread_struct {
+ unsigned long spefscr; /* SPE & eFP status */
+ int used_spe; /* set if process has used spe */
+ #endif /* CONFIG_SPE */
++#ifdef CONFIG_PERFCTR_VIRTUAL
++ struct vperfctr *perfctr; /* performance counters */
++#endif
+ };
+
+ #define ARCH_MIN_TASKALIGN 16
+diff -rupN linux-2.6.16.21/include/asm-powerpc/reg.h linux-2.6.16.21.perfctr27/include/asm-powerpc/reg.h
+--- linux-2.6.16.21/include/asm-powerpc/reg.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.21.perfctr27/include/asm-powerpc/reg.h 2006-08-11 03:48:19.000000000 +0200
+@@ -365,10 +365,8 @@
+ #define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */
+ #define SPRN_PVR 0x11F /* Processor Version Register */
+ #define SPRN_RPA 0x3D6 /* Required Physical Address Register */
+-#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
+ #define SPRN_SDR1 0x019 /* MMU Hash Base Register */
+ #define SPRN_ASR 0x118 /* Address Space Register */
+-#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
+ #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
+ #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
+ #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
+@@ -403,13 +401,6 @@
+ #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
+ #define THRM3_E (1<<0)
+ #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
+-#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
+-#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
+-#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
+-#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
+-#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
+-#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
+-#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
+ #define SPRN_VRSAVE 0x100 /* Vector Register Save Register */
+ #define SPRN_XER 0x001 /* Fixed Point Exception Register */
+
+@@ -455,33 +446,7 @@
+ #define SPRN_SDAR 781
+
+ #else /* 32-bit */
+-#define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */
+-#define MMCR0_FC 0x80000000UL /* freeze counters */
+-#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
+-#define MMCR0_FCP 0x20000000UL /* freeze in problem state */
+-#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
+-#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
+-#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
+-#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
+-#define MMCR0_TBEE 0x00400000UL /* time base exception enable */
+-#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
+ #define MMCR0_PMCnCE 0x00004000UL /* count enable for all but PMC 1*/
+-#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
+-#define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */
+-#define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */
+-
+-#define SPRN_MMCR1 956
+-#define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */
+-#define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */
+-#define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */
+-#define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */
+-#define SPRN_MMCR2 944
+-#define SPRN_PMC1 953 /* Performance Counter Register 1 */
+-#define SPRN_PMC2 954 /* Performance Counter Register 2 */
+-#define SPRN_PMC3 957 /* Performance Counter Register 3 */
+-#define SPRN_PMC4 958 /* Performance Counter Register 4 */
+-#define SPRN_PMC5 945 /* Performance Counter Register 5 */
+-#define SPRN_PMC6 946 /* Performance Counter Register 6 */
+
+ #define SPRN_SIAR 955 /* Sampled Instruction Address Register */
+
+@@ -493,6 +458,77 @@
+ #define MMCR0_PMC2_CYCLES 0x1
+ #define MMCR0_PMC2_ITLB 0x7
+ #define MMCR0_PMC2_LOADMISSTIME 0x5
++
++/* Performance-monitoring control and counter registers */
++#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 (604 and up) */
++#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 (604e and up) */
++#define SPRN_MMCR2 0x3B0 /* Monitor Mode Control Register 2 (7400 and up) */
++#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 (604 and up) */
++#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 (604 and up) */
++#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 (604e and up) */
++#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 (604e and up) */
++#define SPRN_PMC5 0x3B1 /* Performance Counter Register 5 (7450 and up) */
++#define SPRN_PMC6 0x3B2 /* Performance Counter Register 6 (7450 and up) */
++#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register (604 and up) */
++#define SPRN_SDA 0x3BF /* Sampled Data Address Register (604/604e only) */
++#define SPRN_BAMR 0x3B7 /* Breakpoint Address Mask Register (7400 and up) */
++
++#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 (750 and up) */
++#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 (750 and up) */
++#define SPRN_UMMCR2 0x3A0 /* User Monitor Mode Control Register 0 (7400 and up) */
++#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 (750 and up) */
++#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 (750 and up) */
++#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 (750 and up) */
++#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 (750 and up) */
++#define SPRN_UPMC5 0x3A1 /* User Performance Counter Register 5 (7450 and up) */
++#define SPRN_UPMC6 0x3A2 /* User Performance Counter Register 5 (7450 and up) */
++#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register (750 and up) */
++#define SPRN_UBAMR 0x3A7 /* User Breakpoint Address Mask Register (7400 and up) */
++
++/* MMCR0 layout (74xx terminology) */
++#define MMCR0_FC 0x80000000 /* Freeze counters unconditionally. */
++#define MMCR0_FCS 0x40000000 /* Freeze counters while MSR[PR]=0 (supervisor mode). */
++#define MMCR0_FCP 0x20000000 /* Freeze counters while MSR[PR]=1 (user mode). */
++#define MMCR0_FCM1 0x10000000 /* Freeze counters while MSR[PM]=1. */
++#define MMCR0_FCM0 0x08000000 /* Freeze counters while MSR[PM]=0. */
++#define MMCR0_PMXE 0x04000000 /* Enable performance monitor exceptions.
++ * Cleared by hardware when a PM exception occurs.
++ * 604: PMXE is not cleared by hardware.
++ */
++#define MMCR0_FCECE 0x02000000 /* Freeze counters on enabled condition or event.
++ * FCECE is treated as 0 if TRIGGER is 1.
++ * 74xx: FC is set when the event occurs.
++ * 604/750: ineffective when PMXE=0.
++ */
++#define MMCR0_TBSEL 0x01800000 /* Time base lower (TBL) bit selector.
++ * 00: bit 31, 01: bit 23, 10: bit 19, 11: bit 15.
++ */
++#define MMCR0_TBEE 0x00400000 /* Enable event on TBL bit transition from 0 to 1. */
++#define MMCR0_THRESHOLD 0x003F0000 /* Threshold value for certain events. */
++#define MMCR0_PMC1CE 0x00008000 /* Enable event on PMC1 overflow. */
++#define MMCR0_PMCjCE 0x00004000 /* Enable event on PMC2-PMC6 overflow.
++ * 604/750: Overrides FCECE (DISCOUNT).
++ */
++#define MMCR0_TRIGGER 0x00002000 /* Disable PMC2-PMC6 until PMC1 overflow or other event.
++ * 74xx: cleared by hardware when the event occurs.
++ */
++#define MMCR0_PMC1SEL 0x00001FC0 /* PMC1 event selector, 7 bits. */
++#define MMCR0_PMC2SEL 0x0000003F /* PMC2 event selector, 6 bits. */
++
++/* MMCR1 layout (604e-7457) */
++#define MMCR1_PMC3SEL 0xF8000000 /* PMC3 event selector, 5 bits. */
++#define MMCR1_PMC4SEL 0x07C00000 /* PMC4 event selector, 5 bits. */
++#define MMCR1_PMC5SEL 0x003E0000 /* PMC5 event selector, 5 bits. (745x only) */
++#define MMCR1_PMC6SEL 0x0001F800 /* PMC6 event selector, 6 bits. (745x only) */
++#define MMCR1__RESERVED 0x000007FF /* should be zero */
++
++/* MMCR2 layout (7400-7457) */
++#define MMCR2_THRESHMULT 0x80000000 /* MMCR0[THRESHOLD] multiplier. */
++#define MMCR2_SMCNTEN 0x40000000 /* 7400/7410 only, should be zero. */
++#define MMCR2_SMINTEN 0x20000000 /* 7400/7410 only, should be zero. */
++#define MMCR2__RESERVED 0x1FFFFFFF /* should be zero */
++#define MMCR2_RESERVED (MMCR2_SMCNTEN | MMCR2_SMINTEN | MMCR2__RESERVED)
++
+ #endif
+
+ /* Processor Version Register (PVR) field extraction */
+diff -rupN linux-2.6.16.21/include/asm-powerpc/unistd.h linux-2.6.16.21.perfctr27/include/asm-powerpc/unistd.h
+--- linux-2.6.16.21/include/asm-powerpc/unistd.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.21.perfctr27/include/asm-powerpc/unistd.h 2006-08-11 03:48:23.000000000 +0200
+@@ -301,8 +301,12 @@
+ #define __NR_pselect6 280
+ #define __NR_ppoll 281
+ #define __NR_unshare 282
++#define __NR_vperfctr_open 301
++#define __NR_vperfctr_control (__NR_vperfctr_open+1)
++#define __NR_vperfctr_write (__NR_vperfctr_open+2)
++#define __NR_vperfctr_read (__NR_vperfctr_open+3)
+
+-#define __NR_syscalls 283
++#define __NR_syscalls 305
+
+ #ifdef __KERNEL__
+ #define __NR__exit __NR_exit
+diff -rupN linux-2.6.16.21/include/asm-x86_64/hw_irq.h linux-2.6.16.21.perfctr27/include/asm-x86_64/hw_irq.h
+--- linux-2.6.16.21/include/asm-x86_64/hw_irq.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.21.perfctr27/include/asm-x86_64/hw_irq.h 2006-08-11 03:48:19.000000000 +0200
+@@ -67,14 +67,15 @@ struct hw_interrupt_type;
+ * sources per level' errata.
+ */
+ #define LOCAL_TIMER_VECTOR 0xef
++#define LOCAL_PERFCTR_VECTOR 0xee
+
+ /*
+- * First APIC vector available to drivers: (vectors 0x30-0xee)
++ * First APIC vector available to drivers: (vectors 0x30-0xed)
+ * we start at 0x31 to spread out vectors evenly between priority
+ * levels. (0x80 is the syscall vector)
+ */
+ #define FIRST_DEVICE_VECTOR 0x31
+-#define FIRST_SYSTEM_VECTOR 0xef /* duplicated in irq.h */
++#define FIRST_SYSTEM_VECTOR 0xee /* duplicated in irq.h */
+
+
+ #ifndef __ASSEMBLY__
+diff -rupN linux-2.6.16.21/include/asm-x86_64/ia32_unistd.h linux-2.6.16.21.perfctr27/include/asm-x86_64/ia32_unistd.h
+--- linux-2.6.16.21/include/asm-x86_64/ia32_unistd.h 2006-07-03 14:17:56.000000000 -0500
++++ linux-2.6.16.21.perfctr27/include/asm-x86_64/ia32_unistd.h 2006-08-22 11:30:52.000000000 -0500
+@@ -316,5 +316,9 @@
+ #define __NR_ia32_pselect6 308
+ #define __NR_ia32_ppoll 309
+ #define __NR_ia32_unshare 310
++#define __NR_ia32_vperfctr_open 311
++#define __NR_ia32_vperfctr_control (__NR_ia32_vperfctr_open+1)
++#define __NR_ia32_vperfctr_write (__NR_ia32_vperfctr_open+2)
++#define __NR_ia32_vperfctr_read (__NR_ia32_vperfctr_open+3)
+
+ #endif /* _ASM_X86_64_IA32_UNISTD_H_ */
+diff -rupN linux-2.6.16.21/include/asm-x86_64/irq.h linux-2.6.16.21.perfctr27/include/asm-x86_64/irq.h
+--- linux-2.6.16.21/include/asm-x86_64/irq.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.21.perfctr27/include/asm-x86_64/irq.h 2006-08-11 03:48:19.000000000 +0200
+@@ -29,7 +29,7 @@
+ */
+ #define NR_VECTORS 256
+
+-#define FIRST_SYSTEM_VECTOR 0xef /* duplicated in hw_irq.h */
++#define FIRST_SYSTEM_VECTOR 0xee /* duplicated in hw_irq.h */
+
+ #ifdef CONFIG_PCI_MSI
+ #define NR_IRQS FIRST_SYSTEM_VECTOR
+diff -rupN linux-2.6.16.21/include/asm-x86_64/processor.h linux-2.6.16.21.perfctr27/include/asm-x86_64/processor.h
+--- linux-2.6.16.21/include/asm-x86_64/processor.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.21.perfctr27/include/asm-x86_64/processor.h 2006-08-11 03:48:19.000000000 +0200
+@@ -260,6 +260,8 @@ struct thread_struct {
+ unsigned io_bitmap_max;
+ /* cached TLS descriptors. */
+ u64 tls_array[GDT_ENTRY_TLS_ENTRIES];
++/* performance counters */
++ struct vperfctr *perfctr;
+ } __attribute__((aligned(16)));
+
+ #define INIT_THREAD { \
+diff -rupN linux-2.6.16.21/include/asm-x86_64/system.h linux-2.6.16.21.perfctr27/include/asm-x86_64/system.h
+--- linux-2.6.16.21/include/asm-x86_64/system.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.21.perfctr27/include/asm-x86_64/system.h 2006-08-11 03:48:19.000000000 +0200
+@@ -26,7 +26,8 @@
+ #define __EXTRA_CLOBBER \
+ ,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
+
+-#define switch_to(prev,next,last) \
++#define switch_to(prev,next,last) do { \
++ perfctr_suspend_thread(&(prev)->thread); \
+ asm volatile(SAVE_CONTEXT \
+ "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */ \
+ "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */ \
+@@ -46,7 +47,8 @@
+ [tif_fork] "i" (TIF_FORK), \
+ [thread_info] "i" (offsetof(struct task_struct, thread_info)), \
+ [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent)) \
+- : "memory", "cc" __EXTRA_CLOBBER)
++ : "memory", "cc" __EXTRA_CLOBBER); \
++} while (0)
+
+ extern void load_gs_index(unsigned);
+
+diff -rupN linux-2.6.16.21/include/asm-x86_64/unistd.h linux-2.6.16.21.perfctr27/include/asm-x86_64/unistd.h
+--- linux-2.6.16.21/include/asm-x86_64/unistd.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.21.perfctr27/include/asm-x86_64/unistd.h 2006-08-11 03:48:23.000000000 +0200
+@@ -605,8 +605,30 @@ __SYSCALL(__NR_pselect6, sys_ni_syscall)
+ __SYSCALL(__NR_ppoll, sys_ni_syscall) /* for now */
+ #define __NR_unshare 272
+ __SYSCALL(__NR_unshare, sys_unshare)
++#define __NR_set_robust_list 273
++__SYSCALL(__NR_set_robust_list, sys_ni_syscall)
++#define __NR_get_robust_list 274
++__SYSCALL(__NR_get_robust_list, sys_ni_syscall)
++#define __NR_splice 275
++__SYSCALL(__NR_splice, sys_ni_syscall)
++#define __NR_tee 276
++__SYSCALL(__NR_tee, sys_ni_syscall)
++#define __NR_sync_file_range 277
++__SYSCALL(__NR_sync_file_range, sys_ni_syscall)
++#define __NR_vmsplice 278
++__SYSCALL(__NR_vmsplice, sys_ni_syscall)
++#define __NR_move_pages 279
++__SYSCALL(__NR_move_pages, sys_ni_syscall)
++#define __NR_vperfctr_open 280
++__SYSCALL(__NR_vperfctr_open, sys_vperfctr_open)
++#define __NR_vperfctr_control (__NR_vperfctr_open+1)
++__SYSCALL(__NR_vperfctr_control, sys_vperfctr_control)
++#define __NR_vperfctr_write (__NR_vperfctr_open+2)
++__SYSCALL(__NR_vperfctr_write, sys_vperfctr_write)
++#define __NR_vperfctr_read (__NR_vperfctr_open+3)
++__SYSCALL(__NR_vperfctr_read, sys_vperfctr_read)
+
+-#define __NR_syscall_max __NR_unshare
++#define __NR_syscall_max __NR_vperfctr_read
+
+ #ifndef __NO_STUBS
+
+diff -rupN linux-2.6.16.21/include/linux/sched.h linux-2.6.16.21.perfctr27/include/linux/sched.h
+--- linux-2.6.16.21/include/linux/sched.h 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.21.perfctr27/include/linux/sched.h 2006-08-11 03:48:19.000000000 +0200
+@@ -1222,6 +1222,9 @@ extern void unhash_process(struct task_s
+ * subscriptions and synchronises with wait4(). Also used in procfs. Also
+ * pins the final release of task.io_context. Also protects ->cpuset.
+ *
++ * Synchronises set_cpus_allowed(), unlink, and creat of ->thread.perfctr.
++ * [if CONFIG_PERFCTR_VIRTUAL]
++ *
+ * Nests both inside and outside of read_lock(&tasklist_lock).
+ * It must not be nested with write_lock_irq(&tasklist_lock),
+ * neither inside nor outside.
+diff -rupN linux-2.6.16.21/kernel/exit.c linux-2.6.16.21.perfctr27/kernel/exit.c
+--- linux-2.6.16.21/kernel/exit.c 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.21.perfctr27/kernel/exit.c 2006-08-11 03:48:19.000000000 +0200
+@@ -26,6 +26,7 @@
+ #include <linux/mount.h>
+ #include <linux/proc_fs.h>
+ #include <linux/mempolicy.h>
++#include <linux/perfctr.h>
+ #include <linux/cpuset.h>
+ #include <linux/syscalls.h>
+ #include <linux/signal.h>
+@@ -102,6 +103,7 @@ repeat:
+ zap_leader = (leader->exit_signal == -1);
+ }
+
++ perfctr_release_task(p);
+ sched_exit(p);
+ write_unlock_irq(&tasklist_lock);
+ spin_unlock(&p->proc_lock);
+diff -rupN linux-2.6.16.21/kernel/sched.c linux-2.6.16.21.perfctr27/kernel/sched.c
+--- linux-2.6.16.21/kernel/sched.c 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.21.perfctr27/kernel/sched.c 2006-08-11 03:48:19.000000000 +0200
+@@ -44,6 +44,7 @@
+ #include <linux/cpu.h>
+ #include <linux/cpuset.h>
+ #include <linux/percpu.h>
++#include <linux/perfctr.h>
+ #include <linux/kthread.h>
+ #include <linux/seq_file.h>
+ #include <linux/syscalls.h>
+@@ -4393,6 +4394,8 @@ int set_cpus_allowed(task_t *p, cpumask_
+ migration_req_t req;
+ runqueue_t *rq;
+
++ perfctr_set_cpus_allowed(p, new_mask);
++
+ rq = task_rq_lock(p, &flags);
+ if (!cpus_intersects(new_mask, cpu_online_map)) {
+ ret = -EINVAL;
+diff -rupN linux-2.6.16.21/kernel/sys_ni.c linux-2.6.16.21.perfctr27/kernel/sys_ni.c
+--- linux-2.6.16.21/kernel/sys_ni.c 2006-08-10 21:57:10.000000000 +0200
++++ linux-2.6.16.21.perfctr27/kernel/sys_ni.c 2006-08-11 03:48:19.000000000 +0200
+@@ -68,6 +68,10 @@ cond_syscall(compat_sys_mq_timedsend);
+ cond_syscall(compat_sys_mq_timedreceive);
+ cond_syscall(compat_sys_mq_notify);
+ cond_syscall(compat_sys_mq_getsetattr);
++cond_syscall(sys_vperfctr_open);
++cond_syscall(sys_vperfctr_control);
++cond_syscall(sys_vperfctr_write);
++cond_syscall(sys_vperfctr_read);
+ cond_syscall(sys_mbind);
+ cond_syscall(sys_get_mempolicy);
+ cond_syscall(sys_set_mempolicy);
+diff -rupN linux-2.6.16.21/kernel/timer.c linux-2.6.16.21.perfctr27/kernel/timer.c
+--- linux-2.6.16.21/kernel/timer.c 2006-07-03 14:18:09.000000000 -0500
++++ linux-2.6.16.21.perfctr27/kernel/timer.c 2006-08-22 11:28:43.000000000 -0500
+@@ -32,6 +32,7 @@
+ #include <linux/jiffies.h>
+ #include <linux/posix-timers.h>
+ #include <linux/cpu.h>
++#include <linux/perfctr.h>
+ #include <linux/delay.h>
+ #include <linux/diskdump.h>
+ #include <linux/syscalls.h>
+@@ -840,6 +841,7 @@ void update_process_times(int user_tick)
+ account_user_time(p, jiffies_to_cputime(1));
+ else
+ account_system_time(p, HARDIRQ_OFFSET, jiffies_to_cputime(1));
++ perfctr_sample_thread(&p->thread);
+ run_local_timers();
+ if (rcu_pending(cpu))
+ rcu_check_callbacks(cpu, user_tick);
diff --git a/src/perfctr-2.7.x/patches/patch-kernel-2.6.17 b/src/perfctr-2.7.x/patches/patch-kernel-2.6.17
new file mode 100644
index 0000000000000000000000000000000000000000..032773109bd8ec0812aa533230a7bac258c17cd9
--- /dev/null
+++ b/src/perfctr-2.7.x/patches/patch-kernel-2.6.17
@@ -0,0 +1,745 @@
+diff -rupN linux-2.6.17/CREDITS linux-2.6.17.perfctr27/CREDITS
+--- linux-2.6.17/CREDITS 2006-06-18 12:13:01.000000000 +0200
++++ linux-2.6.17.perfctr27/CREDITS 2006-08-11 02:40:43.000000000 +0200
+@@ -2631,6 +2631,7 @@ N: Mikael Pettersson
+ E: mikpe@csd.uu.se
+ W: http://www.csd.uu.se/~mikpe/
+ D: Miscellaneous fixes
++D: Performance-monitoring counters driver
+
+ N: Reed H. Petty
+ E: rhp@draper.net
+diff -rupN linux-2.6.17/MAINTAINERS linux-2.6.17.perfctr27/MAINTAINERS
+--- linux-2.6.17/MAINTAINERS 2006-06-18 12:13:01.000000000 +0200
++++ linux-2.6.17.perfctr27/MAINTAINERS 2006-08-11 02:40:43.000000000 +0200
+@@ -2185,6 +2185,12 @@ M: tsbogend@alpha.franken.de
+ L: netdev@vger.kernel.org
+ S: Maintained
+
++PERFORMANCE-MONITORING COUNTERS DRIVER
++P: Mikael Pettersson
++M: mikpe@it.uu.se
++W: http://user.it.uu.se/~mikpe/linux/perfctr/
++S: Maintained
++
+ PERSONALITY HANDLING
+ P: Christoph Hellwig
+ M: hch@infradead.org
+diff -rupN linux-2.6.17/arch/i386/Kconfig linux-2.6.17.perfctr27/arch/i386/Kconfig
+--- linux-2.6.17/arch/i386/Kconfig 2006-06-18 12:13:01.000000000 +0200
++++ linux-2.6.17.perfctr27/arch/i386/Kconfig 2006-08-11 02:40:43.000000000 +0200
+@@ -708,6 +708,8 @@ config SECCOMP
+
+ If unsure, say Y. Only embedded should say N here.
+
++source "drivers/perfctr/Kconfig"
++
+ source kernel/Kconfig.hz
+
+ config KEXEC
+diff -rupN linux-2.6.17/arch/i386/kernel/entry.S linux-2.6.17.perfctr27/arch/i386/kernel/entry.S
+--- linux-2.6.17/arch/i386/kernel/entry.S 2006-06-18 12:13:01.000000000 +0200
++++ linux-2.6.17.perfctr27/arch/i386/kernel/entry.S 2006-08-11 02:40:43.000000000 +0200
+@@ -436,6 +436,16 @@ ENTRY(name) \
+ /* The include is where all of the SMP etc. interrupts come from */
+ #include "entry_arch.h"
+
++#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PERFCTR)
++ENTRY(perfctr_interrupt)
++ pushl $LOCAL_PERFCTR_VECTOR-256
++ SAVE_ALL
++ pushl %esp
++ call smp_perfctr_interrupt
++ addl $4, %esp
++ jmp ret_from_intr
++#endif
++
+ ENTRY(divide_error)
+ pushl $0 # no error code
+ pushl $do_divide_error
+diff -rupN linux-2.6.17/arch/i386/kernel/i8259.c linux-2.6.17.perfctr27/arch/i386/kernel/i8259.c
+--- linux-2.6.17/arch/i386/kernel/i8259.c 2005-10-28 11:24:06.000000000 +0200
++++ linux-2.6.17.perfctr27/arch/i386/kernel/i8259.c 2006-08-11 02:40:43.000000000 +0200
+@@ -23,6 +23,7 @@
+ #include <asm/apic.h>
+ #include <asm/arch_hooks.h>
+ #include <asm/i8259.h>
++#include <asm/perfctr.h>
+
+ #include <io_ports.h>
+
+@@ -421,6 +422,8 @@ void __init init_IRQ(void)
+ */
+ intr_init_hook();
+
++ perfctr_vector_init();
++
+ /*
+ * Set the clock to HZ Hz, we already have a valid
+ * vector now:
+diff -rupN linux-2.6.17/arch/i386/kernel/process.c linux-2.6.17.perfctr27/arch/i386/kernel/process.c
+--- linux-2.6.17/arch/i386/kernel/process.c 2006-06-18 12:13:01.000000000 +0200
++++ linux-2.6.17.perfctr27/arch/i386/kernel/process.c 2006-08-11 02:40:43.000000000 +0200
+@@ -33,6 +33,7 @@
+ #include <linux/delay.h>
+ #include <linux/reboot.h>
+ #include <linux/init.h>
++#include <linux/perfctr.h>
+ #include <linux/mc146818rtc.h>
+ #include <linux/module.h>
+ #include <linux/kallsyms.h>
+@@ -380,6 +381,7 @@ void exit_thread(void)
+ tss->io_bitmap_base = INVALID_IO_BITMAP_OFFSET;
+ put_cpu();
+ }
++ perfctr_exit_thread(&tsk->thread);
+ }
+
+ void flush_thread(void)
+@@ -431,6 +433,8 @@ int copy_thread(int nr, unsigned long cl
+ savesegment(fs,p->thread.fs);
+ savesegment(gs,p->thread.gs);
+
++ perfctr_copy_task(p, regs);
++
+ tsk = current;
+ if (unlikely(NULL != tsk->thread.io_bitmap_ptr)) {
+ p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
+@@ -689,6 +693,8 @@ struct task_struct fastcall * __switch_t
+
+ disable_tsc(prev_p, next_p);
+
++ perfctr_resume_thread(next);
++
+ return prev_p;
+ }
+
+diff -rupN linux-2.6.17/arch/i386/kernel/syscall_table.S linux-2.6.17.perfctr27/arch/i386/kernel/syscall_table.S
+--- linux-2.6.17/arch/i386/kernel/syscall_table.S 2006-06-18 12:13:01.000000000 +0200
++++ linux-2.6.17.perfctr27/arch/i386/kernel/syscall_table.S 2006-08-11 02:40:46.000000000 +0200
+@@ -316,3 +316,8 @@ ENTRY(sys_call_table)
+ .long sys_sync_file_range
+ .long sys_tee /* 315 */
+ .long sys_vmsplice
++ .long sys_ni_syscall
++ .long sys_vperfctr_open
++ .long sys_vperfctr_control
++ .long sys_vperfctr_write /* 320 */
++ .long sys_vperfctr_read
+diff -rupN linux-2.6.17/arch/powerpc/Kconfig linux-2.6.17.perfctr27/arch/powerpc/Kconfig
+--- linux-2.6.17/arch/powerpc/Kconfig 2006-06-18 12:13:01.000000000 +0200
++++ linux-2.6.17.perfctr27/arch/powerpc/Kconfig 2006-08-11 02:40:43.000000000 +0200
+@@ -299,6 +299,9 @@ config NOT_COHERENT_CACHE
+ bool
+ depends on 4xx || 8xx || E200
+ default y
++
++source "drivers/perfctr/Kconfig"
++
+ endmenu
+
+ source "init/Kconfig"
+diff -rupN linux-2.6.17/arch/powerpc/kernel/process.c linux-2.6.17.perfctr27/arch/powerpc/kernel/process.c
+--- linux-2.6.17/arch/powerpc/kernel/process.c 2006-06-18 12:13:01.000000000 +0200
++++ linux-2.6.17.perfctr27/arch/powerpc/kernel/process.c 2006-08-11 02:40:43.000000000 +0200
+@@ -32,6 +32,7 @@
+ #include <linux/init_task.h>
+ #include <linux/module.h>
+ #include <linux/kallsyms.h>
++#include <linux/perfctr.h>
+ #include <linux/mqueue.h>
+ #include <linux/hardirq.h>
+ #include <linux/utsname.h>
+@@ -333,7 +334,9 @@ struct task_struct *__switch_to(struct t
+ account_process_vtime(current);
+ calculate_steal_time();
+
++ perfctr_suspend_thread(&prev->thread);
+ last = _switch(old_thread, new_thread);
++ perfctr_resume_thread(¤t->thread);
+
+ local_irq_restore(flags);
+
+@@ -465,6 +468,7 @@ void show_regs(struct pt_regs * regs)
+ void exit_thread(void)
+ {
+ discard_lazy_cpu_state();
++ perfctr_exit_thread(¤t->thread);
+ }
+
+ void flush_thread(void)
+@@ -577,6 +581,8 @@ int copy_thread(int nr, unsigned long cl
+ p->thread.last_syscall = -1;
+ #endif
+
++ perfctr_copy_task(p, regs);
++
+ return 0;
+ }
+
+diff -rupN linux-2.6.17/arch/powerpc/kernel/systbl.S linux-2.6.17.perfctr27/arch/powerpc/kernel/systbl.S
+--- linux-2.6.17/arch/powerpc/kernel/systbl.S 2006-06-18 12:13:01.000000000 +0200
++++ linux-2.6.17.perfctr27/arch/powerpc/kernel/systbl.S 2006-08-11 02:40:43.000000000 +0200
+@@ -340,6 +340,10 @@ SYSCALL(fchmodat)
+ SYSCALL(faccessat)
+ COMPAT_SYS(get_robust_list)
+ COMPAT_SYS(set_robust_list)
++SYSCALL(vperfctr_open)
++SYSCALL(vperfctr_control)
++SYSCALL(vperfctr_write)
++SYSCALL(vperfctr_read)
+
+ /*
+ * please add new calls to arch/powerpc/platforms/cell/spu_callbacks.c
+diff -rupN linux-2.6.17/arch/x86_64/Kconfig linux-2.6.17.perfctr27/arch/x86_64/Kconfig
+--- linux-2.6.17/arch/x86_64/Kconfig 2006-06-18 12:13:02.000000000 +0200
++++ linux-2.6.17.perfctr27/arch/x86_64/Kconfig 2006-08-11 02:40:43.000000000 +0200
+@@ -491,6 +491,8 @@ config SECCOMP
+
+ If unsure, say Y. Only embedded should say N here.
+
++source "drivers/perfctr/Kconfig"
++
+ source kernel/Kconfig.hz
+
+ config REORDER
+diff -rupN linux-2.6.17/arch/x86_64/ia32/ia32entry.S linux-2.6.17.perfctr27/arch/x86_64/ia32/ia32entry.S
+--- linux-2.6.17/arch/x86_64/ia32/ia32entry.S 2006-06-18 12:13:02.000000000 +0200
++++ linux-2.6.17.perfctr27/arch/x86_64/ia32/ia32entry.S 2006-08-11 02:40:46.000000000 +0200
+@@ -694,6 +694,11 @@ ia32_sys_call_table:
+ .quad compat_sys_get_robust_list
+ .quad sys_splice
+ .quad sys_sync_file_range
+- .quad sys_tee
++ .quad sys_tee /* 315 */
+ .quad compat_sys_vmsplice
++ .quad quiet_ni_syscall
++ .quad sys_vperfctr_open
++ .quad sys_vperfctr_control
++ .quad sys_vperfctr_write /* 320 */
++ .quad sys_vperfctr_read
+ ia32_syscall_end:
+diff -rupN linux-2.6.17/arch/x86_64/kernel/entry.S linux-2.6.17.perfctr27/arch/x86_64/kernel/entry.S
+--- linux-2.6.17/arch/x86_64/kernel/entry.S 2006-06-18 12:13:02.000000000 +0200
++++ linux-2.6.17.perfctr27/arch/x86_64/kernel/entry.S 2006-08-11 02:40:43.000000000 +0200
+@@ -642,6 +642,11 @@ ENTRY(spurious_interrupt)
+ apicinterrupt SPURIOUS_APIC_VECTOR,smp_spurious_interrupt
+ #endif
+
++#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PERFCTR)
++ENTRY(perfctr_interrupt)
++ apicinterrupt LOCAL_PERFCTR_VECTOR,smp_perfctr_interrupt
++#endif
++
+ /*
+ * Exception entry points.
+ */
+diff -rupN linux-2.6.17/arch/x86_64/kernel/i8259.c linux-2.6.17.perfctr27/arch/x86_64/kernel/i8259.c
+--- linux-2.6.17/arch/x86_64/kernel/i8259.c 2006-03-20 10:40:03.000000000 +0100
++++ linux-2.6.17.perfctr27/arch/x86_64/kernel/i8259.c 2006-08-11 02:40:43.000000000 +0200
+@@ -23,6 +23,7 @@
+ #include <asm/delay.h>
+ #include <asm/desc.h>
+ #include <asm/apic.h>
++#include <asm/perfctr.h>
+
+ /*
+ * Common place to define all x86 IRQ vectors
+@@ -591,6 +592,8 @@ void __init init_IRQ(void)
+ set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
+ #endif
+
++ perfctr_vector_init();
++
+ /*
+ * Set the clock to HZ Hz, we already have a valid
+ * vector now:
+diff -rupN linux-2.6.17/arch/x86_64/kernel/process.c linux-2.6.17.perfctr27/arch/x86_64/kernel/process.c
+--- linux-2.6.17/arch/x86_64/kernel/process.c 2006-06-18 12:13:02.000000000 +0200
++++ linux-2.6.17.perfctr27/arch/x86_64/kernel/process.c 2006-08-11 02:40:43.000000000 +0200
+@@ -33,6 +33,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/delay.h>
+ #include <linux/ptrace.h>
++#include <linux/perfctr.h>
+ #include <linux/utsname.h>
+ #include <linux/random.h>
+ #include <linux/notifier.h>
+@@ -358,6 +359,7 @@ void exit_thread(void)
+ t->io_bitmap_max = 0;
+ put_cpu();
+ }
++ perfctr_exit_thread(&me->thread);
+ }
+
+ void flush_thread(void)
+@@ -459,6 +461,8 @@ int copy_thread(int nr, unsigned long cl
+ asm("mov %%es,%0" : "=m" (p->thread.es));
+ asm("mov %%ds,%0" : "=m" (p->thread.ds));
+
++ perfctr_copy_task(p, regs);
++
+ if (unlikely(me->thread.io_bitmap_ptr != NULL)) {
+ p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
+ if (!p->thread.io_bitmap_ptr) {
+@@ -616,6 +620,8 @@ __switch_to(struct task_struct *prev_p,
+ }
+ }
+
++ perfctr_resume_thread(next);
++
+ return prev_p;
+ }
+
+diff -rupN linux-2.6.17/drivers/Makefile linux-2.6.17.perfctr27/drivers/Makefile
+--- linux-2.6.17/drivers/Makefile 2006-06-18 12:13:02.000000000 +0200
++++ linux-2.6.17.perfctr27/drivers/Makefile 2006-08-11 02:40:43.000000000 +0200
+@@ -71,6 +71,7 @@ obj-$(CONFIG_NEW_LEDS) += leds/
+ obj-$(CONFIG_INFINIBAND) += infiniband/
+ obj-$(CONFIG_IPATH_CORE) += infiniband/
+ obj-$(CONFIG_SGI_SN) += sn/
++obj-$(CONFIG_PERFCTR) += perfctr/
+ obj-y += firmware/
+ obj-$(CONFIG_CRYPTO) += crypto/
+ obj-$(CONFIG_SUPERH) += sh/
+diff -rupN linux-2.6.17/include/asm-i386/mach-default/irq_vectors.h linux-2.6.17.perfctr27/include/asm-i386/mach-default/irq_vectors.h
+--- linux-2.6.17/include/asm-i386/mach-default/irq_vectors.h 2004-05-10 11:14:37.000000000 +0200
++++ linux-2.6.17.perfctr27/include/asm-i386/mach-default/irq_vectors.h 2006-08-11 02:40:43.000000000 +0200
+@@ -56,14 +56,15 @@
+ * sources per level' errata.
+ */
+ #define LOCAL_TIMER_VECTOR 0xef
++#define LOCAL_PERFCTR_VECTOR 0xee
+
+ /*
+- * First APIC vector available to drivers: (vectors 0x30-0xee)
++ * First APIC vector available to drivers: (vectors 0x30-0xed)
+ * we start at 0x31 to spread out vectors evenly between priority
+ * levels. (0x80 is the syscall vector)
+ */
+ #define FIRST_DEVICE_VECTOR 0x31
+-#define FIRST_SYSTEM_VECTOR 0xef
++#define FIRST_SYSTEM_VECTOR 0xee
+
+ #define TIMER_IRQ 0
+
+diff -rupN linux-2.6.17/include/asm-i386/mach-visws/irq_vectors.h linux-2.6.17.perfctr27/include/asm-i386/mach-visws/irq_vectors.h
+--- linux-2.6.17/include/asm-i386/mach-visws/irq_vectors.h 2004-01-09 13:19:11.000000000 +0100
++++ linux-2.6.17.perfctr27/include/asm-i386/mach-visws/irq_vectors.h 2006-08-11 02:40:43.000000000 +0200
+@@ -35,14 +35,15 @@
+ * sources per level' errata.
+ */
+ #define LOCAL_TIMER_VECTOR 0xef
++#define LOCAL_PERFCTR_VECTOR 0xee
+
+ /*
+- * First APIC vector available to drivers: (vectors 0x30-0xee)
++ * First APIC vector available to drivers: (vectors 0x30-0xed)
+ * we start at 0x31 to spread out vectors evenly between priority
+ * levels. (0x80 is the syscall vector)
+ */
+ #define FIRST_DEVICE_VECTOR 0x31
+-#define FIRST_SYSTEM_VECTOR 0xef
++#define FIRST_SYSTEM_VECTOR 0xee
+
+ #define TIMER_IRQ 0
+
+diff -rupN linux-2.6.17/include/asm-i386/processor.h linux-2.6.17.perfctr27/include/asm-i386/processor.h
+--- linux-2.6.17/include/asm-i386/processor.h 2006-06-18 12:13:11.000000000 +0200
++++ linux-2.6.17.perfctr27/include/asm-i386/processor.h 2006-08-11 02:40:43.000000000 +0200
+@@ -469,6 +469,8 @@ struct thread_struct {
+ unsigned long iopl;
+ /* max allowed port in the bitmap, in bytes: */
+ unsigned long io_bitmap_max;
++/* performance counters */
++ struct vperfctr *perfctr;
+ };
+
+ #define INIT_THREAD { \
+diff -rupN linux-2.6.17/include/asm-i386/system.h linux-2.6.17.perfctr27/include/asm-i386/system.h
+--- linux-2.6.17/include/asm-i386/system.h 2006-06-18 12:13:11.000000000 +0200
++++ linux-2.6.17.perfctr27/include/asm-i386/system.h 2006-08-11 02:40:43.000000000 +0200
+@@ -14,6 +14,7 @@ extern struct task_struct * FASTCALL(__s
+
+ #define switch_to(prev,next,last) do { \
+ unsigned long esi,edi; \
++ perfctr_suspend_thread(&(prev)->thread); \
+ asm volatile("pushl %%ebp\n\t" \
+ "movl %%esp,%0\n\t" /* save ESP */ \
+ "movl %5,%%esp\n\t" /* restore ESP */ \
+diff -rupN linux-2.6.17/include/asm-i386/unistd.h linux-2.6.17.perfctr27/include/asm-i386/unistd.h
+--- linux-2.6.17/include/asm-i386/unistd.h 2006-06-18 12:13:11.000000000 +0200
++++ linux-2.6.17.perfctr27/include/asm-i386/unistd.h 2006-08-11 02:40:46.000000000 +0200
+@@ -322,8 +322,12 @@
+ #define __NR_sync_file_range 314
+ #define __NR_tee 315
+ #define __NR_vmsplice 316
++#define __NR_vperfctr_open 318
++#define __NR_vperfctr_control (__NR_vperfctr_open+1)
++#define __NR_vperfctr_write (__NR_vperfctr_open+2)
++#define __NR_vperfctr_read (__NR_vperfctr_open+3)
+
+-#define NR_syscalls 317
++#define NR_syscalls 322
+
+ /*
+ * user-visible error numbers are in the range -1 - -128: see
+diff -rupN linux-2.6.17/include/asm-powerpc/processor.h linux-2.6.17.perfctr27/include/asm-powerpc/processor.h
+--- linux-2.6.17/include/asm-powerpc/processor.h 2006-06-18 12:13:11.000000000 +0200
++++ linux-2.6.17.perfctr27/include/asm-powerpc/processor.h 2006-08-11 02:40:43.000000000 +0200
+@@ -169,6 +169,9 @@ struct thread_struct {
+ unsigned long spefscr; /* SPE & eFP status */
+ int used_spe; /* set if process has used spe */
+ #endif /* CONFIG_SPE */
++#ifdef CONFIG_PERFCTR_VIRTUAL
++ struct vperfctr *perfctr; /* performance counters */
++#endif
+ };
+
+ #define ARCH_MIN_TASKALIGN 16
+diff -rupN linux-2.6.17/include/asm-powerpc/reg.h linux-2.6.17.perfctr27/include/asm-powerpc/reg.h
+--- linux-2.6.17/include/asm-powerpc/reg.h 2006-06-18 12:13:11.000000000 +0200
++++ linux-2.6.17.perfctr27/include/asm-powerpc/reg.h 2006-08-11 02:40:43.000000000 +0200
+@@ -365,10 +365,8 @@
+ #define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */
+ #define SPRN_PVR 0x11F /* Processor Version Register */
+ #define SPRN_RPA 0x3D6 /* Required Physical Address Register */
+-#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
+ #define SPRN_SDR1 0x019 /* MMU Hash Base Register */
+ #define SPRN_ASR 0x118 /* Address Space Register */
+-#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
+ #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
+ #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
+ #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
+@@ -403,13 +401,6 @@
+ #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
+ #define THRM3_E (1<<0)
+ #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
+-#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
+-#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
+-#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
+-#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
+-#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
+-#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
+-#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
+ #define SPRN_VRSAVE 0x100 /* Vector Register Save Register */
+ #define SPRN_XER 0x001 /* Fixed Point Exception Register */
+
+@@ -455,33 +446,7 @@
+ #define SPRN_SDAR 781
+
+ #else /* 32-bit */
+-#define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */
+-#define MMCR0_FC 0x80000000UL /* freeze counters */
+-#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
+-#define MMCR0_FCP 0x20000000UL /* freeze in problem state */
+-#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
+-#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
+-#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
+-#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
+-#define MMCR0_TBEE 0x00400000UL /* time base exception enable */
+-#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
+ #define MMCR0_PMCnCE 0x00004000UL /* count enable for all but PMC 1*/
+-#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
+-#define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */
+-#define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */
+-
+-#define SPRN_MMCR1 956
+-#define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */
+-#define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */
+-#define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */
+-#define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */
+-#define SPRN_MMCR2 944
+-#define SPRN_PMC1 953 /* Performance Counter Register 1 */
+-#define SPRN_PMC2 954 /* Performance Counter Register 2 */
+-#define SPRN_PMC3 957 /* Performance Counter Register 3 */
+-#define SPRN_PMC4 958 /* Performance Counter Register 4 */
+-#define SPRN_PMC5 945 /* Performance Counter Register 5 */
+-#define SPRN_PMC6 946 /* Performance Counter Register 6 */
+
+ #define SPRN_SIAR 955 /* Sampled Instruction Address Register */
+
+@@ -493,6 +458,77 @@
+ #define MMCR0_PMC2_CYCLES 0x1
+ #define MMCR0_PMC2_ITLB 0x7
+ #define MMCR0_PMC2_LOADMISSTIME 0x5
++
++/* Performance-monitoring control and counter registers */
++#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 (604 and up) */
++#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 (604e and up) */
++#define SPRN_MMCR2 0x3B0 /* Monitor Mode Control Register 2 (7400 and up) */
++#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 (604 and up) */
++#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 (604 and up) */
++#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 (604e and up) */
++#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 (604e and up) */
++#define SPRN_PMC5 0x3B1 /* Performance Counter Register 5 (7450 and up) */
++#define SPRN_PMC6 0x3B2 /* Performance Counter Register 6 (7450 and up) */
++#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register (604 and up) */
++#define SPRN_SDA 0x3BF /* Sampled Data Address Register (604/604e only) */
++#define SPRN_BAMR 0x3B7 /* Breakpoint Address Mask Register (7400 and up) */
++
++#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 (750 and up) */
++#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 (750 and up) */
++#define SPRN_UMMCR2 0x3A0 /* User Monitor Mode Control Register 0 (7400 and up) */
++#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 (750 and up) */
++#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 (750 and up) */
++#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 (750 and up) */
++#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 (750 and up) */
++#define SPRN_UPMC5 0x3A1 /* User Performance Counter Register 5 (7450 and up) */
++#define SPRN_UPMC6 0x3A2 /* User Performance Counter Register 5 (7450 and up) */
++#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register (750 and up) */
++#define SPRN_UBAMR 0x3A7 /* User Breakpoint Address Mask Register (7400 and up) */
++
++/* MMCR0 layout (74xx terminology) */
++#define MMCR0_FC 0x80000000 /* Freeze counters unconditionally. */
++#define MMCR0_FCS 0x40000000 /* Freeze counters while MSR[PR]=0 (supervisor mode). */
++#define MMCR0_FCP 0x20000000 /* Freeze counters while MSR[PR]=1 (user mode). */
++#define MMCR0_FCM1 0x10000000 /* Freeze counters while MSR[PM]=1. */
++#define MMCR0_FCM0 0x08000000 /* Freeze counters while MSR[PM]=0. */
++#define MMCR0_PMXE 0x04000000 /* Enable performance monitor exceptions.
++ * Cleared by hardware when a PM exception occurs.
++ * 604: PMXE is not cleared by hardware.
++ */
++#define MMCR0_FCECE 0x02000000 /* Freeze counters on enabled condition or event.
++ * FCECE is treated as 0 if TRIGGER is 1.
++ * 74xx: FC is set when the event occurs.
++ * 604/750: ineffective when PMXE=0.
++ */
++#define MMCR0_TBSEL 0x01800000 /* Time base lower (TBL) bit selector.
++ * 00: bit 31, 01: bit 23, 10: bit 19, 11: bit 15.
++ */
++#define MMCR0_TBEE 0x00400000 /* Enable event on TBL bit transition from 0 to 1. */
++#define MMCR0_THRESHOLD 0x003F0000 /* Threshold value for certain events. */
++#define MMCR0_PMC1CE 0x00008000 /* Enable event on PMC1 overflow. */
++#define MMCR0_PMCjCE 0x00004000 /* Enable event on PMC2-PMC6 overflow.
++ * 604/750: Overrides FCECE (DISCOUNT).
++ */
++#define MMCR0_TRIGGER 0x00002000 /* Disable PMC2-PMC6 until PMC1 overflow or other event.
++ * 74xx: cleared by hardware when the event occurs.
++ */
++#define MMCR0_PMC1SEL 0x00001FC0 /* PMC1 event selector, 7 bits. */
++#define MMCR0_PMC2SEL 0x0000003F /* PMC2 event selector, 6 bits. */
++
++/* MMCR1 layout (604e-7457) */
++#define MMCR1_PMC3SEL 0xF8000000 /* PMC3 event selector, 5 bits. */
++#define MMCR1_PMC4SEL 0x07C00000 /* PMC4 event selector, 5 bits. */
++#define MMCR1_PMC5SEL 0x003E0000 /* PMC5 event selector, 5 bits. (745x only) */
++#define MMCR1_PMC6SEL 0x0001F800 /* PMC6 event selector, 6 bits. (745x only) */
++#define MMCR1__RESERVED 0x000007FF /* should be zero */
++
++/* MMCR2 layout (7400-7457) */
++#define MMCR2_THRESHMULT 0x80000000 /* MMCR0[THRESHOLD] multiplier. */
++#define MMCR2_SMCNTEN 0x40000000 /* 7400/7410 only, should be zero. */
++#define MMCR2_SMINTEN 0x20000000 /* 7400/7410 only, should be zero. */
++#define MMCR2__RESERVED 0x1FFFFFFF /* should be zero */
++#define MMCR2_RESERVED (MMCR2_SMCNTEN | MMCR2_SMINTEN | MMCR2__RESERVED)
++
+ #endif
+
+ /* Processor Version Register (PVR) field extraction */
+diff -rupN linux-2.6.17/include/asm-powerpc/unistd.h linux-2.6.17.perfctr27/include/asm-powerpc/unistd.h
+--- linux-2.6.17/include/asm-powerpc/unistd.h 2006-06-18 12:13:11.000000000 +0200
++++ linux-2.6.17.perfctr27/include/asm-powerpc/unistd.h 2006-08-11 02:40:43.000000000 +0200
+@@ -323,8 +323,12 @@
+ #define __NR_faccessat 298
+ #define __NR_get_robust_list 299
+ #define __NR_set_robust_list 300
++#define __NR_vperfctr_open 301
++#define __NR_vperfctr_control (__NR_vperfctr_open+1)
++#define __NR_vperfctr_write (__NR_vperfctr_open+2)
++#define __NR_vperfctr_read (__NR_vperfctr_open+3)
+
+-#define __NR_syscalls 301
++#define __NR_syscalls 305
+
+ #ifdef __KERNEL__
+ #define __NR__exit __NR_exit
+diff -rupN linux-2.6.17/include/asm-x86_64/hw_irq.h linux-2.6.17.perfctr27/include/asm-x86_64/hw_irq.h
+--- linux-2.6.17/include/asm-x86_64/hw_irq.h 2006-03-20 10:40:11.000000000 +0100
++++ linux-2.6.17.perfctr27/include/asm-x86_64/hw_irq.h 2006-08-11 02:40:43.000000000 +0200
+@@ -67,14 +67,15 @@ struct hw_interrupt_type;
+ * sources per level' errata.
+ */
+ #define LOCAL_TIMER_VECTOR 0xef
++#define LOCAL_PERFCTR_VECTOR 0xee
+
+ /*
+- * First APIC vector available to drivers: (vectors 0x30-0xee)
++ * First APIC vector available to drivers: (vectors 0x30-0xed)
+ * we start at 0x31 to spread out vectors evenly between priority
+ * levels. (0x80 is the syscall vector)
+ */
+ #define FIRST_DEVICE_VECTOR 0x31
+-#define FIRST_SYSTEM_VECTOR 0xef /* duplicated in irq.h */
++#define FIRST_SYSTEM_VECTOR 0xee /* duplicated in irq.h */
+
+
+ #ifndef __ASSEMBLY__
+diff -rupN linux-2.6.17/include/asm-x86_64/ia32_unistd.h linux-2.6.17.perfctr27/include/asm-x86_64/ia32_unistd.h
+--- linux-2.6.17/include/asm-x86_64/ia32_unistd.h 2006-06-18 12:13:11.000000000 +0200
++++ linux-2.6.17.perfctr27/include/asm-x86_64/ia32_unistd.h 2006-08-11 02:40:46.000000000 +0200
+@@ -316,5 +316,9 @@
+ #define __NR_ia32_pselect6 308
+ #define __NR_ia32_ppoll 309
+ #define __NR_ia32_unshare 310
++#define __NR_ia32_vperfctr_open 318
++#define __NR_ia32_vperfctr_control (__NR_ia32_vperfctr_open+1)
++#define __NR_ia32_vperfctr_write (__NR_ia32_vperfctr_open+2)
++#define __NR_ia32_vperfctr_read (__NR_ia32_vperfctr_open+3)
+
+ #endif /* _ASM_X86_64_IA32_UNISTD_H_ */
+diff -rupN linux-2.6.17/include/asm-x86_64/irq.h linux-2.6.17.perfctr27/include/asm-x86_64/irq.h
+--- linux-2.6.17/include/asm-x86_64/irq.h 2006-03-20 10:40:11.000000000 +0100
++++ linux-2.6.17.perfctr27/include/asm-x86_64/irq.h 2006-08-11 02:40:43.000000000 +0200
+@@ -29,7 +29,7 @@
+ */
+ #define NR_VECTORS 256
+
+-#define FIRST_SYSTEM_VECTOR 0xef /* duplicated in hw_irq.h */
++#define FIRST_SYSTEM_VECTOR 0xee /* duplicated in hw_irq.h */
+
+ #ifdef CONFIG_PCI_MSI
+ #define NR_IRQS FIRST_SYSTEM_VECTOR
+diff -rupN linux-2.6.17/include/asm-x86_64/processor.h linux-2.6.17.perfctr27/include/asm-x86_64/processor.h
+--- linux-2.6.17/include/asm-x86_64/processor.h 2006-06-18 12:13:11.000000000 +0200
++++ linux-2.6.17.perfctr27/include/asm-x86_64/processor.h 2006-08-11 02:40:43.000000000 +0200
+@@ -264,6 +264,8 @@ struct thread_struct {
+ unsigned io_bitmap_max;
+ /* cached TLS descriptors. */
+ u64 tls_array[GDT_ENTRY_TLS_ENTRIES];
++/* performance counters */
++ struct vperfctr *perfctr;
+ } __attribute__((aligned(16)));
+
+ #define INIT_THREAD { \
+diff -rupN linux-2.6.17/include/asm-x86_64/system.h linux-2.6.17.perfctr27/include/asm-x86_64/system.h
+--- linux-2.6.17/include/asm-x86_64/system.h 2006-06-18 12:13:11.000000000 +0200
++++ linux-2.6.17.perfctr27/include/asm-x86_64/system.h 2006-08-11 02:40:43.000000000 +0200
+@@ -26,7 +26,8 @@
+ #define __EXTRA_CLOBBER \
+ ,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
+
+-#define switch_to(prev,next,last) \
++#define switch_to(prev,next,last) do { \
++ perfctr_suspend_thread(&(prev)->thread); \
+ asm volatile(SAVE_CONTEXT \
+ "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */ \
+ "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */ \
+@@ -46,7 +47,8 @@
+ [tif_fork] "i" (TIF_FORK), \
+ [thread_info] "i" (offsetof(struct task_struct, thread_info)), \
+ [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent)) \
+- : "memory", "cc" __EXTRA_CLOBBER)
++ : "memory", "cc" __EXTRA_CLOBBER); \
++} while (0)
+
+ extern void load_gs_index(unsigned);
+
+diff -rupN linux-2.6.17/include/asm-x86_64/unistd.h linux-2.6.17.perfctr27/include/asm-x86_64/unistd.h
+--- linux-2.6.17/include/asm-x86_64/unistd.h 2006-06-18 12:13:11.000000000 +0200
++++ linux-2.6.17.perfctr27/include/asm-x86_64/unistd.h 2006-08-11 02:40:46.000000000 +0200
+@@ -617,8 +617,18 @@ __SYSCALL(__NR_tee, sys_tee)
+ __SYSCALL(__NR_sync_file_range, sys_sync_file_range)
+ #define __NR_vmsplice 278
+ __SYSCALL(__NR_vmsplice, sys_vmsplice)
++#define __NR_move_pages 279
++__SYSCALL(__NR_move_pages, sys_ni_syscall)
++#define __NR_vperfctr_open 280
++__SYSCALL(__NR_vperfctr_open, sys_vperfctr_open)
++#define __NR_vperfctr_control (__NR_vperfctr_open+1)
++__SYSCALL(__NR_vperfctr_control, sys_vperfctr_control)
++#define __NR_vperfctr_write (__NR_vperfctr_open+2)
++__SYSCALL(__NR_vperfctr_write, sys_vperfctr_write)
++#define __NR_vperfctr_read (__NR_vperfctr_open+3)
++__SYSCALL(__NR_vperfctr_read, sys_vperfctr_read)
+
+-#define __NR_syscall_max __NR_vmsplice
++#define __NR_syscall_max __NR_vperfctr_read
+
+ #ifndef __NO_STUBS
+
+diff -rupN linux-2.6.17/include/linux/sched.h linux-2.6.17.perfctr27/include/linux/sched.h
+--- linux-2.6.17/include/linux/sched.h 2006-06-18 12:13:11.000000000 +0200
++++ linux-2.6.17.perfctr27/include/linux/sched.h 2006-08-11 02:40:43.000000000 +0200
+@@ -1229,6 +1229,9 @@ static inline int thread_group_empty(tas
+ * subscriptions and synchronises with wait4(). Also used in procfs. Also
+ * pins the final release of task.io_context. Also protects ->cpuset.
+ *
++ * Synchronises set_cpus_allowed(), unlink, and creat of ->thread.perfctr.
++ * [if CONFIG_PERFCTR_VIRTUAL]
++ *
+ * Nests both inside and outside of read_lock(&tasklist_lock).
+ * It must not be nested with write_lock_irq(&tasklist_lock),
+ * neither inside nor outside.
+diff -rupN linux-2.6.17/kernel/exit.c linux-2.6.17.perfctr27/kernel/exit.c
+--- linux-2.6.17/kernel/exit.c 2006-06-18 12:13:11.000000000 +0200
++++ linux-2.6.17.perfctr27/kernel/exit.c 2006-08-11 02:40:43.000000000 +0200
+@@ -26,6 +26,7 @@
+ #include <linux/mount.h>
+ #include <linux/proc_fs.h>
+ #include <linux/mempolicy.h>
++#include <linux/perfctr.h>
+ #include <linux/cpuset.h>
+ #include <linux/syscalls.h>
+ #include <linux/signal.h>
+@@ -170,6 +171,7 @@ repeat:
+ zap_leader = (leader->exit_signal == -1);
+ }
+
++ perfctr_release_task(p);
+ sched_exit(p);
+ write_unlock_irq(&tasklist_lock);
+ spin_unlock(&p->proc_lock);
+diff -rupN linux-2.6.17/kernel/sched.c linux-2.6.17.perfctr27/kernel/sched.c
+--- linux-2.6.17/kernel/sched.c 2006-06-18 12:13:11.000000000 +0200
++++ linux-2.6.17.perfctr27/kernel/sched.c 2006-08-11 02:40:43.000000000 +0200
+@@ -44,6 +44,7 @@
+ #include <linux/cpu.h>
+ #include <linux/cpuset.h>
+ #include <linux/percpu.h>
++#include <linux/perfctr.h>
+ #include <linux/kthread.h>
+ #include <linux/seq_file.h>
+ #include <linux/syscalls.h>
+@@ -4425,6 +4426,8 @@ int set_cpus_allowed(task_t *p, cpumask_
+ migration_req_t req;
+ runqueue_t *rq;
+
++ perfctr_set_cpus_allowed(p, new_mask);
++
+ rq = task_rq_lock(p, &flags);
+ if (!cpus_intersects(new_mask, cpu_online_map)) {
+ ret = -EINVAL;
+diff -rupN linux-2.6.17/kernel/sys_ni.c linux-2.6.17.perfctr27/kernel/sys_ni.c
+--- linux-2.6.17/kernel/sys_ni.c 2006-06-18 12:13:11.000000000 +0200
++++ linux-2.6.17.perfctr27/kernel/sys_ni.c 2006-08-11 02:40:43.000000000 +0200
+@@ -72,6 +72,10 @@ cond_syscall(compat_sys_mq_timedsend);
+ cond_syscall(compat_sys_mq_timedreceive);
+ cond_syscall(compat_sys_mq_notify);
+ cond_syscall(compat_sys_mq_getsetattr);
++cond_syscall(sys_vperfctr_open);
++cond_syscall(sys_vperfctr_control);
++cond_syscall(sys_vperfctr_write);
++cond_syscall(sys_vperfctr_read);
+ cond_syscall(sys_mbind);
+ cond_syscall(sys_get_mempolicy);
+ cond_syscall(sys_set_mempolicy);
+diff -rupN linux-2.6.17/kernel/timer.c linux-2.6.17.perfctr27/kernel/timer.c
+--- linux-2.6.17/kernel/timer.c 2006-06-18 12:13:11.000000000 +0200
++++ linux-2.6.17.perfctr27/kernel/timer.c 2006-08-11 02:40:43.000000000 +0200
+@@ -32,6 +32,7 @@
+ #include <linux/jiffies.h>
+ #include <linux/posix-timers.h>
+ #include <linux/cpu.h>
++#include <linux/perfctr.h>
+ #include <linux/syscalls.h>
+ #include <linux/delay.h>
+
+@@ -830,6 +831,7 @@ void update_process_times(int user_tick)
+ account_user_time(p, jiffies_to_cputime(1));
+ else
+ account_system_time(p, HARDIRQ_OFFSET, jiffies_to_cputime(1));
++ perfctr_sample_thread(&p->thread);
+ run_local_timers();
+ if (rcu_pending(cpu))
+ rcu_check_callbacks(cpu, user_tick);
diff --git a/src/perfctr-2.7.x/patches/patch-kernel-2.6.18-rc4 b/src/perfctr-2.7.x/patches/patch-kernel-2.6.18-rc4
new file mode 100644
index 0000000000000000000000000000000000000000..b5cfbf6f833c6434f5a1293381355911a6b25ad2
--- /dev/null
+++ b/src/perfctr-2.7.x/patches/patch-kernel-2.6.18-rc4
@@ -0,0 +1,735 @@
+diff -rupN linux-2.6.18-rc4/CREDITS linux-2.6.18-rc4.perfctr27/CREDITS
+--- linux-2.6.18-rc4/CREDITS 2006-08-11 01:34:29.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/CREDITS 2006-08-11 02:29:29.000000000 +0200
+@@ -2632,6 +2632,7 @@ N: Mikael Pettersson
+ E: mikpe@csd.uu.se
+ W: http://www.csd.uu.se/~mikpe/
+ D: Miscellaneous fixes
++D: Performance-monitoring counters driver
+
+ N: Reed H. Petty
+ E: rhp@draper.net
+diff -rupN linux-2.6.18-rc4/MAINTAINERS linux-2.6.18-rc4.perfctr27/MAINTAINERS
+--- linux-2.6.18-rc4/MAINTAINERS 2006-08-11 01:34:29.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/MAINTAINERS 2006-08-11 02:29:29.000000000 +0200
+@@ -2266,6 +2266,12 @@ M: nagar@watson.ibm.com
+ L: linux-kernel@vger.kernel.org
+ S: Maintained
+
++PERFORMANCE-MONITORING COUNTERS DRIVER
++P: Mikael Pettersson
++M: mikpe@csd.uu.se
++W: http://www.csd.uu.se/~mikpe/linux/perfctr/
++S: Maintained
++
+ PERSONALITY HANDLING
+ P: Christoph Hellwig
+ M: hch@infradead.org
+diff -rupN linux-2.6.18-rc4/arch/i386/Kconfig linux-2.6.18-rc4.perfctr27/arch/i386/Kconfig
+--- linux-2.6.18-rc4/arch/i386/Kconfig 2006-08-11 01:34:29.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/arch/i386/Kconfig 2006-08-11 02:29:29.000000000 +0200
+@@ -735,6 +735,8 @@ config SECCOMP
+
+ If unsure, say Y. Only embedded should say N here.
+
++source "drivers/perfctr/Kconfig"
++
+ source kernel/Kconfig.hz
+
+ config KEXEC
+diff -rupN linux-2.6.18-rc4/arch/i386/kernel/entry.S linux-2.6.18-rc4.perfctr27/arch/i386/kernel/entry.S
+--- linux-2.6.18-rc4/arch/i386/kernel/entry.S 2006-08-11 01:34:29.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/arch/i386/kernel/entry.S 2006-08-11 02:29:29.000000000 +0200
+@@ -587,6 +587,22 @@ ENTRY(name) \
+ /* The include is where all of the SMP etc. interrupts come from */
+ #include "entry_arch.h"
+
++#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PERFCTR)
++ENTRY(perfctr_interrupt)
++ RING0_INT_FRAME
++ pushl $~(LOCAL_PERFCTR_VECTOR)
++ CFI_ADJUST_CFA_OFFSET 4
++ SAVE_ALL
++ TRACE_IRQS_OFF
++ pushl %esp
++ CFI_ADJUST_CFA_OFFSET 4
++ call smp_perfctr_interrupt
++ addl $4, %esp
++ CFI_ADJUST_CFA_OFFSET -4
++ jmp ret_from_intr
++ CFI_ENDPROC
++#endif
++
+ ENTRY(divide_error)
+ RING0_INT_FRAME
+ pushl $0 # no error code
+diff -rupN linux-2.6.18-rc4/arch/i386/kernel/i8259.c linux-2.6.18-rc4.perfctr27/arch/i386/kernel/i8259.c
+--- linux-2.6.18-rc4/arch/i386/kernel/i8259.c 2006-08-11 01:34:29.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/arch/i386/kernel/i8259.c 2006-08-11 02:29:29.000000000 +0200
+@@ -22,6 +22,7 @@
+ #include <asm/apic.h>
+ #include <asm/arch_hooks.h>
+ #include <asm/i8259.h>
++#include <asm/perfctr.h>
+
+ #include <io_ports.h>
+
+@@ -420,6 +421,8 @@ void __init init_IRQ(void)
+ */
+ intr_init_hook();
+
++ perfctr_vector_init();
++
+ /*
+ * Set the clock to HZ Hz, we already have a valid
+ * vector now:
+diff -rupN linux-2.6.18-rc4/arch/i386/kernel/process.c linux-2.6.18-rc4.perfctr27/arch/i386/kernel/process.c
+--- linux-2.6.18-rc4/arch/i386/kernel/process.c 2006-08-11 01:34:29.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/arch/i386/kernel/process.c 2006-08-11 02:29:29.000000000 +0200
+@@ -32,6 +32,7 @@
+ #include <linux/delay.h>
+ #include <linux/reboot.h>
+ #include <linux/init.h>
++#include <linux/perfctr.h>
+ #include <linux/mc146818rtc.h>
+ #include <linux/module.h>
+ #include <linux/kallsyms.h>
+@@ -379,6 +380,7 @@ void exit_thread(void)
+ tss->io_bitmap_base = INVALID_IO_BITMAP_OFFSET;
+ put_cpu();
+ }
++ perfctr_exit_thread(¤t->thread);
+ }
+
+ void flush_thread(void)
+@@ -431,6 +433,8 @@ int copy_thread(int nr, unsigned long cl
+ savesegment(fs,p->thread.fs);
+ savesegment(gs,p->thread.gs);
+
++ perfctr_copy_task(p, regs);
++
+ tsk = current;
+ if (unlikely(test_tsk_thread_flag(tsk, TIF_IO_BITMAP))) {
+ p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
+@@ -696,6 +700,8 @@ struct task_struct fastcall * __switch_t
+
+ disable_tsc(prev_p, next_p);
+
++ perfctr_resume_thread(next);
++
+ return prev_p;
+ }
+
+diff -rupN linux-2.6.18-rc4/arch/i386/kernel/syscall_table.S linux-2.6.18-rc4.perfctr27/arch/i386/kernel/syscall_table.S
+--- linux-2.6.18-rc4/arch/i386/kernel/syscall_table.S 2006-08-11 01:34:29.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/arch/i386/kernel/syscall_table.S 2006-08-11 02:29:29.000000000 +0200
+@@ -317,3 +317,7 @@ ENTRY(sys_call_table)
+ .long sys_tee /* 315 */
+ .long sys_vmsplice
+ .long sys_move_pages
++ .long sys_vperfctr_open
++ .long sys_vperfctr_control
++ .long sys_vperfctr_write /* 320 */
++ .long sys_vperfctr_read
+diff -rupN linux-2.6.18-rc4/arch/powerpc/Kconfig linux-2.6.18-rc4.perfctr27/arch/powerpc/Kconfig
+--- linux-2.6.18-rc4/arch/powerpc/Kconfig 2006-08-11 01:34:30.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/arch/powerpc/Kconfig 2006-08-11 02:29:29.000000000 +0200
+@@ -316,6 +316,9 @@ config NOT_COHERENT_CACHE
+ bool
+ depends on 4xx || 8xx || E200
+ default y
++
++source "drivers/perfctr/Kconfig"
++
+ endmenu
+
+ source "init/Kconfig"
+diff -rupN linux-2.6.18-rc4/arch/powerpc/kernel/process.c linux-2.6.18-rc4.perfctr27/arch/powerpc/kernel/process.c
+--- linux-2.6.18-rc4/arch/powerpc/kernel/process.c 2006-08-11 01:34:30.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/arch/powerpc/kernel/process.c 2006-08-11 02:29:29.000000000 +0200
+@@ -31,6 +31,7 @@
+ #include <linux/init_task.h>
+ #include <linux/module.h>
+ #include <linux/kallsyms.h>
++#include <linux/perfctr.h>
+ #include <linux/mqueue.h>
+ #include <linux/hardirq.h>
+ #include <linux/utsname.h>
+@@ -332,7 +333,9 @@ struct task_struct *__switch_to(struct t
+ account_process_vtime(current);
+ calculate_steal_time();
+
++ perfctr_suspend_thread(&prev->thread);
+ last = _switch(old_thread, new_thread);
++ perfctr_resume_thread(¤t->thread);
+
+ local_irq_restore(flags);
+
+@@ -464,6 +467,7 @@ void show_regs(struct pt_regs * regs)
+ void exit_thread(void)
+ {
+ discard_lazy_cpu_state();
++ perfctr_exit_thread(¤t->thread);
+ }
+
+ void flush_thread(void)
+@@ -576,6 +580,8 @@ int copy_thread(int nr, unsigned long cl
+ p->thread.last_syscall = -1;
+ #endif
+
++ perfctr_copy_task(p, regs);
++
+ return 0;
+ }
+
+diff -rupN linux-2.6.18-rc4/arch/x86_64/Kconfig linux-2.6.18-rc4.perfctr27/arch/x86_64/Kconfig
+--- linux-2.6.18-rc4/arch/x86_64/Kconfig 2006-08-11 01:34:30.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/arch/x86_64/Kconfig 2006-08-11 02:29:29.000000000 +0200
+@@ -522,6 +522,8 @@ config SECCOMP
+
+ If unsure, say Y. Only embedded should say N here.
+
++source "drivers/perfctr/Kconfig"
++
+ source kernel/Kconfig.hz
+
+ config REORDER
+diff -rupN linux-2.6.18-rc4/arch/x86_64/ia32/ia32entry.S linux-2.6.18-rc4.perfctr27/arch/x86_64/ia32/ia32entry.S
+--- linux-2.6.18-rc4/arch/x86_64/ia32/ia32entry.S 2006-08-11 01:34:30.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/arch/x86_64/ia32/ia32entry.S 2006-08-11 02:29:29.000000000 +0200
+@@ -713,4 +713,8 @@ ia32_sys_call_table:
+ .quad sys_tee
+ .quad compat_sys_vmsplice
+ .quad compat_sys_move_pages
++ .quad sys_vperfctr_open
++ .quad sys_vperfctr_control
++ .quad sys_vperfctr_write /* 320 */
++ .quad sys_vperfctr_read
+ ia32_syscall_end:
+diff -rupN linux-2.6.18-rc4/arch/x86_64/kernel/entry.S linux-2.6.18-rc4.perfctr27/arch/x86_64/kernel/entry.S
+--- linux-2.6.18-rc4/arch/x86_64/kernel/entry.S 2006-08-11 01:34:30.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/arch/x86_64/kernel/entry.S 2006-08-11 02:29:29.000000000 +0200
+@@ -693,6 +693,12 @@ ENTRY(spurious_interrupt)
+ END(spurious_interrupt)
+ #endif
+
++#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PERFCTR)
++ENTRY(perfctr_interrupt)
++ apicinterrupt LOCAL_PERFCTR_VECTOR,smp_perfctr_interrupt
++END(perfctr_interrupt)
++#endif
++
+ /*
+ * Exception entry points.
+ */
+diff -rupN linux-2.6.18-rc4/arch/x86_64/kernel/i8259.c linux-2.6.18-rc4.perfctr27/arch/x86_64/kernel/i8259.c
+--- linux-2.6.18-rc4/arch/x86_64/kernel/i8259.c 2006-08-11 01:34:30.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/arch/x86_64/kernel/i8259.c 2006-08-11 02:29:29.000000000 +0200
+@@ -22,6 +22,7 @@
+ #include <asm/delay.h>
+ #include <asm/desc.h>
+ #include <asm/apic.h>
++#include <asm/perfctr.h>
+
+ /*
+ * Common place to define all x86 IRQ vectors
+@@ -590,6 +591,8 @@ void __init init_IRQ(void)
+ set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
+ #endif
+
++ perfctr_vector_init();
++
+ /*
+ * Set the clock to HZ Hz, we already have a valid
+ * vector now:
+diff -rupN linux-2.6.18-rc4/arch/x86_64/kernel/process.c linux-2.6.18-rc4.perfctr27/arch/x86_64/kernel/process.c
+--- linux-2.6.18-rc4/arch/x86_64/kernel/process.c 2006-08-11 01:34:30.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/arch/x86_64/kernel/process.c 2006-08-11 02:29:29.000000000 +0200
+@@ -32,6 +32,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/delay.h>
+ #include <linux/ptrace.h>
++#include <linux/perfctr.h>
+ #include <linux/utsname.h>
+ #include <linux/random.h>
+ #include <linux/notifier.h>
+@@ -357,6 +358,7 @@ void exit_thread(void)
+ t->io_bitmap_max = 0;
+ put_cpu();
+ }
++ perfctr_exit_thread(&me->thread);
+ }
+
+ void flush_thread(void)
+@@ -461,6 +463,8 @@ int copy_thread(int nr, unsigned long cl
+ asm("mov %%es,%0" : "=m" (p->thread.es));
+ asm("mov %%ds,%0" : "=m" (p->thread.ds));
+
++ perfctr_copy_task(p, regs);
++
+ if (unlikely(me->thread.io_bitmap_ptr != NULL)) {
+ p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
+ if (!p->thread.io_bitmap_ptr) {
+@@ -618,6 +622,8 @@ __switch_to(struct task_struct *prev_p,
+ }
+ }
+
++ perfctr_resume_thread(next);
++
+ return prev_p;
+ }
+
+diff -rupN linux-2.6.18-rc4/drivers/Makefile linux-2.6.18-rc4.perfctr27/drivers/Makefile
+--- linux-2.6.18-rc4/drivers/Makefile 2006-08-11 01:34:30.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/drivers/Makefile 2006-08-11 02:29:29.000000000 +0200
+@@ -71,6 +71,7 @@ obj-$(CONFIG_NEW_LEDS) += leds/
+ obj-$(CONFIG_INFINIBAND) += infiniband/
+ obj-$(CONFIG_IPATH_CORE) += infiniband/
+ obj-$(CONFIG_SGI_SN) += sn/
++obj-$(CONFIG_PERFCTR) += perfctr/
+ obj-y += firmware/
+ obj-$(CONFIG_CRYPTO) += crypto/
+ obj-$(CONFIG_SUPERH) += sh/
+diff -rupN linux-2.6.18-rc4/include/asm-i386/mach-default/irq_vectors.h linux-2.6.18-rc4.perfctr27/include/asm-i386/mach-default/irq_vectors.h
+--- linux-2.6.18-rc4/include/asm-i386/mach-default/irq_vectors.h 2004-05-10 11:14:37.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/include/asm-i386/mach-default/irq_vectors.h 2006-08-11 02:29:29.000000000 +0200
+@@ -56,14 +56,15 @@
+ * sources per level' errata.
+ */
+ #define LOCAL_TIMER_VECTOR 0xef
++#define LOCAL_PERFCTR_VECTOR 0xee
+
+ /*
+- * First APIC vector available to drivers: (vectors 0x30-0xee)
++ * First APIC vector available to drivers: (vectors 0x30-0xed)
+ * we start at 0x31 to spread out vectors evenly between priority
+ * levels. (0x80 is the syscall vector)
+ */
+ #define FIRST_DEVICE_VECTOR 0x31
+-#define FIRST_SYSTEM_VECTOR 0xef
++#define FIRST_SYSTEM_VECTOR 0xee
+
+ #define TIMER_IRQ 0
+
+diff -rupN linux-2.6.18-rc4/include/asm-i386/mach-visws/irq_vectors.h linux-2.6.18-rc4.perfctr27/include/asm-i386/mach-visws/irq_vectors.h
+--- linux-2.6.18-rc4/include/asm-i386/mach-visws/irq_vectors.h 2004-01-09 13:19:11.000000000 +0100
++++ linux-2.6.18-rc4.perfctr27/include/asm-i386/mach-visws/irq_vectors.h 2006-08-11 02:29:29.000000000 +0200
+@@ -35,14 +35,15 @@
+ * sources per level' errata.
+ */
+ #define LOCAL_TIMER_VECTOR 0xef
++#define LOCAL_PERFCTR_VECTOR 0xee
+
+ /*
+- * First APIC vector available to drivers: (vectors 0x30-0xee)
++ * First APIC vector available to drivers: (vectors 0x30-0xed)
+ * we start at 0x31 to spread out vectors evenly between priority
+ * levels. (0x80 is the syscall vector)
+ */
+ #define FIRST_DEVICE_VECTOR 0x31
+-#define FIRST_SYSTEM_VECTOR 0xef
++#define FIRST_SYSTEM_VECTOR 0xee
+
+ #define TIMER_IRQ 0
+
+diff -rupN linux-2.6.18-rc4/include/asm-i386/processor.h linux-2.6.18-rc4.perfctr27/include/asm-i386/processor.h
+--- linux-2.6.18-rc4/include/asm-i386/processor.h 2006-08-11 01:34:35.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/include/asm-i386/processor.h 2006-08-11 02:29:29.000000000 +0200
+@@ -471,6 +471,8 @@ struct thread_struct {
+ unsigned long iopl;
+ /* max allowed port in the bitmap, in bytes: */
+ unsigned long io_bitmap_max;
++/* performance counters */
++ struct vperfctr *perfctr;
+ };
+
+ #define INIT_THREAD { \
+diff -rupN linux-2.6.18-rc4/include/asm-i386/system.h linux-2.6.18-rc4.perfctr27/include/asm-i386/system.h
+--- linux-2.6.18-rc4/include/asm-i386/system.h 2006-08-11 01:34:35.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/include/asm-i386/system.h 2006-08-11 02:29:29.000000000 +0200
+@@ -13,6 +13,7 @@ extern struct task_struct * FASTCALL(__s
+
+ #define switch_to(prev,next,last) do { \
+ unsigned long esi,edi; \
++ perfctr_suspend_thread(&(prev)->thread); \
+ asm volatile("pushl %%ebp\n\t" \
+ "movl %%esp,%0\n\t" /* save ESP */ \
+ "movl %5,%%esp\n\t" /* restore ESP */ \
+diff -rupN linux-2.6.18-rc4/include/asm-i386/unistd.h linux-2.6.18-rc4.perfctr27/include/asm-i386/unistd.h
+--- linux-2.6.18-rc4/include/asm-i386/unistd.h 2006-08-11 01:34:35.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/include/asm-i386/unistd.h 2006-08-11 02:29:29.000000000 +0200
+@@ -323,10 +323,14 @@
+ #define __NR_tee 315
+ #define __NR_vmsplice 316
+ #define __NR_move_pages 317
++#define __NR_vperfctr_open 318
++#define __NR_vperfctr_control (__NR_vperfctr_open+1)
++#define __NR_vperfctr_write (__NR_vperfctr_open+2)
++#define __NR_vperfctr_read (__NR_vperfctr_open+3)
+
+ #ifdef __KERNEL__
+
+-#define NR_syscalls 318
++#define NR_syscalls 322
+
+ /*
+ * user-visible error numbers are in the range -1 - -128: see
+diff -rupN linux-2.6.18-rc4/include/asm-powerpc/processor.h linux-2.6.18-rc4.perfctr27/include/asm-powerpc/processor.h
+--- linux-2.6.18-rc4/include/asm-powerpc/processor.h 2006-08-11 01:34:35.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/include/asm-powerpc/processor.h 2006-08-11 02:29:29.000000000 +0200
+@@ -169,6 +169,9 @@ struct thread_struct {
+ unsigned long spefscr; /* SPE & eFP status */
+ int used_spe; /* set if process has used spe */
+ #endif /* CONFIG_SPE */
++#ifdef CONFIG_PERFCTR_VIRTUAL
++ struct vperfctr *perfctr; /* performance counters */
++#endif
+ };
+
+ #define ARCH_MIN_TASKALIGN 16
+diff -rupN linux-2.6.18-rc4/include/asm-powerpc/reg.h linux-2.6.18-rc4.perfctr27/include/asm-powerpc/reg.h
+--- linux-2.6.18-rc4/include/asm-powerpc/reg.h 2006-08-11 01:34:35.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/include/asm-powerpc/reg.h 2006-08-11 02:29:29.000000000 +0200
+@@ -365,10 +365,8 @@
+ #define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */
+ #define SPRN_PVR 0x11F /* Processor Version Register */
+ #define SPRN_RPA 0x3D6 /* Required Physical Address Register */
+-#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
+ #define SPRN_SDR1 0x019 /* MMU Hash Base Register */
+ #define SPRN_ASR 0x118 /* Address Space Register */
+-#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
+ #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
+ #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
+ #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
+@@ -405,13 +403,6 @@
+ #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
+ #define THRM3_E (1<<0)
+ #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
+-#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
+-#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
+-#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
+-#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
+-#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
+-#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
+-#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
+ #define SPRN_VRSAVE 0x100 /* Vector Register Save Register */
+ #define SPRN_XER 0x001 /* Fixed Point Exception Register */
+
+@@ -461,33 +452,7 @@
+ #define SPRN_SDAR 781
+
+ #else /* 32-bit */
+-#define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */
+-#define MMCR0_FC 0x80000000UL /* freeze counters */
+-#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
+-#define MMCR0_FCP 0x20000000UL /* freeze in problem state */
+-#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
+-#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
+-#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
+-#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
+-#define MMCR0_TBEE 0x00400000UL /* time base exception enable */
+-#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
+ #define MMCR0_PMCnCE 0x00004000UL /* count enable for all but PMC 1*/
+-#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
+-#define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */
+-#define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */
+-
+-#define SPRN_MMCR1 956
+-#define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */
+-#define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */
+-#define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */
+-#define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */
+-#define SPRN_MMCR2 944
+-#define SPRN_PMC1 953 /* Performance Counter Register 1 */
+-#define SPRN_PMC2 954 /* Performance Counter Register 2 */
+-#define SPRN_PMC3 957 /* Performance Counter Register 3 */
+-#define SPRN_PMC4 958 /* Performance Counter Register 4 */
+-#define SPRN_PMC5 945 /* Performance Counter Register 5 */
+-#define SPRN_PMC6 946 /* Performance Counter Register 6 */
+
+ #define SPRN_SIAR 955 /* Sampled Instruction Address Register */
+
+@@ -499,6 +464,77 @@
+ #define MMCR0_PMC2_CYCLES 0x1
+ #define MMCR0_PMC2_ITLB 0x7
+ #define MMCR0_PMC2_LOADMISSTIME 0x5
++
++/* Performance-monitoring control and counter registers */
++#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 (604 and up) */
++#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 (604e and up) */
++#define SPRN_MMCR2 0x3B0 /* Monitor Mode Control Register 2 (7400 and up) */
++#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 (604 and up) */
++#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 (604 and up) */
++#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 (604e and up) */
++#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 (604e and up) */
++#define SPRN_PMC5 0x3B1 /* Performance Counter Register 5 (7450 and up) */
++#define SPRN_PMC6 0x3B2 /* Performance Counter Register 6 (7450 and up) */
++#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register (604 and up) */
++#define SPRN_SDA 0x3BF /* Sampled Data Address Register (604/604e only) */
++#define SPRN_BAMR 0x3B7 /* Breakpoint Address Mask Register (7400 and up) */
++
++#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 (750 and up) */
++#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 (750 and up) */
++#define SPRN_UMMCR2 0x3A0 /* User Monitor Mode Control Register 0 (7400 and up) */
++#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 (750 and up) */
++#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 (750 and up) */
++#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 (750 and up) */
++#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 (750 and up) */
++#define SPRN_UPMC5 0x3A1 /* User Performance Counter Register 5 (7450 and up) */
++#define SPRN_UPMC6 0x3A2 /* User Performance Counter Register 5 (7450 and up) */
++#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register (750 and up) */
++#define SPRN_UBAMR 0x3A7 /* User Breakpoint Address Mask Register (7400 and up) */
++
++/* MMCR0 layout (74xx terminology) */
++#define MMCR0_FC 0x80000000 /* Freeze counters unconditionally. */
++#define MMCR0_FCS 0x40000000 /* Freeze counters while MSR[PR]=0 (supervisor mode). */
++#define MMCR0_FCP 0x20000000 /* Freeze counters while MSR[PR]=1 (user mode). */
++#define MMCR0_FCM1 0x10000000 /* Freeze counters while MSR[PM]=1. */
++#define MMCR0_FCM0 0x08000000 /* Freeze counters while MSR[PM]=0. */
++#define MMCR0_PMXE 0x04000000 /* Enable performance monitor exceptions.
++ * Cleared by hardware when a PM exception occurs.
++ * 604: PMXE is not cleared by hardware.
++ */
++#define MMCR0_FCECE 0x02000000 /* Freeze counters on enabled condition or event.
++ * FCECE is treated as 0 if TRIGGER is 1.
++ * 74xx: FC is set when the event occurs.
++ * 604/750: ineffective when PMXE=0.
++ */
++#define MMCR0_TBSEL 0x01800000 /* Time base lower (TBL) bit selector.
++ * 00: bit 31, 01: bit 23, 10: bit 19, 11: bit 15.
++ */
++#define MMCR0_TBEE 0x00400000 /* Enable event on TBL bit transition from 0 to 1. */
++#define MMCR0_THRESHOLD 0x003F0000 /* Threshold value for certain events. */
++#define MMCR0_PMC1CE 0x00008000 /* Enable event on PMC1 overflow. */
++#define MMCR0_PMCjCE 0x00004000 /* Enable event on PMC2-PMC6 overflow.
++ * 604/750: Overrides FCECE (DISCOUNT).
++ */
++#define MMCR0_TRIGGER 0x00002000 /* Disable PMC2-PMC6 until PMC1 overflow or other event.
++ * 74xx: cleared by hardware when the event occurs.
++ */
++#define MMCR0_PMC1SEL 0x00001FC0 /* PMC1 event selector, 7 bits. */
++#define MMCR0_PMC2SEL 0x0000003F /* PMC2 event selector, 6 bits. */
++
++/* MMCR1 layout (604e-7457) */
++#define MMCR1_PMC3SEL 0xF8000000 /* PMC3 event selector, 5 bits. */
++#define MMCR1_PMC4SEL 0x07C00000 /* PMC4 event selector, 5 bits. */
++#define MMCR1_PMC5SEL 0x003E0000 /* PMC5 event selector, 5 bits. (745x only) */
++#define MMCR1_PMC6SEL 0x0001F800 /* PMC6 event selector, 6 bits. (745x only) */
++#define MMCR1__RESERVED 0x000007FF /* should be zero */
++
++/* MMCR2 layout (7400-7457) */
++#define MMCR2_THRESHMULT 0x80000000 /* MMCR0[THRESHOLD] multiplier. */
++#define MMCR2_SMCNTEN 0x40000000 /* 7400/7410 only, should be zero. */
++#define MMCR2_SMINTEN 0x20000000 /* 7400/7410 only, should be zero. */
++#define MMCR2__RESERVED 0x1FFFFFFF /* should be zero */
++#define MMCR2_RESERVED (MMCR2_SMCNTEN | MMCR2_SMINTEN | MMCR2__RESERVED)
++
+ #endif
+
+ /*
+diff -rupN linux-2.6.18-rc4/include/asm-powerpc/systbl.h linux-2.6.18-rc4.perfctr27/include/asm-powerpc/systbl.h
+--- linux-2.6.18-rc4/include/asm-powerpc/systbl.h 2006-08-11 01:34:35.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/include/asm-powerpc/systbl.h 2006-08-11 02:29:29.000000000 +0200
+@@ -304,3 +304,7 @@ SYSCALL_SPU(fchmodat)
+ SYSCALL_SPU(faccessat)
+ COMPAT_SYS_SPU(get_robust_list)
+ COMPAT_SYS_SPU(set_robust_list)
++SYSCALL(vperfctr_open)
++SYSCALL(vperfctr_control)
++SYSCALL(vperfctr_write)
++SYSCALL(vperfctr_read)
+diff -rupN linux-2.6.18-rc4/include/asm-powerpc/unistd.h linux-2.6.18-rc4.perfctr27/include/asm-powerpc/unistd.h
+--- linux-2.6.18-rc4/include/asm-powerpc/unistd.h 2006-08-11 01:34:35.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/include/asm-powerpc/unistd.h 2006-08-11 02:29:29.000000000 +0200
+@@ -323,10 +323,14 @@
+ #define __NR_faccessat 298
+ #define __NR_get_robust_list 299
+ #define __NR_set_robust_list 300
++#define __NR_vperfctr_open 301
++#define __NR_vperfctr_control (__NR_vperfctr_open+1)
++#define __NR_vperfctr_write (__NR_vperfctr_open+2)
++#define __NR_vperfctr_read (__NR_vperfctr_open+3)
+
+ #ifdef __KERNEL__
+
+-#define __NR_syscalls 301
++#define __NR_syscalls 305
+
+ #define __NR__exit __NR_exit
+ #define NR_syscalls __NR_syscalls
+diff -rupN linux-2.6.18-rc4/include/asm-x86_64/hw_irq.h linux-2.6.18-rc4.perfctr27/include/asm-x86_64/hw_irq.h
+--- linux-2.6.18-rc4/include/asm-x86_64/hw_irq.h 2006-08-11 01:34:35.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/include/asm-x86_64/hw_irq.h 2006-08-11 02:29:29.000000000 +0200
+@@ -64,14 +64,15 @@ struct hw_interrupt_type;
+ * sources per level' errata.
+ */
+ #define LOCAL_TIMER_VECTOR 0xef
++#define LOCAL_PERFCTR_VECTOR 0xee
+
+ /*
+- * First APIC vector available to drivers: (vectors 0x30-0xee)
++ * First APIC vector available to drivers: (vectors 0x30-0xed)
+ * we start at 0x31 to spread out vectors evenly between priority
+ * levels. (0x80 is the syscall vector)
+ */
+ #define FIRST_DEVICE_VECTOR 0x31
+-#define FIRST_SYSTEM_VECTOR 0xef /* duplicated in irq.h */
++#define FIRST_SYSTEM_VECTOR 0xee /* duplicated in irq.h */
+
+
+ #ifndef __ASSEMBLY__
+diff -rupN linux-2.6.18-rc4/include/asm-x86_64/irq.h linux-2.6.18-rc4.perfctr27/include/asm-x86_64/irq.h
+--- linux-2.6.18-rc4/include/asm-x86_64/irq.h 2006-03-20 10:40:11.000000000 +0100
++++ linux-2.6.18-rc4.perfctr27/include/asm-x86_64/irq.h 2006-08-11 02:29:29.000000000 +0200
+@@ -29,7 +29,7 @@
+ */
+ #define NR_VECTORS 256
+
+-#define FIRST_SYSTEM_VECTOR 0xef /* duplicated in hw_irq.h */
++#define FIRST_SYSTEM_VECTOR 0xee /* duplicated in hw_irq.h */
+
+ #ifdef CONFIG_PCI_MSI
+ #define NR_IRQS FIRST_SYSTEM_VECTOR
+diff -rupN linux-2.6.18-rc4/include/asm-x86_64/processor.h linux-2.6.18-rc4.perfctr27/include/asm-x86_64/processor.h
+--- linux-2.6.18-rc4/include/asm-x86_64/processor.h 2006-08-11 01:34:35.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/include/asm-x86_64/processor.h 2006-08-11 02:29:29.000000000 +0200
+@@ -268,6 +268,8 @@ struct thread_struct {
+ unsigned io_bitmap_max;
+ /* cached TLS descriptors. */
+ u64 tls_array[GDT_ENTRY_TLS_ENTRIES];
++/* performance counters */
++ struct vperfctr *perfctr;
+ } __attribute__((aligned(16)));
+
+ #define INIT_THREAD { \
+diff -rupN linux-2.6.18-rc4/include/asm-x86_64/system.h linux-2.6.18-rc4.perfctr27/include/asm-x86_64/system.h
+--- linux-2.6.18-rc4/include/asm-x86_64/system.h 2006-08-11 01:34:35.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/include/asm-x86_64/system.h 2006-08-11 02:29:29.000000000 +0200
+@@ -20,7 +20,8 @@
+ #define __EXTRA_CLOBBER \
+ ,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
+
+-#define switch_to(prev,next,last) \
++#define switch_to(prev,next,last) do { \
++ perfctr_suspend_thread(&(prev)->thread); \
+ asm volatile(SAVE_CONTEXT \
+ "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */ \
+ "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */ \
+@@ -40,7 +41,8 @@
+ [tif_fork] "i" (TIF_FORK), \
+ [thread_info] "i" (offsetof(struct task_struct, thread_info)), \
+ [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent)) \
+- : "memory", "cc" __EXTRA_CLOBBER)
++ : "memory", "cc" __EXTRA_CLOBBER); \
++} while (0)
+
+ extern void load_gs_index(unsigned);
+
+diff -rupN linux-2.6.18-rc4/include/asm-x86_64/unistd.h linux-2.6.18-rc4.perfctr27/include/asm-x86_64/unistd.h
+--- linux-2.6.18-rc4/include/asm-x86_64/unistd.h 2006-08-11 01:34:35.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/include/asm-x86_64/unistd.h 2006-08-11 02:29:29.000000000 +0200
+@@ -619,10 +619,18 @@ __SYSCALL(__NR_sync_file_range, sys_sync
+ __SYSCALL(__NR_vmsplice, sys_vmsplice)
+ #define __NR_move_pages 279
+ __SYSCALL(__NR_move_pages, sys_move_pages)
++#define __NR_vperfctr_open 280
++__SYSCALL(__NR_vperfctr_open, sys_vperfctr_open)
++#define __NR_vperfctr_control (__NR_vperfctr_open+1)
++__SYSCALL(__NR_vperfctr_control, sys_vperfctr_control)
++#define __NR_vperfctr_write (__NR_vperfctr_open+2)
++__SYSCALL(__NR_vperfctr_write, sys_vperfctr_write)
++#define __NR_vperfctr_read (__NR_vperfctr_open+3)
++__SYSCALL(__NR_vperfctr_read, sys_vperfctr_read)
+
+ #ifdef __KERNEL__
+
+-#define __NR_syscall_max __NR_move_pages
++#define __NR_syscall_max __NR_vperfctr_read
+
+ #ifndef __NO_STUBS
+
+diff -rupN linux-2.6.18-rc4/include/linux/sched.h linux-2.6.18-rc4.perfctr27/include/linux/sched.h
+--- linux-2.6.18-rc4/include/linux/sched.h 2006-08-11 01:34:36.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/include/linux/sched.h 2006-08-11 02:29:29.000000000 +0200
+@@ -1352,6 +1352,9 @@ static inline int thread_group_empty(str
+ * subscriptions and synchronises with wait4(). Also used in procfs. Also
+ * pins the final release of task.io_context. Also protects ->cpuset.
+ *
++ * Synchronises set_cpus_allowed(), unlink, and creat of ->thread.perfctr.
++ * [if CONFIG_PERFCTR_VIRTUAL]
++ *
+ * Nests both inside and outside of read_lock(&tasklist_lock).
+ * It must not be nested with write_lock_irq(&tasklist_lock),
+ * neither inside nor outside.
+diff -rupN linux-2.6.18-rc4/kernel/exit.c linux-2.6.18-rc4.perfctr27/kernel/exit.c
+--- linux-2.6.18-rc4/kernel/exit.c 2006-08-11 01:34:36.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/kernel/exit.c 2006-08-11 02:29:29.000000000 +0200
+@@ -25,6 +25,7 @@
+ #include <linux/mount.h>
+ #include <linux/proc_fs.h>
+ #include <linux/mempolicy.h>
++#include <linux/perfctr.h>
+ #include <linux/taskstats_kern.h>
+ #include <linux/delayacct.h>
+ #include <linux/cpuset.h>
+@@ -166,6 +167,7 @@ repeat:
+ zap_leader = (leader->exit_signal == -1);
+ }
+
++ perfctr_release_task(p);
+ sched_exit(p);
+ write_unlock_irq(&tasklist_lock);
+ proc_flush_task(p);
+diff -rupN linux-2.6.18-rc4/kernel/sched.c linux-2.6.18-rc4.perfctr27/kernel/sched.c
+--- linux-2.6.18-rc4/kernel/sched.c 2006-08-11 01:34:36.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/kernel/sched.c 2006-08-11 02:29:29.000000000 +0200
+@@ -45,6 +45,7 @@
+ #include <linux/cpu.h>
+ #include <linux/cpuset.h>
+ #include <linux/percpu.h>
++#include <linux/perfctr.h>
+ #include <linux/kthread.h>
+ #include <linux/seq_file.h>
+ #include <linux/syscalls.h>
+@@ -4847,6 +4848,8 @@ int set_cpus_allowed(struct task_struct
+ struct rq *rq;
+ int ret = 0;
+
++ perfctr_set_cpus_allowed(p, new_mask);
++
+ rq = task_rq_lock(p, &flags);
+ if (!cpus_intersects(new_mask, cpu_online_map)) {
+ ret = -EINVAL;
+diff -rupN linux-2.6.18-rc4/kernel/sys_ni.c linux-2.6.18-rc4.perfctr27/kernel/sys_ni.c
+--- linux-2.6.18-rc4/kernel/sys_ni.c 2006-08-11 01:34:36.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/kernel/sys_ni.c 2006-08-11 02:29:29.000000000 +0200
+@@ -72,6 +72,10 @@ cond_syscall(compat_sys_mq_timedsend);
+ cond_syscall(compat_sys_mq_timedreceive);
+ cond_syscall(compat_sys_mq_notify);
+ cond_syscall(compat_sys_mq_getsetattr);
++cond_syscall(sys_vperfctr_open);
++cond_syscall(sys_vperfctr_control);
++cond_syscall(sys_vperfctr_write);
++cond_syscall(sys_vperfctr_read);
+ cond_syscall(sys_mbind);
+ cond_syscall(sys_get_mempolicy);
+ cond_syscall(sys_set_mempolicy);
+diff -rupN linux-2.6.18-rc4/kernel/timer.c linux-2.6.18-rc4.perfctr27/kernel/timer.c
+--- linux-2.6.18-rc4/kernel/timer.c 2006-08-11 01:34:36.000000000 +0200
++++ linux-2.6.18-rc4.perfctr27/kernel/timer.c 2006-08-11 02:29:29.000000000 +0200
+@@ -32,6 +32,7 @@
+ #include <linux/jiffies.h>
+ #include <linux/posix-timers.h>
+ #include <linux/cpu.h>
++#include <linux/perfctr.h>
+ #include <linux/syscalls.h>
+ #include <linux/delay.h>
+
+@@ -1181,6 +1182,7 @@ void update_process_times(int user_tick)
+ account_user_time(p, jiffies_to_cputime(1));
+ else
+ account_system_time(p, HARDIRQ_OFFSET, jiffies_to_cputime(1));
++ perfctr_sample_thread(&p->thread);
+ run_local_timers();
+ if (rcu_pending(cpu))
+ rcu_check_callbacks(cpu, user_tick);
diff --git a/src/perfctr-2.7.x/perfctr.spec b/src/perfctr-2.7.x/perfctr.spec
index 94206643696905f4cc27dcab0ba1067a5b3f55fa..731c24b644db3cf087ecbce4e3e2c86b0d24cf13 100644
--- a/src/perfctr-2.7.x/perfctr.spec
+++ b/src/perfctr-2.7.x/perfctr.spec
@@ -1,10 +1,10 @@
Name: perfctr
Summary: Linux performance monitoring counters software
-Version: 2.7.18
+Version: 2.7.21.1
Release: 1
License: LGPL
Group: Development/Tools
-URL: http://www.csd.uu.se/~mikpe/linux/perfctr/
+URL: http://user.it.uu.se/~mikpe/linux/perfctr/
BuildRoot: %{_tmppath}/%{name}-%{version}-%{release}-buildroot
Source: %{name}-%{version}.tar.gz
@@ -67,8 +67,11 @@ rm -rf %{buildroot}
%changelog
+* Wed Oct 03 2007 Mikael Pettersson <mikpe@it.uu.se> -
+- Corrected email address and URL.
+
* Fri Apr 08 2005 Mikael Pettersson <mikpe@csd.uu.se> -
-* Don't create /dev/perfctr or update /etc/modules.conf.
+- Don't create /dev/perfctr or update /etc/modules.conf.
* Tue Sep 16 2004 Mikael Pettersson <mikpe@csd.uu.se> -
- Dropped obsolete x86 qualification from Summary.
diff --git a/src/perfctr-2.7.x/update-kernel b/src/perfctr-2.7.x/update-kernel
index b217c2c6159e5bafd3f112349a3ad8904f250e78..a362b3b4b43ebf983e5d028a710ae48d32fd29b1 100755
--- a/src/perfctr-2.7.x/update-kernel
+++ b/src/perfctr-2.7.x/update-kernel
@@ -1,5 +1,5 @@
#!/bin/sh
-# $Id$
+# $Id: update-kernel,v 1.14 2006/08/20 19:34:51 mikpe Exp $
# usage:
# cd ${kernelsrcdir}
# ${perfctrsrcdir}/update-kernel
@@ -37,7 +37,7 @@ get_perfctr_srcdir() {
get_arch() {
if [ -z "$ARCH" ]; then
- ARCH=`uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/`
+ ARCH=`uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/ -e s/ppc.*/powerpc/`
fi
}
@@ -193,10 +193,8 @@ install_files_by_symlinks() {
ln -sf ${perfctr}/linux/include/asm-i386/perfctr.h include/asm-i386/
echo ln -sf ${perfctr}/linux/include/asm-x86_64/perfctr.h include/asm-x86_64/
ln -sf ${perfctr}/linux/include/asm-x86_64/perfctr.h include/asm-x86_64/
- echo ln -sf ${perfctr}/linux/include/asm-ppc/perfctr.h include/asm-ppc/
- ln -sf ${perfctr}/linux/include/asm-ppc/perfctr.h include/asm-ppc/
- echo ln -sf ${perfctr}/linux/include/asm-ppc64/perfctr.h include/asm-ppc64/
- ln -sf ${perfctr}/linux/include/asm-ppc64/perfctr.h include/asm-ppc64/
+ echo ln -sf ${perfctr}/linux/include/asm-powerpc/perfctr.h include/asm-powerpc/
+ ln -sf ${perfctr}/linux/include/asm-powerpc/perfctr.h include/asm-powerpc/
echo ln -sf ${perfctr}/linux/include/linux/perfctr.h include/linux/
ln -sf ${perfctr}/linux/include/linux/perfctr.h include/linux/
echo ln -sf ${perfctr}/linux/drivers/perfctr drivers/
diff --git a/src/perfctr-2.7.x/usr.lib/Makefile b/src/perfctr-2.7.x/usr.lib/Makefile
index 9e3dc0d476ff7bf179ec2ea72764b61e8710d8cb..d73e7ccfcc0015a6449bb41c0d9a98c0500ad1bf 100644
--- a/src/perfctr-2.7.x/usr.lib/Makefile
+++ b/src/perfctr-2.7.x/usr.lib/Makefile
@@ -1,4 +1,4 @@
-# $Id$
+# $Id: Makefile,v 1.60 2007/10/06 13:02:07 mikpe Exp $
SHELL=/bin/sh
ARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/)
@@ -37,7 +37,7 @@ AR_OBJS=misc.o virtual.o $(EVENT_SET_OBJS) $(ARCH_OBJS)
SO_OBJS=$(AR_OBJS:.o=.os)
SO_ABIVER=6
-SO_LIBVER=2.7.18
+SO_LIBVER=2.7.21.1
SO_NAME=libperfctr.so.$(SO_ABIVER)
SO_LIB=libperfctr.so.$(SO_ABIVER).$(SO_LIBVER)
@@ -45,8 +45,8 @@ HDEP=libperfctr.h $(BUILD_INCLDIR)/linux/perfctr.h $(BUILD_INCLDIR)/asm/perfctr.
i386_ASM_DIR=i386
x86_64_ASM_DIR=i386
-ppc_ASM_DIR=ppc
-ppc64_ASM_DIR=ppc64
+ppc_ASM_DIR=powerpc
+ppc64_ASM_DIR=powerpc
ARCH_ASM_DIR=asm-$($(ARCH)_ASM_DIR)
INSTALL_FILES=$(BUILD_INCLDIR)/$(ARCH_ASM_DIR)/perfctr.h $(BUILD_INCLDIR)/linux/perfctr.h\
diff --git a/src/perfctr-2.7.x/usr.lib/arch.h b/src/perfctr-2.7.x/usr.lib/arch.h
index 5a8e5cd37a83a532408d71fffc9f11e817a251b7..b722aeed4767bc906b79401181bbf1419d3afa21 100644
--- a/src/perfctr-2.7.x/usr.lib/arch.h
+++ b/src/perfctr-2.7.x/usr.lib/arch.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: arch.h,v 1.2 2005/03/23 02:02:54 mikpe Exp $
* Architecture-specific code for performance counters library.
*
* Copyright (C) 2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/usr.lib/event_set.h b/src/perfctr-2.7.x/usr.lib/event_set.h
index 2661495b1bb986b554fe84e3afb506e2ef48cdf6..3bc2d96b5ffc56be77beab9416ab04994aa42349 100644
--- a/src/perfctr-2.7.x/usr.lib/event_set.h
+++ b/src/perfctr-2.7.x/usr.lib/event_set.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: event_set.h,v 1.5 2004/02/20 21:32:06 mikpe Exp $
* Common definitions used when creating event set descriptions.
*
* Copyright (C) 2003-2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/usr.lib/event_set_amd.c b/src/perfctr-2.7.x/usr.lib/event_set_amd.c
index f67b56ce9a6a60085dc70cadd6811af5b9096cdb..d298e8a7a79ab8a808775c0bd43dfbdcb40ccc98 100644
--- a/src/perfctr-2.7.x/usr.lib/event_set_amd.c
+++ b/src/perfctr-2.7.x/usr.lib/event_set_amd.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: event_set_amd.c,v 1.9 2004/07/17 00:41:57 mikpe Exp $
* Performance counter event descriptions for AMD K7 and K8.
*
* Copyright (C) 2003 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/usr.lib/event_set_centaur.c b/src/perfctr-2.7.x/usr.lib/event_set_centaur.c
index c751e3b1d0099db27b57879b92d7d777e5d7891a..8405309059707fcab6ce944a8cf664bd90373ea0 100644
--- a/src/perfctr-2.7.x/usr.lib/event_set_centaur.c
+++ b/src/perfctr-2.7.x/usr.lib/event_set_centaur.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: event_set_centaur.c,v 1.1 2003/02/16 21:08:54 mikpe Exp $
* Performance counter event descriptions for Centaur chips:
* IDT WinChip C6/2/3 and VIA C3.
*
diff --git a/src/perfctr-2.7.x/usr.lib/event_set_p4.c b/src/perfctr-2.7.x/usr.lib/event_set_p4.c
index 139d9b92c7f5564ec27ce132af543444e0818a97..97650ff07bf6da9bfaaf6a24489b924713ba0d42 100644
--- a/src/perfctr-2.7.x/usr.lib/event_set_p4.c
+++ b/src/perfctr-2.7.x/usr.lib/event_set_p4.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: event_set_p4.c,v 1.5 2004/02/20 21:32:06 mikpe Exp $
* Performance counter event descriptions for Intel P4.
*
* Copyright (C) 2003-2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/usr.lib/event_set_p5.c b/src/perfctr-2.7.x/usr.lib/event_set_p5.c
index c328d70228a5e2a249933284844df08197a73789..80f8939211af474c745a9c9860db273568e897ad 100644
--- a/src/perfctr-2.7.x/usr.lib/event_set_p5.c
+++ b/src/perfctr-2.7.x/usr.lib/event_set_p5.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: event_set_p5.c,v 1.1 2003/02/16 21:08:54 mikpe Exp $
* Performance counter event descriptions for Intel P5 and P5 MMX
* processors, and Cyrix 6x86/MII/III processors.
*
diff --git a/src/perfctr-2.7.x/usr.lib/event_set_p6.c b/src/perfctr-2.7.x/usr.lib/event_set_p6.c
index 1a2f4175cdc3191c1d065f7af0ed2b814decfaf1..59645839de2199a71f276c451fef954950f536ef 100644
--- a/src/perfctr-2.7.x/usr.lib/event_set_p6.c
+++ b/src/perfctr-2.7.x/usr.lib/event_set_p6.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: event_set_p6.c,v 1.5 2004/05/02 21:45:47 mikpe Exp $
* Performance counter event descriptions for the Intel P6 family.
*
* Copyright (C) 2003-2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/usr.lib/event_set_ppc.c b/src/perfctr-2.7.x/usr.lib/event_set_ppc.c
index e824693b7e846791eb13642f50a1360e28e7a724..cdf73de3855895d29333df32fdf71b8133cf3dc4 100644
--- a/src/perfctr-2.7.x/usr.lib/event_set_ppc.c
+++ b/src/perfctr-2.7.x/usr.lib/event_set_ppc.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: event_set_ppc.c,v 1.3 2004/05/29 11:41:52 mikpe Exp $
* Descriptions of the events available for different processor types.
*
* Copyright (C) 2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/usr.lib/event_set_ppc64.c b/src/perfctr-2.7.x/usr.lib/event_set_ppc64.c
index 44f2f0f287fe9ce31cbd31a24419f8c31d62671b..07e76538409ac64246f1beaae13593fb22818701 100644
--- a/src/perfctr-2.7.x/usr.lib/event_set_ppc64.c
+++ b/src/perfctr-2.7.x/usr.lib/event_set_ppc64.c
@@ -41,6 +41,7 @@ static const struct perfctr_event_set * const cpu_event_set[] = {
[PERFCTR_PPC64_POWER4] = &ppc64_common_event_set,
[PERFCTR_PPC64_POWER4p] = &ppc64_common_event_set,
[PERFCTR_PPC64_970] = &ppc64_common_event_set,
+ [PERFCTR_PPC64_970MP] = &ppc64_common_event_set,
// [PERFCTR_PPC_604e] = &perfctr_ppc604e_event_set,
// [PERFCTR_PPC_750] = &perfctr_ppc750_event_set,
};
diff --git a/src/perfctr-2.7.x/usr.lib/event_set_x86.c b/src/perfctr-2.7.x/usr.lib/event_set_x86.c
index b28685ac529a4eb9e765e492a6001bee50a8a1fc..e35e6174cd2f7938e234111270c3c3fa7b4415ba 100644
--- a/src/perfctr-2.7.x/usr.lib/event_set_x86.c
+++ b/src/perfctr-2.7.x/usr.lib/event_set_x86.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: event_set_x86.c,v 1.3 2004/08/02 14:36:10 mikpe Exp $
* Descriptions of the events available for different processor types.
*
* Copyright (C) 1999-2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/usr.lib/gen-event-codes.c b/src/perfctr-2.7.x/usr.lib/gen-event-codes.c
index 6815c7033bcad38da04530582425989a7f5e8fec..3d0e32430534223822ce1a4aefb90b47782259bc 100644
--- a/src/perfctr-2.7.x/usr.lib/gen-event-codes.c
+++ b/src/perfctr-2.7.x/usr.lib/gen-event-codes.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: gen-event-codes.c,v 1.9 2005/03/23 02:02:54 mikpe Exp $
*
* Generate symbolic constants for performance counter events.
*
diff --git a/src/perfctr-2.7.x/usr.lib/global.c b/src/perfctr-2.7.x/usr.lib/global.c
index 89122a0c53fe7c176b6f49d44722a0371066aa25..1288568cd5ba651d7a590773d832e2ccdddf4e47 100644
--- a/src/perfctr-2.7.x/usr.lib/global.c
+++ b/src/perfctr-2.7.x/usr.lib/global.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: global.c,v 1.11 2004/05/13 23:35:27 mikpe Exp $
* Library interface to global-mode performance counters.
*
* Copyright (C) 1999-2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/usr.lib/libperfctr.h b/src/perfctr-2.7.x/usr.lib/libperfctr.h
index e755783ae298ec309d1693e76b2d3a824d25d015..0792ace79c07a903d61dfdd6748dfe25a742a250 100644
--- a/src/perfctr-2.7.x/usr.lib/libperfctr.h
+++ b/src/perfctr-2.7.x/usr.lib/libperfctr.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: libperfctr.h,v 1.50 2007/10/06 13:02:07 mikpe Exp $
* Library interface to Linux Performance-Monitoring Counters.
*
* Copyright (C) 1999-2007 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/usr.lib/misc.c b/src/perfctr-2.7.x/usr.lib/misc.c
index 933ce4f73cf1f6de923125020880094f787b5234..19a0ea705ffaf79dea5bcff05093a8dcaca9ec48 100644
--- a/src/perfctr-2.7.x/usr.lib/misc.c
+++ b/src/perfctr-2.7.x/usr.lib/misc.c
@@ -1,13 +1,15 @@
-/* $Id$
+/* $Id: misc.c,v 1.26 2006/08/27 07:34:41 mikpe Exp $
* Miscellaneous perfctr operations.
*
* Copyright (C) 1999-2004 Mikael Pettersson
*/
+#include <sys/utsname.h>
#include <errno.h>
#include <stddef.h>
#include <stdio.h>
#include <stdlib.h>
+#include <string.h>
#include "libperfctr.h"
#include "arch.h"
@@ -224,3 +226,19 @@ void perfctr_cpus_info_print(const struct perfctr_cpus_info *info)
printf("cpus\t\t\t"); print_cpus(info->cpus);
printf("cpus_forbidden\t\t"); print_cpus(info->cpus_forbidden);
}
+
+unsigned int perfctr_linux_version_code(void)
+{
+ struct utsname utsname;
+ unsigned int version, patchlevel, sublevel;
+
+ if (uname(&utsname) < 0) {
+ fprintf(stderr, "uname: %s\n", strerror(errno));
+ return 0;
+ }
+ if (sscanf(utsname.release, "%u.%u.%u", &version, &patchlevel, &sublevel) != 3) {
+ fprintf(stderr, "uname: unexpected release '%s'\n", utsname.release);
+ return 0;
+ }
+ return PERFCTR_KERNEL_VERSION(version,patchlevel,sublevel);
+}
diff --git a/src/perfctr-2.7.x/usr.lib/ppc.c b/src/perfctr-2.7.x/usr.lib/ppc.c
index 2bd4efb68e14dd754abf206604b4c26c7ac84dc8..9cbc089c837e004f7f3170c8865b68f5375c5f8a 100644
--- a/src/perfctr-2.7.x/usr.lib/ppc.c
+++ b/src/perfctr-2.7.x/usr.lib/ppc.c
@@ -1,7 +1,7 @@
-/* $Id$
+/* $Id: ppc.c,v 1.20 2007/10/06 13:02:07 mikpe Exp $
* PPC32-specific perfctr library procedures.
*
- * Copyright (C) 2004-2005 Mikael Pettersson
+ * Copyright (C) 2004-2007 Mikael Pettersson
*/
#include <errno.h>
#include <asm/unistd.h>
@@ -10,36 +10,54 @@
#include "libperfctr.h"
#include "ppc.h"
-#ifndef __NR_vperfctr_open
-#define __NR_vperfctr_open 275
+static unsigned int __NR_vperfctr_open;
#define __NR_vperfctr_control (__NR_vperfctr_open+1)
#define __NR_vperfctr_write (__NR_vperfctr_open+2)
#define __NR_vperfctr_read (__NR_vperfctr_open+3)
-#endif
#include <unistd.h>
+static void init_sys_vperfctr(void)
+{
+ if (!__NR_vperfctr_open) {
+ unsigned int nr;
+ unsigned int kver = perfctr_linux_version_code();
+
+ if (kver >= PERFCTR_KERNEL_VERSION(2,6,18))
+ nr = 310;
+ else if (kver >= PERFCTR_KERNEL_VERSION(2,6,16))
+ nr = 301;
+ else
+ nr = 280;
+ __NR_vperfctr_open = nr;
+ }
+}
+
/*
* The actual syscalls.
*/
int _sys_vperfctr_open(int fd_unused, int tid, int creat)
{
+ init_sys_vperfctr();
return syscall(__NR_vperfctr_open, tid, creat);
}
static int _sys_vperfctr_control(int fd, unsigned int cmd)
{
+ init_sys_vperfctr();
return syscall(__NR_vperfctr_control, fd, cmd);
}
static int _sys_vperfctr_write(int fd, unsigned int domain, const void *arg, unsigned int argbytes)
{
+ init_sys_vperfctr();
return syscall(__NR_vperfctr_write, fd, domain, arg, argbytes);
}
static int _sys_vperfctr_read(int fd, unsigned int domain, void *arg, unsigned int argbytes)
{
+ init_sys_vperfctr();
return syscall(__NR_vperfctr_read, fd, domain, arg, argbytes);
}
@@ -81,7 +99,7 @@ int _sys_vperfctr_iresume(int fd)
#define SPRN_PMC5 0x3B1 /* Performance Counter Register 5 (7450 and up) */
#define SPRN_PMC6 0x3B2 /* Performance Counter Register 6 (7450 and up) */
-#define MMCR0_PMC1SEL 0x00001FB0 /* PMC1 event selector, 7 bits. */
+#define MMCR0_PMC1SEL 0x00001FC0 /* PMC1 event selector, 7 bits. */
#define MMCR0_PMC2SEL 0x0000003F /* PMC2 event selector, 6 bits. */
#if 0
diff --git a/src/perfctr-2.7.x/usr.lib/ppc.h b/src/perfctr-2.7.x/usr.lib/ppc.h
index 8ad86da8c3c3bc057fa0ed3007d3c45ad3b60aae..8f1884ebd76b9be10bfb9fa81eccd36d992fd614 100644
--- a/src/perfctr-2.7.x/usr.lib/ppc.h
+++ b/src/perfctr-2.7.x/usr.lib/ppc.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: ppc.h,v 1.2 2005/04/09 10:25:47 mikpe Exp $
* PPC32-specific code for performance counters library.
*
* Copyright (C) 2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/usr.lib/virtual.c b/src/perfctr-2.7.x/usr.lib/virtual.c
index d9e3998f84fb7192c95a28a8c6ad3c7da626a410..7413316229d9fffa5cb1f5dc317cdce9829504dd 100644
--- a/src/perfctr-2.7.x/usr.lib/virtual.c
+++ b/src/perfctr-2.7.x/usr.lib/virtual.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: virtual.c,v 1.35 2005/06/06 21:07:58 mikpe Exp $
* Library interface to virtual per-process performance counters.
*
* Copyright (C) 1999-2005 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/usr.lib/x86.c b/src/perfctr-2.7.x/usr.lib/x86.c
index 6473a07ee0176898ce40e730a04f72b1a1ffd41b..ed571f310150386857ae0002dc793b08de7867b7 100644
--- a/src/perfctr-2.7.x/usr.lib/x86.c
+++ b/src/perfctr-2.7.x/usr.lib/x86.c
@@ -1,7 +1,7 @@
-/* $Id$
+/* $Id: x86.c,v 1.23 2007/10/06 13:02:07 mikpe Exp $
* x86-specific perfctr library procedures.
*
- * Copyright (C) 1999-2005 Mikael Pettersson
+ * Copyright (C) 1999-2007 Mikael Pettersson
*/
#include <errno.h>
#include <asm/unistd.h>
@@ -11,40 +11,63 @@
#include "x86.h"
#include "x86_cpuinfo.h"
-#ifndef __NR_vperfctr_open
-#ifdef __x86_64__
-#define __NR_vperfctr_open 253
-#else
-#define __NR_vperfctr_open 291
-#endif
+static unsigned int __NR_vperfctr_open;
#define __NR_vperfctr_control (__NR_vperfctr_open+1)
#define __NR_vperfctr_write (__NR_vperfctr_open+2)
#define __NR_vperfctr_read (__NR_vperfctr_open+3)
-#endif
#include <unistd.h>
+static void init_sys_vperfctr(void)
+{
+ if (!__NR_vperfctr_open) {
+ unsigned int nr;
+ unsigned int kver = perfctr_linux_version_code();
+
+#if defined(__x86_64__)
+ if (kver >= PERFCTR_KERNEL_VERSION(2,6,18))
+ nr = 286;
+ else if (kver >= PERFCTR_KERNEL_VERSION(2,6,16))
+ nr = 280;
+ else
+ nr = 257;
+#elif defined(__i386__)
+ if (kver >= PERFCTR_KERNEL_VERSION(2,6,18))
+ nr = 325;
+ else if (kver >= PERFCTR_KERNEL_VERSION(2,6,16))
+ nr = 318;
+ else
+ nr = 296;
+#endif
+ __NR_vperfctr_open = nr;
+ }
+}
+
/*
* The actual syscalls.
*/
int _sys_vperfctr_open(int fd_unused, int tid, int creat)
{
+ init_sys_vperfctr();
return syscall(__NR_vperfctr_open, tid, creat);
}
static int _sys_vperfctr_control(int fd, unsigned int cmd)
{
+ init_sys_vperfctr();
return syscall(__NR_vperfctr_control, fd, cmd);
}
static int _sys_vperfctr_write(int fd, unsigned int domain, const void *arg, unsigned int argbytes)
{
+ init_sys_vperfctr();
return syscall(__NR_vperfctr_write, fd, domain, arg, argbytes);
}
static int _sys_vperfctr_read(int fd, unsigned int domain, void *arg, unsigned int argbytes)
{
+ init_sys_vperfctr();
return syscall(__NR_vperfctr_read, fd, domain, arg, argbytes);
}
diff --git a/src/perfctr-2.7.x/usr.lib/x86.h b/src/perfctr-2.7.x/usr.lib/x86.h
index 11dae47b6c506d495f3fb16a5d72dcec294cb417..d533b6a34c101b5457ca6465b46899b1e92ecbca 100644
--- a/src/perfctr-2.7.x/usr.lib/x86.h
+++ b/src/perfctr-2.7.x/usr.lib/x86.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: x86.h,v 1.3 2005/04/09 10:25:47 mikpe Exp $
* x86-specific code for performance counters library.
*
* Copyright (C) 1999-2004 Mikael Pettersson
diff --git a/src/perfctr-2.7.x/usr.lib/x86_cpuinfo.c b/src/perfctr-2.7.x/usr.lib/x86_cpuinfo.c
index df1f960fe0e34e6161d1df869e3f8ac74222d422..a37712b4b95be379a96f0986b0189c3368bff7b2 100644
--- a/src/perfctr-2.7.x/usr.lib/x86_cpuinfo.c
+++ b/src/perfctr-2.7.x/usr.lib/x86_cpuinfo.c
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: x86_cpuinfo.c,v 1.1 2004/05/22 20:59:58 mikpe Exp $
* Copyright (C) 2004 Mikael Pettersson
*/
#include <string.h>
diff --git a/src/perfctr-2.7.x/usr.lib/x86_cpuinfo.h b/src/perfctr-2.7.x/usr.lib/x86_cpuinfo.h
index bccef1cae54eed43fbe96165109ddca8bf4924c8..f39d5c3bb83cfcd347863fe9edb7d96dad635974 100644
--- a/src/perfctr-2.7.x/usr.lib/x86_cpuinfo.h
+++ b/src/perfctr-2.7.x/usr.lib/x86_cpuinfo.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: x86_cpuinfo.h,v 1.1 2004/05/22 20:59:58 mikpe Exp $
* Copyright (C) 2004 Mikael Pettersson
*/