diff --git a/src/uart-transmit/esp32-c3-uart-interface.c b/src/uart-transmit/esp32-c3-uart-interface.c
index a5ec44ef947ae1972666fcb1459f6034fb372524..39f53a1630595711eebbd79b7bdc5b3486973d22 100644
--- a/src/uart-transmit/esp32-c3-uart-interface.c
+++ b/src/uart-transmit/esp32-c3-uart-interface.c
@@ -1,46 +1,52 @@
#include "esp32-c3-uart-interface.h"
+static void clearBits(volatile uint32_t *registerAddress, uint32_t bitPositions, uint32_t numBits) {
+ uint32_t mask = (uint32_t)(1 << numBits) - 1; // Create a mask with the specified number of bits set to 1
+ mask <<= bitPositions; // Shift the mask to the correct bit positions
+ *registerAddress &= ~mask; // Clear the bits in the register using bitwise AND with the inverse of the mask
+}
+
static void init_uart_enable_clk(){
// enable the clock for UART RAM by setting SYSTEM_UART_MEM_CLK_EN to 1;
// enable APB_CLK for UARTn by setting SYSTEM_UARTn_CLK_EN to 1;
- uint32_t perip_clk_en0_reg = *C3_SYSTEM_PERIP_CLK_EN0_REG;
- perip_clk_en0_reg |= 1<<24;
- perip_clk_en0_reg |= 1<<5;
- perip_clk_en0_reg |= 1<<2;
- *C3_SYSTEM_PERIP_CLK_EN0_REG = perip_clk_en0_reg;
+ uint32_t perip_clk_en0 = *C3_SYSTEM_PERIP_CLK_EN0_REG;
+ perip_clk_en0 |= 1<<24;
+ perip_clk_en0 |= 1<<5;
+ perip_clk_en0 |= 1<<2;
+ *C3_SYSTEM_PERIP_CLK_EN0_REG = perip_clk_en0;
}
static void init_uart_toggle_rst(){
// Detailed steps explained in 26.5.2.1
// for resetting and initilizing of uart
// get current regestry values
- uint32_t rx_filt_reg = *C3_UART_RX_FILT_REG;
- uint32_t core_value = *C3_UART_CLK_CONF_REG;
+ uint32_t rx_filt = *C3_UART_RX_FILT_REG_UART0;
+ uint32_t core_value = *C3_UART_CLK_CONF_REG_UART0;
// clear UARTn_RST
- rx_filt_reg &= (uint32_t)~(1<<5);
- rx_filt_reg &= (uint32_t)~(1<<2);
- *C3_UART_RX_FILT_REG = rx_filt_reg;
+ rx_filt &= (uint32_t)~(1<<5);
+ rx_filt &= (uint32_t)~(1<<2);
+ *C3_UART_RX_FILT_REG_UART0 = rx_filt;
// set UART_RST_CORE
core_value |= 1<<23;
- *C3_UART_CLK_CONF_REG = core_value;
+ *C3_UART_CLK_CONF_REG_UART0 = core_value;
// set UARTn_RST
- rx_filt_reg |= 1<<5;
- rx_filt_reg |= 1<<2;
- *C3_UART_RX_FILT_REG = rx_filt_reg;
+ rx_filt |= 1<<5;
+ rx_filt |= 1<<2;
+ *C3_UART_RX_FILT_REG_UART0 = rx_filt;
// clear UARTn_RST
- rx_filt_reg &= (uint32_t)~(1<<5);
- rx_filt_reg &= (uint32_t)~(1<<2);
- *C3_UART_RX_FILT_REG = rx_filt_reg;
+ rx_filt &= (uint32_t)~(1<<5);
+ rx_filt &= (uint32_t)~(1<<2);
+ *C3_UART_RX_FILT_REG_UART0 = rx_filt;
// clear UART_RST_CORE
core_value &= (uint32_t)~(1<<23);
- *C3_UART_CLK_CONF_REG = core_value;
+ *C3_UART_CLK_CONF_REG_UART0 = core_value;
}
static void init_uart_clear_update(){
// enable register synchronization by clearing UART_UPDATE_CTRL.
- uint32_t id_value = *C3_UART_ID_REG;
+ uint32_t id_value = *C3_UART_ID_REG_UART0;
id_value &= (uint32_t)~(1<<30);
- *C3_UART_ID_REG = id_value;
+ *C3_UART_ID_REG_UART0 = id_value;
}
static void config_clock_freq(){
@@ -48,7 +54,7 @@ static void config_clock_freq(){
// baud rate = freq / (UART_CLKDIV + UART_CLKDIV_FRAG / 16)
// select the clock source via UART_SCLK_SEL;
- uint32_t clockSelect = *C3_UART_CLK_CONF_REG;
+ uint32_t clockSelect = *C3_UART_CLK_CONF_REG_UART0;
// making sure we start with 0
clockSelect &= (uint32_t)~(1<<20);
clockSelect &= (uint32_t)~(1<<21);
@@ -56,7 +62,7 @@ static void config_clock_freq(){
// 10 is RC_FAST_CLK with default of 17.5 MHz
// 11 is XTAL_CLK with 40 MHz
clockSelect |= 1<<20;
- *C3_UART_CLK_CONF_REG = clockSelect;
+ *C3_UART_CLK_CONF_REG_UART0 = clockSelect;
// selected ABP_CLK with 80 MHz
// dividing clock to 6 Mhz (divisor should be 13+1/3)
@@ -72,36 +78,36 @@ static void config_clock_freq(){
clockSelect |= 1<<1;
clockSelect |= 1<<0;
- *C3_UART_CLK_CONF_REG = clockSelect;
+ *C3_UART_CLK_CONF_REG_UART0 = clockSelect;
// calculate Baud rate to be 9600 (6Mhz/625)
- uint32_t baudRateDivs = *C3_UART_CLKDIV_REG;
+ uint32_t baudRateDivs = *C3_UART_CLKDIV_REG_UART0;
baudRateDivs |= 1<<0;
baudRateDivs |= 1<<4;
baudRateDivs |= 1<<5;
baudRateDivs |= 1<<6;
baudRateDivs |= 1<<9;
- *C3_UART_CLKDIV_REG = baudRateDivs;
+ *C3_UART_CLKDIV_REG_UART0 = baudRateDivs;
}
static void disable_parity(){
- uint32_t uart_conf_reg = *C3_UART_CONF0_REG;
- uart_conf_reg &= (uint32_t)~(1<<0);
- uart_conf_reg &= (uint32_t)~(1<<1);
- *C3_UART_CONF0_REG = uart_conf_reg;
+ uint32_t uart_conf = *C3_UART_CONF0_REG_UART0;
+ uart_conf &= (uint32_t)~(1<<0);
+ uart_conf &= (uint32_t)~(1<<1);
+ *C3_UART_CONF0_REG_UART0 = uart_conf;
}
static void set_max_data_lenght(){
- uint32_t uart_conf_reg = *C3_UART_CONF0_REG;
- uart_conf_reg |= (1<<2);
- uart_conf_reg |= (1<<3);
- *C3_UART_CONF0_REG = uart_conf_reg;
+ uint32_t uart_conf = *C3_UART_CONF0_REG_UART0;
+ uart_conf |= (1<<2);
+ uart_conf |= (1<<3);
+ *C3_UART_CONF0_REG_UART0 = uart_conf;
}
void config_uart(){
printf("Try to config %d\n", 1);
- // wait for UART_REG_UPDATE to become 0, which indicates the completion of the last synchronization;
- uint32_t reg_update = *C3_UART_ID_REG;
+ // wait for UART_REG_UART0_UPDATE to become 0, which indicates the completion of the last synchronization;
+ uint32_t reg_update = *C3_UART_ID_REG_UART0;
if ((bool)(reg_update & (uint32_t)(1<<31))){
return;
}
@@ -122,13 +128,28 @@ void config_uart(){
// synchronize the configured values to the Core Clock domain by writing 1 to UART_REG_UPDATE.
reg_update |= (uint32_t)(1<<31);
- *C3_UART_ID_REG = reg_update;
+ *C3_UART_ID_REG_UART0 = reg_update;
+}
+
+static void set_65_to_rd_byte(){
+ uint32_t rx_fifo = *C3_UART_FIFO_REG_UART0;
+ // making sure we start with 0
+ rx_fifo |= 1<<0;
+ rx_fifo |= 1<<6;
+ *C3_UART_FIFO_REG_UART0 = rx_fifo;
+
}
void enable_uart_transmitter(){
// configure TX FIFO’s empty threshold via UART_TXFIFO_EMPTY_THRHD;
+ clearBits(C3_UART_CONF1_REG_UART0, 9, 9);
+
// disable UART_TXFIFO_EMPTY_INT interrupt by clearing UART_TXFIFO_EMPTY_INT_ENA;
+ clearBits(C3_UART_INT_ENA_REG_UART0, 1, 1);
+
// write data to be sent to UART_RXFIFO_RD_BYTE;
+ set_65_to_rd_byte();
+
// clear UART_TXFIFO_EMPTY_INT interrupt by setting UART_TXFIFO_EMPTY_INT_CLR;
// enable UART_TXFIFO_EMPTY_INT interrupt by setting UART_TXFIFO_EMPTY_INT_ENA;
// detect UART_TXFIFO_EMPTY_INT and wait for the completion of data transmission.