diff --git a/src/uart-transmit/esp32-c3-uart-interface.c b/src/uart-transmit/esp32-c3-uart-interface.c
index ba50bcf2ca86ee1d65151a70c3a3d35b2f056eef..a838e2d7a41444bfd47f5cb9343397cabd940a91 100644
--- a/src/uart-transmit/esp32-c3-uart-interface.c
+++ b/src/uart-transmit/esp32-c3-uart-interface.c
@@ -1,7 +1,10 @@
#include "esp32-c3-uart-interface.h"
-#include "esp32-c3-led-helpers.h"
#include <stdint.h>
#include <stdbool.h>
+#include <stddef.h>
+
+#include <mdk.h>
+
static void clearBits(volatile uint32_t *registerAddress, uint32_t bitPositions, uint32_t numBits) {
uint32_t mask = (uint32_t)(1 << numBits) - 1; // Create a mask with the specified number of bits set to 1
@@ -14,6 +17,15 @@ static void setBit(volatile uint32_t *registerAddress, uint32_t bitPositions) {
*registerAddress |= ~mask;
}
+static void setSpecificBitsInRegister(volatile uint32_t *reg, uint32_t *bits, size_t numBits) {
+ uint32_t rx_fifo = *reg;
+ for (size_t i = 0; i < numBits; i++) {
+ uint32_t bitPos = bits[i];
+ rx_fifo |= (1 << bitPos);
+ }
+ *reg = rx_fifo;
+}
+
static void init_uart_enable_clk(){
// enable the clock for UART RAM by setting SYSTEM_UART_MEM_CLK_EN to 1;
// enable APB_CLK for UARTn by setting SYSTEM_UARTn_CLK_EN to 1;
@@ -28,33 +40,33 @@ static void init_uart_toggle_rst(){
// Detailed steps explained in 26.5.2.1
// for resetting and initilizing of uart
// get current regestry values
- uint32_t rx_filt = *C3_UART_RX_FILT_REG_UART0;
- uint32_t core_value = *C3_UART_CLK_CONF_REG_UART0;
+ uint32_t rx_filt = *C3_UART_RX_FILT_REG(0);
+ uint32_t core_value = *C3_UART_CLK_CONF_REG(0);
// clear UARTn_RST
rx_filt &= (uint32_t)~(1<<5);
rx_filt &= (uint32_t)~(1<<2);
- *C3_UART_RX_FILT_REG_UART0 = rx_filt;
+ *C3_UART_RX_FILT_REG(0) = rx_filt;
// set UART_RST_CORE
core_value |= 1<<23;
- *C3_UART_CLK_CONF_REG_UART0 = core_value;
+ *C3_UART_CLK_CONF_REG(0) = core_value;
// set UARTn_RST
rx_filt |= 1<<5;
rx_filt |= 1<<2;
- *C3_UART_RX_FILT_REG_UART0 = rx_filt;
+ *C3_UART_RX_FILT_REG(0) = rx_filt;
// clear UARTn_RST
rx_filt &= (uint32_t)~(1<<5);
rx_filt &= (uint32_t)~(1<<2);
- *C3_UART_RX_FILT_REG_UART0 = rx_filt;
+ *C3_UART_RX_FILT_REG(0) = rx_filt;
// clear UART_RST_CORE
core_value &= (uint32_t)~(1<<23);
- *C3_UART_CLK_CONF_REG_UART0 = core_value;
+ *C3_UART_CLK_CONF_REG(0) = core_value;
}
static void init_uart_clear_update(){
// enable register synchronization by clearing UART_UPDATE_CTRL.
- uint32_t id_value = *C3_UART_ID_REG_UART0;
+ uint32_t id_value = *C3_UART_ID_REG(0);
id_value &= (uint32_t)~(1<<30);
- *C3_UART_ID_REG_UART0 = id_value;
+ *C3_UART_ID_REG(0) = id_value;
}
static void config_clock_freq(){
@@ -62,7 +74,7 @@ static void config_clock_freq(){
// baud rate = freq / (UART_CLKDIV + UART_CLKDIV_FRAG / 16)
// select the clock source via UART_SCLK_SEL;
- uint32_t clockSelect = *C3_UART_CLK_CONF_REG_UART0;
+ uint32_t clockSelect = *C3_UART_CLK_CONF_REG(0);
// making sure we start with 0
clockSelect &= (uint32_t)~(1<<20);
clockSelect &= (uint32_t)~(1<<21);
@@ -70,7 +82,7 @@ static void config_clock_freq(){
// 10 is RC_FAST_CLK with default of 17.5 MHz
// 11 is XTAL_CLK with 40 MHz
clockSelect |= 1<<20;
- *C3_UART_CLK_CONF_REG_UART0 = clockSelect;
+ *C3_UART_CLK_CONF_REG(0) = clockSelect;
// selected ABP_CLK with 80 MHz
// dividing clock to 6 Mhz (divisor should be 13+1/3)
@@ -86,35 +98,35 @@ static void config_clock_freq(){
clockSelect |= 1<<1;
clockSelect |= 1<<0;
- *C3_UART_CLK_CONF_REG_UART0 = clockSelect;
+ *C3_UART_CLK_CONF_REG(0) = clockSelect;
// calculate Baud rate to be 9600 (6Mhz/625)
- uint32_t baudRateDivs = *C3_UART_CLKDIV_REG_UART0;
+ uint32_t baudRateDivs = *C3_UART_CLKDIV_REG(0);
baudRateDivs |= 1<<0;
baudRateDivs |= 1<<4;
baudRateDivs |= 1<<5;
baudRateDivs |= 1<<6;
baudRateDivs |= 1<<9;
- *C3_UART_CLKDIV_REG_UART0 = baudRateDivs;
+ *C3_UART_CLKDIV_REG(0) = baudRateDivs;
}
static void disable_parity(){
- uint32_t uart_conf = *C3_UART_CONF0_REG_UART0;
+ uint32_t uart_conf = *C3_UART_CONF0_REG(0);
uart_conf &= (uint32_t)~(1<<0);
uart_conf &= (uint32_t)~(1<<1);
- *C3_UART_CONF0_REG_UART0 = uart_conf;
+ *C3_UART_CONF0_REG(0) = uart_conf;
}
static void set_max_data_lenght(){
- uint32_t uart_conf = *C3_UART_CONF0_REG_UART0;
+ uint32_t uart_conf = *C3_UART_CONF0_REG(0);
uart_conf |= (1<<2);
uart_conf |= (1<<3);
- *C3_UART_CONF0_REG_UART0 = uart_conf;
+ *C3_UART_CONF0_REG(0) = uart_conf;
}
void config_uart(){
- // wait for UART_REG_UART0_UPDATE to become 0, which indicates the completion of the last synchronization;
- uint32_t reg_update = *C3_UART_ID_REG_UART0;
+ // wait for UART_REG(0)_UPDATE to become 0, which indicates the completion of the last synchronization;
+ uint32_t reg_update = *C3_UART_ID_REG(0);
while((bool)(reg_update & (uint32_t)(1<<31))){
__asm__("ADDI x0, x0, 0");
@@ -134,35 +146,41 @@ void config_uart(){
// synchronize the configured values to the Core Clock domain by writing 1 to UART_REG_UPDATE.
reg_update |= (uint32_t)(1<<31);
- *C3_UART_ID_REG_UART0 = reg_update;
+ *C3_UART_ID_REG(0) = reg_update;
}
-static void set_65_to_rd_byte(){
- uint32_t rx_fifo = *C3_UART_FIFO_REG_UART0;
- // making sure we start with 0
- rx_fifo |= 1<<0;
- rx_fifo |= 1<<6;
- *C3_UART_FIFO_REG_UART0 = rx_fifo;
+void writeSomething(){
+ uint32_t bitPositions[] = {0,1,7};
+ size_t numBits = sizeof(bitPositions) / sizeof(bitPositions[0]);
+ setSpecificBitsInRegister(C3_UART_FIFO_REG(0), bitPositions, numBits);
+
+ //uint32_t rx_fifo = *C3_UART_FIFO_REG(0);
+ //rx_fifo |= 1<<7;
+ //rx_fifo |= 1<<6;
+ //rx_fifo |= 1<<5;
+ //*C3_UART_FIFO_REG(0) = rx_fifo;
}
void enable_uart_transmitter(){
- // configure TX FIFO’s empty threshold via UART_TXFIFO_EMPTY_THRHD;
- clearBits(C3_UART_CONF1_REG_UART0, 9, 9);
-
- // disable UART_TXFIFO_EMPTY_INT interrupt by clearing UART_TXFIFO_EMPTY_INT_ENA;
- clearBits(C3_UART_INT_ENA_REG_UART0, 1, 1);
-
- // write data to be sent to UART_RXFIFO_RD_BYTE;
- set_65_to_rd_byte();
-
- // clear UART_TXFIFO_EMPTY_INT interrupt by setting UART_TXFIFO_EMPTY_INT_CLR;
- setBit(C3_UART_INT_CLR_REG_UART0, 1);
-
- // enable UART_TXFIFO_EMPTY_INT interrupt by setting UART_TXFIFO_EMPTY_INT_ENA;
- setBit(C3_UART_INT_ENA_REG_UART0, 1);
-
- // detect UART_TXFIFO_EMPTY_INT and wait for the completion of data transmission.
+ for(int i = 0; i < 100; i++){
+ delay_ms(10);
+ // configure TX FIFO’s empty threshold via UART_TXFIFO_EMPTY_THRHD;
+ clearBits(C3_UART_CONF1_REG(0), 9, 9);
+ setBit(C3_UART_CONF1_REG(0),3);
+
+ // disable UART_TXFIFO_EMPTY_INT interrupt by clearing UART_TXFIFO_EMPTY_INT_ENA;
+ clearBits(C3_UART_INT_ENA_REG(0), 1, 1);
+
+ // write data to be sent to UART_RXFIFO_RD_BYTE;
+ writeSomething();
+
+ // clear UART_TXFIFO_EMPTY_INT interrupt by setting UART_TXFIFO_EMPTY_INT_CLR;
+ setBit(C3_UART_INT_CLR_REG(0), 1);
+
+ // enable UART_TXFIFO_EMPTY_INT interrupt by setting UART_TXFIFO_EMPTY_INT_ENA;
+ setBit(C3_UART_INT_ENA_REG(0), 1);
+ }
}
void reset_uart(){
@@ -172,16 +190,8 @@ void reset_uart(){
}
void init_uart(){
- uint8_t red[3] = {0,1,0};
- uint8_t blue[3] = {0,0,1};
- uint8_t yellow[3] = {1,1,0};
- uint8_t violet[3] = {0,1,1};
// from technical reference manual 543 f
- showColorForDuration(red,1000);
init_uart_enable_clk();
- showColorForDuration(blue,1000);
init_uart_toggle_rst();
- showColorForDuration(violet,1000);
init_uart_clear_update();
- showColorForDuration(yellow,1000);
}
\ No newline at end of file
diff --git a/src/uart-transmit/esp32-c3-uart-interface.h b/src/uart-transmit/esp32-c3-uart-interface.h
index 7dfe002d3fb0292099c0833d2109bd55b9ae8466..3d187ad64d60307f6d6eb43c8d7e2720818fce35 100644
--- a/src/uart-transmit/esp32-c3-uart-interface.h
+++ b/src/uart-transmit/esp32-c3-uart-interface.h
@@ -3,64 +3,57 @@
// all addresses are relative to some other register....
-#define C3_BASE_OFFSET_UART_CONTROLLER_0 ((uint32_t)0x60000000)
-#define C3_BASE_OFFSET_UART_CONTROLLER_1 ((uint32_t)0x60010000)
-#define C3_BASE_OFFSET_SYSTEM_REGISTERS ((uint32_t)0x600C0000)
-#define C3_BASE_OFFSET_SYSTEM_REGISTERS ((uint32_t)0x600C0000)
#define C3_BASE_OFFSET_SYSTEM_REGISTERS ((uint32_t)0x600C0000)
-#define C3_UART_FIFO_REG_UART0 ((volatile uint32_t *)C3_BASE_OFFSET_UART_CONTROLLER_0+0x0000)
-#define C3_UART_FIFO_REG_UART1 ((volatile uint32_t *)C3_BASE_OFFSET_UART_CONTROLLER_1+0x0000)
-// UART_RXFIFO_RD_BYTE is from 0 to 7
+#define C3_UART_CONTROLLER_0_BASE ((uint32_t)0x60000000)
+#define C3_UART_CONTROLLER_1_BASE ((uint32_t)0x60010000)
+#define C3_UART_CONTROLLER_SELECT(base_select) ((volatile uint32_t *)((base_select == 1) ? C3_UART_CONTROLLER_1_BASE : C3_UART_CONTROLLER_0_BASE))
+
+#define C3_UART_FIFO_REG(base_select) ((volatile uint32_t *)(C3_UART_CONTROLLER_SELECT((base_select)) + 0x0000))
-#define C3_UART_INT_ENA_REG_UART0 ((volatile uint32_t *)C3_BASE_OFFSET_UART_CONTROLLER_0+0x000C)
-#define C3_UART_INT_ENA_REG_UART1 ((volatile uint32_t *)C3_BASE_OFFSET_UART_CONTROLLER_1+0x000C)
+#define C3_UART_INT_RAW(base_select) ((volatile uint32_t *)(C3_UART_CONTROLLER_SELECT((base_select)) + 0x0004))
+// UART_TXFIFO_EMPTY_INT_RAW is on 1
+
+#define C3_UART_INT_ENA_REG(base_select) ((volatile uint32_t *)(C3_UART_CONTROLLER_SELECT((base_select)) + 0x000C))
// UART_TXFIFO_EMPTY_INT_ENA is on 1
-#define C3_UART_INT_CLR_REG_UART0 ((volatile uint32_t *)C3_BASE_OFFSET_UART_CONTROLLER_0+0x0010)
-#define C3_UART_INT_CLR_REG_UART1 ((volatile uint32_t *)C3_BASE_OFFSET_UART_CONTROLLER_1+0x0010)
+#define C3_UART_INT_CLR_REG(base_select) ((volatile uint32_t *)(C3_UART_CONTROLLER_SELECT((base_select)) + 0x0010))
// UART_TXFIFO_EMPTY_INT_CLR
-#define C3_SYSTEM_PERIP_CLK_EN0_REG ((volatile uint32_t *)C3_BASE_OFFSET_SYSTEM_REGISTERS+0x0010)
-// SYSTEM_UART_MEM_CLK_EN is on 24
-// SYSTEM_UARTn_CLK_EN n=0 is on 2, n=1 is on 5
-
-#define C3_UART_CLKDIV_REG_UART0 ((volatile uint32_t *)C3_BASE_OFFSET_UART_CONTROLLER_0+0x0014)
-#define C3_UART_CLKDIV_REG_UART1 ((volatile uint32_t *)C3_BASE_OFFSET_UART_CONTROLLER_1+0x0014)
+#define C3_UART_CLKDIV_REG(base_select) ((volatile uint32_t *)(C3_UART_CONTROLLER_SELECT((base_select)) + 0x0014))
// UART_CLKDIV - integer part of baud rate calculator devisor - 0 to 11
// UART_CLKDIV_FRAG - numerator of devisor in baud rate calculator devisor
-#define C3_UART_RX_FILT_REG_UART0 ((volatile uint32_t *)C3_BASE_OFFSET_UART_CONTROLLER_0+0x0018)
-#define C3_UART_RX_FILT_REG_UART1 ((volatile uint32_t *)C3_BASE_OFFSET_UART_CONTROLLER_1+0x0018)
+#define C3_UART_RX_FILT_REG(base_select) ((volatile uint32_t *)(C3_UART_CONTROLLER_SELECT((base_select)) + 0x0018))
// SYSTEM_UARTn_RST n=0 is on 2, n=1 is on 5
-#define C3_UART_CONF0_REG_UART0 ((volatile uint32_t *)C3_BASE_OFFSET_UART_CONTROLLER_0+0x0020)
-#define C3_UART_CONF0_REG_UART1 ((volatile uint32_t *)C3_BASE_OFFSET_UART_CONTROLLER_1+0x0020)
+#define C3_UART_CONF0_REG(base_select) ((volatile uint32_t *)(C3_UART_CONTROLLER_SELECT((base_select)) + 0x0020))
// UART_PARITY is on 0
// UART_PARITY_EN is on 1
// UART_BIT_NUM is on 2 and 3
-
-#define C3_UART_CONF1_REG_UART0 ((volatile uint32_t *)C3_BASE_OFFSET_UART_CONTROLLER_0+0x0024)
-#define C3_UART_CONF1_REG_UART1 ((volatile uint32_t *)C3_BASE_OFFSET_UART_CONTROLLER_1+0x0024)
+#define C3_UART_CONF1_REG(base_select) ((volatile uint32_t *)(C3_UART_CONTROLLER_SELECT((base_select)) + 0x0024))
// UART_TXFIFO_EMPTY_THRHD is 9 to 17
-#define C3_UART_CLK_CONF_REG_UART0 ((volatile uint32_t *)C3_BASE_OFFSET_UART_CONTROLLER_0+0x0078)
-#define C3_UART_CLK_CONF_REG_UART1 ((volatile uint32_t *)C3_BASE_OFFSET_UART_CONTROLLER_1+0x0078)
+#define C3_UART_CLK_CONF_REG(base_select) ((volatile uint32_t *)(C3_UART_CONTROLLER_SELECT((base_select)) + 0x0078))
// UART_RST_CORE is on 23
// UART_SCLK_SEL is on 20 and 21 (2 bits), selcetion is between 1 and 3
// UART_SCLK_DIV_NUM - The integral part of the frequency divisor - 12 to 19
// UART_SCLK_DIV_A - The numerator of the frequency divisor - 6 to 11
// UART_SCLK_DIV_B - The denominator of the frequency divisor - 0 to 5
-#define C3_UART_ID_REG_UART0 ((volatile uint32_t *)C3_BASE_OFFSET_UART_CONTROLLER_0+0x0080)
-#define C3_UART_ID_REG_UART1 ((volatile uint32_t *)C3_BASE_OFFSET_UART_CONTROLLER_1+0x0080)
+#define C3_UART_ID_REG(base_select) ((volatile uint32_t *)(C3_UART_CONTROLLER_SELECT((base_select)) + 0x0080))
// UART_UPDATE_CTRL is on 30
// UART_REG_UPDATE is on 31
+#define C3_SYSTEM_PERIP_CLK_EN0_REG ((volatile uint32_t *)(C3_BASE_OFFSET_SYSTEM_REGISTERS+0x0010))
+// SYSTEM_UART_MEM_CLK_EN is on 24
+// SYSTEM_UARTn_CLK_EN n=0 is on 2, n=1 is on 5
+
void config_uart();
void init_uart();
void reset_uart();
void enable_uart_transmitter();
+void writeSomething();
#endif
\ No newline at end of file