From f10daeeb2e0292ccb15a5ae64e4b7211f111ccb2 Mon Sep 17 00:00:00 2001
From: Jakob <Jakob.knitter@bettermarks.com>
Date: Sun, 18 Jun 2023 16:16:00 +0200
Subject: [PATCH] feat: add simple register read-write example
---
src/reading-writing-registers/Makefile | 3 +++
.../esp32-c3-register-interface.c | 14 ++++++++++++++
.../esp32-c3-register-interface.h | 17 +++++++++++++++++
src/reading-writing-registers/main.c | 13 +++++++++++++
4 files changed, 47 insertions(+)
create mode 100644 src/reading-writing-registers/Makefile
create mode 100644 src/reading-writing-registers/esp32-c3-register-interface.c
create mode 100644 src/reading-writing-registers/esp32-c3-register-interface.h
create mode 100644 src/reading-writing-registers/main.c
diff --git a/src/reading-writing-registers/Makefile b/src/reading-writing-registers/Makefile
new file mode 100644
index 0000000..687c039
--- /dev/null
+++ b/src/reading-writing-registers/Makefile
@@ -0,0 +1,3 @@
+SOURCES = main.c esp32-c3-register-interface.c
+
+include $(MDK)/$(ARCH)/build.mk
diff --git a/src/reading-writing-registers/esp32-c3-register-interface.c b/src/reading-writing-registers/esp32-c3-register-interface.c
new file mode 100644
index 0000000..a20d40f
--- /dev/null
+++ b/src/reading-writing-registers/esp32-c3-register-interface.c
@@ -0,0 +1,14 @@
+#include "esp32-c3-uart-interface.h"
+#include <stdint.h>
+
+void readSetClear(){
+ uint32_t core_value = *C3_UART_CLK_CONF_REG(0);
+
+ // set UART_RST_CORE
+ core_value |= 1<<23;
+ *C3_UART_CLK_CONF_REG(0) = core_value;
+
+ // clear UART_RST_CORE
+ core_value &= (uint32_t)~(1<<23);
+ *C3_UART_CLK_CONF_REG(0) = core_value;
+}
\ No newline at end of file
diff --git a/src/reading-writing-registers/esp32-c3-register-interface.h b/src/reading-writing-registers/esp32-c3-register-interface.h
new file mode 100644
index 0000000..d012dda
--- /dev/null
+++ b/src/reading-writing-registers/esp32-c3-register-interface.h
@@ -0,0 +1,17 @@
+#ifndef ESP32_C3_REGISTER_INTERFACE_H
+#define ESP32_C3_REGISTER_INTERFACE_H
+
+#define C3_UART_CONTROLLER_0_BASE ((uint32_t)0x60000000)
+#define C3_UART_CONTROLLER_1_BASE ((uint32_t)0x60010000)
+#define C3_UART_CONTROLLER_SELECT(base_select) ((volatile uint32_t *)((base_select == 1) ? C3_UART_CONTROLLER_1_BASE : C3_UART_CONTROLLER_0_BASE))
+
+#define C3_UART_CLK_CONF_REG(base_select) ((volatile uint32_t *)(C3_UART_CONTROLLER_SELECT((base_select)) + 0x0078))
+// UART_RST_CORE is on 23
+// UART_SCLK_SEL is on 20 and 21 (2 bits), selcetion is between 1 and 3
+// UART_SCLK_DIV_NUM - The integral part of the frequency divisor - 12 to 19
+// UART_SCLK_DIV_A - The numerator of the frequency divisor - 6 to 11
+// UART_SCLK_DIV_B - The denominator of the frequency divisor - 0 to 5
+
+void readSetClear();
+
+#endif
\ No newline at end of file
diff --git a/src/reading-writing-registers/main.c b/src/reading-writing-registers/main.c
new file mode 100644
index 0000000..e2011f9
--- /dev/null
+++ b/src/reading-writing-registers/main.c
@@ -0,0 +1,13 @@
+// Copyright (c) Charles Lohr
+// All rights reserved
+
+#include <mdk.h>
+#include "esp32-c3-register-interface.h"
+
+int main(void) {
+ wdt_disable();
+
+ readSetClear();
+
+ return 0;
+}
--
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