diff --git a/src/reading-writing-registers/esp32-c3-register-interface.c b/src/reading-writing-registers/esp32-c3-register-interface.c index d5372bffbcd048df0b5649039b8502dc2b134c04..9c9e22e0270635754791b4e30487226b04cdbc15 100644 --- a/src/reading-writing-registers/esp32-c3-register-interface.c +++ b/src/reading-writing-registers/esp32-c3-register-interface.c @@ -1,14 +1,11 @@ #include "esp32-c3-register-interface.h" -#include <stdint.h> void readSetClear(){ - uint32_t core_value = *C3_UART_CLK_CONF_REG(0); + esp32c3_uart_clk_conf_t *clockConfig = UART_CLK_CONF_REG(0); // set UART_RST_CORE - core_value |= 1<<23; - *C3_UART_CLK_CONF_REG(0) = core_value; + clockConfig->REST_CORE = 1; // clear UART_RST_CORE - core_value &= (uint32_t)~(1<<23); - *C3_UART_CLK_CONF_REG(0) = core_value; + clockConfig->REST_CORE = 0; } \ No newline at end of file diff --git a/src/reading-writing-registers/esp32-c3-register-interface.h b/src/reading-writing-registers/esp32-c3-register-interface.h index 6fb3181cea10e3d5c7d14a12e54a981b763f2a7d..be75bca10367fd4162aa835062ff9f3070dc4e22 100644 --- a/src/reading-writing-registers/esp32-c3-register-interface.h +++ b/src/reading-writing-registers/esp32-c3-register-interface.h @@ -1,16 +1,27 @@ #ifndef ESP32_C3_REGISTER_INTERFACE_H #define ESP32_C3_REGISTER_INTERFACE_H +#include <stdint.h> + #define C3_UART_CONTROLLER_0_BASE ((uint32_t)0x60000000) #define C3_UART_CONTROLLER_1_BASE ((uint32_t)0x60010000) #define C3_UART_CONTROLLER_SELECT(base_select) ((uint32_t)((base_select == 1) ? C3_UART_CONTROLLER_1_BASE : C3_UART_CONTROLLER_0_BASE)) -#define C3_UART_CLK_CONF_REG(base_select) ((volatile uint32_t *)(C3_UART_CONTROLLER_SELECT((base_select)) + 0x0078)) -// UART_RST_CORE is on 23 -// UART_SCLK_SEL is on 20 and 21 (2 bits), selcetion is between 1 and 3 -// UART_SCLK_DIV_NUM - The integral part of the frequency divisor - 12 to 19 -// UART_SCLK_DIV_A - The numerator of the frequency divisor - 6 to 11 -// UART_SCLK_DIV_B - The denominator of the frequency divisor - 0 to 5 +typedef volatile struct { + uint32_t SCLK_DIV_B: 6; + uint32_t SCLK_DIV_A: 6; + uint32_t SCLK_DIV_NUM: 8; + uint32_t SCLK_SEL: 2; + uint32_t SCLK_EN: 1; + uint32_t REST_CORE: 1; + uint32_t TX_SCLK_EN: 1; + uint32_t RX_SCLK_EN: 1; + uint32_t TX_REST_CORE: 1; + uint32_t RX_REST_CORE: 1; + uint32_t RESERVED: 4; +} esp32c3_uart_clk_conf_t; + +#define UART_CLK_CONF_REG(base_select) ((esp32c3_uart_clk_conf_t *)(C3_UART_CONTROLLER_SELECT((base_select)) + 0x0078)) // Assuming the offset of clk_conf is 0x18 from the base address void readSetClear();