From f1432e3e855a9b04a2a37ccb39f89c6055149c08 Mon Sep 17 00:00:00 2001
From: Jakob <Jakob.knitter@bettermarks.com>
Date: Mon, 19 Jun 2023 11:09:56 +0200
Subject: [PATCH] refactor: easier register access
---
.../esp32-c3-register-interface.c | 9 +++-----
.../esp32-c3-register-interface.h | 23 ++++++++++++++-----
2 files changed, 20 insertions(+), 12 deletions(-)
diff --git a/src/reading-writing-registers/esp32-c3-register-interface.c b/src/reading-writing-registers/esp32-c3-register-interface.c
index d5372bf..9c9e22e 100644
--- a/src/reading-writing-registers/esp32-c3-register-interface.c
+++ b/src/reading-writing-registers/esp32-c3-register-interface.c
@@ -1,14 +1,11 @@
#include "esp32-c3-register-interface.h"
-#include <stdint.h>
void readSetClear(){
- uint32_t core_value = *C3_UART_CLK_CONF_REG(0);
+ esp32c3_uart_clk_conf_t *clockConfig = UART_CLK_CONF_REG(0);
// set UART_RST_CORE
- core_value |= 1<<23;
- *C3_UART_CLK_CONF_REG(0) = core_value;
+ clockConfig->REST_CORE = 1;
// clear UART_RST_CORE
- core_value &= (uint32_t)~(1<<23);
- *C3_UART_CLK_CONF_REG(0) = core_value;
+ clockConfig->REST_CORE = 0;
}
\ No newline at end of file
diff --git a/src/reading-writing-registers/esp32-c3-register-interface.h b/src/reading-writing-registers/esp32-c3-register-interface.h
index 6fb3181..be75bca 100644
--- a/src/reading-writing-registers/esp32-c3-register-interface.h
+++ b/src/reading-writing-registers/esp32-c3-register-interface.h
@@ -1,16 +1,27 @@
#ifndef ESP32_C3_REGISTER_INTERFACE_H
#define ESP32_C3_REGISTER_INTERFACE_H
+#include <stdint.h>
+
#define C3_UART_CONTROLLER_0_BASE ((uint32_t)0x60000000)
#define C3_UART_CONTROLLER_1_BASE ((uint32_t)0x60010000)
#define C3_UART_CONTROLLER_SELECT(base_select) ((uint32_t)((base_select == 1) ? C3_UART_CONTROLLER_1_BASE : C3_UART_CONTROLLER_0_BASE))
-#define C3_UART_CLK_CONF_REG(base_select) ((volatile uint32_t *)(C3_UART_CONTROLLER_SELECT((base_select)) + 0x0078))
-// UART_RST_CORE is on 23
-// UART_SCLK_SEL is on 20 and 21 (2 bits), selcetion is between 1 and 3
-// UART_SCLK_DIV_NUM - The integral part of the frequency divisor - 12 to 19
-// UART_SCLK_DIV_A - The numerator of the frequency divisor - 6 to 11
-// UART_SCLK_DIV_B - The denominator of the frequency divisor - 0 to 5
+typedef volatile struct {
+ uint32_t SCLK_DIV_B: 6;
+ uint32_t SCLK_DIV_A: 6;
+ uint32_t SCLK_DIV_NUM: 8;
+ uint32_t SCLK_SEL: 2;
+ uint32_t SCLK_EN: 1;
+ uint32_t REST_CORE: 1;
+ uint32_t TX_SCLK_EN: 1;
+ uint32_t RX_SCLK_EN: 1;
+ uint32_t TX_REST_CORE: 1;
+ uint32_t RX_REST_CORE: 1;
+ uint32_t RESERVED: 4;
+} esp32c3_uart_clk_conf_t;
+
+#define UART_CLK_CONF_REG(base_select) ((esp32c3_uart_clk_conf_t *)(C3_UART_CONTROLLER_SELECT((base_select)) + 0x0078)) // Assuming the offset of clk_conf is 0x18 from the base address
void readSetClear();
--
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