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Commit 79b00cf8 authored by Robert Nelson's avatar Robert Nelson
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sync cleanups

parent 8b16e138
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...@@ -6,6 +6,10 @@ ...@@ -6,6 +6,10 @@
#include "am33xx.dtsi" #include "am33xx.dtsi"
#include "am335x-bone-common-no-capemgr.dtsi" #include "am335x-bone-common-no-capemgr.dtsi"
/* #include "am335x-boneblack-common.dtsi" */
/* #include "am335x-bone-jtag.dtsi" */
/* RoboticsCape */
#include "am335x-bone-common-universal-pins.dtsi" #include "am335x-bone-common-universal-pins.dtsi"
#include "am335x-roboticscape.dtsi" #include "am335x-roboticscape.dtsi"
...@@ -14,6 +18,7 @@ ...@@ -14,6 +18,7 @@
compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
}; };
/* needed from: am335x-boneblack-common.dtsi */
&ldo3_reg { &ldo3_reg {
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
......
...@@ -6,13 +6,18 @@ ...@@ -6,13 +6,18 @@
#include "am33xx.dtsi" #include "am33xx.dtsi"
#include "am335x-bone-common-no-capemgr.dtsi" #include "am335x-bone-common-no-capemgr.dtsi"
/* #include "am335x-boneblack-common.dtsi" */
/* #include "am335x-bone-jtag.dtsi" */
#include <dt-bindings/interrupt-controller/irq.h>
/* RoboticsCape */
#include "am335x-bone-common-universal-pins.dtsi" #include "am335x-bone-common-universal-pins.dtsi"
#include "am335x-boneblack-wl1835.dtsi" #include "am335x-boneblack-wl1835.dtsi"
#include "am335x-roboticscape.dtsi" #include "am335x-roboticscape.dtsi"
/ { / {
model = "TI AM335x BeagleBone Black Wireless RoboticsCape"; model = "TI AM335x BeagleBone Black Wireless RoboticsCape";
compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; compatible = "ti,am335x-bone-black-wireless", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
}; };
&ldo3_reg { &ldo3_reg {
......
...@@ -647,7 +647,7 @@ ...@@ -647,7 +647,7 @@
status = "disabled"; status = "disabled";
}; };
mailbox: mailbox@480C8000 { mailbox: mailbox@480c8000 {
compatible = "ti,omap4-mailbox"; compatible = "ti,omap4-mailbox";
reg = <0x480C8000 0x200>; reg = <0x480C8000 0x200>;
interrupts = <77>; interrupts = <77>;
...@@ -1268,7 +1268,7 @@ ...@@ -1268,7 +1268,7 @@
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
mcasp1: mcasp@4803C000 { mcasp1: mcasp@4803c000 {
compatible = "ti,am33xx-mcasp-audio"; compatible = "ti,am33xx-mcasp-audio";
ti,hwmods = "mcasp1"; ti,hwmods = "mcasp1";
reg = <0x4803C000 0x2000>, reg = <0x4803C000 0x2000>,
......
...@@ -223,8 +223,8 @@ ...@@ -223,8 +223,8 @@
compatible = "mmc-pwrseq-simple"; compatible = "mmc-pwrseq-simple";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&brcmf_pwrseq_pins_default>; pinctrl-0 = <&brcmf_pwrseq_pins_default>;
reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>, // BT-REG-ON reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>, /* BT-REG-ON */
<&gpio3 18 GPIO_ACTIVE_LOW>; // WL-REG-ON <&gpio3 18 GPIO_ACTIVE_LOW>; /* WL-REG-ON */
}; };
unused_pins: unused_pins { unused_pins: unused_pins {
......
...@@ -584,11 +584,11 @@ ...@@ -584,11 +584,11 @@
}; };
&gpu { &gpu {
status = "ok"; status = "okay";
}; };
&dss { &dss {
status = "ok"; status = "okay";
vdda_video-supply = <&ldoln_reg>; vdda_video-supply = <&ldoln_reg>;
}; };
...@@ -602,7 +602,7 @@ ...@@ -602,7 +602,7 @@
}; };
&hdmi { &hdmi {
status = "ok"; status = "okay";
vdda-supply = <&ldo4_reg>; vdda-supply = <&ldo4_reg>;
port { port {
...@@ -613,7 +613,7 @@ ...@@ -613,7 +613,7 @@
}; };
&pcie1_rc { &pcie1_rc {
status = "ok"; status = "okay";
gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
}; };
......
// SPDX-License-Identifier: GPL-2.0-only
/* /*
* Device Tree Source for DRA7xx clock data * Device Tree Source for DRA7xx clock data
* *
......
...@@ -280,7 +280,7 @@ ...@@ -280,7 +280,7 @@
}; };
}; };
ocmcram: ocmcram@40300000 { ocmcram: sram@40300000 {
compatible = "mmio-sram"; compatible = "mmio-sram";
reg = <0x40300000 0x20000>; /* 128k */ reg = <0x40300000 0x20000>; /* 128k */
}; };
......
...@@ -617,6 +617,7 @@ ...@@ -617,6 +617,7 @@
reg = <0x1940>; reg = <0x1940>;
}; };
}; };
&cm_core_clocks { &cm_core_clocks {
dpll_per_byp_mux: dpll_per_byp_mux@14c { dpll_per_byp_mux: dpll_per_byp_mux@14c {
......
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