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Commit a0eaae08 authored by Richard Henderson's avatar Richard Henderson
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accel/tcg: Renumber TLB_DISCARD_WRITE


Move to fill a hole in the set of bits.
Reduce the total number of tlb bits by 1.

Reviewed-by: default avatarPhilippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent 187ba694
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......@@ -325,10 +325,10 @@ CPUArchState *cpu_copy(CPUArchState *env);
#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2))
/* Set if TLB entry is an IO callback. */
#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3))
/* Set if TLB entry writes ignored. */
#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 4))
/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */
#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5))
/* Set if TLB entry writes ignored. */
#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6))
/*
* Use this mask to check interception with an alignment mask
......
......@@ -39,7 +39,7 @@ static void check_max_alignment(unsigned a_bits)
* The requested alignment cannot overlap the TLB flags.
* FIXME: Must keep the count up-to-date with "exec/cpu-all.h".
*/
tcg_debug_assert(a_bits + 6 <= tcg_ctx->page_bits);
tcg_debug_assert(a_bits + 5 <= tcg_ctx->page_bits);
#endif
}
......
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