Register all RAM regions and a custom reset vector

hw/riscv/esp32_c3.c

@@ -39,6 +39,13 @@ static const struct MemmapEntry {
     [ESP32_C3_DM]     =  {  0x20000000,  0x7FFFFFF }
 };
 
+// Reset vector according to technical manual page 217
+static const hwaddr esp32_c3_entry = 0x40000400;
+
+static void esp32_c3_setup_reset_vec() {
+    // TODO: Implement
+}
+
 static void esp32_c3_machine_state_init(MachineState *mstate)
 {
     Esp32C3MachineState *sms = RISCV_ESP32_MACHINE(mstate);
@@ -56,18 +63,13 @@ static void esp32_c3_machine_state_init(MachineState *mstate)
     qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
 
     /* register RAM */
-    // TODO: Deal with IRAM vs DRAM
+    // FIXME: Do we really need to do this? The device is realized right afterwards
     memory_region_add_subregion(system_memory,
                                 esp32_c3_memmap[ESP32_C3_IRAM].base,
                                 mstate->ram);
 
-    /* ROM reset vector */
-    // TODO: Check if this is correct
-    // TODO: Does this make sense for our board? Code runs from ROM directly.
-    riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus,
-                              esp32_c3_memmap[ESP32_C3_IRAM].base,
-                              esp32_c3_memmap[ESP32_C3_IROM].base,
-                              esp32_c3_memmap[ESP32_C3_IROM].size, 0x0400, 0);
+    esp32_c3_setup_reset_vec();
+
     if (mstate->firmware) {
         // We don't have any (separate) firmware to load, as this is an MCU
         error_report("This board can't load firmware");
@@ -103,7 +105,7 @@ static void esp32_c3_machine_class_init(ObjectClass *klass, void *data)
     mc->desc = "RISC-V Board compatible with ES32-C3 SDK";
     mc->init = esp32_c3_machine_state_init;
     mc->default_cpu_type = TYPE_RISCV_CPU_ESP32_C3;
-    mc->default_ram_id = "riscv.esp32.c.ram";
+    mc->default_ram_id = "riscv.esp32.c.dram";
 }
 
 static const TypeInfo esp32_c3_machine_type_info = {
@@ -125,16 +127,32 @@ static void esp32_c3_soc_state_realize(DeviceState *dev, Error **errp)
     MachineState *ms = MACHINE(qdev_get_machine());
     (void)ms;
     Esp32C3SoCState *sss = RISCV_ESP32_SOC(dev);
-    MemoryRegion *system_memory = get_system_memory();
+    MemoryRegion *sys_mem = get_system_memory();
 
     sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort);
 
-    /* ROM */
-    // TODO: Deal with IROM vs DROM
-    memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.esp32.c.rom",
+    /* register ROM */
+    memory_region_init_rom(&sss->irom, OBJECT(dev), "riscv.esp32.c.irom",
                            esp32_c3_memmap[ESP32_C3_IROM].size, &error_fatal);
-    memory_region_add_subregion(system_memory,
-        esp32_c3_memmap[ESP32_C3_IROM].base, &sss->rom);
+    memory_region_add_subregion(sys_mem, esp32_c3_memmap[ESP32_C3_IROM].base,
+                                &sss->irom);
+    memory_region_init_rom(&sss->drom, OBJECT(dev), "riscv.esp32.c.drom",
+                           esp32_c3_memmap[ESP32_C3_DROM].size, &error_fatal);
+    memory_region_add_subregion(sys_mem, esp32_c3_memmap[ESP32_C3_DROM].base,
+                                &sss->drom);
+
+    /* register RAM */
+    memory_region_init_ram(&sss->iram, OBJECT(dev), "riscv.esp32.c.iram",
+                           esp32_c3_memmap[ESP32_C3_IRAM].size, &error_fatal);
+    memory_region_add_subregion(sys_mem, esp32_c3_memmap[ESP32_C3_IRAM].base,
+                                &sss->iram);
+    /* TODO: How is this supposed to work with the default RAM region?
+    We have to specify one (otherwise segfault), but then it can't be initialized here.
+    memory_region_init_ram(&sss->dram, OBJECT(dev), "riscv.esp32.c.dram",
+                           esp32_c3_memmap[ESP32_C3_DRAM].size, &error_fatal);
+    memory_region_add_subregion(sys_mem, esp32_c3_memmap[ESP32_C3_DRAM].base,
+                                &sss->dram);
+    */
 }
 
 static void esp32_c3_soc_class_init(ObjectClass *klass, void *data)

include/hw/riscv/esp32_c3.h

@@ -24,6 +24,7 @@
 
 #include "hw/riscv/riscv_hart.h"
 #include "hw/boards.h"
+#include "qemu/typedefs.h"
 
 
 
@@ -38,7 +39,10 @@ typedef struct Esp32C3SoCState {
     /*< public >*/
     RISCVHartArrayState cpus;
     DeviceState *plic;
-    MemoryRegion rom;
+    MemoryRegion irom;
+    MemoryRegion drom;
+    MemoryRegion iram;
+    MemoryRegion dram;
 
 } Esp32C3SoCState;