added some notes

Repos/notes_simulator.md

+# Some notes regarding the simulator `sancus-sim`
+
+* `sancus-sim` is really the python script [sancus-core/core/sim/rtl_sim/sancus/run_sim.py](sancus-core/core/sim/rtl_sim/sancus/run_sim.py) which calls `iverilog` internally
+* The files _sancus\_sim.fst_, _sim-input.bin_, _sim-output.bin_ that usually remain in a project directory after running the simulator, are not used by the simulator (`iverilog`) itself, but from the program being simulated
+  * _sim-[input/ouput].bin_ are somehow used by the "File IO peripheral" ([sancus-core/core/bench/verilog/tb_openMSP430.v line 651](https://github.com/sancus-pma/sancus-core/blob/master/core/bench/verilog/tb_openMSP430.v#L651))
+  * _sancus\_sim.fst_ is called `dumpfile` in the python script, usage: ???
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docs/c_asm_interface/notes.md

@@ -23,3 +23,14 @@ asm("mov %1, r9\n\t"  // move param 1 into r9
     : "9", "15");
 ```
 * `m`(a) bedeuted, dass direkt auf die Speicherstelle `a` zugegriffen wird (anstatt dass a evtl. schon in einem Register liegt) [https://www.ibiblio.org/gferg/ldp/GCC-Inline-Assembly-HOWTO.html]
+    > we use memory constraints for all operands because otherwise LLVM's
+    > register allocator messes up and uses some of the clobbered registers
+
+
+## Links/ files to examine
+* [omsp_frontend.v line 611](../../Repos/sancus-core/core/rtl/verilog/omsp_frontend.v#L611)
+* [openMSP430_defines.v line 647](../../Repos/sancus-core/core/rtl/verilog/openMSP430_defines.v#L647)
+* [omsp_execution_unit.v line 186](../../Repos/sancus-core/core/rtl/verilog/omsp_execution_unit.v#L186)
+  * [sancus module control, line 541](../../Repos/sancus-core/core/rtl/verilog/omsp_execution_unit.v#L541)
+* [omsp_spm_control.v](../../Repos/sancus-core/core/rtl/verilog/omsp_spm_control.v)
+* [omsp_spm.v](../../Repos/sancus-core/core/rtl/verilog/omsp_spm.v) - Looks like the definition of a software module
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