The DE10-Standard is a FPGA/SoC development board containing a Cyclone V FPGA and a dual-core Cortex-A9 hard processor system (HPS)
The Altera DE10-Standard is a FPGA/SoC development board by Terasic equipped with a Cyclone V FPGA and a dual-core Cortex-A9 hard processor system (HPS).
### This directory contains all the documentation we collected/ wrote during the project
The documentation of our work and the collection of useful sources and knowledge are divided into the different topics, but may overlap or depend on each other since it is not possible to completely separate them.
Our main goal was to include all the important knowledge without adding too many unnecessary documents and we provided an overview README for each folder to document the topics of the included files.
| Dir/File | Description |
| - | - |
| [fpga](fpga/README.md) | General description of an FPGA |
Sancus is a security architecture for IoT devices with the claim of supporting distributed applications on a shared infrastructure and having a zero-software Trusted Computing Base. It was first proposed 2013 at the USENIX Security conference by the KU Leuven.
Sancus already provides broad documentation on their architecture, API and examples on their Website [Sancus: Lightweight and Open-Source Trusted Computing for the IoT](https://distrinet.cs.kuleuven.be/software/sancus/index.php), thus we did not add all the documents that may contain useful information and rather focused on the basic knowledge and added our own insights.
This folder mainly concern the general Sancus architecture and tools. Because Sancus may also be simulated with the sancus-sim, we provided information on that in [Repos](../Repos/) as well as a Docker image and Makefile in [Docker](../docker).
