This is OpenMSP430 core+peripherals implementation adapted for Altera DE1 board.
It is based on original Olivier's adaptation for Diligent S3 board, but has following distinctions:
1. Fixed 7segment core, since DE1 has non-muxed digits.
2. It is adapted for MegaWizard-generated 16-bit wide on-chip ROMs and RAMs.
3. Debug ROM write is removed (although it shouldn't be a problem to return it back).
Anyway I haven't used any debug features.
4. As an alternative to the embedded synchronous RAM, there is ext_de1_sram module that
allows core to access external on-board static RAM.
5. Core is configured to have non-standard ROM and RAM sizes (4kB and 1kB), so make
sure the OpenMSP430_defines.v file is properly updated
6. There is new software project that uses custom linker script to compile for non-standard
ROM and RAM sizes.
Hey,
for an academic software project we want to implement the OpenMSP430 on the Cyclone V FPGA.
We are currently working with the Altera DE10 Standard board instead of the older Altera DE1.
We noticed in your repository that the Altera DE1 board was marked as obselete.
Why did you mark this board as obsolete? Is it just the reason that there are newer revisions of this board available?
Now we're at the point to implement the OpenMSP430 architecture onto the Cyclone V FPGA and already worked on adjusting the local assignments.
Can you provide us any tips on how to proceed and on how we have to further adjust the openMsp verilog files?
We already compared the different boards that you provided in the repo, but it is difficult for us to comprehend the changes that you made.
And in case that we'd manage to get the architecture working, we were wondering whether you would be interested in including our DE10 implementations in your repository?
for an academic software project we want to implement Sancus on the Cyclone V FPGA.
We are working with the Altera DE10 Standard board instead of the older Altera DE1 that you've already provided in your repository.
At the OpenMSP430 github repository, we noticed that the DE1 board is moved to obsolete directory.
Now we're at the point to implement the OpenMSP430 architecture onto the Cyclone V FPGA and already worked on adjusting the local assignments.
Here comes the question: Are you also working on the implementation of the Sancus architecture on
the Altera DE10 Standard board? If so, there is no need for doing redundant parallel work and we'd prefer to support you instead and maybe continue from your current status.
If not: Would you be interested in including our DE10 results in your repository, if we'd manage to get the architecture working?
We've also contacted the OpenMSP430 developers for including the Altera DE10 in their repository.
Apart from that, we would also like to know whether you have any older documentation which you used when you started creating the example project for the different boards, or if there might be anything that is not provided in the repository that we need.
