feat: use UART 0, as UART needs configured GPIO

simple-uart-transmit/esp32-c3-uart-interface.c

@@ -5,8 +5,8 @@ static void config_clock_freq_and_baud_rate(){
   //freq = clock source rate / (UART_SCLK_DIV_NUM+UART_SCLK_DIV_A/UART_SCLK_DIV_B)
   // baud rate = freq / (UART_CLKDIV + UART_CLKDIV_FRAG / 16)
 
-  uart_clk_conf_reg_t *clk_config = UART_CLK_CONF_REG(1);
-  uart_clkdiv_reg_t *clk_div = UART_CLKDIV_REG(1);
+  uart_clk_conf_reg_t *clk_config = UART_CLK_CONF_REG(0);
+  uart_clkdiv_reg_t *clk_div = UART_CLKDIV_REG(0);
 
   // select the clock source via UART_SCLK_SEL;  
   // 1 is ABP_CLK with 80 MHz
@@ -25,9 +25,9 @@ static void config_clock_freq_and_baud_rate(){
 }
 
 void config_uart(){
-  // wait for UART_REG(1)_UPDATE to become 0, which indicates the completion of the last synchronization;
-  uart_id_reg_t *id = UART_ID_REG(1);
-  uart_conf0_reg_t *conf0 = UART_CONF0_REG(1);
+  // wait for UART_REG(0)_UPDATE to become 0, which indicates the completion of the last synchronization;
+  uart_id_reg_t *id = UART_ID_REG(0);
+  uart_conf0_reg_t *conf0 = UART_CONF0_REG(0);
 
   while((bool)(id->reg_update)){
     __asm__("ADDI x0, x0, 0");
@@ -51,10 +51,10 @@ void config_uart(){
 }
 
 void enable_uart_transmitter(){
-  uart_conf1_reg_t *uart_conf1 = UART_CONF1_REG(1);
-  uart_fifo_reg_t *fifo = UART_FIFO_REG(1);
-  uart_int_clr_reg_t *int_clr = UART_INT_CLR_REG(1);
-  uart_int_ena_reg_t *int_ena = UART_INT_ENA_REG(1);
+  uart_conf1_reg_t *uart_conf1 = UART_CONF1_REG(0);
+  uart_fifo_reg_t *fifo = UART_FIFO_REG(0);
+  uart_int_clr_reg_t *int_clr = UART_INT_CLR_REG(0);
+  uart_int_ena_reg_t *int_ena = UART_INT_ENA_REG(0);
 
   // configure TX FIFO’s empty threshold via UART_TXFIFO_EMPTY_THRHD;
   uart_conf1->txfifo_empty_thrhd=4;
@@ -77,8 +77,8 @@ void enable_uart_transmitter(){
 void init_uart(){
   // from technical reference manual 543 f
 
-  uart_id_reg_t *id = UART_ID_REG(1);
-  uart_clk_conf_reg_t *clk_config = UART_CLK_CONF_REG(1);
+  uart_id_reg_t *id = UART_ID_REG(0);
+  uart_clk_conf_reg_t *clk_config = UART_CLK_CONF_REG(0);
   system_perip_clk_en0_reg_t *perip_clk_en0 = SYSTEM_PERIP_CLK_EN0_REG;
   system_perip_rst_en0_reg_t *perip_rst_en0 = SYSTEM_PERIP_RST_EN0_REG;
 
@@ -86,19 +86,19 @@ void init_uart(){
   perip_clk_en0->uart_mem_clk_en = 1;
 
   // enable APB_CLK for UARTn by setting SYSTEM_UARTn_CLK_EN to 1;
-  perip_clk_en0->uart1_clk_en = 1;
+  perip_clk_en0->uart_clk_en = 1;
 
   // clear SYSTEM_UARTn_RST;
-  perip_rst_en0->uart1_rst = 0;
+  perip_rst_en0->uart_rst = 0;
 
   // write 1 to UART_RST_CORE;
   clk_config->rst_core = 1;
 
   // write 1 to SYSTEM_UARTn_RST;
-  perip_rst_en0->uart1_rst = 1;
+  perip_rst_en0->uart_rst = 1;
 
   // clear SYSTEM_UARTn_RST;
-  perip_rst_en0->uart1_rst = 0;
+  perip_rst_en0->uart_rst = 0;
 
   // clear UART_RST_CORE;
   clk_config->rst_core = 0;