feat: add simple register read-write example

src/reading-writing-registers/Makefile

+SOURCES = main.c esp32-c3-register-interface.c
+
+include $(MDK)/$(ARCH)/build.mk

src/reading-writing-registers/esp32-c3-register-interface.c

+#include "esp32-c3-uart-interface.h"
+#include <stdint.h>
+
+void readSetClear(){
+  uint32_t core_value = *C3_UART_CLK_CONF_REG(0);
+  
+  // set UART_RST_CORE
+  core_value |= 1<<23;
+  *C3_UART_CLK_CONF_REG(0) = core_value;
+  
+  // clear UART_RST_CORE
+  core_value &= (uint32_t)~(1<<23);
+  *C3_UART_CLK_CONF_REG(0) = core_value;
+}
\ No newline at end of file

src/reading-writing-registers/esp32-c3-register-interface.h

+#ifndef ESP32_C3_REGISTER_INTERFACE_H
+#define ESP32_C3_REGISTER_INTERFACE_H
+
+#define C3_UART_CONTROLLER_0_BASE ((uint32_t)0x60000000)
+#define C3_UART_CONTROLLER_1_BASE ((uint32_t)0x60010000)
+#define C3_UART_CONTROLLER_SELECT(base_select) ((volatile uint32_t *)((base_select == 1) ? C3_UART_CONTROLLER_1_BASE : C3_UART_CONTROLLER_0_BASE))
+
+#define C3_UART_CLK_CONF_REG(base_select) ((volatile uint32_t *)(C3_UART_CONTROLLER_SELECT((base_select)) + 0x0078))
+// UART_RST_CORE is on 23
+// UART_SCLK_SEL is on 20 and 21 (2 bits), selcetion is between 1 and 3
+// UART_SCLK_DIV_NUM - The integral part of the frequency divisor - 12 to 19
+// UART_SCLK_DIV_A - The numerator of the frequency divisor - 6 to 11
+// UART_SCLK_DIV_B - The denominator of the frequency divisor - 0 to 5
+
+void readSetClear();
+
+#endif
\ No newline at end of file

src/reading-writing-registers/main.c

+// Copyright (c) Charles Lohr
+// All rights reserved
+
+#include <mdk.h>
+#include "esp32-c3-register-interface.h"
+
+int main(void) {
+  wdt_disable();
+
+  readSetClear();
+
+  return 0;
+}