notes_simulator.md

Some notes regarding the simulator sancus-sim

• sancus-sim is really the python script sancus-core/core/sim/rtl_sim/sancus/run_sim.py which calls iverilog internally
• The files sancus_sim.fst, sim-input.bin, sim-output.bin that usually remain in a project directory after running the simulator, are not used by the simulator (iverilog) itself, but from the program being simulated
  • sim-[input/ouput].bin are somehow used by the "File IO peripheral" (sancus-core/core/bench/verilog/tb_openMSP430.v line 651)
  • sancus_sim.fst is called dumpfile in the python script, usage: ???