// UART_SCLK_SEL is on 20 and 21 (2 bits), selcetion is between 1 and 3
uint32_tSCLK_DIV_A:6;
// UART_SCLK_DIV_NUM - The integral part of the frequency divisor - 12 to 19
uint32_tSCLK_DIV_NUM:8;
// UART_SCLK_DIV_A - The numerator of the frequency divisor - 6 to 11
uint32_tSCLK_SEL:2;
// UART_SCLK_DIV_B - The denominator of the frequency divisor - 0 to 5
uint32_tSCLK_EN:1;
uint32_tREST_CORE:1;
uint32_tTX_SCLK_EN:1;
uint32_tRX_SCLK_EN:1;
uint32_tTX_REST_CORE:1;
uint32_tRX_REST_CORE:1;
uint32_tRESERVED:4;
}esp32c3_uart_clk_conf_t;
#define UART_CLK_CONF_REG(base_select) ((esp32c3_uart_clk_conf_t *)(C3_UART_CONTROLLER_SELECT((base_select)) + 0x0078)) // Assuming the offset of clk_conf is 0x18 from the base address